57 changes: 57 additions & 0 deletions payloads/external/Memtest86Plus/Makefile.inc
@@ -0,0 +1,57 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##

TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
NAME-$(CONFIG_MEMTEST_MASTER)=Master
TAG-$(CONFIG_MEMTEST_STABLE)=485c4fd363fe8570b3da9f0cc5dacf20e1c40cbc
NAME-$(CONFIG_MEMTEST_STABLE)=Stable

project_name=Memtest86+
project_dir=$(CURDIR)/memtest86plus
project_git_repo=https://review.coreboot.org/memtest86plus.git

all: build

$(project_dir):
echo " Cloning $(project_name) from Git"
git clone $(project_git_repo) $(project_dir)

fetch: $(project_dir)
-cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \
if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
echo " Fetching new commits from the $(project_name) git repo"; \
git fetch; fi

checkout: fetch
echo " Checking out $(project_name) revision $(NAME-y) ($(TAG-y))"
cd $(project_dir); \
git checkout master; \
git branch -D coreboot 2>/dev/null; \
git checkout -b coreboot $(TAG-y)

build: checkout
echo " MAKE $(project_name) $(NAME-y)"
$(MAKE) -C $(project_dir) all

clean:
test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0

distclean:
rm -rf $(project_dir)

print-repo-info:
echo "$(project_git_repo) $(project_dir)"

.PHONY: all build checkout clean distclean fetch print-repo-info
4 changes: 2 additions & 2 deletions payloads/external/iPXE/Kconfig
Expand Up @@ -89,13 +89,13 @@ config PXE_ROM_ID

config PXE_CUSTOM_GENERAL_H
string "iPXE custom general.h file"
default "../../../../apu2-documentation/ipxe/general.h"
default "general.h"
help
This option allows user to customize feature set built-in into iPXE ROM.

config PXE_CUSTOM_BOOTMENU_FILE
string "iPXE custom menu.ipxe file"
default "../../../../apu2-documentation/ipxe/menu.ipxe"
default "menu.ipxe"
help
This option allows user to customize boot menu for iPXE ROM.

Expand Down
136 changes: 136 additions & 0 deletions payloads/external/iPXE/general.h
@@ -0,0 +1,136 @@
/*
* Network protocols
*
*/

#define NET_PROTO_IPV4 /* IPv4 protocol */
#define NET_PROTO_IPV6 /* IPv6 protocol */
#undef NET_PROTO_FCOE /* Fibre Channel over Ethernet protocol */
#define NET_PROTO_STP /* Spanning Tree protocol */

/*
* PXE support
*
*/
#define PXE_STACK /* PXE stack in iPXE - you want this! */
#define PXE_MENU /* PXE menu booting */

/*
* Download protocols
*
*/

#define DOWNLOAD_PROTO_TFTP /* Trivial File Transfer Protocol */
#define DOWNLOAD_PROTO_HTTP /* Hypertext Transfer Protocol */
#define DOWNLOAD_PROTO_HTTPS /* Secure Hypertext Transfer Protocol */
#define DOWNLOAD_PROTO_FTP /* File Transfer Protocol */
#define DOWNLOAD_PROTO_SLAM /* Scalable Local Area Multicast */
#define DOWNLOAD_PROTO_NFS /* Network File System Protocol */

/*
* SAN boot protocols
*
*/

#define SANBOOT_PROTO_ISCSI /* iSCSI protocol */
#define SANBOOT_PROTO_AOE /* AoE protocol */
#undef SANBOOT_PROTO_IB_SRP /* Infiniband SCSI RDMA protocol */
#undef SANBOOT_PROTO_FCP /* Fibre Channel protocol */
#define SANBOOT_PROTO_HTTP /* HTTP SAN protocol */

/*
* HTTP extensions
*
*/
#define HTTP_AUTH_BASIC /* Basic authentication */
#define HTTP_AUTH_DIGEST /* Digest authentication */
#define HTTP_ENC_PEERDIST /* PeerDist content encoding */

/*
* 802.11 cryptosystems and handshaking protocols
*
*/
#define CRYPTO_80211_WEP /* WEP encryption (deprecated and insecure!) */
#define CRYPTO_80211_WPA /* WPA Personal, authenticating with passphrase */
#define CRYPTO_80211_WPA2 /* Add support for stronger WPA cryptography */

/*
* Name resolution modules
*
*/

#define DNS_RESOLVER /* DNS resolver */
/*
* Image types
*
* Etherboot supports various image formats. Select whichever ones
* you want to use.
*
*/
#define IMAGE_NBI /* NBI image support */
#define IMAGE_ELF /* ELF image support */
#define IMAGE_MULTIBOOT /* MultiBoot image support */
#define IMAGE_PXE /* PXE image support */
#define IMAGE_SCRIPT /* iPXE script image support */
#define IMAGE_BZIMAGE /* Linux bzImage image support */
#define IMAGE_COMBOOT /* SYSLINUX COMBOOT image support */
#undef IMAGE_EFI /* EFI image support */
#define IMAGE_SDI /* SDI image support */
#define IMAGE_PNM /* PNM image support */
#define IMAGE_PNG /* PNG image support */

/*
* Command-line commands to include
*
*/
#define AUTOBOOT_CMD /* Automatic booting */
#define NVO_CMD /* Non-volatile option storage commands */
#define CONFIG_CMD /* Option configuration console */
#define IFMGMT_CMD /* Interface management commands */
#define IWMGMT_CMD /* Wireless interface management commands */
#define IBMGMT_CMD /* Infiniband management commands */
#define FCMGMT_CMD /* Fibre Channel management commands */
#define ROUTE_CMD /* Routing table management commands */
#define IMAGE_CMD /* Image management commands */
#define DHCP_CMD /* DHCP management commands */
#define SANBOOT_CMD /* SAN boot commands */
#define MENU_CMD /* Menu commands */
#define LOGIN_CMD /* Login command */
#define SYNC_CMD /* Sync command */
#define NSLOOKUP_CMD /* DNS resolving command */
#define TIME_CMD /* Time commands */
#define DIGEST_CMD /* Image crypto digest commands */
#define LOTEST_CMD /* Loopback testing commands */
#define VLAN_CMD /* VLAN commands */
#define PXE_CMD /* PXE commands */
#define REBOOT_CMD /* Reboot command */
#define POWEROFF_CMD /* Power off command */
#define IMAGE_TRUST_CMD /* Image trust management commands */
#define PCI_CMD /* PCI commands */
#define PARAM_CMD /* Form parameter commands */
#define NEIGHBOUR_CMD /* Neighbour management commands */
#define PING_CMD /* Ping command */
#define CONSOLE_CMD /* Console command */
#define IPSTAT_CMD /* IP statistics commands */
#define PROFSTAT_CMD /* Profiling commands */


/*
* ROM-specific options
*
*/
#undef NONPNP_HOOK_INT19 /* Hook INT19 on non-PnP BIOSes */
#define AUTOBOOT_ROM_FILTER /* Autoboot only devices matching our ROM */

/*
* Virtual network devices
*
*/
#define VNIC_IPOIB /* Infiniband IPoIB virtual NICs */
//#define VNIC_XSIGO /* Infiniband Xsigo virtual NICs */

/*
* Error message tables to include
*
*/
#define ERRMSG_80211 /* All 802.11 error descriptions (~3.3kb) */
17 changes: 17 additions & 0 deletions payloads/external/iPXE/menu.ipxe
@@ -0,0 +1,17 @@
#!ipxe
:MENU
menu
item --gap -- ---------------- iPXE boot menu ----------------
item shell ipxe shell
item boot autoboot
choose --default boot --timeout 3000 target && goto ${target}

:boot
autoboot net0
goto MENU

:shell
shell ||
goto MENU

autoboot net0
29 changes: 29 additions & 0 deletions src/Kconfig
Expand Up @@ -782,6 +782,35 @@ config SORTBOOTORDER

source "payloads/external/iPXE/Kconfig"

config MEMTEST
bool "Load Memtest86+ as a secondary payload"
default y
depends on ARCH_X86
help
Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.

choice
prompt "Memtest86+ version"
default MEMTEST_STABLE
depends on MEMTEST

config MEMTEST_STABLE
bool "Stable"
help
Stable Memtest86+ version.

For reproducible builds, this option must be selected.
config MEMTEST_MASTER
bool "Master"
help
Newest Memtest86+ version.

This option will fetch the newest version of the Memtest86+ code,
updating as new changes are committed. This makes the build
non-reproducible, as it can fetch different code each time.
endchoice

endmenu

menu "Debugging"
Expand Down
8 changes: 4 additions & 4 deletions src/arch/x86/Makefile.inc
Expand Up @@ -341,6 +341,9 @@ seabios:
CONFIG_ELTAN_SEABIOS_TAG=$(CONFIG_ELTAN_SEABIOS_TAG) \
OUT=$(abspath $(obj)) IASL="$(IASL)"

sortbootorder:
$(MAKE) -C payloads/external/sortbootorder -f Makefile.inc

filo:
$(MAKE) -C payloads/external/FILO -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
Expand All @@ -352,14 +355,11 @@ filo:
CONFIG_MENULST_TIMEOUT=$(CONFIG_MENULST_TIMEOUT) \
CONFIG_FILO_GENERIC=$(CONFIG_FILO_GENERIC) \
CONFIG_FILO_ELTAN=$(CONFIG_FILO_ELTAN) \
CONFIG_ELTAN_FILO_TAG=$(CONFIG_ELTAN_FILO_TAG)
CONFIG_ELTAN_FILO_TAG=$(CONFIG_ELTAN_FILO_TAG)

grub2:
$(MAKE) -C payloads/external/GRUB2 -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER)

sortbootorder:
$(MAKE) -C payloads/external/sortbootorder -f Makefile.inc
4 changes: 4 additions & 0 deletions src/cpu/amd/pi/00730F01/Makefile.inc
Expand Up @@ -17,8 +17,12 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#

romstage-y += update_microcode.c

ramstage-y += chip_name.c
ramstage-y += model_16_init.c
ramstage-y += update_microcode.c


subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
Expand Down
57 changes: 57 additions & 0 deletions src/cpu/amd/pi/00730F01/update_microcode.c
@@ -0,0 +1,57 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <cpu/amd/microcode.h>

struct id_mapping {
uint32_t orig_id;
uint16_t new_id;
};

static u16 get_equivalent_processor_rev_id(u32 orig_id) {
static const struct id_mapping id_mapping_table[] = {
/* Family 16h */

/* TODO This equivalent processor revisions ID needs verification */

{ 0x730f01, 0x7301 },

/* Array terminator */
{ 0xffffff, 0x0000 },
};

u32 new_id;
int i;

new_id = 0;

for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
if (id_mapping_table[i].orig_id == orig_id) {
new_id = id_mapping_table[i].new_id;
break;
}
}

return new_id;

}

void update_microcode(u32 cpu_deviceid)
{
u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
}
3 changes: 3 additions & 0 deletions src/cpu/amd/pi/Makefile.inc
Expand Up @@ -30,6 +30,9 @@ romstage-y += heapmanager.c
ramstage-y += heapmanager.c
ramstage-y += amd_late_init.c

romstage-y += microcode_fam16h.c
ramstage-y += microcode_fam16h.c

ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)

$(obj)/coreboot_s3nv.rom: $(obj)/config.h
Expand Down
146 changes: 146 additions & 0 deletions src/cpu/amd/pi/microcode_fam16h.c
@@ -0,0 +1,146 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Raptor Engineering
* Copyright (C) 2018 PC Engines GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs_core.h>
#include <arch/io.h>

#define UCODE_DEBUG(fmt, args...) \
do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while (0)

#define F16H_MPB_MAX_SIZE 3458
#define F16H_MPB_DATA_OFFSET 32

/*
* STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
* Microcode Patch Block
* Microcode Header
* Microcode "Blob"
* ...
* ...
* (end of file)
*
*
* MICROCODE HEADER (offset 0 bytes from start of file)
* Total size = 32 bytes
* [0:3] Date code (32 bits)
* [4:7] Patch level (32 bits)
* [8:9] Microcode patch data ID (16 bits)
* [10:15] Reserved (48 bits)
* [16:19] Chipset 1 device ID (32 bits)
* [20:23] Chipset 2 device ID (32 bits)
* [24:25] Processor Revisions ID (16 bits)
* [26] Chipset 1 revision ID (8 bits)
* [27] Chipset 2 revision ID (8 bits)
* [28:31] Reserved (32 bits)
*
* MICROCODE BLOB (offset += 32)
* Total size = m bytes
*
*/

struct microcode {
uint32_t date_code;
uint32_t patch_id;

uint16_t mc_patch_data_id;
uint8_t reserved1[6];

uint32_t chipset1_dev_id;
uint32_t chipset2_dev_id;

uint16_t processor_rev_id;

uint8_t chipset1_rev_id;
uint8_t chipset2_rev_id;

uint8_t reserved2[4];

uint8_t m_patch_data[F16H_MPB_MAX_SIZE-F16H_MPB_DATA_OFFSET];

};

static void apply_microcode_patch(const struct microcode *m)
{
uint32_t new_patch_id;
msr_t msr;

/* apply patch */
msr.hi = 0;
msr.lo = (uint32_t)m;

wrmsr(0xc0010020, msr);

UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);

/* patch authentication */
msr = rdmsr(0x8b);
new_patch_id = msr.lo;

UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id ,
(new_patch_id == m->patch_id) ? "success" : "fail");
}

static void amd_update_microcode(const void *ucode, size_t ucode_len,
uint32_t equivalent_processor_rev_id)
{
const struct microcode *m;
const uint8_t *c = ucode;

m = (struct microcode *)c;

if (m->processor_rev_id == equivalent_processor_rev_id) {
apply_microcode_patch(m);
}
}

static const char *microcode_cbfs_file[] = {
"cpu_microcode_blob.bin"
};

void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
{
const void *ucode;
size_t ucode_len;

uint32_t i;

for (i = 0; i < ARRAY_SIZE(microcode_cbfs_file); i++)
{
if (equivalent_processor_rev_id == 0) {
UCODE_DEBUG("rev id not found. Skipping microcode patch!\n");
return;
}

ucode = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, microcode_cbfs_file[i],
CBFS_TYPE_MICROCODE, &ucode_len);
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
return;
}

if(ucode_len > F16H_MPB_MAX_SIZE) {
UCODE_DEBUG("microcode file invalid. Skipping updates.\n");
}

amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
}
}
6 changes: 0 additions & 6 deletions src/mainboard/pcengines/Kconfig
Expand Up @@ -20,12 +20,6 @@ endchoice

source "src/mainboard/pcengines/apu2/Kconfig"

source "src/mainboard/pcengines/apu3/Kconfig"

source "src/mainboard/pcengines/apu4/Kconfig"

source "src/mainboard/pcengines/apu5/Kconfig"

config MAINBOARD_VENDOR
string
default "PC Engines"
Expand Down
19 changes: 17 additions & 2 deletions src/mainboard/pcengines/apu2/Kconfig
Expand Up @@ -18,7 +18,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#

if BOARD_PCENGINES_APU2
if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU5

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
Expand All @@ -41,13 +41,28 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SPI_FLASH
select SPI_FLASH_WINBOND

config VARIANT_DIR
string
default apu2 if BOARD_PCENGINES_APU2
default apu3 if BOARD_PCENGINES_APU3
default apu4 if BOARD_PCENGINES_APU4
default apu5 if BOARD_PCENGINES_APU5

config DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"


config MAINBOARD_DIR
string
default pcengines/apu2

config MAINBOARD_PART_NUMBER
string
default "apu2"
default "apu2" if BOARD_PCENGINES_APU2
default "apu3" if BOARD_PCENGINES_APU3
default "apu4" if BOARD_PCENGINES_APU4
default "apu5" if BOARD_PCENGINES_APU5

config SVI2_SLOW_SPEED
bool "SVI2 slow speed"
Expand Down
54 changes: 32 additions & 22 deletions src/mainboard/pcengines/apu2/Makefile.inc
Expand Up @@ -27,13 +27,7 @@ ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ramstage-y += bios_knobs.c

# WIV20150202 add ramtest
cbfs-files-y += img/memtest
img/memtest-file := payloads/eltan/memtest86+/memtest501.serial.com1.nospd.eltan-elf
img/memtest-position := 0xcd900
img/memtest-type := payload
# WIV20150202 add ramtest
ramstage-y += s1_button.c

cbfs-files-y += bootorder_map
bootorder_map-file := bootorder_map
Expand Down Expand Up @@ -91,6 +85,25 @@ spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
# WIV20141001 END ADD SPD FROM FILE

# memtest86+

ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
MEMTEST_SERIAL_OPTIONS=SERIAL_CONSOLE_DEFAULT=1 \
SERIAL_TTY=$(CONFIG_UART_FOR_CONSOLE) \
SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD)
endif

memtest: $(DOTCONFIG)
$(MAKE) -C payloads/external/Memtest86Plus -f Makefile.inc all \
CC="$(CC_x86_32)" \
LD="$(LD_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" \
AS="$(AS_x86_32)" \
CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
$(MEMTEST_SERIAL_OPTIONS) \
MFLAGS= MAKEFLAGS=

# iPXE

ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
Expand All @@ -110,19 +123,16 @@ ifeq ($(CONFIG_BUILD_IPXE),y)
PXE_ROM_FILE:=payloads/external/iPXE/ipxe/ipxe.rom
endif

cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += genroms/pxe.rom
genroms/pxe.rom-file := $(PXE_ROM_FILE)
genroms/pxe.rom-type := raw

payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG)
ipxe: $(DOTCONFIG)
$(MAKE) -C payloads/external/iPXE -f Makefile.inc all \
CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \
PXE_ROM_PCI_ID=$(subst $(comma),,$(CONFIG_PXE_ROM_ID)) \
CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \
CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \
CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \
IPXE_UART=$(IPXE_UART) \
CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \
CONFIG_PXE_CUSTOM_GENERAL_H=$(CONFIG_PXE_CUSTOM_GENERAL_H) \
CONFIG_PXE_CUSTOM_BOOTMENU_FILE=$(CONFIG_PXE_CUSTOM_BOOTMENU_FILE)

CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \
PXE_ROM_PCI_ID=$(subst $(comma),,$(CONFIG_PXE_ROM_ID)) \
CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \
CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \
CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \
IPXE_UART=$(IPXE_UART) \
CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \
CONFIG_PXE_CUSTOM_GENERAL_H=$(CONFIG_PXE_CUSTOM_GENERAL_H) \
CONFIG_PXE_CUSTOM_BOOTMENU_FILE=$(CONFIG_PXE_CUSTOM_BOOTMENU_FILE)

subdirs-y += variants/$(VARIANT_DIR)
38 changes: 16 additions & 22 deletions src/mainboard/pcengines/apu2/apu2.h
Expand Up @@ -20,10 +20,10 @@

#include <agesawrapper.h>

#define APU2_SPD_STRAP0_GPIO 0x40 // GPIO49
#define APU2_SPD_STRAP0_FUNC Function2
#define APU2_SPD_STRAP1_GPIO 0x41 // GPIO50
#define APU2_SPD_STRAP1_FUNC Function2
#define APU2_SPD_STRAP0_GPIO 0x40 // GPIO49
#define APU2_SPD_STRAP0_FUNC Function2
#define APU2_SPD_STRAP1_GPIO 0x41 // GPIO50
#define APU2_SPD_STRAP1_FUNC Function2
#define APU2_PE3_RST_L_GPIO 0x42 // GPIO51
#define APU2_PE3_RST_L_FUNC Function2
#define APU2_PE4_RST_L_GPIO 0x43 // DEVSLP[0]/GPIO59
Expand All @@ -34,25 +34,19 @@
#define APU2_LED2_L_FUNC Function1
#define APU2_LED3_L_GPIO 0x46 // DEVSLP[1]/GPIO59
#define APU2_LED3_L_FUNC Function3
#define APU2_PE3_WDIS_L_GPIO 0x47 // GPIO64
#define APU2_PE3_WDIS_L_FUNC Function2
#define APU2_PE4_WDIS_L_GPIO 0x48 // GPIO68
#define APU2_PE4_WDIS_L_FUNC Function0
#define APU2_PE3_WDIS_L_GPIO 0x47 // GPIO64
#define APU2_PE3_WDIS_L_FUNC Function2
#define APU2_PE4_WDIS_L_GPIO 0x48 // GPIO68
#define APU2_PE4_WDIS_L_FUNC Function0
#define APU2_SKR_GPIO 0x5B // SPKR/GPIO66
#define APU2_SKR_FUNC Function0
#define APU2_PROCHOT_GPIO 0x4D // GPIO71
#define APU2_PROCHOT_FUNC Function0
#define APU2_BIOS_CONSOLE_GPIO 0x59 // GENINT1_L/GPIO32
#define APU2_BIOS_CONSOLE_FUNC Function0












#define APU2_BIOS_CONSOLE_GPIO 0x59 // GENINT1_L/GPIO32
#define APU2_BIOS_CONSOLE_FUNC Function0
#define APU3_SIMSWAP_GPIO 0x5A // GENINT2_L/GPIO33
#define APU3_SIMSWAP_FUNC Function0
#define APU5_SIMSWAP2_GPIO 0x59 // GENINT1_L/GPIO32
#define APU5_SIMSWAP2_FUNC Function0
#define APU5_SIMSWAP3_GPIO 0x5A // GENINT2_L/GPIO33
#define APU5_SIMSWAP3_FUNC Function0
8 changes: 4 additions & 4 deletions src/mainboard/pcengines/apu2/board_info.txt
@@ -1,6 +1,6 @@
Board name: PC Engines APU2
Board URL:
Category: customer
Board name: apu2 apu3 apu4 apu5
Board URL: http://www.pcengines.ch/apu2c2.htm
Category: half
ROM protocol: SPI
ROM socketed: n
Flashrom support: n
Flashrom support: y
Binary file modified src/mainboard/pcengines/apu2/bootorder
Binary file not shown.
3 changes: 1 addition & 2 deletions src/mainboard/pcengines/apu2/bootorder_def
Expand Up @@ -10,9 +10,8 @@
/rom@genroms/pxe.rom
pxen0
scon1
sgaen1
usben1
uartc1
uartd1
ehcien0
ehcien1
mpcie2_clk0
151 changes: 27 additions & 124 deletions src/mainboard/pcengines/apu2/mainboard.c
Expand Up @@ -50,37 +50,7 @@
#include <cpuRegisters.h>
#include <build.h>
#include "bios_knobs.h"
#include <spi-generic.h>
#include <spi_flash.h>
#include <cbfs_core.h>

static int find_knob_index(const char *s, const char *pattern)
{

int pattern_index = 0;
char *result = (char *) s;
char *lpattern = (char *) pattern;

while (*result && *pattern ) {
if ( *lpattern == 0) // the pattern matches return the pointer
return pattern_index;
if ( *result == 0) // We're at the end of the file content but don't have a patter match yet
return -1;
if (*result == *lpattern ) {
// The string matches, simply advance
result++;
pattern_index++;
lpattern++;
} else {
// The string doesn't match restart the pattern
result++;
pattern_index++;
lpattern = (char *) pattern;
}
}

return -1;
}
#include "s1_button.h"

/**********************************************
* enable the dedicated function in mainboard.
Expand Down Expand Up @@ -202,8 +172,7 @@ static void mainboard_final(void *chip_info) {
printk(BIOS_INFO, "USB PORT ROUTING = EHCI PORTS ENABLED\n");
}



#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
bool console_enabled = check_console( ); // Get console setting from bootorder file.

if ( !console_enabled ) {
Expand All @@ -215,85 +184,10 @@ static void mainboard_final(void *chip_info) {

printk(BIOS_INFO, "S1 PRESSED\n");

const struct spi_flash *flash;
const char *file_name = "bootorder";
size_t boot_file_len = 0;
size_t offset;
struct cbfs_file *bootorder_cbfs_file = NULL;
char* bootorder_copy;
int knob_index;

char *boot_file = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, file_name, CBFS_TYPE_RAW, &boot_file_len);

if (boot_file == NULL) {
printk(BIOS_EMERG, "file [%s] not found in CBFS\n", file_name);
return;
}

if (boot_file_len < 4096) {
printk(BIOS_EMERG, "Missing bootorder data.\n");
return;
}

boot_file_len--; // cbfs_get_file_content returns size+1

offset = cbfs_locate_file(CBFS_DEFAULT_MEDIA, bootorder_cbfs_file, file_name);

if(offset ==-1) {
printk(BIOS_WARNING,"Failed to retrieve bootorder file offset\n");
return;
}

bootorder_copy = (char *) malloc(boot_file_len);

if(bootorder_copy == NULL) {
printk(BIOS_WARNING,"Failed to allocate memory for bootorder\n");
return;
}

if(memcpy(bootorder_copy, boot_file, boot_file_len) == NULL) {
printk(BIOS_WARNING,"Copying bootorder failed\n");
free(bootorder_copy);
return;
}

knob_index = find_knob_index(bootorder_copy, "scon");

if(knob_index == -1){
printk(BIOS_WARNING,"scon knob not found in bootorder\n");
free(bootorder_copy);
return;
}

*(bootorder_copy + knob_index) = '1';

spi_init();

flash = spi_flash_probe(0, 0);

if (flash == NULL) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
}

if (spi_flash_erase(flash, (u32) offset, boot_file_len)) {
printk(BIOS_WARNING, "SPI erase failed\n");
free(bootorder_copy);
return;
}

if (spi_flash_write(flash, (u32) offset, boot_file_len, bootorder_copy)) {
printk(BIOS_WARNING, "SPI write failed\n");
free(bootorder_copy);
return;
} else {
printk(BIOS_INFO, "Bootorder write successed\n");
}

free(bootorder_copy);
enable_console();
}
}
#endif // CONFIG_BOARD_PCENGINES_APU2/3/4
}

struct chip_operations mainboard_ops = {
Expand All @@ -304,28 +198,37 @@ struct chip_operations mainboard_ops = {
const char *smbios_mainboard_serial_number(void)
{
static char serial[10];
device_t nic_dev;
uintptr_t bar10;
msr_t msr;
u32 mac_addr = 0;
int i;
device_t nic_dev;

// Allows the IO configuration space access method, IOCF8 and IOCFC, to be
// used to generate extended configuration cycles
msr = rdmsr(NB_CFG_MSR);
msr.hi |= (ENABLE_CF8_EXT_CFG);
wrmsr(NB_CFG_MSR, msr);

nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0));

if ((serial[0] != 0) || !nic_dev)
return serial;

/* Read in the last 3 bytes of NIC's MAC address. */
bar10 = pci_read_config32(nic_dev, 0x10);
bar10 &= 0xFFFE0000;
bar10 += 0x5400;
for (i = 3; i < 6; i++) {
mac_addr <<= 8;
mac_addr |= read8((u8 *)bar10 + i);
}
mac_addr &= 0x00FFFFFF;
return serial;

// Read 4 bytes starting from 0x144 offset
mac_addr = pci_read_config32(nic_dev, 0x144);
// MSB here is always 0xff
// Discard it so only bottom 3b of mac address are left
mac_addr &= 0x00ffffff;

// Set bit EnableCf8ExtCfg back to 0
msr.hi &= ~(ENABLE_CF8_EXT_CFG);
wrmsr(NB_CFG_MSR, msr);

// Calculate serial value
mac_addr /= 4;
mac_addr -= 64;

snprintf(serial, sizeof(serial), "%d", mac_addr);

return serial;
}

Expand Down
26 changes: 20 additions & 6 deletions src/mainboard/pcengines/apu2/romstage.c
Expand Up @@ -34,6 +34,7 @@
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <cpu/amd/microcode.h>
#include <hudson.h>
#include <cpu/amd/pi/s3_resume.h>
#include <fchgpio.h>
Expand All @@ -52,14 +53,23 @@ static const GPIO_CONTROL gGpioInitTable[] = {
GPIO_DEFINITION (APU2_SPD_STRAP1_GPIO, APU2_SPD_STRAP1_FUNC, 0, 0, 0, 0),
GPIO_DEFINITION (APU2_PE3_RST_L_GPIO, APU2_PE3_RST_L_FUNC, 1, 1, 0, 0),
GPIO_DEFINITION (APU2_PE4_RST_L_GPIO, APU2_PE4_RST_L_FUNC, 1, 1, 0, 0),
GPIO_DEFINITION (APU2_LED1_L_GPIO, APU2_LED1_L_FUNC, 1, 0, 0, 0), // Turn on the LEDs by default
GPIO_DEFINITION (APU2_LED2_L_GPIO, APU2_LED2_L_FUNC, 1, 0, 0, 0),
GPIO_DEFINITION (APU2_LED3_L_GPIO, APU2_LED3_L_FUNC, 1, 0, 0, 0),
GPIO_DEFINITION (APU2_LED1_L_GPIO, APU2_LED1_L_FUNC, 1, 0, 0, 0), // Turn on the LEDs by default
GPIO_DEFINITION (APU2_LED2_L_GPIO, APU2_LED2_L_FUNC, 1, 0, 0, 0),
GPIO_DEFINITION (APU2_LED3_L_GPIO, APU2_LED3_L_FUNC, 1, 0, 0, 0),
GPIO_DEFINITION (APU2_PE3_WDIS_L_GPIO, APU2_PE3_WDIS_L_FUNC, 1, 1, 0, 0),
GPIO_DEFINITION (APU2_PE4_WDIS_L_GPIO, APU2_PE4_WDIS_L_FUNC, 1, 1, 0, 0),
// SPKR doesn't require init, left at default
GPIO_DEFINITION (APU2_PROCHOT_GPIO, APU2_PROCHOT_FUNC, 0, 0, 0, 0),
GPIO_DEFINITION (APU2_BIOS_CONSOLE_GPIO, APU2_BIOS_CONSOLE_FUNC, 0, 0, 0, 0),
GPIO_DEFINITION (APU2_PROCHOT_GPIO, APU2_PROCHOT_FUNC, 0, 0, 0, 0),
#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
GPIO_DEFINITION (APU2_BIOS_CONSOLE_GPIO, APU2_BIOS_CONSOLE_FUNC, 0, 0, 0, 0),
#endif
#if CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
GPIO_DEFINITION (APU3_SIMSWAP_GPIO, APU3_SIMSWAP_FUNC, 1, 0, 0, 0),
#endif
#if CONFIG_BOARD_PCENGINES_APU5
GPIO_DEFINITION (APU5_SIMSWAP2_GPIO, APU5_SIMSWAP2_FUNC, 1, 1, 0, 0),
GPIO_DEFINITION (APU5_SIMSWAP3_GPIO, APU5_SIMSWAP3_FUNC, 1, 1, 0, 0),
#endif
{0xFF, 0xFF, 0xFF} // Terminator
};

Expand Down Expand Up @@ -121,7 +131,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
data &= 0xFFFF0000;
data |= (0 + 1) << (0 * 4); // CLKREQ 0 to CLK0
data |= (1 + 1) << (1 * 4); // CLKREQ 1 to CLK1
data |= (2 + 1) << (2 * 4); // CLKREQ 2 to CLK2
#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
data |= (2 + 1) << (2 * 4); // CLKREQ 2 to CLK2 disabled on APU5
#endif
// make CLK3 to ignore CLKREQ# input
// force it to be always on
data |= ( 0xf ) << (3 * 4); // CLKREQ 3 to CLK3
Expand Down Expand Up @@ -168,6 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);

update_microcode(val);

/*
* This refers to LpcClkDrvSth settling time. Without this setting, processor
* initialization is slow or incorrect, so this wait has been replicated from
Expand Down
157 changes: 157 additions & 0 deletions src/mainboard/pcengines/apu2/s1_button.c
@@ -0,0 +1,157 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#include <spi-generic.h>
#include <spi_flash.h>
#include <cbfs_core.h>
#include <console/console.h>
#include <string.h>
#include <stdlib.h>
#include "s1_button.h"

static int find_knob_index(const char *s, const char *pattern)
{

int pattern_index = 0;
char *result = (char *) s;
char *lpattern = (char *) pattern;

while (*result && *pattern ) {
if ( *lpattern == 0) // the pattern matches return the pointer
return pattern_index;
if ( *result == 0) // We're at the end of the file content but don't have a patter match yet
return -1;
if (*result == *lpattern ) {
// The string matches, simply advance
result++;
pattern_index++;
lpattern++;
} else {
// The string doesn't match restart the pattern
result++;
pattern_index++;
lpattern = (char *) pattern;
}
}

return -1;
}

static char* locate_and_map_bootorder(size_t *offset, size_t *length)
{
const char *file_name = "bootorder";
size_t boot_file_len = 0;
size_t file_offset;
struct cbfs_file *bootorder_cbfs_file = NULL;
char* bootorder_copy;

char *boot_file = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, file_name, CBFS_TYPE_RAW, &boot_file_len);

if (boot_file == NULL) {
printk(BIOS_WARNING, "file [%s] not found in CBFS\n", file_name);
return NULL;
}

if (boot_file_len < 4096) {
printk(BIOS_WARNING, "Missing bootorder data.\n");
return NULL;
}

if(boot_file_len & 0xFFF) {
printk(BIOS_WARNING,"Bootorder file not multiple size of 4k\n");
return NULL;
}


file_offset = cbfs_locate_file(CBFS_DEFAULT_MEDIA, bootorder_cbfs_file, file_name);

if(file_offset == -1) {
printk(BIOS_WARNING,"Failed to retrieve bootorder file offset\n");
return NULL;
}

bootorder_copy = (char *) malloc(boot_file_len);

if(bootorder_copy == NULL) {
printk(BIOS_WARNING,"Failed to allocate memory for bootorder\n");
return NULL;
}

if(memcpy(bootorder_copy, boot_file, boot_file_len) == NULL) {
printk(BIOS_WARNING,"Copying bootorder failed\n");
return NULL;
}

*offset = file_offset;
*length = boot_file_len;

return bootorder_copy;
}

static int flash_bootorder(size_t offset, size_t length, char *buffer)
{
const struct spi_flash *flash;

spi_init();

flash = spi_flash_probe(0, 0);

if (flash == NULL) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return -1;
}

if (spi_flash_erase(flash, (u32) offset, length)) {
printk(BIOS_WARNING, "SPI erase failed\n");
return -1;
}

if (spi_flash_write(flash, (u32) offset, length, buffer)) {
printk(BIOS_WARNING, "SPI write failed\n");
return -1;
}

return 0;
}

void enable_console(void)
{
char *bootorder_file;
size_t bootorder_length;
size_t bootorder_offset;
int knob_index;

bootorder_file = locate_and_map_bootorder(&bootorder_offset, &bootorder_length);

knob_index = find_knob_index(bootorder_file, "scon");

if(knob_index == -1){
printk(BIOS_WARNING,"scon knob not found in bootorder\n");
return;
}

*(bootorder_file + knob_index) = '1';

if(flash_bootorder(bootorder_offset, bootorder_length, bootorder_file)) {
printk(BIOS_WARNING, "Failed to flash bootorder\n");
} else {
printk(BIOS_INFO, "Bootorder write successed\n");
}
}
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 3mdeb
* Copyright (C) 2018 PC Engines GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -18,21 +17,4 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#ifndef _BIOS_KNOBS_H
#define _BIOS_KNOBS_H

bool check_console(void);
bool check_uartc(void);
bool check_uartd(void);
bool check_ehci0(void);
bool check_mpcie2_clk(void);

#endif








void enable_console(void);
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168 changes: 0 additions & 168 deletions src/mainboard/pcengines/apu3/BiosCallOuts.c

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