52 changes: 52 additions & 0 deletions Documentation/mainboard/emulation/qemu-power9.md
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@@ -0,0 +1,52 @@
# QEMU PPC64 emulator
This page describes how to build and run coreboot for QEMU/PPC64.

## Building coreboot
```bash
make defconfig KBUILD_DEFCONFIG=configs/config.emulation_qemu_power9
make
```

This builds coreboot with no payload.

## Payloads
You can configure ELF or `skiboot` payload via `make menuconfig`. In either case
you might need to adjust "ROM chip size" and make it large enough to accommodate
the payload (see how much space it needs in the error you get if it doesn't
fit).

## Running coreboot in QEMU
```bash
qemu-system-ppc64 -M powernv,hb-mode=on \
-cpu power9 \
-bios build/coreboot.rom \
-drive file=build/coreboot.rom,if=mtd \
-serial stdio \
-display none
```

- The default CPU in QEMU for AArch64 is a 604. You specify a suitable
PowerPC CPU via `-cpu power9`.
- By default Hostboot mode is off and needs to be turned on to run coreboot
as a firmware rather than like an OS.
- `-bios` specifies initial program (bootloader should suffice, but whole image
works fine too).
- `-drive` specifies image for emulated flash device.

## Running with a kernel
Loading `skiboot` (built automatically by coreboot or otherwise) allows
specifying kernel and root file system to be run.

```bash
qemu-system-ppc64 -M powernv,hb-mode=on \
-cpu power9 \
-bios build/coreboot.rom \
-drive file=build/coreboot.rom,if=mtd \
-serial stdio \
-display none \
-kernel zImage \
-initrd initrd.cpio.xz
```

- Specify path to your kernel via `-kernel`.
- Specify path to your rootfs via `-initrd`.
4 changes: 2 additions & 2 deletions Documentation/mainboard/ti/beaglebone-black.md
View file
Expand Up @@ -127,5 +127,5 @@ ROM.
hang on a bad SD card or when the SD card is removed during boot.


[Beaglebone Black]: https://beagleboard.org/black [U-Boot Falcon mode]:
https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon
[Beaglebone Black]: https://beagleboard.org/black
[U-Boot Falcon mode]: https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon
347 changes: 330 additions & 17 deletions Documentation/releases/coreboot-4.16-relnotes.md
View file
@@ -1,27 +1,340 @@
Upcoming release - coreboot 4.16
================================
coreboot 4.16
========================================================================

The 4.16 release is planned for February, 2022.
The 4.16 release was done on February 25th, 2022.

We are increasing the frequency of releases in order to enable others to release quarterly on
a fresher version of coreboot.
Since 4.15 there have been more than 1770 new commits by more than 170
developers. Of these, more than 35 contributed to coreboot for the
first time.

Update this document with changes that should be in the release notes.
Welcome to the project!

* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
Thank you to all the developers who continue to make coreboot the
great open source firmware project that it is.

Significant changes
New mainboards:
---------------
* Acer Aspire VN7-572G
* AMD Chausie
* ASROCK H77 Pro4-M
* ASUS P8Z77-M
* Emulation QEMU power9
* Google Agah
* Google Anahera4ES
* Google Banshee
* Google Beadrix
* Google Brya4ES
* Google Crota
* Google Dojo
* Google Gimble4ES
* Google Herobrine_Rev0
* Google Kingler
* Google Kinox
* Google Krabby
* Google Moli
* Google Nereid
* Google Nivviks
* Google Primus4ES
* Google Redrix4ES
* Google Skyrim
* Google Taeko4ES
* Google Taniks
* Google Vell
* Google Volmar
* Intel Alderlake-N RVP
* Prodrive Atlas
* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
* System76 gaze16 3050
* System76 gaze16 3060
* System76 gaze16 3060-b

Removed mainboards:
-------------------
* Google -> Corsola
* Google -> Nasher
* Google -> Stryke

Added processors:
-----------------
* src/cpu/power9
* src/soc/amd/sabrina

Submodule Updates
-----------------
* /3rdparty/amd_blobs (6 commits)
* /3rdparty/arm-trusted-firmware (965 commits)
* /3rdparty/blobs (30 commits)
* /3rdparty/chromeec (2212 commits)
* /3rdparty/intel-microcode (1 commits)
* /3rdparty/qc_blobs (13 commits)
* /3rdparty/vboot (44 commits)

Plans to move platform support to a branch:
-------------------------------------------
After the 4.18 release in November 2022, we plan to move support for any
boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was
introduced more than a year ago and with minor changes most platforms
were able to work just fine with it. A major difference is that V3 uses
just one continuous region below 4G to allocate all PCI memory BAR's. V4
uses all available space below 4G and if asked to, also above 4G too.
This makes it important that SoC code properly reports all fixed
resources.

Currently only AGESA platforms have issues with it. On Gerrit both
attempts to fix AMD AGESA codebases to use V4 and compatibility modes
inside the V4 allocator have been proposed, but both efforts seem
stalled. See the (not yet merged) documentation
[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
details. It looks like properly reporting all fixed resources is the
issue.

At this point, we are not specifying which platforms this will include
as there are a number of patches to fix these issues in flight.
Hopefully, all platforms will end up being migrated to the v4 resource
allocator so that none of the platforms need to be supported on the
branch.

Additionally, even if the support for the platform is moved to a branch,
it can be brought back to ToT if they're fixed to support the v4
allocator.

Plans for Code Deprecation
--------------------------
As of release 4.18 (November 2022) we plan to deprecate LEGACY_SMP_INIT.
This also includes the codepath for SMM_ASEG. This code is used to start
APs and do some feature programming on each AP, but also set up SMM.
This has largely been superseded by PARALLEL_MP, which should be able to
cover all use cases of LEGACY_SMP_INIT, with little code changes. The
reason for deprecation is that having 2 codepaths to do the virtually
the same increases maintenance burden on the community a lot, while also
being rather confusing.

### Add significant changes here
A few things are lacking in PARALLEL_MP init:
- Support for !CONFIG_SMP on single core systems. It's likely easy to
extend PARALLEL_MP or write some code that just does CPU detection on
the BSP CPU.
- Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC
showed that it's not that hard to do with PARALLEL_MP
https://review.coreboot.org/c/coreboot/+/58700

No platforms in the tree have any hardware limitations that would block
migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.

Significant changes
-------------------
This is, of course, not a complete list of all changes in the 4.16
coreboot release, but a sampling of some of the more interesting and
significant changes.

### Option to disable Intel Management Engine
Disable the Intel (Converged Security) Management Engine ((CS)ME) via HECI based
on Intel Core processors from Skylake to Alder Lake. State is set based on a
CMOS value of `me_state`. A value of `0` will result in a (CS)ME state of `0`
(working) and value of `1` will result in a (CS)ME state of `3` (disabled). For
an example CMOS layout and more info, see
Disable the Intel (Converged Security) Management Engine ((CS)ME) via
HECI based on Intel Core processors from Skylake to Alder Lake. State is
set based on a CMOS value of `me_state`. A value of `0` will result in a
(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
state of `3` (disabled). For an example CMOS layout and more info, see
[cse.c](../../src/soc/intel/common/block/cse/cse.c).


### Add [AMD] apcb_v3_edit tool
apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
up to 16 SPDs into an existing APCB. The APCB must have a magic number
at the top of each SPD slot.


### Allow enable/disable ME via CMOS
Add .enable method that will set the CSME state. The state is based on
the new CMOS option me_state, with values of 0 and 1. The method is very
stable when switching between different firmware platforms.

This method should not be used in combination with USE_ME_CLEANER.

State 1 will result in:
ME: Current Working State : 4
ME: Current Operation State : 1
ME: Current Operation Mode : 3
ME: Error Code : 2

State 0 will result in:
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 0


### Move LAPIC configuration to MP init
Implementation for setup_lapic() did two things -- call enable_lapic()
and virtual_wire_mode_init().

In PARALLEL_MP case enable_lapic() was redundant as it was already
executed prior to initialize_cpu() call. For the !PARALLEL_MP case
enable_lapic() is added to AP CPUs.


### Add ANSI escape sequences for highlighting
Add ANSI escape sequences to highlight a log line based on its loglevel
to the output of "interactive" consoles that are meant to be displayed
on a terminal (e.g. UART). This should help make errors and warnings
stand out better among the usual spew of debug messages. For users whose
terminal or use case doesn't support these sequences for some reason (or
who simply don't like them), they can be disabled with a Kconfig.

While ANSI escape sequences can be used to add color, minicom (the
presumably most common terminal emulator for UART endpoints?) doesn't
support color output unless explicitly enabled (via -c command line
flag), and other terminal emulators may have similar restrictions, so in
an effort to make this as widely useful by default as possible I have
chosen not to use color codes and implement this highlighting via
bolding, underlining and inverting alone (which seem to go through in
all cases). If desired, support for separate color highlighting could be
added via Kconfig later.


### Add cbmem_dump_console
This function is similar to cbmem_dump_console_to_uart except it uses
the normally configured consoles. A console_paused flag was added to
prevent the cbmem console from writing to itself.


### Add coreboot-configurator
A simple GUI to change CMOS settings in coreboot's CBFS, via the
nvramtool utility. Testing on Debian, Ubuntu and Manjaro with coreboot
4.14+, but should work with any distribution or coreboot release that
has an option table. For more info, please check the
[README](https://web.archive.org/web/20220225194308/https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/coreboot-configurator/README.md).


### Update live ISO configs to NixOS 21.11
Update configs so that they work with NixOS 21.11. Drop `iasl` package
since it was replaced with `acpica-tools`.


### Move to U-Boot v2021.10
Move to building the latest U-Boot.


### Support systems with >128 cores
Each time the spinlock is acquired a byte is decreased and then the
sign of the byte is checked. If there are more than 128 cores the sign
check will overflow. An easy fix is to increase the word size of the
spinlock acquiring and releasing.


### Add [samsung] sx9360 [proximity sensor] driver
Add driver for setting up Semtech sx9360 SAR sensor.
The driver is based on sx9310.c. The core of the driver is the same, but
the bindings are slightly different.

Registers are documented [in the kernel tree:](https://web.archive.org/web/20220225182803/https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/)
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml


### Add driver for Genesys Logic [SD Controller] GL9750
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.

The patch disables ASPM L0s.


### Add support for Realtek RT8125
The Realtek RT8168 and RT8125 have a similar programming interface,
therefore add the PCI device ID for the RT8125 into driver for support.


### Add Fibocom 5G WWAN ACPI support
Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
PXSX._RST is invoked on driver removal.

build dependency:
soc/intel/common/block/pcie/rtd3

This driver will use the rtd3 methods for the same parent in the device
tree. The rtd3 chip needs to be added on the same root port in the
devicetree separately.


### Fix bug in vr_config
The `cpu_get_power_max()` function returns the TDP in milliwatts, but
the vr_config code interprets the value in watts. Divide the value by
1000 to fix this.

This also fixes an integer overflow when `cpu_get_power_max()` returns
a value greater than 65535 (UINT16_MAX).


### Make mixed topology work
When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.


### Add FSP 2.3 support
FSP 2.3 specification introduces following changes:

1. FSP_INFO_HEADER changes
Updated SpecVersion from 0x22 to 0x23
Updated HeaderRevision from 5 to 6
Added ExtendedImageRevision
FSP_INFO_HEADER length changed to 0x50

2. Added FSP_NON_VOLATILE_STORAGE_HOB2

Following changes are implemented in the patch to support FSP 2.3:

- Add Kconfig option
- Update FSP build binary version info based on ExtendedImageRevision
field in header
- New NV HOB related changes will be pushed as part of another patch


### Join hash calculation for verification and measurement
This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
is enabled from the lookup step into the code where a file is actually
loaded or mapped from flash. This has the advantage that CBFS routines
which just look up a file to inspect its metadata (e.g. cbfs_get_size())
do not cause the file to be measured twice. It also removes the existing
inefficiency that files are loaded twice when measurement is enabled
(once to measure and then again when they are used). When CBFS
verification is enabled and uses the same hash algorithm as the TPM, we
are even able to only hash the file a single time and use the result for
both purposes.


### Skip FSP Notify APIs
Alder Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.

Additionally, created a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.

TODO: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.


### Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.

When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.

This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.
19 changes: 19 additions & 0 deletions Documentation/releases/coreboot-4.17-relnotes.md
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@@ -0,0 +1,19 @@
Upcoming release - coreboot 4.17
================================

The 4.17 release is planned for May, 2022.

We are continuing the quarterly release cadence in order to enable others to
release quarterly on a fresher version of coreboot.

Update this document with changes that should be in the release notes.

* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.

Significant changes
-------------------

### Add significant changes here
52 changes: 27 additions & 25 deletions Documentation/releases/index.md
View file
@@ -1,35 +1,37 @@
Release notes for previous releases
===================================
# Release notes

* [4.1 - July 2015](coreboot-4.1-relnotes.md)
* [4.2 - October 2015](coreboot-4.2-relnotes.md)
* [4.3 - January 2016](coreboot-4.3-relnotes.md)
* [4.4 - May 2016](coreboot-4.4-relnotes.md)
* [4.5 - October 2016](coreboot-4.5-relnotes.md)
* [4.6 - April 2017](coreboot-4.6-relnotes.md)
* [4.7 - January 2018](coreboot-4.7-relnotes.md)
* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
* [4.9 - December 2018](coreboot-4.9-relnotes.md)
* [4.10 - July 2019](coreboot-4.10-relnotes.md)
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
## Upcoming release

Please add to the release notes as changes are added:
* [4.17 - May 2022](coreboot-4.17-relnotes.md)

The checklist contains instructions to ensure that a release covers all
The [checklist] contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
names etc.

* [checklist](checklist.md)

For release related communications consider using a template so everything
For release related communications consider using a [template] so everything
important is taken care of.

* [templates](templates.md)

Upcoming release
----------------
## Previous releases

Please add to the release notes as changes are added:
* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md)
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.10 - July 2019](coreboot-4.10-relnotes.md)
* [4.9 - December 2018](coreboot-4.9-relnotes.md)
* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
* [4.7 - January 2018](coreboot-4.7-relnotes.md)
* [4.6 - April 2017](coreboot-4.6-relnotes.md)
* [4.5 - October 2016](coreboot-4.5-relnotes.md)
* [4.4 - May 2016](coreboot-4.4-relnotes.md)
* [4.3 - January 2016](coreboot-4.3-relnotes.md)
* [4.2 - October 2015](coreboot-4.2-relnotes.md)
* [4.1 - July 2015](coreboot-4.1-relnotes.md)


[checklist]: checklist.md
[template]: templates.md
52 changes: 41 additions & 11 deletions Documentation/security/vboot/list_vboot.md
View file
@@ -1,6 +1,7 @@
# vboot-enabled devices

## AMD
- Chausie
- Majolica

## Clevo
Expand Down Expand Up @@ -29,9 +30,37 @@
- Panther (ASUS Chromebox CN60)
- Tricky (Dell Chromebox 3010)
- Zako (HP Chromebox G1)
- Agah
- Anahera
- Anahera4ES
- Brask
- Brya 0
- Brya4ES
- Felwinter
- Gimble
- Gimble4ES
- Kano
- Nivviks
- Nereid
- Primus
- Primus4ES
- Redrix
- Redrix4ES
- Taeko
- Taeko4ES
- Taniks
- Vell
- Volmar
- Banshee
- Crota
- Moli
- Kinox
- Butterfly (HP Pavilion Chromebook 14)
- Cherry
- Dojo
- Tomato
- Kingler
- Krabby
- Banon (Acer Chromebook 15 (CB3-532))
- Celes (Samsung Chromebook 3)
- Cyan (Acer Chromebook R11 (C738T))
Expand Down Expand Up @@ -70,31 +99,31 @@
- Nipperkin
- Dewatt
- Akemi (IdeaPad Flex 5/5i Chromebook)
- Ambassador
- Dooly
- Dratini (HP Pro c640 Chromebook)
- Duffy Legacy (32MB)
- Duffy (ASUS Chromebox 4)
- Faffy (ASUS Fanless Chromebox)
- Genesis
- Hatch
- Helios (ASUS Chromebook Flip C436FA)
- Helios_Diskswap
- Jinlon (HP Elite c1030 Chromebook)
- Kaisa Legacy (32MB)
- Kaisa (Acer Chromebox CXI4)
- Kohaku (Samsung Galaxy Chromebook)
- Kindred (Acer Chromebook 712)
- Helios (ASUS Chromebook Flip C436FA)
- Kohaku (Samsung Galaxy Chromebook)
- Moonbuggy
- Mushu
- Palkia
- Nightfury (Samsung Galaxy Chromebook 2)
- Noibat (HP Chromebox G3)
- Palkia
- Puff
- Helios_Diskswap
- Stryke
- Wyvern (CTL Chromebox CBx2)
- Dooly
- Ambassador
- Genesis
- Scout
- Moonbuggy
- Wyvern (CTL Chromebox CBx2)
- Herobrine
- Herobrine_Rev0
- Senor
- Piglin
- Hoglin
Expand Down Expand Up @@ -165,7 +194,6 @@
- Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
- Sand (Acer Chromebook 15 CB515-1HT/1H)
- Snappy (HP Chromebook x360 11 G1 EE)
- Nasher
- Coral
- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
- Sarien (Dell Latitude 5400 Chromebook Enterprise)
Expand Down Expand Up @@ -215,6 +243,8 @@
- Alderlake-P RVP with Microchip EC
- Alderlake-M RVP
- Alderlake-M RVP with Chrome EC
- Alderlake-N RVP
- Alderlake-N RVP with Chrome EC
- Basking Ridge CRB
- Coffeelake U SO-DIMM DDR4 RVP
- Coffeelake H SO-DIMM DDR4 RVP11
Expand Down
15 changes: 15 additions & 0 deletions MAINTAINERS
View file
Expand Up @@ -141,7 +141,9 @@ AMD family 17h and 19h reference boards
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Fred Reitberger <reitbergerfred@gmail.com>
S: Maintained
F: src/mainboard/amd/chausie/
F: src/mainboard/amd/majolica/
F: src/mainboard/amd/mandolin/

Expand Down Expand Up @@ -612,6 +614,7 @@ M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com>
S: Maintained
F: src/soc/amd/cezanne/
F: src/vendorcode/amd/fsp/cezanne/
Expand All @@ -621,6 +624,7 @@ M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com>
S: Maintained
F: src/soc/amd/common/

Expand All @@ -629,10 +633,21 @@ M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com>
S: Maintained
F: src/soc/amd/picasso/
F: src/vendorcode/amd/fsp/picasso/

AMD Sabrina
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com>
S: Maintained
F: src/soc/amd/sabrina/
F: src/vendorcode/amd/fsp/sabrina/

AMD Stoneyridge
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
Expand Down
21 changes: 15 additions & 6 deletions Makefile.inc
View file
Expand Up @@ -263,15 +263,24 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
# Redundant offset remarks are not useful in any way and are masking useful
# ones that might indicate an issue so it is better to hide them.
REDUNDANT_OFFSET_REMARK = 2158
# Ignore _HID & _ADR coexisting in Intel Lynxpoint ASL code.
# See cb:38802
# "Multiple types (Device object requires either a _HID or _ADR, but not both)"
MULTIPLE_TYPES_WARNING = 3073
# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
# 1) If _PRS is present, must have _CRS and _SRS
# 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
# 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
# 4) If _SRS is present, probably should have a _DIS (Remark only)
# A warning will be issued for each of these cases.
# For existing ASL code, ignore this warnings
IASL_MISSING_DEPENDENCY = 3141

IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)

ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING)
ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
build_complete::
printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n"
printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
printf "*** If _SRS is present, must have _PRS, _CRS, and _SRS ***\n"
printf "*** If _DIS is present, must have _SRS, _PRS, _CRS, and _SRS ***\n"
endif

IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
Expand Down
1 change: 1 addition & 0 deletions configs/config.emulation_qemu_power9
View file
@@ -0,0 +1 @@
CONFIG_BOARD_EMULATION_QEMU_POWER9=y
1 change: 1 addition & 0 deletions configs/config.emulation_qemu_x86_i440fx_debug
View file
Expand Up @@ -8,3 +8,4 @@ CONFIG_DEBUG_PIRQ=y
CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_BOOT_STATE=y
CONFIG_DEBUG_ADA_CODE=y
CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
4 changes: 3 additions & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.3"
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_CBFS_SIZE=0x00200000
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
Expand Down Expand Up @@ -28,3 +28,5 @@ CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.22"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
4 changes: 3 additions & 1 deletion configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.3"
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,157b"
Expand Down Expand Up @@ -32,3 +32,5 @@ CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.22"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
2 changes: 2 additions & 0 deletions configs/config.pcengines_apu2_vboot
View file
Expand Up @@ -23,3 +23,5 @@ CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
4 changes: 3 additions & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.3"
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down Expand Up @@ -32,3 +32,5 @@ CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.22"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
4 changes: 3 additions & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.3"
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down Expand Up @@ -32,3 +32,5 @@ CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.22"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
4 changes: 3 additions & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.3"
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down Expand Up @@ -32,3 +32,5 @@ CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.22"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
4 changes: 3 additions & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.3"
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down Expand Up @@ -32,3 +32,5 @@ CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.22"
CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
1 change: 1 addition & 0 deletions payloads/Makefile.inc
View file
Expand Up @@ -29,6 +29,7 @@ payloads/external/tianocore \
payloads/external/GRUB2 \
payloads/external/LinuxBoot \
payloads/external/Yabits \
payloads/external/skiboot \

force-payload:

Expand Down
2 changes: 2 additions & 0 deletions payloads/external/.gitignore
View file
Expand Up @@ -8,3 +8,5 @@ tint/tint/
U-Boot/u-boot/
Memtest86Plus/memtest86plus/
iPXE/ipxe/
skiboot/skiboot
skiboot/build
29 changes: 22 additions & 7 deletions payloads/external/Makefile.inc
View file
Expand Up @@ -191,22 +191,29 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D

# Tianocore

payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
$(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
$(MAKE) -C payloads/external/tianocore all \
HOSTCC="$(HOSTCC)" \
CC="$(HOSTCC)" \
CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
CONFIG_TIANOCORE_REPOSITORY=$(CONFIG_TIANOCORE_REPOSITORY) \
CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \
CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \
CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
Expand All @@ -216,6 +223,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
OBJCOPY_arm=$(OBJCOPY_arm) \
OBJCOPY_arm64=$(OBJCOPY_arm64) \
MFLAGS= MAKEFLAGS=
mv payloads/external/tianocore/output/UEFIPAYLOAD.fd $@

# FILO

Expand Down Expand Up @@ -409,3 +417,10 @@ payloads/external/Yabits/uefi/build/uefi.elf yabits:

payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf:
$(MAKE) -C payloads/external/BOOTBOOT all

# skiboot

payloads/external/skiboot/build/skiboot.elf:
$(MAKE) -C payloads/external/skiboot all \
CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)
21 changes: 21 additions & 0 deletions payloads/external/skiboot/Kconfig
View file
@@ -0,0 +1,21 @@
## SPDX-License-Identifier: GPL-2.0-only

if PAYLOAD_SKIBOOT

config PAYLOAD_FILE
default "payloads/external/skiboot/build/skiboot.elf"

config SKIBOOT_GIT_REPO
string "Git repository of skiboot payload"
default "https://github.com/open-power/skiboot"
help
Git repository which will be used to clone skiboot.

config SKIBOOT_REVISION
string "Revision of skiboot payload"
default "d93ddbd39b4eeac0bc11dacbdadea76df2996c13" if BOARD_EMULATION_QEMU_POWER9
help
Revision, that skiboot repository will be checked out to, before building
an image.

endif # PAYLOAD_SKIBOOT
8 changes: 8 additions & 0 deletions payloads/external/skiboot/Kconfig.name
View file
@@ -0,0 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only

config PAYLOAD_SKIBOOT
bool "skiboot"
depends on ARCH_PPC64
help
Select this option if you want to build a coreboot image
with a skiboot payload.
36 changes: 36 additions & 0 deletions payloads/external/skiboot/Makefile
View file
@@ -0,0 +1,36 @@
## SPDX-License-Identifier: GPL-2.0-only

build_dir=$(CURDIR)/build
skiboot_dir=$(CURDIR)/skiboot
skiboot_git_repo=$(CONFIG_SKIBOOT_GIT_REPO)
skiboot_revision=$(CONFIG_SKIBOOT_REVISION)
skiboot_elf=$(build_dir)/skiboot.elf
skiboot_cross=$(or $(CROSS),powerpc64-linux-gnu-)

unexport $(COREBOOT_EXPORTS)

.PHONY: all clean distclean

all: $(skiboot_elf)

$(skiboot_elf): | $(skiboot_dir) $(build_dir)
+$(MAKE) -C $(skiboot_dir) CROSS="$(skiboot_cross)"
cp $(skiboot_dir)/skiboot.elf $@
# skiboot is always built with debug information due to unconditional -ggdb
$(skiboot_cross)strip $@

$(skiboot_dir):
git clone $(skiboot_git_repo) $(skiboot_dir)
git -C $(skiboot_dir) checkout $(skiboot_revision)

$(build_dir):
mkdir -p $(build_dir)

distclean: clean
rm -rf $(skiboot_dir)

clean:
# Redefine RM because it's used like `$(RM) non-existent-file`
# Also ignore useless messages about removing test files
[ ! -d $(skiboot_dir) ] || $(MAKE) -C $(skiboot_dir) RM="rm -rf" clean > /dev/null
rm -rf $(build_dir)
125 changes: 90 additions & 35 deletions payloads/external/tianocore/Kconfig
View file
Expand Up @@ -2,7 +2,7 @@ if PAYLOAD_TIANOCORE

config PAYLOAD_FILE
string "Tianocore binary"
default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd"
default "$(obj)/UEFIPAYLOAD.fd"
help
The result of a UefiPayloadPkg build

Expand Down Expand Up @@ -35,13 +35,30 @@ config TIANOCORE_COREBOOTPAYLOAD
Select this option to build using MrChromebox's older (now deprecated)
CorebootPayloadPkg-based Tianocore branch

config TIANOCORE_CUSTOM
bool "Custom"
help
Specify your own edk2 repository and branch to use.

endchoice

config TIANOCORE_REVISION_ID
config TIANOCORE_REPOSITORY
string "URL to git repository for edk2"
default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM
default "https://github.com/mrchromebox/edk2" if TIANOCORE_UEFIPAYLOAD || TIANOCORE_COREBOOTPAYLOAD
help
coreboot supports an array of build options which can be found below. These options
will only have an effect if the relevant options exist in the target repository.

config TIANOCORE_TAG_OR_REV
string "Insert a commit's SHA-1 or a branch name"
default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD
default "origin/master" if TIANOCORE_UPSTREAM
default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD
help
The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master"
for master branch of Tianocore release on github.
The commit's SHA-1 or branch name of the revision to use. This must exist in
TIANOCORE_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
"origin/uefipayload_202202"

choice
prompt "Tianocore build"
Expand All @@ -64,32 +81,33 @@ endchoice

if TIANOCORE_UEFIPAYLOAD

config TIANOCORE_CBMEM_LOGGING
bool "Enable Tianocore logging to CBMEM"
config TIANOCORE_ABOVE_4G_MEMORY
bool "Enable above 4G memory"
default n
help
Select this option if you want to enable Tianocore logging to CBMEM.
You may want to increase the default cbmem buffer size when selecting
this option, especially if using a debug (vs release) build.
Selecting this option will increase the payload size in CBFS by ~220KB.
Select this option to enable Above 4G Decode. This will allow the
payload to use all of the memory, rather than an maximum of 4G.

Disabling memory above 4G is useful for bootloaders that are not
fully 64-bit aware such as Qubes R4.0.4 bootloader.

config TIANOCORE_BOOTSPLASH_IMAGE
bool "Use a custom bootsplash image"
help
Select this option if you have a bootsplash image that you would
like to be used. If this option is not selected, the default
coreboot logo (European Brown Hare) will used.

config TIANOCORE_BOOTSPLASH_FILE
string "Tianocore Bootsplash path and filename"
depends on TIANOCORE_BOOTSPLASH_IMAGE
default "bootsplash.bmp"
help
Select this option if you have a bootsplash image that you would
like to be used. If this option is not selected, the default
coreboot logo (European Brown Hare) will used.

The path and filename of the file to use as graphical bootsplash
image. The file must be an uncompressed BMP.
image. The file must be an uncompressed BMP, in BMP 3 format.

Linux can create these with the below command:
`convert splosh.bmp BMP3:splash.bmp`

This image will also be used as the BGRT boot image, which may
persist through your OS boot process, and will be displayed
vertically centered 38.2% from the top of the display.
persist through your OS boot process.

See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and
Microsoft's documentation on BGRT positioning:
Expand All @@ -101,16 +119,61 @@ config TIANOCORE_BOOTSPLASH_FILE
If an absolute path is not given, the path will assumed to be
relative to the coreboot root directory.

config TIANOCORE_ABOVE_4G_MEMORY
bool "Enable above 4G memory"
config TIANOCORE_BOOT_MANAGER_ESCAPE
bool "Use Escape key for Boot Manager"
default n
help
Select this option to enable Above 4G Decode. This will allow the
payload to use all of the memory, rather than an maximum of 4G.
Use Escape as the hot-key to access the Boot Manager. This replaces
the default key of F2.

Disabling this option, which will reserve memory above 4G, is
useful for bootloaders that are not fully 64-bit aware such as
Qubes R4.0.4 bootloader.
config TIANOCORE_BOOT_TIMEOUT
int
default 2
help
The length of time in seconds for which the boot splash/menu prompt will be displayed.
For boards with an internal display, the default value of 2s is generally sufficient.
For boards with an external display, a value of 5s is generally sufficient.

config TIANOCORE_CBMEM_LOGGING
bool "Enable Tianocore logging to CBMEM"
help
Select this option if you want to enable Tianocore logging to CBMEM.
You may want to increase the default cbmem buffer size when selecting
this option, especially if using a debug (vs release) build.
Selecting this option will increase the payload size in CBFS by 0x10000.

config TIANOCORE_FOLLOW_BGRT_SPEC
bool "Center logo 38.2% from the top of screen"
default n
help
Follow the BGRT Specification implemented by Microsoft and
the Boot Logo 38.2% will be vertically centered 38.2% from
the top of the display.

config TIANOCORE_HAVE_EFI_SHELL
bool "Include EFI Shell"
default y
help
Include the EFI shell Binary

config TIANOCORE_PRIORITIZE_INTERNAL
bool "Prioritize internal boot devices"
default y
help
Prioritize internal boot devices over external devices

config TIANOCORE_PS2_SUPPORT
bool "Support PS/2 Keyboards"
default y
help
Include support for PS/2 keyboards

config TIANOCORE_SD_MMC_TIMEOUT
int "Timeout in μs for initializing SD Card reader"
default 1000
help
The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
Most only require 1000μs, but certain readers can take 1000000μs.

endif

Expand All @@ -123,12 +186,4 @@ config TIANOCORE_USE_8254_TIMER

endif

config TIANOCORE_BOOT_TIMEOUT
int
default 2
help
The length of time in seconds for which the boot splash/menu prompt will be displayed.
For boards with an internal display, the default value of 2s is generally sufficient.
For boards without an internal display, a value of 5s is generally sufficient.

endif
145 changes: 89 additions & 56 deletions payloads/external/tianocore/Makefile
View file
Expand Up @@ -4,83 +4,115 @@
export SHELL := env bash

project_name=Tianocore
project_dir=$(CURDIR)/tianocore
project_dir = $(CURDIR)/$(word 3,$(subst /, ,$(CONFIG_TIANOCORE_REPOSITORY)))
project_git_repo=https://github.com/3mdeb/edk2
project_git_branch=coreboot-4.7.x-uefi
upstream_git_repo=https://github.com/tianocore/edk2

build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE

BUILD_STR = -a IA32 -a X64 -t COREBOOT
ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
project_git_branch=coreboot_fb
bootloader=CorebootPayloadPkg
BUILD_STR += -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
else
bootloader=UefiPayloadPkg
BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
endif

ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y)
TAG=upstream/master
else
TAG=origin/$(project_git_branch)
BUILD_STR += -D BOOTLOADER=COREBOOT -q

#
# EDK II has the following build options relevant to coreboot:
#
#
# OPTION = DEFAULT_VALUE
#
# ABOVE_4G_MEMORY = TRUE
ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
endif

ifneq ($(CONFIG_TIANOCORE_REVISION_ID),)
TAG=$(CONFIG_TIANOCORE_REVISION_ID)
# BOOTSPLASH_IMAGE = FALSE
ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),)
BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
endif

export EDK_TOOLS_PATH=$(project_dir)/BaseTools

ifeq ($(CONFIG_TIANOCORE_DEBUG),y)
BUILD_TYPE=DEBUG
else
BUILD_TYPE=RELEASE
# BOOT_MANAGER_ESCAPE = FALSE
ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y)
BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE
endif

# BUILD_TARGETS = DEBUG
ifeq ($(CONFIG_TIANOCORE_RELEASE),y)
BUILD_STR += -b RELEASE
endif
# FOLLOW_BGRT_SPEC = FALSE
ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
endif
# PRIORITIZE_INTERNAL = FALSE
ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
endif
# PS2_KEYBOARD_ENABLE = FALSE
ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
endif
# PLATFORM_BOOT_TIMEOUT = 3
ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
endif
# SIO_BUS_ENABLE = FALSE
ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
BUILD_STR += -D SIO_BUS_ENABLE=TRUE
endif
# SHELL_TYPE = BUILD_SHELL
ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y)
BUILD_STR += -D SHELL_TYPE=NONE
endif
# USE_CBMEM_FOR_CONSOLE = FALSE
ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE
BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
endif

ifeq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
4G=-D ABOVE_4G_MEMORY=TRUE
else
4G=-D ABOVE_4G_MEMORY=FALSE
# SD_MMC_TIMEOUT = 1000000
ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
BUILD_STR += -D SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT)
endif

TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)

ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
TIMER=-DUSE_HPET_TIMER
#
# The below are legacy options only available in CorebootPayloadPkg:
#
# PCIE_BASE = 0
ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),)
BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
endif

ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE
else
BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G)
# USE_HPET_TIMER = FALSE
ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y)
BUILD_STR += -D USE_HPET_TIMER=TRUE
endif

bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))

export EDK_TOOLS_PATH=$(project_dir)/BaseTools

all: clean build

$(project_dir):
echo " Cloning $(project_name) from Git"
git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \
cd $(project_dir); \
git remote add upstream $(upstream_git_repo)
echo " Cloning $(project_name) from $(CONFIG_TIANOCORE_REPOSITORY)"
git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
cd $(project_dir);

update: $(project_dir)
if [ ! -d "$(project_dir)" ]; then \
git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
fi
cd $(project_dir); \
echo " Fetching new commits from the $(project_name) repo"; \
git fetch --multiple origin upstream 2>/dev/null; \
if ! git rev-parse --verify -q $(TAG) >/dev/null; then \
echo " $(TAG) is not a valid git reference"; \
echo " Fetching new commits from $(CONFIG_TIANOCORE_REPOSITORY)"; \
git fetch origin 2>/dev/null; \
if ! git rev-parse --verify -q $(CONFIG_TIANOCORE_TAG_OR_REV) >/dev/null; then \
echo " $(CONFIG_TIANOCORE_TAG_OR_REV) is not a valid git reference"; \
exit 1; \
fi; \
if git status --ignore-submodules=dirty | grep -qv clean; then \
echo " Checking out $(project_name) revision $(TAG)"; \
git checkout --detach $(TAG); \
echo " Checking out $(project_name) revision $(CONFIG_TIANOCORE_TAG_OR_REV)"; \
git checkout --detach $(CONFIG_TIANOCORE_TAG_OR_REV) -f; \
else \
echo " Working directory not clean; will not overwrite"; \
fi; \
git submodule update --init
git submodule update --init --checkout

checktools:
echo "Checking uuid-dev..."
Expand All @@ -94,15 +126,15 @@ checktools:
( echo " Not found."; echo "Error: Please install nasm."; exit 1 )

build: update checktools
unset CC; $(MAKE) -C $(project_dir)/BaseTools
echo " build $(project_name) $(TAG)"
unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)"
if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
echo " Copying custom bootsplash image"; \
case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
esac \
fi; \
cd $(project_dir); \
Expand All @@ -114,13 +146,14 @@ build: update checktools
cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
fi; \
build $(BUILD_STR); \
mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
mkdir -p $(project_dir)/../output
mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/../output/UEFIPAYLOAD.fd; \
git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true

clean:
test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0

distclean:
rm -rf $(project_dir)
rm -rf */

.PHONY: all update checktools config build clean distclean
2 changes: 1 addition & 1 deletion payloads/libpayload/Makefile.inc
View file
Expand Up @@ -62,7 +62,7 @@ subdirs-$(CONFIG_LP_VBOOT_LIB) += vboot
INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj)
INCLUDES += -include include/kconfig.h -include include/compiler.h
INCLUDES += -I$(coreboottop)/src/commonlib/bsd/include
INCLUDES += -I$(coreboottop)/3rdparty/vboot/firmware/include
INCLUDES += -I$(VBOOT_SOURCE)/firmware/include

CFLAGS += $(INCLUDES) -Os -pipe -nostdinc -ggdb3
CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
Expand Down
1 change: 1 addition & 0 deletions payloads/libpayload/arch/x86/Makefile.inc
View file
Expand Up @@ -42,6 +42,7 @@ libc-$(CONFIG_LP_GPL) += string.c
libgdb-y += gdb.c

libcbfs-$(CONFIG_LP_CBFS) += rom_media.c
libcbfs-$(CONFIG_LP_CBFS) += boot_media.c

# Multiboot support is configurable
libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c
Expand Down
3 changes: 2 additions & 1 deletion payloads/libpayload/arch/x86/boot_media.c
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause */

#include <arch/virtual.h>
#include <boot_device.h>
#include <commonlib/bsd/cb_err.h>
#include <stddef.h>
Expand All @@ -11,7 +12,7 @@ __attribute__((weak)) ssize_t boot_device_read(void *buf, size_t offset, size_t
/* Memory-mapping usually only works for the top 16MB. */
if (!lib_sysinfo.boot_media_size || lib_sysinfo.boot_media_size - offset > 16 * MiB)
return CB_ERR_ARG;
void *ptr = (void *)(uintptr_t)(0 - lib_sysinfo.boot_media_size + offset);
const void *const ptr = phys_to_virt(0 - lib_sysinfo.boot_media_size + offset);
memcpy(buf, ptr, size);
return size;
}
2 changes: 1 addition & 1 deletion payloads/libpayload/bin/lpgcc
View file
Expand Up @@ -182,7 +182,7 @@ trygccoption -fno-stack-protector
_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
_CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"

_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static"
_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections"

if [ $DOLINK -eq 0 ]; then
if [ $DEBUGME -eq 1 ]; then
Expand Down
4 changes: 2 additions & 2 deletions payloads/libpayload/libc/coreboot.c
View file
Expand Up @@ -230,11 +230,11 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
break;
case CBMEM_ID_CBFS_RO_MCACHE:
info->cbfs_ro_mcache_offset = cbmem_entry->address;
info->cbfs_ro_mcache_size = cbmem_entry->size;
info->cbfs_ro_mcache_size = cbmem_entry->entry_size;
break;
case CBMEM_ID_CBFS_RW_MCACHE:
info->cbfs_rw_mcache_offset = cbmem_entry->address;
info->cbfs_rw_mcache_size = cbmem_entry->size;
info->cbfs_rw_mcache_size = cbmem_entry->entry_size;
break;
case CBMEM_ID_CONSOLE:
info->cbmem_cons = cbmem_entry->address;
Expand Down
4 changes: 2 additions & 2 deletions payloads/libpayload/libcbfs/cbfs.c
View file
Expand Up @@ -164,13 +164,13 @@ static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t

if (buf) {
if (!size_inout || *size_inout < out_size) {
ERROR("'%s' buffer too small", mdata->h.filename);
ERROR("'%s' buffer too small\n", mdata->h.filename);
return NULL;
}
} else {
buf = malloc(out_size);
if (!buf) {
ERROR("'%s' allocation failure", mdata->h.filename);
ERROR("'%s' allocation failure\n", mdata->h.filename);
return NULL;
}
malloced = true;
Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/tests/Makefile.inc
View file
Expand Up @@ -34,7 +34,7 @@ TEST_CFLAGS := -include include/kconfig.h -include include/compiler.h
TEST_CFLAGS += -Iinclude -Iinclude/mock
TEST_CFLAGS += -I$(coreboottop)/src/commonlib/bsd/include
TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER))
TEST_CFLAGS += -I$(coreboottop)/3rdparty/vboot/firmware/include
TEST_CFLAGS += -I$(VBOOT_SOURCE)/firmware/include

# Test specific includes
TEST_CFLAGS += -I$(testsrc)/include
Expand Down
2 changes: 2 additions & 0 deletions payloads/libpayload/vboot/Kconfig
View file
Expand Up @@ -2,6 +2,7 @@

config VBOOT_LIB
bool "Compile verified boot (vboot) library"
default y if CHROMEOS
default n
help
This option enables compiling and building vboot libraries vboot_fw and tlcl.
Expand All @@ -16,6 +17,7 @@ config VBOOT_TPM2_MODE

config VBOOT_X86_SHA_EXT
bool "x86 SHA Extension"
default y if CHROMEOS
default n
depends on ARCH_X86
help
Expand Down
8 changes: 4 additions & 4 deletions payloads/libpayload/vboot/Makefile.inc
View file
Expand Up @@ -7,7 +7,7 @@ TLCL_LIB = $(VBOOT_BUILD_DIR)/tlcl.a
vboot_fw-objs += $(VBOOT_FW_LIB)
tlcl-objs += $(TLCL_LIB)

kconfig-to-binary=$(if $(1),1,0)
kconfig-to-binary=$(if $(strip $(1)),1,0)
vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\
$(patsubst include/%.h,$(top)/include/%.h,\
$(filter-out -I$(obj),$(1))))
Expand All @@ -30,14 +30,14 @@ endif

$(VBOOT_FW_LIB): $(obj)/libpayload-config.h
@printf " MAKE $(subst $(obj)/,,$(@))\n"
+$(Q) FIRMWARE_ARCH=$(VBOOT_FIRMWARE_ARCH-y) \
CC=$(CC) \
+$(Q) FIRMWARE_ARCH="$(VBOOT_FIRMWARE_ARCH-y)" \
CC="$(CC)" \
CFLAGS="$(VBOOT_CFLAGS)" \
$(MAKE) -C "$(VBOOT_SOURCE)" \
TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \
X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \
UNROLL_LOOPS=1 \
BUILD=$(VBOOT_BUILD_DIR) \
BUILD="$(VBOOT_BUILD_DIR)" \
V=$(V) \
$(VBOOT_BUILD_DIR)/vboot_fw.a tlcl

Expand Down
12 changes: 12 additions & 0 deletions spd/lp4x/memory_parts.json
View file
Expand Up @@ -339,6 +339,18 @@
"ranksPerChannel": 2,
"speedMbps": 4267
}
},
{
"name": "MT53E2G32D4NQ-046 WT:C",
"attribs": {
"densityPerChannelGb": 16,
"banks": 8,
"channelsPerDie": 2,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 2,
"speedMbps": 4267
}
}
]
}
1 change: 1 addition & 0 deletions spd/lp4x/set-0/parts_spd_manifest.generated.txt
View file
Expand Up @@ -29,3 +29,4 @@ H54G46CYRBX267,spd-1.hex
H54G56CYRBX247,spd-3.hex
K4U6E3S4AB-MGCL,spd-1.hex
K4UBE3D4AB-MGCL,spd-3.hex
MT53E2G32D4NQ-046 WT:C,spd-7.hex
1 change: 1 addition & 0 deletions spd/lp4x/set-1/parts_spd_manifest.generated.txt
View file
Expand Up @@ -29,3 +29,4 @@ H54G46CYRBX267,spd-1.hex
H54G56CYRBX247,spd-3.hex
K4U6E3S4AB-MGCL,spd-1.hex
K4UBE3D4AB-MGCL,spd-3.hex
MT53E2G32D4NQ-046 WT:C,spd-10.hex
20 changes: 20 additions & 0 deletions spd/lp5/memory_parts.json
View file
Expand Up @@ -29,6 +29,26 @@
"ranksPerChannel": 2,
"speedMbps": 6400
}
},
{
"name": "K3LKBKB0BM-MGCP",
"attribs": {
"densityPerDieGb": 16,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 6400
}
},
{
"name": "H9JCNNNBK3MLYR-N6E",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 2,
"bitWidthPerChannel": 16,
"ranksPerChannel": 1,
"speedMbps": 6400
}
}
]
}
1 change: 1 addition & 0 deletions spd/lp5/platforms_manifest.generated.txt
View file
Expand Up @@ -2,3 +2,4 @@
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

ADL,set-0
SBR,set-1
2 changes: 2 additions & 0 deletions spd/lp5/set-0/parts_spd_manifest.generated.txt
View file
Expand Up @@ -4,3 +4,5 @@
MT62F512M32D2DR-031 WT:B,spd-1.hex
MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex
H9JCNNNBK3MLYR-N6E,spd-1.hex
32 changes: 32 additions & 0 deletions spd/lp5/set-0/spd-3.hex
View file
@@ -0,0 +1,32 @@
23 10 13 0E 16 22 95 08 00 00 00 00 02 01 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8 changes: 8 additions & 0 deletions spd/lp5/set-1/parts_spd_manifest.generated.txt
View file
@@ -0,0 +1,8 @@
# Generated by:
# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

MT62F512M32D2DR-031 WT:B,spd-1.hex
MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex
H9JCNNNBK3MLYR-N6E,spd-1.hex
32 changes: 32 additions & 0 deletions spd/lp5/set-1/spd-1.hex
View file
@@ -0,0 +1,32 @@
23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
32 changes: 32 additions & 0 deletions spd/lp5/set-1/spd-2.hex
View file
@@ -0,0 +1,32 @@
23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
32 changes: 32 additions & 0 deletions spd/lp5/set-1/spd-3.hex
View file
@@ -0,0 +1,32 @@
23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
32 changes: 32 additions & 0 deletions spd/lp5/set-1/spd-empty.hex
View file
@@ -0,0 +1,32 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2 changes: 1 addition & 1 deletion src/Kconfig
View file
Expand Up @@ -878,7 +878,7 @@ config GDB_STUB
depends on DRIVERS_UART
help
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.
See src/arch/x86/c_start.S for details.

config GDB_WAIT
bool "Wait for a GDB connection in the ramstage"
Expand Down
16 changes: 12 additions & 4 deletions src/acpi/acpi.c
View file
Expand Up @@ -18,6 +18,8 @@
#include <acpi/acpi.h>
#include <acpi/acpi_ivrs.h>
#include <acpi/acpigen.h>
#include <arch/hpet.h>
#include <arch/mmio.h>
#include <device/pci.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
Expand Down Expand Up @@ -847,10 +849,10 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
addr->space_id = ACPI_ADDRESS_SPACE_MEMORY;
addr->bit_width = 64;
addr->bit_offset = 0;
addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
addr->addrl = HPET_BASE_ADDRESS & 0xffffffff;
addr->addrh = ((unsigned long long)HPET_BASE_ADDRESS) >> 32;

hpet->id = *(unsigned int *)CONFIG_HPET_ADDRESS;
hpet->id = read32p(HPET_BASE_ADDRESS);
hpet->number = 0;
hpet->min_tick = CONFIG_HPET_MIN_TICKS;

Expand Down Expand Up @@ -1507,6 +1509,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = asl_revision;

fadt->FADT_MinorVersion = get_acpi_fadt_minor_version();
fadt->firmware_ctrl = (unsigned long) facs;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
Expand Down Expand Up @@ -1944,11 +1947,16 @@ __weak int acpi_get_gpe(int gpe)
return -1; /* implemented by SOC */
}

u8 get_acpi_fadt_minor_version(void)
{
return ACPI_FADT_MINOR_VERSION_0;
}

int get_acpi_table_revision(enum acpi_tables table)
{
switch (table) {
case FADT:
return ACPI_FADT_REV_ACPI_6_0;
return ACPI_FADT_REV_ACPI_6;
case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */
return 3;
case MCFG:
Expand Down
67 changes: 27 additions & 40 deletions src/acpi/acpigen.c
View file
Expand Up @@ -406,8 +406,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
acpigen_emit_byte(pblock_len);
}

void acpigen_write_processor_package(const char *const name,
const unsigned int first_core,
void acpigen_write_processor_package(const char *const name, const unsigned int first_core,
const unsigned int core_count)
{
unsigned int i;
Expand All @@ -430,8 +429,7 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores)
acpigen_write_method("\\_SB.CNOT", 1);
for (core_id = 0; core_id < number_of_cores; core_id++) {
char buffer[DEVICE_PATH_MAX];
snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING,
core_id);
snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, core_id);
acpigen_emit_byte(NOTIFY_OP);
acpigen_emit_namestring(buffer);
acpigen_emit_byte(ARG0_OP);
Expand Down Expand Up @@ -514,22 +512,19 @@ static void acpigen_write_field_length(uint32_t len)
acpigen_emit_byte(emit[j]);
}

static void acpigen_write_field_offset(uint32_t offset,
uint32_t current_bit_pos)
static void acpigen_write_field_offset(uint32_t offset, uint32_t current_bit_pos)
{
uint32_t diff_bits;

if (offset < current_bit_pos) {
printk(BIOS_WARNING, "%s: Cannot move offset backward",
__func__);
printk(BIOS_WARNING, "%s: Cannot move offset backward", __func__);
return;
}

diff_bits = offset - current_bit_pos;
/* Upper limit */
if (diff_bits > 0xFFFFFFF) {
printk(BIOS_WARNING, "%s: Offset very large to encode",
__func__);
printk(BIOS_WARNING, "%s: Offset very large to encode", __func__);
return;
}

Expand Down Expand Up @@ -601,8 +596,7 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou
current_bit_pos = l[i].bits;
break;
default:
printk(BIOS_ERR, "%s: Invalid field type 0x%X\n"
, __func__, l[i].type);
printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", __func__, l[i].type);
break;
}
}
Expand Down Expand Up @@ -630,8 +624,8 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou
* PMCS, 2
* }
*/
void acpigen_write_indexfield(const char *idx, const char *data,
struct fieldlist *l, size_t count, uint8_t flags)
void acpigen_write_indexfield(const char *idx, const char *data, struct fieldlist *l,
size_t count, uint8_t flags)
{
uint16_t i;
uint32_t current_bit_pos = 0;
Expand All @@ -658,8 +652,7 @@ void acpigen_write_indexfield(const char *idx, const char *data,
current_bit_pos = l[i].bits;
break;
default:
printk(BIOS_ERR, "%s: Invalid field type 0x%X\n"
, __func__, l[i].type);
printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", __func__, l[i].type);
break;
}
}
Expand Down Expand Up @@ -945,8 +938,8 @@ void acpigen_write_PRW(u32 wake, u32 level)
acpigen_pop_len();
}

void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
u32 busmLat, u32 control, u32 status)
void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control,
u32 status)
{
acpigen_write_package(6);
acpigen_write_dword(coreFreq);
Expand All @@ -957,8 +950,8 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
acpigen_write_dword(status);
acpigen_pop_len();

printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n",
coreFreq, power, control, status);
printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", coreFreq, power,
control, status);
}

void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries)
Expand Down Expand Up @@ -1193,14 +1186,12 @@ void acpigen_write_resourcetemplate_footer(void)
acpigen_pop_len();
}

static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev,
struct resource *res)
static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, struct resource *res)
{
acpigen_write_mem32fixed(0, res->base, res->size);
}

static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev,
struct resource *res)
static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, struct resource *res)
{
resource_t base = res->base;
resource_t size = res->size;
Expand All @@ -1219,13 +1210,13 @@ void acpigen_write_mainboard_resource_template(void)
/* Add reserved memory ranges. */
search_global_resources(
IORESOURCE_MEM | IORESOURCE_RESERVE,
IORESOURCE_MEM | IORESOURCE_RESERVE,
IORESOURCE_MEM | IORESOURCE_RESERVE,
acpigen_add_mainboard_rsvd_mem32, 0);

/* Add reserved io ranges. */
search_global_resources(
IORESOURCE_IO | IORESOURCE_RESERVE,
IORESOURCE_IO | IORESOURCE_RESERVE,
IORESOURCE_IO | IORESOURCE_RESERVE,
acpigen_add_mainboard_rsvd_io, 0);

acpigen_write_resourcetemplate_footer();
Expand Down Expand Up @@ -1635,8 +1626,7 @@ void acpigen_write_pld(const struct acpi_pld *pld)
acpigen_pop_len();
}

void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *),
size_t count, void *arg)
void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *), size_t count, void *arg)
{
struct dsm_uuid id = DSM_UUID(uuid, callbacks, count, arg);
acpigen_write_dsm_uuid_arr(&id, 1);
Expand Down Expand Up @@ -1783,8 +1773,7 @@ void acpigen_write_CPPC_package(const struct cppc_config *config)
max = CPPC_MAX_FIELDS_VER_3;
break;
default:
printk(BIOS_ERR, "ERROR: CPPC version %u is not implemented\n",
config->version);
printk(BIOS_ERR, "CPPC version %u is not implemented\n", config->version);
return;
}
acpigen_write_name(CPPC_PACKAGE_NAME);
Expand Down Expand Up @@ -1885,8 +1874,7 @@ void acpigen_write_rom(void *bios, const size_t length)
acpigen_write_method_serialized("_ROM", 2);

/* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */
struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY,
(uintptr_t)bios, length);
struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY, (uintptr_t)bios, length);
acpigen_write_opregion(&opreg);

struct fieldlist l[] = {
Expand All @@ -1899,8 +1887,7 @@ void acpigen_write_rom(void *bios, const size_t length)
* Offset (0),
* RBF0, 0x80000
* } */
acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC |
FIELD_NOLOCK | FIELD_PRESERVE);
acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);

/* Store (Arg0, Local0) */
acpigen_write_store();
Expand Down Expand Up @@ -2058,8 +2045,8 @@ void acpigen_get_tx_gpio(const struct acpi_gpio *gpio)
}

/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */
void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran,
u16 range_min, u16 range_max, u16 translation, u16 length)
void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min,
u16 range_max, u16 translation, u16 length)
{
acpigen_emit_byte(0x88);
/* Byte 1+2: length (0x000d) */
Expand All @@ -2081,8 +2068,8 @@ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran
}

/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */
void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags,
u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length)
void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, u32 gran,
u32 range_min, u32 range_max, u32 translation, u32 length)
{
acpigen_emit_byte(0x87);
/* Byte 1+2: length (0023) */
Expand Down Expand Up @@ -2110,8 +2097,8 @@ static void acpigen_emit_qword(u64 data)
}

/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */
void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags,
u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length)
void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran,
u64 range_min, u64 range_max, u64 translation, u64 length)
{
acpigen_emit_byte(0x8a);
/* Byte 1+2: length (0x002b) */
Expand Down
1 change: 1 addition & 0 deletions src/acpi/acpigen_ps2_keybd.c
View file
Expand Up @@ -55,6 +55,7 @@ static const uint32_t action_keymaps[] = {
KEY_PRIVACY_SCREEN_TOGGLE),
[PS2_KEY_MICMUTE] = KEYMAP(0x9b, KEY_MICMUTE), /* e01b */
[PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE), /* e01e */
[PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL), /* e0d5 */
};

/* Keymap for numeric keypad keys */
Expand Down
5 changes: 2 additions & 3 deletions src/arch/arm64/fit_payload.c
View file
Expand Up @@ -52,7 +52,7 @@ static bool decompress_kernel_header(const struct fit_image_node *node)
scratch.raw, sizeof(scratch.raw));
break;
default:
printk(BIOS_ERR, "ERROR: Unsupported compression algorithm!\n");
printk(BIOS_ERR, "Unsupported compression algorithm!\n");
return false;
}

Expand All @@ -61,8 +61,7 @@ static bool decompress_kernel_header(const struct fit_image_node *node)
die("ERROR: Partial decompression ran over scratchbuf!\n");

if (scratch.header.magic != KERNEL_HEADER_MAGIC) {
printk(BIOS_ERR,
"ERROR: Invalid kernel magic: %#.8x\n != %#.8x\n",
printk(BIOS_ERR, "Invalid kernel magic: %#.8x\n != %#.8x\n",
scratch.header.magic, KERNEL_HEADER_MAGIC);
return false;
}
Expand Down
5 changes: 4 additions & 1 deletion src/arch/ppc64/Makefile.inc
View file
Expand Up @@ -9,7 +9,8 @@ ppc64_asm_flags =
################################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y)

bootblock-y = bootblock.S stages.c
bootblock-y = bootblock_crt0.S
bootblock-y += arch_timer.c
bootblock-y += boot.c
bootblock-y += rom_media.c
bootblock-y += \
Expand All @@ -34,6 +35,7 @@ endif
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y)

romstage-y += arch_timer.c
romstage-y += boot.c
romstage-y += stages.c
romstage-y += rom_media.c
Expand Down Expand Up @@ -64,6 +66,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y)

ramstage-y += rom_media.c
ramstage-y += stages.c
ramstage-y += arch_timer.c
ramstage-y += boot.c
ramstage-y += tables.c
ramstage-y += \
Expand Down
41 changes: 41 additions & 0 deletions src/arch/ppc64/arch_timer.c
View file
@@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <timer.h>
#include <delay.h>
#include <cpu/power/spr.h>

/* Refer to hostboot/src/kernel/timemgr.C */

/* Time base frequency is 512 MHz so 512 ticks per usec */
#define TB_TICKS_PER_USEC 512

__weak void init_timer(void) { /* do nothing */ }

static struct monotonic_counter {
int initialized;
struct mono_time time;
uint64_t last_value;
} mono_counter;

void timer_monotonic_get(struct mono_time *mt)
{
uint64_t current_tick;
uint64_t usecs_elapsed;

if (!mono_counter.initialized) {
mono_counter.last_value = read_spr(SPR_TB);
mono_counter.initialized = 1;
}

current_tick = read_spr(SPR_TB);
usecs_elapsed = (current_tick - mono_counter.last_value) / TB_TICKS_PER_USEC;

/* Update current time and tick values only if a full tick occurred. */
if (usecs_elapsed) {
mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
mono_counter.last_value = current_tick;
}

/* Save result. */
*mt = mono_counter.time;
}
19 changes: 19 additions & 0 deletions src/arch/ppc64/boot.c
View file
Expand Up @@ -2,9 +2,28 @@

#include <program_loading.h>

#if ENV_PAYLOAD_LOADER

/*
* Payload's entry point is an offset to the real entry point, not to OPD
* (Official Procedure Descriptor) for entry point.
*/
void arch_prog_run(struct prog *prog)
{
asm volatile(
"mtctr %1\n"
"mr 3, %0\n"
"bctr\n"
:: "r"(prog_entry_arg(prog)), "r"(prog_entry(prog)) : "memory");
}

#else

void arch_prog_run(struct prog *prog)
{
void (*doit)(void *) = prog_entry(prog);

doit(prog_entry_arg(prog));
}

#endif
10 changes: 0 additions & 10 deletions src/arch/ppc64/bootblock.S
View file

This file was deleted.

98 changes: 98 additions & 0 deletions src/arch/ppc64/bootblock_crt0.S
View file
@@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Early initialization code for POWER8/POWER9.
*/

#include <cpu/power/spr.h>

#define FIXUP_ENDIAN \
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
b $+44; /* Skip trampoline if endian is good */ \
.long 0xa600607d; /* mfmsr r11 */ \
.long 0x01006b69; /* xori r11,r11,1 */ \
.long 0x00004039; /* li r10,0 */ \
.long 0x6401417d; /* mtmsrd r10,1 */ \
.long 0x05009f42; /* bcl 20,31,$+4 */ \
.long 0xa602487d; /* mflr r10 */ \
.long 0x14004a39; /* addi r10,r10,20 */ \
.long 0xa6035a7d; /* mtsrr0 r10 */ \
.long 0xa6037b7d; /* mtsrr1 r11 */ \
.long 0x2400004c /* rfid */

/* Load an immediate 64-bit value into a register */
#define LOAD_IMM64(r, e) \
lis r,(e)@highest; \
ori r,r,(e)@higher; \
rldicr r,r, 32, 31; \
oris r,r, (e)@h; \
ori r,r, (e)@l;

.section ".text._start", "ax", %progbits
.globl _start
_start:
/* QEMU with hb-mode=on starts at address 0x10, while hardware at 0x0 */
nop
nop
nop
nop
FIXUP_ENDIAN

/* Store FDT address provided by QEMU in %r3 to pass it later to
* payload */
mtspr SPR_HSPRG0, %r3

/* Set program priority to medium */
or %r2, %r2, %r2

/* Stack */
lis %r1, _estack@ha
addi %r1, %r1, _estack@l

/* Clear .bss section */
/* Currently not needed, .bss is zeroed in the file. If it were to be
* used, make sure that .bss is 128B aligned (size of cache line),
* otherwise dcbz will clear (part of) .opd section! */
/*
lis %r5, _bss@ha
addi %r5, %r5, _bss@l
lis %r6, _ebss@ha
addi %r6, %r6, _ebss@l
addi %r6, %r6, -1
1:
dcbz 0, %r5
addi %r5, %r5, 128
cmpld cr7, %r5, %r6
blt cr7, 1b
*/

/* This is tested by checkstack() just before jumping to payload */
LOAD_IMM64(%r3, 0xDEADBEEFDEADBEEF)
lis %r5, _stack@ha
addi %r5, %r5, _stack@l
subi %r5, %r5, 8
sub %r4, %r1, %r5
sradi %r4, %r4, 3 /* Divide by 8 */
mtctr %r4
1:
stdu %r3, 8(%r5)
bc 25, 0, 1b

/* Enable floating point and vector operations */
/* Vector operations are sometimes generated for code like
* 'uint8_t x[32] = {0}', this results in an exception when vector
* registers (VEC) are not enabled. VSX (vector-scalar extension) is
* also enabled, there is no reason not to. Floating point must also be
* enabled for VSX.
*/
mfmsr %r3
ori %r3, %r3, 0x2000 /* FP = 1 */
oris %r3, %r3, 0x0280 /* VEC = 1, VSX = 1 */
mtmsr %r3

/* Load official procedure descriptor address for main() */
lis %r12, main@ha
addi %r12, %r12, main@l

/* Load TOC pointer and jump to main() */
ld %r2, 8(%r12)
b main
12 changes: 12 additions & 0 deletions src/arch/ppc64/include/arch/byteorder.h
View file
Expand Up @@ -5,4 +5,16 @@

#define __BIG_ENDIAN 4321

#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))

#ifndef __ASSEMBLER__

#include <types.h>
#define PPC_SHIFT(val, lsb) (((uint64_t)(val)) << (63 - (lsb)))

#else
#define PPC_SHIFT(val, lsb) ((val) << (63 - (lsb)))
#endif

#endif /* _BYTEORDER_H */
3 changes: 3 additions & 0 deletions src/arch/ppc64/include/arch/io.h
View file
Expand Up @@ -8,7 +8,10 @@
/* Set MSB to 1 to ignore HRMOR */
#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
#define LPCHC_IO_SPACE 0xD0010000
#define FLASH_IO_SPACE 0xFC000000
#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE)
#define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000

/* Enforce In-order Execution of I/O */
static inline void eieio(void)
Expand Down
75 changes: 67 additions & 8 deletions src/arch/ppc64/include/arch/mmio.h
View file
Expand Up @@ -5,38 +5,97 @@

#include <stdint.h>

/* NOTE: These are just stubs; if the architecture requires special
* care to avoid posted writes or cachelines, it is not yet done here.
/* NOTE: In some cases accesses to MMIO must be separated by eieio instruction
* to prevent reordering. This is not included in functions below (performance
* reasons) and must be called explicitly. Function eieio() is defined in io.h.
*/

static inline uint8_t read8(const volatile void *addr)
{
return *(volatile uint8_t *)addr;
uint8_t val;

/* Set bit to ignore HRMOR */
addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"lbzcix %0, 0, %1" :
"=r"(val) : "r"(addr));

return val;
}

static inline uint16_t read16(const volatile void *addr)
{
return *(volatile uint16_t *)addr;
uint16_t val;

/* Set bit to ignore HRMOR */
addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"lhzcix %0, 0, %1" :
"=r"(val) : "r"(addr));

return val;
}

static inline uint32_t read32(const volatile void *addr)
{
return *(volatile uint32_t *)addr;
uint32_t val;

/* Set bit to ignore HRMOR */
addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"lwzcix %0, 0, %1" :
"=r"(val) : "r"(addr));

return val;
}

static inline uint64_t read64(const volatile void *addr)
{
uint64_t val;

/* Set bit to ignore HRMOR */
addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"ldcix %0, 0, %1" :
"=r"(val) : "r"(addr));

return val;
}

static inline void write8(volatile void *addr, uint8_t val)
{
*(volatile uint8_t *)addr = val;
/* Set bit to ignore HRMOR */
addr = (volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"stbcix %0, 0, %1" ::
"r"(val), "r"(addr));
}

static inline void write16(volatile void *addr, uint16_t val)
{
*(volatile uint16_t *)addr = val;
/* Set bit to ignore HRMOR */
addr = (volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"sthcix %0, 0, %1" ::
"r"(val), "r"(addr));
}

static inline void write32(volatile void *addr, uint32_t val)
{
*(volatile uint32_t *)addr = val;
/* Set bit to ignore HRMOR */
addr = (volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"stwcix %0, 0, %1" ::
"r"(val), "r"(addr));
}

static inline void write64(volatile void *addr, uint64_t val)
{
/* Set bit to ignore HRMOR */
addr = (volatile void *)((uint64_t)addr | 0x8000000000000000);
asm volatile(
"stdcix %0, 0, %1" ::
"r"(val), "r"(addr));
}

#endif /* __ARCH_MMIO_H__ */
5 changes: 2 additions & 3 deletions src/arch/ppc64/rom_media.c
View file
@@ -1,11 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/io.h>
#include <boot_device.h>

/* This assumes that the CBFS resides at 0x0, which is true for the default
* configuration. */
static const struct mem_region_device boot_dev =
MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE);
MEM_REGION_DEV_RO_INIT(FLASH_BASE_ADDR, CONFIG_ROM_SIZE);

const struct region_device *boot_device_ro(void)
{
Expand Down
13 changes: 13 additions & 0 deletions src/arch/ppc64/stages.c
View file
Expand Up @@ -13,10 +13,23 @@

#include <cbmem.h>
#include <arch/stages.h>
#include <cpu/power/spr.h>

void stage_entry(uintptr_t stage_arg)
{
#if ENV_RAMSTAGE
uint64_t hrmor;
#endif

if (!ENV_ROMSTAGE_OR_BEFORE)
_cbmem_top_ptr = stage_arg;

#if ENV_RAMSTAGE
hrmor = read_spr(SPR_HRMOR);
asm volatile("sync; isync" ::: "memory");
write_spr(SPR_HRMOR, 0);
asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory");
#endif

main();
}
6 changes: 1 addition & 5 deletions src/arch/x86/Kconfig
View file
Expand Up @@ -191,12 +191,8 @@ config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
depends on HAVE_CMOS_DEFAULT

config HPET_ADDRESS_OVERRIDE
def_bool n

config HPET_ADDRESS
config HPET_MIN_TICKS
hex
default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config C_ENV_BOOTBLOCK_SIZE
hex
Expand Down
8 changes: 4 additions & 4 deletions src/arch/x86/acpi/debug.asl
View file
Expand Up @@ -51,7 +51,7 @@ Method(DINI)
Method(THRE)
{
and(CLSR, 0x20, local0)
while (Lequal(local0, Zero)) {
while (local0 == 0) {
and(CLSR, 0x20, local0)
}
}
Expand All @@ -72,7 +72,7 @@ Method(OUTX, 1)
*/
Method(OUTC, 1)
{
if (LEqual(Arg0, 0x0a)) {
if (Arg0 == 0x0a) {
OUTX(0x0d)
}
OUTX(Arg0)
Expand Down Expand Up @@ -133,7 +133,7 @@ Method(DBGD, 1)
Method(DBGO, 1)
{
/* DINI() */
if (LEqual(ObjectType(Arg0), 1)) {
if (ObjectType(Arg0) == 1) {
if (LGreater(Arg0, 0xffff)) {
DBGD(Arg0)
} else {
Expand All @@ -149,7 +149,7 @@ Method(DBGO, 1)
store(0, Local1)
while (One) {
store(GETC(BDBG, Local1), Local0)
if (LEqual(Local0, 0)) {
if (Local0 == 0) {
return (0)
}
OUTC(Local0)
Expand Down
22 changes: 11 additions & 11 deletions src/arch/x86/acpi_bert_storage.c
View file
Expand Up @@ -127,7 +127,7 @@ static acpi_generic_error_status_t *new_bert_status(void)
status = bert_allocate_storage(sizeof(*status));

if (!status) {
printk(BIOS_ERR, "Error: New BERT error entry would exceed available region\n");
printk(BIOS_ERR, "New BERT error entry would exceed available region\n");
return NULL;
}

Expand Down Expand Up @@ -159,13 +159,13 @@ static acpi_hest_generic_data_v300_t *new_generic_error_entry(
acpi_hest_generic_data_v300_t *entry;

if (bert_entry_count(status) == GENERIC_ERR_STS_ENTRY_COUNT_MAX) {
printk(BIOS_ERR, "Error: New BERT error would exceed maximum entries\n");
printk(BIOS_ERR, "New BERT error would exceed maximum entries\n");
return NULL;
}

entry = bert_allocate_storage(sizeof(*entry));
if (!entry) {
printk(BIOS_ERR, "Error: New BERT error entry would exceed available region\n");
printk(BIOS_ERR, "New BERT error entry would exceed available region\n");
return NULL;
}

Expand All @@ -191,15 +191,15 @@ static size_t sizeof_error_section(guid_t *guid)
return sizeof(cper_fw_err_rec_section_t);
/* else if ... sizeof(structures not yet defined) */

printk(BIOS_ERR, "Error: Requested size of unrecognized CPER GUID\n");
printk(BIOS_ERR, "Requested size of unrecognized CPER GUID\n");
return 0;
}

void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size)
{
void *cl_data = bert_allocate_storage(cl_size);
if (!cl_data) {
printk(BIOS_ERR, "Error: Crashlog entry (size %zu) would exceed available region\n",
printk(BIOS_ERR, "Crashlog entry (size %zu) would exceed available region\n",
cl_size);
return NULL;
}
Expand Down Expand Up @@ -348,15 +348,15 @@ cper_ia32x64_context_t *new_cper_ia32x64_ctx(
return NULL;

if (cper_ia32x64_proc_num_ctxs(x86err) == I32X64SEC_VALID_CTXNUM_MAX) {
printk(BIOS_ERR, "Error: New IA32X64 %s context entry would exceed max allowable contexts\n",
printk(BIOS_ERR, "New IA32X64 %s context entry would exceed max allowable contexts\n",
ctx_names[type]);
return NULL;
}

size = cper_ia32x64_ctx_sz_bytype(type, num);
ctx = bert_allocate_storage(size);
if (!ctx) {
printk(BIOS_ERR, "Error: New IA32X64 %s context entry would exceed available region\n",
printk(BIOS_ERR, "New IA32X64 %s context entry would exceed available region\n",
ctx_names[type]);
return NULL;
}
Expand Down Expand Up @@ -402,14 +402,14 @@ cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check(
return NULL;

if (cper_ia32x64_proc_num_chks(x86err) == I32X64SEC_VALID_ERRNUM_MAX) {
printk(BIOS_ERR, "Error: New IA32X64 %s check entry would exceed max allowable errors\n",
printk(BIOS_ERR, "New IA32X64 %s check entry would exceed max allowable errors\n",
check_names[type]);
return NULL;
}

check = bert_allocate_storage(sizeof(*check));
if (!check) {
printk(BIOS_ERR, "Error: New IA32X64 %s check entry would exceed available region\n",
printk(BIOS_ERR, "New IA32X64 %s check entry would exceed available region\n",
check_names[type]);
return NULL;
}
Expand Down Expand Up @@ -518,7 +518,7 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid)
size += sizeof_error_section(guid);

if (size > bert_storage_remaining()) {
printk(BIOS_ERR, "Error: Not enough BERT region space to add event for type %s\n",
printk(BIOS_ERR, "Not enough BERT region space to add event for type %s\n",
generic_error_name(guid));
return NULL;
}
Expand Down Expand Up @@ -571,7 +571,7 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
*/
__weak void bert_reserved_region(void **start, size_t *size)
{
printk(BIOS_ERR, "Error: %s not implemented. BERT region generation disabled\n",
printk(BIOS_ERR, "%s not implemented. BERT region generation disabled\n",
__func__);
*start = NULL;
*size = 0;
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/id.S
View file
Expand Up @@ -11,7 +11,7 @@ vendor:
part:
.asciz CONFIG_MAINBOARD_PART_NUMBER

#if ENV_X86_64
#if ENV_X86_64 || defined(__clang__)
.long 0xffffffff - ver + 1 /* Reverse offset to the version */
.long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */
.long 0xffffffff - part + 1 /* Reverse offset to the part number */
Expand Down
8 changes: 8 additions & 0 deletions src/arch/x86/include/arch/hpet.h
View file
@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef ARCH_X86_HPET_H
#define ARCH_X86_HPET_H

#define HPET_BASE_ADDRESS 0xfed00000

#endif /* ARCH_X86_HPET_H */
11 changes: 5 additions & 6 deletions src/arch/x86/tables.c
View file
Expand Up @@ -36,7 +36,7 @@ static unsigned long write_pirq_table(unsigned long rom_table_end)
// much space it's going to need.
if (new_high_table_pointer > (high_table_pointer
+ MAX_PIRQ_TABLE_SIZE))
printk(BIOS_ERR, "ERROR: Increase PIRQ size.\n");
printk(BIOS_ERR, "Increase PIRQ size.\n");
printk(BIOS_DEBUG, "PIRQ table: %ld bytes.\n",
new_high_table_pointer - high_table_pointer);
}
Expand Down Expand Up @@ -64,7 +64,7 @@ static unsigned long write_mptable(unsigned long rom_table_end)
// much space it's going to need.
if (new_high_table_pointer > (high_table_pointer
+ MAX_MP_TABLE_SIZE))
printk(BIOS_ERR, "ERROR: Increase MP table size.\n");
printk(BIOS_ERR, "Increase MP table size.\n");

printk(BIOS_DEBUG, "MP table: %ld bytes.\n",
new_high_table_pointer - high_table_pointer);
Expand Down Expand Up @@ -102,7 +102,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
new_high_table_pointer = write_acpi_tables(high_table_pointer);
if (new_high_table_pointer > (high_table_pointer
+ max_acpi_size))
printk(BIOS_ERR, "ERROR: Increase ACPI size\n");
printk(BIOS_ERR, "Increase ACPI size\n");
printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n",
new_high_table_pointer - high_table_pointer);

Expand All @@ -127,8 +127,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
writes longest size available. */
memcpy(low_rsdp, high_rsdp, sizeof(acpi_rsdp_t));
} else {
printk(BIOS_ERR,
"ERROR: Didn't find RSDP in high table.\n");
printk(BIOS_ERR, "Didn't find RSDP in high table.\n");
}
rom_table_end = ALIGN_UP(rom_table_end + sizeof(acpi_rsdp_t), 16);
} else {
Expand Down Expand Up @@ -159,7 +158,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)

if (new_high_table_pointer > (high_table_pointer
+ MAX_SMBIOS_SIZE))
printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n");
printk(BIOS_ERR, "Increase SMBIOS size\n");
printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n",
new_high_table_pointer - high_table_pointer);
} else {
Expand Down
4 changes: 3 additions & 1 deletion src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
View file
Expand Up @@ -80,6 +80,7 @@
#define CBMEM_ID_FSP_LOGO 0x4c4f474f
#define CBMEM_ID_SMM_COMBUFFER 0x53534d32
#define CBMEM_ID_TYPE_C_INFO 0x54595045
#define CBMEM_ID_MEM_CHIP_INFO 0x5048434D

#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
Expand Down Expand Up @@ -154,5 +155,6 @@
{ CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \
{ CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \
{ CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \
{ CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}
{ CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\
{ CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"}
#endif /* _CBMEM_ID_H_ */
4 changes: 4 additions & 0 deletions src/commonlib/bsd/include/commonlib/bsd/compiler.h
View file
Expand Up @@ -35,6 +35,10 @@
#define __always_inline inline __attribute__((always_inline))
#endif

#ifndef __fallthrough
#define __fallthrough __attribute__((__fallthrough__))
#endif

/* This evaluates to the type of the first expression, unless that is constant
in which case it evaluates to the type of the second. This is useful when
assigning macro parameters to temporary variables, because that would
Expand Down
60 changes: 60 additions & 0 deletions src/commonlib/include/commonlib/loglevel.h
View file
Expand Up @@ -157,4 +157,64 @@
#define BIOS_NEVER 9
/** @} */

#ifndef __ASSEMBLER__

/*
* When printing logs, lines should be printed with the following prefixes in
* front of them according to the BIOS_LOG_PREFIX_PATTERN printf() pattern.
*/
#define BIOS_LOG_PREFIX_PATTERN "[%.5s] "
#define BIOS_LOG_PREFIX_MAX_LEVEL BIOS_SPEW
static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
/* Note: These strings are *not* null-terminated to save space. */
[BIOS_EMERG] = "EMERG",
[BIOS_ALERT] = "ALERT",
[BIOS_CRIT] = "CRIT ",
[BIOS_ERR] = "ERROR",
[BIOS_WARNING] = "WARN ",
[BIOS_NOTICE] = "NOTE ",
[BIOS_INFO] = "INFO ",
[BIOS_DEBUG] = "DEBUG",
[BIOS_SPEW] = "SPEW ",
};

/*
* When printing to terminals supporting ANSI escape sequences, the following
* escape sequences can be printed to highlight the respective log levels
* according to the BIOS_LOG_ESCAPE_PATTERN printf() pattern. At the end of a
* line, highlighting should be reset with the BIOS_LOG_ESCAPE_RESET seqence.
*
* The escape sequences used here set flags with the following meanings:
* 1 = bold, 4 = underlined, 5 = blinking, 7 = inverted
*/
#define BIOS_LOG_ESCAPE_PATTERN "\x1b[%sm"
#define BIOS_LOG_ESCAPE_RESET "\x1b[0m"
static const char bios_log_escape[BIOS_LOG_PREFIX_MAX_LEVEL + 1][8] = {
[BIOS_EMERG] = "1;4;5;7",
[BIOS_ALERT] = "1;4;7",
[BIOS_CRIT] = "1;7",
[BIOS_ERR] = "7",
[BIOS_WARNING] = "1;4",
[BIOS_NOTICE] = "1",
[BIOS_INFO] = "0",
[BIOS_DEBUG] = "0",
[BIOS_SPEW] = "0",
};

/*
* When storing console logs somewhere for later retrieval, log level prefixes
* and escape sequences should not be stored raw to preserve space. Instead, a
* non-printable control character marker is inserted into the log to indicate
* the log level. Decoders reading this character should translate it back into
* the respective escape sequence and prefix. If a decoder doesn't support this
* feature, the non-printable character should usually be harmless.
*/
#define BIOS_LOG_MARKER_START 0x10
#define BIOS_LOG_MARKER_END (BIOS_LOG_MARKER_START + BIOS_LOG_PREFIX_MAX_LEVEL)
#define BIOS_LOG_IS_MARKER(c) ((c) >= BIOS_LOG_MARKER_START && (c) <= BIOS_LOG_MARKER_END)
#define BIOS_LOG_LEVEL_TO_MARKER(level) (BIOS_LOG_MARKER_START + (level))
#define BIOS_LOG_MARKER_TO_LEVEL(c) ((c) - BIOS_LOG_MARKER_START)

#endif /* __ASSEMBLER__ */

#endif /* LOGLEVEL_H */
4 changes: 2 additions & 2 deletions src/commonlib/storage/sd_mmc.h
View file
Expand Up @@ -71,7 +71,7 @@ int sd_set_partition(struct storage_media *media,
if (CONFIG(SDHC_TRACE)) \
printk(BIOS_DEBUG, format); \
} while (0)
#define sdhc_error(format...) printk(BIOS_ERR, "ERROR: " format)
#define sdhc_error(format...) printk(BIOS_ERR, format)

/* Card/device debug functions */
#define sd_mmc_debug(format...) \
Expand All @@ -84,6 +84,6 @@ int sd_set_partition(struct storage_media *media,
if (CONFIG(SD_MMC_TRACE)) \
printk(BIOS_DEBUG, format); \
} while (0)
#define sd_mmc_error(format...) printk(BIOS_ERR, "ERROR: " format)
#define sd_mmc_error(format...) printk(BIOS_ERR, format)

#endif /* __COMMONLIB_STORAGE_SD_MMC_H__ */
20 changes: 19 additions & 1 deletion src/console/Kconfig
View file
Expand Up @@ -47,7 +47,7 @@ config FIXED_UART_FOR_CONSOLE
specific UART has to be used (e.g. when the platform code
performs dangerous configurations).

if CONSOLE_SERIAL
if CONSOLE_SERIAL || CONSOLE_CBMEM_DUMP_TO_UART

comment "I/O mapped, 8250-compatible"
depends on DRIVERS_UART_8250IO
Expand Down Expand Up @@ -395,6 +395,24 @@ config DEFAULT_CONSOLE_LOGLEVEL

endif

config CONSOLE_USE_LOGLEVEL_PREFIX
bool "Use loglevel prefix to indicate line loglevel"
default y
help
When enabled, if the code contains a:
`printk(BIOS_DEBUG, "This is a debug message!\n")`,
it will show up as:
`[DEBUG] This is a debug message!`

config CONSOLE_USE_ANSI_ESCAPES
bool "Use ANSI escape sequences for console highlighting"
default y
help
If enabled, certain consoles (e.g. UART) that are meant to be read on
a terminal will use ANSI escape sequences (like `ESC [1m`) to
highlight lines based on their log level. Disable this if your
terminal does not support ANSI escape sequences.

config NO_POST
bool "Don't show any POST codes"
default n
Expand Down
27 changes: 18 additions & 9 deletions src/console/console.c
View file
Expand Up @@ -11,6 +11,8 @@
#include <console/flash.h>
#include <console/system76_ec.h>

/* Note: when adding a new console, make sure you update the definition of
HAS_ONLY_FAST_CONSOLES in <console.h>! */
void console_hw_init(void)
{
__cbmemc_init();
Expand All @@ -25,28 +27,35 @@ void console_hw_init(void)
__system76_ec_init();
}

void console_tx_byte(unsigned char byte)
void console_interactive_tx_byte(unsigned char byte, void *data_unused)
{
__cbmemc_tx_byte(byte);
__spkmodem_tx_byte(byte);
__qemu_debugcon_tx_byte(byte);

/* Some consoles want newline conversion
* to keep terminals happy.
*/
if (byte == '\n') {
/* Some consoles want newline conversion to keep terminals happy. */
__uart_tx_byte('\r');
__usb_tx_byte('\r');
}

__spkmodem_tx_byte(byte);
__qemu_debugcon_tx_byte(byte);
__uart_tx_byte(byte);
__ne2k_tx_byte(byte);
__usb_tx_byte(byte);
__spiconsole_tx_byte(byte);
__flashconsole_tx_byte(byte);
__system76_ec_tx_byte(byte);
}

void console_stored_tx_byte(unsigned char byte, void *data_unused)
{
__flashconsole_tx_byte(byte);
__cbmemc_tx_byte(byte);
}

void console_tx_byte(unsigned char byte)
{
console_interactive_tx_byte(byte, NULL);
console_stored_tx_byte(byte, NULL);
}

void console_tx_flush(void)
{
__uart_tx_flush();
Expand Down
2 changes: 1 addition & 1 deletion src/console/post.c
View file
Expand Up @@ -19,7 +19,7 @@ void post_code(uint8_t value)
arch_post_code(value);

if (CONFIG(CONSOLE_POST))
printk(BIOS_EMERG, "POST: 0x%02x\n", value);
printk(BIOS_INFO, "POST: 0x%02x\n", value);

mainboard_post(value);
}
Expand Down
78 changes: 66 additions & 12 deletions src/console/printk.c
View file
Expand Up @@ -59,37 +59,91 @@ void do_putchar(unsigned char byte)
console_time_stop();
}

static void wrap_putchar(unsigned char byte, void *data)
union log_state {
void *as_ptr;
struct {
uint8_t level;
uint8_t speed;
};
};

#define LOG_FAST(state) (HAS_ONLY_FAST_CONSOLES || ((state).speed == CONSOLE_LOG_FAST))

static void wrap_interactive_printf(const char *fmt, ...)
{
console_tx_byte(byte);
va_list args;
va_start(args, fmt);
vtxprintf(console_interactive_tx_byte, fmt, args, NULL);
va_end(args);
}

static void line_start(union log_state state)
{
if (state.level > BIOS_LOG_PREFIX_MAX_LEVEL)
return;

/* Stored consoles just get a single control char marker to save space. If we are in
LOG_FAST mode, just write the marker to CBMC and exit -- the rest of this function
implements the LOG_ALL case. */
unsigned char marker = BIOS_LOG_LEVEL_TO_MARKER(state.level);
if (LOG_FAST(state)) {
__cbmemc_tx_byte(marker);
return;
}
console_stored_tx_byte(marker, NULL);

/* Interactive consoles get a `[DEBUG] ` style readable prefix,
and potentially an escape sequence for highlighting. */
if (CONFIG(CONSOLE_USE_ANSI_ESCAPES))
wrap_interactive_printf(BIOS_LOG_ESCAPE_PATTERN, bios_log_escape[state.level]);
if (CONFIG(CONSOLE_USE_LOGLEVEL_PREFIX))
wrap_interactive_printf(BIOS_LOG_PREFIX_PATTERN, bios_log_prefix[state.level]);
}

static void wrap_putchar_cbmemc(unsigned char byte, void *data)
static void line_end(union log_state state)
{
__cbmemc_tx_byte(byte);
if (CONFIG(CONSOLE_USE_ANSI_ESCAPES) && !LOG_FAST(state))
wrap_interactive_printf(BIOS_LOG_ESCAPE_RESET);
}

static void wrap_putchar(unsigned char byte, void *data)
{
union log_state state = { .as_ptr = data };
static bool line_started = false;

if (byte == '\n') {
line_end(state);
line_started = false;
} else if (!line_started) {
line_start(state);
line_started = true;
}

if (LOG_FAST(state))
__cbmemc_tx_byte(byte);
else
console_tx_byte(byte);
}

int vprintk(int msg_level, const char *fmt, va_list args)
{
int i, log_this;
union log_state state = { .level = msg_level };
int i;

if (CONFIG(SQUELCH_EARLY_SMP) && ENV_ROMSTAGE_OR_BEFORE && !boot_cpu())
return 0;

log_this = console_log_level(msg_level);
if (log_this < CONSOLE_LOG_FAST)
state.speed = console_log_level(msg_level);
if (state.speed < CONSOLE_LOG_FAST)
return 0;

spin_lock(&console_lock);

console_time_run();

if (log_this == CONSOLE_LOG_FAST) {
i = vtxprintf(wrap_putchar_cbmemc, fmt, args, NULL);
} else {
i = vtxprintf(wrap_putchar, fmt, args, NULL);
i = vtxprintf(wrap_putchar, fmt, args, state.as_ptr);
if (LOG_FAST(state))
console_tx_flush();
}

console_time_stop();

Expand Down
3 changes: 2 additions & 1 deletion src/console/vtxprintf.c
View file
Expand Up @@ -244,14 +244,15 @@ int vtxprintf(void (*tx_byte)(unsigned char byte, void *data),

case 'X':
flags |= LARGE;
/* fall through */
__fallthrough;
case 'x':
base = 16;
break;

case 'd':
case 'i':
flags |= SIGN;
__fallthrough;
case 'u':
break;

Expand Down
1 change: 1 addition & 0 deletions src/cpu/Makefile.inc
View file
Expand Up @@ -7,6 +7,7 @@ subdirs-y += intel
subdirs-y += ti
subdirs-$(CONFIG_ARCH_X86) += x86
subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
subdirs-$(CONFIG_CPU_POWER9) += power9

$(eval $(call create_class_compiler,cpu_microcode,x86_32))
################################################################################
Expand Down
3 changes: 2 additions & 1 deletion src/cpu/amd/agesa/family14/fixme.c
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
Expand Down Expand Up @@ -28,7 +29,7 @@ void amd_initcpuio(void)
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Map the remaining PCI hole as posted MMIO */
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/agesa/family14/model_14_init.c
View file
Expand Up @@ -7,7 +7,6 @@
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <acpi/acpi.h>
Expand Down Expand Up @@ -57,9 +56,6 @@ static void model_14_init(struct device *dev)
/* zero the machine check error status registers */
mca_clear_status();

/* Enable the local CPU APICs */
setup_lapic();

#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/agesa/family15tn/Makefile.inc
View file
Expand Up @@ -9,4 +9,4 @@ ramstage-y += model_15_init.c
smm-y += udelay.c

subdirs-y += ../../mtrr
subdirs-y += ../../smm
subdirs-$(CONFIG_SMM_LEGACY_ASEG) += ../../smm
3 changes: 2 additions & 1 deletion src/cpu/amd/agesa/family15tn/fixme.c
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
Expand Down Expand Up @@ -28,7 +29,7 @@ void amd_initcpuio(void)
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Map the remaining PCI hole as posted MMIO */
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/agesa/family15tn/model_15_init.c
View file
Expand Up @@ -8,7 +8,6 @@
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <acpi/acpi.h>
Expand Down Expand Up @@ -59,9 +58,6 @@ static void model_15_init(struct device *dev)
/* zero the machine check error status registers */
mca_clear_status();

/* Enable the local CPU APICs */
setup_lapic();

#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

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