diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,16 +1,25 @@
-CONFIG_LOCALVERSION="v4.14.0.2"
+CONFIG_LOCALVERSION="v4.14.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_BOARD_PCENGINES_APU4=y
 CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_BOARD_PCENGINES_APU4=y
+CONFIG_BOTTOMIO_POSITION=0xD0000000
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_HUDSON_SATA_MODE=2
+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_POST_IO_PORT=0x80
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,16 +1,25 @@
-CONFIG_LOCALVERSION="v4.14.0.2"
+CONFIG_LOCALVERSION="v4.14.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_BOARD_PCENGINES_APU5=y
 CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_BOARD_PCENGINES_APU5=y
+CONFIG_BOTTOMIO_POSITION=0xD0000000
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_HUDSON_SATA_MODE=2
+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_POST_IO_PORT=0x80
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6
@@ -1,16 +1,25 @@
-CONFIG_LOCALVERSION="v4.14.0.2"
+CONFIG_LOCALVERSION="v4.14.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_BOARD_PCENGINES_APU6=y
 CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_BOARD_PCENGINES_APU6=y
+CONFIG_BOTTOMIO_POSITION=0xD0000000
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_HUDSON_SATA_MODE=2
+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_POST_IO_PORT=0x80
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi
@@ -8,6 +8,7 @@
 # + EM100Pro SPI console
 # + Debug options
 CONFIG_VENDOR_PORTWELL=y
+CONFIG_BOARD_PORTWELL_M107=y
 CONFIG_CONSOLE_POST=y
 # CONFIG_CONSOLE_SERIAL is not set
 CONFIG_ENABLE_BUILTIN_COM1=y

diff --git a/configs/config.up_squared.vboot_spi_flash_console b/configs/config.up_squared.vboot_spi_flash_console
@@ -1,3 +1,4 @@
 CONFIG_VENDOR_UP=y
+CONFIG_BOARD_UP_SQUARED=y
 CONFIG_VBOOT=y
 CONFIG_CONSOLE_SPI_FLASH=y
diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile
@@ -34,7 +34,7 @@ export KCONFIG_SPLITCONFIG	:= $(obj)/config
 export KCONFIG_TRISTATE		:= $(obj)/tristate.conf
 export KCONFIG_CONFIG		:= $(CURDIR)/.config
 export KCONFIG_NEGATIVES	:= 1
-export Kconfig			:= Kconfig
+export KBUILD_KCONFIG		:= Kconfig
 
 CONFIG_SHELL := sh
 KBUILD_DEFCONFIG := configs/defconfig
@@ -70,7 +70,7 @@ $(obj)/config.h:
 
 $(shell mkdir -p $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))
 
-include $(srck)/Makefile
+include $(srck)/Makefile.inc
 
 .PHONY: $(PHONY) prepare all real-all defaultbuild
 

diff --git a/payloads/external/FILO/Kconfig b/payloads/external/FILO/Kconfig
@@ -16,6 +16,34 @@ config FILO_MASTER
 
 endchoice
 
+config FILO_USE_AUTOBOOT
+	prompt "Use FILO's autoboot"
+	default n
+	bool
+	help
+	  Select this option to make FILO autoboot a command line after
+	  timeout. This disables the GRUB legacy like interface.
+
+config FILO_AUTOBOOT_FILE
+	string "Configure FILO's autoboot kernel filename and parameters"
+	depends on FILO_USE_AUTOBOOT
+	default "hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200"
+	help
+	  Examples:
+
+	  #AUTOBOOT_FILE = "hda1:/vmlinuz root=/dev/sda1 console=tty0 console=ttyS0,115200"
+	  #AUTOBOOT_FILE = "mem@0xfff80000"
+	  #AUTOBOOT_FILE = "hde1@0"
+	  #AUTOBOOT_FILE = "uda1:/vmlinuz.elf"
+	  #AUTOBOOT_FILE = "flashb@0x00400000,0x154a00 console=tty0 console=ttyS0,115200"
+
+config FILO_AUTOBOOT_DELAY
+	int "Time in seconds before booting"
+	depends on FILO_USE_AUTOBOOT
+	default 2
+	help
+	  Time in seconds before booting AUTOBOOT_FILE.
+
 config PAYLOAD_FILE
 	default "payloads/external/FILO/filo/build/filo.elf"
 

diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile
@@ -33,6 +33,13 @@ config: libpayload
 	#echo "CONFIG_VGAHOOKS=y" >> filo/.config
 	# This shows how to force a previously set .config option *off*
 	#echo "# CONFIG_SMBIOS is not set" >> filo/.config
+ifeq ($(CONFIG_FILO_USE_AUTOBOOT),y)
+	echo "# CONFIG_USE_GRUB is not set" >> filo/.config
+	echo "CONFIG_USE_AUTOBOOT=y" >> filo/.config
+	echo 'CONFIG_AUTOBOOT_FILE="$(CONFIG_FILO_AUTOBOOT_FILE)"' >> filo/.config
+	echo "CONFIG_AUTOBOOT_DELAY=$(CONFIG_FILO_AUTOBOOT_DELAY)" >> filo/.config
+endif
+
 	$(MAKE) -C filo oldconfig LIBCONFIG_PATH=../../../libpayload
 
 filo: config

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -222,7 +222,10 @@ filo:
 			CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
 			OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
 			CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \
-			CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE)
+			CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) \
+			CONFIG_FILO_USE_AUTOBOOT=$(CONFIG_FILO_USE_AUTOBOOT) \
+			CONFIG_FILO_AUTOBOOT_FILE=$(CONFIG_FILO_AUTOBOOT_FILE) \
+			CONFIG_FILO_AUTOBOOT_DELAY=$(CONFIG_FILO_AUTOBOOT_DELAY)
 
 payloads/external/FILO/filo/build/filo.elf: filo
 payloads/external/FILO/filo/.config: filo

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -104,22 +104,22 @@ config SEABIOS_BOOTORDER_FILE
 
 config SEABIOS_BOOTORDER_MAP_FILE
 	string "SeaBIOS bootorder_map file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map_apu5" if BOARD_PCENGINES_APU5
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map"
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_map_apu5" if BOARD_PCENGINES_APU5
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_map"
 	help
 	  Determine mapping of keystrokes to group of positions in bootorder
 
 config SEABIOS_BOOTORDER_DEF_FILE
 	string "SeaBIOS bootorder_def file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def_apu5" if BOARD_PCENGINES_APU5
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def"
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_def_apu5" if BOARD_PCENGINES_APU5
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_def"
 	help
 	  Determine default boot order and default values for runtime config
 	  options e.g. usben, pxen, etc.
 
 config SEABIOS_BOOTMENU_KEY_FILE
 	string "SeaBIOS boot-menu-key file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-key"
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/boot-menu-key"
 	help
 	  Add SeaBIOS boot-menu-key file. From wiki:
 	  "Controls which key activates the boot menu. The value stored is the
@@ -130,7 +130,7 @@ config SEABIOS_BOOTMENU_KEY_FILE
 
 config SEABIOS_BOOTMENU_WAIT_FILE
 	string "SeaBIOS boot-menu-wait file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-wait"
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/boot-menu-wait"
 	help
 	  Add SeaBIOS boot-menu-wait file. From wiki:
 	  "Amount of time (in milliseconds) to wait at the boot menu prompt
@@ -140,7 +140,7 @@ config SEABIOS_BOOTMENU_WAIT_FILE
 
 config SEABIOS_BOOTMENU_MESSAGE_FILE
 	string "SeaBIOS boot-menu-message file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-message"
+	default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/boot-menu-message"
 	help
 	  Customize the text boot menu message. From wiki:
 

diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
@@ -43,10 +43,10 @@ export objk := $(objutil)/lp_kconfig
 export KCONFIG_AUTOHEADER := $(obj)/config.h
 export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
 export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
-export KCONFIG_SPLITCONFIG := $(obj)/config
+export KCONFIG_SPLITCONFIG := $(obj)/config/
 export KCONFIG_TRISTATE := $(obj)/tristate.conf
 export KCONFIG_NEGATIVES := 1
-export Kconfig := Kconfig
+export KBUILD_KCONFIG := Kconfig
 export CONFIG_ := CONFIG_LP_
 
 # directory containing the toplevel Makefile.inc
@@ -88,7 +88,7 @@ endif
 
 # This include must come _before_ the pattern rules below!
 # Order _does_ matter for pattern rules.
-include $(srck)/Makefile
+include $(srck)/Makefile.inc
 
 include $(HAVE_DOTCONFIG)
 
@@ -202,7 +202,8 @@ endif
 .SECONDEXPANSION:
 
 $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG)
-	$(MAKE) oldconfig
+	$(MAKE) CONFIG_=CONFIG_LP_ olddefconfig
+	$(MAKE) CONFIG_=CONFIG_LP_ syncconfig
 
 # Add a new class of source/object files to the build system
 add-class= \

diff --git a/payloads/libpayload/Makefile.payload b/payloads/libpayload/Makefile.payload
@@ -119,6 +119,7 @@ $(obj)/%.S.o: %.S $(LIBPAYLOAD_CONFIG_H) $(DEFAULT_DEPS)
 
 LIBPAYLOAD_OPTS := obj="$(LIBPAYLOAD_OBJ)"
 LIBPAYLOAD_OPTS += DOTCONFIG="$(LIBPAYLOAD_DOTCONFIG)"
+LIBPAYLOAD_OPTS += CONFIG_=CONFIG_LP_
 LIBPAYLOAD_OPTS += $(if $(CCACHE),CONFIG_LP_CCACHE=y)
 
 defconfig: lp-defconfig

diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c b/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c
@@ -212,9 +212,8 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp)
 
 		if (serial_cur_pair != PAIR_NUMBER(attr)) {
 			short int fg, bg;
-			pair_content(PAIR_NUMBER(attr),
-				     &fg, &bg);
-			serial_set_color(fg, bg);
+			if (pair_content(PAIR_NUMBER(attr), &fg, &bg) == OK)
+				serial_set_color(fg, bg);
 			serial_cur_pair = PAIR_NUMBER(attr);
 		}
 

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
@@ -1501,6 +1501,21 @@ void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val)
 	acpigen_write_integer(val);
 }
 
+/*
+ * Generates ACPI code to check at runtime if an object named `namestring`
+ * exists, and leaves the If scope open to continue execute code when this
+ * is true. NOTE: Requires matching acpigen_write_if_end().
+ *
+ * If (CondRefOf (NAME))
+ */
+void acpigen_write_if_cond_ref_of(const char *namestring)
+{
+	acpigen_write_if();
+	acpigen_emit_ext_op(COND_REFOF_OP);
+	acpigen_emit_namestring(namestring);
+	acpigen_emit_byte(ZERO_OP); /* ignore COND_REFOF_OP destination */
+}
+
 /* Closes previously opened if statement and generates ACPI code for else statement. */
 void acpigen_write_else(void)
 {

diff --git a/src/arch/ppc64/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h
@@ -3,6 +3,6 @@
 #ifndef _BYTEORDER_H
 #define _BYTEORDER_H
 
-#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
 
 #endif /* _BYTEORDER_H */
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
@@ -6,30 +6,29 @@ config ARCH_X86
 	select RELOCATABLE_MODULES
 	select HAVE_ASAN_IN_RAMSTAGE
 
+if ARCH_X86
+
 # stage selectors for x86
 
 config ARCH_BOOTBLOCK_X86_32
 	bool
-	select ARCH_X86
 
 config ARCH_VERSTAGE_X86_32
 	bool
-	select ARCH_X86
 
 config ARCH_ROMSTAGE_X86_32
 	bool
-	select ARCH_X86
 
 config ARCH_POSTCAR_X86_32
 	bool
 	default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE
 
 config ARCH_RAMSTAGE_X86_32
 	bool
-	select ARCH_X86
 
 config ARCH_ALL_STAGES_X86_32
 	bool
+	default ARCH_ALL_STAGES_X86 && !ARCH_ALL_STAGES_X86_64
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
@@ -39,23 +38,19 @@ config ARCH_ALL_STAGES_X86_32
 
 config ARCH_BOOTBLOCK_X86_64
 	bool
-	select ARCH_X86
 
 config ARCH_VERSTAGE_X86_64
 	bool
-	select ARCH_X86
 
 config ARCH_ROMSTAGE_X86_64
 	bool
-	select ARCH_X86
 
 config ARCH_POSTCAR_X86_64
 	bool
 	default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE
 
 config ARCH_RAMSTAGE_X86_64
 	bool
-	select ARCH_X86
 
 config ARCH_ALL_STAGES_X86_64
 	bool
@@ -64,7 +59,27 @@ config ARCH_ALL_STAGES_X86_64
 	select ARCH_ROMSTAGE_X86_64
 	select ARCH_RAMSTAGE_X86_64
 
-if ARCH_X86
+config ARCH_ALL_STAGES_X86
+	bool
+	default y
+
+config HAVE_EXP_X86_64_SUPPORT
+	bool
+	help
+	  Enable experimental support to build and run coreboot in 64-bit mode.
+	  When selecting this option for a new platform, it is highly advisable
+	  to provide a config file for Jenkins to build-test the 64-bit option.
+
+config USE_EXP_X86_64_SUPPORT
+	bool "[EXPERIMENTAL] Run coreboot in long (64-bit) mode"
+	depends on HAVE_EXP_X86_64_SUPPORT
+	select ARCH_ALL_STAGES_X86_64
+	help
+	  When set, most of coreboot runs in long (64-bit) mode instead of the
+	  usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used
+	  irrespective of whether coreboot runs in 32-bit or 64-bit mode. This
+	  is an experimental option: do not enable unless one wants to test it
+	  and has the means to recover a system when coreboot fails to boot.
 
 config ARCH_X86_64_PGTBL_LOC
 	hex "x86_64 page table location in CBFS"
@@ -122,11 +137,15 @@ config RAMTOP
 # Traditionally BIOS region on SPI flash boot media was memory mapped right below
 # 4G and it was the last region in the IFD. This way translation between CPU
 # address space to flash address was trivial. However some IFDs on newer SoCs
-# have BIOS region sandwiched between descriptor and other regions. Turning off
-# this option enables soc code to provide custom mmap_boot.c which can be used to
-# implement complex translation.
+# have BIOS region sandwiched between descriptor and other regions. Turning on
+# X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows the
+# soc code to provide custom mmap_boot.c.
+config X86_CUSTOM_BOOTMEDIA
+	bool
+
 config X86_TOP4G_BOOTMEDIA_MAP
 	bool
+	depends on !X86_CUSTOM_BOOTMEDIA
 	default y
 
 # This is something you almost certainly don't want to mess with.

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
@@ -15,7 +15,7 @@
 	#define _STACK_TOP _ecar_stack
 #endif
 
-#ifdef __x86_64__
+#if ENV_X86_64
 .code64
 #else
 .code32
@@ -26,7 +26,7 @@
 _start:
 
 	/* Migrate GDT to this text segment */
-#ifdef __x86_64__
+#if ENV_X86_64
 	call	gdt_init64
 #else
 	call	gdt_init

diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c
@@ -21,14 +21,14 @@ int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size)
 
 void arch_prog_run(struct prog *prog)
 {
-#if ENV_RAMSTAGE && defined(__x86_64__)
+#if ENV_RAMSTAGE && ENV_X86_64
 	const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog));
 	const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog));
 
 	/* On x86 coreboot payloads expect to be called in protected mode */
 	protected_mode_jump(entry, arg);
 #else
-#ifdef __x86_64__
+#if ENV_X86_64
 	void (*doit)(void *arg);
 #else
 	/* Ensure the argument is pushed on the stack. */

diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S
@@ -5,7 +5,7 @@
 #include <cpu/x86/cr.h>
 
 
-#ifdef __x86_64__
+#if ENV_X86_64
 
 	/*
 	 * Functions to handle mode switches from long mode to protected

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
@@ -24,15 +24,15 @@ thread_stacks:
 #endif
 
 	.section ".text._start", "ax", @progbits
-#ifdef __x86_64__
+#if ENV_X86_64
 	.code64
 #else
 	.code32
 #endif
 	.globl _start
 _start:
 	cli
-#ifdef __x86_64__
+#if ENV_X86_64
 	movabs	$gdtaddr, %rax
 	lgdt	(%rax)
 #else
@@ -45,7 +45,7 @@ _start:
 	movl	%eax, %ss
 	movl	%eax, %fs
 	movl	%eax, %gs
-#ifdef __x86_64__
+#if ENV_X86_64
 	mov	$RAM_CODE_SEG64, %ecx
 	call	SetCodeSelector
 #endif
@@ -54,7 +54,7 @@ _start:
 
 	cld
 
-#ifdef	__x86_64__
+#if ENV_X86_64
 	mov	%rdi, %rax
 	movabs	%rax, _cbmem_top_ptr
 	movabs	$_stack, %rdi
@@ -117,7 +117,7 @@ _start:
 
 	.globl gdb_stub_breakpoint
 gdb_stub_breakpoint:
-#ifdef __x86_64__
+#if ENV_X86_64
 	pop	%rax	/* Return address */
 	pushfl
 	push	%cs
@@ -139,7 +139,7 @@ gdb_stub_breakpoint:
 
 gdtaddr:
 	.word	gdt_end - gdt - 1
-#ifdef __x86_64__
+#if ENV_X86_64
 	.quad	gdt
 #else
 	.long	gdt		/* we know the offset */
@@ -176,7 +176,7 @@ gdt:
 
 	/* selgdt 0x18, flat data segment */
 	.word	0xffff, 0x0000
-#ifdef __x86_64__
+#if ENV_X86_64
 	.byte	0x00, 0x92, 0xcf, 0x00
 #else
 	.byte	0x00, 0x93, 0xcf, 0x00
@@ -210,15 +210,15 @@ gdt:
 					* limit
 					*/
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	/* selgdt 0x48, flat x64 code segment */
 	.word	0xffff, 0x0000
 	.byte	0x00, 0x9b, 0xaf, 0x00
 #endif
 gdt_end:
 
 	.section ".text._start", "ax", @progbits
-#ifdef __x86_64__
+#if ENV_X86_64
 SetCodeSelector:
 	# save rsp because iret will align it to a 16 byte boundary
 	mov	%rsp, %rdx

diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
@@ -13,7 +13,7 @@
 #include <device/device.h>
 #include <smp/spinlock.h>
 
-#ifndef __x86_64__
+#if ENV_X86_32
 /* Standard macro to see if a specific flag is changeable */
 static inline int flag_is_changeable_p(uint32_t flag)
 {
@@ -136,7 +136,7 @@ static void identify_cpu(struct device *cpu)
 
 	vendor_name[0] = '\0'; /* Unset */
 
-#ifndef __x86_64__
+#if ENV_X86_32
 	/* Find the id and vendor_name */
 	if (!cpu_have_cpuid()) {
 		/* Its a 486 if we can modify the AC flag */

diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
@@ -2,7 +2,7 @@
 
 #include <cpu/cpu.h>
 
-#ifndef __x86_64__
+#if ENV_X86_32
 /* Standard macro to see if a specific flag is changeable */
 static inline int flag_is_changeable_p(uint32_t flag)
 {

diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
@@ -492,7 +492,7 @@ void x86_exception(struct eregs *info)
 	logical_processor = cpu_index();
 #endif
 	u8 *code;
-#ifdef __x86_64__
+#if ENV_X86_64
 #define MDUMP_SIZE 0x100
 	printk(BIOS_EMERG,
 		"CPU Index %d - APIC %d Unexpected Exception:\n"

diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
@@ -11,7 +11,7 @@ post_car_stack_top:
 .long	0
 .long	0
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 .code64
 .macro pop_eax_edx
 	pop	%rax
@@ -42,13 +42,13 @@ _start:
 	   is expected to be implemented in assembly. */
 
 	/* Migrate GDT to this text segment */
-#if defined(__x86_64__)
+#if ENV_X86_64
 	call	gdt_init64
 #else
 	call	gdt_init
 #endif
 
-#ifdef	__x86_64__
+#if ENV_X86_64
 	mov	%rdi, %rax
 	movabs %rax, _cbmem_top_ptr
 #else
@@ -61,7 +61,7 @@ _start:
 	cpuid
 	btl	$CPUID_FEATURE_CLFLUSH_BIT, %edx
 	jnc	skip_clflush
-#ifdef	__x86_64__
+#if ENV_X86_64
 	movabs	_cbmem_top_ptr, %rax
 	clflush	(%rax)
 #else
@@ -73,7 +73,7 @@ skip_clflush:
 	call	chipset_teardown_car
 
 	/* Enable caching if not already enabled. */
-#ifdef  __x86_64__
+#if ENV_X86_64
 	mov	%cr0, %rax
 	and     $(~(CR0_CD | CR0_NW)), %eax
 	mov	%rax, %cr0
@@ -115,7 +115,7 @@ skip_clflush:
 	/* Need to align stack to 16 bytes at the call instruction. Therefore
 	   account for the 1 push. */
 	andl	$0xfffffff0, %esp
-#if defined(__x86_64__)
+#if ENV_X86_64
 	mov	%rbp, %rdi
 #else
 	sub	$12, %esp

diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S
@@ -18,7 +18,7 @@ gdtptr:
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
 
-#ifdef __x86_64__
+#if ENV_X86_64
 .code64
 .section .init._gdt64_, "ax", @progbits
 	.globl gdt_init64

diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 	.section ".text._idt", "ax", @progbits
-#ifdef __x86_64__
+#if ENV_X86_64
 	.code64
 #else
 	.code32
@@ -109,7 +109,7 @@ vec19:
 
 .global int_hand
 int_hand:
-#ifdef __x86_64__
+#if ENV_X86_64
 	/* At this point, on x86-64, on the stack there is:
 	 *  0(%rsp) vector
 	 *  8(%rsp) error code

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
@@ -235,7 +235,7 @@ static inline struct cpu_info *cpu_info(void)
 {
 	struct cpu_info *ci;
 	__asm__(
-#ifdef __x86_64__
+#if ENV_X86_64
 		"and %%rsp,%0; "
 		"or  %2, %0 "
 #else

diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h
@@ -42,7 +42,7 @@
 		uint64_t r##A; \
 	} __packed
 
-#ifdef __ARCH_x86_64__
+#if ENV_X86_64
 struct eregs {
 	QUAD_DOWNTO8(a);
 	QUAD_DOWNTO8(c);

diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
@@ -3,6 +3,8 @@
 #ifndef ARCH_SMP_SPINLOCK_H
 #define ARCH_SMP_SPINLOCK_H
 
+#include <thread.h>
+
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
@@ -54,10 +56,16 @@ static __always_inline void spin_lock(spinlock_t *lock)
 	__asm__ __volatile__(
 		spin_lock_string
 		: "=m" (lock->lock) : : "memory");
+
+	/* Switching contexts while holding a spinlock will lead to deadlocks */
+	thread_coop_disable();
+
 }
 
 static __always_inline void spin_unlock(spinlock_t *lock)
 {
+	thread_coop_enable();
+
 	__asm__ __volatile__(
 		spin_unlock_string
 		: "=m" (lock->lock) : : "memory");

diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c
@@ -15,7 +15,7 @@ void *memcpy(void *dest, const void *src, size_t n)
 #endif
 
 	asm volatile(
-#ifdef __x86_64__
+#if ENV_X86_64
 		"rep ; movsd\n\t"
 		"mov %4,%%rcx\n\t"
 #else

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S
@@ -6,15 +6,22 @@
 /* CR0 bits */
 #define PE		(1 << 0)
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	.code64
 #else
 	.code32
 #endif
 
 	.globl __wakeup
 __wakeup:
-#ifdef __x86_64__
+#if ENV_X86_64
+	/* When called in x86_64 mode, the resume vector is in %rdi
+	 * instead of the stack, save it in 4(%rsp) for the 32-bit code.
+	 * It's OK to overwrite the return address at (%rsp) because this
+	 * function doesn't return.
+	 */
+	mov	%edi, 4(%rsp)
+
 	xor	%rax,%rax
 	mov	%ss, %ax
 	push	%rax

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -54,6 +54,8 @@ enum timestamp_id {
 	TS_END_POSTCAR = 101,
 	TS_DELAY_START = 110,
 	TS_DELAY_END = 111,
+	TS_READ_UCODE_START = 112,
+	TS_READ_UCODE_END = 113,
 
 	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
 	TS_START_COPYVER = 501,
@@ -77,6 +79,8 @@ enum timestamp_id {
 	TS_START_COPYVPD = 550,
 	TS_END_COPYVPD_RO = 551,
 	TS_END_COPYVPD_RW = 552,
+	TS_START_TPM_ENABLE_UPDATE = 553,
+	TS_END_TPM_ENABLE_UPDATE = 554,
 
 	/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
 	TS_AGESA_INIT_RESET_START = 900,
@@ -107,6 +111,8 @@ enum timestamp_id {
 	/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
 	TS_ME_INFORM_DRAM_WAIT = 940,
 	TS_ME_INFORM_DRAM_DONE = 941,
+	TS_ME_BEFORE_END_OF_POST = 942,
+	TS_ME_AFTER_END_OF_POST = 943,
 
 	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
 	TS_FSP_MEMORY_INIT_START = 950,
@@ -187,6 +193,8 @@ static const struct timestamp_id_to_name {
 	{ TS_SELFBOOT_JUMP,	"selfboot jump" },
 	{ TS_DELAY_START,	"Forced delay start" },
 	{ TS_DELAY_END,		"Forced delay end" },
+	{ TS_READ_UCODE_START,	"started reading uCode" },
+	{ TS_READ_UCODE_END,	"finished reading uCode" },
 
 	{ TS_START_COPYVER,	"starting to load verstage" },
 	{ TS_END_COPYVER,	"finished loading verstage" },
@@ -202,6 +210,8 @@ static const struct timestamp_id_to_name {
 	{ TS_END_TPMPCR,	"finished TPM PCR extend" },
 	{ TS_START_TPMLOCK,	"starting locking TPM" },
 	{ TS_END_TPMLOCK,	"finished locking TPM" },
+	{ TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" },
+	{ TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" },
 
 	{ TS_START_COPYVPD,	"starting to load Chrome OS VPD" },
 	{ TS_END_COPYVPD_RO,	"finished loading Chrome OS VPD (RO)" },
@@ -255,6 +265,8 @@ static const struct timestamp_id_to_name {
 	/* Intel ME related timestamps */
 	{ TS_ME_INFORM_DRAM_WAIT,	"waiting for ME acknowledgement of raminit"},
 	{ TS_ME_INFORM_DRAM_DONE,	"finished waiting for ME response"},
+	{ TS_ME_BEFORE_END_OF_POST,	"before sending EOP to ME"},
+	{ TS_ME_AFTER_END_OF_POST,	"after sending EOP to ME"},
 
 	/* FSP related timestamps */
 	{ TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
@@ -178,6 +178,7 @@ config CPU_MICROCODE_CBFS_NONE
 config AGESA_UCODE_EXPERIMENTAL
 	bool "Add microcode patch for AMD fam16h (EXPERIMENTAL)"
 	help
+	  Include the microcode with Spectre mitigations for AMD fam16h.
 
 endchoice
 

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
@@ -6,7 +6,7 @@ config CPU_AMD_AGESA
 	default y if CPU_AMD_AGESA_FAMILY15_TN
 	default y if CPU_AMD_AGESA_FAMILY16_KB
 	default n
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select DRIVERS_AMD_PI
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC

diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -15,9 +15,7 @@
 
 static void model_14_init(struct device *dev)
 {
-	u8 i;
 	msr_t msr;
-	int num_banks;
 	int msrno;
 #if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
@@ -59,12 +57,7 @@ static void model_14_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+	mca_clear_status();
 
 	/* Enable the local CPU APICs */
 	setup_lapic();

diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -18,9 +18,7 @@ static void model_15_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Model 15 Init.\n");
 
-	u8 i;
 	msr_t msr;
-	int num_banks;
 	int msrno;
 	unsigned int cpu_idx;
 #if CONFIG(LOGICAL_CPUS)
@@ -58,12 +56,7 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+	mca_clear_status();
 
 	/* Enable the local CPU APICs */
 	setup_lapic();

diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -17,9 +17,7 @@ static void model_16_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Model 16 Init.\n");
 
-	u8 i;
 	msr_t msr;
-	int num_banks;
 	int msrno;
 #if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
@@ -56,12 +54,7 @@ static void model_16_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+	mca_clear_status();
 
 	/* Enable the local CPU APICs */
 	setup_lapic();

diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -20,9 +20,7 @@ static void model_16_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Model 16 Init.\n");
 
-	u8 i;
 	msr_t msr;
-	int num_banks;
 	u32 siblings;
 
 	/*
@@ -41,12 +39,7 @@ static void model_16_init(struct device *dev)
 	x86_mtrr_check();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+	mca_clear_status();
 
 	/* Enable the local CPU APICs */
 	setup_lapic();

diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c
@@ -78,7 +78,7 @@ static void apply_microcode_patch(const struct microcode *m)
 	printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n",
 		m->patch_id);
 
-	msr = rdmsr(MSR_PATCH_LEVEL);
+	msr = rdmsr(IA32_BIOS_SIGN_ID);
 	new_patch_id = msr.lo;
 
 	if (new_patch_id == m->patch_id)

diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
@@ -4,7 +4,7 @@ config CPU_AMD_PI
 	bool
 	default y if CPU_AMD_PI_00730F01
 	default n
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select DRIVERS_AMD_PI
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC

diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc
@@ -16,5 +16,11 @@ rom_mtrr_base:
 car_mtrr_mask:
 .uintptr_t _car_mtrr_mask
 
+car_mtrr_size:
+.uintptr_t _car_mtrr_size
+
 car_mtrr_start:
 .uintptr_t _car_mtrr_start
+
+xip_mtrr_mask:
+.uintptr_t _xip_mtrr_mask
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -7,6 +7,8 @@
 .section .init
 .global bootblock_pre_c_entry
 
+#include <cpu/intel/car/cache_as_ram_symbols.inc>
+
 .code32
 _cache_as_ram_setup:
 
@@ -92,7 +94,7 @@ addrsize_set_high:
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRR_PHYS_MASK(0)), %ecx
 	rdmsr
-	movl	$_car_mtrr_mask, %eax
+	movl	car_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
@@ -119,8 +121,8 @@ addrsize_set_high:
 	/* Clear the cache memory region. This will also fill up the cache. */
 	cld
 	xorl	%eax, %eax
-	movl	$_car_mtrr_start, %edi
-	movl	$_car_mtrr_size, %ecx
+	movl	car_mtrr_start, %edi
+	movl	car_mtrr_size, %ecx
 	shr	$2, %ecx
 	rep	stosl
 
@@ -134,12 +136,12 @@ addrsize_set_high:
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
 	movl	$_program, %eax
-	andl	$_xip_mtrr_mask, %eax
+	andl	xip_mtrr_mask, %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	rdmsr
-	movl	$_xip_mtrr_mask, %eax
+	movl	xip_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
@@ -157,13 +159,24 @@ addrsize_set_high:
 	andl	$0xfffffff0, %esp
 	subl	$4, %esp
 
+#if ENV_X86_64
+
+	#include <cpu/x86/64bit/entry64.inc>
+
+	movd	%mm2, %rdi
+	shlq	$32, %rdi
+	movd	%mm1, %rsi
+	or	%rsi, %rdi
+	movd	%mm0, %rsi
+#else
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
 	pushl	%eax	/* BIST */
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
 	pushl	%eax	/* tsc[31:0] */
+#endif
 
 before_c_entry:
 	post_code(0x29)

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -11,6 +11,8 @@
 .section .init
 .global bootblock_pre_c_entry
 
+#include <cpu/intel/car/cache_as_ram_symbols.inc>
+
 .code32
 _cache_as_ram_setup:
 
@@ -212,15 +214,15 @@ sipi_complete:
 
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
-	movl	$_car_mtrr_start, %eax
+	movl	car_mtrr_start, %eax
 	orl	$MTRR_TYPE_WRBACK, %eax
 	xorl	%edx, %edx
 	wrmsr
 
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRR_PHYS_MASK(0)), %ecx
 	rdmsr
-	movl	$_car_mtrr_mask, %eax
+	movl	car_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
@@ -272,12 +274,12 @@ no_msr_11e:
 	/* Cache the whole rom to fetch microcode updates */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
-	movl	$_rom_mtrr_base, %eax
+	movl	rom_mtrr_base, %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	rdmsr
-	movl	$_rom_mtrr_mask, %eax
+	movl	rom_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
@@ -324,12 +326,12 @@ cache_rom:
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
 	movl	$_program, %eax
-	andl	$_xip_mtrr_mask, %eax
+	andl	xip_mtrr_mask, %eax
 	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	rdmsr
-	movl	$_xip_mtrr_mask, %eax
+	movl	xip_mtrr_mask, %eax
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
@@ -357,13 +359,24 @@ fill_cache:
 	andl	$0xfffffff0, %esp
 	subl	$4, %esp
 
+#if ENV_X86_64
+	#include <cpu/x86/64bit/entry64.inc>
+
+	movd	%mm2, %rdi
+	shlq	$32, %rdi	/* BIST */
+	movd	%mm1, %rsi
+	or	%rsi, %rdi	/* tsc[63:32] */
+	movd	%mm0, %rsi	/* tsc[31:0] */
+
+#else
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
 	pushl	%eax	/* BIST */
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
 	pushl	%eax	/* tsc[31:0] */
+#endif
 
 before_c_entry:
 	post_code(0x2f)

diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc
@@ -21,7 +21,7 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 
 ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
 
-$(call add_intermediate, add_mcu_fit, set_fit_ptr)
+$(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
 	@printf "    UPDATE-FIT Microcode\n"
 	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
 
@@ -32,7 +32,7 @@ $(call add_intermediate, set_ts_fit_ptr, $(IFITTOOL))
 	@printf "    UPDATE-FIT Top Swap: set FIT pointer to table\n"
 	$(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT $(TS_OPTIONS)
 
-$(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr)
+$(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr $(IFITTOOL))
 	@printf "    UPDATE-FIT Top Swap: Microcode\n"
 ifneq ($(FIT_ENTRY),)
 	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT

diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
@@ -6,7 +6,7 @@ if CPU_INTEL_HASWELL
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX
 	select SSE2

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
@@ -520,22 +520,17 @@ static void configure_mca(void)
 {
 	msr_t msr;
 	int i;
-	int num_banks;
-
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & 0xff;
+	const unsigned int num_banks = mca_get_bank_count();
 
 	/* Enable all error reporting */
 	msr.lo = msr.hi = ~0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_CTL + (i * 4), msr);
+		wrmsr(IA32_MC_CTL(i), msr);
 
-	msr.lo = msr.hi = 0;
 	/* TODO(adurbin): This should only be done on a cold boot. Also, some
 	 * of these banks are core vs package scope. For now every CPU clears
 	 * every bank. */
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+	mca_clear_status();
 }
 
 /* All CPUs including BSP will run the following function. */

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
@@ -136,9 +136,9 @@ static struct ext_sig_table *ucode_get_ext_sig_table(const struct microcode *uco
 	/* header + ucode data blob size */
 	u32 size = ucode->data_size + sizeof(struct microcode);
 
-	size_t ext_tbl_len = ucode->total_size - size;
+	ssize_t ext_tbl_len = ucode->total_size - size;
 
-	if (ext_tbl_len < sizeof(struct ext_sig_table))
+	if (ext_tbl_len < (ssize_t)sizeof(struct ext_sig_table))
 		return NULL;
 
 	ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size);

diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
@@ -1,6 +1,6 @@
 config CPU_INTEL_MODEL_1067X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
@@ -1,6 +1,6 @@
 config CPU_INTEL_MODEL_106CX
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
@@ -5,7 +5,8 @@ if CPU_INTEL_MODEL_2065X
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32
+	select HAVE_EXP_X86_64_SUPPORT
+	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select SSE2
 	select UDELAY_TSC

diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -73,23 +73,13 @@ static void set_max_ratio(void)
 	       ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK);
 }
 
-static void configure_mca(void)
-{
-	msr_t msr;
-	int i;
-
-	msr.lo = msr.hi = 0;
-	/* This should only be done on a cold boot */
-	for (i = 0; i < 7; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-}
-
 static void model_2065x_init(struct device *cpu)
 {
 	char processor_name[49];
 
 	/* Clear out pending MCEs */
-	configure_mca();
+	/* This should only be done on a cold boot */
+	mca_clear_status();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);

diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
@@ -3,16 +3,11 @@ config CPU_INTEL_MODEL_206AX
 
 if CPU_INTEL_MODEL_206AX
 
-config ARCH_EXP_X86_64
-	bool "Experimental 64bit support"
-	depends on USE_NATIVE_RAMINIT
-	default n
-
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-	select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64
-	select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64
+	select ARCH_X86
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
+	select HAVE_EXP_X86_64_SUPPORT if USE_NATIVE_RAMINIT
 	select MMX
 	select SSE2
 	select UDELAY_TSC

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -297,21 +297,6 @@ unsigned int smbios_processor_external_clock(void)
 	return SANDYBRIDGE_BCLK;
 }
 
-static void configure_mca(void)
-{
-	msr_t msr;
-	int i;
-	int num_banks;
-
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & 0xff;
-
-	msr.lo = msr.hi = 0;
-	/* This should only be done on a cold boot */
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-}
-
 static void model_206ax_report(void)
 {
 	static const char *const mode[] = {"NOT ", ""};
@@ -343,7 +328,8 @@ static void model_206ax_init(struct device *cpu)
 {
 
 	/* Clear out pending MCEs */
-	configure_mca();
+	/* This should only be done on a cold boot */
+	mca_clear_status();
 
 	/* Print infos */
 	model_206ax_report();

diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig
@@ -1,4 +1,4 @@
 config CPU_INTEL_MODEL_65X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig
@@ -1,4 +1,4 @@
 config CPU_INTEL_MODEL_67X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig
@@ -2,5 +2,5 @@
 
 config CPU_INTEL_MODEL_68X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig
@@ -1,4 +1,4 @@
 config CPU_INTEL_MODEL_6BX
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
@@ -1,6 +1,6 @@
 config CPU_INTEL_MODEL_6EX
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
@@ -1,6 +1,6 @@
 config CPU_INTEL_MODEL_6FX
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
@@ -1,4 +1,4 @@
 config CPU_INTEL_MODEL_6XX
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
@@ -1,6 +1,6 @@
 config CPU_INTEL_MODEL_F2X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select SMM_ASEG
 	select CPU_INTEL_COMMON
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
@@ -1,5 +1,5 @@
 config CPU_INTEL_MODEL_F3X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
@@ -1,4 +1,4 @@
 config CPU_INTEL_MODEL_F4X
 	bool
-	select ARCH_ALL_STAGES_X86_32
+	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
@@ -2,6 +2,8 @@
 
 config CPU_QEMU_X86
 	bool
+	select ARCH_X86
+	select HAVE_EXP_X86_64_SUPPORT
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
@@ -48,13 +50,7 @@ config MAX_CPUS
 	default 32 if SMM_TSEG
 	default 4
 
-config CPU_QEMU_X86_64
-	bool "Experimental 64bit support"
-	select ARCH_ALL_STAGES_X86_64
+config HEAP_SIZE
+	default 0x8000
 
-config CPU_QEMU_X86_32
-	bool
-	default n if CPU_QEMU_X86_64
-	default y
-	select ARCH_ALL_STAGES_X86_32
 endif
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -83,7 +83,7 @@ pages_done:
 #include <cpu/x86/64bit/entry64.inc>
 
 	/* Restore the BIST result and timestamps. */
-#if defined(__x86_64__)
+#if ENV_X86_64
 	movd	%mm2, %rdi
 	shlq	$32, %rdi
 	movd	%mm1, %rsi

diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc
@@ -9,7 +9,7 @@
  * Clobbers: eax, ecx, edx
  */
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 	.code32
 #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
 #error pagetables must be 4KiB aligned!

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -38,7 +38,7 @@ static int  lowmem_backup_size;
 static inline void setup_secondary_gdt(void)
 {
 	u16 *gdt_limit;
-#ifdef __x86_64__
+#if ENV_X86_64
 	u64 *gdt_base;
 #else
 	u32 *gdt_base;

diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
@@ -214,7 +214,7 @@ load_msr:
 	mov	%eax, %cr4
 #endif
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	/* entry64.inc preserves ebx. */
 #include <cpu/x86/64bit/entry64.inc>
 

diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
@@ -185,7 +185,7 @@ apicid_end:
 	/* Align stack to 16 bytes. Another 32 bytes are pushed below. */
 	andl	$0xfffffff0, %esp
 
-#ifdef __x86_64__
+#if ENV_X86_64
 	mov	%ecx, %edi
 	/* Backup IA32_EFER. Preserves ebx. */
 	movl	$(IA32_EFER), %ecx
@@ -204,7 +204,7 @@ apicid_end:
 	 *   struct arg = { c_handler_params, cpu_num, smm_runtime, canary };
 	 *   c_handler(&arg)
 	 */
-#ifdef __x86_64__
+#if ENV_X86_64
 	push	%rbx /* uintptr_t *canary */
 	push	%rcx /* size_t cpu */
 

diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
@@ -43,7 +43,7 @@
 
 #define SMM_HANDLER_OFFSET 0x0000
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 .bss
 ia32efer_backup_eax:
 .long 0
@@ -166,7 +166,7 @@ untampered_lapic:
 	addl	$SMM_STACK_SIZE, %ebx
 	movl	%ebx, %esp
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 	/* Backup IA32_EFER. Preserves ebx. */
 	movl	$(IA32_EFER), %ecx
 	rdmsr
@@ -180,7 +180,7 @@ untampered_lapic:
 	/* Call C handler */
 	call	smi_handler
 
-#if defined(__x86_64__)
+#if ENV_X86_64
 	/*
 	 * The only reason to go back to protected mode is that RSM doesn't restore
 	 * MSR registers and MSR IA32_EFER was modified by entering long mode.

diff --git a/src/device/device_const.c b/src/device/device_const.c
@@ -157,12 +157,6 @@ static int path_eq(const struct device_path *path1,
 	case DEVICE_PATH_MMIO:
 		equal = (path1->mmio.addr == path2->mmio.addr);
 		break;
-	case DEVICE_PATH_ESPI:
-		equal = (path1->espi.addr == path2->espi.addr);
-		break;
-	case DEVICE_PATH_LPC:
-		equal = (path1->lpc.addr == path2->lpc.addr);
-		break;
 	case DEVICE_PATH_GPIO:
 		equal = (path1->gpio.id == path2->gpio.id);
 		break;

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -218,14 +218,6 @@ const char *dev_path(const struct device *dev)
 			snprintf(buffer, sizeof(buffer), "MMIO: %08lx",
 				 dev->path.mmio.addr);
 			break;
-		case DEVICE_PATH_ESPI:
-			snprintf(buffer, sizeof(buffer), "ESPI: %08lx",
-				 dev->path.espi.addr);
-			break;
-		case DEVICE_PATH_LPC:
-			snprintf(buffer, sizeof(buffer), "LPC: %08lx",
-				 dev->path.lpc.addr);
-			break;
 		case DEVICE_PATH_GPIO:
 			snprintf(buffer, sizeof(buffer), "GPIO: %d", dev->path.gpio.id);
 			break;
@@ -450,7 +442,7 @@ static resource_t align_down(resource_t val, unsigned long gran)
  * @param resource The resource whose limit is desired.
  * @return The end.
  */
-resource_t resource_end(struct resource *resource)
+resource_t resource_end(const struct resource *resource)
 {
 	resource_t base, end;
 
@@ -476,7 +468,7 @@ resource_t resource_end(struct resource *resource)
  * @param resource The resource whose maximum is desired.
  * @return The maximum.
  */
-resource_t resource_max(struct resource *resource)
+resource_t resource_max(const struct resource *resource)
 {
 	resource_t max;
 
@@ -491,7 +483,7 @@ resource_t resource_max(struct resource *resource)
  * @param resource The resource type to decode.
  * @return TODO.
  */
-const char *resource_type(struct resource *resource)
+const char *resource_type(const struct resource *resource)
 {
 	static char buffer[RESOURCE_TYPE_MAX];
 	snprintf(buffer, sizeof(buffer), "%s%s%s%s",
@@ -513,7 +505,7 @@ const char *resource_type(struct resource *resource)
  * @param resource The resource that was just stored.
  * @param comment TODO
  */
-void report_resource_stored(struct device *dev, struct resource *resource,
+void report_resource_stored(struct device *dev, const struct resource *resource,
 			    const char *comment)
 {
 	char buf[10];
@@ -870,8 +862,8 @@ void mmconf_resource(struct device *dev, unsigned long index)
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
-	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR "
-			"0x%08lx-0x%08lx.\n", (unsigned long)(resource->base),
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+			(unsigned long)(resource->base),
 			(unsigned long)(resource->base + resource->size));
 }
 

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
@@ -149,8 +149,7 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index)
 	 */
 	if (moving == 0) {
 		if (value != 0) {
-			printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
-			       "read-only ignoring it\n",
+			printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
 			       dev_path(dev), index, value);
 		}
 		resource->flags = 0;
@@ -234,8 +233,7 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index)
 		resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
 	} else {
 		if (value != 0) {
-			printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
-			       "read-only ignoring it\n",
+			printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
 			       dev_path(dev), index, value);
 		}
 		resource->flags = 0;
@@ -512,8 +510,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			   we can treat it like an empty resource. */
 			resource->size = 0;
 		} else {
-			printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
-			       "assigned\n", dev_path(dev), resource->index,
+			printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
+			       dev_path(dev), resource->index,
 			       resource_type(resource), resource->size);
 			return;
 		}
@@ -980,9 +978,9 @@ static void set_pci_ops(struct device *dev)
 	default:
 bad:
 		if (dev->enabled) {
-			printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
-			       "header type %02x, ignoring.\n", dev_path(dev),
-			       dev->vendor, dev->device,
+			printk(BIOS_ERR,
+			       "%s [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n",
+			       dev_path(dev), dev->vendor, dev->device,
 			       dev->class >> 8, dev->hdr_type);
 		}
 	}
@@ -1107,8 +1105,9 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus,
 		if ((id == 0xffffffff) || (id == 0x00000000) ||
 		    (id == 0x0000ffff) || (id == 0xffff0000)) {
 			if (dev->enabled) {
-				printk(BIOS_INFO, "PCI: Static device %s not "
-				       "found, disabling it.\n", dev_path(dev));
+				printk(BIOS_INFO,
+				       "PCI: Static device %s not found, disabling it.\n",
+				       dev_path(dev));
 				dev->enabled = 0;
 			}
 			return dev;
@@ -1633,13 +1632,10 @@ void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4])
 
 		printk(BIOS_DEBUG, "Assigning IRQ %d to %s\n", irq, dev_path(dev));
 
-		pci_write_config8(dev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]);
+		pci_write_config8(dev, PCI_INTERRUPT_LINE, irq);
 
-#if CONFIG(PC80_SYSTEM)
 		/* Change to level triggered. */
-		i8259_configure_irq_trigger(pIntAtoD[line - 1],
-					    IRQ_LEVEL_TRIGGERED);
-#endif
+		i8259_configure_irq_trigger(irq, IRQ_LEVEL_TRIGGERED);
 	}
 }
 

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
@@ -6,6 +6,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <stdio.h>
 #include <string.h>
 #include <cbfs.h>
 #include <cbmem.h>
@@ -15,6 +16,24 @@
 void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; }
 u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
 
+static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
+{
+	char name[17] = "pciXXXX,XXXX.rom";
+
+	snprintf(name, sizeof(name), "pci%04hx,%04hx.rom", vendor, device);
+
+	return cbfs_map(name, NULL);
+}
+
+static void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev)
+{
+	char name[20] = "pciXXXX,XXXX,XX.rom";
+
+	snprintf(name, sizeof(name), "pci%04hx,%04hx,%02hhx.rom", vendor, device, rev);
+
+	return cbfs_map(name, NULL);
+}
+
 struct rom_header *pci_rom_probe(const struct device *dev)
 {
 	struct rom_header *rom_header = NULL;
@@ -49,21 +68,15 @@ struct rom_header *pci_rom_probe(const struct device *dev)
 	if (rom_header) {
 		printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
 		       dev_path(dev), rom_header);
-	} else if (!CONFIG(ON_DEVICE_ROM_LOAD)) {
-		printk(BIOS_DEBUG, "PCI Option ROM loading disabled for %s\n",
-		       dev_path(dev));
-		return NULL;
-	} else {
+	} else if (CONFIG(ON_DEVICE_ROM_LOAD)) {
 		uintptr_t rom_address;
 
 		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
 
 		if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
-#if CONFIG(CPU_QEMU_X86)
-			if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
+			if (CONFIG(CPU_QEMU_X86) && (dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
 				rom_address = 0xc0000;
 			else
-#endif
 				return NULL;
 		} else {
 			/* Enable expansion ROM address decoding. */
@@ -76,16 +89,20 @@ struct rom_header *pci_rom_probe(const struct device *dev)
 		printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n",
 		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
+	} else {
+		printk(BIOS_DEBUG, "PCI Option ROM loading disabled for %s\n",
+		       dev_path(dev));
+		return NULL;
 	}
 
-	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "
-	       "INIT size 0x%04x, data ptr 0x%04x\n",
+	printk(BIOS_SPEW,
+	       "PCI expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
 	       le32_to_cpu(rom_header->signature),
 	       rom_header->size * 512, le32_to_cpu(rom_header->data));
 
 	if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
-		printk(BIOS_ERR, "Incorrect expansion ROM header "
-		       "signature %04x\n", le32_to_cpu(rom_header->signature));
+		printk(BIOS_ERR, "Incorrect expansion ROM header signature %04x\n",
+		       le32_to_cpu(rom_header->signature));
 		return NULL;
 	}
 
@@ -97,13 +114,13 @@ struct rom_header *pci_rom_probe(const struct device *dev)
 	if ((dev->vendor != rom_data->vendor
 	    || dev->device != rom_data->device)
 	    && (vendev == mapped_vendev)) {
-		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
-		       "device ID %04x\n", dev->vendor, dev->device);
+		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, device ID %04x\n",
+		       dev->vendor, dev->device);
 		return NULL;
 	}
 
-	printk(BIOS_SPEW, "PCI ROM image, Class Code %04x%02x, "
-	       "Code Type %02x\n", rom_data->class_hi, rom_data->class_lo,
+	printk(BIOS_SPEW, "PCI ROM image, Class Code %04x%02x, Code Type %02x\n",
+	       rom_data->class_hi, rom_data->class_lo,
 	       rom_data->type);
 
 	if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
@@ -152,17 +169,17 @@ struct rom_header *pci_rom_load(struct device *dev,
 		if (dev != vga_pri) return NULL; /* Only one VGA supported. */
 #endif
 		if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) {
-			printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to "
-			       "0x%x, 0x%x bytes\n", rom_header,
-			       PCI_VGA_RAM_IMAGE_START, rom_size);
+			printk(BIOS_DEBUG,
+			       "Copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n",
+			       rom_header, PCI_VGA_RAM_IMAGE_START, rom_size);
 			memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header,
 			       rom_size);
 		}
 		return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START);
 	}
 
-	printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x "
-	       "bytes\n", rom_header, pci_ram_image_start, rom_size);
+	printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n",
+	       rom_header, pci_ram_image_start, rom_size);
 
 	memcpy(pci_ram_image_start, rom_header, rom_size);
 	pci_ram_image_start += rom_size;

diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c
@@ -670,7 +670,7 @@ void allocate_resources(const struct device *root)
 		post_log_path(child);
 
 		/* Pass 1 - Gather requirements. */
-		printk(BIOS_INFO, "==== Resource allocator: %s - Pass 1 (gathering requirements) ===\n",
+		printk(BIOS_INFO, "=== Resource allocator: %s - Pass 1 (gathering requirements) ===\n",
 		       dev_path(child));
 		compute_domain_resources(child);
 

diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <stdint.h>
 #include <string.h>
@@ -97,7 +98,7 @@ void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func)
 {
 	int i;
 
-	task->apic_id = (u8) (cpuid_ebx(1) >> 24);
+	task->apic_id = (u8)initial_lapicid();
 	task->func = func;
 	task->function_name = undefined;
 

diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
@@ -6,6 +6,7 @@
 #include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <cpu/x86/lapic.h>
 #include <halt.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
@@ -35,7 +36,7 @@ static void romstage_main(void)
 	struct postcar_frame pcf;
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
-	u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24);
+	unsigned int initial_apic_id = initial_lapicid();
 	int cbmem_initted = 0;
 
 	fill_sysinfo(cb);
@@ -49,7 +50,7 @@ static void romstage_main(void)
 		console_init();
 	}
 
-	printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n",
+	printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n",
 		initial_apic_id, cpuid_eax(1));
 
 	set_ap_entry_ptr(ap_romstage_main);

diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
@@ -593,8 +593,6 @@ static inline u8 *elog_flash_offset_to_address(void)
  */
 int elog_smbios_write_type15(unsigned long *current, int handle)
 {
-	struct smbios_type15 *t = (struct smbios_type15 *)*current;
-	int len = sizeof(struct smbios_type15);
 	uintptr_t log_address;
 
 	size_t elog_size = region_device_sz(&elog_state.nv_dev);
@@ -614,10 +612,9 @@ int elog_smbios_write_type15(unsigned long *current, int handle)
 		return 0;
 	}
 
-	memset(t, 0, len);
-	t->type = SMBIOS_EVENT_LOG;
-	t->length = len - 2;
-	t->handle = handle;
+	struct smbios_type15 *t = smbios_carve_table(*current, SMBIOS_EVENT_LOG,
+						     sizeof(*t), handle);
+
 	t->area_length = elog_size - 1;
 	t->header_offset = 0;
 	t->data_offset = sizeof(struct elog_header);
@@ -629,6 +626,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle)
 	t->log_type_descriptors = 0;
 	t->log_type_descriptor_length = 2;
 
+	const int len = smbios_full_table_len(&t->header, t->eos);
 	*current += len;
 	return len;
 }

diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h
@@ -12,6 +12,9 @@
 	{.source = DPTF_##src, .temp = (tmp), .type = DPTF_CRITICAL_##typ}
 #define TEMP_PCT(t, p) {.temp = (t), .fan_pct = (p)}
 
+/* Total number of OEM variables */
+#define DPTF_OEM_VARIABLE_COUNT		6
+
 struct drivers_intel_dptf_config {
 	struct {
 		struct dptf_active_policy active[DPTF_MAX_ACTIVE_POLICIES];
@@ -51,6 +54,11 @@ struct drivers_intel_dptf_config {
 			const char *desc;
 		} tsr[DPTF_MAX_TSR];
 	} options;
+
+	/* OEM variables */
+	struct {
+		uint32_t oem_variables[DPTF_OEM_VARIABLE_COUNT];
+	} oem_data;
 };
 
 #endif /* _DRIVERS_INTEL_DPTF_CHIP_H_ */
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
@@ -117,6 +117,62 @@ static void write_fan(const struct drivers_intel_dptf_config *config,
 	acpigen_pop_len(); /* Device */
 }
 
+/* \_SB.DPTF */
+static void write_imok(void)
+{
+	acpigen_write_method("IMOK", 1);
+	/* Return (Arg0) */
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_byte(ARG0_OP);
+	acpigen_write_method_end();
+}
+/* \_SB.DPTF */
+static void write_oem_variables(const struct drivers_intel_dptf_config *config)
+{
+	int i;
+
+	acpigen_write_name("ODVX");
+	acpigen_write_package(DPTF_OEM_VARIABLE_COUNT);
+	for (i = 0; i < DPTF_OEM_VARIABLE_COUNT; i++)
+		acpigen_write_dword(config->oem_data.oem_variables[i]);
+	acpigen_write_package_end();
+
+	/*
+	 * Method (ODUP, 2)
+	 * Arg0 = Index of ODVX to update
+	 * Arg1 = Value to place in ODVX[Arg0]
+	 */
+	acpigen_write_method_serialized("ODUP", 2);
+	/* ODVX[Arg0] = Arg1 */
+	acpigen_write_store();
+	acpigen_emit_byte(ARG1_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring("ODVX");
+	acpigen_emit_byte(ARG0_OP);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+	acpigen_write_method_end();
+
+	/*
+	 * Method (ODGT, 1)
+	 * Arg0 = Index of ODVX to get
+	 */
+	acpigen_write_method_serialized("ODGT", 1);
+	 /* Return (ODVX[Arg0]) */
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_byte(DEREF_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring("ODVX");
+	acpigen_emit_byte(ARG0_OP);
+	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
+	acpigen_write_method_end();
+
+	/* Method (ODVP) { Return (ODVX) } */
+	acpigen_write_method_serialized("ODVP", 0);
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_namestring("ODVX");
+	acpigen_write_method_end();
+}
+
 /* \_SB.DPTF.xxxx */
 static void write_generic_devices(const struct drivers_intel_dptf_config *config,
 				  const struct dptf_platform_info *platform_info)
@@ -169,6 +225,8 @@ static void write_device_definitions(const struct device *dev)
 	write_tcpu(parent, config);
 	write_open_dptf_device(dev, platform_info);
 	write_fan(config, platform_info);
+	write_oem_variables(config);
+	write_imok();
 	write_generic_devices(config, platform_info);
 
 	acpigen_pop_len(); /* DPTF Device (write_open_dptf_device) */

diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c
@@ -6,14 +6,7 @@
 void *cbmem_top_chipset(void)
 {
 	struct range_entry tolum;
-	uint8_t *tolum_base;
 
 	fsp_find_bootloader_tolum(&tolum);
-	tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum);
-
-	/*
-	 * The TOLUM range may have other memory regions (such as APEI
-	 * BERT region on top of CBMEM (IMD root and IMD small) region.
-	 */
-	return tolum_base + cbmem_overhead_size();
+	return (void *)(uintptr_t)range_entry_end(&tolum);
 }
diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c
@@ -43,16 +43,9 @@ void fsp_verify_memory_init_hobs(void)
 		die("Space between FSP reserved region and BIOS TOLUM!\n");
 	}
 
-	if (!CONFIG(ACPI_BERT) && range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
+	if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
 		printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
 			range_entry_end(&tolum), cbmem_top());
 		die("Space between cbmem_top and BIOS TOLUM!\n");
 	}
-
-	if (CONFIG(ACPI_BERT) &&
-		range_entry_end(&tolum) != (uintptr_t)cbmem_top() + CONFIG_ACPI_BERT_SIZE) {
-		printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top + 0x%x: BERT\n",
-			range_entry_end(&tolum), cbmem_top(), CONFIG_ACPI_BERT_SIZE);
-		die("Space between cbmem_top and APEI BERT!\n");
-	}
 }
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
@@ -266,21 +266,6 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 	/* Reserve enough memory under TOLUD to save CBMEM header */
 	arch_upd->BootLoaderTolumSize = cbmem_overhead_size();
 
-	/*
-	 * If ACPI APEI BERT region size is defined, reserve memory for it.
-	 * +------------------------+ range_entry_top(tolum)
-	 * | Other reserved regions |
-	 * | APEI BERT region       |
-	 * +------------------------+ cbmem_top()
-	 * | CBMEM IMD ROOT         |
-	 * | CBMEM IMD SMALL        |
-	 * +------------------------+ range_entry_base(tolum), TOLUM
-	 * | CBMEM FSP MEMORY       |
-	 * | Other CBMEM regions... |
-	 */
-	if (CONFIG(ACPI_BERT))
-		arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE;
-
 	/* Fill common settings on behalf of chipset. */
 	if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
 					memmap) != CB_SUCCESS)

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -126,7 +126,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	else
 		status = silicon_init(upd);
 
-	printk(BIOS_ERR, "FSPS returned %x\n", status);
+	printk(BIOS_INFO, "FSPS returned %x\n", status);
 
 	timestamp_add_now(TS_FSP_SILICON_INIT_END);
 	post_code(POST_FSP_SILICON_EXIT);

diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
@@ -102,6 +102,15 @@ config GFX_GMA_PANEL_1_ON_LVDS
 	default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE
 	default n
 
+config INTEL_GMA_OPREGION_2_0
+	bool
+	default n if INTEL_GMA_OPREGION_2_1
+	default y
+
+config INTEL_GMA_OPREGION_2_1
+	bool
+	default n
+
 if GFX_GMA
 
 config GFX_GMA_DYN_CPU

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
@@ -255,6 +255,15 @@ static enum cb_err find_vbt_location(struct region_device *rdev)
 	return CB_ERR;
 }
 
+/* Function to get the IGD Opregion version */
+static struct opregion_version opregion_get_version(void)
+{
+	if (CONFIG(INTEL_GMA_OPREGION_2_1))
+		return (struct opregion_version) { .major = 2, .minor = 1 };
+
+	return (struct opregion_version) { .major = 2, .minor = 0 };
+}
+
 /*
  * Function to determine if we need to use extended VBT region to pass
  * VBT pointer. If VBT size > 6 KiB then we need to use extended VBT
@@ -265,13 +274,45 @@ static inline bool is_ext_vbt_required(igd_opregion_t *opregion, optionrom_vbt_t
 	return (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1));
 }
 
+/* Function to determine if the VBT uses a relative address */
+static inline bool uses_relative_vbt_addr(opregion_header_t *header)
+{
+	if (header->opver.major > 2)
+		return true;
+
+	return header->opver.major >= 2 && header->opver.minor >= 1;
+}
+
+/*
+ * Copy extended VBT at the end of opregion and fill rvda and rvds
+ * values correctly for the opregion.
+ */
+static void opregion_add_ext_vbt(igd_opregion_t *opregion, uint8_t *ext_vbt,
+				optionrom_vbt_t *vbt)
+{
+
+	opregion_header_t *header = &opregion->header;
+	/* Copy VBT into extended VBT region (at offset 8 KiB) */
+	memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
+
+	/* Fill RVDA value with relative address of the opregion buffer in case of
+	IGD Opregion version 2.1+ and physical address otherwise */
+
+	if (uses_relative_vbt_addr(header))
+		opregion->mailbox3.rvda = sizeof(*opregion);
+	else
+		opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
+
+	opregion->mailbox3.rvds = vbt->hdr_vbt_size;
+}
+
 /* Initialize IGD OpRegion, called from ACPI code and OS drivers */
 enum cb_err intel_gma_init_igd_opregion(void)
 {
 	igd_opregion_t *opregion;
 	struct region_device rdev;
 	optionrom_vbt_t *vbt = NULL;
-	optionrom_vbt_t *ext_vbt = NULL;
+	size_t opregion_size = sizeof(igd_opregion_t);
 
 	if (acpi_is_wakeup_s3())
 		return intel_gma_restore_opregion();
@@ -291,32 +332,30 @@ enum cb_err intel_gma_init_igd_opregion(void)
 		return CB_ERR;
 	}
 
-	opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
+	if (is_ext_vbt_required(opregion, vbt))
+		opregion_size += vbt->hdr_vbt_size;
+
+	opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, opregion_size);
 	if (!opregion) {
 		printk(BIOS_ERR, "GMA: Failed to add IGD OpRegion to CBMEM.\n");
 		return CB_ERR;
 	}
 
-	memset(opregion, 0, sizeof(igd_opregion_t));
+	memset(opregion, 0, opregion_size);
 
 	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
 		sizeof(opregion->header.signature));
 	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
 					ARRAY_SIZE(vbt->coreblock_biosbuild));
-	/* Extended VBT support */
-	if (is_ext_vbt_required(opregion, vbt)) {
-		ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size);
 
-		if (ext_vbt == NULL) {
-			printk(BIOS_ERR,
-			       "GMA: Unable to add Ext VBT to cbmem!\n");
-			rdev_munmap(&rdev, vbt);
-			return CB_ERR;
-		}
+	/* Get the opregion version information */
+	opregion->header.opver = opregion_get_version();
 
-		memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
-		opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
-		opregion->mailbox3.rvds = vbt->hdr_vbt_size;
+	/* Extended VBT support */
+	if (is_ext_vbt_required(opregion, vbt)) {
+		/* Place extended VBT just after opregion */
+		uint8_t *ext_vbt = (uint8_t *)opregion + sizeof(*opregion);
+		opregion_add_ext_vbt(opregion, ext_vbt, vbt);
 	} else {
 		/* Raw VBT size which can fit in gvd1 */
 		memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
@@ -327,26 +366,6 @@ enum cb_err intel_gma_init_igd_opregion(void)
 	/* 8kb */
 	opregion->header.size = sizeof(igd_opregion_t) / 1024;
 
-	/*
-	 * Left-shift version field to accommodate Intel Windows driver quirk
-	 * when not using a VBIOS.
-	 * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver.
-	 *
-	 * Tested on: (platform, GPU, windows driver version)
-	 * samsung/stumpy (SNB, GT2, 9.17.10.4459)
-	 * google/link (IVB, GT2, 15.33.4653)
-	 * google/wolf (HSW, GT1, 15.40.36.4703)
-	 * google/panther (HSW, GT2, 15.40.36.4703)
-	 * google/rikku (BDW, GT1, 15.40.36.4703)
-	 * google/lulu (BDW, GT2, 15.40.36.4703)
-	 * google/chell (SKL-Y, GT2, 15.45.21.4821)
-	 * google/sentry (SKL-U, GT1, 15.45.21.4821)
-	 * purism/librem13v2 (SKL-U, GT2, 15.45.21.4821)
-	 *
-	 * No adverse effects when using VBIOS or booting Linux.
-	 */
-	opregion->header.version = IGD_OPREGION_VERSION << 24;
-
 	// FIXME We just assume we're mobile for now
 	opregion->header.mailboxes = MAILBOXES_MOBILE;
 

diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
@@ -17,7 +17,12 @@
 typedef struct {
 	u8	signature[16];	    /* Offset 0    OpRegion signature */
 	u32	size;		    /* Offset 16   OpRegion size */
-	u32	version;	    /* Offset 20   OpRegion structure version */
+	struct opregion_version {
+		u8 rsvd;
+		u8 revision;
+		u8 minor;
+		u8 major;
+	} opver;		    /* Offset 20   OpRegion version structure */
 	u8	sbios_version[32];  /* Offset 24   System BIOS build version */
 	u8	vbios_version[16];  /* Offset 56   Video BIOS build version */
 	u8	driver_version[16]; /* Offset 72   Graphic drvr build version */
@@ -29,7 +34,6 @@ typedef struct {
 } __packed opregion_header_t;
 
 #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
-#define IGD_OPREGION_VERSION  2
 
 #define IGD_MBOX1	(1 << 0)
 #define IGD_MBOX2	(1 << 1)
@@ -143,7 +147,8 @@ typedef struct {
 	u32	fdss;		/* Offset 178 FFS Display Size */
 	u32	stat;		/* Offset 182 State Indicator */
 	u64	rvda;		/* Offset 186 (Igd opregion offset 0x3BAh)
-				 *            Physical address of Raw VBT data
+				 *            Physical(2.0) or relative opregion
+				 *            (2.1+) address of Raw VBT data
 				 */
 	u32	rvds;		/* Offset 194 (Igd opregion offset 0x3C2h)
 				 *            Size of Raw VBT data

diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h
@@ -14,8 +14,8 @@ struct drivers_intel_usb4_retimer_config {
 	struct {
 		/* GPIO used to control power of retimer device */
 		struct acpi_gpio power_gpio;
-		/* _PLD setting */
-		struct acpi_pld_group group;
+		/* Type-C port associated with retimer */
+		DEVTREE_CONST struct device *typec_port;
 	} dfp[DFP_NUM_MAX];
 };
 

diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c
@@ -6,6 +6,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/path.h>
+#include <drivers/usb/acpi/chip.h>
 #include <gpio.h>
 #include <string.h>
 #include "chip.h"
@@ -336,9 +337,10 @@ static void usb4_retimer_write_dsm(uint8_t port, const char *uuid,
 static void usb4_retimer_fill_ssdt(const struct device *dev)
 {
 	struct drivers_intel_usb4_retimer_config *config = dev->chip_info;
+	const struct device *usb_device;
 	static char dfp[DEVICE_PATH_MAX];
 	struct acpi_pld pld;
-	uint8_t port;
+	uint8_t dfp_port, usb_port;
 
 	usb4_retimer_scope = acpi_device_scope(dev);
 	if (!usb4_retimer_scope || !config)
@@ -352,24 +354,31 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 	acpigen_write_ADR(0);
 	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 
-	for (port = 0; port < DFP_NUM_MAX; port++) {
-		if (!config->dfp[port].power_gpio.pin_count) {
-			printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n", __func__,
-			       port, dev_path(dev));
+	for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) {
+
+		if (!config->dfp[dfp_port].power_gpio.pin_count) {
+			printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n",
+				__func__, dfp_port, dev_path(dev));
 			continue;
 		}
 
+		usb_device = config->dfp[dfp_port].typec_port;
+		usb_port = usb_device->path.usb.port_id;
+
 		/* DFPx */
-		snprintf(dfp, sizeof(dfp), "DFP%1d", port);
+		snprintf(dfp, sizeof(dfp), "DFP%1d", usb_port);
 		acpigen_write_device(dfp);
 		/* _ADR part is for the lane adapter */
-		acpigen_write_ADR(port*2 + 1);
+		acpigen_write_ADR(dfp_port*2 + 1);
 
 		/* Fill _PLD with the same USB 3.x object on the Type-C connector */
-		acpi_pld_fill_usb(&pld, UPC_TYPE_PROPRIETARY, &config->dfp[port].group);
-		pld.shape = PLD_SHAPE_OVAL;
-		pld.visible = 1;
-		acpigen_write_pld(&pld);
+		if (CONFIG(DRIVERS_USB_ACPI)) {
+			if (usb_acpi_get_pld(usb_device, &pld))
+				acpigen_write_pld(&pld);
+			else
+				printk(BIOS_ERR, "Error retrieving PLD for USB Type-C %d\n",
+					usb_port);
+		}
 
 		/* Power online reference counter(_PWR) */
 		acpigen_write_name("PWR");
@@ -387,9 +396,9 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 		/* Return (Buffer (One) { 0x0 }) */
 		acpigen_write_return_singleton_buffer(0x0);
 		acpigen_pop_len();
-		usb4_retimer_write_dsm(port, INTEL_USB4_RETIMER_DSM_UUID,
+		usb4_retimer_write_dsm(usb_port, INTEL_USB4_RETIMER_DSM_UUID,
 			usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks),
-			(void *)&config->dfp[port].power_gpio);
+			(void *)&config->dfp[dfp_port].power_gpio);
 		/* Default case: Return (Buffer (One) { 0x0 }) */
 		acpigen_write_return_singleton_buffer(0x0);
 

diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c
@@ -486,7 +486,7 @@ static void update_mrc_cache_by_type(int type,
 
 	struct update_region_file_entry entries[] = {
 		[0] = {
-			.size = sizeof(struct mrc_metadata),
+			.size = sizeof(*new_md),
 			.data = new_md,
 		},
 		[1] = {
@@ -696,7 +696,7 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 		.data_checksum = compute_ip_checksum(data, size),
 	};
 	md.header_checksum =
-		compute_ip_checksum(&md, sizeof(struct mrc_metadata));
+		compute_ip_checksum(&md, sizeof(md));
 
 	if (CONFIG(MRC_STASH_TO_CBMEM)) {
 		/* Store data in cbmem for use in ramstage */

diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c
@@ -31,72 +31,84 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x4014,
 		.nr_sectors_shift		= 8,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},					/* also GD25Q80B */
 	{
 		/* GD25Q16 */
 		.id[0]				= 0x4015,
 		.nr_sectors_shift		= 9,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},					/* also GD25Q16B */
 	{
 		/* GD25Q32B */
 		.id[0]				= 0x4016,
 		.nr_sectors_shift		= 10,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},					/* also GD25Q32B */
 	{
 		/* GD25Q64 */
 		.id[0]				= 0x4017,
 		.nr_sectors_shift		= 11,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},					/* also GD25Q64B, GD25B64C */
 	{
 		/* GD25Q128 */
 		.id[0]				= 0x4018,
 		.nr_sectors_shift		= 12,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},					/* also GD25Q128B */
 	{
 		/* GD25VQ80C */
 		.id[0]				= 0x4214,
 		.nr_sectors_shift		= 8,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 	{
 		/* GD25VQ16C */
 		.id[0]				= 0x4215,
 		.nr_sectors_shift		= 9,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 	{
 		/* GD25LQ80 */
 		.id[0]				= 0x6014,
 		.nr_sectors_shift		= 8,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 	{
 		/* GD25LQ16 */
 		.id[0]				= 0x6015,
 		.nr_sectors_shift		= 9,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 	{
 		/* GD25LQ32 */
 		.id[0]				= 0x6016,
 		.nr_sectors_shift		= 10,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 	{
 		/* GD25LQ64C */
 		.id[0]				= 0x6017,
 		.nr_sectors_shift		= 11,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},					/* also GD25LB64C */
 	{
 		/* GD25LQ128 */
 		.id[0]				= 0x6018,
 		.nr_sectors_shift		= 12,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 };
 

diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
@@ -63,55 +63,75 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0] = 0x2415,
 		.nr_sectors_shift = 9,
 	},
+	/*
+	 * NOTE: C225xx JEDEC IDs are basically useless because Macronix keeps
+	 * reusing the same IDs for vastly different chips. 35E versions always
+	 * seem to support Dual I/O but not Dual Output, while 35F versions seem
+	 * to support both, so we only set Dual I/O here to improve our chances
+	 * of compatibility. Since Macronix makes it impossible to search all
+	 * different parts that it recklessly assigned the same IDs to, it's
+	 * hard to know if there may be parts that don't even support Dual I/O
+	 * with these IDs, though (or what we should do if there are).
+	 */
 	{
 		/* MX25L1635E */
 		.id[0] = 0x2515,
 		.nr_sectors_shift = 9,
+		.fast_read_dual_io_support = 1,
 	},
 	{
 		/* MX25U8032E */
 		.id[0] = 0x2534,
 		.nr_sectors_shift = 8,
+		.fast_read_dual_io_support = 1,
 	},
 	{
-		/* MX25U1635E */
+		/* MX25U1635E/MX25U1635F */
 		.id[0] = 0x2535,
 		.nr_sectors_shift = 9,
+		.fast_read_dual_io_support = 1,
 	},
 	{
-		/* MX25U3235E */
+		/* MX25U3235E/MX25U3235F */
 		.id[0] = 0x2536,
 		.nr_sectors_shift = 10,
+		.fast_read_dual_io_support = 1,
 	},
 	{
-		/* MX25U6435F */
+		/* MX25U6435E/MX25U6435F */
 		.id[0] = 0x2537,
 		.nr_sectors_shift = 11,
+		.fast_read_dual_io_support = 1,
 	},
 	{
 		/* MX25U12835F */
 		.id[0] = 0x2538,
 		.nr_sectors_shift = 12,
+		.fast_read_dual_io_support = 1,
 	},
 	{
 		/* MX25U25635F */
 		.id[0] = 0x2539,
 		.nr_sectors_shift = 13,
+		.fast_read_dual_io_support = 1,
 	},
 	{
-		/* MX25U51245G */
+		/* MX25U51235F */
 		.id[0] = 0x253a,
 		.nr_sectors_shift = 14,
+		.fast_read_dual_io_support = 1,
 	},
 	{
 		/* MX25L12855E */
 		.id[0] = 0x2618,
 		.nr_sectors_shift = 12,
+		.fast_read_dual_io_support = 1,
 	},
 	{
 		/* MX25L3235D/MX25L3225D/MX25L3236D/MX25L3237D */
 		.id[0] = 0x5e16,
 		.nr_sectors_shift = 10,
+		.fast_read_dual_io_support = 1,
 	},
 	{
 		/* MX25L6495F */

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
@@ -20,7 +20,7 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
 	cmd[3] = addr >> 0;
 }
 
-static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout,
+static int do_spi_flash_cmd(const struct spi_slave *spi, const u8 *dout,
 			    size_t bytes_out, void *din, size_t bytes_in)
 {
 	int ret;
@@ -51,8 +51,8 @@ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout,
 	return ret;
 }
 
-static int do_dual_read_cmd(const struct spi_slave *spi, const void *dout,
-			    size_t bytes_out, void *din, size_t bytes_in)
+static int do_dual_output_cmd(const struct spi_slave *spi, const u8 *dout,
+			      size_t bytes_out, void *din, size_t bytes_in)
 {
 	int ret;
 
@@ -79,6 +79,31 @@ static int do_dual_read_cmd(const struct spi_slave *spi, const void *dout,
 	return ret;
 }
 
+static int do_dual_io_cmd(const struct spi_slave *spi, const u8 *dout,
+			  size_t bytes_out, void *din, size_t bytes_in)
+{
+	int ret;
+
+	/* Only the very first byte (opcode) is transferred in "single" mode. */
+	struct spi_op vector = { .dout = dout, .bytesout = 1,
+				 .din = NULL, .bytesin = 0 };
+
+	ret = spi_claim_bus(spi);
+	if (ret)
+		return ret;
+
+	ret = spi_xfer_vector(spi, &vector, 1);
+
+	if (!ret)
+		ret = spi->ctrlr->xfer_dual(spi, &dout[1], bytes_out - 1, NULL, 0);
+
+	if (!ret)
+		ret = spi->ctrlr->xfer_dual(spi, NULL, 0, din, bytes_in);
+
+	spi_release_bus(spi);
+	return ret;
+}
+
 int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len)
 {
 	int ret = do_spi_flash_cmd(spi, &cmd, sizeof(cmd), response, len);
@@ -119,18 +144,23 @@ int spi_flash_cmd_read(const struct spi_flash *flash, u32 offset,
 {
 	u8 cmd[5];
 	int ret, cmd_len;
-	int (*do_cmd)(const struct spi_slave *spi, const void *din,
+	int (*do_cmd)(const struct spi_slave *spi, const u8 *din,
 		      size_t in_bytes, void *out, size_t out_bytes);
 
 	if (CONFIG(SPI_FLASH_NO_FAST_READ)) {
 		cmd_len = 4;
 		cmd[0] = CMD_READ_ARRAY_SLOW;
 		do_cmd = do_spi_flash_cmd;
-	} else if (flash->flags.dual_spi && flash->spi.ctrlr->xfer_dual) {
+	} else if (flash->flags.dual_io && flash->spi.ctrlr->xfer_dual) {
+		cmd_len = 5;
+		cmd[0] = CMD_READ_FAST_DUAL_IO;
+		cmd[4] = 0;
+		do_cmd = do_dual_io_cmd;
+	} else if (flash->flags.dual_output && flash->spi.ctrlr->xfer_dual) {
 		cmd_len = 5;
 		cmd[0] = CMD_READ_FAST_DUAL_OUTPUT;
 		cmd[4] = 0;
-		do_cmd = do_dual_read_cmd;
+		do_cmd = do_dual_output_cmd;
 	} else {
 		cmd_len = 5;
 		cmd[0] = CMD_READ_ARRAY_FAST;
@@ -352,7 +382,8 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash,
 	flash->pp_cmd = vi->desc->pp_cmd;
 	flash->wren_cmd = vi->desc->wren_cmd;
 
-	flash->flags.dual_spi = part->fast_read_dual_output_support;
+	flash->flags.dual_output = part->fast_read_dual_output_support;
+	flash->flags.dual_io = part->fast_read_dual_io_support;
 
 	flash->ops = &vi->desc->ops;
 	flash->prot_ops = vi->prot_ops;
@@ -471,8 +502,10 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
 	}
 
 	const char *mode_string = "";
-	if (flash->flags.dual_spi && spi.ctrlr->xfer_dual)
-		mode_string = " (Dual SPI mode)";
+	if (flash->flags.dual_io && spi.ctrlr->xfer_dual)
+		mode_string = " (Dual I/O mode)";
+	else if (flash->flags.dual_output && spi.ctrlr->xfer_dual)
+		mode_string = " (Dual Output mode)";
 	printk(BIOS_INFO,
 	       "SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n",
 		flash->vendor, flash->model, flash->sector_size, flash->size, mode_string);

diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h
@@ -15,6 +15,7 @@
 #define CMD_READ_ARRAY_LEGACY		0xe8
 
 #define CMD_READ_FAST_DUAL_OUTPUT	0x3b
+#define CMD_READ_FAST_DUAL_IO		0xbb
 
 #define CMD_READ_STATUS			0x05
 #define CMD_WRITE_ENABLE		0x06
@@ -69,8 +70,9 @@ struct spi_flash_part_id {
 	uint16_t id[2];
 	/* Log based 2 total number of sectors. */
 	uint16_t nr_sectors_shift: 4;
-	uint16_t fast_read_dual_output_support : 1;
-	uint16_t _reserved_for_flags: 3;
+	uint16_t fast_read_dual_output_support : 1;	/*  1-1-2 read */
+	uint16_t fast_read_dual_io_support : 1;		/*  1-2-2 read */
+	uint16_t _reserved_for_flags: 2;
 	/* Block protection. Currently used by Winbond. */
 	uint16_t protection_granularity_shift : 5;
 	uint16_t bp_bits : 3;

diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
@@ -101,12 +101,14 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x4014,
 		.nr_sectors_shift		= 8,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 	},
 	{
 		/* W25Q16_V */
 		.id[0]				= 0x4015,
 		.nr_sectors_shift		= 9,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -115,6 +117,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x6015,
 		.nr_sectors_shift		= 9,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -123,6 +126,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x4016,
 		.nr_sectors_shift		= 10,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -131,6 +135,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x6016,
 		.nr_sectors_shift		= 10,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -139,6 +144,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x4017,
 		.nr_sectors_shift		= 11,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 17,
 		.bp_bits			= 3,
 	},
@@ -147,6 +153,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x6017,
 		.nr_sectors_shift		= 11,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 17,
 		.bp_bits			= 3,
 	},
@@ -155,6 +162,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x8017,
 		.nr_sectors_shift		= 11,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 17,
 		.bp_bits			= 3,
 	},
@@ -163,6 +171,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x4018,
 		.nr_sectors_shift		= 12,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -171,6 +180,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x6018,
 		.nr_sectors_shift		= 12,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -179,6 +189,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x7018,
 		.nr_sectors_shift		= 12,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -187,6 +198,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x8018,
 		.nr_sectors_shift		= 12,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -195,6 +207,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x8020,
 		.nr_sectors_shift		= 11,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 4,
 	},
@@ -203,6 +216,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x4019,
 		.nr_sectors_shift		= 13,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 4,
 	},
@@ -211,6 +225,7 @@ static const struct spi_flash_part_id flash_table[] = {
 		.id[0]				= 0x7019,
 		.nr_sectors_shift		= 13,
 		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 4,
 	},

diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h
@@ -68,4 +68,7 @@ struct drivers_usb_acpi_config {
 	struct acpi_gpio privacy_gpio;
 };
 
+/* Method to get PLD structure from USB device */
+bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld);
+
 #endif /* __USB_ACPI_CHIP_H__ */
diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c
@@ -37,6 +37,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 {
 	struct drivers_usb_acpi_config *config = dev->chip_info;
 	const char *path = acpi_device_path(dev);
+	struct acpi_pld pld;
 
 	if (!path || !config)
 		return;
@@ -50,15 +51,10 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 		acpigen_write_name_string("_DDN", config->desc);
 	acpigen_write_upc(config->type);
 
-	if (config->use_custom_pld) {
-		/* Use board defined PLD */
-		acpigen_write_pld(&config->custom_pld);
-	} else {
-		/* Fill PLD strucutre based on port type */
-		struct acpi_pld pld;
-		acpi_pld_fill_usb(&pld, config->type, &config->group);
+	if (usb_acpi_get_pld(dev, &pld))
 		acpigen_write_pld(&pld);
-	}
+	else
+		printk(BIOS_ERR, "Error retrieving PLD for %s\n", path);
 
 	/* Resources */
 	if (usb_acpi_add_gpios_to_crs(config) == true) {
@@ -126,3 +122,20 @@ struct chip_operations drivers_usb_acpi_ops = {
 	CHIP_NAME("USB ACPI Device")
 	.enable_dev = usb_acpi_enable
 };
+
+bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld)
+{
+	struct drivers_usb_acpi_config *config;
+
+	if (!usb_device || !usb_device->chip_info ||
+		usb_device->chip_ops != &drivers_usb_acpi_ops)
+		return false;
+
+	config = usb_device->chip_info;
+	if (config->use_custom_pld)
+		*pld = config->custom_pld;
+	else
+		acpi_pld_fill_usb(pld, config->type, &config->group);
+
+	return true;
+}
diff --git a/src/drivers/wifi/generic/smbios.c b/src/drivers/wifi/generic/smbios.c
@@ -10,24 +10,18 @@
 static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current)
 {
 	struct smbios_type_intel_wifi {
-		u8 type;
-		u8 length;
-		u16 handle;
+		struct smbios_header header;
 		u8 str;
 		u8 eos[2];
 	} __packed;
 
-	struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current;
-	int len = sizeof(struct smbios_type_intel_wifi);
+	struct smbios_type_intel_wifi *t = smbios_carve_table(*current, 0x85,
+							      sizeof(*t), *handle);
 
-	memset(t, 0, sizeof(struct smbios_type_intel_wifi));
-	t->type = 0x85;
-	t->length = len - 2;
-	t->handle = *handle;
 	/* Intel wifi driver expects this string to be in the table 0x85. */
 	t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII");
 
-	len = t->length + smbios_string_table_len(t->eos);
+	const int len = smbios_full_table_len(&t->header, t->eos);
 	*current += len;
 	*handle += 1;
 	return len;

diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
@@ -19,7 +19,7 @@ uint64_t google_chromeec_get_wake_mask(void);
 int google_chromeec_set_sci_mask(uint64_t mask);
 int google_chromeec_set_smi_mask(uint64_t mask);
 int google_chromeec_set_wake_mask(uint64_t mask);
-uint8_t google_chromeec_get_event(void);
+enum host_event_code google_chromeec_get_event(void);
 
 /* Check if EC supports feature EC_FEATURE_UNIFIED_WAKE_MASKS */
 bool google_chromeec_is_uhepi_supported(void);