diff --git a/configs/pcengines_apu2.config b/configs/pcengines_apu2.config
diff --git a/configs/pcengines_apu3.config b/configs/pcengines_apu3.config
diff --git a/configs/pcengines_apu5.config b/configs/pcengines_apu5.config
diff --git a/payloads/Kconfig b/payloads/Kconfig
@@ -106,6 +106,15 @@ config MEMTEST_MASTER
 	  non-reproducible, as it can fetch different code each time.
 endchoice
 
+config MEMTEST_DISABLE_SPD
+	bool "Disable retrieving SPD info"
+	depends on MEMTEST_SECONDARY_PAYLOAD
+	help
+	  Disables retrieving RAM SPD info in Memtest86+.
+
+	  Some chipsets and mainboards do not support this feature and it
+	  should be disabled in Memtest86+ to avoid unwanted behaviour.
+
 config NVRAMCUI_SECONDARY_PAYLOAD
 	bool "Load nvramcui as a secondary payload"
 	default n

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -206,6 +206,10 @@ ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
 		SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD)
 endif
 
+ifeq ($(CONFIG_MEMTEST_DISABLE_SPD),y)
+	MEMTEST_SPD_OPTIONS=CB_NOSPD=1
+endif
+
 payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/Memtest86Plus all \
 		CC="$(CC_x86_32)" \
@@ -214,6 +218,8 @@ payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG)
 		AS="$(AS_x86_32)" \
 		CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
 		CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
+		CONFIG_MEMTEST_SPD=$(CONFIG_MEMTEST_SPD) \
+		$(MEMTEST_SPD_OPTIONS) \
 		$(MEMTEST_SERIAL_OPTIONS) \
 		MFLAGS= MAKEFLAGS=
 

diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile
@@ -15,7 +15,7 @@
 
 TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
 NAME-$(CONFIG_MEMTEST_MASTER)=Master
-TAG-$(CONFIG_MEMTEST_STABLE)=a4efe01c3d15cdb6c64adc8dfe5f890c15459f27
+TAG-$(CONFIG_MEMTEST_STABLE)=7afa395fe8b11d681b27c38e204814ba643c2108
 NAME-$(CONFIG_MEMTEST_STABLE)=Stable
 
 project_name=Memtest86+
@@ -38,8 +38,8 @@ checkout: fetch
 	echo "    Checking out $(project_name) revision $(NAME-y) ($(TAG-y))"
 	cd $(project_dir); \
 		git checkout master; \
-		git branch -D coreboot 2>/dev/null; \
-		git checkout -b coreboot $(TAG-y)
+ 		git branch -D coreboot 2>/dev/null; \
+ 		git checkout -b coreboot $(TAG-y)
 
 build: checkout
 	echo "    MAKE       $(project_name) $(NAME-y)"

diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -99,7 +99,12 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
 
 		/* EHCI configuration */
 		FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+
+#if CONFIG_BOARD_PCENGINES_APU2
 		FchParams->Usb.Ehci1Enable = FALSE;	// Disable EHCI 0 (port 0 to 3)
+#else
+		FchParams->Usb.Ehci1Enable = TRUE;	// Enable EHCI 0 (port 0 to 3)
+#endif
 		FchParams->Usb.Ehci2Enable = TRUE;	// Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
 
 		/* sata configuration */

diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
@@ -14,7 +14,7 @@
 # GNU General Public License for more details.
 #
 
-if BOARD_PCENGINES_APU2
+if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -30,14 +30,27 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select USE_BLOBS
 	select GENERIC_SPD_BIN
 	select PXE
+	select MEMTEST_DISABLE_SPD if MEMTEST_SECONDARY_PAYLOAD
 
 config MAINBOARD_DIR
 	string
 	default pcengines/apu2
 
+config VARIANT_DIR
+	string
+	default apu2 if BOARD_PCENGINES_APU2
+	default apu3 if BOARD_PCENGINES_APU3
+	default apu5 if BOARD_PCENGINES_APU5
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
 config MAINBOARD_PART_NUMBER
 	string
-	default "PC Engines apu2"
+	default "PC Engines apu2" if BOARD_PCENGINES_APU2
+	default "PC Engines apu3" if BOARD_PCENGINES_APU3
+	default "PC Engines apu5" if BOARD_PCENGINES_APU5
 
 config MAX_CPUS
 	int

diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -1,2 +1,8 @@
 config BOARD_PCENGINES_APU2
 	bool "APU2"
+
+config BOARD_PCENGINES_APU3
+	bool "APU3"
+
+config BOARD_PCENGINES_APU5
+	bool "APU5"
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -24,3 +24,5 @@ ramstage-y += gpio_ftns.c
 # Order of names in SPD_SOURCES is important!
 SPD_SOURCES  = HYNIX-2G-1333
 SPD_SOURCES += HYNIX-4G-1333-ECC
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -25,33 +25,36 @@ int get_spd_offset(void);
 #define GPIO_OFFSET     0x1500
 
 //
-// Based on PC Engines APU2C schematics
+// Based on PC Engines APU2C and APU3A schematics
 // http://www.pcengines.ch/schema/apu2c.pdf
+// http://www.pcengines.ch/schema/apu3a.pdf
 //
-#define IOMUX_GPIO_32   0x59    // MODESW
+#define IOMUX_GPIO_32   0x59    // MODESW (SIMSWAP2 on APU5)
+#define IOMUX_GPIO_33   0x5A    // SIMSWAP (SIMSWAP3 on APU5)
 #define IOMUX_GPIO_49   0x40    // STRAP0
 #define IOMUX_GPIO_50   0x41    // STRAP1
-#define IOMUX_GPIO_51   0x42    // PE3 Reset
-#define IOMUX_GPIO_55   0x43    // PE4 Reset
+#define IOMUX_GPIO_51   0x42    // PE3 Reset (SIM1 Reset on APU5)
+#define IOMUX_GPIO_55   0x43    // PE4 Reset (SIM2 Reset on APU5)
 #define IOMUX_GPIO_57   0x44    // LED1#
 #define IOMUX_GPIO_58   0x45    // LED2#
 #define IOMUX_GPIO_59   0x46    // LED3#
-#define IOMUX_GPIO_64   0x47    // PE3_WDIS
+#define IOMUX_GPIO_64   0x47    // PE3_WDIS (SIM3 Reset on APU5)
 #define IOMUX_GPIO_66   0x5B    // SPKR
-#define IOMUX_GPIO_68   0x48    // PE4_WDIS
+#define IOMUX_GPIO_68   0x48    // PE4_WDIS (SIMSWAP1 on APU5)
 #define IOMUX_GPIO_71   0x4D    // PROCHOT
 
-#define GPIO_32   0x164    // MODESW
+#define GPIO_32   0x164    // MODESW (SIMSWAP2 on APU5)
+#define GPIO_33   0x168    // SIMSWAP (SIMSWAP3 on APU5)
 #define GPIO_49   0x100    // STRAP0
 #define GPIO_50   0x104    // STRAP1
-#define GPIO_51   0x108    // PE3 Reset
-#define GPIO_55   0x10C    // PE4 Reset
+#define GPIO_51   0x108    // PE3 Reset (SIM1 Reset on APU5)
+#define GPIO_55   0x10C    // PE4 Reset (SIM2 Reset on APU5)
 #define GPIO_57   0x110    // LED1#
 #define GPIO_58   0x114    // LED2#
 #define GPIO_59   0x118    // LED3#
-#define GPIO_64   0x11C    // PE3_WDIS
+#define GPIO_64   0x11C    // PE3_WDIS (SIM3 Reset on APU5)
 #define GPIO_66   0x16C    // SPKR
-#define GPIO_68   0x120    // PE4_WDIS
+#define GPIO_68   0x120    // PE4_WDIS (SIMSWAP1 on APU5)
 #define GPIO_71   0x134    // PROCHOT
 
 #define GPIO_OUTPUT_ENABLE      BIT23

diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
@@ -216,7 +216,7 @@ static void mainboard_enable(device_t dev)
 static void mainboard_final(void *chip_info)
 {
 	//
-	// Turn off LED D4 and D5
+	// Turn off LED 2 and 3
 	//
 	write_gpio(GPIO_58, 1);
 	write_gpio(GPIO_59, 1);

diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
@@ -89,7 +89,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		data &= 0xFFFF0000;
 		data |= (0 + 1) << (0 * 4);	// CLKREQ 0 to CLK0
 		data |= (1 + 1) << (1 * 4);	// CLKREQ 1 to CLK1
-		data |= (2 + 1) << (2 * 4);	// CLKREQ 2 to CLK2
+#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3
+		data |= (2 + 1) << (2 * 4);	// CLKREQ 2 to CLK2 disabled on APU5
+#endif
 		// make CLK3 to ignore CLKREQ# input
 		// force it to be always on
 		data |= ( 0xf ) << (3 * 4);	// CLKREQ 3 to CLK3
@@ -156,21 +158,30 @@ static void early_lpc_init(void)
 	//
 	// Configure output disabled, value low, pull up/down disabled
 	//
+#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3
 	configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
+#endif
 	configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting);
 	configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting);
 	configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting);
 	//
 	// Configure output enabled, value low, pull up/down disabled
 	//
 	setting = GPIO_OUTPUT_ENABLE;
+#if CONFIG_BOARD_PCENGINES_APU3
+	configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
+#endif
 	configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting);
 	configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting);
 	configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting);
 	//
 	// Configure output enabled, value high, pull up/down disabled
 	//
 	setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
+#if CONFIG_BOARD_PCENGINES_APU5
+	configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
+	configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
+#endif
 	configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting);
 	configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting);
 	configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting);

diff --git a/src/mainboard/pcengines/apu2/board_info.txt → ...engines/apu2/variants/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt → ...engines/apu2/variants/apu2/board_info.txt
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb → ...cengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb → ...cengines/apu2/variants/apu2/devicetree.cb
diff --git a/src/mainboard/pcengines/apu3/board_info.txt → ...engines/apu2/variants/apu3/board_info.txt b/src/mainboard/pcengines/apu3/board_info.txt → ...engines/apu2/variants/apu3/board_info.txt
diff --git a/src/mainboard/pcengines/apu5/devicetree.cb → ...cengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu5/devicetree.cb → ...cengines/apu2/variants/apu3/devicetree.cb
@@ -40,7 +40,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0 muxed with EHCI 2
 				device pci 11.0 on  end # SATA
-				device pci 12.0 on  end # USB EHCI0 usb[0:3] not connected
+				device pci 12.0 on  end # USB EHCI0 usb[0:3] is connected
 				device pci 13.0 on  end # USB EHCI1 usb[4:7]
 				device pci 14.0 on  end # SM
 				device pci 14.3 on      # LPC 0x439d

diff --git a/src/mainboard/pcengines/apu5/board_info.txt → ...engines/apu2/variants/apu5/board_info.txt b/src/mainboard/pcengines/apu5/board_info.txt → ...engines/apu2/variants/apu5/board_info.txt
diff --git a/src/mainboard/pcengines/apu3/devicetree.cb → ...cengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu3/devicetree.cb → ...cengines/apu2/variants/apu5/devicetree.cb
@@ -40,7 +40,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0 muxed with EHCI 2
 				device pci 11.0 on  end # SATA
-				device pci 12.0 on  end # USB EHCI0 usb[0:3] not connected
+				device pci 12.0 on  end # USB EHCI0 usb[0:3] is connected
 				device pci 13.0 on  end # USB EHCI1 usb[4:7]
 				device pci 14.0 on  end # SM
 				device pci 14.3 on      # LPC 0x439d

diff --git a/src/mainboard/pcengines/apu3/BiosCallOuts.c b/src/mainboard/pcengines/apu3/BiosCallOuts.c
diff --git a/src/mainboard/pcengines/apu3/Kconfig b/src/mainboard/pcengines/apu3/Kconfig
diff --git a/src/mainboard/pcengines/apu3/Kconfig.name b/src/mainboard/pcengines/apu3/Kconfig.name
diff --git a/src/mainboard/pcengines/apu3/Makefile.inc b/src/mainboard/pcengines/apu3/Makefile.inc
diff --git a/src/mainboard/pcengines/apu3/OemCustomize.c b/src/mainboard/pcengines/apu3/OemCustomize.c
diff --git a/src/mainboard/pcengines/apu3/acpi/AmdImc.asl b/src/mainboard/pcengines/apu3/acpi/AmdImc.asl
diff --git a/src/mainboard/pcengines/apu3/acpi/gpe.asl b/src/mainboard/pcengines/apu3/acpi/gpe.asl
diff --git a/src/mainboard/pcengines/apu3/acpi/mainboard.asl b/src/mainboard/pcengines/apu3/acpi/mainboard.asl
diff --git a/src/mainboard/pcengines/apu3/acpi/routing.asl b/src/mainboard/pcengines/apu3/acpi/routing.asl
diff --git a/src/mainboard/pcengines/apu3/acpi/si.asl b/src/mainboard/pcengines/apu3/acpi/si.asl
diff --git a/src/mainboard/pcengines/apu3/acpi/sleep.asl b/src/mainboard/pcengines/apu3/acpi/sleep.asl
diff --git a/src/mainboard/pcengines/apu3/acpi/usb_oc.asl b/src/mainboard/pcengines/apu3/acpi/usb_oc.asl
diff --git a/src/mainboard/pcengines/apu3/acpi_tables.c b/src/mainboard/pcengines/apu3/acpi_tables.c
diff --git a/src/mainboard/pcengines/apu3/boot-menu-key b/src/mainboard/pcengines/apu3/boot-menu-key
diff --git a/src/mainboard/pcengines/apu3/boot-menu-message b/src/mainboard/pcengines/apu3/boot-menu-message
diff --git a/src/mainboard/pcengines/apu3/boot-menu-wait b/src/mainboard/pcengines/apu3/boot-menu-wait
diff --git a/src/mainboard/pcengines/apu3/bootorder b/src/mainboard/pcengines/apu3/bootorder
diff --git a/src/mainboard/pcengines/apu3/bootorder_def b/src/mainboard/pcengines/apu3/bootorder_def
diff --git a/src/mainboard/pcengines/apu3/bootorder_map b/src/mainboard/pcengines/apu3/bootorder_map
diff --git a/src/mainboard/pcengines/apu3/cmos.layout b/src/mainboard/pcengines/apu3/cmos.layout
diff --git a/src/mainboard/pcengines/apu3/dsdt.asl b/src/mainboard/pcengines/apu3/dsdt.asl
diff --git a/src/mainboard/pcengines/apu3/gpio_ftns.c b/src/mainboard/pcengines/apu3/gpio_ftns.c
diff --git a/src/mainboard/pcengines/apu3/gpio_ftns.h b/src/mainboard/pcengines/apu3/gpio_ftns.h
diff --git a/src/mainboard/pcengines/apu3/irq_tables.c b/src/mainboard/pcengines/apu3/irq_tables.c
diff --git a/src/mainboard/pcengines/apu3/mainboard.c b/src/mainboard/pcengines/apu3/mainboard.c
diff --git a/src/mainboard/pcengines/apu3/mptable.c b/src/mainboard/pcengines/apu3/mptable.c
diff --git a/src/mainboard/pcengines/apu3/romstage.c b/src/mainboard/pcengines/apu3/romstage.c
diff --git a/src/mainboard/pcengines/apu3/spd/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu3/spd/HYNIX-2G-1333.spd.hex
diff --git a/src/mainboard/pcengines/apu3/spd/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu3/spd/HYNIX-4G-1333-ECC.spd.hex
diff --git a/src/mainboard/pcengines/apu5/BiosCallOuts.c b/src/mainboard/pcengines/apu5/BiosCallOuts.c