31 changes: 16 additions & 15 deletions MAINTAINERS
View file
Expand Up @@ -219,25 +219,18 @@ F: src/mainboard/clevo/

FACEBOOK FBG1701 MAINBOARD
M: Frans Hendriks <fhendriks@eltan.com>
M: Wim Vervoorn <wvervoorn@eltan.com>
M: Erik van den Bogaert <ebogaert@eltan.com>
S: Maintained
F: src/mainboard/facebook/fbg1701/

FACEBOOK MONOLITH MAINBOARD
M: Frans Hendriks <fhendriks@eltan.com>
M: Wim Vervoorn <wvervoorn@eltan.com>
M: Erik van den Bogaert <ebogaert@eltan.com>
S: Maintained
F: src/mainboard/facebook/monolith/



GETAC P470 MAINBOARD
M: Patrick Georgi <patrick@georgi.software>
S: Maintained
F: src/mainboard/getac/p470/



GIGABYTE GA-D510UD MAINBOARD
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
Expand Down Expand Up @@ -401,7 +394,7 @@ F: src/mainboard/pcengines/

PORTWELL PQ-M107 MAINBOARD
M: Frans Hendriks <fhendriks@eltan.com>
M: Wim Vervoorn <wvervoorn@eltan.com>
M: Erik van den Bogaert <ebogaert@eltan.com>
S: Maintained
F: src/mainboard/portwell/m107/

Expand Down Expand Up @@ -451,6 +444,13 @@ F: src/mainboard/siemens/mc_apl1/



STAR LABS MAINBOARDS
M: Sean Rhodes <sean@starlabs.systems>
S: Maintained
F: src/mainboard/starlabs/



SYSTEM76 MAINBOARDS
M: Jeremy Soller <jeremy@system76.com>
M: Tim Crawford <tcrawford@system76.com>
Expand Down Expand Up @@ -523,6 +523,11 @@ M: Alexander Couzens <lynxis@fe80.eu>
S: Maintained
F: src/ec/lenovo/

STARLABS EC
M: Sean Rhodes <sean@starlabs.systems>
S: Maintained
F: src/ec/starlabs/

SYSTEM76 EC
M: Jeremy Soller <jeremy@system76.com>
M: Tim Crawford <tcrawford@system76.com>
Expand Down Expand Up @@ -719,7 +724,6 @@ F: payloads/external/LinuxBoot/
################################################################################

ABUILD
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: util/abuild/
Expand All @@ -728,7 +732,6 @@ BOARD STATUS
F: util/board_status/

BUILD SYSTEM
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: Makefile
Expand All @@ -752,7 +755,6 @@ F: .git*
F: /util/gitconfig

LINT SCRIPTS
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: util/lint/
Expand Down Expand Up @@ -876,7 +878,7 @@ F: *.ld

ELTAN VENDORCODE
M: Frans Hendriks <fhendriks@eltan.com>
M: Wim Vervoorn <wvervoorn@eltan.com>
M: Erik van den Bogaert <ebogaert@eltan.com>
S: Maintained
F: src/vendorcode/eltan/

Expand Down Expand Up @@ -927,7 +929,6 @@ MISSING: SPI

CODE OF CONDUCT
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Patrick Georgi <patrick@coreboot.org>
M: Ronald Minnich <rminnich@coreboot.org>
M: Martin Roth <martin@coreboot.org>
S: Maintained
Expand Down
1 change: 1 addition & 0 deletions Makefile
View file
Expand Up @@ -63,6 +63,7 @@ ifneq ($(V),1)
ifneq ($(Q),)
.SILENT:
MAKEFLAGS += -s
quiet_errors := 2>/dev/null
endif
endif

Expand Down
19 changes: 11 additions & 8 deletions Makefile.inc
View file
Expand Up @@ -189,29 +189,29 @@ ramstage-generic-ccopts += -D__RAMSTAGE__
ifeq ($(CONFIG_COVERAGE),y)
ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
endif

ifneq ($(UPDATED_SUBMODULES),1)
# try to fetch non-optional submodules if the source is under git
forgetthis:=$(if $(GIT),$(shell git submodule update --init))
forgetthis:=$(if $(GIT),$(shell git submodule update --init $(quiet_errors)))
# Checkout Cmocka repository
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors)))
ifeq ($(CONFIG_USE_BLOBS),y)
# These items are necessary because each has update=none in .gitmodules. They are ignored
# until expressly requested and enabled with --checkout
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors)))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors)))
ifeq ($(CONFIG_FSP_USE_REPO),y)
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors)))
endif
ifeq ($(CONFIG_USE_AMD_BLOBS),y)
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors)))
endif
ifeq ($(CONFIG_USE_QC_BLOBS),y)
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors)))
endif
endif
UPDATED_SUBMODULES:=1
COREBOOT_EXPORTS += UPDATED_SUBMODULES

endif

postcar-c-deps:=$$(OPTION_TABLE_H)
Expand Down Expand Up @@ -280,6 +280,9 @@ define asl_template
$(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
$(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw
$(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
$(CONFIG_CBFS_PREFIX)/$(1).aml-align = 64
endif
cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml
-include $(obj)/$(1).d
$(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
Expand Down
1 change: 0 additions & 1 deletion configs/config.facebook_fbg1701.mboot_vboot
View file
@@ -1,6 +1,5 @@
CONFIG_VENDOR_FACEBOOK=y
CONFIG_BOARD_FACEBOOK_FBG1701=y
CONFIG_ONBOARD_SAMSUNG_MEM=y
CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.1"
CONFIG_LOCALVERSION="v4.15.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_CBFS_SIZE=0x00200000
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.1"
CONFIG_LOCALVERSION="v4.15.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,157b"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.1"
CONFIG_LOCALVERSION="v4.15.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.1"
CONFIG_LOCALVERSION="v4.15.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.1"
CONFIG_LOCALVERSION="v4.15.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.15.0.1"
CONFIG_LOCALVERSION="v4.15.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
3 changes: 2 additions & 1 deletion payloads/external/Makefile.inc
View file
Expand Up @@ -252,8 +252,9 @@ payloads/external/GRUB2/grub2/build/default_payload.elf: grub2

# U-Boot

payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG)
payloads/external/U-Boot/build/u-boot.bin u-boot: $(DOTCONFIG)
$(MAKE) -C payloads/external/U-Boot \
STABLE_COMMIT_ID=$(CONFIG_UBOOT_STABLE_COMMIT_ID) \
CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \
CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE)

Expand Down
2 changes: 1 addition & 1 deletion payloads/external/SeaBIOS/Kconfig
View file
Expand Up @@ -5,7 +5,7 @@ choice
default SEABIOS_STABLE

config SEABIOS_STABLE
bool "1.14.0"
bool "1.15.0"
help
Stable SeaBIOS version
config SEABIOS_MASTER
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/SeaBIOS/Makefile
View file
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0
TAG-$(CONFIG_SEABIOS_STABLE)=2dd4b9b3f84019668719344b40dba79d681be41c
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)

project_git_repo=https://github.com/pcengines/seabios.git
Expand Down
11 changes: 8 additions & 3 deletions payloads/external/U-Boot/Kconfig
View file
Expand Up @@ -3,13 +3,18 @@ if PAYLOAD_UBOOT
config PAYLOAD_SPECIFIC_OPTIONS
def_bool y
select PAYLOAD_IS_FLAT_BINARY
select WANT_LINEAR_FRAMEBUFFER

config UBOOT_STABLE_COMMIT_ID
string
default "v2021.07"

choice
prompt "U-Boot version"
default UBOOT_STABLE

config UBOOT_STABLE
bool "v2019.4"
bool "v2021.07"
help
Stable U-Boot version

Expand All @@ -32,9 +37,9 @@ config PAYLOAD_CONFIGFILE
from the U-Boot config directory

config PAYLOAD_FILE
default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin"
default "payloads/external/U-Boot/build/u-boot.bin"

config PAYLOAD_OPTIONS
default "-l 0x1110000 -e 0x1110015"
default "-l 0x1110000 -e 0x1110000"

endif
24 changes: 12 additions & 12 deletions payloads/external/U-Boot/Makefile
View file
@@ -1,15 +1,15 @@
## SPDX-License-Identifier: GPL-2.0-only

# 2019-4 tag
STABLE_COMMIT_ID=3c99166441bf3ea325af2da83cfe65430b49c066

TAG-$(CONFIG_UBOOT_MASTER)=origin/master
TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)

project_name=U-Boot
project_dir=u-boot
project_git_repo=http://git.denx.de/u-boot.git
project_config_file=$(project_dir)/.config
project_build_dir=build
project_config_file=$(project_build_dir)/.config

make_args=-C $(project_dir) O=../build

unexport KCONFIG_AUTOHEADER
unexport KCONFIG_AUTOCONFIG
Expand All @@ -23,46 +23,46 @@ all: build

$(project_dir):
echo " Cloning $(project_name) from Git"
git clone $(project_git_repo) $(project_dir)
git clone $(project_git_repo) -b $(TAG-y) $(project_dir)

fetch: $(project_dir)
ifeq ($(CONFIG_UBOOT_MASTER),y)
echo " Fetching new commits from the $(project_name) git repo"
git fetch

#master doesn't get a file, so it's continuously updated
rm -f $(project_dir)/$(STABLE_COMMIT_ID)
rm -f $(STABLE_COMMIT_ID)
else
cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \
then echo " Fetching new commits from the $(project_name) git repo"; git fetch; fi
touch $(project_dir)/$(STABLE_COMMIT_ID)
touch $(STABLE_COMMIT_ID)
endif

checkout: fetch
echo " Checking out $(project_name) revision $(TAG-y)"
cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)

config: checkout
mkdir -p $(project_build_dir)
rm -f $(project_config_file)
ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),)
ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","")
cat $(CONFIG_PAYLOAD_CONFIGFILE)" > tag-$(project_config_file)
$(MAKE) $(make_args) olddefconfig
else
echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist"
false
endif
else
cat $(project_dir)/configs/coreboot_defconfig >> $(project_config_file)
$(MAKE) $(make_args) coreboot_defconfig
endif

$(MAKE) -C $(project_dir) olddefconfig

build: config
echo " MAKE $(project_name) $(TAG-y)"
$(MAKE) -C $(project_dir)
$(MAKE) $(make_args)

clean:
test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0
test -d $(project_dir) && $(MAKE) $(make_args) clean || exit 0

distclean:
rm -rf $(project_dir)
Expand Down
25 changes: 20 additions & 5 deletions payloads/libpayload/Makefile
View file
Expand Up @@ -29,16 +29,22 @@
## SUCH DAMAGE.
##

ifneq ($(words $(CURDIR)),1)
$(error ERROR: Path to the main directory cannot contain spaces)
endif

ifeq ($(INNER_SCANBUILD),y)
CC_real:=$(CC)
endif

export top := $(CURDIR)
export coreboottop ?= $(abspath $(top)/../../)
export src := src
export srck := $(abspath $(top)/../../util/kconfig)
export obj ?= build
export objutil ?= $(obj)/util
export objk := $(objutil)/lp_kconfig
export absobj := $(abspath $(obj))

export KCONFIG_AUTOHEADER := $(obj)/config.h
export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
Expand Down Expand Up @@ -289,9 +295,11 @@ includemakefiles= \
$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
$(foreach class,$(classes), \
$(eval $(class)-srcs+= \
$$(subst $(absobj)/,$(obj)/, \
$$(subst $(top)/,, \
$$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \
$(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))


# For each path in $(subdirs) call includemakefiles
# Repeat until subdirs is empty
Expand All @@ -310,8 +318,15 @@ else
include $(TOPLEVEL)/tests/Makefile.inc
endif

src-to-obj=$(addsuffix .$(1).o, $(basename $(addprefix $(obj)/, $($(1)-srcs))))
$(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class))))
# Converts one or more source file paths to the corresponding build/ paths.
# $1 lib name
# $2 file path (list)
src-to-obj=\
$(addsuffix .$(1).o,\
$(basename \
$(addprefix $(obj)/,\
$(subst $(coreboottop)/,coreboot/,$(2)))))
$(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class),$($(class)-srcs))))

allsrcs:=$(foreach var, $(addsuffix -srcs,$(classes)), $($(var)))
allobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var)))
Expand All @@ -325,7 +340,7 @@ define create_cc_template
# $4 additional dependencies
ifn$(EMPTY)def $(1)-objs_$(2)_template
de$(EMPTY)fine $(1)-objs_$(2)_template
$(obj)/$$(1).$(1).o: $$(1).$(2) $(obj)/libpayload-config.h $(4)
$$(call src-to-obj,$(1), $$(1).$(2)): $$(1).$(2) $(obj)/libpayload-config.h $(4)
@printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n"
$(CC) $(3) -MMD $$$$(CFLAGS) $(EXTRA_CFLAGS) -c -o $$$$@ $$$$<
en$(EMPTY)def
Expand Down
6 changes: 6 additions & 0 deletions payloads/libpayload/Makefile.inc
View file
Expand Up @@ -58,6 +58,7 @@ subdirs-$(CONFIG_LP_LZ4) += liblz4

INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj)
INCLUDES += -include include/kconfig.h -include include/compiler.h
INCLUDES += -I$(coreboottop)/src/commonlib/bsd/include

CFLAGS += $(INCLUDES) -Os -pipe -nostdinc -ggdb3
CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
Expand Down Expand Up @@ -115,6 +116,11 @@ install: real-target
install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \
install -m 644 $$file $(DESTDIR)/libpayload/$$file; \
done
for file in `find $(coreboottop)/src/commonlib/bsd/include -name *.h -type f`; do \
dest_file=$$(realpath --relative-to=$(coreboottop)/src/commonlib/bsd/ $$file); \
install -m 755 -d "$(DESTDIR)/libpayload/`dirname $$dest_file`"; \
install -m 644 "$$file" "$(DESTDIR)/libpayload/$$dest_file"; \
done
install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include
$(foreach item,$(includes), \
install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \
Expand Down
17 changes: 17 additions & 0 deletions payloads/libpayload/arch/x86/boot_media.c
View file
@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: BSD-3-Clause */

#include <boot_device.h>
#include <commonlib/bsd/cb_err.h>
#include <stddef.h>
#include <string.h>
#include <sysinfo.h>

__attribute__((weak)) ssize_t boot_device_read(void *buf, size_t offset, size_t size)
{
/* Memory-mapping usually only works for the top 16MB. */
if (!lib_sysinfo.boot_media_size || lib_sysinfo.boot_media_size - offset > 16 * MiB)
return CB_ERR_ARG;
void *ptr = (void *)(uintptr_t)(0 - lib_sysinfo.boot_media_size + offset);
memcpy(buf, ptr, size);
return size;
}
8 changes: 0 additions & 8 deletions payloads/libpayload/arch/x86/coreboot.c
View file
Expand Up @@ -47,20 +47,12 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info)
info->x86_rom_var_mtrr_index = rom_mtrr->index;
}

static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info)
{
info->mrc_cache = get_cbmem_addr(ptr);
}

int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
{
switch(rec->tag) {
case CB_TAG_X86_ROM_MTRR:
cb_parse_x86_rom_var_mtrr(rec, info);
break;
case CB_TAG_MRC_CACHE:
cb_parse_mrc_cache(rec, info);
break;
default:
return 0;
}
Expand Down
13 changes: 13 additions & 0 deletions payloads/libpayload/include/assert.h
View file
Expand Up @@ -29,6 +29,17 @@
#include <stdlib.h>
#include <stdio.h>

#ifdef __TEST__

/* CMocka function redefinition */
void mock_assert(const int result, const char *const expression, const char *const file,
const int line);

#define MOCK_ASSERT(result, expression) mock_assert((result), (expression), __FILE__, __LINE__)
#define assert(statement) MOCK_ASSERT(!!(statement), #statement)

#else

// assert's existence depends on NDEBUG state on _last_ inclusion of assert.h,
// so don't guard this against double-includes.
#ifdef NDEBUG
Expand All @@ -43,3 +54,5 @@
abort(); \
}
#endif

#endif /* __TEST__ */
22 changes: 22 additions & 0 deletions payloads/libpayload/include/boot_device.h
View file
@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: BSD-3-Clause */

#ifndef _BOOT_DEVICE_H
#define _BOOT_DEVICE_H

#include <stddef.h>

/**
* This is a boot device access function, which is used by libpayload to read data from
* the flash memory (or other boot device). It has to be implemented by payloads that want
* to use FMAP or libcbfs.
*
* @param buf The output buffer to which the data should be written to.
* @param offset Absolute offset in bytes of the requested boot device memory area. Not aligned.
* @param size Size in bytes of the requested boot device memory area. Not aligned.
*
* @returns Number of bytes returned to the buffer, or negative value on error. Typically should
* be equal to the `size`, and not aligned forcefully.
*/
ssize_t boot_device_read(void *buf, size_t offset, size_t size);

#endif /* _BOOT_DEVICE_H */
12 changes: 10 additions & 2 deletions payloads/libpayload/include/coreboot_tables.h
View file
Expand Up @@ -321,6 +321,16 @@ struct cb_boot_media_params {
uint64_t boot_media_size;
};


struct cb_cbmem_entry {
uint32_t tag;
uint32_t size;

uint64_t address;
uint32_t entry_size;
uint32_t id;
};

struct cb_tsc_info {
uint32_t tag;
uint32_t size;
Expand Down Expand Up @@ -443,6 +453,4 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
+ (sizeof((_rec)->map[0]) * (_idx)))

/* Helper functions */
uintptr_t get_cbmem_addr(const void *cbmem_tab_entry);
#endif
3 changes: 3 additions & 0 deletions payloads/libpayload/include/libpayload.h
View file
Expand Up @@ -457,6 +457,8 @@ static inline int clz(u32 x)
static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; }
/* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */
static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); }
/* Find Last Set: __fls(1) == 0, __fls(5) == 2, __fls(1 << 31) == 31 */
static inline int __fls(u32 x) { return log2(x); }

static inline int popcnt64(u64 x) { return __builtin_popcountll(x); }
static inline int clz64(u64 x)
Expand All @@ -466,6 +468,7 @@ static inline int clz64(u64 x)

static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; }
static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); }
static inline int __fls64(u64 x) { return log2_64(x); }
/** @} */

/**
Expand Down
6 changes: 6 additions & 0 deletions payloads/libpayload/include/sysinfo.h
View file
Expand Up @@ -150,6 +150,12 @@ struct sysinfo_t {
#endif
/* USB Type-C Port Configuration Info */
uintptr_t type_c_info;

/* CBFS RW/RO Metadata Cache */
uintptr_t cbfs_ro_mcache_offset;
uint32_t cbfs_ro_mcache_size;
uintptr_t cbfs_rw_mcache_offset;
uint32_t cbfs_rw_mcache_size;
};

extern struct sysinfo_t lib_sysinfo;
Expand Down
133 changes: 55 additions & 78 deletions payloads/libpayload/libc/coreboot.c
View file
Expand Up @@ -29,6 +29,7 @@

#include <libpayload-config.h>
#include <libpayload.h>
#include <commonlib/bsd/cbmem_id.h>
#include <coreboot_tables.h>
#include <stdint.h>

Expand All @@ -41,12 +42,6 @@
/* === Parsing code === */
/* This is the generic parsing code. */

uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry)
{
const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry;
return cbmem->cbmem_tab;
}

static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
{
struct cb_memory *mem = ptr;
Expand Down Expand Up @@ -83,11 +78,6 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
info->cb_serial = virt_to_phys(ptr);
}

static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info)
{
info->vboot_workbuf = get_cbmem_addr(ptr);
}

static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
{
struct lb_range *vbnv = (struct lb_range *)ptr;
Expand Down Expand Up @@ -128,26 +118,6 @@ static void cb_parse_mac_addresses(unsigned char *ptr,
info->macs[i] = macs->mac_addrs[i];
}

static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info)
{
info->tstamp_table = get_cbmem_addr(ptr);
}

static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info)
{
info->cbmem_cons = get_cbmem_addr(ptr);
}

static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info)
{
info->acpi_gnvs = get_cbmem_addr(ptr);
}

static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info)
{
info->acpi_cnvs = get_cbmem_addr(ptr);
}

static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info)
{
struct cb_board_config *const config = (struct cb_board_config *)ptr;
Expand Down Expand Up @@ -188,11 +158,6 @@ static void cb_parse_string(const void *const ptr, uintptr_t *const info)
*info = virt_to_phys(str->string);
}

static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info)
{
info->wifi_calibration = get_cbmem_addr(ptr);
}

static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info)
{
struct lb_range *ramoops = (struct lb_range *)ptr;
Expand Down Expand Up @@ -236,21 +201,6 @@ static void cb_parse_boot_media_params(unsigned char *ptr,
info->boot_media_size = bmp->boot_media_size;
}

static void cb_parse_vpd(void *ptr, struct sysinfo_t *info)
{
info->chromeos_vpd = get_cbmem_addr(ptr);
}

static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info)
{
info->fmap_cache = get_cbmem_addr(ptr);
}

static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info)
{
info->type_c_info = get_cbmem_addr(ptr);
}

#if CONFIG(LP_TIMER_RDTSC)
static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
{
Expand All @@ -264,6 +214,57 @@ static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
}
#endif

static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
{
const struct cb_cbmem_entry *cbmem_entry = ptr;

if (cbmem_entry->size != sizeof(*cbmem_entry))
return;

switch (cbmem_entry->id) {
case CBMEM_ID_ACPI_CNVS:
info->acpi_cnvs = cbmem_entry->address;
break;
case CBMEM_ID_ACPI_GNVS:
info->acpi_gnvs = cbmem_entry->address;
break;
case CBMEM_ID_CBFS_RO_MCACHE:
info->cbfs_ro_mcache_offset = cbmem_entry->address;
info->cbfs_ro_mcache_size = cbmem_entry->size;
break;
case CBMEM_ID_CBFS_RW_MCACHE:
info->cbfs_rw_mcache_offset = cbmem_entry->address;
info->cbfs_rw_mcache_size = cbmem_entry->size;
break;
case CBMEM_ID_CONSOLE:
info->cbmem_cons = cbmem_entry->address;
break;
case CBMEM_ID_MRCDATA:
info->mrc_cache = cbmem_entry->address;
break;
case CBMEM_ID_VBOOT_WORKBUF:
info->vboot_workbuf = cbmem_entry->address;
break;
case CBMEM_ID_TIMESTAMP:
info->tstamp_table = cbmem_entry->address;
break;
case CBMEM_ID_VPD:
info->chromeos_vpd = cbmem_entry->address;
break;
case CBMEM_ID_FMAP:
info->fmap_cache = cbmem_entry->address;
break;
case CBMEM_ID_WIFI_CALIBRATION:
info->wifi_calibration = cbmem_entry->address;
break;
case CBMEM_ID_TYPE_C_INFO:
info->type_c_info = cbmem_entry->address;
break;
default:
break;
}
}

int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
Expand Down Expand Up @@ -372,33 +373,15 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;
case CB_TAG_VBOOT_WORKBUF:
cb_parse_vboot_workbuf(ptr, info);
break;
case CB_TAG_MAC_ADDRS:
cb_parse_mac_addresses(ptr, info);
break;
case CB_TAG_SERIALNO:
cb_parse_string(ptr, &info->serialno);
break;
case CB_TAG_TIMESTAMPS:
cb_parse_tstamp(ptr, info);
break;
case CB_TAG_CBMEM_CONSOLE:
cb_parse_cbmem_cons(ptr, info);
break;
case CB_TAG_ACPI_GNVS:
cb_parse_acpi_gnvs(ptr, info);
break;
case CB_TAG_ACPI_CNVS:
cb_parse_acpi_cnvs(ptr, info);
break;
case CB_TAG_BOARD_CONFIG:
cb_parse_board_config(ptr, info);
break;
case CB_TAG_WIFI_CALIBRATION:
cb_parse_wifi_calibration(ptr, info);
break;
case CB_TAG_RAM_OOPS:
cb_parse_ramoops(ptr, info);
break;
Expand All @@ -414,20 +397,14 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_BOOT_MEDIA_PARAMS:
cb_parse_boot_media_params(ptr, info);
break;
case CB_TAG_CBMEM_ENTRY:
cb_parse_cbmem_entry(ptr, info);
break;
#if CONFIG(LP_TIMER_RDTSC)
case CB_TAG_TSC_INFO:
cb_parse_tsc_info(ptr, info);
break;
#endif
case CB_TAG_VPD:
cb_parse_vpd(ptr, info);
break;
case CB_TAG_FMAP:
cb_parse_fmap_cache(ptr, info);
break;
case CB_TAG_TYPE_C_INFO:
cb_parse_type_c_info(ptr, info);
break;
default:
cb_parse_arch_specific(rec, info);
break;
Expand Down
12 changes: 6 additions & 6 deletions payloads/libpayload/tests/Makefile.inc
View file
Expand Up @@ -11,8 +11,6 @@ testobj := $(obj)/tests
endif
coverage-dir := $(testobj)/coverage_reports

coreboottop := ../../

cmockasrc := $(coreboottop)/3rdparty/cmocka
cmockaobj := $(objutil)/cmocka
CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so
Expand All @@ -34,16 +32,18 @@ TEST_CONFIG_ := CONFIG_LP_
# Default includes
TEST_CFLAGS := -include include/kconfig.h -include include/compiler.h
TEST_CFLAGS += -Iinclude -Iinclude/mock
TEST_CFLAGS += -I$(coreboottop)/src/commonlib/bsd/include
TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER))

# Test specific includes
TEST_CFLAGS += -I$(testsrc)/include -I$(testsrc)/include/mocks
TEST_CFLAGS += -I$(testsrc)/include
TEST_CFLAGS += -I$(cmockasrc)/include

# Minimal subset of warnings and errors. Tests can be less strict than actual build.
TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla
TEST_CFLAGS += -Wwrite-strings -Wno-trigraphs -Wimplicit-fallthrough
TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror
TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type

TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin

Expand Down Expand Up @@ -140,10 +140,10 @@ $($(1)-objs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file)
objcopy_wrap_flags=''; \
for sym in $$($(1)-mocks); do \
sym_line="$$$$($(HOSTOBJDUMP) -t $$@.orig \
| grep -E \"[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$\")"; \
| grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s+$$$$sym$$$$")"; \
if [ ! -z "$$$$sym_line" ] ; then \
addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \
section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \
addr="$$$$(echo "$$$$sym_line" | awk '{ print $$$$1 }')"; \
section="$$$$(echo "$$$$sym_line" | awk '{ print $$$$(NF - 2) }')"; \
objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \
fi \
done ; \
Expand Down
11 changes: 11 additions & 0 deletions src/acpi/acpi.c
View file
Expand Up @@ -1577,6 +1577,17 @@ unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
return 0;
}

void preload_acpi_dsdt(void)
{
const char *file = CONFIG_CBFS_PREFIX "/dsdt.aml";

if (!CONFIG(CBFS_PRELOAD))
return;

printk(BIOS_DEBUG, "Preloading %s\n", file);
cbfs_preload(file);
}

unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
Expand Down
2 changes: 2 additions & 0 deletions src/acpi/acpigen_dptf.c
View file
Expand Up @@ -70,6 +70,8 @@ static const char *namestring_of(enum dptf_participant participant)
return "TSR2";
case DPTF_TEMP_SENSOR_3:
return "TSR3";
case DPTF_TEMP_SENSOR_4:
return "TSR4";
case DPTF_TPCH:
return "TPCH";
default:
Expand Down
4 changes: 4 additions & 0 deletions src/acpi/acpigen_usb.c
View file
Expand Up @@ -2,6 +2,7 @@

#include <acpi/acpi.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_pld.h>
#include <acpi/acpigen.h>
#include <acpi/acpigen_usb.h>

Expand Down Expand Up @@ -132,5 +133,8 @@ void acpigen_write_typec_connector(const struct typec_connector_class_config *co
add_custom_dsd_property(dsd, port_number);
acpi_dp_write(dsd);

/* Add PLD */
acpigen_write_pld(config->pld);

acpigen_pop_len(); /* Device */
}
2 changes: 2 additions & 0 deletions src/arch/arm/include/armv4/arch/cpu.h
View file
Expand Up @@ -3,6 +3,8 @@
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__

static inline void cpu_relax(void) { }

#define asmlinkage

#endif /* __ARCH_CPU_H__ */
2 changes: 2 additions & 0 deletions src/arch/arm/include/armv7/arch/cpu.h
View file
Expand Up @@ -6,6 +6,8 @@
#include <stdint.h>
#include <device/device.h>

static inline void cpu_relax(void) { }

#define asmlinkage

struct cpu_driver {
Expand Down
3 changes: 3 additions & 0 deletions src/arch/arm64/include/armv8/arch/cpu.h
View file
Expand Up @@ -3,6 +3,9 @@
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__

/* TODO: Implement using SEV/WFE if this is ever actually used. */
static inline void cpu_relax(void) { }

#define asmlinkage

struct cpu_driver { };
Expand Down
2 changes: 2 additions & 0 deletions src/arch/ppc64/include/arch/cpu.h
View file
Expand Up @@ -5,6 +5,8 @@

#include <device/device.h>

static inline void cpu_relax(void) { }

#define asmlinkage

struct cpu_driver {
Expand Down
38 changes: 35 additions & 3 deletions src/arch/ppc64/include/arch/io.h
View file
Expand Up @@ -5,31 +5,63 @@

#include <stdint.h>

/* Set MSB to 1 to ignore HRMOR */
#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
#define LPCHC_IO_SPACE 0xD0010000
#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)

/* Enforce In-order Execution of I/O */
static inline void eieio(void)
{
asm volatile("eieio" ::: "memory");
}

static inline void outb(uint8_t value, uint16_t port)
{
asm volatile("stbcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port));
eieio();
}

static inline void outw(uint16_t value, uint16_t port)
{
asm volatile("sthcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port));
eieio();
}

static inline void outl(uint32_t value, uint16_t port)
{
asm volatile("stwcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port));
eieio();
}

static inline uint8_t inb(uint16_t port)
{
return 0;
uint8_t buffer;
asm volatile("lbzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port));
eieio();
return buffer;
}

static inline uint16_t inw(uint16_t port)
{
return 0;
uint16_t buffer;
asm volatile("lhzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port));
eieio();
return buffer;
}

static inline uint32_t inl(uint16_t port)
{
return 0;
uint32_t buffer;
asm volatile("lwzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port));
eieio();
return buffer;
}

static inline void report_istep(uint8_t step, uint8_t substep)
{
outb(step, 0x81);
outb(substep, 0x82);
}

#endif
2 changes: 2 additions & 0 deletions src/arch/riscv/include/arch/cpu.h
View file
Expand Up @@ -6,6 +6,8 @@
#include <arch/encoding.h>
#include <device/device.h>

static inline void cpu_relax(void) { }

#define asmlinkage

struct cpu_driver {
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/c_start.S
View file
Expand Up @@ -4,7 +4,7 @@
#include <cpu/x86/post_code.h>
#include <arch/ram_segs.h>

/* Place the stack in the bss section. It's not necessary to define it in the
/* Place the stack in the bss section. It's not necessary to define it in
* the linker script. */
.section .bss, "aw", @nobits
.global _stack
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/exit_car.S
View file
Expand Up @@ -62,7 +62,7 @@ _start:
btl $CPUID_FEATURE_CLFLUSH_BIT, %edx
jnc skip_clflush
#if ENV_X86_64
movabs _cbmem_top_ptr, %rax
movabs $_cbmem_top_ptr, %rax
clflush (%rax)
#else
clflush _cbmem_top_ptr
Expand Down
7 changes: 0 additions & 7 deletions src/commonlib/Makefile.inc
View file
Expand Up @@ -27,13 +27,6 @@ romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
endif
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c

bootblock-y += cbfs.c
verstage-y += cbfs.c
romstage-y += cbfs.c
ramstage-y += cbfs.c
smm-y += cbfs.c
postcar-y += cbfs.c

bootblock-y += bsd/cbfs_private.c
verstage-y += bsd/cbfs_private.c
romstage-y += bsd/cbfs_private.c
Expand Down
11 changes: 8 additions & 3 deletions src/commonlib/include/commonlib/cbmem_id.h → ...nlib/bsd/include/commonlib/bsd/cbmem_id.h
View file
@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-License-Identifier: BSD-3-Clause */

#ifndef _CBMEM_ID_H_
#define _CBMEM_ID_H_
Expand All @@ -7,7 +7,7 @@
#define CBMEM_ID_ACPI_BERT 0x42455254
#define CBMEM_ID_ACPI_CNVS 0x434e5653
#define CBMEM_ID_ACPI_GNVS 0x474e5653
#define CMBMEM_ID_ACPI_HEST 0x48455354
#define CBMEM_ID_ACPI_HEST 0x48455354
#define CBMEM_ID_ACPI_UCSI 0x55435349
#define CBMEM_ID_AFTER_CAR 0xc4787a93
#define CBMEM_ID_AGESA_RUNTIME 0x41474553
Expand Down Expand Up @@ -86,7 +86,7 @@
{ CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \
{ CBMEM_ID_ACPI_CNVS, "CHROMEOS NVS" }, \
{ CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
{ CMBMEM_ID_ACPI_HEST, "ACPI HEST " }, \
{ CBMEM_ID_ACPI_HEST, "ACPI HEST " }, \
{ CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \
{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
{ CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \
Expand All @@ -106,8 +106,10 @@
{ CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
{ CBMEM_ID_GDT, "GDT " }, \
{ CBMEM_ID_HOB_POINTER, "HOB " }, \
{ CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \
{ CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \
{ CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \
{ CBMEM_ID_MDATA_HASH, "METADATA HASH" }, \
{ CBMEM_ID_MEMINFO, "MEM INFO " }, \
{ CBMEM_ID_MMA_DATA, "MMA DATA " }, \
{ CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \
Expand Down Expand Up @@ -135,6 +137,7 @@
{ CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \
{ CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
{ CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \
{ CBMEM_ID_TPM_PPI, "TPM PPI " }, \
{ CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
{ CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \
{ CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
Expand All @@ -149,5 +152,7 @@
{ CBMEM_ID_FMAP, "FMAP "}, \
{ CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \
{ CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \
{ CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \
{ CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \
{ CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}
#endif /* _CBMEM_ID_H_ */
4 changes: 4 additions & 0 deletions src/commonlib/bsd/include/commonlib/bsd/elog.h
View file
Expand Up @@ -305,6 +305,10 @@ struct elog_event_mem_cache_update {
#define ELOG_TYPE_MI_HRPC 0xb4
#define ELOG_TYPE_MI_HR 0xb5

/* Chrome OS diagnostics-related events */
#define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6
#define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01

struct elog_event_extended_event {
uint8_t event_type;
uint32_t event_complement;
Expand Down
347 changes: 0 additions & 347 deletions src/commonlib/cbfs.c
View file

This file was deleted.

75 changes: 0 additions & 75 deletions src/commonlib/include/commonlib/cbfs.h
View file

This file was deleted.

2 changes: 1 addition & 1 deletion src/commonlib/include/commonlib/region.h
View file
Expand Up @@ -163,7 +163,7 @@ static inline int rdev_chain_full(struct region_device *child,
*
* You must ensure the buffer is large enough to hold the full region_device.
*/
static inline ssize_t rdev_readat_full(const struct region_device *rd, void *b)
static inline ssize_t rdev_read_full(const struct region_device *rd, void *b)
{
return rdev_readat(rd, b, 0, region_device_sz(rd));
}
Expand Down
35 changes: 3 additions & 32 deletions src/commonlib/storage/sdhci.c
View file
Expand Up @@ -6,14 +6,15 @@
#include "bouncebuf.h"
#include <commonlib/sd_mmc_ctrlr.h>
#include <commonlib/sdhci.h>
#include <commonlib/stdlib.h>
#include <commonlib/storage.h>
#include <delay.h>
#include <endian.h>
#include <lib.h>
#include "sdhci.h"
#include "sd_mmc.h"
#include "storage.h"
#include <timer.h>
#include <commonlib/stdlib.h>

#define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
|| (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \
Expand Down Expand Up @@ -411,36 +412,6 @@ static int sdhci_set_clock(struct sdhci_ctrlr *sdhci_ctrlr, unsigned int clock)
return 0;
}

/* Find leftmost set bit in a 32 bit integer */
static int fls(u32 x)
{
int r = 32;

if (!x)
return 0;
if (!(x & 0xffff0000u)) {
x <<= 16;
r -= 16;
}
if (!(x & 0xff000000u)) {
x <<= 8;
r -= 8;
}
if (!(x & 0xf0000000u)) {
x <<= 4;
r -= 4;
}
if (!(x & 0xc0000000u)) {
x <<= 2;
r -= 2;
}
if (!(x & 0x80000000u)) {
x <<= 1;
r -= 1;
}
return r;
}

static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr,
unsigned short power)
{
Expand Down Expand Up @@ -718,7 +689,7 @@ static int sdhci_init(struct sdhci_ctrlr *sdhci_ctrlr)
if (rv)
return rv; /* The error has been already reported */

sdhci_set_power(sdhci_ctrlr, fls(ctrlr->voltages) - 1);
sdhci_set_power(sdhci_ctrlr, __fls(ctrlr->voltages));

if (ctrlr->caps & DRVR_CAP_NO_CD) {
unsigned int status;
Expand Down
5 changes: 5 additions & 0 deletions src/cpu/Makefile.inc
View file
Expand Up @@ -56,7 +56,12 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))

cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
cpu_microcode_blob.bin-type := microcode
# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
cpu_microcode_blob.bin-align := 64
else
cpu_microcode_blob.bin-align := 16
endif

ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/Kconfig
View file
Expand Up @@ -12,7 +12,6 @@ config CPU_AMD_AGESA
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select SMM_ASEG
select SSE2

if CPU_AMD_AGESA
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/agesa/family14/Kconfig
View file
Expand Up @@ -2,4 +2,5 @@

config CPU_AMD_AGESA_FAMILY14
bool
select NO_SMM
select X86_AMD_FIXED_MTRRS
1 change: 1 addition & 0 deletions src/cpu/amd/agesa/family15tn/Kconfig
View file
Expand Up @@ -3,4 +3,5 @@
config CPU_AMD_AGESA_FAMILY15_TN
bool
select IDS_OPTIONS_HOOKED_UP
select SMM_ASEG
select X86_AMD_FIXED_MTRRS
1 change: 1 addition & 0 deletions src/cpu/amd/agesa/family16kb/Kconfig
View file
Expand Up @@ -2,6 +2,7 @@

config CPU_AMD_AGESA_FAMILY16_KB
bool
select SMM_ASEG
select X86_AMD_FIXED_MTRRS

if CPU_AMD_AGESA_FAMILY16_KB
Expand Down
15 changes: 0 additions & 15 deletions src/cpu/amd/pi/00730F01/model_16_init.c
View file
Expand Up @@ -23,21 +23,6 @@ static void model_16_init(struct device *dev)
msr_t msr;
u32 siblings;

/*
* All cores are initialized sequentially, so the solution for APs will be created
* before they start.
*/
x86_setup_mtrrs_with_detect();
/*
* Enable ROM caching on BSP we just lost when creating MTRR solution, for faster
* execution of e.g. AmdInitLate
*/
if (boot_cpu()) {
mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
}
x86_mtrr_check();

/* zero the machine check error status registers */
mca_clear_status();

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/pi/Kconfig
View file
Expand Up @@ -10,7 +10,7 @@ config CPU_AMD_PI
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
select SMM_ASEG
select NO_SMM
select SSE2

if CPU_AMD_PI
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/hyperthreading/intel_sibling.c
View file
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/hyperthreading.h>
#include <device/device.h>
#include <option.h>
#include <smp/spinlock.h>

/* Intel hyper-threading requires serialized CPU init. */

Expand Down
1 change: 0 additions & 1 deletion src/cpu/x86/64bit/exit32.inc
View file
Expand Up @@ -68,7 +68,6 @@ __longmode_compatibility:
movl %eax, %es
movl %eax, %ss
movl %eax, %fs
movl %eax, %gs

/* Disable paging. */
movl %cr0, %eax
Expand Down
14 changes: 10 additions & 4 deletions src/cpu/x86/64bit/mode_switch.S
View file
Expand Up @@ -15,6 +15,10 @@ protected_mode_call_narg:
push %r14
push %r15

/* Backup gs to stack */
movl %gs, %eax
push %rax

/* Arguments to stack */
push %rdi
push %rsi
Expand All @@ -23,9 +27,9 @@ protected_mode_call_narg:

#include <cpu/x86/64bit/exit32.inc>

movl -48(%ebp), %eax /* Argument count */
movl -64(%ebp), %edx /* Argument 0 */
movl -72(%ebp), %ecx /* Argument 1 */
movl -56(%ebp), %eax /* Argument count */
movl -72(%ebp), %edx /* Argument 0 */
movl -80(%ebp), %ecx /* Argument 1 */

/* Align the stack */
andl $0xFFFFFFF0, %esp
Expand All @@ -46,7 +50,7 @@ protected_mode_call_narg:
pushl %edx /* Argument 0 */

1:
movl -56(%ebp), %ebx /* Function to call */
movl -64(%ebp), %ebx /* Function to call */
call *%ebx
movl %eax, %ebx

Expand All @@ -57,6 +61,8 @@ protected_mode_call_narg:
movl %ebx, %eax

/* Restore registers */
mov -48(%rbp), %rbx
movl %ebx, %gs
mov -40(%rbp), %r15
mov -32(%rbp), %r14
mov -24(%rbp), %r13
Expand Down
11 changes: 6 additions & 5 deletions src/cpu/x86/Kconfig
View file
@@ -1,12 +1,13 @@
config PARALLEL_MP
def_bool y
depends on !LEGACY_SMP_INIT
depends on SMP
select CPU_INFO_V2
help
This option uses common MP infrastructure for bringing up APs
in parallel. It additionally provides a more flexible mechanism
for sequencing the steps of bringing up the APs.
The code also works for just initialising the BSP in case there
are no APs.

config PARALLEL_MP_AP_WORK
def_bool n
Expand Down Expand Up @@ -164,15 +165,15 @@ config X86_AMD_FIXED_MTRRS
This option informs the MTRR code to use the RdMem and WrMem fields
in the fixed MTRR MSRs.

config X86_AMD_INIT_SIPI
config X86_INIT_NEED_1_SIPI
bool
default n
help
This option limits the number of SIPI signals sent during during the
common AP setup. Intel documentation specifies an INIT SIPI SIPI
sequence, however this doesn't work on some AMD platforms. These
newer AMD platforms don't need the 10ms wait between INIT and SIPI,
so skip that too to save some time.
sequence, however this doesn't work on some AMD and Intel platforms.
These newer AMD and Intel platforms don't need the 10ms wait between
INIT and SIPI, so skip that too to save some time.

config SOC_SETS_MSRS
bool
Expand Down
37 changes: 23 additions & 14 deletions src/cpu/x86/mp_init.c
View file
Expand Up @@ -469,7 +469,7 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap
/* Send INIT IPI to all but self. */
lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0);

if (!CONFIG(X86_AMD_INIT_SIPI)) {
if (!CONFIG(X86_INIT_NEED_1_SIPI)) {
printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
mdelay(10);

Expand Down Expand Up @@ -593,6 +593,10 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p)
return CB_ERR;
}

/* We just need to run things on the BSP */
if (!CONFIG(SMP))
return bsp_do_flight_plan(p);

/* Default to currently running CPU. */
num_cpus = allocate_cpu_devices(cpu_bus, p);

Expand Down Expand Up @@ -1061,20 +1065,11 @@ static size_t smm_stub_size(void)
return rmodule_memory_size(&smm_stub);
}

static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops)
{
/*
* Make copy of the ops so that defaults can be set in the non-const
* structure if needed.
*/
memcpy(&state->ops, ops, sizeof(*ops));

if (ops->get_cpu_count != NULL)
state->cpu_count = ops->get_cpu_count();

if (ops->get_smm_info != NULL)
ops->get_smm_info(&state->perm_smbase, &state->perm_smsize,
&state->smm_real_save_state_size);
&state->smm_real_save_state_size);

state->smm_save_state_size = MAX(state->smm_real_save_state_size, smm_stub_size());

Expand All @@ -1090,11 +1085,25 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
* Default to smm_initiate_relocation() if trigger callback isn't
* provided.
*/
if (CONFIG(HAVE_SMI_HANDLER) &&
ops->per_cpu_smm_trigger == NULL)
if (ops->per_cpu_smm_trigger == NULL)
mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
}

static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
{
/*
* Make copy of the ops so that defaults can be set in the non-const
* structure if needed.
*/
memcpy(&state->ops, ops, sizeof(*ops));

if (ops->get_cpu_count != NULL)
state->cpu_count = ops->get_cpu_count();

if (CONFIG(HAVE_SMI_HANDLER))
fill_mp_state_smm(state, ops);
}

static enum cb_err do_mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops)
{
enum cb_err ret;
Expand Down
27 changes: 27 additions & 0 deletions src/device/pci_device.c
View file
Expand Up @@ -1203,6 +1203,30 @@ static void pci_scan_hidden_device(struct device *dev)
dev->device, dev->ops ? "" : " No operations");
}

/**
* A PCIe Downstream Port normally leads to a Link with only Device 0 on it
* (PCIe spec r5.0, sec 7.3.1). As an optimization, scan only for Device 0 in
* that situation.
*
* @param bus Pointer to the bus structure.
*/
static bool pci_bus_only_one_child(struct bus *bus)
{
struct device *bridge = bus->dev;
u16 pcie_pos, pcie_flags_reg;
int pcie_type;

pcie_pos = pci_find_capability(bridge, PCI_CAP_ID_PCIE);
if (!pcie_pos)
return false;

pcie_flags_reg = pci_read_config16(bridge, pcie_pos + PCI_EXP_FLAGS);

pcie_type = (pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;

return pciexp_is_downstream_port(pcie_type);
}

/**
* Scan a PCI bus.
*
Expand Down Expand Up @@ -1232,6 +1256,9 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,

post_code(0x24);

if (pci_bus_only_one_child(bus))
max_devfn = MIN(max_devfn, 0x07);

/*
* Probe all devices/functions on this bus with some optimization for
* non-existence and single function devices.
Expand Down
159 changes: 77 additions & 82 deletions src/drivers/analogix/anx7625/anx7625.c
View file
Expand Up @@ -6,6 +6,7 @@
#include <edid.h>
#include <gpio.h>
#include <string.h>
#include <types.h>

#include "anx7625.h"

Expand Down Expand Up @@ -54,9 +55,11 @@ static int i2c_access_workaround(uint8_t bus, uint8_t saddr)
}

ret = i2c_writeb(bus, saddr, offset, 0x00);
if (ret < 0)
if (ret < 0) {
ANXERROR("Failed to access %#x:%#x\n", saddr, offset);
return ret;
return ret;
}
return 0;
}

static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset,
Expand All @@ -70,7 +73,7 @@ static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset,
ANXERROR("Failed to read i2c reg=%#x:%#x\n", saddr, offset);
return ret;
}
return *val;
return 0;
}

static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr,
Expand All @@ -80,10 +83,12 @@ static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr,

i2c_access_workaround(bus, saddr);
ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len);
if (ret < 0)
if (ret < 0) {
ANXERROR("Failed to read i2c block=%#x:%#x[len=%#x]\n", saddr,
reg_addr, len);
return ret;
return ret;
}
return 0;
}

static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr,
Expand All @@ -93,10 +98,11 @@ static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr,

i2c_access_workaround(bus, saddr);
ret = i2c_writeb(bus, saddr, reg_addr, reg_val);
if (ret < 0)
if (ret < 0) {
ANXERROR("Failed to write i2c id=%#x:%#x\n", saddr, reg_addr);

return ret;
return ret;
}
return 0;
}

static int anx7625_write_or(uint8_t bus, uint8_t saddr, uint8_t offset,
Expand Down Expand Up @@ -128,30 +134,22 @@ static int anx7625_write_and(uint8_t bus, uint8_t saddr, uint8_t offset,
static int wait_aux_op_finish(uint8_t bus)
{
uint8_t val;
int ret = -1;
int loop;

for (loop = 0; loop < 150; loop++) {
mdelay(2);
anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val);
if (!(val & AP_AUX_CTRL_OP_EN)) {
ret = 0;
break;
}
}
int ret;

if (ret != 0) {
if (!retry(150,
(anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val),
!(val & AP_AUX_CTRL_OP_EN)), mdelay(2))) {
ANXERROR("Timed out waiting aux operation.\n");
return ret;
return -1;
}

ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val);
if (ret < 0 || val & 0x0F) {
ANXDEBUG("aux status %02x\n", val);
ret = -1;
return -1;
}

return ret;
return 0;
}

static unsigned long gcd(unsigned long a, unsigned long b)
Expand Down Expand Up @@ -210,15 +208,15 @@ static int anx7625_calculate_m_n(u32 pixelclock,
ANXERROR("pixelclock %u higher than %lu, "
"output may be unstable\n",
pixelclock, PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
return 1;
return -1;
}

if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
/* pixel clock frequency is too low */
ANXERROR("pixelclock %u lower than %lu, "
"output may be unstable\n",
pixelclock, PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
return 1;
return -1;
}

post_divider = 1;
Expand All @@ -237,7 +235,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
if (post_divider > POST_DIVIDER_MAX) {
ANXERROR("cannot find property post_divider(%d)\n",
post_divider);
return 1;
return -1;
}
}

Expand All @@ -256,7 +254,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
if (pixelclock * post_divider > PLL_OUT_FREQ_ABS_MAX) {
ANXINFO("act clock(%u) large than maximum(%lu)\n",
pixelclock * post_divider, PLL_OUT_FREQ_ABS_MAX);
return 1;
return -1;
}

*m = pixelclock;
Expand Down Expand Up @@ -292,10 +290,12 @@ static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider)
ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7,
MIPI_PLL_RESET_N);

if (ret < 0)
if (ret < 0) {
ANXERROR("IO error.\n");
return ret;
}

return ret;
return 0;
}

static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
Expand All @@ -305,10 +305,8 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
int ret;
uint8_t post_divider = 0;

ret = anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n,
&post_divider);

if (ret != 0) {
if (anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n,
&post_divider) < 0) {
ANXERROR("cannot get property m n value.\n");
return -1;
}
Expand Down Expand Up @@ -385,10 +383,12 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)

ret |= anx7625_odfc_config(bus, post_divider - 1);

if (ret < 0)
if (ret < 0) {
ANXERROR("mipi dsi setup IO error.\n");
return ret;
}

return ret;
return 0;
}

static int anx7625_swap_dsi_lane3(uint8_t bus)
Expand All @@ -400,7 +400,7 @@ static int anx7625_swap_dsi_lane3(uint8_t bus)
ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val);
if (ret < 0) {
ANXERROR("IO error: access MIPI_SWAP.\n");
return -1;
return ret;
}

val |= (1 << MIPI_SWAP_CH3);
Expand Down Expand Up @@ -461,10 +461,12 @@ static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt)
ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x00);
ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x80);

if (ret < 0)
if (ret < 0) {
ANXERROR("IO error: mipi dsi enable init failed.\n");
return ret;
}

return ret;
return 0;
}

static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt)
Expand All @@ -487,12 +489,13 @@ static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt)
/* clear mute flag */
ret |= anx7625_write_and(bus, RX_P0_ADDR, AP_AV_STATUS, ~AP_MIPI_MUTE);

if (ret < 0)
if (ret < 0) {
ANXERROR("IO error: enable mipi rx failed.\n");
else
ANXINFO("success to config DSI\n");
return ret;
}

return ret;
ANXINFO("success to config DSI\n");
return 0;
}

static int sp_tx_rst_aux(uint8_t bus)
Expand Down Expand Up @@ -549,34 +552,32 @@ static int sp_tx_get_edid_block(uint8_t bus)

static int edid_read(uint8_t bus, uint8_t offset, uint8_t *pblock_buf)
{
uint8_t c, cnt = 0;
int ret, cnt;

c = 0;
for (cnt = 0; cnt < 3; cnt++) {
sp_tx_aux_wr(bus, offset);
/* set I2C read com 0x01 mot = 0 and read 16 bytes */
c = sp_tx_aux_rd(bus, 0xf1);
ret = sp_tx_aux_rd(bus, 0xf1);

if (c == 1) {
if (ret < 0) {
sp_tx_rst_aux(bus);
ANXERROR("edid read failed, reset!\n");
cnt++;
} else {
anx7625_reg_block_read(bus, RX_P0_ADDR,
AP_AUX_BUFF_START,
MAX_DPCD_BUFFER_SIZE, pblock_buf);
return 0;
if (anx7625_reg_block_read(bus, RX_P0_ADDR,
AP_AUX_BUFF_START,
MAX_DPCD_BUFFER_SIZE,
pblock_buf) >= 0)
return 0;
}
}

return 1;
return -1;
}

static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf,
uint8_t offset)
{
uint8_t c, cnt = 0;
int ret;
int ret, cnt;

/* write address only */
ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x30);
Expand All @@ -598,21 +599,21 @@ static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf,
for (cnt = 0; cnt < 3; cnt++) {
sp_tx_aux_wr(bus, offset);
/* set I2C read com 0x01 mot = 0 and read 16 bytes */
c = sp_tx_aux_rd(bus, 0xf1);
ret = sp_tx_aux_rd(bus, 0xf1);

if (c == 1) {
ret = sp_tx_rst_aux(bus);
if (ret < 0) {
sp_tx_rst_aux(bus);
ANXERROR("segment read failed, reset!\n");
cnt++;
} else {
ret = anx7625_reg_block_read(bus, RX_P0_ADDR,
AP_AUX_BUFF_START,
MAX_DPCD_BUFFER_SIZE, buf);
return ret;
if (anx7625_reg_block_read(bus, RX_P0_ADDR,
AP_AUX_BUFF_START,
MAX_DPCD_BUFFER_SIZE,
buf) >= 0)
return 0;
}
}

return ret;
return -1;
}

static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
Expand All @@ -621,9 +622,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
uint8_t offset, edid_pos;
int count, blocks_num;
uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE];
uint8_t i;
uint8_t g_edid_break = 0;
int ret;
int i, ret, g_edid_break = 0;

/* address initial */
ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50);
Expand All @@ -637,7 +636,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,

blocks_num = sp_tx_get_edid_block(bus);
if (blocks_num < 0)
return blocks_num;
return -1;

count = 0;

Expand All @@ -647,10 +646,10 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
case 1:
for (i = 0; i < 8; i++) {
offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
g_edid_break = edid_read(bus, offset,
pblock_buf);
g_edid_break = !!edid_read(bus, offset,
pblock_buf);

if (g_edid_break == 1)
if (g_edid_break)
break;

if (offset <= size - MAX_DPCD_BUFFER_SIZE)
Expand All @@ -668,11 +667,11 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf,
edid_pos = (i + count * 8) *
MAX_DPCD_BUFFER_SIZE;

if (g_edid_break == 1)
if (g_edid_break)
break;

segments_edid_read(bus, count / 2,
pblock_buf, offset);
pblock_buf, offset);
if (edid_pos <= size - MAX_DPCD_BUFFER_SIZE)
memcpy(&pedid_blocks_buf[edid_pos],
pblock_buf,
Expand Down Expand Up @@ -834,12 +833,13 @@ int anx7625_dp_start(uint8_t bus, const struct edid *edid)
anx7625_parse_edid(edid, &dt);

ret = anx7625_dsi_config(bus, &dt);
if (ret < 0)
if (ret < 0) {
ANXERROR("MIPI phy setup error.\n");
else
ANXINFO("MIPI phy setup OK.\n");
return ret;
}

return ret;
ANXINFO("MIPI phy setup OK.\n");
return 0;
}

int anx7625_dp_get_edid(uint8_t bus, struct edid *out)
Expand All @@ -866,13 +866,8 @@ int anx7625_dp_get_edid(uint8_t bus, struct edid *out)
int anx7625_init(uint8_t bus)
{
int retry_hpd_change = 50;
int retry_power_on = 3;

while (--retry_power_on) {
if (anx7625_power_on_init(bus) == 0)
break;
}
if (!retry_power_on) {
if (!retry(3, anx7625_power_on_init(bus) >= 0)) {
ANXERROR("Failed to power on.\n");
return -1;
}
Expand Down
8 changes: 8 additions & 0 deletions src/drivers/genesyslogic/gl9750/Kconfig
View file
@@ -0,0 +1,8 @@
config DRIVERS_GENESYSLOGIC_GL9750
bool "Genesys Logic GL9750"
help
GL9750 is a PCI Express Rev. 1.1 compliant card reader controller
which integrates PCI Express PHY, memory card access interface,
regulators (3.3V-to-1.2V) and card power switch. Enabling this driver
will disable L0s support, which will allow the device to enter the
PCIe L1 link state.
1 change: 1 addition & 0 deletions src/drivers/genesyslogic/gl9750/Makefile.inc
View file
@@ -0,0 +1 @@
ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9750) += gl9750.c
50 changes: 50 additions & 0 deletions src/drivers/genesyslogic/gl9750/gl9750.c
View file
@@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/* Driver for Genesys Logic GL9750 */

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "gl9750.h"

static void gl9750_enable(struct device *dev)
{
printk(BIOS_INFO, "GL9750: configure ASPM\n");

/* Set Vendor Config to be configurable */
pci_or_config32(dev, CFG, CFG_EN);

/*
* When both ASPM L0s and L1 are supported, GL9750 may not enter L1.
* So disable L0s support.
*/
pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT);

/* Set Vendor Config to be non-configurable */
pci_and_config32(dev, CFG, ~CFG_EN);
}

static struct device_operations gl9750_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci,
.enable = gl9750_enable
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_GLI_9750,
0
};

static const struct pci_driver genesyslogic_gl9750 __pci_driver = {
.ops = &gl9750_ops,
.vendor = PCI_VENDOR_ID_GLI,
.devices = pci_device_ids,
};

struct chip_operations drivers_generic_genesyslogic_gl9750_ops = {
CHIP_NAME("Genesys Logic GL9750")
};
13 changes: 13 additions & 0 deletions src/drivers/genesyslogic/gl9750/gl9750.h
View file
@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef DRIVERS_GENESYSLOGIC_GL9750_H
#define DRIVERS_GENESYSLOGIC_GL9750_H

/* Definitions for Genesys Logic GL9750 */

#define CFG 0x800
#define CFG_EN 0x1
#define CFG2 0x848
#define CFG2_L0S_SUPPORT (0x1 << 6)

#endif /* DRIVERS_GENESYSLOGIC_GL9750_H */
2 changes: 2 additions & 0 deletions src/drivers/gfx/generic/chip.h
View file
Expand Up @@ -29,6 +29,8 @@ struct drivers_gfx_generic_privacy_screen_config {
struct drivers_gfx_generic_device_config {
/* ACPI device name of the output device */
const char *name;
/* Value to use for _HID Name, will take precedence over _ADR */
const char *hid;
/* The address of the output device. See section A.3.2 */
unsigned int addr;
/* Electronic privacy screen specific config */
Expand Down
6 changes: 5 additions & 1 deletion src/drivers/gfx/generic/generic.c
View file
Expand Up @@ -121,7 +121,11 @@ static void gfx_fill_ssdt_generator(const struct device *dev)

for (i = 0; i < config->device_count; i++) {
acpigen_write_device(config->device[i].name);
acpigen_write_name_integer("_ADR", config->device[i].addr);
if (config->device[i].hid)
acpigen_write_name_string("_HID", config->device[i].hid);
else
acpigen_write_name_integer("_ADR", config->device[i].addr);

acpigen_write_name_integer("_STA", 0xF);
gfx_fill_privacy_screen_dsm(&config->device[i].privacy);
acpigen_pop_len(); /* Device */
Expand Down
17 changes: 17 additions & 0 deletions src/drivers/i2c/tpm/chip.c
View file
Expand Up @@ -11,6 +11,7 @@

static void i2c_tpm_fill_ssdt(const struct device *dev)
{
struct acpi_dp *dsd;
struct drivers_i2c_tpm_config *config = dev->chip_info;
const char *scope = acpi_device_scope(dev);
struct acpi_i2c i2c = {
Expand Down Expand Up @@ -47,6 +48,22 @@ static void i2c_tpm_fill_ssdt(const struct device *dev)

acpigen_write_resourcetemplate_footer();

/* _DSD, Device-Specific Data */
dsd = acpi_dp_new_table("_DSD");
switch (config->power_managed_mode) {
case TPM_FIRMWARE_POWER_MANAGED:
acpi_dp_add_integer(dsd, "firmware-power-managed", 1);
break;
case TPM_KERNEL_POWER_MANAGED:
acpi_dp_add_integer(dsd, "firmware-power-managed", 0);
break;
case TPM_DEFAULT_POWER_MANAGED:
default:
/* Leave firmware-power-managed unset */
break;
}
acpi_dp_write(dsd);

acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */

Expand Down
7 changes: 7 additions & 0 deletions src/drivers/i2c/tpm/chip.h
View file
Expand Up @@ -3,11 +3,18 @@
#include <acpi/acpi_device.h>
#include <device/i2c_simple.h>

enum tpm_power_managed_mode {
TPM_DEFAULT_POWER_MANAGED = 0,
TPM_FIRMWARE_POWER_MANAGED,
TPM_KERNEL_POWER_MANAGED,
};

struct drivers_i2c_tpm_config {
const char *hid; /* ACPI _HID (required) */
const char *desc; /* Device Description */
unsigned int uid; /* ACPI _UID */
enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */
struct acpi_irq irq; /* Interrupt */
struct acpi_gpio irq_gpio; /* GPIO interrupt */
enum tpm_power_managed_mode power_managed_mode; /* TPM power managed mode */
};
4 changes: 2 additions & 2 deletions src/drivers/intel/dptf/dptf.c
View file
Expand Up @@ -192,7 +192,7 @@ static void write_generic_devices(const struct drivers_intel_dptf_config *config
get_STA_value(config, DPTF_CHARGER),
platform_info);

for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < 4; ++i, ++participant) {
for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < DPTF_MAX_TSR; ++i, ++participant) {
snprintf(name, sizeof(name), "TSR%1d", i);
dptf_write_generic_participant(name, DPTF_GENERIC_PARTICIPANT_TYPE_TSR,
NULL, get_STA_value(config, participant),
Expand Down Expand Up @@ -449,7 +449,7 @@ static void write_options(const struct drivers_intel_dptf_config *config)
acpigen_pop_len(); /* Scope */

/* TSR options */
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) {
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) {
if (is_participant_used(config, p) && (config->options.tsr[i].hysteresis ||
config->options.tsr[i].desc)) {
dptf_write_scope(p);
Expand Down
10 changes: 10 additions & 0 deletions src/drivers/intel/mipi_camera/camera.c
View file
Expand Up @@ -5,7 +5,9 @@
#include <acpi/acpi_device.h>
#include <acpi/acpigen.h>
#include <acpi/acpigen_pci.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/cpu_ids.h>
#include <device/i2c_simple.h>
#include <device/device.h>
#include <device/path.h>
Expand Down Expand Up @@ -134,6 +136,14 @@ static void camera_fill_cio2(const struct device *dev)

snprintf(name, sizeof(name), "port%u", i);
port_name[i] = strdup(name);
if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) {
u32 cpu_id = cpu_get_cpuid();
if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1)
acpi_dp_add_integer(dsd, "is_es", 1);
else
acpi_dp_add_integer(dsd, "is_es", 0);
}

acpi_dp_add_child(dsd, port_name[i], port_table);
}

Expand Down
28 changes: 26 additions & 2 deletions src/drivers/intel/usb4/retimer/retimer.c
View file
Expand Up @@ -341,6 +341,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
static char dfp[DEVICE_PATH_MAX];
struct acpi_pld pld;
uint8_t dfp_port, usb_port;
int ec_port = 0;

usb4_retimer_scope = acpi_device_scope(dev);
if (!usb4_retimer_scope || !config)
Expand All @@ -365,8 +366,14 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
usb_device = config->dfp[dfp_port].typec_port;
usb_port = usb_device->path.usb.port_id;

ec_port = retimer_get_index_for_typec(usb_port);
if (ec_port == -1) {
printk(BIOS_ERR, "%s: No relative EC port found for TC port %d\n",
__func__, usb_port);
continue;
}
/* DFPx */
snprintf(dfp, sizeof(dfp), "DFP%1d", usb_port);
snprintf(dfp, sizeof(dfp), "DFP%1d", ec_port);
acpigen_write_device(dfp);
/* _ADR part is for the lane adapter */
acpigen_write_ADR(dfp_port*2 + 1);
Expand Down Expand Up @@ -396,7 +403,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
/* Return (Buffer (One) { 0x0 }) */
acpigen_write_return_singleton_buffer(0x0);
acpigen_pop_len();
usb4_retimer_write_dsm(usb_port, INTEL_USB4_RETIMER_DSM_UUID,
usb4_retimer_write_dsm(ec_port, INTEL_USB4_RETIMER_DSM_UUID,
usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks),
(void *)&config->dfp[dfp_port].power_gpio);
/* Default case: Return (Buffer (One) { 0x0 }) */
Expand Down Expand Up @@ -436,3 +443,20 @@ __weak const char *ec_retimer_fw_update_path(void)
__weak void ec_retimer_fw_update(uint8_t data)
{
}

/*
* This function will convert CPU physical port mapping to abstract
* EC port mapping.
* For example, board might have enabled TCSS port 1 and 3 as per physical
* port mapping. Since only 2 TCSS ports are enabled EC will index it as port 0
* and port 1. So there will be an issue when coreboot sends command to EC for
* port 3 (with coreboot index of 2). EC will produce an error due to wrong index.
*
* Note: Each SoC code using retimer driver needs to implement this function
* since SoC will have physical port details.
*/
__weak int retimer_get_index_for_typec(uint8_t typec_port)
{
/* By default assume that retimer port index = Type C port */
return (int)typec_port;
}
10 changes: 10 additions & 0 deletions src/drivers/intel/usb4/retimer/retimer.h
View file
Expand Up @@ -30,5 +30,15 @@ struct usb4_retimer_dsm_uuid {

const char *ec_retimer_fw_update_path(void);
void ec_retimer_fw_update(uint8_t data);
/*
* This function will convert CPU physical port mapping to abstract
* EC port mapping. For example, board might have enabled TCSS port 1
* and 3 as per physical port mapping. Since only 2 TCSS ports are enabled
* EC will name it as port 0 and port 1. So there will be mismatch when
* coreboot sends index for port 3.
* Each SoC code using retimer driver needs to implement this function
* since SoC will have physical port details.
*/
int retimer_get_index_for_typec(uint8_t typec_port);

#endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */
11 changes: 9 additions & 2 deletions src/drivers/net/r8168.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <delay.h>
#include <fmap.h>
#include <types.h>
Expand Down Expand Up @@ -360,10 +361,16 @@ static struct device_operations r8168_ops = {
#endif
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_REALTEK_8168,
PCI_DEVICE_ID_REALTEK_8125,
0
};

static const struct pci_driver r8168_driver __pci_driver = {
.ops = &r8168_ops,
.vendor = 0x10ec,
.device = 0x8168,
.vendor = PCI_VENDOR_ID_REALTEK,
.devices = pci_device_ids,
};

struct chip_operations drivers_net_ops = {
Expand Down
17 changes: 0 additions & 17 deletions src/drivers/smmstore/Kconfig
View file
Expand Up @@ -19,27 +19,10 @@ config SMMSTORE_V2
By using version 2 you cannot make use of software that expects
a version 1 SMMSTORE.

config SMMSTORE_IN_CBFS
bool
default n
help
Select this if you want to add an SMMSTORE region to a
cbfsfile in a cbfs FMAP region

if SMMSTORE
config SMMSTORE_REGION
string "fmap region in which SMM store file is kept" if SMMSTORE_IN_CBFS
default "RW_LEGACY" if CHROMEOS && SMMSTORE_IN_CBFS
default "COREBOOT" if SMMSTORE_IN_CBFS
default "SMMSTORE"

config SMMSTORE_FILENAME
string "SMM store file name" if SMMSTORE_IN_CBFS
default "smm_store"

config SMMSTORE_SIZE
hex "size of the SMMSTORE FMAP region"
depends on !SMMSTORE_IN_CBFS
default 0x40000
help
Sets the size of the default SMMSTORE FMAP region.
Expand Down
28 changes: 7 additions & 21 deletions src/drivers/smmstore/store.c
View file
@@ -1,14 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <boot_device.h>
#include <cbfs.h>
#include <fmap.h>
#include <commonlib/helpers.h>
#include <commonlib/region.h>
#include <console/console.h>
#include <smmstore.h>
#include <types.h>

#define SMMSTORE_REGION "SMMSTORE"

/*
* The region format is still not finalized, but so far it looks like this:
* (
Expand All @@ -33,26 +34,11 @@

static enum cb_err lookup_store_region(struct region *region)
{
if (CONFIG(SMMSTORE_IN_CBFS)) {
struct cbfsf file;
if (cbfs_locate_file_in_region(&file,
CONFIG_SMMSTORE_REGION,
CONFIG_SMMSTORE_FILENAME, NULL) < 0) {
printk(BIOS_WARNING,
"smm store: Unable to find SMM store file in region '%s'\n",
CONFIG_SMMSTORE_REGION);
return CB_ERR;
}
struct region_device rdev;
cbfs_file_data(&rdev, &file);
*region = *region_device_region(&rdev);
} else {
if (fmap_locate_area(CONFIG_SMMSTORE_REGION, region)) {
printk(BIOS_WARNING,
"smm store: Unable to find SMM store FMAP region '%s'\n",
CONFIG_SMMSTORE_REGION);
return CB_ERR;
}
if (fmap_locate_area(SMMSTORE_REGION, region)) {
printk(BIOS_WARNING,
"smm store: Unable to find SMM store FMAP region '%s'\n",
SMMSTORE_REGION);
return CB_ERR;
}

return CB_SUCCESS;
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/uart/Kconfig
View file
Expand Up @@ -5,7 +5,7 @@ config DRIVERS_UART_8250IO
# FIXME: Shouldn't have a prompt, should default to n, and
# should be selected by boards that have it instead.
bool "Serial port on SuperIO"
depends on ARCH_X86
depends on ARCH_X86 || ARCH_PPC64
default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL
default n if NO_UART_ON_SUPERIO
default y
Expand Down
26 changes: 26 additions & 0 deletions src/ec/google/chromeec/ec_acpi.c
View file
Expand Up @@ -2,6 +2,7 @@

#include <acpi/acpi.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_pld.h>
#include <acpi/acpigen.h>
#include <acpi/acpigen_ps2_keybd.h>
#include <acpi/acpigen_usb.h>
Expand Down Expand Up @@ -117,6 +118,27 @@ static void add_port_location(struct acpi_dp *dsd, int port_number)
acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location));
}

static void get_pld_from_usb_ports(struct acpi_pld *pld,
struct device *usb2_port, struct device *usb3_port,
struct device *usb4_port)
{
struct drivers_usb_acpi_config *config = NULL;

if (usb4_port)
config = usb4_port->chip_info;
else if (usb3_port)
config = usb3_port->chip_info;
else if (usb2_port)
config = usb2_port->chip_info;

if (config) {
if (config->use_custom_pld)
*pld = config->custom_pld;
else
acpi_pld_fill_usb(pld, config->type, &config->group);
}
}

static void fill_ssdt_typec_device(const struct device *dev)
{
struct ec_google_chromeec_config *config = dev->chip_info;
Expand All @@ -126,6 +148,7 @@ static void fill_ssdt_typec_device(const struct device *dev)
struct device *usb2_port;
struct device *usb3_port;
struct device *usb4_port;
struct acpi_pld pld = {0};

if (google_chromeec_get_num_pd_ports(&num_ports))
return;
Expand All @@ -146,6 +169,8 @@ static void fill_ssdt_typec_device(const struct device *dev)
usb4_port = NULL;
get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port);

get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port);

struct typec_connector_class_config typec_config = {
.power_role = port_caps.power_role_cap,
.try_power_role = port_caps.try_power_role_cap,
Expand All @@ -156,6 +181,7 @@ static void fill_ssdt_typec_device(const struct device *dev)
.orientation_switch = config->mux_conn[i],
.usb_role_switch = config->mux_conn[i],
.mode_switch = config->mux_conn[i],
.pld = &pld,
};

acpigen_write_typec_connector(&typec_config, i, add_port_location);
Expand Down
6 changes: 3 additions & 3 deletions src/ec/google/chromeec/ec_dptf_helpers.c
View file
Expand Up @@ -265,7 +265,7 @@ static void write_dppm_methods(const struct device *ec)

/* Local0 = ToInteger(Arg0) */
acpigen_write_to_integer(ARG0_OP, LOCAL0_OP);
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) {
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) {
snprintf(name, sizeof(name), "^TSR%1d", i);
acpigen_write_if_lequal_op_int(LOCAL0_OP, i);
acpigen_notify(name, THERMAL_EVENT);
Expand All @@ -277,7 +277,7 @@ static void write_dppm_methods(const struct device *ec)

/* TPET */
acpigen_write_method("TPET", 0);
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) {
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) {
snprintf(name, sizeof(name), "^TSR%1d", i);
acpigen_notify(name, TRIP_POINTS_CHANGED_EVENT);
}
Expand Down Expand Up @@ -355,6 +355,6 @@ void ec_fill_dptf_helpers(const struct device *ec)
write_charger_methods(ec);
write_fan_methods(ec);

for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i)
for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i)
write_thermal_methods(ec, p, i);
}
57 changes: 57 additions & 0 deletions src/ec/starlabs/merlin/Kconfig
View file
@@ -0,0 +1,57 @@
## SPDX-License-Identifier: GPL-2.0-only

config EC_STARLABS_ITE
bool
select EC_ACPI
help
Interface to ITE embedded controller principally in Star Labs notebooks.
Works with closed-source ITE firmware versions:
TGL - 1.00 or later
CML - 1.04 or later
KBL - 3.12 or later
And open-source Merlin firmware version 1.00 or later

config EC_STARLABS_NEED_ITE_BIN
bool
depends on EC_STARLABS_ITE
help
Select if the mainboard requires EC firmware in the main flash chip.

config EC_STARLABS_ADD_ITE_BIN
bool "Add Star Labs EC binary file"
default n
depends on EC_STARLABS_NEED_ITE_BIN
help
Select to add an EC firmware binary into the coreboot image. EC firmware
is necessary, flashing a coreboot image without EC firmware will render
your laptop unusable.

config EC_STARLABS_ITE_BIN_PATH
string "Star Labs EC binary file path"
depends on EC_STARLABS_ADD_ITE_BIN

config EC_STARLABS_KBL_LEVELS
bool
default n
depends on EC_STARLABS_ITE
help
Select if the mainboard supports multiple levels of brightness for the keyboard.

config EC_STARLABS_FAN
bool
default n
depends on EC_STARLABS_ITE
help
Select if the mainboard has a fan.

config EC_STARLABS_MERLIN
bool "Use open-source Merlin EC Firmware"
default n
depends on EC_STARLABS_ITE
help
Use open source embedded controller firmware. Both firmwares have the
same features but differ in licensing and compilers.

config EC_VARIANT_DIR
string
default "merlin" if EC_STARLABS_MERLIN
28 changes: 28 additions & 0 deletions src/ec/starlabs/merlin/Makefile.inc
View file
@@ -0,0 +1,28 @@
## SPDX-License-Identifier: GPL-2.0-only

ifeq ($(CONFIG_EC_STARLABS_ITE),y)

PHONY+=add_ite_fw
INTERMEDIATE+=add_ite_fw

EC_VARIANT_DIR := $(call strip_quotes, $(CONFIG_EC_VARIANT_DIR))
CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR)

all-y += ec.c

ifeq ($(CONFIG_EC_STARLABS_NEED_ITE_BIN),y)
ifeq ($(CONFIG_EC_STARLABS_ADD_ITE_BIN),y)
add_ite_fw: $(obj)/coreboot.pre
$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_ITE_BIN_PATH) -u
else
files_added:: warn_no_ite_fw

PHONY+=warn_no_ite_fw
warn_no_ite_fw:
printf "\n\t** WARNING **\n"
printf "coreboot has been built without the ITE EC Firmware.\n"
printf "Do not flash this image. Your laptop's power button\n"
printf "may not respond when you press it.\n\n"
endif
endif
endif
21 changes: 21 additions & 0 deletions src/ec/starlabs/merlin/acpi/ac.asl
View file
@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */

Device (ADP1)
{
Name (_HID, "ACPI0003")
Method (_STA)
{
Return (0x0F)
}
Method (_PSR, 0)
{
PWRS = ECPS & 0x01
Return(PWRS)
}
Method (_PCL, 0)
{
Return (
Package() { _SB }
)
}
}
68 changes: 68 additions & 0 deletions src/ec/starlabs/merlin/acpi/battery.asl
View file
@@ -0,0 +1,68 @@
/* SPDX-License-Identifier: GPL-2.0-only */

Device (BAT0)
{
Name (_HID, EisaId("PNP0C0A"))
Name (_UID, 0)
Method (_STA, 0, NotSerialized)
{
// Battery Status
// 0x80 BIT1 0x01 = Present
// 0x80 BIT1 0x00 = Not Present
If(ECPS & 0x02)
{
Return(0x1F)
}
Return(0x0F)
}
Name (BPKG, Package(13)
{
1, // 0: Power Unit
0xFFFFFFFF, // 1: Design Capacity
0xFFFFFFFF, // 2: Last Full Charge Capacity
1, // 3: Battery Technology(Rechargeable)
0xFFFFFFFF, // 4: Design Voltage 10.8V
0, // 5: Design capacity of warning
0, // 6: Design capacity of low
100, // 7: Battery capacity granularity 1
0, // 8: Battery capacity granularity 2
"597077-3S", // 9: Model Number
"3ICP6/70/77", // 10: Serial Number
"Real", // 11: Battery Type
"DGFGE" // 12: OEM Information
})
Method (_BIF, 0, Serialized)
{
BPKG[1] = B1DC
BPKG[2] = B1FC
BPKG[4] = B1DV
If(B1FC)
{
BPKG[5] = B1FC / 10
BPKG[6] = B1FC / 100
BPKG[7] = B1DC / 100
}
Return(BPKG)
}
Name (PKG1, Package (4)
{
0xFFFFFFFF, // Battery State
0xFFFFFFFF, // Battery Present Rate
0xFFFFFFFF, // Battery Remaining Capacity
0xFFFFFFFF, // Battery Present Voltage
})
Method (_BST, 0, NotSerialized)
{
PKG1[0] = (B1ST & 0x07)
PKG1[1] = B1PR
PKG1[2] = B1RC
PKG1[3] = B1PV
Return(PKG1)
}
Method (_PCL, 0, NotSerialized)
{
Return (
Package() { _SB }
)
}
}
33 changes: 33 additions & 0 deletions src/ec/starlabs/merlin/acpi/cmos.asl
View file
@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-only */

OperationRegion (CMOS, SystemIO, 0x70, 0x2)
Field (CMOS, ByteAcc, NoLock, Preserve)
{
IND1, 8,
DAT1, 8,
}

IndexField (IND1, DAT1, ByteAcc, NoLock, Preserve)
{
Offset (0x4b),
KLTC, 8, // Keyboard Backlight Timeout
FCLS, 8, // Ctrl Fn Reverse (make keyboard Apple-like)
MXCH, 8, // Max Charge Level
FNMD, 8, // Fan Mode
}

OperationRegion (CMS2, SystemIO, 0x72, 0x2)
Field (CMS2, ByteAcc, NoLock, Preserve)
{
IND2, 8,
DAT2, 8,
}

IndexField (IND2, DAT2, ByteAcc, NoLock, Preserve)
{
Offset (0x80),
FLKS, 8, // Function Lock State
TPLS, 8, // Trackpad State
KLBC, 8, // Keyboard Backlight Brightness
KLSC, 8, // Keyboard Backlight State
}