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Expand Up @@ -20,6 +20,62 @@ devicetree. Note, not all mainboards will have the devicetree/overridetree
distinction, and may only have a devicetree.cb file. Or you can always just
write the ASL (ACPI Source Language) code yourself.

### Naming and referencing devices

When declaring a device, it can optionally be given an alias that can be
referred to elsewhere. This is particularly useful to declare a device in one
device tree while allowing its configuration to be more easily changed in an
overlay. For instance, the AMD Picasso SoC definition
(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
by default:

```
chip soc/amd/picasso
device domain 0 on
...
device pci 00.2 alias iommu off end
...
end
end
```

A device based on this SoC can override the configuration for the IOMMU without
duplicating addresses, as in
`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:

```
chip soc/amd/picasso
device domain 0
...
device ref iommu on end
...
end
end
```

In this example the override simply enables the IOMMU, but it could also
set additional properties (or even add child devices) inside the IOMMU `device`
block.

---

It is important to note that devices that use `device ref` syntax to override
previous definitions of a device by alias must be placed at **exactly the same
location in the device tree** as the original declaration. If not, this will
actually create another device rather than overriding the properties of the
existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
were written as follows:

```
chip soc/amd/picasso
# NOTE: not inside domain 0!
device ref iommu on end
end
```

Then this would leave the SoC's IOMMU disabled, and instead create a new device
with no properties as a direct child of the SoC.

## Device drivers

Let's take a look at an example entry from
Expand Down
9 changes: 8 additions & 1 deletion Documentation/mainboard/index.md
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Expand Up @@ -180,8 +180,15 @@ The boards in this section are not real mainboards, but emulators.

## System76

- [Adder Workstation 1](system76/addw1.md)
- [Adder Workstation 2](system76/addw2.md)
- [Darter Pro 6](system76/darp6.md)
- [Darter Pro 7](system76/darp7.md)
- [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md)
- [Gazelle 15](system76/gaze15.md)
- [Lemur Pro](system76/lemp9.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md)

Expand Down
8 changes: 1 addition & 7 deletions Documentation/mainboard/kontron/mal10.md
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Expand Up @@ -73,20 +73,14 @@ PECI is not supported by Apollo Lake Pentium/Celeron/Atom processors and the CPU
temperature value is taken from a thermal resistor (NTC) that is placed very
close to the CPU.

## Known issues

- Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91
Booting with the "CorebootPayload" [crashes].
- Tianocore outputs video through an external GPU only.

## Untested

- IGD/LVDS
- SDIO

## Tested and working

- Kontron CPLD/EC (Serial ports, I2C port)
- Kontron CPLD/EC (Serial ports, I2C port, GPIOs)
- NCT7802 [HWM](#Hardware Monitor)
- USB2/3
- Gigabit Ethernet ports
Expand Down
40 changes: 27 additions & 13 deletions Documentation/mainboard/ocp/deltalake.md
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Expand Up @@ -6,31 +6,42 @@ Delta Lake server platform.
## Introduction

OCP Delta Lake server platform is a component of multi-host server system
Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020].
Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design
spec] were contributed to [OCP].

Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
Intel Cooper Lake Scalable Processor was launched in Q2 2020.

Yosemite-V3 has multiple configurations. Depending on configurations, it may
host up to 4 Delta Lake servers (blades) in one sled.

The Yosemite-V3 system is in mass production. Facebook, Intel and partners
jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
OSF solution reached DVT exit equivalent status.
OSF solution reached production quality for some use cases in July, 2021.

## Required blobs
## How to build

Delta Lake server OSF solution requires:
OSF code base is public at
https://github.com/opencomputeproject/OpenSystemFirmware

Run following commands to build Delta Lake OSF image from scratch:
git clone https://github.com/opencomputeproject/OpenSystemFirmware.git
cd OpenSystemFirmware/Wiwynn/deltalake && ./download_and_build.sh

The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
Linux kernel and u-root code from their upstream repo, and sync down needed
binary blobs. [osf-builder] also provides the top level build system.

Delta Lake server OSF solution requires following binary blobs:
- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
is not yet available to the public. It will be made public soon by Intel
with redistributable license.
- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git.
- ME binary: Ignition binary will be made public soon by Intel with
redistributable license.
can be downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
coreboot.org mirrors this repo and by default the correct binary is included.
- ME binary: Ignition binary can be downloaded from
https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
- ACM binaries: only required for CBnT enablement. Available under NDA with Intel.

## Payload
- LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload.
- Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
U-root as initramfs, is used in the joint development. It can be built
following [All about u-root].

Expand Down Expand Up @@ -65,7 +76,7 @@ VPD variables supported are:
mapped to verbose, 0 to 4 and 9 would be mapped to quiet.
- VPDs affecting coreboot are listed/documented in [src/mainboard/ocp/deltalake/vpd.h].

## Working features
## Features
The solution is developed using LinuxBoot payload with Linux kernel 5.2.9,
and [u-root] as initramfs.
- SMBIOS:
Expand Down Expand Up @@ -174,6 +185,9 @@ and [u-root] as initramfs.
```

[OCP]: https://www.opencompute.org
[Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specification-1v05-pdf
[Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf
[osf-builder]: https://github.com/facebookincubator/osf-builder
[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
[flashrom]: https://flashrom.org/Flashrom
[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
Expand Down
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# System76 Adder Workstation 1 (addw1)

## Specs

- CPU
- Intel Core i7-9750H
- Intel Core i9-9980HK
- Chipset
- Intel HM370
- EC
- ITE IT8587E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel UHD Graphics 630
- NVIDIA GeForce RTX 2070
- eDP 15.6" 3840x2160 OLED (Samsung ATNA56WR06)
- 1x HDMI
- 1x Mini DisplayPort 1.3
- 1x DisplayPort 1.3 over USB-C
- Memory:
- Up to 64GB dual-channel DDR4 @ 2666 MHz, or
- Up to 32GB dual-channel DDR4 @ 3000 MHz
- Networking
- Gigabit Ethernet
- Intel Wireless-AC
- Power
- 230W (19.5V, 11.8A) AC adapter
- Removable 62Wh 6-cell battery
- Sound
- Realtek ALC1220 codec
- TAS5825MRHBR smart AMP
- Internal speakers and microphone
- Combined headphone and microphone 3.5mm jack
- Combined microphone and S/PDIF 3.5mm jack
- HDMI, Mini DisplayPort, USB-C DP audio
- Storage
- M.2 PCIe/SATA SSD1
- M.2 PCIe/SATA SSD2
- 2.5" SATA HDD/SSD
- RTS5250 SD card reader
- USB
- 1x USB Type-C with Thunderbolt 3
- 1x USB 3.1 Gen2 Type-C
- 3x USB 3.1 Gen1 Type-A

## Flashing coreboot

```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L12873F |
+---------------------+---------------------+
| Size | 16 MiB |
+---------------------+---------------------+
| Package | SOIC-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```

The flash chip (U61) is next to the battery connector.
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# System76 Adder Workstation 2 (addw2)

## Specs

- CPU
- Intel Core i7-10875H
- Chipset
- Intel HM470
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- NVIDIA GeForce RTX 2070 Super
- eDP 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR06)
- 1x HDMI
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64 (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX200/AX201
- Power
- 230W (19.5V, 11.8A) AC barrel adapter
- Chicony A17-230P1A, using a C5 power cord
- 62Wh 6-cell Lithium-Ion battery
- Sound
- Internal speakers and microphone
- Combined 3.5mm headhpone and microphone jack
- Combined 3.5mm microphone and S/PDIF jack
- HDMI, Mini DisplayPort, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- M.2 PCIe NVMe Gen 3 SSD
- 2.5" SATA 3 SSD
- SD card reader (RTS5250S)
- USB
- 1x USB Type-C with Thunderbolt 3
- 1x USB 3.2 Gen 2 Type-C
- 3x USB 3.2 Gen 1 Type-A
- Dimensions
- 35.890cm x 25.806cm x 2.997cm, 2.5kg

## Flashing coreboot

```eval_rst
+---------------------+-----------------+
| Type | Value |
+=====================+=================+
| Socketed flash | no |
+---------------------+-----------------+
| Vendor | Macronix |
+---------------------+-----------------+
| Model | MX25L12872F |
+---------------------+-----------------+
| Size | 16 MiB |
+---------------------+-----------------+
| Package | SOIC-8 |
+---------------------+-----------------+
| Internal flashing | yes |
+---------------------+-----------------+
| External flashing | yes |
+---------------------+-----------------+
```

The flash chip (U60) is next to the battery connector.
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# System76 Darter Pro 6 (darp6)

## Specs

- CPU
- Intel Core i7-10510U
- Intel Core i5-10210U
- EC
- ITE IT8587E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel UHD Graphics 620
- eDP 15.6" 1920x1080@60Hz LCD (LG LP156WFC-SPD3)
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 2666 MHz
- Networking
- Gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX200/AX201
- or Intel Wireless-AC 9560
- Power
- 65W (19V, 3.42A) AC barrel adapter
- Chicony A12-065N2A, using a C5 power cord
- 54.5Wh 4-cell Lithium-Ion battery
- Sound
- Realtek ALC293 codec
- Internal speakers and microphone
- Combined 3.5mm headphone and microphone jack
- Combined 3.5mm microphone and S/PDIF jack
- HDMI, Mini DisplayPort, USB-C DisplayPort audio
- Storage
- 1x M.2 PCIe NVMe or SATA SSD
- SD card reader
- USB
- 1x USB Type-C with Thunderbolt 3
- 2x USB 3.0 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 1.98cm x 36.04cm x 24.46cm, 1.6kg


## Flashing coreboot

```eval_rst
+---------------------+-----------------+
| Type | Value |
+=====================+=================+
| Socketed flash | no |
+---------------------+-----------------+
| Vendor | GigaDevice |
+---------------------+-----------------+
| Model | GD25B127D |
+---------------------+-----------------+
| Size | 16 MiB |
+---------------------+-----------------+
| Package | SOIC-8 |
+---------------------+-----------------+
| Internal flashing | yes |
+---------------------+-----------------+
| External flashing | yes |
+---------------------+-----------------+
```

The flash chip (U26) is right of the DIMM slots.
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# System76 Darter Pro 7 (darp7)

## Specs

- CPU
- Intel Core i5-1135G7
- Intel Core i7-1165G7
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 15.6" 1920x1080@60Hz LCD
- 1x HDMI
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 PCIe/CNVi Wifi/Bluetooth
- Intel Wi-Fi 6 AX200/201
- Power
- 65W (19V, 3.42A) AC barrel adapter
- Included: Chicony A18-065N3A, using a C5 power cord
- USB-C charging, compatible with 65W+ chargers
- 73Wh 4-cell Lithium-ion battery
- Sound
- Realtek ALC293 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 4 SSD
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB-C Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 1x USB 3.2 (Gen 2) Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 1.99cm x 35.70cm x 22.05cm, 1.74kg

## Flashing coreboot

```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B127D |
+---------------------+---------------------+
| Size | 16 MiB |
+---------------------+---------------------+
| Package | SOIC-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```

The flash chip (U12) is above the left DIMM slot.
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# System76 Galago Pro 4 (galp4)

## Specs

- CPU
- Intel Core i7-10510U
- Intel Core i5-10210U
- EC
- ITE IT8587E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel UHD Graphics 620
- eDP 14.1" 1920x1080@60Hz LCD (Innolux N140HCA-EAC)
- 1x HDMI
- 1x Mini DisplayPort 1.2
- 1x DisplayPort over USB-C
- Memory
- Up to 64 (2x32GB) dual-channel DDR4 SO-DIMMs @ 2666 MHz
- Networking
- Gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX200/AX201
- or Intel Wireless-AC 9560
- Power
- 40W (19V, 2.1A) AC barrel adapter
- Chicony A13-040A3A, using a C5 power cord
- 35.3Wh 3-cell Lithium-Ion battery
- Sound
- Realtek ALC293 codec
- Internal speakers and microphone
- 3.5mm headphone jack
- 3.5mm microphone jack
- HDMI, Mini DisplayPort, USB-C DisplayPort audio
- Storage
- 1x M.2 PCIe NVMe or SATA SSD
- 1x 2.5" SATA SSD
- SD card reader
- USB
- 1x USB Type-C with Thunderbolt 3
- 2x USB 3.1 Gen 1 Type-A
- Dimensions
- 1.8cm x 33cm x 22.5cm, 1.3kg

## Flashing coreboot

```eval_rst
+---------------------+-----------------+
| Type | Value |
+=====================+=================+
| Socketed flash | no |
+---------------------+-----------------+
| Vendor | GigaDevice |
+---------------------+-----------------+
| Model | GD25B127D |
+---------------------+-----------------+
| Size | 16 MiB |
+---------------------+-----------------+
| Package | SOIC-8 |
+---------------------+-----------------+
| Internal flashing | yes |
+---------------------+-----------------+
| External flashing | yes |
+---------------------+-----------------+
```

The flash chip (U25) is right of the DIMM slots.
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# System76 Galago Pro 5 (galp5)

## Specs

- CPU
- Intel Core i7-1165G7
- Intel Core i5-1135G7
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- dGPU options
- NVIDIA GeForce 1650
- NVIDIA GeForce 1650 Ti
- eDP 14.1" 1920x1080@60Hz LCD (BOE NV140FHM-N62)
- 1x HDMI
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64 (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX200/AX201
- Power
- with Intel iGPU only
- 65W (19V, 3.42A) AC barrel adapter
- USB-C charging compatible with 65W+ charger
- with NVIDIA dGPU
- 90W (19V, 4.74A) AC barrel adapter
- USB-C charging compatible with 90W+ charger
- Sound
- Realtek ALC293D codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- SD card reader
- USB
- 2x USB 3.2 (Gen 1) Type-A
- 1x USB 3.2 (Gen 2) Type-C
- 1x USB Type-C with Thunderbolt 4
- Dimensions
- 32.49cm x 22.5cm x 1.75cm, 1.41kg

## Flashing coreboot

```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B127D |
+---------------------+---------------------+
| Size | 16 MiB |
+---------------------+---------------------+
| Package | SOIC-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```

The flash chip (U33) is next to the M.2 WiFi card.
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# System76 Lemur Pro 10 (lemp10)

## Specs

- CPU
- Intel Core i7-1165G7
- Intel Core i5-1135G7
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.0" 1920x1080@60Hz LCD
- 1x HDMI
- 1x DisplayPort 1.4 over USB-C
- Memory
- Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE x 8)
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
- Networking
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX200/AX201
- Power
- 65W (19V, 3.42A) AC barrel adapter
- Included: AcBel ADA012, using a C7 power cord
- USB-C charging compatible with 65W+ charger
- 73Wh 4-cell Lithium-Ion battery
- TI BQ24780S battery charge controller
- Sound
- Realtek ALC293 codec
- Internal speakers and microphone
- Combined 3.5 mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 4 SSD
- M.2 PCIe NVMe Gen 3 or SATA SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.1 (3.1 Gen 2) Type-A
- 1x USB 3.0 (3.2 Gen 1) Type-A

## Flashing coreboot

```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B127D |
+---------------------+---------------------+
| Size | 16 MiB |
+---------------------+---------------------+
| Package | SOIC-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```

The flash chip (U33) is left of the DIMM slot.
2 changes: 2 additions & 0 deletions Documentation/security/vboot/list_vboot.md
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Expand Up @@ -170,11 +170,13 @@
- Bubs
- Coachz
- Homestar
- Kingoftown
- Lazor
- Marzipan
- Mrbland
- Pazquel
- Pompom
- Quackingstick
- Trogdor
- Wormdingler
- Veyron_Jaq (Haier Chromebook 11)
Expand Down
16 changes: 8 additions & 8 deletions MAINTAINERS
View file
Expand Up @@ -266,6 +266,7 @@ F: src/mainboard/google/panther/

GOOGLE VOLTEER MAINBOARDS
M: Tim Wawrzynczak <twawrzynczak@chromium.org>
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained
F: src/mainboard/google/volteer/

Expand Down Expand Up @@ -357,12 +358,11 @@ F: src/mainboard/msi/h81m-p33/


OCP DELTALAKE MAINBOARD
M: Jonathan Zhang <jonzhang@fb.com>
M: Reddy Chagam <anjaneya.chagam@intel.com>
M: Arthur Heymans <arthur@aheymans.xyz>
M: Christian Walter <christian.walter@9elements.com>
M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Morgan Jang <Morgan_Jang@wiwynn.com>
M: Ryback Hung <<Ryback.Hung@quantatw.com>
M: Bryant Ou <Bryant.Ou@quantatw.com>
M: Jonathan Zhang <jonzhang@fb.com>
M: Tim Chu <Tim.Chu@quantatw.com>
S: Supported
F: src/mainboard/ocp/deltalake/

Expand Down Expand Up @@ -656,9 +656,9 @@ INTEL Xeon Sacalable Processor Family
M: Jonathan Zhang <jonzhang@fb.com>
M: Reddy Chagam <anjaneya.chagam@intel.com>
M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Morgan Jang <Morgan_Jang@wiwynn.com>
M: Ryback Hung <<Ryback.Hung@quantatw.com>
M: Bryant Ou <Bryant.Ou@quantatw.com>
M: Tim Chu <Tim.Chu@quantatw.com>
M: Arthur Heymans <arthur@aheymans.xyz>
M: Christian Walter <christian.walter@9elements.com>
S: Supported
F: src/soc/intel/xeon_sp/
F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.14.0.4"
CONFIG_LOCALVERSION="v4.14.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_CBFS_SIZE=0x00200000
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.14.0.4"
CONFIG_LOCALVERSION="v4.14.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,157b"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.14.0.4"
CONFIG_LOCALVERSION="v4.14.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.14.0.4"
CONFIG_LOCALVERSION="v4.14.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.14.0.4"
CONFIG_LOCALVERSION="v4.14.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.14.0.4"
CONFIG_LOCALVERSION="v4.14.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
1 change: 1 addition & 0 deletions payloads/external/Makefile.inc
View file
Expand Up @@ -202,6 +202,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
Expand Down
11 changes: 11 additions & 0 deletions payloads/external/tianocore/Kconfig
View file
Expand Up @@ -82,6 +82,17 @@ config TIANOCORE_BOOTSPLASH_FILE
If an absolute path is not given, the path will assumed to be
relative to the coreboot root directory.

config TIANOCORE_ABOVE_4G_MEMORY
bool "Enable above 4G memory"
default n
help
Select this option to enable Above 4G Decode. This will allow the
payload to use all of the memory, rather than an maximum of 4G.

Disabling this option, which will reserve memory above 4G, is
useful for bootloaders that are not fully 64-bit aware such as
Qubes R4.0.4 bootloader.

endif

config TIANOCORE_BOOT_TIMEOUT
Expand Down
8 changes: 7 additions & 1 deletion payloads/external/tianocore/Makefile
View file
Expand Up @@ -33,9 +33,15 @@ ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE
endif

ifeq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
4G=-D ABOVE_4G_MEMORY=TRUE
else
4G=-D ABOVE_4G_MEMORY=FALSE
endif

TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)

BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM)
BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G)

all: clean build

Expand Down
28 changes: 28 additions & 0 deletions payloads/libpayload/include/coreboot_tables.h
View file
Expand Up @@ -82,6 +82,7 @@ enum {
CB_TAG_SMMSTOREV2 = 0x0039,
CB_TAG_BOARD_CONFIG = 0x0040,
CB_TAG_ACPI_CNVS = 0x0041,
CB_TAG_TYPE_C_INFO = 0x0042,
CB_TAG_CMOS_OPTION_TABLE = 0x00c8,
CB_TAG_OPTION = 0x00c9,
CB_TAG_OPTION_ENUM = 0x00ca,
Expand Down Expand Up @@ -142,6 +143,33 @@ struct cb_mainboard {
u8 strings[0];
};

enum type_c_orientation {
TYPEC_ORIENTATION_NONE,
TYPEC_ORIENTATION_NORMAL,
TYPEC_ORIENTATION_REVERSE,
};

struct type_c_port_info {
/*
* usb2_port_number and usb3_port_number are expected to be
* the port numbers as seen by the USB controller in the SoC.
*/
uint8_t usb2_port_number;
uint8_t usb3_port_number;

/*
* Valid sbu_orientation and data_orientation values will be of
* type enum type_c_orienation.
*/
uint8_t sbu_orientation;
uint8_t data_orientation;
};

struct type_c_info {
u32 port_count;
struct type_c_port_info port_info[0];
};

struct cb_string {
u32 tag;
u32 size;
Expand Down
6 changes: 2 additions & 4 deletions payloads/libpayload/include/libpayload.h
View file
Expand Up @@ -472,18 +472,16 @@ static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); }
* @defgroup mmio MMIO helper functions
* @{
*/
#if !CONFIG(LP_ARCH_MIPS)
void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
int fifo_stride, int fifo_width);
void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
void buffer_to_fifo32_prefix(const void *buffer, u32 prefix, int prefsz, size_t size,
void *fifo, int fifo_stride, int fifo_width);
static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
static inline void buffer_to_fifo32(const void *buffer, size_t size, void *fifo,
int fifo_stride, int fifo_width)
{
buffer_to_fifo32_prefix(buffer, 0, 0, size, fifo,
fifo_stride, fifo_width);
}
#endif
/** @} */

/**
Expand Down
2 changes: 2 additions & 0 deletions payloads/libpayload/include/sysinfo.h
View file
Expand Up @@ -148,6 +148,8 @@ struct sysinfo_t {
#if CONFIG(LP_PCI)
struct pci_access pacc;
#endif
/* USB Type-C Port Configuration Info */
uintptr_t type_c_info;
};

extern struct sysinfo_t lib_sysinfo;
Expand Down
8 changes: 8 additions & 0 deletions payloads/libpayload/libc/coreboot.c
View file
Expand Up @@ -246,6 +246,11 @@ static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info)
info->fmap_cache = get_cbmem_addr(ptr);
}

static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info)
{
info->type_c_info = get_cbmem_addr(ptr);
}

#if CONFIG(LP_TIMER_RDTSC)
static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
{
Expand Down Expand Up @@ -420,6 +425,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_FMAP:
cb_parse_fmap_cache(ptr, info);
break;
case CB_TAG_TYPE_C_INFO:
cb_parse_type_c_info(ptr, info);
break;
default:
cb_parse_arch_specific(rec, info);
break;
Expand Down
6 changes: 2 additions & 4 deletions payloads/libpayload/libc/lib.c
View file
Expand Up @@ -126,7 +126,6 @@ char *getenv(const char *name)
return NULL;
}

#if !CONFIG(LP_ARCH_MIPS)
/*
* Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the
* distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit
Expand Down Expand Up @@ -156,10 +155,10 @@ void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
* bytes of the 'prefix' u32 parameter and any high-order bytes exceeding prefsz
* must be 0. Note that 'size' counts total bytes written, including 'prefsz'.
*/
void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
void buffer_to_fifo32_prefix(const void *buffer, u32 prefix, int prefsz, size_t size,
void *fifo, int fifo_stride, int fifo_width)
{
u8 *p = buffer;
const u8 *p = buffer;
int i, j = prefsz;

assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
Expand All @@ -175,4 +174,3 @@ void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
}

}
#endif
11 changes: 11 additions & 0 deletions ...tools/ddr4/global_ddr4_mem_parts.json.txt → spd/ddr4/memory_parts.json
View file
Expand Up @@ -238,6 +238,17 @@
"packageBusWidth": 16,
"ranksPerPackage": 1
}
},
{
"name": "4JQA-0622AD",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,
"capacityPerDieGb": 8,
"diesPerPackage": 1,
"packageBusWidth": 16,
"ranksPerPackage": 1
}
}
]
}
5 changes: 5 additions & 0 deletions spd/ddr4/platforms_manifest.generated.txt
View file
@@ -0,0 +1,5 @@
# Generated by:
# util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4

TGL,set-0
PCO,set-0
23 changes: 23 additions & 0 deletions spd/ddr4/set-0/parts_spd_manifest.generated.txt
View file
@@ -0,0 +1,23 @@
# Generated by:
# util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4

H5AN8G6NDJR-XNC,spd-1.hex
MT40A512M16TB-062E:J,spd-1.hex
H5ANAG6NCMR-XNC,spd-2.hex
HMA851S6CJR6N-VK,spd-3.hex
K4A8G165WC-BCTD,spd-3.hex
H5AN8G6NCJR-VKC,spd-3.hex
MT40A1G16KNR-075:E,spd-4.hex
K4AAG165WB-MCTD,spd-5.hex
H5ANAG6NCMR-VKC,spd-6.hex
K4A8G165WC-BCWE,spd-1.hex
MT40A1G16KD-062E:E,spd-7.hex
K4AAG165WA-BCWE,spd-7.hex
H5AN8G6NCJR-XNC,spd-1.hex
K4AAG165WA-BCTD,spd-8.hex
H5ANAG6NDMR-XNC,spd-2.hex
H5ANAG6NCJR-XNC,spd-9.hex
K4AAG165WB-BCWE,spd-9.hex
MT40A1G16RC-062E:B,spd-9.hex
MT40A512M16TB-062E:R,spd-1.hex
4JQA-0622AD,spd-1.hex
0 src/mainboard/google/zork/spd/ddr4-spd-1.hex → spd/ddr4/set-0/spd-1.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-2.hex → spd/ddr4/set-0/spd-2.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-3.hex → spd/ddr4/set-0/spd-3.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-4.hex → spd/ddr4/set-0/spd-4.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-5.hex → spd/ddr4/set-0/spd-5.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-6.hex → spd/ddr4/set-0/spd-6.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-7.hex → spd/ddr4/set-0/spd-7.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-8.hex → spd/ddr4/set-0/spd-8.hex
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0 src/mainboard/google/zork/spd/ddr4-spd-9.hex → spd/ddr4/set-0/spd-9.hex
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0 ...nboard/google/zork/spd/ddr4-spd-empty.hex → spd/ddr4/set-0/spd-empty.hex
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0 ...tools/lp4x/global_lp4x_mem_parts.json.txt → spd/lp4x/memory_parts.json
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7 changes: 7 additions & 0 deletions spd/lp4x/platforms_manifest.generated.txt
View file
@@ -0,0 +1,7 @@
# Generated by:
# util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

TGL,set-0
ADL,set-0
JSL,set-1
CZN,set-1
31 changes: 31 additions & 0 deletions spd/lp4x/set-0/parts_spd_manifest.generated.txt
View file
@@ -0,0 +1,31 @@
# Generated by:
# util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

H9HCNNNBKMMLXR-NEE,spd-1.hex
H9HCNNNFAMMLXR-NEE,spd-2.hex
K4U6E3S4AA-MGCL,spd-1.hex
K4UBE3D4AA-MGCL,spd-3.hex
MT53E1G32D2NP-046 WT:A,spd-4.hex
MT53E1G32D2NP-046 WT:B,spd-3.hex
H9HKNNNCRMBVAR-NEH,spd-1.hex
MT53E1G64D4SQ-046 WT:A,spd-4.hex
MT53E512M32D2NP-046 WT:F,spd-1.hex
NT6AP256T32AV-J2,spd-5.hex
K4U6E3S4AA-MGCR,spd-1.hex
MT53E512M32D2NP-046 WT:E,spd-1.hex
H9HCNNNCPMMLXR-NEE,spd-3.hex
K4UBE3D4AA-MGCR,spd-3.hex
MT53E512M64D4NW-046 WT:E,spd-1.hex
MT53E1G64D8NW-046 WT:E,spd-3.hex
H9HCNNNCRMBLPR-NEE,spd-1.hex
H9HCNNNFBMBLPR-NEE,spd-3.hex
MT53D1G64D4NW-046 WT:A,spd-4.hex
MT53D512M64D4NW-046 WT:F,spd-1.hex
NT6AP256T32AV-J1,spd-6.hex
MT53E1G32D4NQ-046 WT:E,spd-3.hex
MT53E2G32D4NQ-046 WT:A,spd-7.hex
MT53E512M32D1NP-046 WT:B,spd-1.hex
H54G46CYRBX267,spd-1.hex
H54G56CYRBX247,spd-3.hex
K4U6E3S4AB-MGCL,spd-1.hex
K4UBE3D4AB-MGCL,spd-3.hex
0 src/soc/intel/alderlake/spd/lp4x-spd-1.hex → spd/lp4x/set-0/spd-1.hex
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0 src/soc/intel/alderlake/spd/lp4x-spd-2.hex → spd/lp4x/set-0/spd-2.hex
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0 src/soc/intel/alderlake/spd/lp4x-spd-3.hex → spd/lp4x/set-0/spd-3.hex
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0 src/soc/intel/alderlake/spd/lp4x-spd-4.hex → spd/lp4x/set-0/spd-4.hex
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0 src/soc/intel/alderlake/spd/lp4x-spd-5.hex → spd/lp4x/set-0/spd-5.hex
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0 src/soc/intel/alderlake/spd/lp4x-spd-6.hex → spd/lp4x/set-0/spd-6.hex
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0 src/soc/intel/alderlake/spd/lp4x-spd-7.hex → spd/lp4x/set-0/spd-7.hex
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0 ...c/intel/alderlake/spd/placeholder.spd.hex → spd/lp4x/set-0/spd-empty.hex
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31 changes: 31 additions & 0 deletions spd/lp4x/set-1/parts_spd_manifest.generated.txt
View file
@@ -0,0 +1,31 @@
# Generated by:
# util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

H9HCNNNBKMMLXR-NEE,spd-1.hex
H9HCNNNFAMMLXR-NEE,spd-2.hex
K4U6E3S4AA-MGCL,spd-1.hex
K4UBE3D4AA-MGCL,spd-3.hex
MT53E1G32D2NP-046 WT:A,spd-4.hex
MT53E1G32D2NP-046 WT:B,spd-3.hex
H9HKNNNCRMBVAR-NEH,spd-5.hex
MT53E1G64D4SQ-046 WT:A,spd-6.hex
MT53E512M32D2NP-046 WT:F,spd-1.hex
NT6AP256T32AV-J2,spd-7.hex
K4U6E3S4AA-MGCR,spd-1.hex
MT53E512M32D2NP-046 WT:E,spd-1.hex
H9HCNNNCPMMLXR-NEE,spd-3.hex
K4UBE3D4AA-MGCR,spd-3.hex
MT53E512M64D4NW-046 WT:E,spd-5.hex
MT53E1G64D8NW-046 WT:E,spd-8.hex
H9HCNNNCRMBLPR-NEE,spd-5.hex
H9HCNNNFBMBLPR-NEE,spd-8.hex
MT53D1G64D4NW-046 WT:A,spd-6.hex
MT53D512M64D4NW-046 WT:F,spd-5.hex
NT6AP256T32AV-J1,spd-9.hex
MT53E1G32D4NQ-046 WT:E,spd-3.hex
MT53E2G32D4NQ-046 WT:A,spd-10.hex
MT53E512M32D1NP-046 WT:B,spd-1.hex
H54G46CYRBX267,spd-1.hex
H54G56CYRBX247,spd-3.hex
K4U6E3S4AB-MGCL,spd-1.hex
K4UBE3D4AB-MGCL,spd-3.hex
0 ...nboard/google/guybrush/spd/lp4x-spd-1.hex → spd/lp4x/set-1/spd-1.hex
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0 ...board/google/guybrush/spd/lp4x-spd-10.hex → spd/lp4x/set-1/spd-10.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-2.hex → spd/lp4x/set-1/spd-2.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-3.hex → spd/lp4x/set-1/spd-3.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-4.hex → spd/lp4x/set-1/spd-4.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-5.hex → spd/lp4x/set-1/spd-5.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-6.hex → spd/lp4x/set-1/spd-6.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-7.hex → spd/lp4x/set-1/spd-7.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-8.hex → spd/lp4x/set-1/spd-8.hex
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0 ...nboard/google/guybrush/spd/lp4x-spd-9.hex → spd/lp4x/set-1/spd-9.hex
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0 ...oc/intel/tigerlake/spd/ddr4-spd-empty.hex → spd/lp4x/set-1/spd-empty.hex
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2 changes: 1 addition & 1 deletion src/Kconfig
View file
Expand Up @@ -112,7 +112,7 @@ config FMD_GENPARSER
Otherwise, say N to use the provided pregenerated scanner/parser.

config UTIL_GENPARSER
bool "Generate SCONFIG & BINCFG parser using flex and bison"
bool "Generate parsers for bincfg, sconfig and kconfig locally"
default n
help
Enable this option if you are working on the sconfig device tree
Expand Down
49 changes: 46 additions & 3 deletions src/acpi/acpigen.c
View file
Expand Up @@ -16,6 +16,7 @@
#include <string.h>
#include <acpi/acpigen.h>
#include <assert.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/device.h>
#include <device/soundwire.h>
Expand Down Expand Up @@ -1643,6 +1644,38 @@ void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *),
acpigen_write_dsm_uuid_arr(&id, 1);
}

/*
* Create a supported functions bitmask
* bit 0: other functions than 0 are supported
* bits 1-x: function x supported
*/
static void acpigen_dsm_uuid_enum_functions(const struct dsm_uuid *id)
{
const size_t bytes = DIV_ROUND_UP(id->count, BITS_PER_BYTE);
uint8_t *buffer = alloca(bytes);
bool set = false;
size_t cb_idx = 0;

memset(buffer, 0, bytes);

for (size_t i = 0; i < bytes; i++) {
for (size_t j = 0; j < BITS_PER_BYTE; j++) {
if (cb_idx >= id->count)
break;

if (id->callbacks[cb_idx++]) {
set = true;
buffer[i] |= BIT(j);
}
}
}

if (set)
buffer[0] |= BIT(0);

acpigen_write_return_byte_buffer(buffer, bytes);
}

static void acpigen_write_dsm_uuid(struct dsm_uuid *id)
{
size_t i;
Expand All @@ -1656,21 +1689,31 @@ static void acpigen_write_dsm_uuid(struct dsm_uuid *id)
/* ToInteger (Arg2, Local1) */
acpigen_write_to_integer(ARG2_OP, LOCAL1_OP);

for (i = 0; i < id->count; i++) {
/* If (LEqual(Local1, 0)) */
{
acpigen_write_if_lequal_op_int(LOCAL1_OP, 0);
if (id->callbacks[0])
id->callbacks[0](id->arg);
else if (id->count)
acpigen_dsm_uuid_enum_functions(id);
acpigen_write_if_end();
}

for (i = 1; i < id->count; i++) {
/* If (LEqual (Local1, i)) */
acpigen_write_if_lequal_op_int(LOCAL1_OP, i);

/* Callback to write if handler. */
if (id->callbacks[i])
id->callbacks[i](id->arg);

acpigen_pop_len(); /* If */
acpigen_write_if_end(); /* If */
}

/* Default case: Return (Buffer (One) { 0x0 }) */
acpigen_write_return_singleton_buffer(0x0);

acpigen_pop_len(); /* If (LEqual (Local0, ToUUID(uuid))) */
acpigen_write_if_end(); /* If (LEqual (Local0, ToUUID(uuid))) */

}

Expand Down
2 changes: 2 additions & 0 deletions src/acpi/acpigen_dptf.c
View file
Expand Up @@ -70,6 +70,8 @@ static const char *namestring_of(enum dptf_participant participant)
return "TSR2";
case DPTF_TEMP_SENSOR_3:
return "TSR3";
case DPTF_TPCH:
return "TPCH";
default:
return "";
}
Expand Down
10 changes: 7 additions & 3 deletions src/acpi/device.c
View file
Expand Up @@ -645,16 +645,20 @@ static void acpigen_write_power_res_STA(const struct acpi_power_res_params *para
/* PowerResource() with Enable and/or Reset control */
void acpi_device_add_power_res(const struct acpi_power_res_params *params)
{
static uint8_t id;
static const char * const power_res_dev_states[] = { "_PR0", "_PR3" };
unsigned int reset_gpio = params->reset_gpio ? params->reset_gpio->pins[0] : 0;
unsigned int enable_gpio = params->enable_gpio ? params->enable_gpio->pins[0] : 0;
unsigned int stop_gpio = params->stop_gpio ? params->stop_gpio->pins[0] : 0;
char pr_name[ACPI_NAME_BUFFER_SIZE];

if (!reset_gpio && !enable_gpio && !stop_gpio)
return;

/* PowerResource (PRIC, 0, 0) */
acpigen_write_power_res("PRIC", 0, 0, power_res_dev_states,
snprintf(pr_name, sizeof(pr_name), "PR%02X", id++);

/* PowerResource (PR##, 0, 0) */
acpigen_write_power_res(pr_name, 0, 0, power_res_dev_states,
ARRAY_SIZE(power_res_dev_states));

if (params->use_gpio_for_status) {
Expand Down Expand Up @@ -704,7 +708,7 @@ void acpi_device_add_power_res(const struct acpi_power_res_params *params)
}
acpigen_pop_len(); /* _OFF method */

acpigen_pop_len(); /* PowerResource PRIC */
acpigen_pop_len(); /* PowerResource PR## */
}

static void acpi_dp_write_array(const struct acpi_dp *array);
Expand Down
2 changes: 0 additions & 2 deletions src/arch/arm64/include/armv8/arch/cpu.h
View file
Expand Up @@ -5,8 +5,6 @@

#define asmlinkage

static inline unsigned int smp_processor_id(void) { return 0; }

struct cpu_driver { };

#endif /* __ARCH_CPU_H__ */
24 changes: 0 additions & 24 deletions src/arch/arm64/include/clocks.h
View file

This file was deleted.

2 changes: 1 addition & 1 deletion src/arch/riscv/Makefile.inc
View file
Expand Up @@ -171,7 +171,7 @@ $(OPENSBI_TARGET): $(obj)/config.h | $(OPENSBI_SOURCE)
mkdir -p $(OPENSBI_BUILD)
$(MAKE) \
-C "$(OPENSBI_SOURCE)" \
CC="$(CC_ramstage)" \
CC="$(CC_ramstage) -fno-builtin" \
LD="$(LD_ramstage)" \
OBJCOPY="$(OBJCOPY_ramstage)" \
AR="$(AR_ramstage)" \
Expand Down
1 change: 1 addition & 0 deletions src/arch/riscv/trap_handler.c
View file
Expand Up @@ -9,6 +9,7 @@
#include <vm.h>
#include <mcall.h>
#include <sbi.h>
#include <types.h>

static const char *const exception_names[] = {
"Instruction address misaligned",
Expand Down
9 changes: 2 additions & 7 deletions src/arch/x86/assembly_entry.S
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <cpu/x86/cpu_info.S.inc>
#include <rules.h>

/*
Expand Down Expand Up @@ -35,13 +36,7 @@ _start:
/* reset stack pointer to CAR/EARLYRAM stack */
mov $_STACK_TOP, %esp

#if CONFIG(COOP_MULTITASKING)
/* Push the thread pointer. */
push $0
#endif
/* Push the CPU index and struct CPU */
push $0
push $0
push_cpu_info

/* clear .bss section as it is not shared */
cld
Expand Down
1 change: 1 addition & 0 deletions src/arch/x86/boot.c
View file
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/boot/boot.h>
#include <arch/cpu.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <program_loading.h>
Expand Down
12 changes: 4 additions & 8 deletions src/arch/x86/c_start.S
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <cpu/x86/cpu_info.S.inc>
#include <cpu/x86/post_code.h>
#include <arch/ram_segs.h>

Expand Down Expand Up @@ -38,8 +39,9 @@ _start:
movl %eax, %ds
movl %eax, %es
movl %eax, %ss
xor %eax, %eax /* zero out the gs and fs segment index */
movl %eax, %fs
movl %eax, %gs
movl %eax, %gs /* Will be used for cpu_info */
#if ENV_X86_64
mov $RAM_CODE_SEG64, %ecx
call SetCodeSelector
Expand Down Expand Up @@ -76,13 +78,7 @@ _start:
movl $_estack, %esp
andl $(~(CONFIG_STACK_SIZE-1)), %esp

#if CONFIG(COOP_MULTITASKING)
/* Push the thread pointer. */
push $0
#endif
/* Push the CPU index and struct CPU */
push $0
push $0
push_cpu_info

/*
* Now we are finished. Memory is up, data is copied and
Expand Down
5 changes: 3 additions & 2 deletions src/arch/x86/include/arch/hlt.h
View file
Expand Up @@ -3,9 +3,10 @@
#ifndef ARCH_HLT_H
#define ARCH_HLT_H

static __always_inline void hlt(void)
static __noreturn __always_inline void hlt(void)
{
asm("hlt");
while (1)
asm("hlt");
}

#endif /* ARCH_HLT_H */
19 changes: 16 additions & 3 deletions src/arch/x86/smbios.c
View file
Expand Up @@ -1213,18 +1213,31 @@ static int smbios_generate_type9_from_devtree(struct device *dev, int *handle,
dev->path.pci.devfn);
}

int get_smbios_data(struct device *dev, int *handle, unsigned long *current)
{
int len = 0;

len += smbios_generate_type9_from_devtree(dev, handle, current);
len += smbios_generate_type41_from_devtree(dev, handle, current);

return len;
}

static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current)
{
struct device *dev;
int len = 0;

for (dev = tree; dev; dev = dev->next) {
if (dev->enabled && dev->ops && dev->ops->get_smbios_data) {
if (!dev->enabled)
continue;

if (dev->ops && dev->ops->get_smbios_data) {
printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev_name(dev));
len += dev->ops->get_smbios_data(dev, handle, current);
} else {
len += get_smbios_data(dev, handle, current);
}
len += smbios_generate_type9_from_devtree(dev, handle, current);
len += smbios_generate_type41_from_devtree(dev, handle, current);
}
return len;
}
Expand Down
11 changes: 7 additions & 4 deletions src/commonlib/bsd/cbfs_private.c
View file
Expand Up @@ -54,7 +54,8 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
if (data_offset > sizeof(mdata) || data_length > devsize ||
offset + data_offset + data_length > devsize) {
ERROR("File @%#zx too large\n", offset);
goto next_file;
offset += CBFS_ALIGNMENT;
continue;
}

if (empty && !(flags & CBFS_WALK_INCLUDE_EMPTY))
Expand All @@ -77,6 +78,8 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h),
offset + sizeof(mdata.h), todo) != todo)
return CB_CBFS_IO;
/* Force filename null-termination, just in case. */
mdata.raw[attr_offset ? attr_offset - 1 : data_offset - 1] = '\0';
DEBUG("File name: '%s'\n", mdata.h.filename);

if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset))
Expand Down Expand Up @@ -174,9 +177,9 @@ const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, siz
const uint32_t tag = be32toh(attr->tag);
const uint32_t len = be32toh(attr->len);

if (offset + len > end) {
ERROR("Attribute %s[%x] overflows end of metadata\n",
mdata->h.filename, tag);
if (len < sizeof(struct cbfs_file_attribute) || len > end - offset) {
ERROR("Attribute %s[%x] invalid length: %u\n",
mdata->h.filename, tag, len);
return NULL;
}
if (tag == attr_tag) {
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/bsd/elog.c
View file
Expand Up @@ -50,7 +50,7 @@ const void *event_get_data(const struct event_header *event)

/* Populate timestamp in event header with given time. */
void elog_fill_timestamp(struct event_header *event, uint8_t sec, uint8_t min,
uint8_t hour, uint8_t mday, uint8_t mon, uint8_t year)
uint8_t hour, uint8_t mday, uint8_t mon, uint16_t year)
{
event->second = bin2bcd(sec);
event->minute = bin2bcd(min);
Expand Down
5 changes: 4 additions & 1 deletion src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h
View file
Expand Up @@ -8,7 +8,10 @@
#include <stdint.h>

/*
* Helper structure to allocate space for a blob of metadata on the stack.
* Helper structure to allocate space for a blob of metadata on the stack. All functions using
* a cbfs_mdata should be getting it via cbfs_walk(), and can rely on the fact that cbfs_walk()
* has already fully validated the header (range checks for `len`, `attributes_offset` and
* `offset`, and null-termination for `filename`).
* NOTE: The fields in any union cbfs_mdata or any of its substructures from cbfs_serialized.h
* should always remain in the same byte order as they are stored on flash (= big endian). To
* avoid byte-order confusion, fields should always and only be converted to host byte order at
Expand Down
5 changes: 4 additions & 1 deletion src/commonlib/bsd/include/commonlib/bsd/elog.h
View file
Expand Up @@ -311,11 +311,14 @@ struct elog_event_extended_event {
} __packed;


/* Only the 7-LSB are used for size */
#define ELOG_MAX_EVENT_SIZE 0x7F

enum cb_err elog_verify_header(const struct elog_header *header);
const struct event_header *elog_get_next_event(const struct event_header *event);
const void *event_get_data(const struct event_header *event);
void elog_fill_timestamp(struct event_header *event, uint8_t sec, uint8_t min,
uint8_t hour, uint8_t mday, uint8_t mon, uint8_t year);
uint8_t hour, uint8_t mday, uint8_t mon, uint16_t year);
/* Update the checksum at the last byte. */
void elog_update_checksum(struct event_header *event, uint8_t checksum);
/* Simple byte checksum for events. */
Expand Down
4 changes: 3 additions & 1 deletion src/commonlib/include/commonlib/cbmem_id.h
View file
Expand Up @@ -79,6 +79,7 @@
#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346
#define CBMEM_ID_FSP_LOGO 0x4c4f474f
#define CBMEM_ID_SMM_COMBUFFER 0x53534d32
#define CBMEM_ID_TYPE_C_INFO 0x54595045

#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
Expand Down Expand Up @@ -147,5 +148,6 @@
{ CBMEM_ID_ROM3, "VGA ROM #3 "}, \
{ CBMEM_ID_FMAP, "FMAP "}, \
{ CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \
{ CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}
{ CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \
{ CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}
#endif /* _CBMEM_ID_H_ */
28 changes: 28 additions & 0 deletions src/commonlib/include/commonlib/coreboot_tables.h
View file
Expand Up @@ -84,6 +84,7 @@ enum {
LB_TAG_TPM_PPI_HANDOFF = 0x003a,
LB_TAG_BOARD_CONFIG = 0x0040,
LB_TAG_ACPI_CNVS = 0x0041,
LB_TAG_TYPE_C_INFO = 0x0042,
/* The following options are CMOS-related */
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,
Expand Down Expand Up @@ -421,6 +422,33 @@ struct lb_mmc_info {
int32_t early_cmd1_status;
};

/*
* USB Type-C Port Information
* This record contains board-specific type-c port information.
* There will be one record per type-C port.
* Orientation fields should be of type enum type_c_orientation.
*/
enum type_c_orientation {
/* The orientation of the signal follows the orientation of the CC lines. */
TYPEC_ORIENTATION_NONE,
/* The orientation of the signal is fixed to follow CC1 */
TYPEC_ORIENTATION_NORMAL,
/* The orientation of the signal is fixed to follow CC2 */
TYPEC_ORIENTATION_REVERSE,
};

struct type_c_port_info {
uint8_t usb2_port_number;
uint8_t usb3_port_number;
uint8_t sbu_orientation;
uint8_t data_orientation;
};

struct type_c_info {
uint32_t port_count;
struct type_c_port_info port_info[0];
};

struct lb_macs {
uint32_t tag;
uint32_t size;
Expand Down
2 changes: 1 addition & 1 deletion src/console/init.c
View file
Expand Up @@ -45,7 +45,7 @@ int console_log_level(int msg_level)
return 0;
}

asmlinkage void console_init(void)
void console_init(void)
{
init_log_level();

Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family14/Makefile.inc
View file
Expand Up @@ -7,7 +7,6 @@ ramstage-y += chip_name.c
ramstage-y += model_14_init.c

subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
Expand Down
21 changes: 8 additions & 13 deletions src/cpu/amd/agesa/family14/acpi/cpu.asl
View file
Expand Up @@ -4,20 +4,15 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
Scope (\_SB) { /* define processor scope */

Device (C000) {
Name (_HID, "ACPI0007")
Name (_UID, 0)
}

Processor(
C001, /* name space name */
1, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
Device (C001) {
Name (_HID, "ACPI0007")
Name (_UID, 1)
}
} /* End _SB scope */
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family15tn/Makefile.inc
View file
Expand Up @@ -10,7 +10,6 @@ smm-y += udelay.c

subdirs-y += ../../mtrr
subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
Expand Down
107 changes: 45 additions & 62 deletions src/cpu/amd/agesa/family15tn/acpi/cpu.asl
View file
@@ -1,65 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */

Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family16kb/Makefile.inc
View file
Expand Up @@ -7,7 +7,6 @@ ramstage-y += chip_name.c
ramstage-y += model_16_init.c

subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
Expand Down
80 changes: 31 additions & 49 deletions src/cpu/amd/agesa/family16kb/acpi/cpu.asl
View file
Expand Up @@ -4,62 +4,44 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
Scope (\_SB) {/* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00730F01/Makefile.inc
View file
Expand Up @@ -8,7 +8,6 @@ ramstage-y += model_16_init.c
ramstage-y += update_microcode.c

subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
Expand Down
107 changes: 45 additions & 62 deletions src/cpu/amd/pi/00730F01/acpi/cpu.asl
View file
@@ -1,65 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */

Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */
1 change: 1 addition & 0 deletions src/cpu/amd/pi/00730F01/update_microcode.c
View file
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/amd/microcode.h>
#include <commonlib/helpers.h>
#include <console/console.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/common/fsb.c
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/speedstep.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/haswell/Makefile.inc
View file
Expand Up @@ -15,7 +15,6 @@ bootblock-y += bootblock.c

postcar-y += ../car/non-evict/exit_car.S

subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_2065x/Makefile.inc
View file
Expand Up @@ -3,7 +3,6 @@ subdirs-y += ../../x86/name
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/tsc
subdirs-y += ../../intel/turbo
subdirs-y += ../../intel/microcode
subdirs-y += ../smm/gen1
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1 change: 0 additions & 1 deletion src/cpu/intel/model_206ax/Makefile.inc
View file
Expand Up @@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c
subdirs-y += ../../x86/name
subdirs-y += ../smm/gen1

subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/slot_1/Makefile.inc
View file
Expand Up @@ -7,7 +7,6 @@ subdirs-y += ../model_65x
subdirs-y += ../model_67x
subdirs-y += ../model_68x
subdirs-y += ../model_6bx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 1 addition & 0 deletions src/cpu/intel/slot_1/l2_cache.c
View file
Expand Up @@ -24,6 +24,7 @@
*/

#include <stdint.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/l2_cache.h>
#include <cpu/x86/cache.h>
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_441/Makefile.inc
View file
@@ -1,5 +1,4 @@
subdirs-y += ../model_106cx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_BGA956/Makefile.inc
View file
@@ -1,5 +1,4 @@
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_FCBGA559/Makefile.inc
View file
@@ -1,5 +1,4 @@
subdirs-y += ../model_106cx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_LGA775/Makefile.inc
View file
Expand Up @@ -4,7 +4,6 @@ subdirs-y += ../model_f4x
#subdirs-y += ../model_f6x
#subdirs-y += ../model_1066x
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_m/Makefile.inc
View file
@@ -1,6 +1,5 @@
subdirs-y += ../model_6ex
subdirs-y += ../model_6fx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_mPGA604/Makefile.inc
View file
@@ -1,5 +1,4 @@
subdirs-y += ../model_f2x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/intel/socket_p/Makefile.inc
View file
@@ -1,6 +1,5 @@
subdirs-y += ../model_6fx
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
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1 change: 0 additions & 1 deletion src/cpu/qemu-x86/Makefile.inc
View file
Expand Up @@ -9,4 +9,3 @@ ramstage-y += qemu.c

subdirs-y += ../x86/mtrr
subdirs-y += ../x86/lapic
subdirs-y += ../x86/tsc
1 change: 1 addition & 0 deletions src/cpu/x86/Makefile.inc
View file
@@ -1,5 +1,6 @@
subdirs-y += pae
subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm
subdirs-$(CONFIG_UDELAY_TSC) += tsc

all-$(CONFIG_ARCH_ALL_STAGES_X86_64) += 64bit/mode_switch.S

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10 changes: 10 additions & 0 deletions src/cpu/x86/cpu_info.S.inc
View file
@@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

/* Push struct cpu_info */
.macro push_cpu_info index=$0
#if CONFIG(COOP_MULTITASKING)
push $0 /* *thread */
#endif
push \index /* index */
push $0 /* *cpu */
.endm
3 changes: 2 additions & 1 deletion src/cpu/x86/entry32.S
View file
Expand Up @@ -37,8 +37,9 @@ bootblock_protected_mode_entry:
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs
movw %ax, %gs
movw %ax, %gs /* Will be used for cpu_info */

/* Restore the BIST value to %eax */
movl %ebp, %eax
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3 changes: 2 additions & 1 deletion src/cpu/x86/lapic/secondary.S
View file
Expand Up @@ -52,8 +52,9 @@ __ap_protected_start:
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs
movw %ax, %gs
movw %ax, %gs /* Will be used for cpu_info */

/* Load the Interrupt descriptor table */
lidt idtarg
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7 changes: 6 additions & 1 deletion src/cpu/x86/mp_init.c
View file
Expand Up @@ -455,7 +455,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
mdelay(10);
}

/* Send 1st SIPI */
/* Send 1st Startup IPI (SIPI) */
if (lapic_busy()) {
printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
Expand Down Expand Up @@ -714,6 +714,11 @@ static void smm_enable(void)
mp_state.do_smm = 1;
}

/*
* This code is built as part of ramstage, but it actually runs in SMM. This
* means that ENV_SMM is 0, but we are actually executing in the environment
* setup by the smm_stub.
*/
static void asmlinkage smm_do_relocation(void *arg)
{
const struct smm_module_params *p;
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3 changes: 2 additions & 1 deletion src/cpu/x86/sipi_vector.S
View file
Expand Up @@ -77,8 +77,9 @@ _start:
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs
movw %ax, %gs
movw %ax, %gs /* Will be used for cpu_info */

/* Load the Interrupt descriptor table */
mov idt_ptr, %ebx
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3 changes: 2 additions & 1 deletion src/cpu/x86/smm/smm_stub.S
View file
Expand Up @@ -93,8 +93,9 @@ smm_trampoline32:
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs
movw %ax, %gs
movw %ax, %gs /* Will be used for cpu_info */

/* The CPU number is calculated by reading the initial APIC id. Since
* the OS can manipulate the APIC id use the non-changing cpuid result
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3 changes: 2 additions & 1 deletion src/cpu/x86/smm/smmhandler.S
View file
Expand Up @@ -123,8 +123,9 @@ untampered_lapic:
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs
movw %ax, %gs
movw %ax, %gs /* Will be used for cpu_info */

/* FIXME: Incompatible with X2APIC_SUPPORT. */
/* Get this CPU's LAPIC ID */
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12 changes: 6 additions & 6 deletions src/cpu/x86/tsc/Makefile.inc
View file
@@ -1,6 +1,6 @@
bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
verstage_x86-$(CONFIG_UDELAY_TSC) += delay_tsc.c
postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c
smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c
bootblock-y += delay_tsc.c
ramstage-y += delay_tsc.c
romstage-y += delay_tsc.c
verstage_x86-y += delay_tsc.c
postcar-y += delay_tsc.c
smm-y += delay_tsc.c
13 changes: 0 additions & 13 deletions src/device/device_const.c
View file
Expand Up @@ -70,19 +70,6 @@ DEVTREE_CONST struct device *dev_find_path(
return result;
}

DEVTREE_CONST struct device *dev_find_matching_device_on_bus(const struct bus *bus,
match_device_fn fn)
{
DEVTREE_CONST struct device *child = NULL;

while ((child = dev_bus_each_child(bus, child)) != NULL) {
if (fn(child))
break;
}

return child;
}

/**
* Given a device pointer, find the next PCI device.
*
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44 changes: 37 additions & 7 deletions src/device/dram/lpddr4.c
View file
Expand Up @@ -10,10 +10,15 @@
#include <types.h>

enum lpddr4_speed_grade {
LPDDR4_1333,
LPDDR4_1600,
LPDDR4_1866,
LPDDR4_2133,
LPDDR4_2400,
LPDDR4_2666,
LPDDR4_3200,
LPDDR4_4266
LPDDR4_3733,
LPDDR4_4266,
};

struct lpddr4_speed_attr {
Expand All @@ -23,32 +28,57 @@ struct lpddr4_speed_attr {
};

/**
* LPDDR4 speed attributes derived from JEDEC 209-4C table 210
* LPDDR4 speed attributes derived from JEDEC 209-4C and industry norms
*
* min_clock_mhz = Previous max_clock_mhz + 1
* max_clock_mhz = 1000/min_tCk_avg(ns)
* reported_mts = Standard reported DDR4 speed in MT/s
* May be slightly less than the actual max MT/s
*/
static const struct lpddr4_speed_attr lpddr4_speeds[] = {
[LPDDR4_1600] = {
[LPDDR4_1333] = {
.min_clock_mhz = 10,
.max_clock_mhz = 667,
.reported_mts = 1333,
},
[LPDDR4_1600] = {
.min_clock_mhz = 668,
.max_clock_mhz = 800,
.reported_mts = 1600
},
[LPDDR4_2400] = {
[LPDDR4_1866] = {
.min_clock_mhz = 801,
.max_clock_mhz = 934,
.reported_mts = 1866,
},
[LPDDR4_2133] = {
.min_clock_mhz = 935,
.max_clock_mhz = 1067,
.reported_mts = 2133
},
[LPDDR4_2400] = {
.min_clock_mhz = 1068,
.max_clock_mhz = 1200,
.reported_mts = 2400
},
[LPDDR4_3200] = {
[LPDDR4_2666] = {
.min_clock_mhz = 1201,
.max_clock_mhz = 1333,
.reported_mts = 2666
},
[LPDDR4_3200] = {
.min_clock_mhz = 1334,
.max_clock_mhz = 1600,
.reported_mts = 3200
},
[LPDDR4_4266] = {
[LPDDR4_3733] = {
.min_clock_mhz = 1601,
.max_clock_mhz = 2137,
.max_clock_mhz = 1867,
.reported_mts = 3733
},
[LPDDR4_4266] = {
.min_clock_mhz = 1868,
.max_clock_mhz = 2134,
.reported_mts = 4266
},
};
Expand Down
3 changes: 3 additions & 0 deletions src/device/dram/spd.c
View file
Expand Up @@ -14,6 +14,7 @@ const char *spd_manufacturer_name(const uint16_t mod_id)
case 0x9801:
return "Kingston";
case 0x987f:
case 0xad00:
return "Hynix";
case 0x9e02:
return "Corsair";
Expand All @@ -26,10 +27,12 @@ const char *spd_manufacturer_name(const uint16_t mod_id)
case 0xcd04:
return "GSkill";
case 0xce80:
case 0xce00:
return "Samsung";
case 0xfe02:
return "Elpida";
case 0x2c80:
case 0x2c00:
return "Micron";
default:
return NULL;
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4 changes: 2 additions & 2 deletions src/device/mmio.c
View file
Expand Up @@ -21,10 +21,10 @@ void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
}
}

void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
void buffer_to_fifo32_prefix(const void *buffer, u32 prefix, int prefsz, size_t size,
void *fifo, int fifo_stride, int fifo_width)
{
u8 *p = buffer;
const u8 *p = buffer;
int i, j = prefsz;

assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
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