diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -179,6 +179,7 @@ The boards in this section are not real mainboards, but emulators.
 - [Gazelle 15](system76/gaze15.md)
 - [Lemur Pro](system76/lemp9.md)
 - [Oryx Pro 5](system76/oryp5.md)
+- [Oryx Pro 6](system76/oryp6.md)
 
 ## Texas Instruments
 

diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
@@ -4,9 +4,14 @@ This section details how to run coreboot on the [Supermicro X11SSM-F].
 
 ## Flashing coreboot
 
-The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. For this,
-one needs to add a diode between VCC and the flash chip. The flash IC [MX25L12873F] can be found
-near PCH PCIe Slot 4.
+The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4.
+
+The board can be flashed externally with a SOIC test clip or probes. Since
+there is no diode between VCC3.3 and the flash chip, so VCC must **not** be
+connected. Instead, the flash chip is powered from VCC3.3, which is always-on
+(even in S5). WP# and HOLD# have pull-ups and don't need to be connected.
+
+FTDI FT2232H and FT232H based programmers worked.
 
 Flashing is also possible through the BMC web interface, when a valid license was entered.
 

diff --git a/Documentation/mainboard/system76/oryp6.md b/Documentation/mainboard/system76/oryp6.md
@@ -0,0 +1,60 @@
+# System76 Oryx Pro (oryp6)
+
+## Specs
+
+- CPU
+  - Intel i7-10875H
+- Chipset
+  - Intel HM470
+- EC
+  - ITE IT5570E running https://github.com/system76/ec
+- GPU
+  - NVIDIA GeForce RTX 2080 Super (Max-Q)
+  - or NVIDIA GeForce RTX 2070 (Max-Q)
+  - or NVIDIA GeForce RTX 2060
+  - eDP 15.6" or 17.3" 1920x1080@144Hz LCD
+  - HDMI, Mini DisplayPort 1.4, and DisplayPort over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX200/AX201
+- Power
+  - 180W (19.5V, 9.23A) AC adapter
+  - 73Wh 3-cell battery
+- Sound
+  - Internal speakers and microphone
+  - Combined headphone and microphone 3.5mm jack
+  - Combined microphone and S/PDIF (optical) 3.5mm jack
+  - HDMI, Mini DisplayPort, USB-C DisplayPort audio
+- USB
+  - 3x USB 3.2 Gen 1 Type-A
+  - 1x USB Type-C with Thunderbolt 3
+- Dimensions
+  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
+  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+-----------------+
+| Type                | Value           |
++=====================+=================+
+| Socketed flash      | no              |
++---------------------+-----------------+
+| Vendor              | Macronix        |
++---------------------+-----------------+
+| Model               | MX25L12872F     |
++---------------------+-----------------+
+| Size                | 16 MiB          |
++---------------------+-----------------+
+| Package             | SOIC-8          |
++---------------------+-----------------+
+| Internal flashing   | yes             |
++---------------------+-----------------+
+| External flashing   | yes             |
++---------------------+-----------------+
+```
+
+The flash chip (U53) is above the M.2 SSD connectors.
diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md
@@ -4,6 +4,6 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid
 
 ## Topics
 
-- [Native Ram Initialization](nri.md)
+- [Native RAM Initialization](nri.md)
 - [RAM initialization feature matrix](nri_features.md)
 - [ME Cleaner](me_cleaner.md)
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md
@@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties:
 +---------+-------------------------------------------------------------------+------------+--------------+
 ```
 
-## (Inoffical) register documentation
+## (Unoffical) register documentation
 - [Sandy Bridge - Register documentation](nri_registers.md)
 
 ## Frequency selection
@@ -83,7 +83,7 @@ in each DIMM's SPD.
 > **Note:** This feature is available since coreboot 4.4
 
 ### MRC cache
-The name *MRC cache* might be missleading as in case of *Native ram init*
+The name *MRC cache* might be misleading as in case of *Native RAM init*
 there's no MRC, but for historical reasons it's still named *MRC cache*.
 The MRC cache is part of flash memory that is writeable by coreboot.
 At the end of the boot process coreboot will write the RAM training results to

diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md
@@ -1,9 +1,9 @@
-# Inoffical Documentation of Intel MCHBAR register space.
+# Unofficial Documentation of Intel MCHBAR register space.
 
 The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device.
 
 This documentation is incomplete and might be incorrect.
-Please handle with care !
+Please handle with care!
 
 **MCHBAR + 0x4**
 

diff --git a/Documentation/payloads.md b/Documentation/payloads.md
@@ -21,7 +21,7 @@ mainline code.
 implementation of the UEFI Specifications that modern firmware for PCs is
 based on. There were various projects in the past to make it suitable as a
 coreboot payload, but these days this function is available directly in the
-CorebootPayloadPkg part of its source tree.
+UefiPayloadPkg part of its source tree.
 
 ## GRUB2
 

diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
@@ -59,19 +59,21 @@ be more frequent than was needed, so we scaled it back to twice a year.
 - [ ] If there are any deprecations announced for the following release,
       make sure that a list of currently affected boards and chipsets is
       part of the release notes.
-- [ ] Finalize release notes (as much as possible), without specifying
-      release commit ids.
+- [ ] Finalize release notes as much as possible
+- [ ] Prepare release notes template for following release
+- [ ] Update `Documentation/releases/index.md`
+- [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
+      boards supported by vboot.
 
 ### Day of release
 - [ ] Select a commit ID to base the release upon, announce to IRC,
       ask for testing.
 - [ ] Test the commit selected for release.
-- [ ] Update release notes with actual commit id, push to repo.
+- [ ] Submit release notes
 - [ ] Create new release notes doc template for the next version.
 - [ ] Fill in the release date, remove "Upcoming release" and other filler
       from the current release notes.
 - [ ] Run release script.
-- [ ] Run vboot_list script.
 - [ ] Test the release from the actual release tarballs.
 - [ ] Push signed Tag to repo.
 - [ ] Announce that the release tag is done on IRC.

diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -1,14 +1,73 @@
-Upcoming release - coreboot 4.14
-================================
+coreboot 4.14
+=============
 
-The 4.14 release is planned for May 2021.
+coreboot 4.14 was released on May 10th, 2021.
 
-Update this document with changes that should be in the release notes.
+Since 4.13 there have been 3660 new commits by 215 developers.
+Of these, about 50 contributed to coreboot for the first time.
+Welcome to the project!
 
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
+These changes have been all over the place, so that there's no
+particular area to focus on when describing this release: We had
+improvements to mainboards, to chipsets (including much welcomed
+work to open source implementations of what has been blobs before),
+to the overall architecture.
+
+Thank you to all developers who made coreboot the great open source
+firmware project that it is, and made our code better than ever.
+
+New mainboards
+--------------
+
+* AMD Bilby
+* AMD Majolica
+* GIGABYTE GA-D510UD
+* Google Blipper
+* Google Brya
+* Google Cherry
+* Google Collis
+* Google Copano
+* Google Cozmo
+* Google Cret
+* Google Drobit
+* Google Galtic
+* Google Gumboz
+* Google Guybrush
+* Google Herobrine
+* Google Homestar
+* Google Katsu
+* Google Kracko
+* Google Lalala
+* Google Makomo
+* Google Mancomb
+* Google Marzipan
+* Google Pirika
+* Google Sasuke
+* Google Sasukette
+* Google Spherion
+* Google Storo
+* Google Volet
+* HP 280 G2
+* Intel Alderlake-M RVP
+* Intel Alderlake-M RVP with Chrome EC
+* Intel Elkhartlake LPDDR4x CRB
+* Intel shadowmountain
+* Kontron COMe-mAL10
+* MSI H81M-P33 (MS-7817 v1.2)
+* Pine64 ROCKPro64
+* Purism Librem 14
+* System76 darp5
+* System76 galp3-c
+* System76 gaze15
+* System76 oryp5
+* System76 oryp6
+
+Removed mainboards
+------------------
+
+* Google Boldar
+* Intel Cannonlake U LPDDR4 RVP
+* Intel Cannonlake Y LPDDR4 RVP
 
 Deprecations and incompatible changes
 -------------------------------------
@@ -52,4 +111,51 @@ scenarios.
 Significant changes
 -------------------
 
-### Add significant changes here
+### AMD SoC cleanup and initial Cezanne APU support
+
+There's initial support for the AMD Cezanne APUs in the tree. This code
+hasn't started as a copy of the previous generation, but was based on a
+slightly modified version of the example/min86 SoC. During the cleanup
+of the existing Picasso SoC code the common parts of the code were
+moved to the common AMD SoC code, so that they could be used by the
+Cezanne code instead of adding another slightly different copy.
+
+### X86 bootblock layout
+
+The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favor of
+dynamically allocating the stage size; the Kconfig is still available
+to use as a fixed size and to enforce a maximum for selected chipsets.
+Linker sections are now top-aligned for a reduced flash footprint and to
+maintain the requirements of near jump from reset vector.
+
+### ACPI GNVS framework
+
+SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is
+now passed from within SMM_MODULE_LOADER. Allocation and initialisations
+for common ACPI GNVS table entries were largely moved to one centralized
+implementation.
+
+### Intel Xeon Scalable Processor support is now considered mature
+
+Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed
+primarily to serve the needs of the server market.
+
+coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
+This release has support for SkyLake-SP (SKX-SP) which is the 2nd
+generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+or the latest generation [2] on market.
+
+With this release, the codebase for multiple generations of Xeon-SP
+were unified and optimized:
+* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for
+this board is in Proof Of Concept Status.
+* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for
+this board is in DVT (Design Validation Test) exit equivalent status.
+Features supported, (performance/stability) test scopes, known issues,
+features gaps are described in [4].
+
+
+[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html
+[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html
+[3] ../mainboard/ocp/tiogapass.md
+[4] ../mainboard/ocp/deltalake.md
diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -0,0 +1,22 @@
+Upcoming release - coreboot 4.15
+================================
+
+The 4.15 release is planned for October 2021.
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Merged family of Asus mainboards using H61 chipset
+
+By using newer coreboot features like board variants and override devicetrees,
+lots of code can now be shared. This should ease maintenance and also make it
+easier for newcomers to add support for even more mainboards.
+
+### Add significant changes here
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -14,6 +14,7 @@ Release notes for previous releases
 * [4.11 - November 2019](coreboot-4.11-relnotes.md)
 * [4.12 - May 2020](coreboot-4.12-relnotes.md)
 * [4.13 - November 2020](coreboot-4.13-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -25,4 +26,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.14 - May 2021](coreboot-4.14-relnotes.md)
+* [4.15 - October 2021](coreboot-4.15-relnotes.md)
diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
@@ -1,15 +1,23 @@
 # vboot-enabled devices
 
+## AMD
+- Majolica
+
+## Clevo
+- N130WU / N131WU
+
 ## Emulation
 - QEMU x86 i440fx/piix4 (aka qemu -M pc)
 - QEMU x86 q35/ich9 (aka qemu -M q35, since v1.4)
 
 ## Facebook
+- fbg1701
 - Facebook Monolith
 
 ## Google
 - Asurada
 - Hayato
+- Spherion
 - Auron_Paine (Acer C740 Chromebook)
 - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))
 - Buddy (Acer Chromebase 24)
@@ -22,6 +30,7 @@
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
 - Butterfly (HP Pavilion Chromebook 14)
+- Cherry
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -56,6 +65,7 @@
 - Scarlet
 - Nefario
 - Rainier
+- Guybrush
 - Akemi
 - Dratini
 - Duffy Legacy (32MB)
@@ -79,6 +89,7 @@
 - Dooly
 - Ambassador
 - Genesis
+- Herobrine
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
@@ -94,6 +105,7 @@
 - Kodama
 - Kakadu
 - Flapjack
+- Katsu
 - Jacuzzi
 - Juniper
 - Kappa
@@ -104,7 +116,10 @@
 - Esche
 - Burnet
 - Fennel
+- Cozmo
+- Makomo
 - Link (Google Chromebook Pixel (2013))
+- Mancomb
 - Mistral
 - Nyan
 - Nyan Big (Acer Chromebook 13 (CB5-311))
@@ -175,21 +190,23 @@
 - Woomax
 - Dirinboz
 - Shuboz
+- Gumboz
 
 ## HP
 - Z220 SFF Workstation
 
 ## Intel
 - Alderlake-P RVP
 - Alderlake-P RVP with Chrome EC
+- Alderlake-M RVP
+- Alderlake-M RVP with Chrome EC
 - Basking Ridge CRB
-- Cannonlake U LPDDR4 RVP
-- Cannonlake Y LPDDR4 RVP
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11
 - Whiskeylake U DDR4 RVP
 - Coffeelake S U-DIMM DDR4 RVP8
 - Cometlake U DDR4 RVP
+- Elkhartlake LPDDR4x CRB
 - Emerald Lake 2 CRB
 - Galileo
 - Glkrvp
@@ -202,6 +219,7 @@
 - Kabylake DDR4 RVP8
 - Kabylake DDR4 RVP11
 - Kunimitsu
+- shadowmountain
 - Strago
 - Tigerlake UP3 RVP
 - Tigerlake UP4 RVP
@@ -255,7 +273,7 @@
 ## Supermicro
 - X11SSH-TF
 - X11SSM-F
-- X11SSH-F/X11SSH-LN4F
+- X11SSH-F/LN4F
 
 ## UP
 - Squared
diff --git a/Documentation/technotes/2021-05-code-coverage.md b/Documentation/technotes/2021-05-code-coverage.md
@@ -0,0 +1,56 @@
+# Unit Test Code Coverage
+
+Code coverage for the coreboot unit tests allows us to see what lines of
+code in the coreboot library are covered by unit tests, and allows a test
+author to see where they need to add test cases for additional coverage.
+
+Enable code coverage in your unit test build by setting the environment
+variable `COV` to 1; either `export COV=1` in your shell, or add it to your
+`make` command, e.g. `COV=1 make unit-tests`.
+
+The build output directory is either `build/tests` or `build/coverage`,
+depending on whether `COV=1` is set in the environment.
+
+All of the unit test targets are available with and without `COV=1`
+* `clean-unit-tests`
+* `build-unit-tests`
+* `run-unit-tests`
+* `unit-tests` (which is just `build-unit-tests` followed by `run-unit-tests`)
+
+There are two new `make` targets:
+* `coverage-report` generates a code coverage report from all of the
+GCOV data (`*.gcda` and `*.gcno` files) in the build directory. To view the
+coverage report, open `build/coverage/coverage_reports/index.html` in your web
+browser.
+* `clean-coverage-report` deletes just the coverage report.
+
+The `coverage-report` and `clean-coverage-report` targets automatically set
+`COV=1` if it is not already set in the environment.
+
+
+## Examples
+
+`COV=1 make unit-tests coverage-report` builds all of the unit tests with code
+coverage, runs the unit tests, and generates the code coverage report.
+
+`COV=1 make build-unit-tests` builds all of the unit tests with code coverage.
+
+`COV=1 make run-unit-tests` runs the unit tests, building them with code
+coverage if they are out-of-date.
+
+`COV=1 make coverage-report` creates the code coverage report. This
+target does not explicitly depend on the tests being built and run; it gathers
+the code coverage data from the output directory, which it assumes already
+exists.
+
+`COV=1 make tests/lib/uuid-test coverage-report` builds the uuid test
+with code coverage, runs it, and generates a code coverage report just for
+that test.
+
+As a demonstration that building with and without coverage uses different
+output directories:
+1. `make build-unit-tests` builds unit tests without code coverage into
+`build/tests`.
+2. `COV=1 make clean-unit-tests` cleans `build/coverage`
+3. `make build-unit-tests` doesn't need to build anything in `build/tests`,
+because those files weren't affected by the previous `clean-unit-tests`.
diff --git a/Documentation/tutorial/part3.md b/Documentation/tutorial/part3.md
@@ -3,6 +3,8 @@
 ## Introduction
 General thoughts about unit testing coreboot can be found in
 [Unit testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
+Additionally, [code coverage](../technotes/2021-05-code-coverage.md) support
+is available for unit tests.
 
 This document aims to guide developers through the process of adding and writing
 unit tests for coreboot modules.

diff --git a/MAINTAINERS b/MAINTAINERS
@@ -174,13 +174,20 @@ M:	Mike Banon <mikebdp2@gmail.com>
 S:	Maintained
 F:	src/mainboard/asus/am1i-a/
 
+ASUS H61 SERIES MAINBOARDS
+M:	Angel Pons <th3fanbus@gmail.com>
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/asus/h61-series/
+
 ASUS MAXIMUS IV GENE-Z MAINBOARD
 M:	Tristan Corrick <tristan@corrick.kiwi>
 S:	Maintained
 F:	src/mainboard/asus/maximus_iv_gene-z/
 
 ASUS P5QC PRO MAINBOARD & VARIANTS
 M:	Angel Pons <th3fanbus@gmail.com>
+R:	Stefan Ott <coreboot@desire.ch>
 S:	Maintained
 F:	src/mainboard/asus/p5qc/
 
@@ -189,30 +196,11 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/asus/p5qpl-am/
 
-ASUS P8H61-M LX MAINBOARD
-M:	Tristan Corrick <tristan@corrick.kiwi>
-S:	Maintained
-F:	src/mainboard/asus/p8h61-m_lx/
-
-ASUS P8H61-M LX3 R2.0 MAINBOARD
-M:	Angel Pons <th3fanbus@gmail.com>
-S:	Maintained
-F:	src/mainboard/asus/p8h61-m_lx3_r2_0/
-
-ASUS P8H61-M PRO MAINBOARD
+ASUS P8Z77 SERIES MAINBOARDS
 M:	Angel Pons <th3fanbus@gmail.com>
-S:	Maintained
-F:	src/mainboard/asus/p8h61-m_pro/
-
-ASUS P8Z77-M PRO MAINBOARD
 M:	Vlado Cibic <vladocb@protonmail.com>
 S:	Maintained
-F:	src/mainboard/asus/p8z77-m_pro/
-
-ASUS P8Z77-V LX2 MAINBOARD
-M:	Angel Pons <th3fanbus@gmail.com>
-S:	Maintained
-F:	src/mainboard/asus/p8z77-v_lx2/
+F:	src/mainboard/asus/p8z77-series/
 
 
 
@@ -342,6 +330,15 @@ M:	Mike Banon <mikebdp2@gmail.com>
 S:	Maintained
 F:	src/mainboard/lenovo/g505s/
 
+LENOVO X200 MAINBOARD
+R:	Stefan Ott <coreboot@desire.ch>
+S:	Maintained
+F:	src/mainboard/lenovo/x200/
+
+LENOVO X201 MAINBOARD
+R:	Stefan Ott <coreboot@desire.ch>
+S:	Maintained
+F:	src/mainboard/lenovo/x201/
 
 
 LIBRETREND LT1000 MAINBOARD

diff --git a/Makefile b/Makefile
@@ -24,7 +24,9 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
 LANG:=C
 LC_ALL:=C
 TZ:=UTC0
+ifneq ($(NOCOMPILE),1)
 SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
+endif
 # don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
 # are reproducible
 export LANG LC_ALL TZ SOURCE_DATE_EPOCH
@@ -122,8 +124,8 @@ ifneq ($(filter help%, $(MAKECMDGOALS)), )
 NOCOMPILE:=1
 UNIT_TEST:=1
 else
-ifneq ($(filter %-test %-tests, $(MAKECMDGOALS)),)
-ifneq ($(filter-out %-test %-tests, $(MAKECMDGOALS)),)
+ifneq ($(filter %-test %-tests %coverage-report, $(MAKECMDGOALS)),)
+ifneq ($(filter-out %-test %-tests %coverage-report, $(MAKECMDGOALS)),)
 $(error Cannot mix unit-tests targets with other targets)
 endif
 UNIT_TEST:=1

diff --git a/Makefile.inc b/Makefile.inc
@@ -193,6 +193,8 @@ endif
 ifneq ($(UPDATED_SUBMODULES),1)
 # try to fetch non-optional submodules if the source is under git
 forgetthis:=$(if $(GIT),$(shell git submodule update --init))
+# Checkout Cmocka repository
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka))
 ifeq ($(CONFIG_USE_BLOBS),y)
 # These items are necessary because each has update=none in .gitmodules.  They are ignored
 # until expressly requested and enabled with --checkout
@@ -300,21 +302,11 @@ endef
 # arg1: source file
 # arg2: binary file name
 cbfs-files-processor-nvramtool= \
-	$(eval $(2): $(1) $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout | $(objutil)/nvramtool/nvramtool ; \
+	$(eval $(2): $(1) $(top)/$(call strip_quotes,$(CONFIG_CMOS_LAYOUT_FILE)) | $(objutil)/nvramtool/nvramtool ; \
 		printf "    CREATE     $(2) (from $(1))\n"; \
-		$(objutil)/nvramtool/nvramtool -y $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout -D $(2).tmp -p $(1) && \
+		$(objutil)/nvramtool/nvramtool -y $(top)/$(call strip_quotes,$(CONFIG_CMOS_LAYOUT_FILE)) -D $(2).tmp -p $(1) && \
 		mv $(2).tmp $(2))
 
-#######################################################################
-# Link VSA binary to ELF-ish stage
-# arg1: source file
-# arg2: binary file name
-cbfs-files-processor-vsa= \
-	$(eval $(2): $(1) ; \
-		printf "    CREATE     $(2) (from $(1))\n"; \
-		$(OBJCOPY_ramstage) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(1) $(2).tmp && \
-		$(LD_ramstage) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(2).tmp -o $(2))
-
 #######################################################################
 # Reduce a .config file to its minimal representation
 # arg1: input

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,11 +1,11 @@
-CONFIG_LOCALVERSION="v4.13.0.6"
+CONFIG_LOCALVERSION="v4.14.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
+CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
@@ -19,4 +19,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y
 CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
 CONFIG_SORTBOOTORDER_REVISION=y
-CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
+CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.21"
diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,13 +1,14 @@
-CONFIG_LOCALVERSION="v4.13.0.6"
+CONFIG_LOCALVERSION="v4.14.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_BOARD_PCENGINES_APU2=y
 CONFIG_PXE_ROM_ID="8086,157b"
+CONFIG_BOARD_PCENGINES_APU2=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
+CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
@@ -21,4 +22,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y
 CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
 CONFIG_SORTBOOTORDER_REVISION=y
-CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
+CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.21"
diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.13.0.6"
+CONFIG_LOCALVERSION="v4.14.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y
@@ -7,7 +7,8 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
+CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
@@ -21,4 +22,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y
 CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
 CONFIG_SORTBOOTORDER_REVISION=y
-CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
+CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.21"
diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.13.0.6"
+CONFIG_LOCALVERSION="v4.14.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y
@@ -7,7 +7,8 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
+CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
@@ -21,4 +22,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y
 CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
 CONFIG_SORTBOOTORDER_REVISION=y
-CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
+CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.21"
diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.13.0.6"
+CONFIG_LOCALVERSION="v4.14.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y
@@ -7,7 +7,8 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
+CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
@@ -21,4 +22,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y
 CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
 CONFIG_SORTBOOTORDER_REVISION=y
-CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
+CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.21"
diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.13.0.6"
+CONFIG_LOCALVERSION="v4.14.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU6=y
@@ -7,7 +7,8 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
+CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
@@ -21,4 +22,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y
 CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
 CONFIG_SORTBOOTORDER_REVISION=y
-CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
+CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.21"
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -93,12 +93,14 @@ payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out
 payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
 
 # add a SeaBIOS bootorder file
+ifneq ($(CONFIG_SEABIOS_BOOTORDER_IN_FMAP),y)
 ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),)
 cbfs-files-y += bootorder
 bootorder-file := $(strip $(CONFIG_SEABIOS_BOOTORDER_FILE))
 bootorder-type := raw
 bootorder-align := 0x1000
 endif
+endif
 
 # add a SeaBIOS bootorder_map file
 ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_MAP_FILE)),)
@@ -166,6 +168,15 @@ $(call add_intermediate, seabios_thread_optionroms, $(CBFSTOOL))
 	$(CBFSTOOL) $< add-int -i 2 -n etc/threads
 endif
 
+ifeq ($(CONFIG_SEABIOS_BOOTORDER_IN_FMAP),y)
+ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),)
+$(call add_intermediate, seabios_bootorder_fmap, $(CBFSTOOL))
+	@printf "    SeaBIOS    Fill bootorder region\n"
+	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< write -r BOOTORDER -u -i 0 -f /dev/zero 2>/dev/null)
+	$(CBFSTOOL) $< write -r BOOTORDER -u -i 0 -f $(CONFIG_SEABIOS_BOOTORDER_FILE)
+endif
+endif
+
 # Depthcharge
 
 payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL)
@@ -187,10 +198,9 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
 		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
 		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
-		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
-		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
+		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
 		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -80,6 +80,12 @@ config PAYLOAD_CONFIGFILE
 	  SeaBIOS payload.  In general, if the option is used, the default
 	  would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
 
+config SEABIOS_BOOTORDER_IN_FMAP
+	bool "SeaBIOS bootorder file in FMAP"
+	default n
+	help
+	  Place the SeaBIOS bootorder into BOOTORDER FMAP region.
+
 config SEABIOS_BOOTORDER_FILE
 	string "SeaBIOS bootorder file"
 	default ""

diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
@@ -4,25 +4,25 @@ config PAYLOAD_FILE
 	string "Tianocore binary"
 	default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd"
 	help
-	  The result of a corebootPkg build
+	  The result of a UefiPayloadPkg build
 
 choice
 	prompt "Tianocore payload"
-	default TIANOCORE_COREBOOTPAYLOAD
+	default TIANOCORE_UEFIPAYLOAD
 	help
-	  Select which type of payload Tianocore will build (default is CorebootPayload)
-	  CorebootPayload: MrChromebox's customized version of Tianocore which works on most
-	  (all?) x86_64 devices
-	  UEFIPayload: Use upstream Tianocore payload from https://github.com/tianocore/edk2
-
-config TIANOCORE_COREBOOTPAYLOAD
-	bool "CorebootPayload"
-	help
-	  Select this option to build using MrChromebox's custom Tianocore tree
-	  i.e. a version of Tianocore that builds without any errors and just works.
+	  Select which type of payload Tianocore will build (default is UefiPayload)
+	  UefiPayload: MrChromebox's customized fork of Tianocore which works on most
+	  x86_64 devices
+	  Upstream: Use upstream Tianocore payload from https://github.com/tianocore/edk2
 
 config TIANOCORE_UEFIPAYLOAD
 	bool "UEFIPayload"
+	help
+	  Select this option to build using MrChromebox's custom Tianocore fork,
+	  which incorporates fixes/improvements from System 76's and 9elements' trees.
+
+config TIANOCORE_UPSTREAM
+	bool "Upstream"
 	help
 	  Select this option if you want to use upstream EDK2 to build Tianocore.
 
@@ -34,29 +34,6 @@ config TIANOCORE_REVISION_ID
 	   The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master"
 	   for master branch of Tianocore release on github.
 
-choice
-	prompt "Target architecture"
-	default TIANOCORE_TARGET_X64
-	help
-	  The Tianocore coreboot Payload Package binary can be
-	  built for either only IA32 or both X64 and IA32 architectures.
-	  Select which architecture(s) to build for; default is to build
-	  for both X64 and IA32.
-
-config TIANOCORE_TARGET_IA32
-	bool "IA32"
-	help
-	  By selecting this option, the target architecture will be built
-	  for only IA32.
-
-config TIANOCORE_TARGET_X64
-	bool "X64"
-	help
-	  By selecting this option, the target architecture will be built
-	  for X64 and IA32.
-
-endchoice
-
 choice
 	prompt "Tianocore build"
 	default TIANOCORE_RELEASE
@@ -76,11 +53,6 @@ config TIANOCORE_RELEASE
 
 endchoice
 
-config TIANOCORE_USE_8254_TIMER
-	bool "TianoCore 8254 Timer"
-	help
-	  Use 8254 Timer for legacy support.
-
 config TIANOCORE_BOOTSPLASH_IMAGE
 	bool "Use a custom bootsplash image"
 	help

diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
@@ -9,16 +9,16 @@ project_git_repo=https://github.com/3mdeb/edk2
 project_git_branch=coreboot-4.7.x-uefi
 upstream_git_repo=https://github.com/tianocore/edk2
 
-# STABLE revision is 3mdeb's coreboot uefi (coreboot-4.7.x-uefi) branch
-ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y)
-bootloader=UefiPayloadPkg
-logo_pkg=MdeModulePkg
 build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+
+ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y)
 TAG=upstream/master
 else
-bootloader=CorebootPayloadPkg
-logo_pkg=CorebootPayloadPkg
-# STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
+# STABLE revision is MrChromebox's UefiPayloadPkg (ueifpayloadpkg) branch
+TAG=origin/$(project_git_branch)
+endif
+
+ifneq ($(CONFIG_TIANOCORE_REVISION_ID),)
 TAG=$(CONFIG_TIANOCORE_REVISION_ID)
 endif
 
@@ -30,23 +30,9 @@ else
 BUILD_TYPE=RELEASE
 endif
 
-ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
-TIMER=-DUSE_HPET_TIMER
-endif
-
 TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
 
-ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
-ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
-ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
-else
-ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
-endif
-else
-ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc
-endif
-
-BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor)
+BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor)
 
 all: clean build
 
@@ -90,9 +76,9 @@ build: update checktools
 		echo "    Copying custom bootsplash image"; \
 		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
 			/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				$(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \
+				$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
 			*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				$(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \
+				$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
 		esac \
 	fi; \
 	cd $(project_dir); \
@@ -105,7 +91,7 @@ build: update checktools
 		fi; \
 		build $(BUILD_STR); \
 		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
-		git checkout $(logo_pkg)/Logo/Logo.bmp > /dev/null 2>&1 || true
+		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true
 
 clean:
 	test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -385,6 +385,11 @@ config PC_KEYBOARD_LAYOUT_DE
 	depends on PC_KEYBOARD
 	default n
 
+config PC_KEYBOARD_TRANSLATION
+	bool "Enable or Disable translation in PC keyboard set 2 on exit"
+	depends on PC_KEYBOARD
+	default y
+
 endmenu
 
 menu "Drivers"

diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -658,7 +658,7 @@ void keyboard_disconnect(void)
 	/* Nobody but us seems to still use scancode set #1.
 	   So try to hand over with more modern settings. */
 	set_scancode_set(2);
-	i8042_set_kbd_translation(false);
+	i8042_set_kbd_translation(CONFIG(LP_PC_KEYBOARD_TRANSLATION));
 
 	/* Send keyboard disconnect command */
 	i8042_cmd(I8042_CMD_DIS_KB);

diff --git a/src/Kconfig b/src/Kconfig
@@ -682,6 +682,11 @@ config HAVE_OPTION_TABLE
 	  file containing NVRAM/CMOS bit definitions.
 	  It defaults to 'n' but can be selected in mainboard/*/Kconfig.
 
+config CMOS_LAYOUT_FILE
+	string
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout"
+	depends on HAVE_OPTION_TABLE
+
 config PCI_IO_CFG_EXT
 	bool
 	default n

diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig
@@ -38,6 +38,12 @@ config ACPI_NO_PCAT_8259
 	help
 	  Selected by platforms that don't expose a PC/AT 8259 PIC pair.
 
+config ACPI_EINJ
+	def_bool n
+	depends on HAVE_ACPI_TABLES
+	help
+	  This variable provides control for ACPI error injection table (EINJ)
+
 config HAVE_ACPI_TABLES
 	bool
 	help

diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc
@@ -10,7 +10,6 @@ ramstage-$(CONFIG_PCI) += acpigen_pci.c
 ramstage-y += acpigen_ps2_keybd.c
 ramstage-y += acpigen_usb.c
 ramstage-y += device.c
-ramstage-$(CONFIG_CHROMEOS_NVS) += chromeos-gnvs.c
 ramstage-$(CONFIG_ACPI_SOC_NVS) += gnvs.c
 ramstage-y += pld.c
 ramstage-y += sata.c

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
@@ -508,6 +508,23 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
 	return mem->length;
 }
 
+int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain,
+				u16 seg, u8 bus, u8 dev, u8 func, u32 flags)
+{
+	gia->type = ACPI_SRAT_STRUCTURE_GIA;
+	gia->length = sizeof(acpi_srat_gia_t);
+	gia->proximity_domain = proximity_domain;
+	gia->dev_handle_type = ACPI_SRAT_GIA_DEV_HANDLE_PCI;
+	/* First two bytes has segment number */
+	memcpy(gia->dev_handle, &seg, 2);
+	gia->dev_handle[2] = bus; /* Byte 2 has bus number */
+	/* Byte 3 has bits 7:3 for dev, bits 2:0 for func */
+	gia->dev_handle[3] = PCI_SLOT(dev) | PCI_FUNC(func);
+	gia->flags = flags;
+
+	return gia->length;
+}
+
 /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */
 void acpi_create_srat(acpi_srat_t *srat,
 		      unsigned long (*acpi_fill_srat)(unsigned long current))
@@ -539,6 +556,51 @@ void acpi_create_srat(acpi_srat_t *srat,
 	header->checksum = acpi_checksum((void *)srat, header->length);
 }
 
+int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory)
+{
+	memset((void *)mpda, 0, sizeof(acpi_hmat_mpda_t));
+
+	mpda->type = 0; /* Memory Proximity Domain Attributes structure */
+	mpda->length = sizeof(acpi_hmat_mpda_t);
+	/*
+	 * Proximity Domain for Attached Initiator field is valid.
+	 * Bit 1 and bit 2 are reserved since HMAT revision 2.
+	 */
+	mpda->flags = (1 << 0);
+	mpda->proximity_domain_initiator = initiator;
+	mpda->proximity_domain_memory = memory;
+
+	return mpda->length;
+}
+
+void acpi_create_hmat(acpi_hmat_t *hmat,
+		 unsigned long (*acpi_fill_hmat)(unsigned long current))
+{
+	acpi_header_t *header = &(hmat->header);
+	unsigned long current = (unsigned long)hmat + sizeof(acpi_hmat_t);
+
+	memset((void *)hmat, 0, sizeof(acpi_hmat_t));
+
+	if (!header)
+		return;
+
+	/* Fill out header fields. */
+	memcpy(header->signature, "HMAT", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->asl_compiler_revision = asl_revision;
+	header->length = sizeof(acpi_hmat_t);
+	header->revision = get_acpi_table_revision(HMAT);
+
+	current = acpi_fill_hmat(current);
+
+	/* (Re)calculate length and checksum. */
+	header->length = current - (unsigned long)hmat;
+	header->checksum = acpi_checksum((void *)hmat, header->length);
+}
+
 void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
 		      unsigned long (*acpi_fill_dmar)(unsigned long))
 {
@@ -785,6 +847,152 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
 	header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
 }
 
+/*
+ * This method adds the ACPI error injection capability. It fills the default information.
+ * HW dependent code (caller) can modify the defaults upon return. If no changes are necessary
+ * and the defaults are acceptable then caller can simply add the table (acpi_add_table).
+ * INPUTS:
+ * einj - ptr to the starting location of EINJ table
+ * actions - number of actions to trigger an error (HW dependent)
+ * addr - address of trigger action table. This should be ACPI reserved memory and it will be
+ *        shared between OS and FW.
+ */
+void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
+{
+	int i;
+	acpi_header_t *header = &(einj->header);
+	acpi_injection_header_t *inj_header = &(einj->inj_header);
+	acpi_einj_smi_t *einj_smi = (acpi_einj_smi_t *)addr;
+	acpi_einj_trigger_table_t *tat;
+	if (!header)
+		return;
+
+	printk(BIOS_DEBUG, "%s einj_smi = %p\n", __func__, einj_smi);
+	memset(einj_smi, 0, sizeof(acpi_einj_smi_t));
+	tat = (acpi_einj_trigger_table_t *)(einj_smi + sizeof(acpi_einj_smi_t));
+	tat->header_size =  16;
+	tat->revision =  0;
+	tat->table_size =  sizeof(acpi_einj_trigger_table_t) +
+		sizeof(acpi_einj_action_table_t) * actions - 1;
+	tat->entry_count = actions;
+	printk(BIOS_DEBUG, "%s trigger_action_table = %p\n", __func__, tat);
+
+	for (i = 0; i < actions; i++) {
+		tat->trigger_action[i].action = TRIGGER_ERROR;
+		tat->trigger_action[i].instruction = NO_OP;
+		tat->trigger_action[i].flags = FLAG_IGNORE;
+		tat->trigger_action[i].reg.space_id = ACPI_ADDRESS_SPACE_MEMORY;
+		tat->trigger_action[i].reg.bit_width = 64;
+		tat->trigger_action[i].reg.bit_offset = 0;
+		tat->trigger_action[i].reg.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
+		tat->trigger_action[i].reg.addr = 0;
+		tat->trigger_action[i].value = 0;
+		tat->trigger_action[i].mask = 0xFFFFFFFF;
+	}
+
+	acpi_einj_action_table_t default_actions[ACTION_COUNT] = {
+		[0] = {
+			.action = BEGIN_INJECT_OP,
+			.instruction = WRITE_REGISTER_VALUE,
+			.flags = FLAG_PRESERVE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state),
+			.value = 0,
+			.mask = 0xFFFFFFFF
+		},
+		[1] = {
+			.action = GET_TRIGGER_ACTION_TABLE,
+			.instruction = READ_REGISTER,
+			.flags = FLAG_IGNORE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->trigger_action_table),
+			.value = 0,
+			.mask = 0xFFFFFFFFFFFFFFFF
+		},
+		[2] = {
+			.action = SET_ERROR_TYPE,
+			.instruction = WRITE_REGISTER,
+			.flags = FLAG_PRESERVE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inject[0]),
+			.value = 0,
+			.mask = 0xFFFFFFFF
+		},
+		[3] = {
+			.action = GET_ERROR_TYPE,
+			.instruction = READ_REGISTER,
+			.flags = FLAG_IGNORE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inj_cap),
+			.value = 0,
+			.mask = 0xFFFFFFFF
+		},
+		[4] = {
+			.action = END_INJECT_OP,
+			.instruction = WRITE_REGISTER_VALUE,
+			.flags = FLAG_PRESERVE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state),
+			.value = 0,
+			.mask = 0xFFFFFFFF
+
+		},
+		[5] = {
+			.action = EXECUTE_INJECT_OP,
+			.instruction = WRITE_REGISTER_VALUE,
+			.flags = FLAG_PRESERVE,
+			.reg = EINJ_REG_IO(),
+			.value = 0x9a,
+			.mask = 0xFFFF,
+		},
+		[6] = {
+			.action = CHECK_BUSY_STATUS,
+			.instruction = READ_REGISTER_VALUE,
+			.flags = FLAG_IGNORE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_status),
+			.value = 1,
+			.mask = 1,
+		},
+		[7] = {
+			.action = GET_CMD_STATUS,
+			.instruction = READ_REGISTER,
+			.flags = FLAG_PRESERVE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->cmd_sts),
+			.value = 0,
+			.mask = 0x1fe,
+		},
+		[8] = {
+			.action = SET_ERROR_TYPE_WITH_ADDRESS,
+			.instruction = WRITE_REGISTER,
+			.flags = FLAG_PRESERVE,
+			.reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->setaddrtable),
+			.value = 1,
+			.mask = 0xffffffff
+		}
+	};
+
+	einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP;
+	einj_smi->trigger_action_table = (u64) (uintptr_t)tat;
+
+	for (i = 0; i < ACTION_COUNT; i++)
+		printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i,
+			default_actions[i].reg.addr);
+
+	memset((void *)einj, 0, sizeof(*einj));
+
+	/* Fill out header fields. */
+	memcpy(header->signature, "EINJ", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->asl_compiler_revision = asl_revision;
+	header->length = sizeof(acpi_einj_t);
+	header->revision = 1;
+	inj_header->einj_header_size = sizeof(acpi_injection_header_t);
+	inj_header->entry_count = ACTION_COUNT;
+
+	printk(BIOS_DEBUG, "%s einj->action_table = %p\n",
+		 __func__, einj->action_table);
+	memcpy((void *)einj->action_table, (void *)default_actions, sizeof(einj->action_table));
+	header->checksum = acpi_checksum((void *)einj, sizeof(*einj));
+}
+
 void acpi_create_vfct(const struct device *device,
 		      acpi_vfct_t *vfct,
 		      unsigned long (*acpi_fill_vfct)(const struct device *device,
@@ -1734,6 +1942,8 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return 2;
 	case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */
 		return 1; /* TODO Should probably be upgraded to 2 */
+	case HMAT: /* ACPI 6.4: 2 */
+		return 2;
 	case DMAR:
 		return 1;
 	case DRTM:
@@ -1758,6 +1968,8 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return 1;
 	case RSDP: /* ACPI 2.0 upto 6.3: 2 */
 		return 2;
+	case EINJ:
+		return 1;
 	case HEST:
 		return 1;
 	case NHLT:

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
@@ -781,6 +781,13 @@ void acpigen_write_device(const char *name)
 	acpigen_emit_namestring(name);
 }
 
+void acpigen_write_thermal_zone(const char *name)
+{
+	acpigen_emit_ext_op(THERMAL_ZONE_OP);
+	acpigen_write_len_f();
+	acpigen_emit_namestring(name);
+}
+
 void acpigen_write_STA(uint8_t status)
 {
 	/*

diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl
@@ -8,19 +8,13 @@
  */
 
 #if CONFIG(ACPI_SOC_NVS)
-External (NVB0, IntObj)
-External (NVS0, IntObj)
-OperationRegion (GNVS, SystemMemory, NVB0, NVS0)
+External (GNVS, OpRegionObj)
 #endif
 
 #if CONFIG(ACPI_HAS_DEVICE_NVS)
-External (NVB1, IntObj)
-External (NVS1, IntObj)
-OperationRegion (DNVS, SystemMemory, NVB1, NVS1)
+External (DNVS, OpRegionObj)
 #endif
 
 #if CONFIG(CHROMEOS_NVS)
-External (NVB2, IntObj)
-External (NVS2, IntObj)
-OperationRegion (CNVS, SystemMemory, NVB2, NVS2)
+External (CNVS, OpRegionObj)
 #endif
diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c
diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c
@@ -38,8 +38,10 @@ void acpi_create_gnvs(void)
 	if (CONFIG(CONSOLE_CBMEM))
 		gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 
-	if (CONFIG(CHROMEOS_NVS))
-		gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
+	if (CONFIG(CHROMEOS_NVS)) {
+		chromeos_acpi_t *init = (void *)((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
+		chromeos_init_chromeos_acpi(init);
+	}
 }
 
 void *acpi_get_gnvs(void)
@@ -67,30 +69,28 @@ __weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }
 /* Called from write_acpi_tables() only on normal boot path. */
 void acpi_fill_gnvs(void)
 {
+	const struct opregion gnvs_op = OPREGION("GNVS", SYSTEMMEMORY, (uintptr_t)gnvs, 0x100);
+	const struct opregion cnvs_op =	OPREGION("CNVS", SYSTEMMEMORY,
+					(uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET, 0xf00);
+	const struct opregion dnvs_op = OPREGION("DNVS", SYSTEMMEMORY,
+					(uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET, 0x1000);
+
 	if (!gnvs)
 		return;
 
 	soc_fill_gnvs(gnvs);
 	mainboard_fill_gnvs(gnvs);
 
 	acpigen_write_scope("\\");
-	acpigen_write_name_dword("NVB0", (uintptr_t)gnvs);
-	acpigen_write_name_dword("NVS0", 0x100);
-	acpigen_pop_len();
+	acpigen_write_opregion(&gnvs_op);
 
-	if (CONFIG(CHROMEOS_NVS)) {
-		acpigen_write_scope("\\");
-		acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
-		acpigen_write_name_dword("NVS2", 0xf00);
-		acpigen_pop_len();
-	}
+	if (CONFIG(CHROMEOS_NVS))
+		acpigen_write_opregion(&cnvs_op);
 
-	if (CONFIG(ACPI_HAS_DEVICE_NVS)) {
-		acpigen_write_scope("\\");
-		acpigen_write_name_dword("NVB1", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
-		acpigen_write_name_dword("NVS1", 0x1000);
-		acpigen_pop_len();
-	}
+	if (CONFIG(ACPI_HAS_DEVICE_NVS))
+		acpigen_write_opregion(&dnvs_op);
+
+	acpigen_pop_len();
 }
 
 int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs_)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
@@ -147,9 +147,10 @@ config PRERAM_CBMEM_CONSOLE_SIZE
 config CBFS_MCACHE_SIZE
 	hex
 	depends on !NO_CBFS_MCACHE
-	default 0x2000
+	default 0x4000
 	help
-	  Increase this value if you see CBFS mcache overflow warnings.
+	  Increase this value if you see CBFS mcache overflow warnings. Do NOT
+	  change this value for vboot RW updates!
 
 config PC80_SYSTEM
 	bool

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -11,19 +11,21 @@ NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
 OPTION_TABLE_H:=
 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
 
+CMOS_LAYOUT_FILE := $(top)/$(call strip_quotes,$(CONFIG_CMOS_LAYOUT_FILE))
+
 cbfs-files-y += cmos_layout.bin
 cmos_layout.bin-file = $(obj)/cmos_layout.bin
 cmos_layout.bin-type = cmos_layout
 
-$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
+$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(CMOS_LAYOUT_FILE)
 	@printf "    OPTION     $(subst $(obj)/,,$(@))\n"
-	$(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@
+	$(NVRAMTOOL) -y $(CMOS_LAYOUT_FILE) -L $@
 
 OPTION_TABLE_H:=$(obj)/option_table.h
 
-$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
+$(OPTION_TABLE_H): $(NVRAMTOOL) $(CMOS_LAYOUT_FILE)
 	@printf "    OPTION     $(subst $(obj)/,,$(@))\n"
-	$(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@
+	$(NVRAMTOOL) -y $(CMOS_LAYOUT_FILE) -H $@
 endif # CONFIG_HAVE_OPTION_TABLE
 
 stripped_vgabios_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_ID))
@@ -91,7 +93,8 @@ else
 $(eval $(call early_x86_stage,bootblock,elf64-x86-64))
 endif
 
-bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += walkcbfs.S
+$(call src-to-obj,bootblock,$(dir)/walkcbfs.S): $(obj)/fmap_config.h
+bootblock-y += walkcbfs.S
 
 endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
@@ -101,7 +104,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
 
-verstage-y += assembly_entry.S
+verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += assembly_entry.S
 verstage-y += boot.c
 verstage-y += post.c
 verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
@@ -89,7 +89,7 @@ _start:
 	 *	bss is cleared.   Now we call the main routine and
 	 *	let it do the rest.
 	 */
-	post_code(POST_PRE_HARDWAREMAIN)	/* post fe */
+	post_code(POST_PRE_HARDWAREMAIN)	/* post 6e */
 
 	andl	$0xFFFFFFF0, %esp
 

diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
@@ -1,13 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#define CBFS_HEADER_PTR 0xfffffffc
-
-#define CBFS_HEADER_MAGIC 0
-#define CBFS_HEADER_VERSION (CBFS_HEADER_MAGIC + 4)
-#define CBFS_HEADER_ROMSIZE (CBFS_HEADER_VERSION + 4)
-#define CBFS_HEADER_BOOTBLOCKSIZE (CBFS_HEADER_ROMSIZE + 4)
-#define CBFS_HEADER_ALIGN (CBFS_HEADER_BOOTBLOCKSIZE + 4)
-#define CBFS_HEADER_OFFSET (CBFS_HEADER_ALIGN + 4)
+#include <fmap_config.h>
 
 /* we use this instead of CBFS_HEADER_ALIGN because the latter is retired. */
 #define CBFS_ALIGNMENT 64
@@ -33,14 +26,7 @@
 walkcbfs_asm:
 	cld
 
-	mov CBFS_HEADER_PTR, %eax
-	mov CBFS_HEADER_ROMSIZE(%eax), %ecx
-	bswap %ecx
-	mov $0, %ebx
-	sub %ecx, %ebx	/* ROM base address in ebx */
-	mov CBFS_HEADER_OFFSET(%eax), %ecx
-	bswap %ecx
-	add %ecx, %ebx	/* address where we start looking for LARCHIVEs */
+	movl $FMAP_SECTION_COREBOOT_START, %ebx
 
 	/* determine filename length */
 	mov $0, %eax
@@ -96,17 +82,11 @@ tryharder:
 	mov %ecx, %ebx
 
 check_for_exit:
-	/* look if we should exit: did we pass into the bootblock already? */
-	mov CBFS_HEADER_PTR, %ecx
-	mov CBFS_HEADER_BOOTBLOCKSIZE(%ecx), %ecx
-	bswap %ecx
-	not %ecx
-	add $1, %ecx
+	/* if addr <= COREBOOT_END - 1, continue */
+#define FMAP_SECTION_COREBOOT_END (FMAP_SECTION_COREBOOT_START - 1 + FMAP_SECTION_COREBOOT_SIZE)
 
+	movl $FMAP_SECTION_COREBOOT_END, %ecx
 	cmp %ecx, %ebx
-	/* if bootblockstart >= addr (==we're still in the data area),
-	 * jump back
-	 */
 	jbe walker
 
 out:

diff --git a/src/console/init.c b/src/console/init.c
@@ -26,7 +26,7 @@ static void init_log_level(void)
 	console_loglevel = get_console_loglevel();
 
 	if (!FIRST_CONSOLE)
-		console_loglevel = get_int_option("debug_level", console_loglevel);
+		console_loglevel = get_uint_option("debug_level", console_loglevel);
 }
 
 int console_log_level(int msg_level)

diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -12,4 +12,3 @@ subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
 subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -15,4 +15,3 @@ subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
 subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
@@ -12,4 +12,3 @@ subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
 subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc
diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl
diff --git a/src/cpu/amd/pi/00630F01/chip_name.c b/src/cpu/amd/pi/00630F01/chip_name.c
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c
diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
@@ -13,4 +13,3 @@ subdirs-y += ../../../x86/lapic
 subdirs-y += ../../../x86/cache
 subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cbmem.h>
+#include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
 #include <cpu/x86/msr.h>
@@ -12,6 +14,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
+#include <smp/node.h>
 
 static void model_16_init(struct device *dev)
 {
@@ -20,36 +23,22 @@ static void model_16_init(struct device *dev)
 	u8 i;
 	msr_t msr;
 	int num_banks;
-	int msrno;
-#if CONFIG(LOGICAL_CPUS)
 	u32 siblings;
-#endif
 
-	disable_cache();
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	/* BSP: make a0000-bffff UC, c0000-fffff WB,
-	 * same as OntarioApMtrrSettingsList for APs
+	/*
+	 * All cores are initialized sequentially, so the solution for APs will be created
+	 * before they start.
 	 */
-	msr.lo = msr.hi = 0;
-	wrmsr(MTRR_FIX_16K_A0000, msr);
-	msr.lo = msr.hi = 0x1e1e1e1e;
-	wrmsr(MTRR_FIX_64K_00000, msr);
-	wrmsr(MTRR_FIX_16K_80000, msr);
-	for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
-		wrmsr(msrno, msr);
-
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
+	x86_setup_mtrrs_with_detect();
+	/*
+	 * Enable ROM caching on BSP we just lost when creating MTRR solution, for faster
+	 * execution of e.g. AmdInitLate
+	 */
+	if (boot_cpu()) {
+		mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
+				    MTRR_TYPE_WRPROT);
+	}
 	x86_mtrr_check();
-	x86_enable_cache();
 
 	/* zero the machine check error status registers */
 	msr = rdmsr(IA32_MCG_CAP);
@@ -62,20 +51,20 @@ static void model_16_init(struct device *dev)
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-#if CONFIG(LOGICAL_CPUS)
-	siblings = cpuid_ecx(0x80000008) & 0xff;
+	if (CONFIG(LOGICAL_CPUS)) {
+		siblings = cpuid_ecx(0x80000008) & 0xff;
 
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+		if (siblings > 0) {
+			msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+			msr.lo |= 1 << 28;
+			wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
 
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+			msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+			msr.hi |= 1 << (33 - 32);
+			wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+		}
+		printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
 
 	/* DisableCf8ExtCfg */
 	msr = rdmsr(NB_CFG_MSR);
@@ -88,6 +77,8 @@ static void model_16_init(struct device *dev)
 	wrmsr(HWCR_MSR, msr);
 
 	amd_update_microcode_from_cbfs();
+
+	display_mtrrs();
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
@@ -2,7 +2,6 @@
 
 config CPU_AMD_PI
 	bool
-	default y if CPU_AMD_PI_00630F01
 	default y if CPU_AMD_PI_00730F01
 	default n
 	select ARCH_ALL_STAGES_X86_32
@@ -38,5 +37,4 @@ config DCACHE_BSP_STACK_SIZE
 
 endif # CPU_AMD_PI
 
-source "src/cpu/amd/pi/00630F01/Kconfig"
 source "src/cpu/amd/pi/00730F01/Kconfig"
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc
@@ -21,14 +21,18 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 
 ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
 
-$(call add_intermediate, add_mcu_fit, $(IFITTOOL))
+$(call add_intermediate, add_mcu_fit, set_fit_ptr)
 	@printf "    UPDATE-FIT Microcode\n"
 	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
 
 # Second FIT in TOP_SWAP bootblock
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 
-$(call add_intermediate, add_ts_mcu_fit, $(IFITTOOL) set_fit_ptr_ts)
+$(call add_intermediate, set_ts_fit_ptr, $(IFITTOOL))
+	@printf "    UPDATE-FIT Top Swap: set FIT pointer to table\n"
+	$(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT $(TS_OPTIONS)
+
+$(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr)
 	@printf "    UPDATE-FIT Top Swap: Microcode\n"
 ifneq ($(FIT_ENTRY),)
 	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
@@ -40,11 +44,6 @@ intel_fit_ts-file := fit_table.c:struct
 intel_fit_ts-type := raw
 intel_fit_ts-align := 16
 
-PHONY += set_ts_fit_ptr
-set_ts_fit_ptr: $(obj)/coreboot.pre $(IFITTOOL)
-	@printf "    UPDATE-FIT Top Swap: set FIT pointer to table\n"
-	$(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT -t $(TS_OPTIONS)
-
 endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
 
 endif # CONFIG_CPU_MICROCODE_CBFS_NONE

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
@@ -19,7 +19,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
@@ -52,7 +52,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	RCBA32_OR(SOFT_RESET_CTRL, 1);
 
 	/* Delay before reset to avoid potential TPM lockout */
-	if (CONFIG(TPM1) || CONFIG(TPM2))
+	if (CONFIG(TPM))
 		mdelay(30);
 
 	/* Issue warm reset, will be "CPU only" due to soft reset data */

diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -21,7 +21,7 @@ void intel_sibling_init(struct device *cpu)
 	/* On the bootstrap processor see if I want sibling cpus enabled */
 	if (first_time) {
 		first_time = 0;
-		disable_siblings = get_int_option("hyper_threading", disable_siblings);
+		disable_siblings = get_uint_option("hyper_threading", disable_siblings);
 	}
 	result = cpuid(1);
 	/* Is hyperthreading supported */

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
@@ -29,6 +29,18 @@ struct microcode {
 	u32 reserved[3];
 };
 
+struct ext_sig_table {
+	u32 ext_sig_cnt;
+	u32 ext_tbl_chksm;
+	u32 res[3];
+};
+
+struct ext_sig_entry {
+	u32 sig;
+	u32 pf;
+	u32 chksm;
+};
+
 static inline u32 read_microcode_rev(void)
 {
 	/* Some Intel CPUs can be very finicky about the
@@ -117,9 +129,31 @@ uint32_t get_microcode_checksum(const void *microcode)
 	return ((struct microcode *)microcode)->cksum;
 }
 
+
+static struct ext_sig_table *ucode_get_ext_sig_table(const struct microcode *ucode)
+{
+	struct ext_sig_table *ext_tbl;
+	/* header + ucode data blob size */
+	u32 size = ucode->data_size + sizeof(struct microcode);
+
+	size_t ext_tbl_len = ucode->total_size - size;
+
+	if (ext_tbl_len < sizeof(struct ext_sig_table))
+		return NULL;
+
+	ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size);
+
+	if (ext_tbl_len < (sizeof(struct ext_sig_table) +
+				ext_tbl->ext_sig_cnt * sizeof(struct ext_sig_entry)))
+		return NULL;
+
+	return ext_tbl;
+}
+
 static const void *find_cbfs_microcode(void)
 {
 	const struct microcode *ucode_updates;
+	struct ext_sig_table *ext_tbl;
 	size_t microcode_len;
 	u32 eax;
 	u32 pf, rev, sig, update_size;
@@ -163,6 +197,22 @@ static const void *find_cbfs_microcode(void)
 		if ((ucode_updates->sig == sig) && (ucode_updates->pf & pf))
 			return ucode_updates;
 
+
+		/* Check if there is extended signature table */
+		ext_tbl = ucode_get_ext_sig_table(ucode_updates);
+
+		if (ext_tbl != NULL) {
+			int i;
+			struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
+
+			for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
+
+				if ((sig == entry->sig) && (pf & entry->pf)) {
+					return ucode_updates;
+				}
+			}
+		}
+
 		ucode_updates = (void *)((char *)ucode_updates + update_size);
 		microcode_len -= update_size;
 	}

diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
@@ -6,7 +6,6 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode
-subdirs-y += ../../x86/smm
 subdirs-y += ../smm/gen1
 
 ramstage-y += acpi.c

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
@@ -6,7 +6,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
@@ -17,6 +17,7 @@ config SLOT_SPECIFIC_OPTIONS
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
 	select SETUP_XIP_CACHE
+	select RESERVE_MTRRS_FOR_OS
 
 config DCACHE_RAM_BASE
 	hex

diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
@@ -11,7 +11,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 bootblock-y += ../car/p3/cache_as_ram.S

diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
@@ -3,7 +3,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -3,7 +3,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -3,7 +3,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -8,7 +8,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc
@@ -4,7 +4,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -3,7 +3,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 

diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc
@@ -4,7 +4,6 @@ subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep

diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc
@@ -2,13 +2,11 @@
 
 bootblock-y += cache_as_ram_bootblock.S
 bootblock-y += bootblock.c
-bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_64) += $(top)/src/arch/x86/walkcbfs.S
 
 romstage-y += ../intel/car/romstage.c
 
 ramstage-y += qemu.c
 
 subdirs-y += ../x86/mtrr
 subdirs-y += ../x86/lapic
-subdirs-y += ../x86/smm
 subdirs-y += ../x86/tsc
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -160,3 +160,13 @@ config SOC_SETS_MSRS
 	help
 	  The SoC requires different access methods for reading and writing
 	  the MSRs.  Use SoC specific routines to handle the MSR access.
+
+config RESERVE_MTRRS_FOR_OS
+	bool
+	default n
+	help
+	  This option allows a platform to reserve 2 MTRRs for the OS usage.
+	  The Intel SDM documents that the the first 6 MTRRs are intended for
+	  the system BIOS and the last 2 are to be reserved for OS usage.
+	  However, modern OSes use PAT to control cacheability instead of
+	  using MTRRs.
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
@@ -1,4 +1,5 @@
 subdirs-y += pae
+subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm
 
 all-$(CONFIG_ARCH_ALL_STAGES_X86_64) += 64bit/mode_switch.S
 

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
@@ -28,19 +28,16 @@
 #define MTRR_FIXED_WRBACK_BITS 0
 #endif
 
-/* 2 MTRRS are reserved for the operating system */
-#define BIOS_MTRRS 6
-#define OS_MTRRS   2
-#define MTRRS      (BIOS_MTRRS + OS_MTRRS)
+#define MIN_MTRRS	8
+
 /*
  * Static storage size for variable MTRRs. It's sized sufficiently large to
  * handle different types of CPUs. Empirically, 16 variable MTRRs has not
  * yet been observed.
  */
 #define NUM_MTRR_STATIC_STORAGE 16
 
-static int total_mtrrs = MTRRS;
-static int bios_mtrrs = BIOS_MTRRS;
+static int total_mtrrs;
 
 static void detect_var_mtrrs(void)
 {
@@ -56,7 +53,6 @@ static void detect_var_mtrrs(void)
 			total_mtrrs, NUM_MTRR_STATIC_STORAGE);
 		total_mtrrs = NUM_MTRR_STATIC_STORAGE;
 	}
-	bios_mtrrs = total_mtrrs - OS_MTRRS;
 }
 
 void enable_fixed_mtrr(void)
@@ -399,6 +395,11 @@ static void clear_var_mtrr(int index)
 	wrmsr(MTRR_PHYS_MASK(index), msr);
 }
 
+static int get_os_reserved_mtrrs(void)
+{
+	return CONFIG(RESERVE_MTRRS_FOR_OS) ? 2 : 0;
+}
+
 static void prep_var_mtrr(struct var_mtrr_state *var_state,
 			  uint64_t base, uint64_t size, int mtrr_type)
 {
@@ -407,17 +408,20 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state,
 	resource_t rsize;
 	resource_t mask;
 
-	/* Some variable MTRRs are attempted to be saved for the OS use.
-	 * However, it's more important to try to map the full address space
-	 * properly. */
-	if (var_state->mtrr_index >= bios_mtrrs)
-		printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");
 	if (var_state->mtrr_index >= total_mtrrs) {
 		printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n",
 		       var_state->mtrr_index, total_mtrrs);
 		return;
 	}
 
+	/*
+	 * If desired, 2 variable MTRRs are attempted to be saved for the OS to
+	 * use. However, it's more important to try to map the full address
+	 * space properly.
+	 */
+	if (var_state->mtrr_index >= total_mtrrs - get_os_reserved_mtrrs())
+		printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");
+
 	rbase = base;
 	rsize = size;
 
@@ -710,6 +714,7 @@ static int calc_var_mtrrs(struct memranges *addr_space,
 	__calc_var_mtrrs(addr_space, above4gb, address_bits, &wb_deftype_count,
 			 &uc_deftype_count);
 
+	const int bios_mtrrs = total_mtrrs - get_os_reserved_mtrrs();
 	if (wb_deftype_count > bios_mtrrs && uc_deftype_count > bios_mtrrs) {
 		printk(BIOS_DEBUG, "MTRR: Removing WRCOMB type. "
 		       "WB/UC MTRR counts: %d/%d > %d.\n",
@@ -813,6 +818,8 @@ static void _x86_setup_mtrrs(unsigned int above4gb)
 
 void x86_setup_mtrrs(void)
 {
+	/* Without detect, assume the minimum */
+	total_mtrrs = MIN_MTRRS;
 	/* Always handle addresses above 4GiB. */
 	_x86_setup_mtrrs(1);
 }

diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
@@ -132,9 +132,7 @@ asmlinkage void smm_handler_start(void *arg)
 	gnvs = (void *)(uintptr_t)smm_runtime.gnvs_ptr;
 
 	if (cpu >= CONFIG_MAX_CPUS) {
-		console_init();
-		printk(BIOS_CRIT,
-		       "Invalid CPU number assigned in SMM stub: %d\n", cpu);
+		/* Do not log messages to console here, it is not thread safe */
 		return;
 	}
 

diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
@@ -97,29 +97,32 @@ smm_trampoline32:
 	movw	%ax, %gs
 
 	/* The CPU number is calculated by reading the initial APIC id. Since
-	 * the OS can maniuplate the APIC id use the non-changing cpuid result
-	 * for APIC id (ax). A table is used to handle a discontiguous
+	 * the OS can manipulate the APIC id use the non-changing cpuid result
+	 * for APIC id (eax). A table is used to handle a discontiguous
 	 * APIC id space.  */
 apic_id:
-        mov $LAPIC_BASE_MSR, %ecx
-        rdmsr
-        andl $LAPIC_BASE_MSR_X2APIC_MODE, %eax
-        jz xapic
+	mov	$LAPIC_BASE_MSR, %ecx
+	rdmsr
+	and	$LAPIC_BASE_X2APIC_ENABLED, %eax
+	cmp	$LAPIC_BASE_X2APIC_ENABLED, %eax
+	jne	xapic
 
 x2apic:
-        mov $X2APIC_LAPIC_ID, %ecx
-        rdmsr
-        jmp apicid_end
+	mov	$0xb, %eax
+	mov	$0, %ecx
+	cpuid
+	mov	%edx, %eax
+	jmp	apicid_end
 
 xapic:
-        movl    $(LOCAL_APIC_ADDR | LAPIC_ID), %esi
-        movl    (%esi), %eax
-        shr     $24, %eax
+	mov	$1, %eax
+	cpuid
+	mov	%ebx, %eax
+	shr	$24, %eax
 
 apicid_end:
-
-        mov     $(apic_to_cpu_num), %ebx
-        xor     %ecx, %ecx
+	mov	$(apic_to_cpu_num), %ebx
+	xor	%ecx, %ecx
 
 1:
 	cmp	(%ebx, %ecx, 2), %ax

diff --git a/src/device/device.c b/src/device/device.c
@@ -66,12 +66,6 @@ void dev_finalize_chips(void)
 
 DECLARE_SPIN_LOCK(dev_lock)
 
-#if CONFIG(GFXUMA)
-/* IGD UMA memory */
-uint64_t uma_memory_base = 0;
-uint64_t uma_memory_size = 0;
-#endif
-
 /**
  * Allocate a new device structure.
  *
@@ -154,7 +148,7 @@ static void read_resources(struct bus *bus)
 {
 	struct device *curdev;
 
-	printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev),
+	printk(BIOS_SPEW, "%s %s bus %d link: %d\n", dev_path(bus->dev),
 	       __func__, bus->secondary, bus->link_num);
 
 	/* Walk through all devices and find which resources they need. */

diff --git a/src/device/device_const.c b/src/device/device_const.c
@@ -7,6 +7,7 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/resource.h>
+#include <fw_config.h>
 
 /** Linked list of ALL devices */
 DEVTREE_CONST struct device *DEVTREE_CONST all_devices = &dev_root;
@@ -383,3 +384,16 @@ DEVTREE_CONST struct device *dev_bus_each_child(const struct bus *parent,
 
 	return dev;
 }
+
+bool is_dev_enabled(const struct device *dev)
+{
+	if (!dev)
+		return false;
+
+	/* For stages with immutable device tree, first check if device is disabled because of
+	   fw_config probing. In these stages, dev->enabled does not reflect the true state of a
+	   device that uses fw_config probing. */
+	if (DEVTREE_EARLY && !fw_config_probe_dev(dev, NULL))
+		return false;
+	return dev->enabled;
+}
diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
@@ -79,19 +79,16 @@ void __noreturn pcidev_die(void)
 	die("PCI: dev is NULL!\n");
 }
 
-bool pci_dev_is_wake_source(const struct device *dev)
+bool pci_dev_is_wake_source(pci_devfn_t dev)
 {
 	unsigned int pm_cap;
 	uint16_t pmcs;
 
-	if (dev->path.type != DEVICE_PATH_PCI)
-		return false;
-
-	pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM);
+	pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM);
 	if (!pm_cap)
 		return false;
 
-	pmcs = pci_s_read_config16(PCI_BDF(dev), pm_cap + PCI_PM_CTRL);
+	pmcs = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL);
 
 	/* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */
 	return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS);

diff --git a/src/drivers/acpi/thermal_zone/Kconfig b/src/drivers/acpi/thermal_zone/Kconfig
@@ -0,0 +1,7 @@
+config DRIVERS_ACPI_THERMAL_ZONE
+	bool
+	default n
+	depends on HAVE_ACPI_TABLES
+	help
+	  Adds a chip driver that generates ACPI ThermalZones. See the chapter
+	  on Thermal Management in the ACPI specification.
diff --git a/src/drivers/acpi/thermal_zone/Makefile.inc b/src/drivers/acpi/thermal_zone/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_ACPI_THERMAL_ZONE) += thermal_zone.c
diff --git a/src/drivers/acpi/thermal_zone/chip.h b/src/drivers/acpi/thermal_zone/chip.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __DRIVERS_ACPI_THERMAL_ZONE_H__
+#define __DRIVERS_ACPI_THERMAL_ZONE_H__
+
+#include <types.h>
+
+/*
+ * All temperature units are in Celsius.
+ * All time units are in seconds.
+ */
+struct drivers_acpi_thermal_zone_config {
+	/* Description of the thermal zone */
+	const char *description;
+
+	/*
+	 * Device that will provide the temperature reading
+	 *
+	 * This device must have an ACPI method named `TMP` that accepts the
+	 * sensor ID as the first argument. It must then return an Integer containing the
+	 * sensor's temperature in deci-Kelvin.
+	 */
+	DEVTREE_CONST struct device *temperature_controller;
+
+	/* Used to identify the temperature sensor */
+	unsigned int sensor_id;
+
+	/* The polling period in seconds for this thermal zone. */
+	unsigned int polling_period;
+
+	/* The temperature (_CRT) at which the OS must shutdown the system. */
+	unsigned int critical_temperature;
+
+	/* The temperature (_HOT) at which the OS may choose to hibernate the system */
+	unsigned int hibernate_temperature;
+
+	struct acpi_thermal_zone_passive_config {
+		/*
+		 * The temperature (_PSV) at which the OS must activate passive cooling (i.e.,
+		 * throttle the CPUs).
+		 */
+		unsigned int temperature;
+
+		/**
+		 * DeltaP[%] = _TC1 * (Tn - Tn-1) + _TC2 * (Tn - Tt)
+		 * Where:
+		 * Tn = current temperature
+		 * Tt = target temperature (_PSV)
+		 *
+		 * If any of these values are 0, then one of the following defaults will be
+		 * used: TC1: 2, TC2: 5, TSP: 10
+		 */
+		unsigned int time_constant_1;
+		unsigned int time_constant_2;
+		unsigned int time_sampling_period;
+
+	} passive_config;
+
+	/* Place the ThermalZone in the \_TZ scope */
+	bool use_acpi1_thermal_zone_scope;
+};
+
+#endif /* __DRIVERS_ACPI_THERMAL_ZONE_H__ */
diff --git a/src/drivers/acpi/thermal_zone/thermal_zone.c b/src/drivers/acpi/thermal_zone/thermal_zone.c
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+#include <assert.h>
+#include <commonlib/bsd/helpers.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "chip.h"
+
+#define TZ_DEVICE_PATH	"\\_TZ"
+/* These defaults should be good enough for most systems */
+#define DEFAULT_TC1	2
+#define DEFAULT_TC2	5
+#define DEFAULT_TSP	10
+
+#define CELSIUS_TO_DECI_KELVIN(temp_c)	((temp_c) * 10 + 2731)
+#define SECONDS_TO_DECI_SECONDS(s)	((s) * 10)
+
+static const char *thermal_zone_acpi_name(const struct device *dev)
+{
+	char *name;
+
+	if (dev->path.type != DEVICE_PATH_GENERIC)
+		return NULL;
+
+	name = malloc(ACPI_NAME_BUFFER_SIZE);
+	snprintf(name, ACPI_NAME_BUFFER_SIZE, "TM%02X", dev->path.generic.id);
+
+	return name;
+}
+
+static void thermal_zone_fill_ssdt(const struct device *dev)
+{
+	struct drivers_acpi_thermal_zone_config *config = config_of(dev);
+	const char *scope;
+	const char *name;
+
+	assert(dev->path.type == DEVICE_PATH_GENERIC);
+
+	if (config->use_acpi1_thermal_zone_scope)
+		scope = TZ_DEVICE_PATH;
+	else
+		scope = acpi_device_scope(dev);
+
+	name = acpi_device_name(dev);
+
+	assert(name);
+	assert(scope);
+
+	if (!config->temperature_controller) {
+		printk(BIOS_ERR, "%s: missing temperature_controller\n", dev_path(dev));
+		return;
+	}
+
+	printk(BIOS_INFO, "%s.%s: %s at %s\n", scope, name, dev->chip_ops->name, dev_path(dev));
+
+	acpigen_write_scope(scope);
+	acpigen_write_thermal_zone(name);
+
+	if (config->description)
+		acpigen_write_name_string("_STR", config->description);
+
+	if (config->polling_period)
+		acpigen_write_name_integer(
+			"_TZP", SECONDS_TO_DECI_SECONDS(config->polling_period));
+
+	if (config->critical_temperature)
+		acpigen_write_name_integer(
+			"_CRT", CELSIUS_TO_DECI_KELVIN(config->critical_temperature));
+
+	if (config->hibernate_temperature)
+		acpigen_write_name_integer(
+			"_HOT", CELSIUS_TO_DECI_KELVIN(config->hibernate_temperature));
+
+	if (config->passive_config.temperature) {
+		acpigen_write_name_integer(
+			"_PSV", CELSIUS_TO_DECI_KELVIN(config->passive_config.temperature));
+
+		/*
+		 * The linux kernel currently has an artificial limit of 10 on the number of
+		 * references that can be returned in a list. If we don't respect this limit,
+		 * then the passive threshold won't work.
+		 *
+		 * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/include/acpi/acpi_bus.h;l=19
+		 */
+		acpigen_write_processor_package("_PSL", 0, MIN(10, dev_count_cpu()));
+
+		acpigen_write_name_integer("_TC1", config->passive_config.time_constant_1
+							   ?: DEFAULT_TC1);
+		acpigen_write_name_integer("_TC2", config->passive_config.time_constant_2
+							   ?: DEFAULT_TC2);
+		acpigen_write_name_integer(
+			"_TSP",
+			SECONDS_TO_DECI_SECONDS(config->passive_config.time_sampling_period
+							?: DEFAULT_TSP));
+	}
+
+	/*
+	 * Method (_TMP) {
+	 *   Return (<path>.TMP(<sensor_id>))
+	 * }
+	 */
+	acpigen_write_method_serialized("_TMP", 0);
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_namestring(acpi_device_path_join(config->temperature_controller, "TMP"));
+	acpigen_write_integer(config->sensor_id);
+	acpigen_write_method_end();
+
+	acpigen_write_thermal_zone_end();
+	acpigen_write_scope_end();
+}
+
+static struct device_operations thermal_zone_ops = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.acpi_name		= thermal_zone_acpi_name,
+	.acpi_fill_ssdt		= thermal_zone_fill_ssdt,
+};
+
+static void thermal_zone_enable_dev(struct device *dev)
+{
+	dev->ops = &thermal_zone_ops;
+}
+
+struct chip_operations drivers_acpi_thermal_zone_ops = {
+	CHIP_NAME("ACPI Thermal Zone")
+	.enable_dev = thermal_zone_enable_dev,
+};
diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c
@@ -9,7 +9,6 @@
  * without new builds of the binaryPI blobs.
  */
 #if !CONFIG(CPU_AMD_AGESA_BINARY_PI) || \
-	CONFIG(NORTHBRIDGE_AMD_PI_00630F01) || \
 	CONFIG(NORTHBRIDGE_AMD_PI_00730F01)
 
 #define HAS_ACPI_SRAT	TRUE

diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h
@@ -14,6 +14,7 @@ enum {
 
 /* Switch events type (Linux code emitted for EV_SW) */
 enum {
+	SW_MUTE_DEVICE = 0xe,
 	SW_PEN_INSERTED = 0xf,
 };
 
@@ -74,6 +75,8 @@ struct key_info {
 struct drivers_generic_gpio_keys_config {
 	/* Device name of the parent gpio-keys node */
 	const char *name;
+	/* Name of the input device - Optional */
+	const char *label;
 	/* GPIO line providing the key - Mandatory */
 	struct acpi_gpio gpio;
 	/* Is this a polled GPIO button? - Optional */

diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c
@@ -76,6 +76,8 @@ static void gpio_keys_fill_ssdt_generator(const struct device *dev)
 	/* DSD */
 	dsd = acpi_dp_new_table("_DSD");
 	acpi_dp_add_string(dsd, "compatible", drv_string);
+	if (config->label)
+		acpi_dp_add_string(dsd, "label", config->label);
 	if (config->is_polled)
 		acpi_dp_add_integer(dsd, "poll-interval",
 					config->poll_interval);

diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c
@@ -28,6 +28,9 @@ static void gl9755_enable(struct device *dev)
 	reg |= CFG2_LAT_L1_64US;
 	pci_write_config32(dev, CFG2, reg);
 
+	/* Turn off debug mode to enable SCP/OCP */
+	pci_and_config32(dev, CFG3, ~SCP_DEBUG);
+
 	/* Set Vendor Config to be non-configurable */
 	pci_and_config32(dev, CFG, ~CFG_EN);
 }

diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h
@@ -15,5 +15,7 @@
 #define   SNOOP_SCALE		(0x3 << 10)
 #define   NO_SNOOP_VALUE	(0x25 << 16)
 #define   NO_SNOOP_SCALE	(0x3 << 26)
+#define CFG3			0x70
+#define	  SCP_DEBUG		(0x1 << 19)
 
 #endif /* DRIVERS_GENESYSLOGIC_GL9755_H */
diff --git a/src/drivers/i2c/cs42l42/chip.h b/src/drivers/i2c/cs42l42/chip.h
@@ -106,4 +106,14 @@ struct drivers_i2c_cs42l42_config {
 	uint64_t bias_lvls[4];
 	/* headset bias ramp rate */
 	enum cs42l42_hs_bias_ramp_rate hs_bias_ramp_rate;
+	/*
+	 * cirrus,hs-bias-sense-disable: This is boolean property. If present the
+	 * HSBIAS sense is disabled. Configures HSBIAS output current sense through
+	 * the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce
+	 * the potential pop noise during the headset plug out slowly. But on some
+	 * platforms ESD voltage will affect it causing test to fail, especially
+	 * with CTIA headset type. For different hardware setups, a designer might
+	 * want to tweak default behavior.
+	 */
+	bool hs_bias_sense_disable;
 };
diff --git a/src/drivers/i2c/cs42l42/cs42l42.c b/src/drivers/i2c/cs42l42/cs42l42.c
@@ -87,6 +87,8 @@ static void cs42l42_fill_ssdt(const struct device *dev)
 
 	acpi_dp_add_integer_array(dsd, "cirrus,bias-lvls", config->bias_lvls, 4);
 	acpi_dp_add_integer(dsd, "cirrus,hs-bias-ramp-rate", config->hs_bias_ramp_rate);
+	if (config->hs_bias_sense_disable)
+		acpi_dp_add_integer(dsd, "cirrus,hs-bias-sense-disable", 1);
 
 	/* Write Device Property Hierarchy */
 	acpi_dp_write(dsd);

diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c
@@ -621,7 +621,6 @@ int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr,
 {
 	const int ic_clk = CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ;
 	struct dw_i2c_regs *regs;
-	uint16_t hcnt_min, lcnt_min;
 	int i;
 
 	regs = (struct dw_i2c_regs *)dw_i2c_addr;
@@ -637,35 +636,8 @@ int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr,
 		return 0;
 	}
 
-	/* If rise time is set use the time calculation. */
-	if (bcfg->rise_time_ns)
-		return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg,
-							ic_clk, config);
-
-	if (speed >= I2C_SPEED_HIGH) {
-		/* High speed */
-		hcnt_min = MIN_HS_SCL_HIGHTIME;
-		lcnt_min = MIN_HS_SCL_LOWTIME;
-	} else if (speed >= I2C_SPEED_FAST_PLUS) {
-		/* Fast-Plus speed */
-		hcnt_min = MIN_FP_SCL_HIGHTIME;
-		lcnt_min = MIN_FP_SCL_LOWTIME;
-	} else if (speed >= I2C_SPEED_FAST) {
-		/* Fast speed */
-		hcnt_min = MIN_FS_SCL_HIGHTIME;
-		lcnt_min = MIN_FS_SCL_LOWTIME;
-	} else {
-		/* Standard speed */
-		hcnt_min = MIN_SS_SCL_HIGHTIME;
-		lcnt_min = MIN_SS_SCL_LOWTIME;
-	}
-
-	config->speed = speed;
-	config->scl_hcnt = ic_clk * hcnt_min / KHz;
-	config->scl_lcnt = ic_clk * lcnt_min / KHz;
-	config->sda_hold = ic_clk * DEFAULT_SDA_HOLD_TIME / KHz;
-
-	return 0;
+	/* Use the time calculation. */
+	return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg, ic_clk, config);
 }
 
 static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed,

diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c
@@ -98,7 +98,7 @@ void i2c_generic_fill_ssdt(const struct device *dev,
 
 	/* Wake capabilities */
 	if (config->wake) {
-		acpigen_write_name_integer("_S0W", 4);
+		acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT);
 		acpigen_write_PRW(config->wake, 3);
 	}
 

diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -2,10 +2,6 @@
 
 ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
 
-verstage-y += car.c
-verstage-y += fsp_util.c
-verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c
-
 bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
 bootblock-y += fsp_util.c
 bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S

diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -8,8 +8,6 @@
 
 /* Perform Intel silicon init. */
 void intel_silicon_init(void);
-/* Called after the silicon init code has run. */
-void soc_after_silicon_init(void);
 /* Initialize UPD data before SiliconInit call. */
 void soc_silicon_init_params(SILICON_INIT_UPD *params);
 void mainboard_silicon_init_params(SILICON_INIT_UPD *params);

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -8,7 +8,6 @@
 #include <memory_info.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
-#include <soc/intel/common/mma.h>
 #include <soc/pm.h>
 
 struct romstage_params {
@@ -30,9 +29,6 @@ void mainboard_memory_init_params(struct romstage_params *params,
 	MEMORY_INIT_UPD *memory_params);
 void mainboard_pre_raminit(struct romstage_params *params);
 void mainboard_save_dimm_info(struct romstage_params *params);
-void mainboard_add_dimm_info(struct romstage_params *params,
-			     struct memory_info *mem_info,
-			     int channel, int dimm, int index);
 void raminit(struct romstage_params *params);
 /* Initialize memory margin analysis settings. */
 void setup_mma(MEMORY_INIT_UPD *memory_upd);
@@ -41,10 +37,6 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	MEMORY_INIT_UPD *new);
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd);
-void soc_pre_ram_init(struct romstage_params *params);
-/* Update the SOC specific memory config param for mma. */
-void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
-		struct mma_config_param *mma_cfg);
 void mainboard_after_memory_init(void);
 
 #endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
@@ -249,30 +249,6 @@ void raminit(struct romstage_params *params)
 	}
 }
 
-/* Initialize the UPD parameters for MemoryInit */
-__weak void mainboard_memory_init_params(
-	struct romstage_params *params,
-	MEMORY_INIT_UPD *upd_ptr)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Display the UPD parameters for MemoryInit */
-__weak void soc_display_memory_init_params(
-	const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
-{
-	printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
-	hexdump32(BIOS_SPEW, new, sizeof(*new));
-}
-
-/* Initialize the UPD parameters for MemoryInit */
-__weak void soc_memory_init_params(
-	struct romstage_params *params,
-	MEMORY_INIT_UPD *upd)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
 /* Initialize the SoC after MemoryInit */
 __weak void mainboard_after_memory_init(void)
 {

diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
@@ -13,11 +13,6 @@
 #include <timestamp.h>
 #include <cbmem.h>
 
-/* SOC initialization after FSP silicon init */
-__weak void soc_after_silicon_init(void)
-{
-}
-
 static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
 {
 	const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
@@ -141,7 +136,6 @@ static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header)
 	}
 
 	display_hob_info(fsp_info_header);
-	soc_after_silicon_init();
 }
 
 static void fsp_load(void)
@@ -171,17 +165,4 @@ void intel_silicon_init(void)
 __weak void mainboard_silicon_init_params(
 	SILICON_INIT_UPD *params)
 {
-};
-
-/* Display the UPD parameters for SiliconInit */
-__weak void soc_display_silicon_init_params(
-	const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
-{
-	printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
-	hexdump32(BIOS_SPEW, new, sizeof(*new));
-}
-
-/* Initialize the UPD parameters for SiliconInit */
-__weak void soc_silicon_init_params(SILICON_INIT_UPD *params)
-{
 }
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		ramstage-$(CONFIG_DRIVERS_ACPI_THERMAL_ZONE) += thermal_zone.c