30 changes: 9 additions & 21 deletions MAINTAINERS
Expand Up @@ -198,10 +198,10 @@ M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/gigabyte/ga-g41m-es2l

GIGABYTE GA-H61M-S2PV MAINBOARD
GIGABYTE GA-H61M SERIES MAINBOARDS
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/gigabyte/ga-h61m-s2pv
F: src/mainboard/gigabyte/ga-h61m-series

GOOGLE PANTHER MAINBOARD
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
Expand All @@ -223,7 +223,7 @@ F: src/mainboard/google/slippy/
F: src/mainboard/google/stout/

OPENCELLULAR MAINBOARDS
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
M: Christian Walter <christian.walter@9elements.com>
M: Patrick Rudolph <patrick.rudolph@9elements.com>
S: Supported
F: src/mainboard/opencellular/elgon/
Expand Down Expand Up @@ -374,10 +374,6 @@ S: Supported
F: src/drivers/aspeed/common/
F: src/drivers/aspeed/ast2050/

ATI MACH64 Driver
S: Orphan
F: src/drivers/ati/mach64/

ABUILD
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
Expand Down Expand Up @@ -409,13 +405,10 @@ F: util/rockchip/

ORPHANED ARM SOCS
S: Orphaned
F: src/cpu/allwinner/
F: src/cpu/armltd/
F: src/cpu/ti/
F: src/soc/marvell/
F: src/soc/qualcomm/
F: src/soc/samsung/
F: util/arm_boot_tools/
F: util/exynos/
F: util/ipqheader/

Expand Down Expand Up @@ -455,7 +448,7 @@ M: Stefan Reinauer <stefan.reinauer@coreboot.org>
F: util/inteltool/

INTELMETOOL
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
M: Christian Walter <christian.walter@9elements.com>
F: util/intelmetool/

ME_CLEANER
Expand Down Expand Up @@ -517,15 +510,11 @@ F: src/drivers/uart/

NVRAM
F: util/nvramtool/
F: util/optionlist/
F: payloads/nvramcui/

LIBPAYLOAD
F: payloads/libpayload/

BAYOU PAYLOAD
F: payloads/bayou/

COREINFO PAYLOAD
F: payloads/coreinfo/

Expand All @@ -535,7 +524,7 @@ M: Martin Roth <gaumless@gmail.com>
F: payloads/external

LINUXBOOT PAYLOAD INTEGRATION
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
M: Christian Walter <christian.walter@9elements.com>
M: Marcello Sylvester Bauer <info@marcellobauer.com>
S: Supported
F: payloads/external/LinuxBoot
Expand All @@ -545,10 +534,9 @@ M: Aaron Durbin <adurbin@chromium.org>
F: src/security/vboot/

TPM SUPPORT
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
M: Christian Walter <christian.walter@9elements.com>
S: Supported
F: src/drivers/*/tpm/
F: src/security/vboot/vboot_crtm.*
F: src/security/tpm

DOCKER
Expand Down Expand Up @@ -597,7 +585,7 @@ MISSING: ELOG

MISSING: SPI

# *** Infrastructure Owners***
# *** Infrastructure Owners ***
# This is intended to let people know who they should contact for issues with various infrastructure pieces.
# Hardware
# Owners: Stefan, Patrick
Expand All @@ -608,11 +596,11 @@ MISSING: SPI
# Backups:

# Website
# Owners: Martin, Philipp
# Owners: Martin
# Backups: Patrick, Stefan

# Documentation Website
# Owners: Patrick, Philipp
# Owners: Patrick
# Backups:

CODE OF CONDUCT
Expand Down
80 changes: 35 additions & 45 deletions Makefile.inc
Expand Up @@ -896,52 +896,42 @@ FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A
# X86 CONSOLE FMAP region
#
# position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
FMAP_CONSOLE_BASE := 0

FMAP_CURRENT_BASE := 0

ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE)
FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
FMAP_CONSOLE_SIZE := 0
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE))
else
FMAP_CONSOLE_ENTRY :=
endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
endif

#
# X86 RW_MRC_CACHE FMAP region
#
# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
$(FMAP_CONSOLE_SIZE)), 0x10000)
FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000)
FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
FMAP_MRC_CACHE_BASE := 0
FMAP_MRC_CACHE_SIZE := 0
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
else
FMAP_MRC_CACHE_ENTRY :=
endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
endif

#
# X86 SMMSTORE FMAP region
#
# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled
ifeq ($(CONFIG_SMMSTORE),y)
FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
$(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000)
FMAP_SMMSTORE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000)
FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE)
FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE)
else # ifeq ($(CONFIG_SMMSTORE),y)
FMAP_SMMSTORE_BASE := 0
FMAP_SMMSTORE_SIZE := 0
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE))
else
FMAP_SMMSTORE_ENTRY :=
endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
endif

#
# X86 FMAP region
#
#
# position, size
FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \
$(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE))
FMAP_FMAP_BASE := $(FMAP_CURRENT_BASE)
FMAP_FMAP_SIZE := 0x200

#
Expand All @@ -950,7 +940,9 @@ FMAP_FMAP_SIZE := 0x200
# position and size of CBFS, relative to BIOS_BASE
FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))

else # ifeq ($(CONFIG_ARCH_X86),y)

DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
# entire flash
FMAP_ROM_ADDR := 0
Expand All @@ -961,49 +953,43 @@ FMAP_BIOS_BASE := 0
FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE)
# position and size of flashmap, relative to BIOS_BASE
FMAP_FMAP_BASE := 0x20000
FMAP_FMAP_SIZE := 0x100
FMAP_FMAP_SIZE := 0x200

FMAP_CURRENT_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))

#
# NON-X86 CONSOLE FMAP region
#
# position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
FMAP_CONSOLE_BASE := $(FMAP_CURRENT_BASE)
FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
FMAP_CONSOLE_BASE := 0
FMAP_CONSOLE_SIZE := 0
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE))
else
FMAP_CONSOLE_ENTRY :=
endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
endif

#
# NON-X86 RW_MRC_CACHE FMAP region
#
# position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
$(FMAP_CONSOLE_SIZE)), 0x10000)
else
FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \
$(FMAP_FMAP_SIZE)), 0x10000)
endif
FMAP_MRC_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x10000)
FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
FMAP_MRC_CACHE_BASE := 0
FMAP_MRC_CACHE_SIZE := 0
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
else
FMAP_MRC_CACHE_ENTRY :=
endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
endif

#
# NON-X86 COREBOOT default cbfs FMAP region
#
# position and size of CBFS, relative to BIOS_BASE
FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE) $(FMAP_CONSOLE_SIZE) \
$(FMAP_MRC_CACHE_SIZE))
FMAP_CBFS_BASE := $(FMAP_CURRENT_BASE)
FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))

endif # ifeq ($(CONFIG_ARCH_X86),y)

$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
Expand Down Expand Up @@ -1111,6 +1097,10 @@ ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
@printf " SeaBIOS Add sercon-port file\n"
$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
endif
ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
@printf " SeaBIOS Thread optionroms\n"
$(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads
endif
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
Expand Down
7 changes: 7 additions & 0 deletions configs/config.emulation_qemu_aarch64_fit_support_timestamps
@@ -0,0 +1,7 @@
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_TIMESTAMPS_ON_CONSOLE=y
CONFIG_MAINBOARD_VENDOR="Emulation"
CONFIG_CBFS_SIZE=0x1000000
CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
CONFIG_PAYLOAD_FIT_SUPPORT=y
File renamed without changes.
1 change: 0 additions & 1 deletion configs/config.google_meep_cros
Expand Up @@ -14,7 +14,6 @@ CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y

# Event Logging
CONFIG_CMOS_POST=y
CONFIG_CMOS_POST_EXTRA=y
CONFIG_CMOS_POST_OFFSET=0x70
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_ELOG=y
Expand Down
1 change: 0 additions & 1 deletion configs/config.google_reef_cros
Expand Up @@ -10,5 +10,4 @@ CONFIG_SPI_FLASH_SMM=y
# CONFIG_CONSOLE_SERIAL is not set
CONFIG_CMOS_POST=y
CONFIG_CMOS_POST_OFFSET=0x70
CONFIG_CMOS_POST_EXTRA=y
CONFIG_PAYLOAD_NONE=y
2 changes: 0 additions & 2 deletions configs/config.intel_coffeelake_rvp11.fsp_car
Expand Up @@ -2,8 +2,6 @@ CONFIG_USE_BLOBS=y
CONFIG_VENDOR_INTEL=y
CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_USE_CANNONLAKE_FSP_CAR=y
CONFIG_RUN_FSP_GOP=y
CONFIG_FSP_USE_REPO=y
CONFIG_PAYLOAD_NONE=y
6 changes: 4 additions & 2 deletions configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.5"
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_NO_GFX_INIT=y
Expand All @@ -16,5 +16,7 @@ CONFIG_PXE_ADD_SCRIPT=y
CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="3754fd440f4009b62244e0f95c56bbb12c2fffcb"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.17"
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.5"
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
Expand All @@ -21,4 +21,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.17"
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.5"
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
Expand All @@ -20,4 +20,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.17"
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.5"
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
Expand All @@ -20,4 +20,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.17"
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.5"
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
Expand All @@ -21,4 +21,4 @@ CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.17"
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
3 changes: 2 additions & 1 deletion payloads/Kconfig
Expand Up @@ -132,7 +132,8 @@ config MEMTEST_SECONDARY_PAYLOAD
config NVRAMCUI_SECONDARY_PAYLOAD
bool "Load nvramcui as a secondary payload"
default n
depends on ARCH_X86
depends on ARCH_X86 && HAVE_OPTION_TABLE
select USE_OPTION_TABLE
help
nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.
Expand Down
5 changes: 4 additions & 1 deletion payloads/external/depthcharge/Makefile
Expand Up @@ -10,6 +10,7 @@ libpayload_dir=$(abspath $(CURDIR)/../../libpayload)
libpayload_install_dir=$(output_dir)/lp_$(BOARD)

VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot)
EC_HEADERS ?= $(abspath $(CURDIR)/../../../3rdparty/chromeec/include)

TAG-$(DEPTHCHARGE_MASTER)=origin/master
TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID)
Expand Down Expand Up @@ -79,13 +80,15 @@ config: $(project_dir)/.version_$(TAG-y) $(libpayload_install_dir)
cd $(project_dir) && \
$(MAKE) BOARD=$(BOARD) \
LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
VB_SOURCE=$(VBOOT_SOURCE) defconfig
VB_SOURCE=$(VBOOT_SOURCE) \
EC_HEADERS=$(EC_HEADERS) defconfig

build: config
echo " MAKE $(project_name) $(TAG-y)"
$(MAKE) -C $(project_dir) depthcharge BOARD=$(BOARD) \
LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
VB_SOURCE=$(VBOOT_SOURCE) \
EC_HEADERS=$(EC_HEADERS) \
PATH="$(abspath ../../../build/util/cbfstool):$$PATH"

clean:
Expand Down
8 changes: 8 additions & 0 deletions payloads/libpayload/configs/config.bubs
@@ -0,0 +1,8 @@
CONFIG_LP_CHROMEOS=y
CONFIG_LP_ARCH_ARM64=y
CONFIG_LP_TIMER_ARM64_ARCH=y
CONFIG_LP_SERIAL_CONSOLE=y
CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y
CONFIG_LP_USB=y
CONFIG_LP_USB_EHCI=y
CONFIG_LP_USB_XHCI=y
21 changes: 10 additions & 11 deletions payloads/libpayload/drivers/serial/8250.c
Expand Up @@ -31,37 +31,39 @@
#include <libpayload-config.h>
#include <libpayload.h>

#define IOBASE lib_sysinfo.serial->baseaddr
static struct cb_serial cb_serial;

#define IOBASE cb_serial.baseaddr
#define MEMBASE (phys_to_virt(IOBASE))

static int serial_hardware_is_present = 0;
static int serial_is_mem_mapped = 0;

static uint8_t serial_read_reg(int offset)
{
offset *= lib_sysinfo.serial->regwidth;
offset *= cb_serial.regwidth;

#if CONFIG(LP_IO_ADDRESS_SPACE)
if (!serial_is_mem_mapped)
return inb(IOBASE + offset);
else
#endif
if (lib_sysinfo.serial->regwidth == 4)
if (cb_serial.regwidth == 4)
return readl(MEMBASE + offset) & 0xff;
else
return readb(MEMBASE + offset);
}

static void serial_write_reg(uint8_t val, int offset)
{
offset *= lib_sysinfo.serial->regwidth;
offset *= cb_serial.regwidth;

#if CONFIG(LP_IO_ADDRESS_SPACE)
if (!serial_is_mem_mapped)
outb(val, IOBASE + offset);
else
#endif
if (lib_sysinfo.serial->regwidth == 4)
if (cb_serial.regwidth == 4)
writel(val & 0xff, MEMBASE + offset);
else
writeb(val, MEMBASE + offset);
Expand Down Expand Up @@ -108,11 +110,7 @@ static struct console_output_driver consout = {

void serial_init(void)
{
if (!lib_sysinfo.serial)
return;

serial_is_mem_mapped =
(lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED);
serial_is_mem_mapped = (cb_serial.type == CB_SERIAL_TYPE_MEMORY_MAPPED);

if (!serial_is_mem_mapped) {
#if CONFIG(LP_IO_ADDRESS_SPACE)
Expand All @@ -130,15 +128,16 @@ void serial_init(void)
#if CONFIG(LP_SERIAL_SET_SPEED)
serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1);
#endif
serial_hardware_is_present = 1;
}

void serial_console_init(void)
{
if (!lib_sysinfo.serial)
return;
cb_serial = *lib_sysinfo.serial;

serial_init();
serial_hardware_is_present = 1;

console_add_input_driver(&consin);
console_add_output_driver(&consout);
Expand Down
41 changes: 23 additions & 18 deletions payloads/libpayload/drivers/usb/xhci.c
Expand Up @@ -185,26 +185,27 @@ xhci_init (unsigned long physical_bar)
goto _free_xhci;
}

xhci->capreg = phys_to_virt(physical_bar);
xhci->opreg = ((void *)xhci->capreg) + xhci->capreg->caplength;
xhci->hcrreg = ((void *)xhci->capreg) + xhci->capreg->rtsoff;
xhci->dbreg = ((void *)xhci->capreg) + xhci->capreg->dboff;
memcpy(&xhci->capreg, phys_to_virt(physical_bar), sizeof(xhci->capreg));
xhci->opreg = phys_to_virt(physical_bar) + CAP_GET(CAPLEN, xhci->capreg);
xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg.rtsoff;
xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg.dboff;

xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar);
xhci_debug("caplen: 0x%"PRIx32"\n", xhci->capreg->caplength);
xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff);
xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff);
xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg));
xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg.rtsoff);
xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg.dboff);

xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n",
xhci->capreg->hciver_hi, xhci->capreg->hciver_lo);
if ((xhci->capreg->hciversion < 0x96) ||
(xhci->capreg->hciversion > 0x110)) {
CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg));
if ((CAP_GET(CAPVER, xhci->capreg) < 0x96) ||
(CAP_GET(CAPVER, xhci->capreg) > 0x110)) {
xhci_debug("Unsupported xHCI version\n");
goto _free_xhci;
}

xhci_debug("context size: %dB\n", CTXSIZE(xhci));
xhci_debug("maxslots: 0x%02lx\n", xhci->capreg->MaxSlots);
xhci_debug("maxports: 0x%02lx\n", xhci->capreg->MaxPorts);
xhci_debug("maxslots: 0x%02lx\n", CAP_GET(MAXSLOTS, xhci->capreg));
xhci_debug("maxports: 0x%02lx\n", CAP_GET(MAXPORTS, xhci->capreg));
const unsigned pagesize = xhci->opreg->pagesize << 12;
xhci_debug("pagesize: 0x%04x\n", pagesize);

Expand All @@ -213,7 +214,8 @@ xhci_init (unsigned long physical_bar)
* structures at first and can still chicken out easily if we run out
* of memory.
*/
xhci->max_slots_en = xhci->capreg->MaxSlots & CONFIG_LP_MASK_MaxSlotsEn;
xhci->max_slots_en = CAP_GET(MAXSLOTS, xhci->capreg) &
CONFIG_LP_MASK_MaxSlotsEn;
xhci->dcbaa = xhci_align(64, (xhci->max_slots_en + 1) * sizeof(u64));
xhci->dev = malloc((xhci->max_slots_en + 1) * sizeof(*xhci->dev));
if (!xhci->dcbaa || !xhci->dev) {
Expand All @@ -227,8 +229,9 @@ xhci_init (unsigned long physical_bar)
* Let dcbaa[0] point to another array of pointers, sp_ptrs.
* The pointers therein point to scratchpad buffers (pages).
*/
const size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs_Hi << 5 |
xhci->capreg->Max_Scratchpad_Bufs_Lo;
const size_t max_sp_bufs =
CAP_GET(MAX_SCRATCH_BUFS_HI, xhci->capreg) << 5 |
CAP_GET(MAX_SCRATCH_BUFS_LO, xhci->capreg);
xhci_debug("max scratchpad bufs: 0x%zx\n", max_sp_bufs);
if (max_sp_bufs) {
const size_t sp_ptrs_size = max_sp_bufs * sizeof(u64);
Expand Down Expand Up @@ -376,7 +379,8 @@ xhci_reinit (hci_t *controller)
xhci_debug("event ring @%p (0x%08x)\n",
xhci->er.ring, virt_to_phys(xhci->er.ring));
xhci_debug("ERST Max: 0x%lx -> 0x%lx entries\n",
xhci->capreg->ERST_Max, 1 << xhci->capreg->ERST_Max);
CAP_GET(ERST_MAX, xhci->capreg),
1 << CAP_GET(ERST_MAX, xhci->capreg));
memset((void*)xhci->ev_ring_table, 0x00, sizeof(erst_entry_t));
xhci->ev_ring_table[0].seg_base_lo = virt_to_phys(xhci->er.ring);
xhci->ev_ring_table[0].seg_base_hi = 0;
Expand Down Expand Up @@ -432,8 +436,9 @@ xhci_shutdown(hci_t *const controller)
#endif

if (xhci->sp_ptrs) {
size_t max_sp_bufs = xhci->capreg->Max_Scratchpad_Bufs_Hi << 5 |
xhci->capreg->Max_Scratchpad_Bufs_Lo;
const size_t max_sp_bufs =
CAP_GET(MAX_SCRATCH_BUFS_HI, xhci->capreg) << 5 |
CAP_GET(MAX_SCRATCH_BUFS_LO, xhci->capreg);
for (i = 0; i < max_sp_bufs; ++i) {
if (xhci->sp_ptrs[i])
free(phys_to_virt(xhci->sp_ptrs[i]));
Expand Down
116 changes: 57 additions & 59 deletions payloads/libpayload/drivers/usb/xhci_private.h
Expand Up @@ -274,7 +274,6 @@ typedef volatile struct epctx {
} epctx_t;

#define NUM_EPS 32
#define CTXSIZE(xhci) ((xhci)->capreg->csz ? 64 : 32)

typedef union devctx {
/* set of pointers, so we can dynamically adjust Slot/EP context size */
Expand Down Expand Up @@ -321,66 +320,65 @@ typedef struct erst_entry {
u32 rsvd;
} erst_entry_t;

#define CAP_CAPLEN_FIELD hciparams
#define CAP_CAPLEN_START 0
#define CAP_CAPLEN_LEN 8
#define CAP_CAPVER_FIELD hciparams
#define CAP_CAPVER_START 16
#define CAP_CAPVER_LEN 16
#define CAP_CAPVER_HI_FIELD hciparams
#define CAP_CAPVER_HI_START 24
#define CAP_CAPVER_HI_LEN 8
#define CAP_CAPVER_LO_FIELD hciparams
#define CAP_CAPVER_LO_START 16
#define CAP_CAPVER_LO_LEN 8
#define CAP_MAXSLOTS_FIELD hcsparams1
#define CAP_MAXSLOTS_START 0
#define CAP_MAXSLOTS_LEN 7
#define CAP_MAXINTRS_FIELD hcsparams1
#define CAP_MAXINTRS_START 7
#define CAP_MAXINTRS_LEN 11
#define CAP_MAXPORTS_FIELD hcsparams1
#define CAP_MAXPORTS_START 24
#define CAP_MAXPORTS_LEN 8
#define CAP_IST_FIELD hcsparams2
#define CAP_IST_START 0
#define CAP_IST_LEN 4
#define CAP_ERST_MAX_FIELD hcsparams2
#define CAP_ERST_MAX_START 4
#define CAP_ERST_MAX_LEN 4
#define CAP_MAX_SCRATCH_BUFS_HI_FIELD hcsparams2
#define CAP_MAX_SCRATCH_BUFS_HI_START 21
#define CAP_MAX_SCRATCH_BUFS_HI_LEN 5
#define CAP_MAX_SCRATCH_BUFS_LO_FIELD hcsparams2
#define CAP_MAX_SCRATCH_BUFS_LO_START 27
#define CAP_MAX_SCRATCH_BUFS_LO_LEN 5
#define CAP_U1_LATENCY_FIELD hcsparams3
#define CAP_U1_LATENCY_START 0
#define CAP_U1_LATENCY_LEN 8
#define CAP_U2_LATENCY_FIELD hcsparams3
#define CAP_U2_LATENCY_START 16
#define CAP_U2_LATENCY_LEN 16
#define CAP_CSZ_FIELD hccparams
#define CAP_CSZ_START 2
#define CAP_CSZ_LEN 1

#define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN)
#define CAP_GET(tok, cap) (((cap).CAP_##tok##_FIELD & CAP_MASK(tok)) \
>> CAP_##tok##_START)

#define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32)

typedef struct xhci {
/* capreg is read-only, so no need for volatile,
and thus 32bit accesses can be assumed. */
struct capreg {
u8 caplength; /* 0x00 */
u8 res1; /* 0x01 */
union { /* 0x02 */
u16 hciversion;
struct {
u8 hciver_lo;
u8 hciver_hi;
} __packed;
} __packed;
union { /* 0x04 */
u32 hcsparams1;
struct {
unsigned long MaxSlots:7;
unsigned long MaxIntrs:11;
unsigned long:6;
unsigned long MaxPorts:8;
} __packed;
} __packed;
union { /* 0x08 */
u32 hcsparams2;
struct {
unsigned long IST:4;
unsigned long ERST_Max:4;
unsigned long:13;
unsigned long Max_Scratchpad_Bufs_Hi:5;
unsigned long SPR:1;
unsigned long Max_Scratchpad_Bufs_Lo:5;
} __packed;
} __packed;
union { /* 0x0C */
u32 hcsparams3;
struct {
unsigned long u1latency:8;
unsigned long:8;
unsigned long u2latency:16;
} __packed;
} __packed;
union { /* 0x10 */
u32 hccparams;
struct {
unsigned long ac64:1;
unsigned long bnc:1;
unsigned long csz:1;
unsigned long ppc:1;
unsigned long pind:1;
unsigned long lhrc:1;
unsigned long ltc:1;
unsigned long nss:1;
unsigned long:4;
unsigned long MaxPSASize:4;
unsigned long xECP:16;
} __packed;
} __packed;
u32 dboff; /* 0x14 */
u32 rtsoff; /* 0x18 */
} __packed *capreg;
u32 hciparams;
u32 hcsparams1;
u32 hcsparams2;
u32 hcsparams3;
u32 hccparams;
u32 dboff;
u32 rtsoff;
} __packed capreg;

/* opreg is R/W is most places, so volatile access is necessary.
volatile means that the compiler seeks byte writes if possible,
Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/drivers/usb/xhci_rh.c
Expand Up @@ -160,7 +160,7 @@ xhci_rh_init (usbdev_t *dev)
dev->port = -1;

const int num_ports = /* TODO: maybe we need to read extended caps */
(XHCI_INST(dev->controller)->capreg->hcsparams1 >> 24) & 0xff;
CAP_GET(MAXPORTS, XHCI_INST(dev->controller)->capreg);
generic_hub_init(dev, num_ports, &xhci_rh_ops);

usb_debug("xHCI: root hub init done\n");
Expand Down
5 changes: 3 additions & 2 deletions payloads/libpayload/libc/malloc.c
Expand Up @@ -310,8 +310,9 @@ void *realloc(void *ptr, size_t size)
if (ret == NULL || ret == ptr)
return ret;

/* Copy the memory to the new location. */
memcpy(ret, ptr, osize > size ? size : osize);
/* Move the memory to the new location. Might be before the old location
and overlap since the free() above includes a _consolidate(). */
memmove(ret, ptr, osize > size ? size : osize);

return ret;
}
Expand Down
1 change: 1 addition & 0 deletions src/Kconfig
Expand Up @@ -226,6 +226,7 @@ config TIMESTAMPS_ON_CONSOLE

config USE_BLOBS
bool "Allow use of binary-only repository"
default y
help
This draws in the blobs repository, which contains binary files that
might be required for some chipsets or boards.
Expand Down
6 changes: 6 additions & 0 deletions src/arch/x86/Kconfig
Expand Up @@ -322,4 +322,10 @@ config MAX_PIRQ_LINKS
table specifies links greater than 4, pirq_route_irqs will not
function properly, unless this variable is correctly set.

config MAX_ACPI_TABLE_SIZE_KB
int
default 144
help
Set the maximum size of all ACPI tables in KiB.

endif
1 change: 1 addition & 0 deletions src/arch/x86/Makefile.inc
Expand Up @@ -235,6 +235,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_ps2_keybd.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c
ramstage-y += c_start.S
Expand Down
47 changes: 39 additions & 8 deletions src/arch/x86/acpi.c
Expand Up @@ -127,6 +127,18 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
return lapic->length;
}

int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic)
{
lapic->type = LOCAL_X2APIC; /* Local APIC structure */
lapic->reserved = 0;
lapic->length = sizeof(acpi_madt_lx2apic_t);
lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
lapic->processor_id = cpu;
lapic->x2apic_id = apic;

return lapic->length;
}

unsigned long acpi_create_madt_lapics(unsigned long current)
{
struct device *cpu;
Expand All @@ -146,8 +158,12 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
if (num_cpus > 1)
bubblesort(apic_ids, num_cpus, NUM_ASCENDING);
for (index = 0; index < num_cpus; index++) {
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
index, apic_ids[index]);
if (apic_ids[index] < 0xff)
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
index, apic_ids[index]);
else
current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current,
index, apic_ids[index]);
}

return current;
Expand Down Expand Up @@ -191,6 +207,21 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
return lapic_nmi->length;
}

int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
u16 flags, u8 lint)
{
lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */
lapic_nmi->length = sizeof(acpi_madt_lx2apic_nmi_t);
lapic_nmi->flags = flags;
lapic_nmi->processor_id = cpu;
lapic_nmi->lint = lint;
lapic_nmi->reserved[0] = 0;
lapic_nmi->reserved[1] = 0;
lapic_nmi->reserved[2] = 0;

return lapic_nmi->length;
}

void acpi_create_madt(acpi_madt_t *madt)
{
acpi_header_t *header = &(madt->header);
Expand Down Expand Up @@ -430,8 +461,8 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
{
struct device *dev;
for (dev = all_devices; dev; dev = dev->next)
if (dev->ops && dev->ops->acpi_fill_ssdt_generator)
dev->ops->acpi_fill_ssdt_generator(dev);
if (dev->ops && dev->ops->acpi_fill_ssdt)
dev->ops->acpi_fill_ssdt(dev);
current = (unsigned long) acpigen_get_current();
}

Expand Down Expand Up @@ -1366,8 +1397,8 @@ unsigned long write_acpi_tables(unsigned long start)

acpigen_set_current((char *) current);
for (dev = all_devices; dev; dev = dev->next)
if (dev->ops && dev->ops->acpi_inject_dsdt_generator)
dev->ops->acpi_inject_dsdt_generator(dev);
if (dev->ops && dev->ops->acpi_inject_dsdt)
dev->ops->acpi_inject_dsdt(dev);
current = (unsigned long) acpigen_get_current();
memcpy((char *)current,
(char *)dsdt_file + sizeof(acpi_header_t),
Expand Down Expand Up @@ -1554,9 +1585,9 @@ int get_acpi_table_revision(enum acpi_tables table)
{
switch (table) {
case FADT:
return ACPI_FADT_REV_ACPI_3_0;
return ACPI_FADT_REV_ACPI_6_0;
case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */
return 2;
return 3;
case MCFG:
return 1;
case TCPA:
Expand Down
302 changes: 302 additions & 0 deletions src/arch/x86/acpigen_ps2_keybd.c
@@ -0,0 +1,302 @@
/*
* This file is part of the coreboot project.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/

#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/acpigen_ps2_keybd.h>
#include <console/console.h>
#include <input-event-codes.h>

#define KEYMAP(scancode, keycode) (((uint32_t)(scancode) << 16) | (keycode & 0xFFFF))
#define SCANCODE(keymap) ((keymap >> 16) & 0xFFFF)

/* Possible keymaps for function keys in the top row */
static const uint32_t function_keymaps[] = {
KEYMAP(0x3b, KEY_F1),
KEYMAP(0x3c, KEY_F2),
KEYMAP(0x3d, KEY_F3),
KEYMAP(0x3e, KEY_F4),
KEYMAP(0x3f, KEY_F5),
KEYMAP(0x40, KEY_F6),
KEYMAP(0x41, KEY_F7),
KEYMAP(0x42, KEY_F8),
KEYMAP(0x43, KEY_F9),
KEYMAP(0x44, KEY_F10),
KEYMAP(0x57, KEY_F11),
KEYMAP(0x58, KEY_F12),
KEYMAP(0x59, KEY_F13),
KEYMAP(0x5a, KEY_F14),
KEYMAP(0x5b, KEY_F15),
};

/*
* Possible keymaps for action keys in the top row. This is a superset of
* possible keys. Individual keyboards will have a subset of these keys.
* The scancodes are true / condensed 1 byte scancodes from set-1
*/
static const uint32_t action_keymaps[] = {
[PS2_KEY_BACK] = KEYMAP(0xea, KEY_BACK), /* e06a */
[PS2_KEY_FORWARD] = KEYMAP(0xe9, KEY_FORWARD), /* e069 */
[PS2_KEY_REFRESH] = KEYMAP(0xe7, KEY_REFRESH), /* e067 */
[PS2_KEY_FULLSCREEN] = KEYMAP(0x91, KEY_FULL_SCREEN), /* e011 */
[PS2_KEY_OVERVIEW] = KEYMAP(0x92, KEY_SCALE), /* e012 */
[PS2_KEY_VOL_MUTE] = KEYMAP(0xa0, KEY_MUTE), /* e020 */
[PS2_KEY_VOL_DOWN] = KEYMAP(0xae, KEY_VOLUMEDOWN), /* e02e */
[PS2_KEY_VOL_UP] = KEYMAP(0xb0, KEY_VOLUMEUP), /* e030 */
[PS2_KEY_PLAY_PAUSE] = KEYMAP(0x9a, KEY_PLAYPAUSE), /* e01a */
[PS2_KEY_NEXT_TRACK] = KEYMAP(0x99, KEY_NEXTSONG), /* e019 */
[PS2_KEY_PREV_TRACK] = KEYMAP(0x90, KEY_PREVIOUSSONG), /* e010 */
[PS2_KEY_SNAPSHOT] = KEYMAP(0x93, KEY_SYSRQ), /* e013 */
[PS2_KEY_BRIGHTNESS_DOWN] = KEYMAP(0x94, KEY_BRIGHTNESSDOWN),/* e014 */
[PS2_KEY_BRIGHTNESS_UP] = KEYMAP(0x95, KEY_BRIGHTNESSUP), /* e015 */
[PS2_KEY_KBD_BKLIGHT_DOWN] = KEYMAP(0x97, KEY_KBDILLUMDOWN), /* e017 */
[PS2_KEY_KBD_BKLIGHT_UP] = KEYMAP(0x98, KEY_KBDILLUMUP), /* e018 */
[PS2_KEY_PRIVACY_SCRN_TOGGLE] = KEYMAP(0x96, /* e016 */
KEY_PRIVACY_SCREEN_TOGGLE),
};

/* Keymap for numeric keypad keys */
static uint32_t numeric_keypad_keymaps[] = {
/* Row-0 */
KEYMAP(0xc9, KEY_PAGEUP),
KEYMAP(0xd1, KEY_PAGEDOWN),
KEYMAP(0xc7, KEY_HOME),
KEYMAP(0xcf, KEY_END),
/* Row-1 */
KEYMAP(0xd3, KEY_DELETE),
KEYMAP(0xb5, KEY_KPSLASH),
KEYMAP(0x37, KEY_KPASTERISK),
KEYMAP(0x4a, KEY_KPMINUS),
/* Row-2 */
KEYMAP(0x47, KEY_KP7),
KEYMAP(0x48, KEY_KP8),
KEYMAP(0x49, KEY_KP9),
KEYMAP(0x4e, KEY_KPPLUS),
/* Row-3 */
KEYMAP(0x4b, KEY_KP4),
KEYMAP(0x4c, KEY_KP5),
KEYMAP(0x4d, KEY_KP6),
/* Row-4 */
KEYMAP(0x4f, KEY_KP1),
KEYMAP(0x50, KEY_KP2),
KEYMAP(0x51, KEY_KP3),
KEYMAP(0x9c, KEY_KPENTER),
/* Row-5 */
KEYMAP(0x52, KEY_KP0),
KEYMAP(0x53, KEY_KPDOT),
};

/*
* Keymap for rest of non-top-row keys. This is a superset of all the possible
* keys that any chromeos keyboards can have.
*/
static uint32_t rest_of_keymaps[] = {
/* Row-0 */
KEYMAP(0x01, KEY_ESC),
/* Row-1 */
KEYMAP(0x29, KEY_GRAVE),
KEYMAP(0x02, KEY_1),
KEYMAP(0x03, KEY_2),
KEYMAP(0x04, KEY_3),
KEYMAP(0x05, KEY_4),
KEYMAP(0x06, KEY_5),
KEYMAP(0x07, KEY_6),
KEYMAP(0x08, KEY_7),
KEYMAP(0x09, KEY_8),
KEYMAP(0x0a, KEY_9),
KEYMAP(0x0b, KEY_0),
KEYMAP(0x0c, KEY_MINUS),
KEYMAP(0x0d, KEY_EQUAL),
KEYMAP(0x7d, KEY_YEN), /* JP keyboards only */
KEYMAP(0x0e, KEY_BACKSPACE),
/* Row-2 */
KEYMAP(0x0f, KEY_TAB),
KEYMAP(0x10, KEY_Q),
KEYMAP(0x11, KEY_W),
KEYMAP(0x12, KEY_E),
KEYMAP(0x13, KEY_R),
KEYMAP(0x14, KEY_T),
KEYMAP(0x15, KEY_Y),
KEYMAP(0x16, KEY_U),
KEYMAP(0x17, KEY_I),
KEYMAP(0x18, KEY_O),
KEYMAP(0x19, KEY_P),
KEYMAP(0x1a, KEY_LEFTBRACE),
KEYMAP(0x1b, KEY_RIGHTBRACE),
KEYMAP(0x2b, KEY_BACKSLASH),
/* Row-3 */
KEYMAP(0xdb, KEY_LEFTMETA), /* Search Key */
KEYMAP(0x1e, KEY_A),
KEYMAP(0x1f, KEY_S),
KEYMAP(0x20, KEY_D),
KEYMAP(0x21, KEY_F),
KEYMAP(0x22, KEY_G),
KEYMAP(0x23, KEY_H),
KEYMAP(0x24, KEY_J),
KEYMAP(0x25, KEY_K),
KEYMAP(0x26, KEY_L),
KEYMAP(0x27, KEY_SEMICOLON),
KEYMAP(0x28, KEY_APOSTROPHE),
KEYMAP(0x1c, KEY_ENTER),
/* Row-4 */
KEYMAP(0x2a, KEY_LEFTSHIFT),
KEYMAP(0x56, KEY_102ND), /* UK keyboards only */
KEYMAP(0x2c, KEY_Z),
KEYMAP(0x2d, KEY_X),
KEYMAP(0x2e, KEY_C),
KEYMAP(0x2f, KEY_V),
KEYMAP(0x30, KEY_B),
KEYMAP(0x31, KEY_N),
KEYMAP(0x32, KEY_M),
KEYMAP(0x33, KEY_COMMA),
KEYMAP(0x34, KEY_DOT),
KEYMAP(0x35, KEY_SLASH),
KEYMAP(0x73, KEY_RO), /* JP keyboards only */
KEYMAP(0x36, KEY_RIGHTSHIFT),
/* Row-5 */
KEYMAP(0x1d, KEY_LEFTCTRL),
KEYMAP(0x38, KEY_LEFTALT),
KEYMAP(0x7b, KEY_MUHENKAN), /* JP keyboards only */
KEYMAP(0x39, KEY_SPACE),
KEYMAP(0x79, KEY_HENKAN), /* JP keyboards only */
KEYMAP(0xb8, KEY_RIGHTALT),
KEYMAP(0x9d, KEY_RIGHTCTRL),
/* Arrow keys */
KEYMAP(0xcb, KEY_LEFT),
KEYMAP(0xd0, KEY_DOWN),
KEYMAP(0xcd, KEY_RIGHT),
KEYMAP(0xc8, KEY_UP),
};

static void ssdt_generate_physmap(struct acpi_dp *dp, uint8_t num_top_row_keys,
enum ps2_action_key action_keys[])
{
struct acpi_dp *dp_array;
enum ps2_action_key key;
uint32_t keymap, i;

dp_array = acpi_dp_new_table("function-row-physmap");
if (!dp_array) {
printk(BIOS_ERR, "PS2K: couldn't write function-row-physmap\n");
return;
}

printk(BIOS_INFO, "PS2K: Physmap: [");
for (i = 0; i < num_top_row_keys; i++) {
key = action_keys[i];
if (key && key < ARRAY_SIZE(action_keymaps)) {
keymap = action_keymaps[key];
} else {
keymap = 0;
printk(BIOS_ERR,
"PS2K: invalid top-action-key-%u: %u(skipped)\n",
i, key);
}
acpi_dp_add_integer(dp_array, NULL, SCANCODE(keymap));
printk(BIOS_INFO, " %X", SCANCODE(keymap));
}

printk(BIOS_INFO, " ]\n");
acpi_dp_add_array(dp, dp_array);
}

static void ssdt_generate_keymap(struct acpi_dp *dp, uint8_t num_top_row_keys,
enum ps2_action_key action_keys[],
bool can_send_function_keys,
bool has_numeric_keypad,
bool has_scrnlock_key)
{
struct acpi_dp *dp_array;
enum ps2_action_key key;
uint32_t keymap;
unsigned int i, total = 0;

dp_array = acpi_dp_new_table("linux,keymap");
if (!dp_array) {
printk(BIOS_ERR, "PS2K: couldn't write linux,keymap\n");
return;
}

/* Write out keymap for top row action keys */
for (i = 0; i < num_top_row_keys; i++) {
key = action_keys[i];
if (!key || key >= ARRAY_SIZE(action_keymaps)) {
printk(BIOS_ERR,
"PS2K: invalid top-action-key-%u: %u\n", i, key);
continue;
}
keymap = action_keymaps[key];
acpi_dp_add_integer(dp_array, NULL, keymap);
total++;
}

/* Write out keymap for function keys, if keyboard can send them */
if (can_send_function_keys) {
for (i = 0; i < num_top_row_keys; i++) {
keymap = function_keymaps[i];
acpi_dp_add_integer(dp_array, NULL, keymap);
}

total += num_top_row_keys;
}

/* Write out keymap for numeric keypad, if the keyboard has it */
if (has_numeric_keypad) {
for (i = 0; i < ARRAY_SIZE(numeric_keypad_keymaps); i++) {
keymap = numeric_keypad_keymaps[i];
acpi_dp_add_integer(dp_array, NULL, keymap);
}

total += ARRAY_SIZE(numeric_keypad_keymaps);
}

/* Provide keymap for screenlock only if it is present */
if (has_scrnlock_key) {
acpi_dp_add_integer(dp_array, NULL, KEYMAP(0x5d, KEY_SLEEP));
total++;
}

/* Write out keymap for rest of keys */
for (i = 0; i < ARRAY_SIZE(rest_of_keymaps); i++) {
keymap = rest_of_keymaps[i];
acpi_dp_add_integer(dp_array, NULL, keymap);
}

total += ARRAY_SIZE(rest_of_keymaps);
printk(BIOS_INFO, "PS2K: Passing %u keymaps to kernel\n", total);

acpi_dp_add_array(dp, dp_array);
}

void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys,
enum ps2_action_key action_keys[],
bool can_send_function_keys,
bool has_numeric_keypad,
bool has_scrnlock_key)
{
struct acpi_dp *dsd;

if (!scope ||
num_top_row_keys < PS2_MIN_TOP_ROW_KEYS ||
num_top_row_keys > PS2_MAX_TOP_ROW_KEYS) {
printk(BIOS_ERR, "PS2K: %s: invalid args\n", __func__);
return;
}

dsd = acpi_dp_new_table("_DSD");
if (!dsd) {
printk(BIOS_ERR, "PS2K: couldn't write _DSD\n");
return;
}

acpigen_write_scope(scope);
ssdt_generate_physmap(dsd, num_top_row_keys, action_keys);
ssdt_generate_keymap(dsd, num_top_row_keys, action_keys,
can_send_function_keys, has_numeric_keypad,
has_scrnlock_key);
acpi_dp_write(dsd);
acpigen_pop_len(); /* Scope */
}
2 changes: 1 addition & 1 deletion src/arch/x86/assembly_entry.S
Expand Up @@ -28,7 +28,7 @@ _start:
shrl $2, %ecx
rep stosl

#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
#if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
|| (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))

/* Wait for a JTAG debugger to break in and set EBX non-zero */
Expand Down
4 changes: 2 additions & 2 deletions src/arch/x86/car.ld
Expand Up @@ -20,8 +20,8 @@
/* Vboot measured boot TCPA log measurements.
* Needs to be transferred until CBMEM is available
*/
#if CONFIG(VBOOT_MEASURED_BOOT)
VBOOT2_TPM_LOG(., 2K)
#if CONFIG(TPM_MEASURED_BOOT)
TPM_TCPA_LOG(., 2K)
#endif
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
Expand Down
1 change: 1 addition & 0 deletions src/arch/x86/cpu.c
Expand Up @@ -5,6 +5,7 @@
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <post.h>
#include <string.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/lapic.h>
Expand Down
73 changes: 64 additions & 9 deletions src/arch/x86/include/arch/acpi.h
Expand Up @@ -290,6 +290,33 @@ typedef struct acpi_ivrs {
struct acpi_ivrs_ivhd ivhd;
} __packed acpi_ivrs_t;

/* IVHD Type 11h IOMMU Attributes */
typedef struct ivhd11_iommu_attr {
uint32_t reserved1 : 13;
uint32_t perf_counters : 4;
uint32_t perf_counter_banks : 6;
uint32_t msi_num_ppr : 5;
uint32_t reserved2 : 4;
} __packed ivhd11_iommu_attr_t;

/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 11h */
typedef struct acpi_ivrs_ivhd_11 {
uint8_t type;
uint8_t flags;
uint16_t length;
uint16_t device_id;
uint16_t capability_offset;
uint32_t iommu_base_low;
uint32_t iommu_base_high;
uint16_t pci_segment_group;
uint16_t iommu_info;
struct ivhd11_iommu_attr iommu_attributes;
uint32_t efr_reg_image_low;
uint32_t efr_reg_image_high;
uint32_t reserved[2];
uint8_t entry[0];
} __packed acpi_ivrs_ivhd11_t;

enum dev_scope_type {
SCOPE_PCI_ENDPOINT = 1,
SCOPE_PCI_SUB = 2,
Expand Down Expand Up @@ -439,6 +466,26 @@ typedef struct acpi_madt_irqoverride {
u16 flags; /* MPS INTI flags */
} __packed acpi_madt_irqoverride_t;

/* MADT: Processor Local x2APIC Structure */
typedef struct acpi_madt_lx2apic {
u8 type; /* Type (9) */
u8 length; /* Length in bytes (16) */
u16 reserved;
u32 x2apic_id; /* Local x2APIC ID */
u32 flags; /* Same as Local APIC flags */
u32 processor_id; /* ACPI processor ID */
} __packed acpi_madt_lx2apic_t;

/* MADT: Processor Local x2APIC NMI Structure */
typedef struct acpi_madt_lx2apic_nmi {
u8 type; /* Type (10) */
u8 length; /* Length in bytes (12) */
u16 flags; /* Same as MPS INTI flags */
u32 processor_id; /* ACPI processor ID */
u8 lint; /* Local APIC LINT# */
u8 reserved[3];
} __packed acpi_madt_lx2apic_nmi_t;

#define ACPI_DBG2_PORT_SERIAL 0x8000
#define ACPI_DBG2_PORT_SERIAL_16550 0x0000
#define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001
Expand Down Expand Up @@ -519,8 +566,8 @@ typedef struct acpi_fadt {
u32 flags;
acpi_addr_t reset_reg;
u8 reset_value;
u16 ARM_boot_arch;
u8 FADT_MinorVersion;
u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */
u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */
u32 x_firmware_ctl_l;
u32 x_firmware_ctl_h;
u32 x_dsdt_l;
Expand All @@ -533,6 +580,11 @@ typedef struct acpi_fadt {
acpi_addr_t x_pm_tmr_blk;
acpi_addr_t x_gpe0_blk;
acpi_addr_t x_gpe1_blk;
/* Revision 5 */
acpi_addr_t sleep_control_reg;
acpi_addr_t sleep_status_reg;
/* Revision 6 */
u64 hypervisor_vendor_identity;
} __packed acpi_fadt_t;

/* FADT TABLE Revision values */
Expand Down Expand Up @@ -839,7 +891,9 @@ void acpi_create_madt(acpi_madt_t *madt);
unsigned long acpi_create_madt_lapics(unsigned long current);
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
u8 lint);

int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic);
int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
u16 flags, u8 lint);
int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic);
int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
u32 flags);
Expand Down Expand Up @@ -925,13 +979,14 @@ void acpi_resume(void *wake_vec);
void mainboard_suspend_resume(void);
void *acpi_find_wakeup_vector(void);

/* ACPI_Sn assignments are defined to always equal the sleep state numbers */
enum {
ACPI_S0,
ACPI_S1,
ACPI_S2,
ACPI_S3,
ACPI_S4,
ACPI_S5,
ACPI_S0 = 0,
ACPI_S1 = 1,
ACPI_S2 = 2,
ACPI_S3 = 3,
ACPI_S4 = 4,
ACPI_S5 = 5,
};

#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
Expand Down
33 changes: 33 additions & 0 deletions src/arch/x86/include/arch/acpi_ivrs.h
Expand Up @@ -107,4 +107,37 @@
#define IVHD_UID_INT 0x01
#define IVHD_UID_STRING 0x02

/* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */
typedef struct ivrs_ivhd_generic {
uint8_t type;
uint16_t dev_id;
uint8_t dte_setting;
} __packed ivrs_ivhd_generic_t;

/* IVHD (I/O Virtualization Hardware Definition Block) 8-byte entries */
typedef struct ivrs_ivhd_alias {
uint8_t type;
uint16_t dev_id;
uint8_t dte_setting;
uint8_t reserved1;
uint16_t source_dev_id;
uint8_t reserved2;
} __packed ivrs_ivhd_alias_t;

typedef struct ivrs_ivhd_extended {
uint8_t type;
uint16_t dev_id;
uint8_t dte_setting;
uint32_t extended_dte_setting;
} __packed ivrs_ivhd_extended_t;

typedef struct ivrs_ivhd_special {
uint8_t type;
uint16_t reserved;
uint8_t dte_setting;
uint8_t handle;
uint16_t source_dev_id;
uint8_t variety;
} __packed ivrs_ivhd_special_t;

#endif
41 changes: 41 additions & 0 deletions src/arch/x86/include/arch/acpigen_ps2_keybd.h
@@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/

#ifndef __ACPIGEN_PS2_KEYBD_H__
#define __ACPIGEN_PS2_KEYBD_H__

#include <types.h>

enum ps2_action_key {
PS2_KEY_ABSENT = 0,
PS2_KEY_BACK,
PS2_KEY_FORWARD,
PS2_KEY_REFRESH,
PS2_KEY_FULLSCREEN,
PS2_KEY_OVERVIEW,
PS2_KEY_BRIGHTNESS_DOWN,
PS2_KEY_BRIGHTNESS_UP,
PS2_KEY_VOL_MUTE,
PS2_KEY_VOL_DOWN,
PS2_KEY_VOL_UP,
PS2_KEY_SNAPSHOT,
PS2_KEY_PRIVACY_SCRN_TOGGLE,
PS2_KEY_KBD_BKLIGHT_DOWN,
PS2_KEY_KBD_BKLIGHT_UP,
PS2_KEY_PLAY_PAUSE,
PS2_KEY_NEXT_TRACK,
PS2_KEY_PREV_TRACK,
};

#define PS2_MIN_TOP_ROW_KEYS 10
#define PS2_MAX_TOP_ROW_KEYS 15

void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys,
enum ps2_action_key action_keys[],
bool can_send_function_keys,
bool has_numeric_keypad, bool has_scrnlock_key);

#endif /* __ACPIGEN_PS2_KEYBD_H__ */
2 changes: 1 addition & 1 deletion src/arch/x86/memlayout.ld
Expand Up @@ -32,7 +32,7 @@ SECTIONS
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)

#include EARLY_MEMLAYOUT
#elif ENV_VERSTAGE
#elif ENV_SEPARATE_VERSTAGE
/* The 1M size is not allocated. It's just for basic size checking.
* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
Expand Down
1 change: 1 addition & 0 deletions src/arch/x86/post.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <post.h>
#include <stdint.h>
#include <console/console.h>
#include <arch/io.h>
Expand Down
7 changes: 3 additions & 4 deletions src/arch/x86/tables.c
Expand Up @@ -78,8 +78,7 @@ static unsigned long write_mptable(unsigned long rom_table_end)
static unsigned long write_acpi_table(unsigned long rom_table_end)
{
unsigned long high_table_pointer;

#define MAX_ACPI_SIZE (144 * 1024)
const size_t max_acpi_size = CONFIG_MAX_ACPI_TABLE_SIZE_KB * KiB;

post_code(0x9c);

Expand All @@ -96,15 +95,15 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
* how far we get.
*/
high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI,
MAX_ACPI_SIZE);
max_acpi_size);
if (high_table_pointer) {
unsigned long acpi_start = high_table_pointer;
unsigned long new_high_table_pointer;

rom_table_end = ALIGN_UP(rom_table_end, 16);
new_high_table_pointer = write_acpi_tables(high_table_pointer);
if (new_high_table_pointer > (high_table_pointer
+ MAX_ACPI_SIZE))
+ max_acpi_size))
printk(BIOS_ERR, "ERROR: Increase ACPI size\n");
printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n",
new_high_table_pointer - high_table_pointer);
Expand Down
2 changes: 2 additions & 0 deletions src/commonlib/bsd/include/commonlib/bsd/helpers.h
Expand Up @@ -52,6 +52,8 @@
(_power_local_x & (_power_local_x - 1)) == 0; \
})

#define POWER_OF_2(x) (1ULL << (x))

#define DIV_ROUND_UP(x, y) ({ \
__typeof__(x) _div_local_x = (x); \
__typeof__(y) _div_local_y = (y); \
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/cbfs.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <commonlib/cbfs.h>
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/fsp_relocate.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <commonlib/endian.h>
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/cbfs.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _COMMONLIB_CBFS_H_
#define _COMMONLIB_CBFS_H_
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/cbmem_id.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _CBMEM_ID_H_
#define _CBMEM_ID_H_
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/coreboot_tables.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef COMMONLIB_COREBOOT_TABLES_H
#define COMMONLIB_COREBOOT_TABLES_H
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/endian.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _COMMONLIB_ENDIAN_H_
#define _COMMONLIB_ENDIAN_H_
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/fsp.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _COMMONLIB_FSP_H_
#define _COMMONLIB_FSP_H_
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/helpers.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef COMMONLIB_HELPERS_H
#define COMMONLIB_HELPERS_H
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/iobuf.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef COMMONLIB_IOBUF_H
#define COMMONLIB_IOBUF_H
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/mem_pool.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _MEM_POOL_H_
#define _MEM_POOL_H_
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/region.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _REGION_H_
#define _REGION_H_
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/rmodule-defs.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#ifndef RMODULE_DEFS_H
#define RMODULE_DEFS_H

Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/sort.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#ifndef _COMMONLIB_SORT_H_
#define _COMMONLIB_SORT_H_

Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/tcpa_log_serialized.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef __TCPA_LOG_SERIALIZED_H__
#define __TCPA_LOG_SERIALIZED_H__
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/include/commonlib/timestamp_serialized.h
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef __TIMESTAMP_SERIALIZED_H__
#define __TIMESTAMP_SERIALIZED_H__
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/iobuf.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <commonlib/endian.h>
#include <commonlib/iobuf.h>
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/mem_pool.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <commonlib/helpers.h>
#include <commonlib/mem_pool.h>
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/region.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <commonlib/helpers.h>
#include <commonlib/region.h>
Expand Down
14 changes: 2 additions & 12 deletions src/commonlib/sort.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <commonlib/helpers.h>
#include <commonlib/sort.h>
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/sdhci.c
Expand Up @@ -27,7 +27,7 @@
#include <commonlib/stdlib.h>

#define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
|| (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \
|| (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \
|| (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \
|| ENV_POSTCAR || ENV_RAMSTAGE)

Expand Down
8 changes: 0 additions & 8 deletions src/console/Kconfig
Expand Up @@ -392,14 +392,6 @@ config CMOS_POST_OFFSET
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
defined in the mainboard option table.

config CMOS_POST_EXTRA
bool "Store extra logging info into CMOS"
depends on CMOS_POST
default n
help
This will enable extra logging of work that happens between post
codes into CMOS for debug. This uses an additional 8 bytes of CMOS.

config CONSOLE_POST
bool "Show POST codes on the debug console"
depends on !NO_POST
Expand Down
14 changes: 2 additions & 12 deletions src/console/console.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/cbmem_console.h>
#include <console/ne2k.h>
Expand Down
15 changes: 2 additions & 13 deletions src/console/die.c
@@ -1,16 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <halt.h>
Expand Down
15 changes: 2 additions & 13 deletions src/console/init.c
@@ -1,16 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <commonlib/helpers.h>
#include <console/console.h>
Expand Down
15 changes: 2 additions & 13 deletions src/console/post.c
@@ -1,16 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <stdint.h>
#include <console/console.h>
Expand Down
14 changes: 3 additions & 11 deletions src/console/printk.c
@@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* blatantly copied from linux/kernel/printk.c
*/

Expand Down
15 changes: 2 additions & 13 deletions src/console/vsprintf.c
@@ -1,16 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/vtxprintf.h>
#include <string.h>
Expand Down
14 changes: 3 additions & 11 deletions src/console/vtxprintf.c
@@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* vtxprintf.c, originally from linux/lib/vsprintf.c
*/

Expand Down
35 changes: 15 additions & 20 deletions src/cpu/amd/agesa/family14/acpi/cpu.asl
@@ -1,29 +1,24 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */

Device (C000) {
Name (_HID, "ACPI0007")
Name (_UID, 0)
Scope (\_PR) { /* define processor scope */
Processor(
C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (C001) {
Name (_HID, "ACPI0007")
Name (_UID, 1)
Processor(
C001, /* name space name */
1, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _SB scope */
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family14/chip_name.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <device/device.h>

Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family14/fixme.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family14/model_14_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <cpu/x86/msr.h>
Expand Down
121 changes: 64 additions & 57 deletions src/cpu/amd/agesa/family15tn/acpi/cpu.asl
@@ -1,59 +1,66 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */
/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */
Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family15tn/chip_name.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <device/device.h>

Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family15tn/fixme.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <cpu/x86/msr.h>
Expand Down
94 changes: 51 additions & 43 deletions src/cpu/amd/agesa/family16kb/acpi/cpu.asl
@@ -1,58 +1,66 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* Processor Object
*
*/
Scope (\_SB) {/* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _SB scope */
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family16kb/chip_name.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <device/device.h>

Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family16kb/fixme.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <cpu/x86/msr.h>
Expand Down
14 changes: 2 additions & 12 deletions src/cpu/amd/mtrr/amd_mtrr.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cbmem.h>
#include <console/console.h>
Expand Down
149 changes: 92 additions & 57 deletions src/cpu/amd/pi/00630F01/acpi/cpu.asl
@@ -1,59 +1,94 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */
/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique core number for this processor within a socket */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */
Processor(
P001, /* name space name */
1, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P008, /* name space name */
8, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P009, /* name space name */
9, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P010, /* name space name */
10, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P011, /* name space name */
11, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00630F01/chip_name.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <device/device.h>

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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00630F01/fixme.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00630F01/model_15_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <cpu/x86/msr.h>
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95 changes: 51 additions & 44 deletions src/cpu/amd/pi/00660F01/acpi/cpu.asl
@@ -1,59 +1,66 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _SB scope */
14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00660F01/chip_name.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <device/device.h>

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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00660F01/fixme.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00660F01/model_15_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <cpu/x86/msr.h>
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121 changes: 64 additions & 57 deletions src/cpu/amd/pi/00730F01/acpi/cpu.asl
@@ -1,59 +1,66 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */
/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */
Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00730F01/chip_name.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <device/device.h>

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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00730F01/fixme.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00730F01/microcode_fam16h.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <stdint.h>
#include <console/console.h>
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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00730F01/model_16_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <console/console.h>
#include <cpu/amd/microcode.h>
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14 changes: 2 additions & 12 deletions src/cpu/amd/pi/00730F01/update_microcode.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <stdint.h>
#include <cpu/amd/microcode.h>
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14 changes: 2 additions & 12 deletions src/cpu/amd/smm/smm_init.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
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14 changes: 2 additions & 12 deletions src/cpu/intel/car/bootblock.c
@@ -1,15 +1,5 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <bootblock_common.h>
#include <arch/bootblock.h>
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