diff --git a/Makefile.inc b/Makefile.inc
@@ -486,7 +486,7 @@ ifeq ($(CONFIG_DEBUG_ADA_CODE),y)
 ADAFLAGS_common += -gnata
 endif
 
-additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \
+additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \
 		   $(objutil)/options $(objutil)/amdfwtool \
 		   $(objutil)/cbootimage
 
@@ -552,16 +552,6 @@ ifeq ($(_WINCHECK),Cygwin)
 	STACK=-Wl,--stack,16384000
 endif
 
-# this allows ccache to prepend itself
-# (ccache handling happens first)
-ROMCC_BIN= $(objutil)/romcc/romcc
-ROMCC?=$(ROMCC_BIN)
-$(ROMCC_BIN): $(top)/util/romcc/romcc.c
-	@printf "    HOSTCC     $(subst $(obj)/,,$(@)) (this may take a while)\n"
-	@# Note: Adding -O2 here might cause problems. For details see:
-	@# https://www.coreboot.org/pipermail/coreboot/2010-February/055825.html
-	$(HOSTCC) -g $(STACK) -Wall -o $@ $<
-
 BINCFG:=$(objutil)/bincfg/bincfg
 
 IFDTOOL:=$(objutil)/ifdtool/ifdtool
@@ -651,7 +641,7 @@ install-git-commit-clangfmt:
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL)
+tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL)
 
 ###########################################################################
 # Common recipes for all stages

diff --git a/configs/config.google_kevin_secdata_mock b/configs/config.google_kevin_secdata_mock
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_KEVIN=y
+CONFIG_CHROMEOS=y
+CONFIG_VBOOT_MOCK_SECDATA=y
+CONFIG_PAYLOAD_NONE=y
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros
@@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_BOARD_GOOGLE_MEEP=y
 
 CONFIG_PAYLOAD_NONE=y
-CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SMM=y
 CONFIG_USE_BLOBS=y

diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros
@@ -3,7 +3,6 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_BOARD_GOOGLE_REEF=y
 CONFIG_CHROMEOS=y
 CONFIG_ADD_FSP_BINARIES=y
-CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
 CONFIG_ELOG_GSMI=y
 CONFIG_ELOG_BOOT_COUNT=y
 CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.1"
+CONFIG_LOCALVERSION="v4.11.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_NO_GFX_INIT=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.1"
+CONFIG_LOCALVERSION="v4.11.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.1"
+CONFIG_LOCALVERSION="v4.11.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.1"
+CONFIG_LOCALVERSION="v4.11.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.1"
+CONFIG_LOCALVERSION="v4.11.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y

diff --git a/payloads/Kconfig b/payloads/Kconfig
@@ -40,21 +40,12 @@ config PAYLOAD_FIT
 	  You will be able to specify the location and file name of the
 	  payload image later.
 
-config PAYLOAD_BAYOU
-	bool "Bayou"
-	depends on ARCH_X86
-	help
-	  Select this option if you want to set bayou as your primary
-	  payload.
-
 source "payloads/external/*/Kconfig.name"
 
 endchoice
 
 source "payloads/external/*/Kconfig"
 
-source "payloads/bayou/Kconfig"
-
 config PAYLOAD_FILE
 	string "Payload path and filename"
 	depends on PAYLOAD_ELF || PAYLOAD_FIT

diff --git a/payloads/bayou/Doxyfile b/payloads/bayou/Doxyfile
diff --git a/payloads/bayou/Makefile b/payloads/bayou/Makefile
diff --git a/payloads/bayou/bayou.h b/payloads/bayou/bayou.h
diff --git a/payloads/bayou/bayou.ldscript b/payloads/bayou/bayou.ldscript
diff --git a/payloads/bayou/bayou.xml.example b/payloads/bayou/bayou.xml.example
diff --git a/payloads/bayou/config.c b/payloads/bayou/config.c
diff --git a/payloads/bayou/lzma.c b/payloads/bayou/lzma.c
diff --git a/payloads/bayou/lzmadecode.c b/payloads/bayou/lzmadecode.c
diff --git a/payloads/bayou/lzmadecode.h b/payloads/bayou/lzmadecode.h
diff --git a/payloads/bayou/main.c b/payloads/bayou/main.c
diff --git a/payloads/bayou/menu.c b/payloads/bayou/menu.c
diff --git a/payloads/bayou/nrv2b.c b/payloads/bayou/nrv2b.c
diff --git a/payloads/bayou/payload.c b/payloads/bayou/payload.c
diff --git a/payloads/bayou/self.c b/payloads/bayou/self.c
diff --git a/payloads/bayou/self.h b/payloads/bayou/self.h
diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.12.1"
+	bool "1.13.0"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER

diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=a5cab58e9a3fb6e168aba919c5669bea406573b4
+TAG-$(CONFIG_SEABIOS_STABLE)=f21b5a4aeb020f2a5e2c6503f906a9349dd2f069
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://github.com/pcengines/seabios.git

diff --git a/payloads/external/sortbootorder/Makefile b/payloads/external/sortbootorder/Makefile
@@ -1,4 +1,4 @@
-version=4.6.15
+version=4.6.16
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -343,8 +343,8 @@ config PC_KEYBOARD
 	default y if ARCH_X86 # uses IO
 	default n
 
-config PC_KEYBOARD_IGNORE_INIT_FAILURE
-	bool "Ignore keyboard failures during init and always add input device"
+config PC_KEYBOARD_AT_TRANSLATED
+	bool "AT Translation keyboard device"
 	default n
 
 config PC_KEYBOARD_LAYOUT_US

diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
@@ -163,7 +163,6 @@ CCACHE:=CCACHE_COMPILERCHECK=content CCACHE_BASEDIR=$(top) $(CCACHE)
 CC := $(CCACHE) $(CC)
 HOSTCC := $(CCACHE) $(HOSTCC)
 HOSTCXX := $(CCACHE) $(HOSTCXX)
-ROMCC := $(CCACHE) $(ROMCC)
 endif
 
 strip_quotes = $(subst ",,$(subst \",,$(1)))

diff --git a/payloads/libpayload/arch/arm/virtual.c b/payloads/libpayload/arch/arm/virtual.c
@@ -92,7 +92,7 @@ static void lpae_map_init(void)
 	/* get work block address */
 	work_block = ALIGN_UP((uintptr_t)_end, 2*MiB);
 	assert(work_block);
-	printf("Work block for LPAE mapping is @ 0x%p\n", (void *)work_block);
+	printf("Work block for LPAE mapping is @ %p\n", (void *)work_block);
 
 	/* get the address of the 1st pmd from pgd[0] */
 	pgd = (pgd_t *)((uintptr_t)read_ttbr0() & PGD_MASK);

diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c
@@ -273,7 +273,7 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges)
 	max_tables = (TTB_DEFAULT_SIZE >> GRANULE_SIZE_SHIFT);
 	free_idx = 1;
 
-	printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n",
+	printf("Libpayload ARM64: TTB_BUFFER: %p Max Tables: %d\n",
 	       (void*)xlat_addr, max_tables);
 
 	/*

diff --git a/payloads/libpayload/drivers/cbmem_console.c b/payloads/libpayload/drivers/cbmem_console.c
@@ -75,3 +75,49 @@ void cbmem_console_write(const void *buffer, size_t count)
 
 	do_write(buffer, count);
 }
+
+char *cbmem_console_snapshot(void)
+{
+	const struct cbmem_console *console_p = cbmem_console_p;
+	char *console_c;
+	uint32_t size, cursor, overflow;
+
+	if (!console_p) {
+		printf("ERROR: No cbmem console found in coreboot table\n");
+		return NULL;
+	}
+
+	cursor = console_p->cursor & CURSOR_MASK;
+	overflow = console_p->cursor & OVERFLOW;
+	if (!overflow && cursor < console_p->size)
+		size = cursor;
+	else
+		size = console_p->size;
+
+	console_c = malloc(size + 1);
+	if (!console_c) {
+		printf("ERROR: Not enough memory for console (size = %u)\n",
+		       size);
+		return NULL;
+	}
+	console_c[size] = '\0';
+
+	if (overflow) {
+		if (cursor >= size) {
+			printf("ERROR: CBMEM console struct is corrupted\n");
+			return NULL;
+		}
+		memcpy(console_c, console_p->body + cursor, size - cursor);
+		memcpy(console_c + size - cursor, console_p->body, cursor);
+	} else {
+		memcpy(console_c, console_p->body, size);
+	}
+
+	/* Slight memory corruption may occur between reboots and give us a few
+	   unprintable characters like '\0'. Replace them with '?' on output. */
+	for (cursor = 0; cursor < size; cursor++)
+		if (!isprint(console_c[cursor]) && !isspace(console_c[cursor]))
+			console_c[cursor] = '?';
+
+	return console_c;
+}
diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c
@@ -197,23 +197,29 @@ u8 i8042_probe(void)
 
 	/* If 0x64 returns 0xff, then we have no keyboard
 	 * controller */
-	if (read_status() == 0xFF)
+	if (read_status() == 0xFF) {
+		printf("ERROR: No keyboard controller found!\n");
 		return 0;
+	}
 
-	if (!i8042_wait_cmd_rdy())
+	if (!i8042_wait_cmd_rdy()) {
+		printf("ERROR: i8042_wait_cmd_rdy failed!\n");
 		return 0;
+	}
 
 	kbc_init = 1;
 
 	/* Disable first device */
 	if (i8042_cmd(I8042_CMD_DIS_KB) != 0) {
 		kbc_init = 0;
+		printf("ERROR: i8042_cmd I8042_CMD_DIS_KB failed!\n");
 		return 0;
 	}
 
 	/* Disable second device */
 	if (i8042_cmd(I8042_CMD_DIS_AUX) != 0) {
 		kbc_init = 0;
+		printf("ERROR: i8042_cmd I8042_CMD_DIS_AUX failed!\n");
 		return 0;
 	}
 
@@ -225,6 +231,7 @@ u8 i8042_probe(void)
 	if (i8042_cmd_with_response(I8042_CMD_SELF_TEST)
 	    != I8042_SELF_TEST_RSP) {
 		kbc_init = 0;
+		printf("ERROR: i8042_cmd I8042_CMD_SELF_TEST failed!\n");
 		return 0;
 	}
 

diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h
@@ -33,6 +33,7 @@
 /* Port 0x64 commands */
 #define I8042_CMD_RD_CMD_BYTE		0x20
 #define I8042_CMD_WR_CMD_BYTE		0x60
+#define   I8042_CMD_BYTE_XLATE		(1 << 6)
 #define I8042_CMD_DIS_AUX		0xa7
 #define I8042_CMD_EN_AUX		0xa8
 #define I8042_CMD_AUX_TEST		0xa9

diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -312,50 +312,82 @@ static struct console_input_driver cons = {
 	.input_type = CONSOLE_INPUT_TYPE_EC,
 };
 
-void keyboard_init(void)
+/* Enable keyboard translated */
+static int enable_translated(void)
 {
-	unsigned int ret;
-	map = &keyboard_layouts[0];
-
-	/* Initialized keyboard controller. */
-	if (!i8042_probe() || !i8042_has_ps2())
-		return;
-
-	/* Empty keyboard buffer */
-	while (keyboard_havechar())
-		keyboard_getchar();
-
-	/* Enable first PS/2 port */
-	i8042_cmd(I8042_CMD_EN_KB);
+	if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) {
+		int cmd = i8042_read_data_ps2();
+		cmd |= I8042_CMD_BYTE_XLATE;
+		if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) {
+			i8042_write_data(cmd);
+		} else {
+			printf("ERROR: i8042_cmd WR_CMD failed!\n");
+			return 0;
+		}
+	} else {
+		printf("ERROR: i8042_cmd RD_CMD failed!\n");
+		return 0;
+	}
+	return 1;
+}
 
-	/* Set scancode set 1 */
+/* Set scancode set 1 */
+static int set_scancode_set(void)
+{
+	unsigned int ret;
 	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
+	if (!ret) {
 		printf("ERROR: Keyboard set scancode failed!\n");
-		return;
+		return ret;
 	}
 
 	ret = keyboard_cmd(I8042_SCANCODE_SET_1);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
+	if (!ret) {
 		printf("ERROR: Keyboard scancode set#1 failed!\n");
-		return;
+		return ret;
 	}
 
 	/*
 	 * Set default parameters.
 	 * Fix for broken QEMU ps/2 make scancodes.
 	 */
-	ret = keyboard_cmd(0xf6);
+	ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT);
 	if (!ret) {
 		printf("ERROR: Keyboard set default params failed!\n");
-		return;
+		return ret;
 	}
 
 	/* Enable scanning */
 	ret = keyboard_cmd(I8042_KBCMD_EN);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
+	if (!ret) {
 		printf("ERROR: Keyboard enable scanning failed!\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void keyboard_init(void)
+{
+	map = &keyboard_layouts[0];
+
+	/* Initialized keyboard controller. */
+	if (!i8042_probe() || !i8042_has_ps2())
 		return;
+
+	/* Empty keyboard buffer */
+	while (keyboard_havechar())
+		keyboard_getchar();
+
+	/* Enable first PS/2 port */
+	i8042_cmd(I8042_CMD_EN_KB);
+
+	if (CONFIG(LP_PC_KEYBOARD_AT_TRANSLATED)) {
+		if (!enable_translated())
+			return;
+	} else {
+		if (!set_scancode_set())
+			return;
 	}
 
 	console_add_input_driver(&cons);

diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
@@ -313,6 +313,13 @@ void video_printf(int foreground, int background, enum video_printf_align align,
  */
 void cbmem_console_init(void);
 void cbmem_console_write(const void *buffer, size_t count);
+/**
+ * Take a snapshot of the CBMEM memory console. This function will allocate a
+ * range of memory. Callers must free the returned buffer by themselves.
+ *
+ * @return The allocated buffer on success, NULL on failure.
+ */
+char *cbmem_console_snapshot(void);
 /** @} */
 
 /* drivers/option.c */

diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
@@ -106,7 +106,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 	if (stage == NULL)
 		return (void *) -1;
 
-	LOG("loading stage %s @ 0x%p (%d bytes), entry @ 0x%llx\n",
+	LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n",
 			name,
 			(void*)(uintptr_t) stage->load, stage->memlen,
 			stage->entry);
@@ -215,7 +215,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer,
 			       const void *address) {
 	// TODO Add simple buffer management so we can free more than last
 	// allocated one.
-	DEBUG("simple_buffer_unmap(address=0x%p): "
+	DEBUG("simple_buffer_unmap(address=%p): "
 	      "allocated=%zu, size=%zu, last_allocate=%zu\n",
 	    address, buffer->allocated, buffer->size,
 	    buffer->last_allocate);

diff --git a/src/Kconfig b/src/Kconfig
@@ -263,14 +263,9 @@ config UBSAN
 	  say N because it adds a small performance penalty and may abort
 	  on code that happens to work in spite of the UB.
 
-config NO_RELOCATABLE_RAMSTAGE
-	bool
-	default n if ARCH_X86
-	default y
-
 config RELOCATABLE_RAMSTAGE
 	bool
-	default !NO_RELOCATABLE_RAMSTAGE
+	default y if ARCH_X86
 	select RELOCATABLE_MODULES
 	help
 	 The reloctable ramstage support allows for the ramstage to be built
@@ -279,18 +274,28 @@ config RELOCATABLE_RAMSTAGE
 	 wake. When selecting this option the romstage is responsible for
 	 determing a stack location to use for loading the ramstage.
 
+choice
+	prompt "Stage Cache for ACPI S3 resume"
+	default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
+	default TSEG_STAGE_CACHE if SMM_TSEG
+
+config NO_STAGE_CACHE
+	bool "Disabled"
+	help
+	  Do not save any component in stage cache for resume path. On resume,
+	  all components would be read back from CBFS again.
+
 config TSEG_STAGE_CACHE
-	bool
-	default y
-	depends on !NO_STAGE_CACHE && SMM_TSEG
+	bool "TSEG"
+	depends on SMM_TSEG
 	help
 	  The option enables stage cache support for platform. Platform
 	  can stash copies of postcar, ramstage and raw runtime data
 	  inside SMM TSEG, to be restored on S3 resume path.
 
 config CBMEM_STAGE_CACHE
-	bool "Cache stages in CBMEM"
-	depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE
+	bool "CBMEM"
+	depends on !SMM_TSEG
 	help
 	  The option enables stage cache support for platform. Platform
 	  can stash copies of postcar, ramstage and raw runtime data
@@ -302,6 +307,8 @@ config CBMEM_STAGE_CACHE
 
 	  If unsure, select 'N'
 
+endchoice
+
 config UPDATE_IMAGE
 	bool "Update existing coreboot.rom image"
 	help
@@ -1158,13 +1165,6 @@ config RELOCATABLE_MODULES
 	  building relocatable modules in the RAM stage. Those modules can be
 	  loaded anywhere and all the relocations are handled automatically.
 
-config NO_STAGE_CACHE
-	bool
-	default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
-	help
-	  Do not save any component in stage cache for resume path. On resume,
-	  all components would be read back from CBFS again.
-
 config GENERIC_GPIO_LIB
 	bool
 	help
@@ -1177,9 +1177,6 @@ config BOOTBLOCK_CUSTOM
 	# src/lib/bootblock.c#main() C entry point.
 	bool
 
-config ROMCC_BOOTBLOCK
-	bool
-
 ###############################################################################
 # Set default values for symbols created before mainboards.  This allows the
 # option to be displayed in the general menu, but the default to be loaded in

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
@@ -30,7 +30,6 @@
 
 #include <assert.h>
 #include <commonlib/helpers.h>
-#include <stdlib.h>
 #include <stdint.h>
 #include <symbols.h>
 

diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c
@@ -27,7 +27,6 @@
  * SUCH DAMAGE.
  *
  */
-#include <stdlib.h>
 #include <arch/cpu.h>
 #include <commonlib/helpers.h>
 

diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c
@@ -14,7 +14,6 @@
  * Utility functions needed for (some) EABI conformant tool chains.
  */
 
-#include <stdint.h>
 #include <stddef.h>
 #include <string.h>
 #include <console/console.h>

diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
@@ -28,7 +28,6 @@
  */
 
 #include <assert.h>
-#include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
 #include <symbols.h>

diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c
@@ -14,7 +14,6 @@
 
 #include <console/console.h>
 #include <bootmem.h>
-#include <stdlib.h>
 #include <program_loading.h>
 #include <string.h>
 #include <commonlib/compression.h>

diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c
@@ -16,7 +16,6 @@
 
 #include <console/console.h>
 #include <bootmem.h>
-#include <stdlib.h>
 #include <program_loading.h>
 #include <commonlib/compression.h>
 #include <commonlib/cbfs_serialized.h>

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
@@ -13,57 +13,54 @@
 
 config ARCH_X86
 	bool
-	default n
 	select PCI
 	select RELOCATABLE_MODULES
 
 # stage selectors for x86
 
 config ARCH_BOOTBLOCK_X86_32
 	bool
-	default n
 	select ARCH_X86
-	select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK
 
 config ARCH_VERSTAGE_X86_32
 	bool
-	default n
+	select ARCH_X86
 
 config ARCH_ROMSTAGE_X86_32
 	bool
-	default n
+	select ARCH_X86
 
 config ARCH_POSTCAR_X86_32
 	bool
 	default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE
 
 config ARCH_RAMSTAGE_X86_32
 	bool
-	default n
+	select ARCH_X86
 
 # stage selectors for x64
 
 config ARCH_BOOTBLOCK_X86_64
 	bool
-	default n
 	select ARCH_X86
-	select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK
 
 config ARCH_VERSTAGE_X86_64
 	bool
-	default n
+	select ARCH_X86
 
 config ARCH_ROMSTAGE_X86_64
 	bool
-	default n
+	select ARCH_X86
 
 config ARCH_POSTCAR_X86_64
 	bool
 	default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE
 
 config ARCH_RAMSTAGE_X86_64
 	bool
-	default n
+	select ARCH_X86
+
+if ARCH_X86
 
 config ARCH_X86_64_PGTBL_LOC
 	hex "x86_64 page table location in CBFS"
@@ -169,12 +166,6 @@ config BOOTBLOCK_DEBUG_SPINLOOP
 	  Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
 	  for a JTAG debugger to break into the execution sequence.
 
-config BOOTBLOCK_MAINBOARD_INIT
-	string
-
-config BOOTBLOCK_NORTHBRIDGE_INIT
-	string
-
 config BOOTBLOCK_RESETS
 	string
 
@@ -187,9 +178,6 @@ config CMOS_DEFAULT_FILE
 	default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
 	depends on HAVE_CMOS_DEFAULT
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-
 config IOAPIC_INTERRUPTS_ON_FSB
 	bool
 	default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
@@ -244,11 +232,10 @@ config ROMSTAGE_DEBUG_SPINLOOP
 	  Add a spin (JMP .) in assembly_entry.S during early romstage to wait
 	  for a JTAG debugger to break into the execution sequence.
 
-# Selecting a cbfs prefix from the bootblock is only implemented with romcc
 choice
 	prompt "Bootblock behaviour"
 	default BOOTBLOCK_SIMPLE
-	depends on ROMCC_BOOTBLOCK
+	depends on !VBOOT
 
 config BOOTBLOCK_SIMPLE
 	bool "Always load fallback"
@@ -259,11 +246,6 @@ config BOOTBLOCK_NORMAL
 
 endchoice
 
-config BOOTBLOCK_SOURCE
-	string
-	default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
-	default "bootblock_normal.c" if BOOTBLOCK_NORMAL
-
 config SKIP_MAX_REBOOT_CNT_CLEAR
 	bool "Do not clear reboot count after successful boot"
 	depends on BOOTBLOCK_NORMAL
@@ -350,3 +332,5 @@ config MAX_PIRQ_LINKS
 	  also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
 	  table specifies links greater than 4, pirq_route_irqs will not
 	  function properly, unless this variable is correctly set.
+
+endif
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -112,12 +112,10 @@ bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
 bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-
+bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c
 bootblock-y += id.S
 $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
 
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
-
 bootblock-y += bootblock_crt0.S
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
@@ -126,60 +124,7 @@ else
 $(eval $(call early_x86_stage,bootblock,elf64-x86-64))
 endif
 
-bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
-
-else # ROMCC_BOOTBLOCK
-
-# x86-specific linker flags
-ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
-LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386
-else
-LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64
-endif
-
-# Add the assembly file that pulls in the rest of the dependencies in
-# the right order. Make sure the auto generated bootblock.inc is a proper
-# dependency. Make the same true for the linker sript.
-bootblock-y += bootblock_romcc.S
-bootblock-y += walkcbfs.S
-$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc
-
-bootblock-y += bootblock.ld
-$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld
-
-bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__
-ifeq ($(CONFIG_SSE),y)
-bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__
-endif
-
-# This is a hack in case there are no per chipset linker files.
-$(objgenerated)/empty: build-dirs
-	touch $@
-
-$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
-	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
-	cat $^ >> $@.tmp
-	mv $@.tmp $@
-
--include $(objgenerated)/bootblock.inc.d
-$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
-# The open quote in the subst messes with syntax highlighting. Fix it - ")
-	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
-		$< > $(objgenerated)/bootblock.inc.d
-	$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \
-		$< -o $(objgenerated)/bootblock_romcc.c
-	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
-
-# bootblock.ld is part of $(bootblock-objs)
-$(objcbfs)/bootblock.debug: $$(bootblock-objs)
-	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
-		$(filter-out %.ld,$(bootblock-objs)) \
-		-T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld)
-
-endif # ROMCC_BOOTBLOCK
-
+bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += walkcbfs.S
 
 endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
@@ -223,17 +168,14 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 # gdt_init.S is included by entry32.inc when romstage is the first C
 # environment.
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
 romstage-y += gdt_init.S
-endif
 romstage-y += cbmem.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
 romstage-y += memmove.c
 romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 romstage-y += postcar_loader.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += walkcbfs.S
 
 romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
 romstage-libs ?=
@@ -347,7 +289,9 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/reset.c),)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c
 endif
 ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
+ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c
+endif
 $(eval $(call asl_template,dsdt))
 ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c

diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
@@ -403,6 +403,37 @@ void acpigen_write_opregion(struct opregion *opreg)
 	acpigen_write_integer(opreg->regionlen);
 }
 
+/*
+ * Generate ACPI AML code for Mutex
+ * Arg0: Pointer to name of mutex
+ * Arg1: Initial value of mutex
+ */
+void acpigen_write_mutex(const char *name, const uint8_t flags)
+{
+	/* MutexOp */
+	acpigen_emit_ext_op(MUTEX_OP);
+	/* NameString 4 chars only */
+	acpigen_emit_simple_namestring(name);
+	acpigen_emit_byte(flags);
+}
+
+void acpigen_write_acquire(const char *name, const uint16_t val)
+{
+	/* AcquireOp */
+	acpigen_emit_ext_op(ACQUIRE_OP);
+	/* NameString 4 chars only */
+	acpigen_emit_simple_namestring(name);
+	acpigen_emit_word(val);
+}
+
+void acpigen_write_release(const char *name)
+{
+	/* ReleaseOp */
+	acpigen_emit_ext_op(RELEASE_OP);
+	/* NameString 4 chars only */
+	acpigen_emit_simple_namestring(name);
+}
+
 static void acpigen_write_field_length(uint32_t len)
 {
 	uint8_t i, j;

diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c
@@ -13,7 +13,6 @@
 
 #include <arch/acpigen.h>
 #include <arch/acpigen_dsm.h>
-#include <stdlib.h>
 
 /* -------------------  I2C HID DSM ---------------------------- */
 

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
@@ -13,8 +13,6 @@
 
 #include <rules.h>
 
-#if !CONFIG(ROMCC_BOOTBLOCK)
-
 /*
  * This path is for stages that are post bootblock. The gdt is reloaded
  * to accommodate platforms that are executing out of CAR. In order to
@@ -60,26 +58,3 @@ debug_spinloop:
 	/* Expect to never return. */
 1:
 	jmp	1b
-
-#else
-
-/* This file assembles the start of the romstage program by the order of the
- * includes. Thus, it's extremely important that one pays very careful
- * attention to the order of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/32bit/entry32.inc>
-#include <cpu/x86/fpu_enable.inc>
-#if CONFIG(SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * The assembly.inc is generated based on the requirements of the mainboard.
- * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
- * processed by ROMCC and added. In non-ROMCC boards the chipsets'
- * cache-as-ram setup files would be here.
- */
-#include <generated/assembly.inc>
-
-#endif
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c
@@ -11,10 +11,11 @@
  * GNU General Public License for more details.
  */
 
-#include <smp/node.h>
-#include <arch/bootblock_romcc.h>
+#include <cbfs.h>
 #include <pc80/mc146818rtc.h>
-#include <halt.h>
+#include <program_loading.h>
+#include <stddef.h>
+#include <string.h>
 
 static const char *get_fallback(const char *stagelist)
 {
@@ -23,44 +24,22 @@ static const char *get_fallback(const char *stagelist)
 	return ++stagelist;
 }
 
-static void main(unsigned long bist)
+int legacy_romstage_selector(struct prog *romstage)
 {
-	u8 boot_mode;
-	const char *default_filenames =
-		"normal/romstage\0fallback/romstage";
-
-	if (boot_cpu()) {
-		bootblock_mainboard_init();
-
-		sanitize_cmos();
-
-		boot_mode = do_normal_boot();
-	} else {
-
-		/* Questionable single byte read from CMOS.
-		 * Do not add any other CMOS access in the
-		 * bootblock for AP CPUs.
-		 */
-		boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE));
-	}
-
-	char *normal_candidate = (char *)walkcbfs("coreboot-stages");
-
-	if (!normal_candidate)
-		normal_candidate = default_filenames;
-
-	unsigned long entry;
-
-	if (boot_mode) {
-		entry = findstage(normal_candidate);
-		if (entry)
-			call(entry, bist);
+	static const char *default_filenames = "normal/romstage\0fallback/romstage";
+	const char *boot_candidate;
+	size_t stages_len;
+
+	boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len);
+	if (!boot_candidate)
+		boot_candidate = default_filenames;
+
+	if (do_normal_boot()) {
+		romstage->name = boot_candidate;
+		if (!prog_locate(romstage))
+			return 0;
 	}
 
-	entry = findstage(get_fallback(normal_candidate));
-	if (entry)
-		call(entry, bist);
-
-	/* duh. we're stuck */
-	halt();
+	romstage->name = get_fallback(boot_candidate);
+	return prog_locate(romstage);
 }
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
@@ -148,7 +148,7 @@ gdtaddr:
 	 .data
 
 	/* This is the gdt for GCC part of coreboot.
-	 * It is different from the gdt in ROMCC/ASM part of coreboot
+	 * It is different from the gdt in ASM part of coreboot
 	 * which is defined in entry32.inc
 	 *
 	 * When the machine is initially started, we use a very simple

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -36,11 +36,9 @@
 	/* Stack for CAR stages. Since it persists across all stages that
 	 * use CAR it can be reused. The chipset/SoC is expected to provide
 	 * the stack size. */
-#if !CONFIG(ROMCC_BOOTBLOCK)
 	_car_stack = .;
 	. += CONFIG_DCACHE_BSP_STACK_SIZE;
 	_ecar_stack = .;
-#endif
 	/* The pre-ram cbmem console as well as the timestamp region are fixed
 	 * in size. Therefore place them above the car global section so that
          * multiple stages (romstage and verstage) have a consistent
@@ -86,10 +84,6 @@
 	_ebss = .;
 	_car_unallocated_start = .;
 
-#if CONFIG(ROMCC_BOOTBLOCK)
-	_car_stack = .;
-	_ecar_stack = _car_region_end;
-#endif
 	_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
 }
 
@@ -108,6 +102,4 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
 #if CONFIG(PAGING_IN_CACHE_AS_RAM)
 _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
 #endif
-#if !CONFIG(ROMCC_BOOTBLOCK)
 _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
-#endif
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <stdlib.h>
 #include <cbmem.h>
 
 #if CONFIG(CBMEM_TOP_BACKUP)

diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c
@@ -13,7 +13,6 @@
  */
 
 #include <stdint.h>
-#include <string.h>
 #include <arch/acpi.h>
 #include <arch/ebda.h>
 #include <commonlib/endian.h>

diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld
@@ -12,7 +12,7 @@
  */
 
 SECTIONS {
-	. = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 0x10;
+	. = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
 	.id (.): {
 		KEEP(*(.id))
 	}

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
@@ -45,7 +45,7 @@
 #define ACPI_TABLE_CREATOR	"COREBOOT"  /* Must be exactly 8 bytes long! */
 #define OEM_ID			"COREv4"    /* Must be exactly 6 bytes long! */
 
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 #include <commonlib/helpers.h>
 #include <device/device.h>
 #include <uuid.h>

diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
@@ -14,7 +14,6 @@
 #ifndef LIBACPI_H
 #define LIBACPI_H
 
-#include <stdlib.h>
 #include <stdint.h>
 #include <arch/acpi.h>
 #include <arch/acpi_device.h>
@@ -410,6 +409,21 @@ void acpigen_write_rom(void *bios, const size_t length);
  * length.
  */
 void acpigen_write_opregion(struct opregion *opreg);
+/*
+ * Generate ACPI AML code for Mutex
+ * This function takes mutex name and initial value.
+ */
+void acpigen_write_mutex(const char *name, const uint8_t flags);
+/*
+ * Generate ACPI AML code for Acquire
+ * This function takes mutex name and privilege value.
+ */
+void acpigen_write_acquire(const char *name, const uint16_t val);
+/*
+ * Generate ACPI AML code for Release
+ * This function takes mutex name.
+ */
+void acpigen_write_release(const char *name);
 /*
  * Generate ACPI AML code for Field
  * This function takes input region name, fieldlist, count & flags.

diff --git a/src/cpu/intel/car/bootblock.h → src/arch/x86/include/arch/bootblock.h b/src/cpu/intel/car/bootblock.h → src/arch/x86/include/arch/bootblock.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _CPU_INTEL_CAR_BOOTBLOCK_H
-#define _CPU_INTEL_CAR_BOOTBLOCK_H
+#ifndef __ARCH_BOOTBLOCK_H__
+#define __ARCH_BOOTBLOCK_H__
 
 void bootblock_early_cpu_init(void);
 void bootblock_early_northbridge_init(void);

diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
@@ -218,9 +218,6 @@ static inline bool cpu_is_intel(void)
 	return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON);
 }
 
-#ifndef __ROMCC__
-/* romcc does not support anonymous structs. */
-
 struct device;
 
 struct cpu_device_id {
@@ -288,13 +285,11 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 #define asmlinkage __attribute__((regparm(0)))
 
 /*
- * When not using a romcc bootblock the car_stage_entry() is the symbol
- * jumped to for each stage after bootblock using cache-as-ram.
+ * The car_stage_entry() is the symbol jumped to for each stage
+ * after bootblock using cache-as-ram.
  */
 asmlinkage void car_stage_entry(void);
 
-#endif
-
 /*
  * Get processor id using cpuid eax=1
  * return value in EAX register

diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h
@@ -14,16 +14,9 @@
 #ifndef ARCH_HLT_H
 #define ARCH_HLT_H
 
-#if defined(__ROMCC__)
-static void hlt(void)
-{
-	__builtin_hlt();
-}
-#else
 static __always_inline void hlt(void)
 {
 	asm("hlt");
 }
-#endif
 
 #endif /* ARCH_HLT_H */
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
@@ -21,39 +21,6 @@
  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
  * (insb/insw/insl/outsb/outsw/outsl).
  */
-#if defined(__ROMCC__)
-static inline void outb(uint8_t value, uint16_t port)
-{
-	__builtin_outb(value, port);
-}
-
-static inline void outw(uint16_t value, uint16_t port)
-{
-	__builtin_outw(value, port);
-}
-
-static inline void outl(uint32_t value, uint16_t port)
-{
-	__builtin_outl(value, port);
-}
-
-
-static inline uint8_t inb(uint16_t port)
-{
-	return __builtin_inb(port);
-}
-
-
-static inline uint16_t inw(uint16_t port)
-{
-	return __builtin_inw(port);
-}
-
-static inline uint32_t inl(uint16_t port)
-{
-	return __builtin_inl(port);
-}
-#else
 static inline void outb(uint8_t value, uint16_t port)
 {
 	__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
@@ -89,7 +56,6 @@ static inline uint32_t inl(uint16_t port)
 	__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
 	return value;
 }
-#endif /* __ROMCC__ */
 
 static inline void outsb(uint16_t port, const void *addr, unsigned long count)
 {

diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h
@@ -34,13 +34,11 @@ static __always_inline uint32_t read32(
 	return *((volatile uint32_t *)(addr));
 }
 
-#ifndef __ROMCC__
 static __always_inline uint64_t read64(
 	const volatile void *addr)
 {
 	return *((volatile uint64_t *)(addr));
 }
-#endif
 
 static __always_inline void write8(volatile void *addr,
 	uint8_t value)
@@ -60,12 +58,10 @@ static __always_inline void write32(volatile void *addr,
 	*((volatile uint32_t *)(addr)) = value;
 }
 
-#ifndef __ROMCC__
 static __always_inline void write64(volatile void *addr,
 	uint64_t value)
 {
 	*((volatile uint64_t *)(addr)) = value;
 }
-#endif
 
 #endif /* __ARCH_MMIO_H__ */