diff --git a/Documentation/distributions.md b/Documentation/distributions.md
@@ -0,0 +1,91 @@
+# Distributions
+
+coreboot doesn't provide binaries but provides a toolbox that others can use
+to build boot firmware for all kinds of purposes. These third-parties can be
+broadly separated in two groups: Those shipping coreboot on their hardware,
+and those providing after-market firmware to extend the usefulness of devices.
+
+
+## Hardware shipping with coreboot
+
+### Purism
+
+[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
+security; part of that effort is to minimize the amount of proprietary and/or
+binary code. Their laptops ship with a blob-free OS and coreboot firmware
+with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
+
+### ChromeOS Devices
+
+All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
+Chromebit, etc) released from 2012 onward use coreboot for their main system
+firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
+running on the Embedded Controller (EC - a small microcontroller which provides
+functions like battery management, keyboard support, and sensor interfacing)
+is open source as well.
+
+### Libretrend
+
+[Libretrend](https://libretrend.com) sells the Librebox, a NUC-like PC which
+ships with coreboot firmware.
+
+
+### PC Engines APUs
+
+[PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that
+ships with coreboot and support upstream maintenance for the devices through a
+third party, [3mdeb](https://3mdeb.com). They provide current and tested
+firmware binaries on [GitHub](https://pcengines.github.io).
+
+## After-market firmware
+
+### Libreboot
+
+[Libreboot](https://libreboot.org) is a downstream coreboot distribution that
+provides ready-made firmware images for supported devices: those which can be
+built entirely from source code. Their copy of the coreboot repository is
+therefore stripped of all devices that require binary components to boot.
+
+### MrChromebox
+
+[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
+images for the vast majority of x86-based Chromebooks and Chromeboxes, using
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
+coreboot with coreboot? Mr Chromebox's images are built using upstream
+coreboot (vs Google's older, static tree/branch), include many features and
+fixes not found in the stock firmware, and offer much broader OS compatibility
+(i.e., they run Windows as well as Linux). They also offer updated CPU
+microcode, as well as firmware updates for the device's embedded controller
+(EC). This firmware "takes the training wheels off" your ChromeOS device :)
+
+### John Lewis
+
+[John Lewis](https://johnlewis.ie/custom-chromebook-firmware) also provides
+replacement firmware for ChromeOS devices, for the express purpose of
+running Linux on Chromebooks. John Lewis' firmware supports a much smaller
+set of devices, and uses SeaBIOS as the payload to support Legacy BIOS booting.
+His firmware images are significantly older, and not actively maintained or
+supported, but worth a look if you need Legacy Boot support and is not
+available via Mr Chromebox's firmware.
+
+### Heads
+
+[Heads](http://osresearch.net) is an open source custom firmware and OS
+configuration for laptops and servers that aims to provide slightly better
+physical security and protection for data on the system. Unlike
+[Tails](https://tails.boum.org/), which aims to be a stateless OS that leaves
+no trace on the computer of its presence, Heads is intended for the case where
+you need to store data and state on the computer.
+
+Heads is not just another Linux distribution – it combines physical hardening
+of specific hardware platforms and flash security features with custom coreboot
+firmware and a Linux boot loader in ROM.
+
+### Skulls
+
+[Skulls](https://github.com/merge/skulls) provides firmware images for
+laptops like the Lenovo Thinkpad X230. It uses upstream coreboot, an easy
+to use payload like SeaBIOS and Intel's latest microcode update.
+
+It simplifies installation and includes compact documentation. Skulls also
+enables easy switching to [Heads](#heads) and back.
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -5,14 +5,171 @@ It is built from Markdown files in the
 [Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
 directory in the source code.
 
+## Purpose of coreboot
+
+coreboot is a project to develop open source boot firmware for various
+architectures. Its design philosophy is to do the bare minimum necessary to
+ensure that hardware is usable and then pass control to a different program
+called the _payload_.
+
+### Separation of concerns
+
+The payload can then provide user interfaces, file system drivers,
+various policies etc. to load the OS. Through this separation of concerns
+coreboot maximizes reusability of the complicated and fundamental hardware
+initialization routines across many different use cases, no matter if
+they provide standard interfaces or entirely custom boot flows.
+
+Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
+GRUB2, the bootloader used by many Linux distributions, or depthcharge,
+a custom boot loader used on Chromebooks.
+
+### No resident services (if possible)
+
+Ideally coreboot completely hands over control to the payload with no
+piece of coreboot remaining resident in the system, or even available
+for callback.  Given the reality of contemporary computer design,
+there's often a small piece that survives for the whole runtime of
+the computer. It runs in a highly privileged CPU mode (e.g. SMM on x86)
+and provides some limited amount of services to the OS. But here, too,
+coreboot aims to keep everything at the minimum possible, both in scope
+(e.g. services provided) and code size.
+
+### No specification of its own
+
+coreboot uses a very minimal interface to the payload, and otherwise
+doesn't impose any standards on the ecosystem. This is made possible by
+separating out concerns (interfaces and resident services are delegated
+to the payload), but it's also a value that is deeply ingrained in the
+project. We fearlessly rip out parts of the architecture and remodel it
+when a better way of doing the same was identified.
+
+### One tree for everything
+
+Another difference to various other firmware projects is that we try
+to avoid fragmentation: the traditional development model of firmware
+is one of "set and forget" in which some code base is copied, adapted
+for the purpose at hands, shipped and only touched again if there's an
+important fix to do.
+
+All newer development happens on another copy of some code base without
+flowing back to any older copy, and so normally there's a huge amount
+of fragmentation.
+
+In coreboot, we try to keep everything in a single source tree, and
+lift up older devices when we change something fundamentally. That way,
+new and old devices benefit alike from new development in the common parts.
+
+There's a downside to that: Some devices might have no maintainer anymore
+who could ensure that coreboot is still functional for them after a big
+rework, or maybe a rework even requires knowledge that doesn't exist
+anymore within the project (for example because the developer moved on
+to do something else).
+
+In this case, we announce the deprecation of the device and defer the big
+rework until the deprecation period passed, typically 6-12 months. This
+gives interested developers a chance to step in and bring devices up to
+latest standards.
+
+While without this deprecation mechanism we could inflate the number
+of supported devices (probably 300+), only a tiny fraction of them
+would even work, which helps nobody.
+
+## Scope of the coreboot project
+
+coreboot as a project is closer to the Linux kernel than to most
+user level programs. One place where this becomes apparent is the
+distribution mechanism: The project itself only provides source code
+and does not ship ready-to-install coreboot-based firmware binaries.
+
+What the project distributes, even if - strictly speaking - it's not
+part of the project, is a collection of vendor binaries (that we call
+"blobs") that are redistributable. They cover the parts of hardware init
+that we haven't managed to open up, and while some hardware requires them,
+there's still hardware that can boot without any such binary components.
+
+The build system can integrate them into the build automatically if
+required, but that requires explicit opt-in and downloads a separate
+repository to ensure that the distinction remains clear.
+
+There are various [distributions](distributions.md), some shipping
+coreboot with their hardware (e.g. Purism or Chromebooks), others
+providing after-market images for various devices (e.g. Libreboot,
+MrChromebox).
+
+If you want to use coreboot on your system, that's great!
+
+Please note that the infrastructure around coreboot.org is built for
+development purposes. We gladly help out users through our communication
+channels, but we also expect a "firmware developer mindset": If compiling
+your own firmware and, at some point, recovering from a bad flash by
+hooking wires onto chips in your computer sounds scary to you, you're
+right, as it is.
+
+If that's _way_ beyond your comfort zone, consider looking into the
+various distributions, as they typically provide pre-tested binaries
+which massively reduces the risk that the binary you write to flash is
+one that won't boot the system (with the consequence that to get it to work
+again, you'll need to attach various tools to various chips)
+
+## The coreboot community
+
+If you're interested in getting your hands dirty (incl. potentially wiring
+up an external flasher to your computer), you've come to the right place!
+
+We have various [forums](community/forums.md) where we discuss and coordinate
+our activities, review patches, and help out each other. To
+help promote a positive atmosphere, we established a [Code of
+Conduct](community/code_of_conduct.md). We invested a lot of time
+to balance it out, so please keep it in mind when engaging with the
+coreboot community.
+
+Every now and then, coreboot is present in one way or another at
+[conferences](community/conferences.md). If you're around, come and
+say hello!
+
+## Getting the source code
+
+coreboot is primarily developed in the
+[git](https://review.coreboot.org/cgit/coreboot.git) version control
+system, using [Gerrit](https://review.coreboot.org) to manage
+contributions and code review.
+
+In general we try to keep the `master` branch in the repository functional
+for all hardware we support. So far, the only guarantee we can make is
+that the master branch will (nearly) always build for all boards in a
+standard configuration.
+
+However, we're continually working on improvements to our infrastructure to
+get better in that respect, e.g. by setting up boot testing facilities. This
+is obviously more complex than regular integration testing, so progress
+is slow.
+
+### What our releases mean
+
+We also schedule two source code releases every year, around April and
+October. These releases see some very limited testing and mostly serve
+as synchronization points for deprecation notices and for other projects
+such as external distributions.
+
+This approach and terminology differs somewhat from how other projects handle
+releases where releases are well-tested artifacts and the development
+repository tends to be unstable. The "rolling release" model of some projects,
+for example OpenBSD, is probably the closest cousin of our approach.
+
 Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Rookie Guide](lessons/index.md)
 * [Coding Style](coding_style.md)
+* [Project Ideas](contributing/project_ideas.md)
 * [Code of Conduct](community/code_of_conduct.md)
 * [Community forums](community/forums.md)
 * [coreboot at conferences](community/conferences.md)
+* [Security](security.md)
+* [Payloads](payloads.md)
+* [Distributions](distributions.md)
 * [Timestamps](timestamp.md)
 * [Intel IFD Binary Extraction](Binary_Extraction.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)

diff --git a/Documentation/lessons/lesson1.md b/Documentation/lessons/lesson1.md
@@ -8,7 +8,7 @@ Download, configure, and build coreboot
 ---------------------------------------
 
 ### Step 1 - Install tools and libraries needed for coreboot
-    $ sudo apt-get install -y bison build-essential curl flex git gnat-5 libncurses5-dev m4 zlib1g-dev
+    $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
 
 ### Step 2 - Download coreboot source tree
     $ git clone https://review.coreboot.org/coreboot
@@ -99,8 +99,9 @@ required installed by default.
 on some Ubuntu flavors, and not on others.
 * `git` is needed to download coreboot from the coreboot git repository.
 * `libncurses5-dev` is needed to build the menu for 'make menuconfig'
-* `m4, bison, curl, flex, gnat-5, zlib1g-dev` are needed to build the coreboot
-toolchain.
+* `m4, bison, curl, flex, zlib1g-dev, gcc, gnat` and `g++` or `clang`
+are needed to build the coreboot toolchain. `gcc` and `gnat` have to be
+of the same version.
 
 If you started with a different distribution, you might need to install many
 other items which vary by distribution.

diff --git a/Documentation/payloads.md b/Documentation/payloads.md
@@ -0,0 +1,42 @@
+# Payloads
+
+coreboot doesn't try to mandate how the boot process should look, it merely
+does hardware init and then passes on control to another piece of software
+that we carry along in firmware storage, the _payload_.
+
+There is various software in that space that is either explicitly written as
+payload or can be made to work as one.
+
+## SeaBIOS
+
+[SeaBIOS](https://www.seabios.org) is an open source implementation of
+the PCBIOS API that exists since the original IBM PC and was extended
+since. While originally written for emulators such as QEMU, it can be made
+to work as a coreboot payload and all the necessary code is in SeaBIOS'
+mainline code.
+
+## Tianocore
+
+[Tianocore](https://www.tianocore.org) is the open source reference
+implementation of the UEFI Specifications that modern firmware for PCs is
+based on. There were various projects in the past to make it suitable as a
+coreboot payload, but these days this function is available directly in the
+CorebootPayloadPkg part of its source tree.
+
+## GRUB2
+
+GRUB2 was originally written as a bootloader and that's its most popular
+purpose, but it can also be compiled as a coreboot payload.
+
+## Linux
+
+There are several projects using Linux as a payload (which was the
+configuration that gave coreboot its original name, LinuxBIOS). That kernel is
+often rather small and serves to load a current kernel from somewhere, e.g.
+disk or network, and run that through the kexec mechanism.
+
+Two aspects emphasized by proponents of Linux-as-a-payload are the
+availability of well-tested, battle-hardened drivers (as compared to
+firmware project drivers that often reinvent the wheel) and the ability to
+define boot policy with familiar tools, no matter if those are shell scripts
+or compiled userland programs written in C, Go or other programming languages.
diff --git a/Documentation/security.md b/Documentation/security.md
@@ -0,0 +1,5 @@
+# Security
+
+## Google VBoot2 Measured boot extension
+
+- [Measured Boot](vboot/measured_boot.md)
diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md
@@ -0,0 +1,58 @@
+# Measured Boot
+coreboot measured boot is implemented as Google Verified Boot extension. This
+means in order to use it, vboot needs to be available for your platform.
+
+## IBB/CRTM
+The "Initial Boot Block" or "Core Root of Trust for Measurement" is the first
+code block loaded at reset vector and measured by a DRTM solution.
+In case SRTM mode is active, the IBB measures itself before measuring the next
+code block. In coreboot, cbfs files which are part of the IBB are identified
+by a metatdata tag. This makes it possible to have platform specific IBB
+measurements without hardcoding them.
+
+## Known Limitations
+At the moment measuring IBB dynamically and FMAP partitions are not possible but
+will be added later to the implementation.
+
+Also SoCs making use of VBOOT_RETURN_FROM_VERSTAGE are not able to use the
+measured boot extension because of platform constraints.
+
+## SRTM Mode
+The "Static Root of Trust for Measurement" is the easiest way doing measurements
+by measuring code before it is loaded.
+
+![][srtm]
+
+[srtm]: srtm.png
+
+## DRTM Mode
+The "Dynamic Root of Trust for Measurement" is realised by platform features
+like Intel TXT or Boot Guard. The features provide a way of loading a signed
+"Authenticated Code Module" aka signed blob. Most of these features are also
+a "Trusted Execution Environment", e.g. Intel TXT.
+
+DRTM gives you the ability of measuring the IBB from a higher Root of Trust
+instead of doing it yourself without any hardware support.
+
+## Platform Configuration Register
+Normally PCR 0-7 are reserved for firmware usage. In coreboot we use just 4 PCR
+banks in order to store the measurements. coreboot uses the SHA-1 or SHA-256
+hash algorithm depending on the TPM specification for measurements. PCR-4 to
+PCR-7 are left empty.
+
+### PCR-0
+_Hash:_ SHA1
+_Description:_ Google VBoot GBB flags.
+
+### PCR-1
+_Hash:_ SHA1/SHA256
+_Description:_ Google VBoot GBB HWID.
+
+### PCR-2
+_Hash:_ SHA1/SHA256
+_Description:_ Core Root of Trust for Measurement which includes all stages,
+data and blobs.
+
+### PCR-3
+_Hash:_ SHA1/SHA256
+_Description:_ Runtime data like hwinfo.hex or MRC cache.
diff --git a/Documentation/security/vboot/srtm.png b/Documentation/security/vboot/srtm.png
diff --git a/MAINTAINERS b/MAINTAINERS
@@ -306,8 +306,10 @@ S:	Supported
 F:	/src/mainboard/intel/strago/
 
 INTEL BRASWELL SOC
-M:	Hannah Williams <hannah.williams@intel.com>
-S:	Supported
+M:	Piotr Król <piotr.krol@3mdeb.com>
+M:	Michał Żygowski <michal.zygowski@3mdeb.com>
+M:	Frans Hendriks <fhendriks@eltan.com>
+S:	Maintained
 F:	/src/soc/intel/braswell
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell
 

diff --git a/Makefile b/Makefile
@@ -188,6 +188,9 @@ $(KCONFIG_AUTOCONFIG): $(KCONFIG_AUTOHEADER)
 $(KCONFIG_AUTOADS): $(KCONFIG_AUTOCONFIG) $(objutil)/kconfig/toada
 	$(objutil)/kconfig/toada CB.Config <$< >$@
 
+$(obj)/%/$(notdir $(KCONFIG_AUTOADS)): $(KCONFIG_AUTOADS)
+	cp $< $@
+
 # Add a new class of source/object files to the build system
 add-class= \
 	$(eval $(1)-srcs:=) \
@@ -272,6 +275,11 @@ $(eval $(postinclude-hooks))
 # Eliminate duplicate mentions of source files in a class
 $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
 
+# Build Kconfig .ads if necessary
+ifeq ($(CONFIG_RAMSTAGE_ADA),y)
+ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS))
+endif
+
 # To track dependencies, we need all Ada specification (.ads) files in
 # *-srcs. Extract / filter all specification files that have a matching
 # body (.adb) file here (specifications without a body are valid sources
@@ -320,7 +328,7 @@ define create_cc_template
 ifn$(EMPTY)def $(1)-objs_$(2)_template
 de$(EMPTY)fine $(1)-objs_$(2)_template
 ifn$(EMPTY)eq ($(filter ads adb,$(2)),)
-$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $$(call create_ada_deps,$1,$$(call src-to-ali,$1,$$(1).$2)) $(KCONFIG_AUTOHEADER) $(4)
+$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $$(call create_ada_deps,$1,$$(call src-to-ali,$1,$$(1).$2)) $(4)
 	@printf "    GCC        $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$(GCC_$(1)) \
 		$$$$(ADAFLAGS_$(1)) $$$$(addprefix -I,$$$$($(1)-ada-dirs)) \

diff --git a/Makefile.inc b/Makefile.inc
@@ -146,6 +146,7 @@ int-lt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(wor
 int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) \> $(call _toint,$(word 2,$1))))
 int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1))))
 int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + \( \( $$B - \( $$A % $$B \) \) % $$B \) )
+int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - \( $$A % $$B \) )
 file-size=$(strip $(shell cat $1 | wc -c))
 tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
 toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
@@ -215,7 +216,9 @@ verstage-c-deps:=$$(OPTION_TABLE_H)
 bootblock-c-deps:=$$(OPTION_TABLE_H)
 $(foreach type,ads adb, \
   $(foreach stage,$(COREBOOT_STANDARD_STAGES), \
-    $(eval $(stage)-$(type)-deps := $(obj)/libgnat-$(ARCH-$(stage)-y)/libgnat.a)))
+    $(eval $(stage)-$(type)-deps := \
+	$(obj)/$(stage)/$(notdir $(KCONFIG_AUTOADS)) \
+	$(obj)/libgnat-$(ARCH-$(stage)-y)/libgnat.a)))
 
 # Add handler to copy linker scripts
 define generic-objs_ld_template_gen
@@ -262,8 +265,8 @@ cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml
 -include $(obj)/$(1).d
 $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
 	@printf "    IASL       $$(subst $(top)/,,$$(@))\n"
-	$(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@
-	cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $$(notdir $$@)
+	$(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $(obj)/$(1).asl
+	cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $(1).asl
 	if [ -z "$$$$($(IASL) -d $$@ 2>&1 | grep 'ACPI Warning')" ]; then echo "    IASL       $$@ disassembled correctly."; true; else echo "Error: Could not correctly disassemble $$@"; $(IASL) -d $$@; false; fi
 endef
 
@@ -379,7 +382,6 @@ COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION
 endif
 
 CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
-CPPFLAGS_common += -Isrc/device/oprom/include
 VBOOT_SOURCE ?= 3rdparty/vboot
 CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
@@ -388,6 +390,10 @@ CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
 CPPFLAGS_common += -I3rdparty
 CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\"
 
+ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL)$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE),y)
+CPPFLAGS_ramstage += -Isrc/device/oprom/include
+endif
+
 CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
@@ -847,22 +853,19 @@ FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE))
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
 # entire "BIOS" region (everything directly of concern to the host system)
 # relative to ROM_BASE
-FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE))
-FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f)
+FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000)
+FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000)
 # position and size of flashmap, relative to BIOS_BASE
-FMAP_FMAP_BASE := 0
-FMAP_FMAP_SIZE := 0x200
 
 #
 # X86 CONSOLE FMAP region
 #
 # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled
+FMAP_CONSOLE_BASE := 0
 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_CONSOLE_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE)
 FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE)
 else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_CONSOLE_BASE := 0
 FMAP_CONSOLE_SIZE := 0
 FMAP_CONSOLE_ENTRY :=
 endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
@@ -872,13 +875,8 @@ endif # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
 #
 # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled
 ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
-ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
-FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
+FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add,  $(FMAP_CONSOLE_BASE) \
 	$(FMAP_CONSOLE_SIZE)), 0x10000)
-else
-FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_FMAP_BASE) \
-	$(FMAP_FMAP_SIZE)), 0x10000)
-endif
 FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE)
 FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE)
 else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
@@ -887,15 +885,35 @@ FMAP_MRC_CACHE_SIZE := 0
 FMAP_MRC_CACHE_ENTRY :=
 endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
 
+#
+# X86 SMMSTORE FMAP region
+#
+# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled
+ifeq ($(CONFIG_SMMSTORE),y)
+FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
+	$(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000)
+FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE)
+FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE)
+else # ifeq ($(CONFIG_SMMSTORE),y)
+FMAP_SMMSTORE_BASE := 0
+FMAP_SMMSTORE_SIZE := 0
+FMAP_SMMSTORE_ENTRY :=
+endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
+
+#
+# X86 FMAP region
+#
+#
+# position, size
+FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \
+	$(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE))
+FMAP_FMAP_SIZE := 0x200
+
 #
 # X86 COREBOOT default cbfs FMAP region
 #
 # position and size of CBFS, relative to BIOS_BASE
-ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE))
-else
-FMAP_CBFS_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_FMAP_SIZE))
-endif
+FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE))
 FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE))
 else # ifeq ($(CONFIG_ARCH_X86),y)
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd
@@ -962,6 +980,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
 	    -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
 	    -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
 	    -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
+	    -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
 	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
 	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
 		$(DEFAULT_FLASHMAP) > $@.tmp

diff --git a/configs/config.intel_galileo_gen2.fsp1.1 b/configs/config.intel_galileo_gen2.fsp1.1
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,18 +1,16 @@
-CONFIG_LOCALVERSION="v4.9.0.2"
+CONFIG_LOCALVERSION="v4.9.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_BOARD_PCENGINES_APU1=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
-CONFIG_IPXE_MASTER=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_USER_TPM2=y
diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,20 +1,21 @@
-CONFIG_LOCALVERSION="v4.9.0.2"
+CONFIG_LOCALVERSION="v4.9.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
-CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,157b"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
-CONFIG_USER_TPM2=y
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,7 +1,8 @@
-CONFIG_LOCALVERSION="v4.9.0.2"
+CONFIG_LOCALVERSION="v4.9.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
@@ -10,10 +11,10 @@ CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(C
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
-CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,7 +1,8 @@
-CONFIG_LOCALVERSION="v4.9.0.2"
+CONFIG_LOCALVERSION="v4.9.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
@@ -10,10 +11,10 @@ CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(C
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
-CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,20 +1,21 @@
-CONFIG_LOCALVERSION="v4.9.0.2"
+CONFIG_LOCALVERSION="v4.9.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
-CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
-CONFIG_USER_TPM2=y
+CONFIG_MEMTEST_REVISION=y
+CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -179,6 +179,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
 		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
 		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
+		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \

diff --git a/payloads/external/sortbootorder/Makefile b/payloads/external/sortbootorder/Makefile
@@ -1,4 +1,4 @@
-version=4.6.12
+version=4.6.13
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
@@ -11,28 +11,22 @@ choice
 	default TIANOCORE_STABLE
 	help
 	  Select which version of Tianocore to build (default is to build stable)
-	  stable: a version of Tianocore that builds without any errors
-	  master: most recent version from upstream Tianocore repository
+	  stable: MrChromebox's customized version of Tianocore which works on most
+	  (all?) x86_64 devices
 	  revision: use specific commit or branch to build Tianocore (specified by user)
 
 config TIANOCORE_STABLE
 	bool "stable"
 	help
-	  Select this option to build the stable tianocore version
-	  i.e. a version of Tianocore that builds without any errors
-
-config TIANOCORE_MASTER
-	bool "master"
-	help
-	  Select this option to build the master tianocore version
-	  i.e. most recent version from upstream Tianocore repository
+	  Select this option to build using MrChromebox's custom Tianocore tree
+	  i.e. a version of Tianocore that builds without any errors and just works.
 
 config TIANOCORE_REVISION
 	bool "git revision"
 	help
 	  Select this option if you have a specific commit or branch
-	  that you want to use as the revision from which to
-	  build Tianocore.
+	  that you want to use from either MrChromebox's tree or upstream
+	  EDK2 from which to build Tianocore.
 
 	  You will be able to specify the name of a branch or a commit id
 	  later.
@@ -42,7 +36,7 @@ endchoice
 config TIANOCORE_REVISION_ID
 	string "Insert a commit's SHA-1 or a branch name"
 	depends on TIANOCORE_REVISION
-	default "origin/master"
+	default "upstream/master"
 	help
 	   The commit's SHA-1 or branch name of the revision to use.
 
@@ -93,4 +87,24 @@ config TIANOCORE_USE_8254_TIMER
 	help
 	  Use 8254 Timer for legacy support.
 
+config TIANOCORE_BOOTSPLASH_IMAGE
+	bool "Use a custom bootsplash image"
+	depends on TIANOCORE_STABLE
+	help
+	  Select this option if you have a bootsplash image that you would
+	  like to be used. If this option is not selected, the default
+	  coreboot logo (European Brown Hare) will used.
+
+config TIANOCORE_BOOTSPLASH_FILE
+	string "Tianocore Bootsplash path and filename"
+	depends on TIANOCORE_BOOTSPLASH_IMAGE
+	default "bootsplash.bmp"
+	help
+	  The path and filename of the file to use as graphical bootsplash
+	  screen. The file format must be uncompressed BMP, and the file's
+	  resolution must be less than the native resolution of the display.
+
+	  If an absolute path is not given, the path will assumed to be
+	  relative to the coreboot root directory.
+
 endif
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
@@ -16,15 +16,15 @@
 # force the shell to bash - the edksetup.sh script doesn't work with dash
 export SHELL := env bash
 
-# STABLE_COMMIT_ID represent official edk2 release, currently UDK2018
-STABLE_COMMIT_ID=3e72ffe8afdd03f1f89eba65c921cbdcb004cfee
-TAG-$(CONFIG_TIANOCORE_MASTER)=origin/master
-TAG-$(CONFIG_TIANOCORE_STABLE)=$(STABLE_COMMIT_ID)
-TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID)
-
 project_name=Tianocore
 project_dir=$(CURDIR)/tianocore
-project_git_repo=https://github.com/tianocore/edk2
+project_git_repo=https://github.com/mrchromebox/edk2
+project_git_branch=coreboot_fb
+upstream_git_repo=https://github.com/tianocore/edk2
+
+# STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
+TAG-$(CONFIG_TIANOCORE_STABLE)=origin/$(project_git_branch)
+TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID)
 
 export EDK_TOOLS_PATH=$(project_dir)/BaseTools
 
@@ -44,39 +44,28 @@ else
 	BUILD_STR=-a IA32 -a X64 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -b $(BUILD_TYPE) $(TIMER)
 endif
 
-all: build
+all: clean build
 
 $(project_dir):
 	echo "    Cloning $(project_name) from Git"
-	git clone $(project_git_repo) $(project_dir)
-
-fetch: $(project_dir)
-	cd $(project_dir); \
-		git show $(TAG-y) >/dev/null 2>&1 ; \
-		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
-			echo "    Fetching new commits from the $(project_name) repo"; \
-			git fetch; \
-		fi
-
-$(project_dir)/.version_$(TAG-y): fetch
-	if  ! [[ -e $(project_dir)/.version_$(STABLE_COMMIT_ID) ]] || \
-		[ "$(TAG-y)" = "origin/master" ] ; then \
-		rm -f .version_*; \
-		echo "    Checking out $(project_name) revision $(TAG-y)"; \
-		cd  $(project_dir); \
-			git checkout master; \
-			git branch -D coreboot 2>/dev/null; \
-			git checkout -b coreboot $(TAG-y); \
-		for patch in $(CURDIR)/patches/*.patch; do \
-			echo "Applying $$patch"; \
-			cd $(project_dir); \
-			git am --keep-cr --ignore-space-change $$patch || \
-				( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \
-		done; \
-		if ! [ "$(TAG-y)" = "origin/master" ] ; then \
-			touch $(project_dir)/.version_$(STABLE_COMMIT_ID); \
+	git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \
+		cd $(project_dir); \
+		git remote add upstream $(upstream_git_repo)
+
+update: $(project_dir)
+	cd  $(project_dir); \
+		echo "    Fetching new commits from the $(project_name) repo"; \
+		git fetch --multiple origin upstream 2>/dev/null; \
+		if ! git rev-parse --verify -q $(TAG-y) >/dev/null; then \
+			echo "    $(TAG-y) is not a valid git reference"; \
+			exit 1; \
 		fi; \
-	fi; \
+		if git describe --all --dirty | grep -qv dirty; then \
+			echo "    Checking out $(project_name) revision $(TAG-y)"; \
+			git checkout --detach $(TAG-y); \
+		else \
+			echo "    Working directory not clean; will not overwrite"; \
+		fi
 
 checktools:
 	echo "Checking uuid-dev..."
@@ -89,9 +78,18 @@ checktools:
 	type nasm > /dev/null 2>&1 && echo " found nasm." || \
 		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
 
-build: $(project_dir)/.version_$(TAG-y) checktools
+build: update checktools
 	unset CC; $(MAKE) -C $(project_dir)/BaseTools
 	echo " build $(project_name) $(TAG-y)"
+	if [ -n $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) ]; then \
+		echo "    Copying custom bootsplash image"; \
+		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
+			/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+				$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \
+			*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+				$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \
+		esac \
+	fi; \
 	cd $(project_dir); \
 		export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
 		export WORKSPACE=$(project_dir); \
@@ -101,12 +99,13 @@ build: $(project_dir)/.version_$(TAG-y) checktools
 			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
 		fi; \
 		build $(BUILD_STR); \
-		mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd
+		mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
+		git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1
 
 clean:
 	test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
 
 distclean:
 	rm -rf $(project_dir)
 
-.PHONY: all fetch checkout checktools config build clean distclean
+.PHONY: all update checktools config build clean distclean
diff --git a/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch b/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch
diff --git a/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch b/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch
diff --git a/payloads/external/tianocore/patches/03_Library_EndofDXE.patch b/payloads/external/tianocore/patches/03_Library_EndofDXE.patch
diff --git a/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch b/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch
diff --git a/...l/tianocore/patches/05_CorebootPayloadPkg-don-t-use-serial-output-for-Release-build.patch b/...l/tianocore/patches/05_CorebootPayloadPkg-don-t-use-serial-output-for-Release-build.patch
diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch
diff --git a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch b/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch
diff --git a/.../external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch b/.../external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -344,6 +344,10 @@ config PC_KEYBOARD
 	default y if ARCH_X86 # uses IO
 	default n
 
+config PC_KEYBOARD_IGNORE_INIT_FAILURE
+	bool "Ignore keyboard failures during init and always add input device"
+	default n
+
 config PC_KEYBOARD_LAYOUT_US
 	bool "English (US) keyboard layout"
 	depends on PC_KEYBOARD

diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c
@@ -229,8 +229,10 @@ u8 i8042_probe(void)
 	}
 
 	/* Test secondary port */
-	if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0)
-		aux_fifo = fifo_init(4 * 32);
+	if (IS_ENABLED(CONFIG_LP_PC_MOUSE)) {
+		if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0)
+			aux_fifo = fifo_init(4 * 32);
+	}
 
 	/* Test first PS/2 port */
 	if (i8042_cmd_with_response(I8042_CMD_KB_TEST) == 0)

diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -309,16 +309,16 @@ void keyboard_init(void)
 
 	/* Set scancode set 1 */
 	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
-	if (!ret)
+	if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
 
 	ret = keyboard_cmd(I8042_SCANCODE_SET_1);
-	if (!ret)
+	if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
 
 	/* Enable scanning */
 	ret = keyboard_cmd(I8042_KBCMD_EN);
-	if (!ret)
+	if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
 
 	console_add_input_driver(&cons);

diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
@@ -253,8 +253,9 @@ struct cbfs_media {
 void *cbfs_get_file_content(struct cbfs_media *media, const char *name,
 			    int type, size_t *sz);
 
-/* returns decompressed size on success, 0 on failure */
-int cbfs_decompress(int algo, void *src, void *dst, int len);
+/* Returns decompressed size on success, 0 on failure. */
+size_t cbfs_decompress(int algo, const void *src, size_t srcn, void *dst,
+		       size_t dstn);
 
 /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS
  *  on failure */

diff --git a/payloads/libpayload/include/fmap_serialized.h b/payloads/libpayload/include/fmap_serialized.h
@@ -48,6 +48,7 @@ enum fmap_flags {
 	FMAP_AREA_STATIC	= 1 << 0,
 	FMAP_AREA_COMPRESSED	= 1 << 1,
 	FMAP_AREA_RO		= 1 << 2,
+	FMAP_AREA_PRESERVE	= 1 << 3,
 };
 
 /* Mapping of volatile and static regions in firmware binary */

diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
@@ -58,6 +58,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <time.h>
+#include <sys/types.h>
 #include <arch/types.h>
 #include <arch/io.h>
 #include <arch/virtual.h>

diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h
@@ -39,6 +39,7 @@
 void *memset(void *s, int c, size_t n);
 void *memcpy(void *dst, const void *src, size_t n);
 void *memmove(void *dst, const void *src, size_t n);
+void *memchr(const void *s, int c, size_t n);
 int memcmp(const void *s1, const void *s2, size_t len);
 /** @} */
 

diff --git a/payloads/libpayload/include/sys/types.h b/payloads/libpayload/include/sys/types.h
@@ -27,4 +27,11 @@
  * SUCH DAMAGE.
  */
 
+#ifndef _SYS_TYPES_H
+#define _SYS_TYPES_H
+
 #include <arch/types.h>
+
+typedef signed long int off_t;
+
+#endif /* _SYS_TYPES_H */
diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c
@@ -145,3 +145,15 @@ static int default_memcmp(const void *s1, const void *s2, size_t n)
 
 int memcmp(const void *s1, const void *s2, size_t n)
 	__attribute__((weak, alias("default_memcmp")));
+
+
+void *memchr(const void *s, int c, size_t n)
+{
+	unsigned char *p = (unsigned char *)s;
+	while (n--)
+		if (*p != (unsigned char)c)
+			p++;
+		else
+			return p;
+	return 0;
+}
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
@@ -114,8 +114,9 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name)
 	final_size = cbfs_decompress(stage->compression,
 				     ((unsigned char *) stage) +
 				     sizeof(struct cbfs_stage),
+				     stage->len,
 				     (void *) (uintptr_t) stage->load,
-				     stage->len);
+				     stage->memlen);
 	if (!final_size) {
 		entry = -1;
 		goto out;

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -48,6 +48,7 @@
  *
  */
 
+#include <libpayload.h>
 #include <cbfs.h>
 #include <string.h>
 #include <sysinfo.h>
@@ -242,12 +243,9 @@ void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit)
 	}
 
 	if (algo == CBFS_COMPRESS_NONE) {
-		if (limit != 0 && limit < on_media_size) {
-			*size = limit;
+		if (limit != 0 && limit < on_media_size)
 			on_media_size = limit;
-		} else {
-			*size = on_media_size;
-		}
+		*size = on_media_size;
 	}
 
 	void *data = m->map(m, handle->media_offset + handle->content_offset,
@@ -256,9 +254,15 @@ void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit)
 		return NULL;
 
 	ret = malloc(*size);
-	if (ret != NULL && !cbfs_decompress(algo, data, ret, *size)) {
-		free(ret);
-		ret = NULL;
+	if (ret != NULL) {
+		size_t final_size = cbfs_decompress(algo, data, on_media_size,
+						    ret, *size);
+		if (final_size != *size) {
+			ERROR("Expect %zu bytes but got %zu bytes after "
+			      "decompression.\n", *size, final_size);
+			free(ret);
+			ret = NULL;
+		}
 	}
 
 	m->unmap(m, data);
@@ -321,24 +325,27 @@ void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag)
 	return NULL;
 }
 
-int cbfs_decompress(int algo, void *src, void *dst, int len)
+size_t cbfs_decompress(int algo, const void *src, size_t srcn, void *dst,
+		       size_t dstn)
 {
+	size_t len;
 	switch (algo) {
 		case CBFS_COMPRESS_NONE:
+			len = MIN(srcn, dstn);
 			memcpy(dst, src, len);
 			return len;
 #ifdef CBFS_CORE_WITH_LZMA
 		case CBFS_COMPRESS_LZMA:
-			return ulzma(src, dst);
+			return ulzman(src, srcn, dst, dstn);
 #endif
 #ifdef CBFS_CORE_WITH_LZ4
 		case CBFS_COMPRESS_LZ4:
-			return ulz4f(src, dst);
+			return ulz4fn(src, srcn, dst, dstn);
 #endif
 		default:
-			ERROR("tried to decompress %d bytes with algorithm #%x,"
-			      "but that algorithm id is unsupported.\n", len,
-			      algo);
+			ERROR("tried to decompress %zu bytes with algorithm "
+			      "#%x, but that algorithm id is unsupported.\n",
+			      srcn, algo);
 			return 0;
 	}
 }
diff --git a/src/Kconfig b/src/Kconfig
@@ -335,6 +335,18 @@ config SYSTEM_TYPE_LAPTOP
 	default n
 	bool
 
+config SYSTEM_TYPE_TABLET
+	default n
+	bool
+
+config SYSTEM_TYPE_DETACHABLE
+	default n
+	bool
+
+config SYSTEM_TYPE_CONVERTIBLE
+	default n
+	bool
+
 config CBFS_AUTOGEN_ATTRIBUTES
 	default n
 	bool
@@ -654,11 +666,15 @@ config SMBIOS_ENCLOSURE_TYPE
 	hex
 	depends on GENERATE_SMBIOS_TABLES
 	default 0x09 if SYSTEM_TYPE_LAPTOP
+	default 0x1e if SYSTEM_TYPE_TABLET
+	default 0x1f if SYSTEM_TYPE_CONVERTIBLE
+	default 0x20 if SYSTEM_TYPE_DETACHABLE
 	default 0x03
 	help
 	  System Enclosure or Chassis Types as defined in SMBIOS specification.
-	  The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or
-	  SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.
+	  The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop,
+	  convertible, or tablet enclosure will be used if the appropriate
+	  system type is selected.
 
 endmenu
 

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
@@ -36,7 +36,6 @@
 #include <console/console.h>
 
 #include <arch/cache.h>
-#include <arch/io.h>
 
 #if IS_ENABLED(CONFIG_ARM_LPAE)
 /* See B3.6.2 of ARMv7 Architecture Reference Manual */

diff --git a/src/arch/arm/include/armv4/arch/io.h → src/arch/arm/include/armv4/arch/mmio.h b/src/arch/arm/include/armv4/arch/io.h → src/arch/arm/include/armv4/arch/mmio.h
@@ -25,8 +25,9 @@
  *  12-Dec-1999	RMK	More cleanups
  *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
  */
-#ifndef __ARCH_IO_H
-#define __ARCH_IO_H
+
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
 
 #include <endian.h>
 #include <stdint.h>
@@ -61,4 +62,4 @@ static inline void write32(void *addr, uint32_t val)
 	*(volatile uint32_t *)addr = val;
 }
 
-#endif	/* __ARCH_IO_H */
+#endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/arm/include/armv7/arch/io.h → src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/io.h → src/arch/arm/include/armv7/arch/mmio.h
@@ -25,8 +25,9 @@
  *  12-Dec-1999	RMK	More cleanups
  *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
  */
-#ifndef __ARCH_IO_H
-#define __ARCH_IO_H
+
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
 
 #include <arch/cache.h>		/* for dmb() */
 #include <endian.h>
@@ -71,4 +72,4 @@ static inline void write32(void *addr, uint32_t val)
 	dmb();
 }
 
-#endif	/* __ARCH_IO_H */
+#endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
@@ -28,14 +28,14 @@ void bootmem_arch_add_ranges(void)
 {
 	DECLARE_OPTIONAL_REGION(ttb_subtables);
 
-	bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE);
-	bootmem_add_range((uintptr_t)_ttb_subtables, _ttb_subtables_size,
+	bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
+	bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
 			  BM_MEM_RAMSTAGE);
 
 	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
-			  _postram_cbfs_cache_size, BM_MEM_RAMSTAGE);
+			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
 }
 
 void lb_arch_add_records(struct lb_header *header)

diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
@@ -50,7 +50,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 	if (prog_locate(&bl31))
 		die("BL31 not found");
 
-	if (!selfload(&bl31))
+	if (!selfload_check(&bl31, BM_MEM_BL31))
 		die("BL31 load failed");
 	bl31_entry = prog_entry(&bl31);
 

diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
@@ -37,4 +37,8 @@
 	REGION(stack, addr, size, 16) \
 	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
 
+#define BL31(addr, size) \
+	REGION(bl31, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, "BL31 size must be divisible by 4K!");
+
 #endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h
@@ -16,16 +16,6 @@
 #ifndef ARCH_ARM64_PCI_OPS_H
 #define ARCH_ARM64_PCI_OPS_H
 
-#include <stdint.h>
-#include <device/pci_type.h>
-
-#ifdef __SIMPLE_DEVICE__
-u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
-u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
-u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
-void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val);
-void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val);
-void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val);
-#endif
+#include <device/pci_mmio_cfg.h>
 
 #endif
diff --git a/src/arch/arm64/include/armv8/arch/io.h → src/arch/arm64/include/armv8/arch/mmio.h b/src/arch/arm64/include/armv8/arch/io.h → src/arch/arm64/include/armv8/arch/mmio.h
@@ -25,8 +25,9 @@
  *  12-Dec-1999	RMK	More cleanups
  *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
  */
-#ifndef __ARCH_IO_H
-#define __ARCH_IO_H
+
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
 
 #include <endian.h>
 #include <stdint.h>
@@ -85,4 +86,4 @@ static inline void write64(void *addr, uint64_t val)
 	dmb();
 }
 
-#endif	/* __ARCH_IO_H */
+#endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c
@@ -20,18 +20,25 @@
 #include <boot/coreboot_tables.h>
 #include <symbols.h>
 
+DECLARE_OPTIONAL_REGION(bl31);
+
 void arch_write_tables(uintptr_t coreboot_table)
 {
 }
 
 void bootmem_arch_add_ranges(void)
 {
-	bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE);
+	bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
+
+	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
+	    REGION_SIZE(bl31) > 0)
+		bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31),
+				  BM_MEM_BL31);
 
 	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
-			  _postram_cbfs_cache_size, BM_MEM_RAMSTAGE);
+			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
 }
 
 void lb_arch_add_records(struct lb_header *header)

diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c
@@ -111,5 +111,6 @@ void arch_segment_loaded(uintptr_t start, size_t size, int flags)
 {
 	cache_invalidate_all(start, size);
 	if (flags & SEG_FINAL)
-		cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
+		cache_invalidate_all((uintptr_t)_cbfs_cache,
+				     REGION_SIZE(cbfs_cache));
 }
diff --git a/src/arch/mips/include/arch/io.h → src/arch/mips/include/arch/mmio.h b/src/arch/mips/include/arch/io.h → src/arch/mips/include/arch/mmio.h
@@ -17,8 +17,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __MIPS_ARCH_IO_H
-#define __MIPS_ARCH_IO_H
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
 
 #include <types.h>
 #include <arch/cache.h>

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
@@ -86,6 +86,10 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs)
 bootblock-c-ccopts += $(riscv_flags)
 bootblock-S-ccopts += $(riscv_asm_flags)
 
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
+LDFLAGS_bootblock += -m elf32lriscv
+endif #CONFIG_ARCH_RISCV_RV32
+
 endif #CONFIG_ARCH_BOOTBLOCK_RISCV
 
 ################################################################################
@@ -116,6 +120,10 @@ $(objcbfs)/romstage.debug: $$(romstage-objs)
 romstage-c-ccopts += $(riscv_flags)
 romstage-S-ccopts += $(riscv_asm_flags)
 
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
+LDFLAGS_romstage += -m elf32lriscv
+endif #CONFIG_ARCH_RISCV_RV32
+
 endif #CONFIG_ARCH_ROMSTAGE_RISCV
 
 ################################################################################
@@ -161,5 +169,9 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 ramstage-c-ccopts += $(riscv_flags)
 ramstage-S-ccopts += $(riscv_asm_flags)
 
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
+LDFLAGS_ramstage += -m elf32lriscv
+endif #CONFIG_ARCH_RISCV_RV32
+
 endif #CONFIG_ARCH_RAMSTAGE_RISCV
 endif #CONFIG_ARCH_RISCV
diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/mmio.h>
 #include <arch/encoding.h>
 #include <console/console.h>
 #include <stddef.h>

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
@@ -16,6 +16,7 @@
  */
 
 #include <arch/encoding.h>
+#include <bits.h>
 #include <mcall.h>
 
 .section ".text._start", "ax", %progbits
@@ -44,7 +45,7 @@ _start:
 	slli t1, a0, RISCV_PGSHIFT
 	add  t0, t0, t1
 	li   t1, 0xDEADBEEF
-	sd   t1, 0(t0)
+	STORE t1, 0(t0)
 	li   t1, RISCV_PGSIZE - HLS_SIZE
 	add  sp, t0, t1
 

diff --git a/src/arch/riscv/include/arch/io.h → src/arch/riscv/include/arch/mmio.h b/src/arch/riscv/include/arch/io.h → src/arch/riscv/include/arch/mmio.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
 
 #include <endian.h>
 #include <stdint.h>
@@ -57,4 +57,4 @@ static __always_inline void write64(volatile void *addr, uint64_t value)
 	*((volatile uint64_t *)(addr)) = value;
 }
 
-#endif
+#endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h
@@ -21,7 +21,7 @@
 #define barrier() { asm volatile ("fence" ::: "memory"); }
 
 typedef struct {
-	volatile atomic_t lock;
+	atomic_t lock;
 } spinlock_t;
 
 static inline void spinlock_lock(spinlock_t *lock)

diff --git a/src/arch/riscv/include/bits.h b/src/arch/riscv/include/bits.h
@@ -47,10 +47,19 @@
 #define STR(x) XSTR(x)
 #define XSTR(x) #x
 
-# define SLL32    sllw
-# define STORE    sd
-# define LOAD     ld
-# define LOG_REGBYTES 3
+#if __riscv_xlen == 64
+#define SLL32 sllw
+#define STORE sd
+#define LOAD ld
+#define LWU lwu
+#define LOG_REGBYTES 3
+#else
+#define SLL32 sll
+#define STORE sw
+#define LOAD lw
+#define LWU lw
+#define LOG_REGBYTES 2
+#endif
 
 #define REGBYTES (1 << LOG_REGBYTES)
 

diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
@@ -18,14 +18,21 @@
 
 // NOTE: this is the size of hls_t below. A static_assert would be
 // nice to have.
+#if __riscv_xlen == 64
 #define HLS_SIZE 88
+#endif
+
+#if __riscv_xlen == 32
+#define HLS_SIZE 52
+#endif
 
 /* We save 37 registers, currently. */
 #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
 
 #ifndef __ASSEMBLER__
 
 #include <arch/encoding.h>
+#include <arch/smp/atomic.h>
 #include <stdint.h>
 
 typedef struct {
@@ -38,8 +45,8 @@ typedef struct {
 struct blocker {
 	void *arg;
 	void (*fn)(void *arg);
-	uint32_t sync_a;
-	uint32_t sync_b;
+	atomic_t sync_a;
+	atomic_t sync_b;
 };
 
 typedef struct {

diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
@@ -44,7 +44,7 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode)
 	write_csr(mepc, doit);
 	asm volatile(
 		"mv a0, %0\n\t"
-		"mv a1, %0\n\t"
+		"mv a1, %1\n\t"
 		"mret" ::"r"(hart_id),
 		"r"(fdt)
 		: "a0", "a1");

diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S
@@ -14,6 +14,7 @@
  */
 
 #include <arch/encoding.h>
+#include <bits.h>
 #include <mcall.h>
 
 .section ".text._start", "ax", %progbits
@@ -27,7 +28,7 @@ _start:
 	slli t1, a0, RISCV_PGSHIFT
 	add  t0, t0, t1
 	li   t1, 0xDEADBEEF
-	sd   t1, 0(t0)
+	STORE t1, 0(t0)
 	li   t1, RISCV_PGSIZE - HLS_SIZE
 	add  sp, t0, t1
 

diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
@@ -32,13 +32,13 @@ void smp_pause(int working_hartid)
 		/* waiting for work hart */
 		do {
 			barrier();
-		} while (SYNCA != 0x01234567);
+		} while (atomic_read(&SYNCA) != 0x01234567);
 
 		clear_csr(mstatus, MSTATUS_MIE);
 		write_csr(mie, MIP_MSIP);
 
 		/* count how many cores enter the halt */
-		__sync_fetch_and_add(&SYNCB, 1);
+		atomic_add(&SYNCB, 1);
 
 		do {
 			barrier();
@@ -49,17 +49,17 @@ void smp_pause(int working_hartid)
 	} else {
 		/* Initialize the counter and
 		 * mark the work hart into smp_pause */
-		SYNCB = 0;
-		SYNCA = 0x01234567;
+		atomic_set(&SYNCB, 0);
+		atomic_set(&SYNCA, 0x01234567);
 
 		/* waiting for other Hart to enter the halt */
 		do {
 			barrier();
-		} while (SYNCB + 1 < CONFIG_MAX_CPUS);
+		} while (atomic_read(&SYNCB) + 1 < CONFIG_MAX_CPUS);
 
 		/* initialize for the next call */
-		SYNCA = 0;
-		SYNCB = 0;
+		atomic_set(&SYNCA, 0);
+		atomic_set(&SYNCB, 0);
 	}
 #undef SYNCA
 #undef SYNCB

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -122,7 +122,7 @@ else
 $(eval $(call early_x86_stage,bootblock,elf64-x86-64))
 endif
 
-bootblock-y += walkcbfs.S
+bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
 
 else # !C_ENVIRONMENT_BOOTBLOCK
 
@@ -235,7 +235,7 @@ romstage-y += memset.c
 romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 romstage-y += postcar_loader.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
-romstage-y += walkcbfs.S
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += walkcbfs.S
 
 romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
 romstage-libs ?=

diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
@@ -8,7 +8,7 @@
  * Copyright (C) 2005-2009 coresystems GmbH
  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
  * Raptor Engineering
- * Copyright (C) 2016-2017 Siemens AG
+ * Copyright (C) 2016-2019 Siemens AG
  *
  * ACPI FADT, FACS, and DSDT table support added by
  * Nick Barker <nick.barker9@btinternet.com>, and those portions
@@ -47,6 +47,8 @@
 #include <cpu/x86/lapic_def.h>
 #include <cpu/cpu.h>
 #include <cbfs.h>
+#include <version.h>
+#include <commonlib/sort.h>
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -148,7 +150,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 unsigned long acpi_create_madt_lapics(unsigned long current)
 {
 	struct device *cpu;
-	int index = 0;
+	int index, apic_ids[CONFIG_MAX_CPUS], num_cpus = 0;
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
@@ -157,9 +159,14 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 		}
 		if (!cpu->enabled)
 			continue;
+		if (num_cpus >= ARRAY_SIZE(apic_ids))
+			break;
+		apic_ids[num_cpus++] = cpu->path.apic.apic_id;
+	}
+	bubblesort(apic_ids, num_cpus, NUM_ASCENDING);
+	for (index = 0; index < num_cpus; index++) {
 		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
-				index, cpu->path.apic.apic_id);
-		index++;
+				index, apic_ids[index]);
 	}
 
 	return current;
@@ -216,6 +223,7 @@ void acpi_create_madt(acpi_madt_t *madt)
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_madt_t);
 	header->revision = get_acpi_table_revision(MADT);
 
@@ -244,6 +252,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_mcfg_t);
 	header->revision = get_acpi_table_revision(MCFG);
 
@@ -297,6 +306,7 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa)
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_tcpa_t);
 	header->revision = get_acpi_table_revision(TCPA);
 
@@ -355,6 +365,7 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2)
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_tpm2_t);
 	header->revision = get_acpi_table_revision(TPM2);
 
@@ -409,7 +420,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
 	ssdt->oem_revision = 42;
 	memcpy(&ssdt->asl_compiler_id, ASLC, 4);
-	ssdt->asl_compiler_revision = 42;
+	ssdt->asl_compiler_revision = asl_revision;
 	ssdt->length = sizeof(acpi_header_t);
 
 	acpigen_set_current((char *) current);
@@ -474,6 +485,7 @@ void acpi_create_srat(acpi_srat_t *srat,
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_srat_t);
 	header->revision = get_acpi_table_revision(SRAT);
 
@@ -500,6 +512,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_dmar_t);
 	header->revision = get_acpi_table_revision(DMAR);
 
@@ -633,6 +646,7 @@ void acpi_create_slit(acpi_slit_t *slit,
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_slit_t);
 	header->revision = get_acpi_table_revision(SLIT);
 
@@ -657,6 +671,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_hpet_t);
 	header->revision = get_acpi_table_revision(HPET);
 
@@ -690,6 +705,7 @@ void acpi_create_vfct(struct device *device,
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(struct acpi_vfct);
 	header->revision = get_acpi_table_revision(VFCT);
 
@@ -715,6 +731,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_ivrs_t);
 	header->revision = get_acpi_table_revision(IVRS);
 
@@ -766,6 +783,7 @@ void acpi_create_dbg2(acpi_dbg2_header_t *dbg2,
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = asl_revision;
 
 	/* One debug device defined */
 	dbg2->devices_offset = sizeof(acpi_dbg2_header_t);
@@ -885,6 +903,7 @@ static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id)
 	memcpy(header->oem_table_id, oem_table_id, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_rsdt_t);
 	header->revision = get_acpi_table_revision(RSDT);
 
@@ -904,6 +923,7 @@ static void acpi_write_xsdt(acpi_xsdt_t *xsdt, char *oem_id, char *oem_table_id)
 	memcpy(header->oem_table_id, oem_table_id, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
+	header->asl_compiler_revision = asl_revision;
 	header->length = sizeof(acpi_xsdt_t);
 	header->revision = get_acpi_table_revision(XSDT);
 
@@ -1014,6 +1034,7 @@ void acpi_write_hest(acpi_hest_t *hest,
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = asl_revision;
 	header->length += sizeof(acpi_hest_t);
 	header->revision = get_acpi_table_revision(HEST);
 
@@ -1034,6 +1055,7 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length)
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = asl_revision;
 	header->length += sizeof(acpi_bert_t);
 	header->revision = get_acpi_table_revision(BERT);
 
@@ -1056,7 +1078,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
+	header->asl_compiler_revision = asl_revision;
 
 	fadt->firmware_ctrl = (unsigned long) facs;
 	fadt->dsdt = (unsigned long) dsdt;
@@ -1066,8 +1088,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->x_dsdt_l = (unsigned long)dsdt;
 	fadt->x_dsdt_h = 0;
 
-	if (IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP))
+	if (IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE) ||
+	    IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP))
 		fadt->preferred_pm_profile = PM_MOBILE;
+	else if (IS_ENABLED(CONFIG_SYSTEM_TYPE_DETACHABLE) ||
+		 IS_ENABLED(CONFIG_SYSTEM_TYPE_TABLET))
+		fadt->preferred_pm_profile = PM_TABLET;
 	else
 		fadt->preferred_pm_profile = PM_DESKTOP;
 
@@ -1368,37 +1394,37 @@ int get_acpi_table_revision(enum acpi_tables table)
 	switch (table) {
 	case FADT:
 		return ACPI_FADT_REV_ACPI_3_0;
-	case MADT: /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+	case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */
 		return 2;
 	case MCFG:
 		return 1;
 	case TCPA:
 		return 2;
 	case TPM2:
 		return 4;
-	case SSDT: /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */
+	case SSDT: /* ACPI 3.0 upto 6.3: 2 */
 		return 2;
-	case SRAT:  /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */
+	case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */
 		return 1; /* TODO Should probably be upgraded to 2 */
 	case DMAR:
 		return 1;
-	case SLIT:  /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+	case SLIT: /* ACPI 2.0 upto 6.3: 1 */
 		return 1;
 	case HPET: /* Currently 1. Table added in ACPI 2.0. */
 		return 1;
-	case VFCT:  /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+	case VFCT: /* ACPI 2.0/3.0/4.0: 1 */
 		return 1;
 	case IVRS:
 		return IVRS_FORMAT_FIXED;
 	case DBG2:
 		return 0;
-	case FACS: /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
+	case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */
 		return 1;
-	case RSDT: /* ACPI 1.0/2.0/3.0/4.0: 1 */
+	case RSDT: /* ACPI 1.0 upto 6.3: 1 */
 		return 1;
-	case XSDT: /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */
+	case XSDT: /* ACPI 2.0 upto 6.3: 1 */
 		return 1;
-	case RSDP:  /* ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2. */
+	case RSDP: /* ACPI 2.0 upto 6.3: 2 */
 		return 2;
 	case HEST:
 		return 1;

diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
@@ -632,7 +632,7 @@ static void acpi_dp_free(struct acpi_dp *dp)
 void acpi_dp_write(struct acpi_dp *table)
 {
 	struct acpi_dp *dp, *prop;
-	char *dp_count, *prop_count;
+	char *dp_count, *prop_count = NULL;
 	int child_count = 0;
 
 	if (!table || table->type != ACPI_DP_TYPE_TABLE)
@@ -644,32 +644,42 @@ void acpi_dp_write(struct acpi_dp *table)
 	/* Device Property list starts with the next entry */
 	prop = table->next;
 
-	/* Package (DP), default to 2 elements (assuming no children) */
-	dp_count = acpigen_write_package(2);
-
-	/* ToUUID (ACPI_DP_UUID) */
-	acpigen_write_uuid(ACPI_DP_UUID);
-
-	/* Package (PROP), element count determined as it is populated */
-	prop_count = acpigen_write_package(0);
+	/* Package (DP), default to assuming no properties or children */
+	dp_count = acpigen_write_package(0);
 
 	/* Print base properties */
 	for (dp = prop; dp; dp = dp->next) {
 		if (dp->type == ACPI_DP_TYPE_CHILD) {
 			child_count++;
 		} else {
+			/*
+			 * The UUID and package is only added when
+			 * we come across the first property.  This
+			 * is to avoid creating a zero-length package
+			 * in situations where there are only children.
+			 */
+			if (!prop_count) {
+				*dp_count += 2;
+				/* ToUUID (ACPI_DP_UUID) */
+				acpigen_write_uuid(ACPI_DP_UUID);
+				/*
+				 * Package (PROP), element count determined as
+				 * it is populated
+				 */
+				prop_count = acpigen_write_package(0);
+			}
 			(*prop_count)++;
 			acpi_dp_write_property(dp);
 		}
 	}
-
-	/* Package (PROP) length */
-	acpigen_pop_len();
+	if (prop_count) {
+		/* Package (PROP) length, if a package was written */
+		acpigen_pop_len();
+	}
 
 	if (child_count) {
-		/* Update DP package count to 4 */
-		*dp_count = 4;
-
+		/* Update DP package count to 2 or 4 */
+		*dp_count += 2;
 		/* ToUUID (ACPI_DP_CHILD_UUID) */
 		acpigen_write_uuid(ACPI_DP_CHILD_UUID);
 
@@ -679,7 +689,7 @@ void acpi_dp_write(struct acpi_dp *table)
 		for (dp = prop; dp; dp = dp->next)
 			if (dp->type == ACPI_DP_TYPE_CHILD)
 				acpi_dp_write_property(dp);
-
+		/* Package (CHILD) length */
 		acpigen_pop_len();
 	}
 

diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
@@ -172,7 +172,8 @@ void acpi_prepare_resume_backup(void)
 	if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
 		return;
 
-	backup_create_or_update(NULL, (uintptr_t)_program, _program_size);
+	backup_create_or_update(NULL, (uintptr_t)_program,
+				REGION_SIZE(program));
 }
 
 #define WAKEUP_BASE 0x600

diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
@@ -580,14 +580,12 @@ void acpigen_write_empty_PTC(void)
 	})
 */
 	acpi_addr_t addr = {
-		.space_id   = ACPI_ADDRESS_SPACE_FIXED,
-		.bit_width  = 0,
-		.bit_offset = 0,
-		{
-			.resv       = 0
-		},
-		.addrl      = 0,
-		.addrh      = 0,
+		.space_id    = ACPI_ADDRESS_SPACE_FIXED,
+		.bit_width   = 0,
+		.bit_offset  = 0,
+		.access_size = 0,
+		.addrl       = 0,
+		.addrh       = 0,
 	};
 
 	acpigen_write_name("_PTC");
@@ -845,7 +843,7 @@ static void acpigen_write_register(const acpi_addr_t *addr)
 	acpigen_emit_byte(addr->space_id);	/* Address Space ID */
 	acpigen_emit_byte(addr->bit_width);	/* Register Bit Width */
 	acpigen_emit_byte(addr->bit_offset);	/* Register Bit Offset */
-	acpigen_emit_byte(addr->resv);		/* Register Access Size */
+	acpigen_emit_byte(addr->access_size);	/* Register Access Size */
 	acpigen_emit_dword(addr->addrl);	/* Register Address Low */
 	acpigen_emit_dword(addr->addrh);	/* Register Address High */
 }
@@ -1261,7 +1259,9 @@ void acpigen_write_pld(const struct acpi_pld *pld)
 		return;
 
 	acpigen_write_name("_PLD");
+	acpigen_write_package(1);
 	acpigen_write_byte_buffer(buf, ARRAY_SIZE(buf));
+	acpigen_pop_len();
 }
 
 void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *),

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -26,9 +26,9 @@
 	.  += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
 	_epagetables = . ;
 #endif
-	/* Vboot work buffer is completely volatile outside of verstage and
-	 * romstage. Appropriate code needs to handle the transition. */
-#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)
+	/* Vboot work buffer only needs to be available when verified boot
+	 * starts in bootblock. */
+#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)
 	VBOOT2_WORK(., 16K)
 #endif
 	/* Stack for CAR stages. Since it persists across all stages that
@@ -61,11 +61,6 @@
 	 * to reside in the migrated area (between _car_relocatable_data_start
 	 * and _car_relocatable_data_end). */
 	TIMESTAMP(., 0x200)
-#if IS_ENABLED(CONFIG_COMMONLIB_STORAGE)
-	_car_drivers_storage_start = .;
-	. += 256;
-	_car_drivers_storage_end = .;
-#endif
 	_car_ehci_dbg_info_start = .;
 	/* Reserve sizeof(struct ehci_dbg_info). */
         . += 80;
@@ -90,6 +85,14 @@
 	_car_global_end = .;
 	_car_relocatable_data_end = .;
 
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
+    !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+	. = ABSOLUTE(0xff7e1000);
+	_mrc_pool = .;
+	. += 0x5000;
+	_emrc_pool = .;
+#endif
+
 #if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
 	_car_stack_end = _car_region_end;

diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
@@ -15,7 +15,6 @@
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
-#include <arch/io.h>
 #include <string.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/lapic.h>

diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c
@@ -16,7 +16,6 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <arch/io.h>
 #include <arch/acpi.h>
 #include <arch/ebda.h>
 #include <commonlib/endian.h>

diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S
@@ -21,11 +21,15 @@ gdt_init:
 .previous
 	.align	4
 .globl gdtptr
-gdt:
 gdtptr:
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
-	.word	0
+
+	.align	4
+gdt:
+	/* selgdt 0, unused */
+	.word	0x0000, 0x0000		/* dummy */
+	.byte	0x00, 0x00, 0x00, 0x00
 
 	/* selgdt 0x08, flat code segment */
 	.word	0xffff, 0x0000

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
@@ -77,43 +77,33 @@ enum coreboot_acpi_ids {
 	COREBOOT_ACPI_ID_MAX		= 0xFFFF, /* BOOTFFFF */
 };
 
-/* Table 5-30 DESCRIPTION_HEADER Signatures for tables defined by ACPI 6.2a
- *  Additional tables mssing in 5-30:  MADT, RSDP, VFCT, NHLT
- */
 enum acpi_tables {
-	APIC, BERT, BGRT, CPEP, DSDT, ECDT, EINJ, ERST, FACP, FADT, FACS,
-	FPDT, GTDT, HEST, MSCT, MPST, NFIT, OEMX, PCCT, PMTT, PSDT, RASF,
-	RSDT, SBST, SDEV, SLIT, SRAT, SSDT, XSDT, BOOT, CSRT, DBG2, DBGP,
-	DMAR, DPPT, DRTM, ETDT, HPET, IBFT, IORT, IVRS, LPIT, MCFG, MCHI,
-	MSDM, SDEI, SLIC, SPCR, SPMI, STAO, TCPA, TPM2, WAET, WDAT, WDRT,
-	WPBT, WSMT, XENV, MADT, RSDP, VFCT, NHLT
+	/* Tables defined by ACPI and used by coreboot */
+	BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG,
+	RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT,
+	/* Additional proprietary tables used by coreboot */
+	VFCT, NHLT
 };
 
 /* RSDP (Root System Description Pointer) */
 typedef struct acpi_rsdp {
 	char  signature[8];	/* RSDP signature */
 	u8    checksum;		/* Checksum of the first 20 bytes */
 	char  oem_id[6];	/* OEM ID */
-	u8    revision;		/* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0/6.2a */
+	u8    revision;		/* RSDP revision */
 	u32   rsdt_address;	/* Physical address of RSDT (32 bits) */
 	u32   length;		/* Total RSDP length (incl. extended part) */
 	u64   xsdt_address;	/* Physical address of XSDT (64 bits) */
 	u8    ext_checksum;	/* Checksum of the whole table */
 	u8    reserved[3];
 } __packed acpi_rsdp_t;
-/* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum. */
 
 /* GAS (Generic Address Structure) */
 typedef struct acpi_gen_regaddr {
 	u8  space_id;		/* Address space ID */
 	u8  bit_width;		/* Register size in bits */
 	u8  bit_offset;		/* Register bit offset */
-	union {
-		u8  resv;		/* Reserved in ACPI 2.0 - 2.0b */
-		u8  access_size;	/* Access size in
-					 * ACPI 2.0c/3.0/4.0/5.0/6.2a
-					 */
-	};
+	u8  access_size;	/* Access size since ACPI 2.0c */
 	u32 addrl;		/* Register address, low 32 bits */
 	u32 addrh;		/* Register address, high 32 bits */
 } __packed acpi_addr_t;
@@ -488,11 +478,7 @@ typedef struct acpi_fadt {
 	struct acpi_table_header header;
 	u32 firmware_ctrl;
 	u32 dsdt;
-	u8 model;	/* Eliminated in ACPI 2.0. Platforms should set
-			 * this field to zero but field values of one
-			 * are also allowed to maintain compatibility
-			 * with ACPI 1.0.
-			 */
+	u8 reserved;	/* Should be 0 */
 	u8 preferred_pm_profile;
 	u16 sci_int;
 	u32 smi_cmd;
@@ -582,7 +568,7 @@ typedef struct acpi_fadt {
 /* Bits 20-31: reserved ACPI 3.0 & 4.0 */
 #define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
 #define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
-/* bits 22-31: reserved ACPI 5.0/6.2a */
+/* bits 22-31: reserved since ACPI 5.0 */
 
 /* FADT Boot Architecture Flags */
 #define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
@@ -596,7 +582,7 @@ typedef struct acpi_fadt {
 /* FADT ARM Boot Architecture Flags */
 #define ACPI_FADT_ARM_PSCI_COMPLIANT	(1 << 0)
 #define ACPI_FADT_ARM_PSCI_USE_HVC	(1 << 1)
-/* bits 2-16: reserved ACPI 6.2a */
+/* bits 2-16: reserved since ACPI 5.1 */
 
 /* FADT Preferred Power Management Profile */
 enum acpi_preferred_pm_profiles {
@@ -608,7 +594,7 @@ enum acpi_preferred_pm_profiles {
 	PM_SOHO_SERVER		= 5,
 	PM_APPLIANCE_PC		= 6,
 	PM_PERFORMANCE_SERVER	= 7,
-	PM_TABLET		= 8,	/* ACPI 5.0/6.2a */
+	PM_TABLET		= 8,	/* ACPI 5.0 & greater */
 };
 
 /* FACS (Firmware ACPI Control Structure) */
@@ -621,10 +607,10 @@ typedef struct acpi_facs {
 	u32 flags;				/* FACS flags */
 	u32 x_firmware_waking_vector_l;		/* X FW waking vector, low */
 	u32 x_firmware_waking_vector_h;		/* X FW waking vector, high */
-	u8 version;				/* ACPI 6.2-A: 2 */
-	u8 resv1[3];				/* ACPI 6.2-A: 0 */
+	u8 version;				/* FACS version */
+	u8 resv1[3];				/* This value is 0 */
 	u32 ospm_flags;				/* 64BIT_WAKE_F */
-	u8 resv2[24];				/* ACPI 6.2-A: 0 */
+	u8 resv2[24];				/* This value is 0 */
 } __packed acpi_facs_t;
 
 /* FACS flags */
@@ -682,7 +668,7 @@ typedef struct acpi_bert {
 	u64 error_region;
 } __packed acpi_bert_t;
 
-/* Generic Error Data Entry (ACPI spec v6.2-A, table 382) */
+/* Generic Error Data Entry */
 typedef struct acpi_hest_generic_data {
 	guid_t section_type;
 	u32 error_severity;
@@ -695,7 +681,7 @@ typedef struct acpi_hest_generic_data {
 	/* error data */
 } __packed acpi_hest_generic_data_t;
 
-/* Generic Error Data Entry (ACPI spec v6.2-A, table 382) */
+/* Generic Error Data Entry v300 */
 typedef struct acpi_hest_generic_data_v300 {
 	guid_t section_type;
 	u32 error_severity;
@@ -721,7 +707,7 @@ typedef struct acpi_hest_generic_data_v300 {
 #define ACPI_GENERROR_VALID_FRUID_TEXT		BIT(1)
 #define ACPI_GENERROR_VALID_TIMESTAMP		BIT(2)
 
-/* Generic Error Status Block (ACPI spec v6.2-A, table 381) */
+/* Generic Error Status Block */
 typedef struct acpi_generic_error_status {
 	u32 block_status;
 	u32 raw_data_offset;	/* must follow any generic entries */
@@ -759,7 +745,6 @@ typedef struct acpi_tstate {
 
 /* Port types for ACPI _UPC object */
 enum acpi_upc_type {
-	/* These types are defined in ACPI 6.2 section 9.14 */
 	UPC_TYPE_A,
 	UPC_TYPE_MINI_AB,
 	UPC_TYPE_EXPRESSCARD,

diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
@@ -11,12 +11,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
+#ifndef __ARCH_IO_H__
+#define __ARCH_IO_H__
 
-#include <endian.h>
 #include <stdint.h>
-#include <device/pci_type.h>
 
 /*
  * This file contains the definitions for the x86 IO instructions
@@ -151,265 +149,4 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
 		);
 }
 
-static __always_inline uint8_t read8(
-	const volatile void *addr)
-{
-	return *((volatile uint8_t *)(addr));
-}
-
-static __always_inline uint16_t read16(
-	const volatile void *addr)
-{
-	return *((volatile uint16_t *)(addr));
-}
-
-static __always_inline uint32_t read32(
-	const volatile void *addr)
-{
-	return *((volatile uint32_t *)(addr));
-}
-
-#ifndef __ROMCC__
-static __always_inline uint64_t read64(
-	const volatile void *addr)
-{
-	return *((volatile uint64_t *)(addr));
-}
-#endif
-
-static __always_inline void write8(volatile void *addr,
-	uint8_t value)
-{
-	*((volatile uint8_t *)(addr)) = value;
-}
-
-static __always_inline void write16(volatile void *addr,
-	uint16_t value)
-{
-	*((volatile uint16_t *)(addr)) = value;
-}
-
-static __always_inline void write32(volatile void *addr,
-	uint32_t value)
-{
-	*((volatile uint32_t *)(addr)) = value;
-}
-
-#ifndef __ROMCC__
-static __always_inline void write64(volatile void *addr,
-	uint64_t value)
-{
-	*((volatile uint64_t *)(addr)) = value;
-}
-#endif
-
-/* Conflicts with definition in lib.h */
-#if defined(__ROMCC__)
-static inline int log2(u32 value)
-{
-	unsigned int r = 0;
-	__asm__ volatile (
-		"bsrl %1, %0\n\t"
-		"jnz 1f\n\t"
-		"movl $-1, %0\n\t"
-		"1:\n\t"
-		: "=r" (r) : "r" (value));
-	return r;
-
-}
-
-static inline int __ffs(u32 value)
-{
-	unsigned int r = 0;
-	__asm__ volatile (
-		"bsfl %1, %0\n\t"
-		"jnz 1f\n\t"
-		"movl $-1, %0\n\t"
-		"1:\n\t"
-		: "=r" (r) : "r" (value));
-	return r;
-
-}
-#endif
-
-#ifdef __SIMPLE_DEVICE__
-
-#define PCI_DEV(SEGBUS, DEV, FN) ( \
-	(((SEGBUS) & 0xFFF) << 20) | \
-	(((DEV) & 0x1F) << 15) | \
-	(((FN)  & 0x07) << 12))
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
-	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-
-#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-
-/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write
- * memory above 4G, We don't need to set %fs, and %gs anymore
- * Before that We need to use %gs, and leave %fs to other RAM access
- */
-
-#include <arch/pci_io_cfg.h>
-#include <arch/pci_mmio_cfg.h>
-
-static __always_inline
-uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where)
-{
-	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
-		return pci_mmio_read_config8(dev, where);
-	else
-		return pci_io_read_config8(dev, where);
-}
-
-static __always_inline
-uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where)
-{
-	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
-		return pci_mmio_read_config16(dev, where);
-	else
-		return pci_io_read_config16(dev, where);
-}
-
-static __always_inline
-uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where)
-{
-	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
-		return pci_mmio_read_config32(dev, where);
-	else
-		return pci_io_read_config32(dev, where);
-}
-
-static __always_inline
-void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
-{
-	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
-		pci_mmio_write_config8(dev, where, value);
-	else
-		pci_io_write_config8(dev, where, value);
-}
-
-static __always_inline
-void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
-{
-	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
-		pci_mmio_write_config16(dev, where, value);
-	else
-		pci_io_write_config16(dev, where, value);
-}
-
-static __always_inline
-void pci_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
-{
-	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
-		pci_mmio_write_config32(dev, where, value);
-	else
-		pci_io_write_config32(dev, where, value);
-}
-
-#define PCI_DEV_INVALID (0xffffffffU)
-static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id,
-	pci_devfn_t dev)
-{
-	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_io_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
-static inline pci_devfn_t pci_locate_device(unsigned int pci_id,
-	pci_devfn_t dev)
-{
-	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
-static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id,
-	unsigned int bus)
-{
-	pci_devfn_t dev, last;
-
-	dev = PCI_DEV(bus, 0, 0);
-	last = PCI_DEV(bus, 31, 7);
-
-	for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
-/* Generic functions for pnp devices */
-static __always_inline void pnp_write_config(
-	pnp_devfn_t dev, uint8_t reg, uint8_t value)
-{
-	unsigned int port = dev >> 8;
-	outb(reg, port);
-	outb(value, port + 1);
-}
-
-static __always_inline uint8_t pnp_read_config(
-	pnp_devfn_t dev, uint8_t reg)
-{
-	unsigned int port = dev >> 8;
-	outb(reg, port);
-	return inb(port + 1);
-}
-
-static __always_inline
-void pnp_set_logical_device(pnp_devfn_t dev)
-{
-	unsigned int device = dev & 0xff;
-	pnp_write_config(dev, 0x07, device);
-}
-
-static __always_inline
-void pnp_set_enable(pnp_devfn_t dev, int enable)
-{
-	pnp_write_config(dev, 0x30, enable?0x1:0x0);
-}
-
-static __always_inline
-int pnp_read_enable(pnp_devfn_t dev)
-{
-	return !!pnp_read_config(dev, 0x30);
-}
-
-static __always_inline
-void pnp_set_iobase(pnp_devfn_t dev, unsigned int index, unsigned int iobase)
-{
-	pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
-	pnp_write_config(dev, index + 1, iobase & 0xff);
-}
-
-static __always_inline
-uint16_t pnp_read_iobase(pnp_devfn_t dev, unsigned int index)
-{
-	return ((uint16_t)(pnp_read_config(dev, index)) << 8)
-		| pnp_read_config(dev, index + 1);
-}
-
-static __always_inline
-void pnp_set_irq(pnp_devfn_t dev, unsigned int index, unsigned int irq)
-{
-	pnp_write_config(dev, index, irq);
-}
-
-static __always_inline
-void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq)
-{
-	pnp_write_config(dev, index, drq & 0xff);
-}
-
-#endif /* __SIMPLE_DEVICE__ */
 #endif
diff --git a/src/arch/x86/include/arch/mmio.h b/src/arch/x86/include/arch/mmio.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
+
+#include <stdint.h>
+
+static __always_inline uint8_t read8(
+	const volatile void *addr)
+{
+	return *((volatile uint8_t *)(addr));
+}
+
+static __always_inline uint16_t read16(
+	const volatile void *addr)
+{
+	return *((volatile uint16_t *)(addr));
+}
+
+static __always_inline uint32_t read32(
+	const volatile void *addr)
+{
+	return *((volatile uint32_t *)(addr));
+}
+
+#ifndef __ROMCC__
+static __always_inline uint64_t read64(
+	const volatile void *addr)
+{
+	return *((volatile uint64_t *)(addr));
+}
+#endif
+
+static __always_inline void write8(volatile void *addr,
+	uint8_t value)
+{
+	*((volatile uint8_t *)(addr)) = value;
+}
+
+static __always_inline void write16(volatile void *addr,
+	uint16_t value)
+{
+	*((volatile uint16_t *)(addr)) = value;
+}
+
+static __always_inline void write32(volatile void *addr,
+	uint32_t value)
+{
+	*((volatile uint32_t *)(addr)) = value;
+}
+
+#ifndef __ROMCC__
+static __always_inline void write64(volatile void *addr,
+	uint64_t value)
+{
+	*((volatile uint64_t *)(addr)) = value;
+}
+#endif
+
+#endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h
@@ -14,7 +14,9 @@
 #ifndef _PCI_IO_CFG_H
 #define _PCI_IO_CFG_H
 
+#include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_type.h>
 
 static __always_inline
 unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
@@ -75,4 +77,49 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
 	outl(value, 0xCFC);
 }
 
+#if !IS_ENABLED(CONFIG_MMCONF_SUPPORT)
+
+/* Avoid name collisions as different stages have different signature
+ * for these functions. The _s_ stands for simple, fundamental IO or
+ * MMIO variant.
+ */
+
+static __always_inline
+uint8_t pci_s_read_config8(pci_devfn_t dev, unsigned int where)
+{
+	return pci_io_read_config8(dev, where);
+}
+
+static __always_inline
+uint16_t pci_s_read_config16(pci_devfn_t dev, unsigned int where)
+{
+	return pci_io_read_config16(dev, where);
+}
+
+static __always_inline
+uint32_t pci_s_read_config32(pci_devfn_t dev, unsigned int where)
+{
+	return pci_io_read_config32(dev, where);
+}
+
+static __always_inline
+void pci_s_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
+{
+	pci_io_write_config8(dev, where, value);
+}
+
+static __always_inline
+void pci_s_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
+{
+	pci_io_write_config16(dev, where, value);
+}
+
+static __always_inline
+void pci_s_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
+{
+	pci_io_write_config32(dev, where, value);
+}
+
+#endif
+
 #endif /* _PCI_IO_CFG_H */
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
@@ -14,6 +14,9 @@
 #ifndef ARCH_I386_PCI_OPS_H
 #define ARCH_I386_PCI_OPS_H
 
+#include <arch/pci_io_cfg.h>
+#include <device/pci_mmio_cfg.h>
+
 #ifndef __SIMPLE_DEVICE__
 
 extern const struct pci_bus_operations pci_cf8_conf1;

diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/mmio.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
 #include <cpu/x86/lapic.h>

diff --git a/src/arch/x86/pci_ops.c b/src/arch/x86/pci_ops.c
@@ -16,7 +16,7 @@
 #include <device/device.h>
 #include <device/pci_ops.h>
 
-const struct pci_bus_operations *pci_bus_default_ops(struct device *dev)
+const struct pci_bus_operations *pci_bus_default_ops(void)
 {
 	return &pci_cf8_conf1;
 }