diff --git a/configs/pcengines_apu1.config b/configs/pcengines_apu1.config
diff --git a/configs/pcengines_apu2.config b/configs/pcengines_apu2.config
@@ -17,7 +17,7 @@ CONFIG_COMPILER_GCC=y
 # CONFIG_UTIL_GENPARSER is not set
 CONFIG_COMPRESS_RAMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
-# CONFIG_COLLECT_TIMESTAMPS is not set
+CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_USE_BLOBS=y
 # CONFIG_COVERAGE is not set
 # CONFIG_UPDATE_IMAGE is not set
@@ -158,6 +158,7 @@ CONFIG_BOARD_PCENGINES_APU2=y
 # CONFIG_BOARD_PCENGINES_APU3 is not set
 # CONFIG_BOARD_PCENGINES_APU4 is not set
 # CONFIG_BOARD_PCENGINES_APU5 is not set
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_BINARY_PI_FILE="3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
 # CONFIG_APU2_PINMUX_OFF_C is not set
@@ -606,7 +607,6 @@ CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
 # CONFIG_SEABIOS_REVISION is not set
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_BOOTORDER_MAP_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map"
 CONFIG_SEABIOS_BOOTORDER_DEF_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def"
 CONFIG_SEABIOS_BOOTMENU_KEY_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-key"

diff --git a/configs/pcengines_apu3.config b/configs/pcengines_apu3.config
@@ -17,7 +17,7 @@ CONFIG_COMPILER_GCC=y
 # CONFIG_UTIL_GENPARSER is not set
 CONFIG_COMPRESS_RAMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
-# CONFIG_COLLECT_TIMESTAMPS is not set
+CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_USE_BLOBS=y
 # CONFIG_COVERAGE is not set
 # CONFIG_UPDATE_IMAGE is not set
@@ -158,6 +158,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
 CONFIG_BOARD_PCENGINES_APU3=y
 # CONFIG_BOARD_PCENGINES_APU4 is not set
 # CONFIG_BOARD_PCENGINES_APU5 is not set
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_BINARY_PI_FILE="3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
 # CONFIG_APU2_PINMUX_OFF_C is not set
@@ -606,7 +607,6 @@ CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
 # CONFIG_SEABIOS_REVISION is not set
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_BOOTORDER_MAP_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map"
 CONFIG_SEABIOS_BOOTORDER_DEF_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def"
 CONFIG_SEABIOS_BOOTMENU_KEY_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-key"

diff --git a/configs/pcengines_apu4.config b/configs/pcengines_apu4.config
@@ -17,7 +17,7 @@ CONFIG_COMPILER_GCC=y
 # CONFIG_UTIL_GENPARSER is not set
 CONFIG_COMPRESS_RAMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
-# CONFIG_COLLECT_TIMESTAMPS is not set
+CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_USE_BLOBS=y
 # CONFIG_COVERAGE is not set
 # CONFIG_UPDATE_IMAGE is not set
@@ -158,6 +158,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
 # CONFIG_BOARD_PCENGINES_APU3 is not set
 CONFIG_BOARD_PCENGINES_APU4=y
 # CONFIG_BOARD_PCENGINES_APU5 is not set
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_BINARY_PI_FILE="3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
 # CONFIG_APU2_PINMUX_OFF_C is not set
@@ -606,7 +607,6 @@ CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
 # CONFIG_SEABIOS_REVISION is not set
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_BOOTORDER_MAP_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map"
 CONFIG_SEABIOS_BOOTORDER_DEF_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def"
 CONFIG_SEABIOS_BOOTMENU_KEY_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-key"

diff --git a/configs/pcengines_apu5.config b/configs/pcengines_apu5.config
@@ -17,7 +17,7 @@ CONFIG_COMPILER_GCC=y
 # CONFIG_UTIL_GENPARSER is not set
 CONFIG_COMPRESS_RAMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
-# CONFIG_COLLECT_TIMESTAMPS is not set
+CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_USE_BLOBS=y
 # CONFIG_COVERAGE is not set
 # CONFIG_UPDATE_IMAGE is not set
@@ -158,6 +158,7 @@ CONFIG_MAINBOARD_VERSION="1.0"
 # CONFIG_BOARD_PCENGINES_APU3 is not set
 # CONFIG_BOARD_PCENGINES_APU4 is not set
 CONFIG_BOARD_PCENGINES_APU5=y
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_AGESA_BINARY_PI_FILE="3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
 # CONFIG_APU2_PINMUX_OFF_C is not set
@@ -604,7 +605,6 @@ CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
 # CONFIG_SEABIOS_REVISION is not set
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_BOOTORDER_MAP_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map"
 CONFIG_SEABIOS_BOOTORDER_DEF_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def"
 CONFIG_SEABIOS_BOOTMENU_KEY_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-key"

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -228,7 +228,8 @@ payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG)
 # sortbootorder
 
 payloads/external/sortbootorder/sortbootorder/sortbootorder.elf sortbootorder:
-	$(MAKE) -C payloads/external/sortbootorder
+	$(MAKE) -C payloads/external/sortbootorder \
+		TARGET_APU1=$(CONFIG_BOARD_PCENGINES_APU1)
 
 cbfs-files-$(CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD) += img/setup
 img/setup-file := payloads/external/sortbootorder/sortbootorder/sortbootorder.elf

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.11.0.3"
+	bool "1.11.0.4"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER

diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=rel-1.11.0.3
+TAG-$(CONFIG_SEABIOS_STABLE)=rel-1.11.0.4
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://github.com/pcengines/seabios.git

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
@@ -72,6 +72,7 @@ config PXE_SERIAL_CONSOLE
 
 config PXE_ROM_ID
 	string "network card PCI IDs"
+	default "10ec,8168" if BOARD_PCENGINES_APU1
 	default "8086,157b" if BOARD_PCENGINES_APU2
  	default "8086,1539" if BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
 	BOARD_PCENGINES_APU5

diff --git a/payloads/external/sortbootorder/Makefile b/payloads/external/sortbootorder/Makefile
@@ -1,4 +1,4 @@
-version=4.6.5
+version=4.6.8
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz
@@ -14,7 +14,7 @@ all: sortbootorder
 
 sortbootorder: download
 	echo "    MAKE       sortbootorder     "
-	$(MAKE) -C sortbootorder VERSION=$(branch_name)
+	$(MAKE) -C sortbootorder VERSION=$(branch_name) APU1=$(TARGET_APU1)
 
 download:
 	test -d sortbootorder || { wget $(project_url); \

diff --git a/src/Kconfig b/src/Kconfig
@@ -181,6 +181,7 @@ config INCLUDE_CONFIG_FILE
 
 config COLLECT_TIMESTAMPS
 	bool "Create a table of timestamps collected during boot"
+	default y if ARCH_X86
 	help
 	  Make coreboot create a table of timer-ID/timer-value pairs to
 	  allow measuring time spent at different phases of the boot process.

diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
@@ -46,7 +46,6 @@ void * asmlinkage romstage_main(unsigned long bist)
 
 		platform_once(cb);
 
-		console_init();
 	}
 
 	printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n",
@@ -58,6 +57,7 @@ void * asmlinkage romstage_main(unsigned long bist)
 	agesa_main(cb);
 
 	uintptr_t stack_top = CACHE_TMP_RAMTOP;
+
 	if (cb->s3resume) {
 		if (cbmem_recovery(1)) {
 			printk(BIOS_EMERG, "Unable to recover CBMEM\n");

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
@@ -29,14 +29,16 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
+	select GENERIC_SPD_BIN
+	select PXE
 
 config MAINBOARD_DIR
 	string
 	default pcengines/apu1
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "APU1"
+	default "apu1"
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -67,6 +69,10 @@ config VGA_BIOS
 #	depends on VGA_BIOS
 #	default "rom/video/OntarioGenericVbios.bin"
 
+config SEABIOS_BOOTORDER_FILE
+	string
+	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
+
 config VGA_BIOS_ID
 	string
 	default "1002,9802"

diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
@@ -25,28 +25,15 @@ romstage-y += buildOpts.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
 romstage-y += gpio_ftns.c
+romstage-y += bios_knobs.c
 
+ramstage-y += bios_knobs.c
 ramstage-y += buildOpts.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += OemCustomize.c
 ramstage-y += gpio_ftns.c
 
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-
 # Order of names in SPD_SOURCES is important!
-SPD_SOURCES  = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
-	for f in $+; \
-	  do for c in $$(cat $$f | grep -v ^#); \
-	    do printf $$(printf '\%o' 0x$$c); \
-	  done; \
-	done > $@
+SPD_SOURCES = HYNIX-H5TQ2G83CFR
+SPD_SOURCES += HYNIX-H5TQ4G83MFR
 
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/pcengines/apu1/bios_knobs.c b/src/mainboard/pcengines/apu1/bios_knobs.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+
+ *
+ * Copyright (C) 2017 3mdeb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <cbfs.h>
+#include <commonlib/cbfs.h>
+#include <commonlib/region.h>
+#include <commonlib/cbfs_serialized.h>
+#include "bios_knobs.h"
+
+#define BOOTORDER_FILE "bootorder"
+
+static char * findstr(const char *s, const char *pattern)
+{
+	char *result = (char *) s;
+	char *lpattern = (char *) pattern;
+
+	while (*result && *pattern ) {
+		if ( *lpattern == 0)  // the pattern matches return the pointer
+			return result;
+		if ( *result == 0)  // We're at the end of the file content but don't have a patter match yet
+			return NULL;
+		if (*result == *lpattern ) {
+			// The string matches, simply advance
+			result++;
+			lpattern++;
+		} else {
+			// The string doesn't match restart the pattern
+			result++;
+			lpattern = (char *) pattern;
+		}
+	}
+
+	return NULL;
+}
+
+static u8 check_knob_value(const char *s)
+{
+	const char *boot_file = NULL;
+	size_t boot_file_len = 0;
+	char * token = NULL;
+
+	//
+	// This function locates a file in cbfs, maps it to memory and returns
+	// a void* pointer
+	//
+	boot_file = cbfs_boot_map_with_leak(BOOTORDER_FILE, CBFS_TYPE_RAW, &boot_file_len);
+	if (boot_file == NULL)
+		printk(BIOS_ALERT, "file [%s] not found in CBFS\n", BOOTORDER_FILE);
+	if (boot_file_len < 4096)
+		printk(BIOS_ALERT, "Missing bootorder data.\n");
+	if (boot_file == NULL || boot_file_len < 4096)
+		return -1;
+
+	token = findstr( boot_file, s );
+
+	if (token) {
+		if (*token == '0') return 0;
+		if (*token == '1') return 1;
+	}
+
+	return -1;
+}
+
+bool check_console(void)
+{
+	u8 scon;
+
+	//
+	// Find the serial console item
+	//
+	scon = check_knob_value("scon");
+
+	switch (scon) {
+	case 0:
+		return false;
+		break;
+	case 1:
+		return true;
+		break;
+	default:
+		printk(BIOS_EMERG, "Missing or invalid scon knob, enable console.\n");
+		break;
+	}
+
+	return true;
+}
+
+static bool check_uart(char uart_letter)
+{
+	u8 uarten;
+
+	switch (uart_letter) {
+	case 'c':
+		uarten = check_knob_value("uartc");
+		break;
+	case 'd':
+		uarten = check_knob_value("uartd");
+		break;
+	default:
+		uarten = -1;
+		break;
+	}
+
+	switch (uarten) {
+	case 0:
+		return false;
+		break;
+	case 1:
+		return true;
+		break;
+	default:
+		printk(BIOS_EMERG, "Missing or invalid uart knob, disable port.\n");
+		break;
+	}
+
+	return false;
+}
+
+inline bool check_uartc(void)
+{
+	return check_uart('c');
+}
+
+inline bool check_uartd(void)
+{
+	return check_uart('d');
+}
+
+bool check_ehci0(void)
+{
+	u8 ehci0;
+
+	//
+	// Find the serial console item
+	//
+	ehci0 = check_knob_value("ehcien");
+
+	switch (ehci0) {
+	case 0:
+		return false;
+		break;
+	case 1:
+		return true;
+		break;
+	default:
+		printk(BIOS_EMERG, "Missing or invalid ehci0 knob, enable ehci0.\n");
+		break;
+	}
+
+	return true;
+}
+
+bool check_mpcie2_clk(void)
+{
+	u8 mpcie2_clk;
+
+	//
+	// Find the serial console item
+	//
+	mpcie2_clk = check_knob_value("mpcie2_clk");
+
+	switch (mpcie2_clk) {
+	case 0:
+		return false;
+		break;
+	case 1:
+		return true;
+		break;
+	default:
+		printk(BIOS_EMERG, "Missing or invalid mpcie2_clk knob, forcing CLK of mPCIe2 slot is not enabled .\n");
+		break;
+	}
+
+	return false;
+}
diff --git a/src/mainboard/pcengines/apu1/bios_knobs.h b/src/mainboard/pcengines/apu1/bios_knobs.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+
+ *
+ * Copyright (C) 2017 3mdeb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_KNOBS_H
+#define _BIOS_KNOBS_H
+
+bool check_console(void);
+bool check_uartc(void);
+bool check_uartd(void);
+bool check_ehci0(void);
+bool check_mpcie2_clk(void);
+
+
+#endif
diff --git a/src/mainboard/pcengines/apu1/boot-menu-key b/src/mainboard/pcengines/apu1/boot-menu-key
diff --git a/src/mainboard/pcengines/apu1/boot-menu-message b/src/mainboard/pcengines/apu1/boot-menu-message
@@ -0,0 +1 @@
+Press F10 key now for boot menu, N for PXE boot
diff --git a/src/mainboard/pcengines/apu1/boot-menu-wait b/src/mainboard/pcengines/apu1/boot-menu-wait
diff --git a/src/mainboard/pcengines/apu1/bootorder b/src/mainboard/pcengines/apu1/bootorder
diff --git a/src/mainboard/pcengines/apu1/bootorder_def b/src/mainboard/pcengines/apu1/bootorder_def
@@ -0,0 +1,15 @@
+/pci@i0cf8/usb@10/usb-*@1
+/pci@i0cf8/usb@10/usb-*@2
+/pci@i0cf8/usb@10/usb-*@3
+/pci@i0cf8/usb@10/usb-*@4
+/pci@i0cf8/*@14,7
+/pci@i0cf8/*@11/drive@0/disk@0
+/pci@i0cf8/*@11/drive@1/disk@0
+/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
+/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
+/rom@genroms/pxe.rom
+pxen0
+scon1
+usben1
+uartc1
+uartd1
diff --git a/src/mainboard/pcengines/apu1/bootorder_map b/src/mainboard/pcengines/apu1/bootorder_map
@@ -0,0 +1,10 @@
+a USB 1 / USB 2 SS and HS
+a USB 1 / USB 2 SS and HS
+a USB 1 / USB 2 SS and HS
+a USB 1 / USB 2 SS and HS
+b SDCARD
+c mSATA
+d SATA
+e mPCIe1 SATA1 and SATA2
+e mPCIe1 SATA1 and SATA2
+f iPXE
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
@@ -32,6 +32,7 @@
 #include <northbridge/amd/agesa/family14/pci_devs.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"
+#include "bios_knobs.h"
 
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
@@ -142,19 +143,49 @@ static void config_gpio_mux(void)
 {
 	struct device *uart, *gpio;
 
-	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
-	gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
-	if (uart)
-		uart->enabled = CONFIG_APU1_PINMUX_UART_C;
-	if (gpio)
-		gpio->enabled = CONFIG_APU1_PINMUX_GPIO0;
+	if (check_uartc()) {
+		printk(BIOS_INFO, "UARTC enabled\n");
 
-	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
-	gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
-	if (uart)
-		uart->enabled = CONFIG_APU1_PINMUX_UART_D;
-	if (gpio)
-		gpio->enabled = CONFIG_APU1_PINMUX_GPIO1;
+		uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
+		if (uart)
+			uart->enabled = 1;
+
+		gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
+		if (gpio)
+			gpio->enabled = 0;
+	} else {
+		printk(BIOS_INFO, "UARTC disabled\n");
+
+		uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
+		if (uart)
+			uart->enabled = 0;
+
+		gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
+		if (gpio)
+			gpio->enabled = 1;
+	}
+
+	if (check_uartd()) {
+		printk(BIOS_INFO, "UARTD enabled\n");
+
+		uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
+		if (uart)
+			uart->enabled = 1;
+
+		gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
+		if (gpio)
+			gpio->enabled = 0;
+	} else {
+		printk(BIOS_INFO, "UARTD disabled\n");
+
+		uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
+		if (uart)
+			uart->enabled = 0;
+
+		gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
+		if (gpio)
+			gpio->enabled = 1;
+	}
 }
 
 static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)

diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
@@ -19,8 +19,11 @@
 #include <southbridge/amd/cimx/cimx_util.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
+#include <console/console.h>
 #include "gpio_ftns.h"
 #include "SB800.h"
+#include <build.h>
+#include "bios_knobs.h"
 
 #define SIO_PORT 0x2e
 #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
@@ -62,4 +65,17 @@ void board_BeforeAgesa(struct sysinfo *cb)
 {
 	early_lpc_init();
 	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	console_init();
+
+	bool scon = check_console();
+
+	if(scon) {
+		// sign of life strings
+		printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " "
+			                   CONFIG_MAINBOARD_PART_NUMBER "\n");
+		printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
+		printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
+	}
+
 }
diff --git a/src/mainboard/pcengines/apu1/sercon-port b/src/mainboard/pcengines/apu1/sercon-port
diff --git a/.../pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex → ...ngines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex b/.../pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex → ...ngines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex
diff --git a/.../pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex → ...ngines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex b/.../pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex → ...ngines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex
diff --git a/src/mainboard/pcengines/apu2/bios_knobs.h b/src/mainboard/pcengines/apu2/bios_knobs.h
@@ -26,6 +26,8 @@ bool check_uartc(void);
 bool check_uartd(void);
 bool check_ehci0(void);
 bool check_mpcie2_clk(void);
+int find_knob_index(const char *s, const char *pattern);
+size_t get_bootorder_cbfs_offset(const char *name, uint32_t type);
 
 
 #endif
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
@@ -34,6 +34,10 @@
 #include <spd_bin.h>
 #include <spi_flash.h>
 #include <spi-generic.h>
+#include <boot_device.h>
+#include <cbfs.h>
+#include <commonlib/region.h>
+#include <commonlib/cbfs.h>
 #include "gpio_ftns.h"
 #include "bios_knobs.h"
 
@@ -44,6 +48,8 @@
 #define SEC_REG_SERIAL_ADDR 0x1000
 #define MAX_SERIAL_LEN	    10
 
+#define BOOTORDER_FILE "bootorder"
+
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  * This table is responsible for physically routing the PIC and
@@ -198,6 +204,67 @@ static void config_gpio_mux(void)
 	}
 }
 
+size_t get_bootorder_cbfs_offset(const char *name, uint32_t type)
+{
+	struct region_device rdev;
+	const struct region_device *boot_dev;
+	struct cbfs_props props;
+	struct cbfsf fh;
+
+	boot_dev = boot_device_ro();
+
+	if (boot_dev == NULL) {
+		printk(BIOS_WARNING, "Can't init CBFS boot device\n");
+		return 0;
+	}
+
+	if (cbfs_boot_region_properties(&props)) {
+		printk(BIOS_WARNING, "Can't locate CBFS\n");
+		return 0;
+	}
+
+	if (rdev_chain(&rdev, boot_dev, props.offset, props.size)) {
+		printk(BIOS_WARNING, "Rdev chain failed\n");
+		return 0;
+	}
+
+	if (cbfs_locate(&fh, &rdev, name, &type)) {
+		printk(BIOS_WARNING, "Can't locate file in CBFS\n");
+		return 0;
+	}
+
+	return (size_t) rdev_relative_offset(boot_dev, &fh.data);
+}
+
+int find_knob_index(const char *s, const char *pattern)
+{
+
+	int pattern_index = 0;
+	char *result = (char *) s;
+	char *lpattern = (char *) pattern;
+
+	while (*result && *pattern ) {
+		if ( *lpattern == 0)  // the pattern matches return the pointer
+			return pattern_index;
+		if ( *result == 0)  // We're at the end of the file content but don't have a patter match yet
+			return -1;
+		if (*result == *lpattern ) {
+			// The string matches, simply advance
+			result++;
+			pattern_index++;
+			lpattern++;
+		} else {
+			// The string doesn't match restart the pattern
+			result++;
+			pattern_index++;
+			lpattern = (char *) pattern;
+		}
+	}
+
+	return -1;
+
+}
+
 /**********************************************
  * enable the dedicated function in mainboard.
  **********************************************/
@@ -259,6 +326,91 @@ static void mainboard_final(void *chip_info)
 	//
 	write_gpio(GPIO_58, 1);
 	write_gpio(GPIO_59, 1);
+
+#if CONFIG_BOARD_PCENGINES_APU2 || CONFIG_BOARD_PCENGINES_APU3 || CONFIG_BOARD_PCENGINES_APU4
+	if (!check_console()) {
+
+		//
+		// The console is disabled, check if S1 is pressed and enable if so
+		//
+		if (!read_gpio(GPIO_32)) {
+
+			printk(BIOS_INFO, "S1 PRESSED\n");
+
+			const struct spi_flash *flash = NULL;
+			size_t fsize, offset;
+			char* bootorder_file = NULL;
+			int knob_index;
+			char *bootorder_copy;
+
+			bootorder_file = cbfs_boot_map_with_leak("bootorder", CBFS_TYPE_RAW, &fsize);
+
+			if (bootorder_file == NULL){
+				printk(BIOS_WARNING, "Could not mmap bootorder\n");
+				return;
+			}
+
+			if (fsize & 0xFFF) {
+				printk(BIOS_WARNING,"The bootorder file is not 4k aligned\n");
+				return;
+			}
+
+			offset = get_bootorder_cbfs_offset("bootorder", CBFS_TYPE_RAW);
+
+			if(offset == -1) {
+				printk(BIOS_WARNING,"Failed to retrieve bootorder file offset\n");
+				return;
+			}
+
+			bootorder_copy = (char *)malloc(fsize);
+
+			if(bootorder_copy == NULL) {
+				printk(BIOS_WARNING,"Failed to allocate memory for bootorder\n");
+				return;
+			}
+
+			if(memcpy(bootorder_copy, bootorder_file, fsize) == NULL) {
+				printk(BIOS_WARNING,"Copying bootorder failed\n");
+				free(bootorder_copy);
+				return;
+			}
+
+			knob_index = find_knob_index(bootorder_copy, "scon");
+
+			if(knob_index == -1){
+				printk(BIOS_WARNING,"scon knob not found in bootorder\n");
+				free(bootorder_copy);
+				return;
+			}
+
+			*(bootorder_copy + knob_index) = '1';
+
+			flash = boot_device_spi_flash();
+
+			if (flash == NULL) {
+				printk(BIOS_WARNING, "Can't get boot flash device\n");
+				free(bootorder_copy);
+				return;
+			}
+
+			if (spi_flash_erase(flash, (u32) offset, fsize)) {
+				printk(BIOS_WARNING, "SPI erase failed\n");
+				free(bootorder_copy);
+				return;
+			}
+
+			if (spi_flash_write(flash, offset, fsize, bootorder_copy)) {
+				printk(BIOS_WARNING, "SPI write failed\n");
+				free(bootorder_copy);
+				return;
+			} else {
+				printk(BIOS_INFO, "Bootorder write successed\n");
+			}
+
+			free(bootorder_copy);
+		}
+	}
+#endif
 }
 
 /*

diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
@@ -81,7 +81,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		if(scon) {
 			// sign of life strings
-			printk(BIOS_ALERT, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER " "
+			printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " "
 			                   CONFIG_MAINBOARD_PART_NUMBER "\n");
 			printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
 			printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);

diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c
@@ -35,6 +35,9 @@ static void sata_init(struct device *dev)
 	#define UNLOCK_BIT (1<<0)
 	#define SATA_CAPABILITIES_REG 0xFC
 	#define CFG_CAP_SPM (1<<12)
+	#define SATA_REV_SUBCLASS_REG 0x08
+	#define SUBCLASS_AHCI_MODE 0x60000
+	#define SATA_PROGRAMIF_AHCI 0x100
 
 	volatile u32 *ahci_ptr =
 		(u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
@@ -48,6 +51,11 @@ static void sata_init(struct device *dev)
 	/* set the SATA AHCI mode to allow port expanders */
 	*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
 
+	/* enable AHCI mode */
+	temp = pci_read_config32(dev, SATA_REV_SUBCLASS_REG);
+	temp = (temp & 0xFF0070FF) | SUBCLASS_AHCI_MODE | SATA_PROGRAMIF_AHCI;
+	pci_write_config32(dev, SATA_REV_SUBCLASS_REG, temp);
+
 	/* lock the write-protect */
 	temp = pci_read_config32(dev, MISC_CONTROL_REG);
 	temp &= ~UNLOCK_BIT;
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		Press F10 key now for boot menu, N for PXE boot