diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md
diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md
@@ -3,7 +3,7 @@
 This document describes the preferred C coding style for the
 coreboot project. It is in many ways exactly the same as the Linux
 kernel coding style. In fact, most of this document has been copied from
-the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD)
+the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/plain/Documentation/process/4.Coding.rst)
 
 The guidelines in this file should be seen as a strong suggestion, and
 should overrule personal preference. But they may be ignored in

diff --git a/Documentation/contributing/gerrit_guidelines.md b/Documentation/contributing/gerrit_guidelines.md
@@ -53,7 +53,10 @@ it's implemented, should restart the wait period.
 a recently-introduced issue (build, boot or OS-level compatibility, not
 necessarily identified by coreboot.org facilities). Its commit message
 has to explain what change introduced the problem and the nature of
-the problem so that the emergency need becomes apparent. The change
+the problem so that the emergency need becomes apparent. Avoid stating
+something like "fix build error" in the commit summary, describe what
+the commit does instead, just like any other commit. In addition, it is
+recommended to reference the commit that introduced the issue. The change
 itself should be as limited in scope and impact as possible to make it
 simple to assess the impact. Such a change can be merged early with 3
 Code-Review+2. For emergency fixes that affect a single project (SoC,

diff --git a/Documentation/coreboot_logo.svg b/Documentation/coreboot_logo.svg
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -5,6 +5,11 @@ It is built from Markdown files in the
 [Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
 directory in the source code.
 
+## Spelling of coreboot
+
+The correct spelling of coreboot is completely in lower case characters and in
+one word without a space between the two parts.
+
 ## Purpose of coreboot
 
 coreboot is a project to develop open source boot firmware for various
@@ -191,4 +196,5 @@ Contents:
 * [Project infrastructure & services](infrastructure/index.md)
 * [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
+* [Acronyms & Definitions](acronyms.md)
 * [Documentation License](documentation_license.md)
diff --git a/Documentation/infrastructure/builders.md b/Documentation/infrastructure/builders.md
@@ -41,11 +41,12 @@ can run into "out of storage space" errors.
 #### Current Build Machines
 
 To give an idea of what a suitable build machine might be, currently the
-coreboot project has 4 active jenkins build machines.
+coreboot project has 6 active jenkins build machines.
 
 These times are taken from the week of Feb 21 - Feb 28, 2022
 
 * Congenialbuilder - 128 threads, 256GiB RAM
+  * Coverity Builds, Toolchain builds, Scanbuild-builds
   * Fastest Passing coreboot gerrit build: 6 min, 47 sec
   * Slowest Passing coreboot gerrit build: 14 min
 
@@ -58,9 +59,16 @@ These times are taken from the week of Feb 21 - Feb 28, 2022
   * Slowest Passing coreboot gerrit build: 56 min (No ccache)
 
 * Ultron (9elements) - 48 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 12
+  * Fastest Passing coreboot gerrit build: 12 min
   * Slowest Passing coreboot gerrit build: 58 min
 
+* Bob - 64 threads, 128GiB RAM
+  * Fastest Passing coreboot gerrit build: 7 min
+  * Slowest Passing coreboot gerrit build: 34 min
+
+* Pokeybuilder - 32 Threads, 96GiB RAM
+  * Runs coreboot-checkpatch and other lighter builds
+
 
 ### Jenkins Builds
 
@@ -69,17 +77,28 @@ for a number of different projects - coreboot, flashrom, memtest86+,
 em100, etc.  Many of these have builders for their current master branch
 as well as Gerrit and [Coverity](coverity.md) builds.
 
-You can see all the builds here:
+
+#### Long builds - over 90 minutes on congenialbuilder
+There are a few builds that take a long time even on the fastest
+machines.  These tasks run overnight in the US timezones.
+* coreboot_coverity - 9 to 12 hours
+* coreboot_scanbuild - ~3 hours
+* coreboot_toolchain - ~1 hour 45 minutes
+
+
+#### All builds
+
+You can see all the builds in the main jenkins interface:
 [https://qa.coreboot.org/](https://qa.coreboot.org/)
 
 Most of the time on the builders is taken up by the coreboot master and
 coreboot gerrit builds.
 
-*[coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
+* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
 ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
 
 
-*[coreboot master build](https://qa.coreboot.org/job/coreboot/)
+* [coreboot master build](https://qa.coreboot.org/job/coreboot/)
  ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
 
 

diff --git a/Documentation/infrastructure/services.md b/Documentation/infrastructure/services.md
@@ -16,6 +16,21 @@ all your email addresses you intend to use in the context of coreboot
 development so that commits with your email address in them are associated with
 you properly.
 
+Below is a list of its SSH host keys and fingerprints.
+```Bash
+[review.coreboot.org]:29418 ssh-rsa AAAAB3NzaC1yc2EAAAABIwAAAQEAvNDn8qGHlWM/5ndFltStlg3QTc8xvGOgyjxxZByhMZx8LVE4cfgF38WP3euq0avyFy7gAJNghHorXpYKoOzuQPn2WNi5QhyGsUhg7ZJz9hC7Z2gqxxsZF3E7rku4Uj9sN7hWx9fBngxD4z2tP4y/18FTT5XTMcC3Q2sBCOLM0XVAO5R/nb2GO3d27avy+sanKAFEwJHnZ996IoTlU8JJFyi1Y6g30dC2K75oFgCtzntxf++wvrkkKPa+CFQub8fp20shat9WwX9kXjpRjt/Yv9LgqFCaI5ztJvWXicAmbgghGVzbzz4GoSjjF9cxxJF//KTmNb4iGQqmP3Olm27xuw==
+
+[review.coreboot.org]:29418 ecdsa-sha2-nistp256 AAAAE2VjZHNhLXNoYTItbmlzdHAyNTYAAAAIbmlzdHAyNTYAAABBBBzlwf/bFejt4EEz1QmbNOfK/HN1NtdcefrRs5Gs42uGnIvjxsff+vEF3//jCTvFPadoy3DrPsbQB3ioQAcYppk=
+
+[review.coreboot.org]:29418 ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAIOC3Z32gc+1rJXhKX+SW0vESlXR/h/mhcxd+62B1PWC2
+```
+
+```Bash
+2048 SHA256:WW5prF7YE3MTnkRIxLklr9Gxddj9s5BZKUqWJF5dnTg review.coreboot.org:29418 (RSA)
+256 SHA256:IuLv/DgrBtVn36eMP1zFD0ISAl3IxIoCeiRms6UDhZc review.coreboot.org:29418 (ECDSA)
+256 SHA256:QFZieVHy8dCRl9tDib6qiwELnfa7SVU4ZWJ5VrXoC8k review.coreboot.org:29418 (ED25519)
+```
+
 ### https push access
 When using the https URLs to git repositories, you can push with the "HTTP
 Credentials" you can have Gerrit generate for you on that page. By default,

diff --git a/Documentation/lib/flashmap.md b/Documentation/lib/flashmap.md
@@ -4,7 +4,7 @@
 
 [Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to
 describe partitions in a flash chip. It was added to coreboot to support the
-requirements of Chromium OS firmware but then was also used in other scenarios
+requirements of ChromiumOS firmware but then was also used in other scenarios
 where precise placement of data in flash was necessary, or for data that is
 written to at runtime, as CBFS is considered too fragile for such situations.
 The Flashmap implementation inside coreboot is the de facto standard today.

diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md
@@ -8,8 +8,8 @@ BIOS image to be used across a wide variety of devices which may have key differ
 otherwise similar enough to use the same coreboot build target.
 
 The initial implementation is designed to take advantage of a bitmask returned by the Embedded
-Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware
-image across multiple devices by selecting various options at runtime.  See the Chromium OS
+Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
+image across multiple devices by selecting various options at runtime.  See the ChromiumOS
 [Firmware Config][1] documentation for more information.
 
 This firmware configuration interface differs from the CMOS option interface in that this
@@ -91,7 +91,7 @@ file in CBFS use the value it contains when matching fields and options.
 
 ### Embedded Controller
 
-Google Chrome OS devices support an Embedded Controller interface for reading and writing the
+Google ChromeOS devices support an Embedded Controller interface for reading and writing the
 firmware configuration value, along with other board-specific information.  It is possible for
 coreboot to read this value at boot on systems that support this feature.
 
@@ -101,9 +101,9 @@ possible by enabling the CBFS source and coreboot will look in CBFS first for a
 before asking the embedded controller.
 
 It is also possible to adjust the value in the embedded controller *(after disabling write
-protection)* with the `ectool` command in a Chrome OS environment.
+protection)* with the `ectool` command in a ChromeOS environment.
 
-For more information on the firmware configuration field on Chrome OS devices see the Chromium
+For more information on the firmware configuration field on ChromeOS devices see the Chromium
 documentation for [Firmware Config][1] and [Board Info][2].
 
 [1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md

diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md
@@ -3,7 +3,7 @@
 All Haswell boards supported by coreboot currently require a proprietary
 blob in order to initialise the DRAM and a few other components. The
 blob, named `mrc.bin`, largely consists of Intel's memory reference code
-(MRC), but it has been tailored specifically for Chrome OS. It is just
+(MRC), but it has been tailored specifically for ChromeOS. It is just
 under 200 KiB in size. Another name for `mrc.bin` is the system agent
 binary.
 

diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md
@@ -176,7 +176,6 @@ CMOS, the EC, or in a read/write area of the SPI flash device.
 Select one of the following:
 
 * `VBOOT_VBNV_CMOS`
-* `VBOOT_VBNV_EC`
 * `VBOOT_VBNV_FLASH`
 
 More non-volatile storage features may be found in `security/vboot/Kconfig`.
@@ -329,7 +328,7 @@ Google's Chromebooks have some special features:
 ### Developer Mode
 
 Developer mode allows the user to use coreboot to boot another operating system.
-This may be a another (beta) version of Chrome OS, or another flavor of
+This may be a another (beta) version of ChromeOS, or another flavor of
 GNU/Linux. Use of developer mode does not void the system warranty. Upon entry
 into developer mode, all locally saved data on the system is lost.
 This prevents someone from entering developer mode to subvert the system

diff --git a/Documentation/soc/amd/amdblobs_license.md b/Documentation/soc/amd/amdblobs_license.md
diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md
diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md
diff --git a/Documentation/soc/intel/cse_fw_update/cse_fw_update.md b/Documentation/soc/intel/cse_fw_update/cse_fw_update.md
@@ -8,7 +8,7 @@ power transition flows.
 
 ## Problem Statement
 
-Currently, on Chromium OS Systems, CSE region is not updatable. So, new CSE FW
+Currently, on ChromiumOS Systems, CSE region is not updatable. So, new CSE FW
 versions that are released by Intel to address important functional and security
 bugs post-product launch will not be available to the end-user. Hence, the proposed
 solution allows in-field CSE FW update to propagate those bug fixes

diff --git a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md
@@ -3,7 +3,7 @@ Rebuilding coreboot image generation
 
 Current situation
 -----------------
-Chrome OS (CrOS) probably has the most complex image bundling process in the
+ChromeOS (CrOS) probably has the most complex image bundling process in the
 coreboot ecosystem. To make CrOS features more accessible to the wider
 coreboot community, we want to move these capabilities into upstream
 coreboot’s build system.
@@ -21,7 +21,7 @@ putting more data (eg. the bitmap data, keys) as raw data into other fmap
 regions.
 
 With the recent addition of more files to CBFS, both on the coreboot side
-(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing
+(dsdt, FSP, and so on) and with ChromeOS specifics (eg. more files describing
 boot screens) we either need to expand the scope of bundle\_firmware or move
 the capability to build complex images to upstream coreboot’s build system.
 This document proposes to do the latter and outlines how this could be
@@ -41,14 +41,14 @@ images:
   variable to guarantee success if there’s enough room for the files. While that
   could be added, that becomes more make macro work indistinguishable from magic
   that people fail to understand, break and with good reason complain about
-  to work around such issues, Chrome OS firmware uses a custom tool with even
+  to work around such issues, ChromeOS firmware uses a custom tool with even
   more special cases to finally build the image it needs. If coreboot upstream
   is to support vboot, it should also be powerful enough not to need magic tools
   that only live within downstream projects.
 
 Requirements
 ------------
-A complete Chrome OS coreboot image consists of (depending on the device)
+A complete ChromeOS coreboot image consists of (depending on the device)
 * platform specific data in raw fmap regions (eg IFD, ME firmware),
 * the bootblock (coming from the bootblock),
 * three copies of coreboot, consisting of the stages (verstage, romstage,
@@ -68,7 +68,7 @@ using a yet to be implemented switching scheme based on fmaps) consists of
 * payload plus data (with each of the coreboot copies),
 
 Since a single platform is potentially built with different payload
-configurations (eg. modding a Chromebook to not use the verified Chrome OS
+configurations (eg. modding a Chromebook to not use the verified ChromeOS
 boot scheme), some concerns need to be kept separate:
 * Platform requirements that have nothing to do with the payload or boot schemes
  * IFD, ME, … need to copied to the right place
@@ -111,11 +111,11 @@ Boot method manifest
 --------------------
 The boot method manifest can subdivide the BIOS region, eg. using it directly
 (for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s
-fallback/normal) or in many parts (for Chrome OS, which requires two CBFS
+fallback/normal) or in many parts (for ChromeOS, which requires two CBFS
 regions, one for GBB, several for VPD, …).
 It also specifies which of the file lists specified earlier belong in which
 region (eg. with verstage verifying romstage, verstage needs to be only in
-Chrome OS’ RO region, while romstage belongs in RO and both RW regions).
+ChromeOS’ RO region, while romstage belongs in RO and both RW regions).
 It can also specify a post processing step that is executed before the
 chipset’s.
 
@@ -148,7 +148,7 @@ It specifies an IFD region, an ME, and the BIOS region. After the image is
 built, the entire image needs to be processed (although the tool likely works
 only on a small part of it)
 
-It’s built in a Chrome OS-like configuration (simplified at places to avoid
+It’s built in a ChromeOS-like configuration (simplified at places to avoid
 distracting from the important parts), so it has three CBFS regions, and
 several data regions for its own purpose (similar to GBB, FWID, VPD, …). After
 the regions are filled, one data region must be post-processed to contain

diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md
@@ -2,118 +2,179 @@ Tutorial, part 1: Starting from scratch
 ===========================================
 
 This tutorial will guide you through the process of setting up a working
-coreboot toolchain. In same cases you will find specific instructions for Debian (apt-get),
-Fedora (dnf) and Arch Linux (pacman) based package management systems. Use the
-instructions according to your system.
+coreboot toolchain. In same cases you will find specific instructions
+for Debian (apt-get), Fedora (dnf) and Arch Linux (pacman) based package
+management systems. Use the instructions according to your system.
+
+**Note: Summaries of each of the steps are at the end of the document.**
+
 
 Download, configure, and build coreboot
 ---------------------------------------
 
+
 ### Step 1 - Install tools and libraries needed for coreboot
-    $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
-    $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib
-    $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel patch
+
+Debian based distros:
+`sudo apt-get install -y bison build-essential curl flex git gnat`
+`libncurses5-dev m4 zlib1g-dev`
+
+Arch based distros:
+`sudo pacman -S base-devel curl git gcc-ada ncurses zlib`
+
+Redhat based distros:
+`sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++`
+`ncurses-devel wget zlib-devel patch`
+
 
 ### Step 2 - Download coreboot source tree
-    $ git clone https://review.coreboot.org/coreboot
-    $ cd coreboot
+
+```Bash
+git clone https://review.coreboot.org/coreboot
+cd coreboot
+```
+
+
 
 ### Step 3 - Build the coreboot toolchain
-Please note that this can take a significant amount of time. Use `CPUS=` to
-specify number of `make` jobs to run in parallel.
+
+Please note that this can take a significant amount of time. Use `CPUS=`
+to specify number of `make` jobs to run in parallel.
 
 This will list toolchain options and supported architectures:
 
-    $ make help_toolchain
+```Bash
+make help_toolchain
+```
 
 Here are some examples:
 
-    $ make crossgcc-i386 CPUS=$(nproc)       # build i386 toolchain
-    $ make crossgcc-aarch64 CPUS=$(nproc)    # build Aarch64 toolchain
-    $ make crossgcc-riscv CPUS=$(nproc)      # build RISC-V toolchain
+```Bash
+make crossgcc-i386 CPUS=$(nproc)       # build i386 toolchain
+make crossgcc-aarch64 CPUS=$(nproc)    # build Aarch64 toolchain
+make crossgcc-riscv CPUS=$(nproc)      # build RISC-V toolchain
+```
 
-Note that the i386 toolchain is currently used for all x86 platforms, including
-x86_64.
+Note that the i386 toolchain is currently used for all x86 platforms,
+including x86_64.
+
+Also note that you can possibly use your system toolchain, but the
+results are not reproducible, and may have issues, so this is not
+recommended.  See step 5 to use your system toolchain.
 
-Also note that you can possibly use your system toolchain, but the results are
-not reproducible, and may have issues, so this is not recommended.  See step 5
-to use your system toolchain.
 
 ### Step 4 - Build the payload - coreinfo
-    $ make -C payloads/coreinfo olddefconfig
-    $ make -C payloads/coreinfo
+
+```Bash
+make -C payloads/coreinfo olddefconfig
+make -C payloads/coreinfo
+```
+
 
 ### Step 5 - Configure the build
 
 ##### Configure your mainboard
-    $ make menuconfig
-       select 'Mainboard' menu
-       Beside 'Mainboard vendor' should be '(Emulation)'
-       Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'
-       select < Exit >
+
+```Bash
+make menuconfig
+```
+
+Do the next steps in the menu:
+
+```Text
+select 'Mainboard' menu
+Beside 'Mainboard vendor' should be '(Emulation)'
+Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'
+select < Exit >
+```
+
 These should be the default selections, so if anything else was set, run
 `make distclean` to remove your old config file and start over.
 
 ##### Optionally use your system toolchain (Again, not recommended)
-       select 'General Setup' menu
-       select 'Allow building with any toolchain'
-       select < Exit >
+
+```Text
+select 'General Setup' menu
+select 'Allow building with any toolchain'
+select < Exit >
+```
 
 ##### Select the payload
-       select 'Payload' menu
-       select 'Add a Payload'
-       choose 'An Elf executable payload'
-       select 'Payload path and filename'
-       enter 'payloads/coreinfo/build/coreinfo.elf'
-       select < Exit >
-       select < Exit >
-       select < Yes >
+
+```Text
+select 'Payload' menu
+select 'Add a Payload'
+choose 'An Elf executable payload'
+select 'Payload path and filename'
+enter 'payloads/coreinfo/build/coreinfo.elf'
+select < Exit >
+select < Exit >
+select < Yes >
+```
 
 ##### Check your configuration (optional step):
 
-    $ make savedefconfig
-    $ cat defconfig
+```Bash
+make savedefconfig
+cat defconfig
+```
 
-There should only be two lines (or 3 if you're using the system toolchain):
+There should only be two lines (or 3 if you're using the system
+toolchain):
 
-    CONFIG_PAYLOAD_ELF=y
-    CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
+```Text
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
+```
 
 ### Step 6 - build coreboot
-    $ make
+
+```Bash
+make
+```
 
 At the end of the build, you should see:
 
-    Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)
+`Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)``
+
+This means your build was successful. The output from the build is in
+the build directory. build/coreboot.rom is the full rom file.
 
-This means your build was successful. The output from the build is in the build
-directory. build/coreboot.rom is the full rom file.
 
 Test the image using QEMU
 -------------------------
 
+
 ### Step 7 - Install QEMU
-    $ sudo apt-get install -y qemu
-    $ sudo pacman -S qemu
-    $ sudo dnf install qemu
+
+* Debian: `sudo apt-get install -y qemu`
+* Arch: `sudo pacman -S qemu`
+* Redhat: `sudo dnf install qemu`
+
 
 ### Step 8 - Run QEMU
+
 Start QEMU, and point it to the ROM you just built:
 
-    $ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+```Bash
+qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+```
+
+You should see the serial output of coreboot in the original console
+window, and a new window will appear running the coreinfo payload.
 
-You should see the serial output of coreboot in the original console window, and
-a new window will appear running the coreinfo payload.
 
 Summary
 -------
 
+
 ### Step 1 summary - Install tools and libraries needed for coreboot
+
 Depending on your distribution you have installed the minimum additional
-software requirements to continue with downloading and building coreboot.
-Not every distribution has the tools, that would be required,
-installed by default. In the following we shortly introduce the purpose of the
-installed packages:
+software requirements to continue with downloading and building
+coreboot.  Not every distribution has the tools, that would be required,
+installed by default. In the following we shortly introduce the purpose
+of the installed packages:
 
 * `build-essential` or `base-devel` are the basic tools for building software.
 * `git` is needed to download coreboot from the coreboot git repository.
@@ -122,71 +183,89 @@ installed packages:
 are needed to build the coreboot toolchain. `gcc` and `gnat` have to be
 of the same version.
 
-If you started with a different distribution or package management system you
-might need to install other packages. Most likely they are named slightly
-different. If that is the case for you, we'd like to encourage you to contribute
-to the project and submit a pull request with an update for this documentation
-for your system.
+If you started with a different distribution or package management
+system you might need to install other packages. Most likely they are
+named slightly different. If that is the case for you, we'd like to
+encourage you to contribute to the project and submit a pull request
+with an update for this documentation for your system.
+
 
 ### Step 2 summary - Download coreboot source tree
-This will download a 'read-only' copy of the coreboot tree. This just means
-that if you made changes to the coreboot tree, you couldn't immediately
-contribute them back to the community. To pull a copy of coreboot that would
-allow you to contribute back, you would first need to sign up for an account on
-gerrit.
+
+This will download a 'read-only' copy of the coreboot tree. This just
+means that if you made changes to the coreboot tree, you couldn't
+immediately contribute them back to the community. To pull a copy of
+coreboot that would allow you to contribute back, you would first need
+to sign up for an account on gerrit.
+
 
 ### Step 3 summary - Build the coreboot toolchain.
-This builds one of the coreboot cross-compiler toolchains for X86 platforms.
-Because of the variability of compilers and the other required tools between
-the various operating systems that coreboot can be built on, coreboot supplies
-and uses its own cross-compiler toolchain to build the binaries that end up as
-part of the coreboot ROM. The toolchain provided by the operating system (the
-'host toolchain') is used to build various tools that will run on the local
-system during the build process.
+
+This builds one of the coreboot cross-compiler toolchains for X86
+platforms.  Because of the variability of compilers and the other
+required tools between the various operating systems that coreboot can
+be built on, coreboot supplies and uses its own cross-compiler toolchain
+to build the binaries that end up as part of the coreboot ROM. The
+toolchain provided by the operating system (the 'host toolchain') is
+used to build various tools that will run on the local system during the
+build process.
+
 
 ### Step 4 summary - Build the payload
-To actually do anything useful with coreboot, you need to build a payload to
-include into the rom. The idea behind coreboot is that it does the minimum amount
-possible before passing control of the machine to a payload. There are various
-payloads such as grub or SeaBIOS that are typically used to boot the operating
-system. Instead, we used coreinfo, a small demonstration payload that allows the
-user to look at various things such as memory and the contents of the coreboot
-file system (CBFS) - the pieces that make up the coreboot rom.
+
+To actually do anything useful with coreboot, you need to build a
+payload to include into the rom. The idea behind coreboot is that it
+does the minimum amount possible before passing control of the machine
+to a payload. There are various payloads such as grub or SeaBIOS that
+are typically used to boot the operating system. Instead, we used
+coreinfo, a small demonstration payload that allows the user to look at
+various things such as memory and the contents of the coreboot file
+system (CBFS) - the pieces that make up the coreboot rom.
+
 
 ### Step 5 summary - Configure the build
-This step configures coreboot's build options using the menuconfig interface to
-Kconfig. Kconfig is the same configuration program used by the linux kernel. It
-allows you to enable, disable, and change various values to control the coreboot
-build process, including which mainboard(motherboard) to use, which toolchain to
-use, and how the runtime debug console should be presented and saved.
-Anytime you change mainboards in Kconfig, you should always run `make distclean`
-before running `make menuconfig`. Due to the way that Kconfig works, values will
-be kept from the previous mainboard if you skip the clean step. This leads to a
-hybrid configuration which may or may not work as expected.
+
+This step configures coreboot's build options using the menuconfig
+interface to Kconfig. Kconfig is the same configuration program used by
+the linux kernel. It allows you to enable, disable, and change various
+values to control the coreboot build process, including which
+mainboard(motherboard) to use, which toolchain to use, and how the
+runtime debug console should be presented and saved.  Anytime you change
+mainboards in Kconfig, you should always run `make distclean` before
+running `make menuconfig`. Due to the way that Kconfig works, values
+will be kept from the previous mainboard if you skip the clean step.
+This leads to a hybrid configuration which may or may not work as
+expected.
+
 
 ### Step 6 summary - Build coreboot
-You may notice that a number of other pieces are downloaded at the beginning of
-the build process. These are the git submodules used in various coreboot builds.
-By default, the _blobs_ submodule is not downloaded. This git submodule may be
-required for other builds for microcode or other binaries. To enable downloading
-this submodule, select the option "Allow use of binary-only repository" in the
-"General Setup" menu of Kconfig
-This attempts to build the coreboot rom. The rom file itself ends up in the
-build directory as 'coreboot.rom'. At the end of the build process, the build
-displayed the contents of the rom file.
+
+You may notice that a number of other pieces are downloaded at the
+beginning of the build process. These are the git submodules used in
+various coreboot builds.  By default, the _blobs_ submodule is not
+downloaded. This git submodule may be required for other builds for
+microcode or other binaries. To enable downloading this submodule,
+select the option "Allow use of binary-only repository" in the "General
+Setup" menu of Kconfig This attempts to build the coreboot rom. The rom
+file itself ends up in the build directory as 'coreboot.rom'. At the end
+of the build process, the build displayed the contents of the rom file.
+
 
 ### Step 7 summary - Install QEMU
+
 QEMU is a processor emulator which we can use to show the coreboot boot
 process in a virtualised environment.
 
+
 ### Step 8 summary - Run QEMU
+
 Here's the command line instruction broken down:
 * `qemu-system-x86_64`
-This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
-ISA bridge.
+This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3
+PCI to ISA bridge.
 * `-bios build/coreboot.rom`
-Use the coreboot rom image that we just built. If this flag is left out, the
-standard SeaBIOS image that comes with QEMU is used.
+Use the coreboot rom image that we just built. If this flag is left out,
+the standard SeaBIOS image that comes with QEMU is used.
 * `-serial stdio`
-Send the serial output to the console. This allows you to view the coreboot
-boot log.
+Send the serial output to the console. This allows you to view the
+coreboot boot log.
diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md
diff --git a/Documentation/tutorial/part3.md b/Documentation/tutorial/part3.md
diff --git a/Documentation/util.md b/Documentation/util.md
@@ -47,9 +47,9 @@ file `Python`
 	* _rmodtool_ - Creates rmodules `C`
 	* _ifwitool_ - For manipulating IFWI `C`
 * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
-* __chromeos__ - These scripts can be used to access Chrome OS
+* __chromeos__ - These scripts can be used to access ChromeOS
 resources, for example to extract System Agent reference code and other
-blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS
+blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
 recovery image. `C`
 * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
 libc support) `Bash`

diff --git a/Documentation/util/ifdtool/layout.md b/Documentation/util/ifdtool/layout.md
@@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 +------------+------------------+-----------+-------------------------------------------+
 | 4          | Platform Data    | SI_PDR    |                                           |
 +------------+------------------+-----------+-------------------------------------------+
-| 8          | EC Firmware      | SI_EC     | Most Chrome OS devices do not use this    |
+| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this    |
 |            |                  |           | region; EC firmware is stored in BIOS     |
 |            |                  |           | region of flash                           |
 +------------+------------------+-----------+-------------------------------------------+

diff --git a/LICENSES/retained-copyrights.txt b/LICENSES/retained-copyrights.txt
@@ -7,17 +7,17 @@ Copyright © 2012 Intel Corporation
 Copyright 2012 Red Hat Inc.
 Copyright 2013 Google Inc.
 Copyright 2014 Google Inc.
-Copyright 2014 The Chromium OS Authors. All rights reserved.
+Copyright 2014 The ChromiumOS Authors. All rights reserved.
 Copyright 2015 Google Inc.
 Copyright 2015, Google Inc.
 Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
-Copyright 2016 The Chromium OS Authors. All rights reserved.
+Copyright 2016 The ChromiumOS Authors. All rights reserved.
 Copyright 2017-2019 Eltan B.V.
 Copyright 2017 Google Inc.
 Copyright 2018 Generated Code
 Copyright 2018-present Facebook, Inc.
 Copyright 2019 9Elements Agency GmbH <patrick.rudolph@9elements.com>
-Copyright 2019 The Chromium OS Authors. All rights reserved.
+Copyright 2019 The ChromiumOS Authors. All rights reserved.
 Copyright (C) 2002 David S. Peterson.  All rights reserved.
 Copyright (c) 2003-2016  Cavium Inc. (support@cavium.com). All rights
 Copyright (c) 2003-2017  Cavium Inc. (support@cavium.com). All rights
@@ -35,7 +35,7 @@ Copyright (c) 2010-2017, The Regents of the University of California
 Copyright (c) 2010, Code Aurora Forum. All rights reserved.
 Copyright (C) 2010 coresystems GmbH
 Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
-Copyright (c) 2010 The Chromium OS Authors. All rights reserved.
+Copyright (c) 2010 The ChromiumOS Authors. All rights reserved.
 Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
 Copyright (c) 2011-2012 The Linux Foundation. All rights reserved.
 Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
@@ -52,14 +52,14 @@ Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc.
 Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
 Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.*
 Copyright (c) 2012, Code Aurora Forum. All rights reserved.
-Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+Copyright (c) 2012 The ChromiumOS Authors. All rights reserved.
 Copyright (c) 2012 The Linux Foundation. All rights reserved.
 Copyright (c) 2012 The Linux Foundation. All rights reserved.*
 Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
 Copyright (c) 2013-2015 Intel Corporation.
 Copyright (c) 2013-2017 Intel Corporation.
 Copyright (C) 2013 Google Inc.
-Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+Copyright (c) 2013 The ChromiumOS Authors. All rights reserved.
 Copyright (c) 2013 The Linux Foundation. All rights reserved.
 Copyright (c) 2013, The Regents of the University of California (Regents).
 Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
@@ -69,14 +69,14 @@ Copyright (C) 2014 - 2016 The Linux Foundation. All rights reserved.
 Copyright (c) 2014 Google Inc.
 Copyright (C) 2014 Google Inc.
 Copyright (c) 2014 Google Inc. All rights reserved.
-Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+Copyright (c) 2014 The ChromiumOS Authors. All rights reserved.
 Copyright (C) 2014 The Linux Foundation. All rights reserved.
 Copyright (C) 2015-2016 Intel Corporation.
 Copyright (C) 2015-2016, Intel Corporation
 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
 Copyright (C) 2015 Google Inc.
 Copyright (c) 2015, Intel Corporation. All rights reserved.
-Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+Copyright (c) 2015 The ChromiumOS Authors. All rights reserved.
 Copyright (C) 2015 The Linux Foundation. All rights reserved.
 Copyright (c) 2015, The Linux Foundation. All rights reserved.
 Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering

diff --git a/MAINTAINERS b/MAINTAINERS
@@ -620,6 +620,7 @@ M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
+M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
@@ -630,6 +631,7 @@ M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
+M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 S:	Maintained
 F:	src/soc/amd/common/
 
@@ -639,6 +641,7 @@ M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
+M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
@@ -649,13 +652,15 @@ M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
+M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 S:	Maintained
 F:	src/soc/amd/sabrina/
 F:	src/vendorcode/amd/fsp/sabrina/
 
 AMD Stoneyridge
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
+M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 S:	Odd Fixes
 F:	src/soc/amd/stoneyridge/
 

diff --git a/Makefile b/Makefile
@@ -31,6 +31,7 @@ KCONFIG_TRISTATE := $(obj)/tristate.conf
 KCONFIG_NEGATIVES := 1
 KCONFIG_STRICT := 1
 KCONFIG_PACKAGE := CB.Config
+KCONFIG_MAKEFILE_REAL ?= $(objk)/Makefile.real
 
 COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
 COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
@@ -44,6 +45,7 @@ CONFIG_SHELL := sh
 KBUILD_DEFCONFIG := configs/defconfig
 UNAME_RELEASE := $(shell uname -r)
 HAVE_DOTCONFIG := $(wildcard $(DOTCONFIG))
+HAVE_KCONFIG_MAKEFILE_REAL := $(wildcard $(KCONFIG_MAKEFILE_REAL))
 MAKEFLAGS += -rR --no-print-directory
 
 # Make is silent per default, but 'make V=1' will show all compiler calls.
@@ -87,14 +89,20 @@ help_coreboot help::
 # Order _does_ matter for pattern rules.
 include $(srck)/Makefile.inc
 
-# Three cases where we don't need fully populated $(obj) lists:
+# The cases where we don't need fully populated $(obj) lists:
 # 1. when no .config exists
-# 2. when make config (in any flavour) is run
-# 3. when make distclean is run
+# 2. When no $(obj)/util/kconfig/Makefile.real exists and we're building tools
+# 3. when make config (in any flavour) is run
+# 4. when make distclean is run
 # Don't waste time on reading all Makefile.incs in these cases
 ifeq ($(strip $(HAVE_DOTCONFIG)),)
 NOCOMPILE:=1
 endif
+ifeq ($(strip $(HAVE_KCONFIG_MAKEFILE_REAL)),)
+ifneq ($(MAKECMDGOALS),tools)
+NOCOMPILE:=1
+endif
+endif
 ifneq ($(MAKECMDGOALS),)
 ifneq ($(filter %config %clean cross% clang iasl lint% help% what-jenkins-does,$(MAKECMDGOALS)),)
 NOCOMPILE:=1
@@ -136,9 +144,11 @@ include $(TOPLEVEL)/util/testing/Makefile.inc
 -include $(TOPLEVEL)/site-local/Makefile.inc
 include $(TOPLEVEL)/tests/Makefile.inc
 real-all:
-	@echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2
-	@echo "Please specify a config file or run 'make menuconfig' to" >&2
-	@echo "generate a new config file." >&2
+	@echo "Error: Trying to build, but NOCOMPILE is set." >&2
+	@echo "  Please file a bug with the following information:"
+	@echo "- MAKECMDGOALS: $(MAKECMDGOALS)" >&2
+	@echo "- HAVE_DOTCONFIG: $(HAVE_DOTCONFIG)" >&2
+	@echo "- HAVE_KCONFIG_MAKEFILE_REAL: $(HAVE_KCONFIG_MAKEFILE_REAL)" >&2
 	@exit 1
 else
 

diff --git a/Makefile.inc b/Makefile.inc
@@ -190,30 +190,33 @@ ramstage-generic-ccopts += -D__RAMSTAGE__
 ifeq ($(CONFIG_COVERAGE),y)
 ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
 endif
+ifneq ($(GIT),)
 ifneq ($(UPDATED_SUBMODULES),1)
+$(info Updating git submodules.)
 # try to fetch non-optional submodules if the source is under git
-forgetthis:=$(if $(GIT),$(shell git submodule update --init $(quiet_errors)))
+forgetthis:=$(shell git submodule update --init $(quiet_errors))
 # Checkout Cmocka repository
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors)))
+forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))
 ifeq ($(CONFIG_USE_BLOBS),y)
 # These items are necessary because each has update=none in .gitmodules.  They are ignored
 # until expressly requested and enabled with --checkout
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors)))
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors)))
+forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
+forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
 ifeq ($(CONFIG_FSP_USE_REPO),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors)))
+forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
 endif
 ifeq ($(CONFIG_USE_AMD_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors)))
+forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
 endif
 ifeq ($(CONFIG_USE_QC_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors)))
+forgetthis:=$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))
 endif
 endif
 UPDATED_SUBMODULES:=1
 COREBOOT_EXPORTS += UPDATED_SUBMODULES
 
 endif
+endif # GIT != ""
 
 postcar-c-deps:=$$(OPTION_TABLE_H)
 ramstage-c-deps:=$$(OPTION_TABLE_H)
@@ -340,7 +343,7 @@ cbfs-files-processor-struct= \
 	$(eval $(2): $(1) $(obj)/build.h $(obj)/fmap_config.h $(KCONFIG_AUTOHEADER); \
 		printf "    CC+STRIP   $(1)\n"; \
 		$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) --param asan-globals=0 $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
-		$(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
+		$(OBJCOPY_ramstage) -O binary --only-section='.data*' --only-section='.bss*' --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
 		rm -f $(2).tmp) \
 	$(eval DEPENDENCIES += $(2).d)
 

diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros
@@ -7,7 +7,7 @@ CONFIG_SPI_FLASH_SMM=y
 CONFIG_USE_BLOBS=y
 CONFIG_ANY_TOOLCHAIN=y
 
-# Chrome OS
+# ChromeOS
 CONFIG_CHROMEOS=y
 CONFIG_HAS_RECOVERY_MRC_CACHE=y
 CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y

diff --git a/configs/config.msi_ms7d25 b/configs/config.msi_ms7d25
@@ -0,0 +1,19 @@
+CONFIG_VENDOR_MSI=y
+CONFIG_CBFS_SIZE=0x1000000
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_TIANOCORE_BOOT_TIMEOUT=3
+CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+CONFIG_PCIEXP_HOTPLUG=y
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+CONFIG_POST_DEVICE_PCI_PCIE=y
+CONFIG_POST_IO_PORT=0x80
+CONFIG_PAYLOAD_TIANOCORE=y
+CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
+CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
+CONFIG_TIANOCORE_CBMEM_LOGGING=y
+CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
+CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
+CONFIG_TPM2=y
+CONFIG_TPM_MEASURED_BOOT=y
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_CBFS_SIZE=0x00200000
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
@@ -8,16 +8,17 @@ CONFIG_UART_PCI_ADDR=0x0
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,157b"
@@ -11,17 +11,18 @@ CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"
@@ -11,17 +11,18 @@ CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"
@@ -11,17 +11,18 @@ CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"
@@ -11,17 +11,18 @@ CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"
@@ -11,17 +11,18 @@ CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu7 b/configs/config.pcengines_apu7
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.17.0.1"
+CONFIG_LOCALVERSION="v4.17.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
@@ -10,18 +10,19 @@ CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=n
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
 CONFIG_POST_IO_PORT=0x80
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1"
+CONFIG_SEABIOS_NO_OPROMS=y
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
-CONFIG_SEABIOS_NO_OPROMS=y
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_REVISION=y

diff --git a/configs/config.prodrive_hermes b/configs/config.prodrive_hermes
@@ -11,3 +11,5 @@ CONFIG_SMMSTORE_V2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
 CONFIG_POST_DEVICE_LPC=y
 CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"
+CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
+CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -225,6 +225,7 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
 		CONFIG_TIANOCORE_CUSTOM=$(CONFIG_TIANOCORE_CUSTOM) \
+		CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS=$(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS) \
 		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
 		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
 		CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \
@@ -237,10 +238,11 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 		CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
 		CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
 		CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
+		CONFIG_TIANOCORE_SERIAL_SUPPORT=$(TIANOCORE_SERIAL_SUPPORT) \
 		CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
 		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
-		CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS=$(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS) \
+		CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \

diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
@@ -79,7 +79,7 @@ config TIANOCORE_RELEASE
 
 endchoice
 
-if TIANOCORE_UEFIPAYLOAD
+if TIANOCORE_UEFIPAYLOAD || TIANOCORE_CUSTOM || TIANOCORE_UPSTREAM
 
 config TIANOCORE_ABOVE_4G_MEMORY
 	bool "Enable above 4G memory"
@@ -94,17 +94,25 @@ config TIANOCORE_ABOVE_4G_MEMORY
 
 config TIANOCORE_BOOTSPLASH_FILE
 	string "Tianocore Bootsplash path and filename"
-	default "bootsplash.bmp"
+	default "Documentation/coreboot_logo.svg"
 	help
-	  Select this option if you have a bootsplash image that you would
-	  like to be used. If this option is not selected, the default
+	  The path and filename of the file to use as graphical bootsplash
+	  image. If this option is not configured, the default
 	  coreboot logo (European Brown Hare) will used.
 
-	  The path and filename of the file to use as graphical bootsplash
-	  image. The file must be an uncompressed BMP, in BMP 3 format.
+	  You can use any image format supported by imagemagick, a list of which
+	  can be found [here](https://imagemagick.org/script/formats.php).
+
+	  The build process will automatically convert this to the format that
+	  EDK2 requires, which is an uncompressed BMP, in BMP3 format. It does
+	  this using imagemagick (`convert splosh.bmp BMP3:splash.bmp`).
+
+	  The newly formatted file will be the dimensions size as the original
+	  one.
 
-	  Linux can create these with the below command:
-	      `convert splosh.bmp BMP3:splash.bmp`
+	  The build process will automatically do this conversion, so it can
+	  be supplied with any format that imagemagick can process (which is
+	  pretty much any!).
 
 	  This image will also be used as the BGRT boot image, which may
 	  persist through your OS boot process.
@@ -169,11 +177,19 @@ config TIANOCORE_PS2_SUPPORT
 	  Include support for PS/2 keyboards
 
 config TIANOCORE_SD_MMC_TIMEOUT
-	int "Timeout in μs for initializing SD Card reader"
-	default 1000
+	int "Timeout in ms for initializing SD and eMMC devices"
+	default 10
 	help
 	  The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
-	  Most only require 1000μs, but certain readers can take 1000000μs.
+	  Most only require 10ms, but certain readers can take 1s.
+
+config TIANOCORE_SERIAL_SUPPORT
+	bool "Support serial output"
+	default y if TIANOCORE_DEBUG
+	default n
+	help
+	  Enable serial port output in edk2. Serial output limits the performance of edk2's
+	  FrontPage.
 
 endif
 

diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
@@ -40,10 +40,22 @@ endif
 ifeq ($(CONFIG_TIANOCORE_RELEASE),y)
 BUILD_STR += -b RELEASE
 endif
+# DISABLE_SERIAL_TERMINAL	= FALSE
+ifneq ($(CONFIG_TIANOCORE_SERIAL_SUPPORT),y)
+BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
+endif
 # FOLLOW_BGRT_SPEC		= FALSE
 ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
 BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
 endif
+# PCIE_BASE_ADDRESS		= 0
+ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
+BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
+endif
+# PCIE_BASE_LENGTH		= 0
+ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
+BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH)
+endif
 # PRIORITIZE_INTERNAL		= FALSE
 ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
 BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
@@ -70,19 +82,29 @@ BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
 endif
 # SD_MMC_TIMEOUT		= 1000000
 ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
-BUILD_STR += -D SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT)
+BUILD_STR += -D SD_MMC_TIMEOUT=$(call int-multiply, $(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) 1000)
 endif
 #
+# EDKII has the below PCDs that are revalant to coreboot:
+#
+# Allows EDKII to use the full framebuffer
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
+#
 # The below are legacy options only available in CorebootPayloadPkg:
 #
 # PCIE_BASE			= 0
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
 ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),)
 BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
 endif
 # USE_HPET_TIMER		= FALSE
 ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y)
 BUILD_STR += -D USE_HPET_TIMER=TRUE
 endif
+endif # CONFIG_TIANOCORE_COREBOOTPAYLOAD
 
 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
 
@@ -118,29 +140,48 @@ update: $(project_dir)
 		fi; \
 		git submodule update --init --checkout
 
+logo: $(project_dir)/edk2
+	case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
+		/*) convert -background None $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+			BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+		*) convert -background None $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+			BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+	esac \
+
 checktools:
-	echo "Checking uuid-dev..."
+	echo -n "EDK2: Checking uuid-dev:"
 	echo "#include <uuid/uuid.h>" > libtest.c
 	echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
-	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \
-		( echo " Not found."; echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
+	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo "    Found!" || \
+		( echo "    Not found!"; \
+			echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
 	rm -rf libtest.c libtest
-	echo "Checking nasm..."
-	type nasm > /dev/null 2>&1 && echo " found nasm." || \
-		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
+	echo -n "EDK2: Checking nasm:"
+	type nasm > /dev/null 2>&1 && echo "        Found!" || \
+		( echo "        Not found!"; echo "ERROR: Please install nasm."; exit 1 )
+	echo -n "EDK2: Checking imagemagick:"
+	-convert -size 1x1 xc: test.png &> /dev/null;
+	if [ -f test.png ]; then \
+		rm test.png && echo " Found!"; \
+	else \
+		echo " Not found!"; \
+		echo "ERROR: Please install imagemagick"; \
+		exit 1; \
+	fi
 
-build: update checktools
+build: update logo checktools
+	echo "   ##### $(project_name) Build Summary #####"
+	echo "   Repository:     $(CONFIG_TIANOCORE_REPOSITORY)"
+	echo "   Branch:         $(CONFIG_TIANOCORE_TAG_OR_REV)"
+	echo " $(BUILD_STR)" | \
+		sed 's/-/\n   /g' | sort | sed \
+		-e 's/a /Architecture:   /g' \
+		-e 's/b /Release:        /g' \
+		-e 's/D /Option:         /g' \
+		-e 's/p /Payload:        /g' \
+		-e 's/q /Build:          Quiet/' \
+		-e 's/t /Toolchain:      /'
 	unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
-	echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)"
-	if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
-		echo "    Copying custom bootsplash image"; \
-		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
-			/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
-			*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
-		esac \
-	fi; \
 	cd $(project_dir); \
 		export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
 		export WORKSPACE=$(project_dir); \
@@ -160,4 +201,4 @@ clean:
 distclean:
 	rm -rf */
 
-.PHONY: all update checktools config build clean distclean
+.PHONY: all update checktools config build clean distclean logo
diff --git a/payloads/external/tianocore/tools_def.txt b/payloads/external/tianocore/tools_def.txt
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -56,10 +56,10 @@ config DEVELOPER
 	  libpayload developers.
 
 config CHROMEOS
-	bool "Chrome OS Options"
+	bool "ChromeOS Options"
 	default n
 	help
-	  Select configuration defaults appropriate for Chrome OS boards.
+	  Select configuration defaults appropriate for ChromeOS boards.
 
 choice
 	prompt "Compiler to use"

diff --git a/payloads/libpayload/arch/x86/string.c b/payloads/libpayload/arch/x86/string.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
- * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2011 The ChromiumOS Authors.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 Chromium OS authors
+ * Copyright (c) 2014 ChromiumOS authors
  */
 
 #include <libpayload.h>

diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (c) 2012 The Chromium OS Authors.
+ * Copyright (c) 2012 The ChromiumOS Authors.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions

diff --git a/payloads/libpayload/include/ipchksum.h b/payloads/libpayload/include/ipchksum.h
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (c) 2012 The Chromium OS Authors.
+ * Copyright (c) 2012 The ChromiumOS Authors.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions

diff --git a/spd/ddr4/memory_parts.json b/spd/ddr4/memory_parts.json
@@ -204,6 +204,18 @@
                 "ranksPerPackage": 1
             }
         },
+	{
+            // Datasheet Revision: Rev. 1.0 Dec. 2021
+            "name": "H5AG36EXNDX019",
+            "attribs": {
+                "speedMTps": 3200,
+                "CL_nRCD_nRP": 22,
+                "capacityPerDieGb": 8,
+                "diesPerPackage": 1,
+                "packageBusWidth": 16,
+                "ranksPerPackage": 1
+            }
+        },
         {
             // Datasheet Revision: Rev. 0.0, Apr. 2020
             "name": "K4AAG165WB-BCWE",

diff --git a/spd/ddr4/platforms_manifest.generated.txt b/spd/ddr4/platforms_manifest.generated.txt
@@ -1,5 +1,5 @@
 # Generated by:
-# util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4
+# ../../util/spd_tools/bin/spd_gen memory_parts.json ddr4
 
 TGL,set-0
 PCO,set-0
diff --git a/spd/ddr4/set-0/parts_spd_manifest.generated.txt b/spd/ddr4/set-0/parts_spd_manifest.generated.txt
@@ -1,5 +1,5 @@
 # Generated by:
-# util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4
+# ../../util/spd_tools/bin/spd_gen memory_parts.json ddr4
 
 H5AN8G6NDJR-XNC,spd-1.hex
 MT40A512M16TB-062E:J,spd-1.hex
@@ -17,6 +17,7 @@ H5AN8G6NCJR-XNC,spd-1.hex
 K4AAG165WA-BCTD,spd-8.hex
 H5ANAG6NDMR-XNC,spd-2.hex
 H5ANAG6NCJR-XNC,spd-9.hex
+H5AG36EXNDX019,spd-1.hex
 K4AAG165WB-BCWE,spd-9.hex
 MT40A1G16RC-062E:B,spd-9.hex
 MT40A512M16TB-062E:R,spd-1.hex

diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
@@ -99,6 +99,16 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 6400
             }
+        },
+        {
+            "name":  "MT62F1G32D2DS-026 WT:B",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 7500
+            }
         }
     ]
 }
diff --git a/spd/lp5/platforms_manifest.generated.txt b/spd/lp5/platforms_manifest.generated.txt
@@ -1,5 +1,6 @@
 # Generated by:
 # util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
 
+MTL,set-0
 ADL,set-0
 SBR,set-1
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -11,3 +11,4 @@ K3LKLKL0EM-MGCN,spd-5.hex
 H58G56AK6BX069,spd-3.hex
 MT62F1G32D4DS-031 WT:B,spd-2.hex
 K3LKCKC0BM-MGCP,spd-6.hex
+MT62F1G32D2DS-026 WT:B,spd-7.hex
diff --git a/...s/skyrim/memory/spd-MT62F2G32D8DR-031.hex → spd/lp5/set-0/spd-7.hex b/...s/skyrim/memory/spd-MT62F2G32D8DR-031.hex → spd/lp5/set-0/spd-7.hex
@@ -1,11 +1,11 @@
-23 11 13 0E 85 21 F9 18 00 40 00 00 09 02 00 00
-00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+23 10 13 0E 16 22 95 08 00 00 00 00 02 01 00 00
+00 00 09 00 00 00 00 00 AB 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 C5 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -7,7 +7,8 @@ H9JCNNNCP3MLYR-N6E,spd-2.hex
 K3LKBKB0BM-MGCP,spd-3.hex
 H9JCNNNBK3MLYR-N6E,spd-1.hex
 MT62F2G32D8DR-031 WT:B,spd-4.hex
-K3LKLKL0EM-MGCN,spd-5.hex
+K3LKLKL0EM-MGCN,spd-1.hex
 H58G56AK6BX069,spd-3.hex
 MT62F1G32D4DS-031 WT:B,spd-2.hex
-K3LKCKC0BM-MGCP,spd-6.hex
+K3LKCKC0BM-MGCP,spd-5.hex
+MT62F1G32D2DS-026 WT:B,spd-3.hex
diff --git a/spd/lp5/set-1/spd-1.hex b/spd/lp5/set-1/spd-1.hex
@@ -1,11 +1,11 @@
 23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
-00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
+00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/spd/lp5/set-1/spd-2.hex b/spd/lp5/set-1/spd-2.hex
@@ -1,11 +1,11 @@
 23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00
-00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
+00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/spd/lp5/set-1/spd-3.hex b/spd/lp5/set-1/spd-3.hex
@@ -1,11 +1,11 @@
 23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
-00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
+00 00 03 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/spd/lp5/set-1/spd-4.hex b/spd/lp5/set-1/spd-4.hex
@@ -1,11 +1,11 @@
 23 11 13 0E 85 21 F9 18 00 40 00 00 09 02 00 00
-00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
+00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/spd/lp5/set-1/spd-5.hex b/spd/lp5/set-1/spd-5.hex
@@ -1,6 +1,6 @@
-23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
-00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
+00 00 03 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/spd/lp5/set-1/spd-6.hex → spd/lp5/set-1/spd-7.hex b/spd/lp5/set-1/spd-6.hex → spd/lp5/set-1/spd-7.hex
@@ -1,11 +1,11 @@
-23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
+23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
 00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 93 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/src/Kconfig b/src/Kconfig
@@ -559,7 +559,8 @@ config CBFS_AUTOGEN_ATTRIBUTES
 menu "Chipset"
 
 comment "SoC"
-source "src/soc/*/Kconfig"
+source "src/soc/*/*/Kconfig"
+source "src/soc/*/*/Kconfig.common"
 comment "CPU"
 source "src/cpu/Kconfig"
 comment "Northbridge"

diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
@@ -3,7 +3,7 @@
 #include <acpi/acpigen_extern.asl>
 
 #if CONFIG(CHROMEOS_NVS)
-/* Chrome OS specific */
+/* ChromeOS specific */
 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
 #endif
 

diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c
@@ -5,6 +5,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
+#include <romstage_common.h>
 #include <timestamp.h>
 
 __weak void platform_romstage_main(void) { /* no-op, for bring-up */ }
@@ -15,8 +16,13 @@ void main(void)
 	timestamp_add_now(TS_ROMSTAGE_START);
 
 	console_init();
+
 	exception_init();
+	romstage_main();
+}
 
+void __noreturn romstage_main(void)
+{
 	platform_romstage_main();
 	cbmem_initialize_empty();
 	platform_romstage_postram();

diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
@@ -59,7 +59,7 @@ void handle_sbi(trapframe *tf)
 {
 	uintptr_t ret = 0;
 	uintptr_t arg0 = tf->gpr[10];
-	__unused uintptr_t arg1 = tf->gpr[11];
+	__maybe_unused uintptr_t arg1 = tf->gpr[11];
 	uintptr_t which = tf->gpr[17];
 
 	switch (which) {

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -93,6 +93,8 @@ bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c
 bootblock-y += gdt_init.S
 bootblock-y += id.S
 bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
+bootblock-y += bootblock.ld
+bootblock-y += car.ld
 
 $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
 
@@ -142,6 +144,8 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c
 
 verstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 
+verstage-y += car.ld
+
 verstage-libs ?=
 
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y)
@@ -177,6 +181,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
 romstage-$(CONFIG_COOP_MULTITASKING) += thread.c
 romstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
+romstage-y += car.ld
 
 romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
 romstage-libs ?=

diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S
@@ -1,10 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/ram_segs.h>
-#include <cpu/x86/msr.h>
 #include <cpu/x86/cr.h>
 
-
 #if ENV_X86_64
 
 	/*

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -2,6 +2,7 @@
 
 /* CACHE_ROM_SIZE defined here. */
 #include <cpu/x86/mtrr.h>
+#include <memlayout.h>
 
 /* This file is included inside a SECTIONS block */
 . = CONFIG_DCACHE_RAM_BASE;

diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
@@ -43,7 +43,7 @@ void fill_postcar_frame(struct postcar_frame *pcf);
  * prepare_and_run_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use.
  */
-void prepare_and_run_postcar(void);
+void __noreturn prepare_and_run_postcar(void);
 
 /*
  * Systems without a native coreboot cache-as-ram teardown may implement

diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
@@ -21,22 +21,22 @@ SECTIONS
 	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
 	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
 
-	#include "car.ld"
+	INCLUDE "romstage/arch/x86/car.ld"
 #elif ENV_SEPARATE_VERSTAGE
 	/* The 1M size is not allocated. It's just for basic size checking.
 	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
 	VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
 
-	#include "car.ld"
+	INCLUDE "verstage/arch/x86/car.ld"
 #elif ENV_BOOTBLOCK
 
-	#include "car.ld"
+	INCLUDE "bootblock/arch/x86/car.ld"
 
 #elif ENV_POSTCAR
 	POSTCAR(32M, 1M)
 #endif
 }
 
 #if ENV_BOOTBLOCK
-#include <arch/x86/bootblock.ld>
+	INCLUDE "bootblock/arch/x86/bootblock.ld"
 #endif  /* ENV_BOOTBLOCK */
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
@@ -63,7 +63,7 @@ static void run_postcar_phase(struct postcar_frame *pcf);
 
 /* prepare_and_run_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
-void prepare_and_run_postcar(void)
+void __noreturn prepare_and_run_postcar(void)
 {
 	struct postcar_frame pcf;
 
@@ -76,6 +76,7 @@ void prepare_and_run_postcar(void)
 
 	run_postcar_phase(&pcf);
 	/* We do not return here. */
+	die("Failed to load postcar\n!");
 }
 
 static void finalize_load(uintptr_t *reloc_params, uintptr_t mtrr_frame_ptr)

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -21,6 +21,7 @@
 #define CBMEM_ID_CPU_CRASHLOG	0x4350555f
 #define CBMEM_ID_COVERAGE	0x47434f56
 #define CBMEM_ID_DRTM_LOG	0x444c4f47
+#define CBMEM_ID_CSE_UPDATE	0x43534555
 #define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
 #define CBMEM_ID_ELOG		0x454c4f47
 #define CBMEM_ID_FREESPACE	0x46524545

diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h
@@ -15,8 +15,21 @@
 #define __aligned(x) __attribute__((__aligned__(x)))
 #endif
 
-#ifndef __unused
-#define __unused __attribute__((__unused__))
+/* Because there may be variables/parameters whose name contains "__unused" in
+   header files of libc, namely musl, names consistent with the ones in the
+   Linux kernel may be a better choice. */
+
+/* This is used to mark identifiers unused in all conditions, e.g. a parameter
+   completely unused in all code branch, only present to fit an API. */
+#ifndef __always_unused
+#define __always_unused __attribute__((__unused__))
+#endif
+
+/* This is used to mark identifiers unused in some conditions, e.g. a parameter
+   only unused in some code branches, a global variable only accessed with code
+   being conditionally preprocessed, etc. */
+#ifndef __maybe_unused
+#define __maybe_unused __attribute__((__unused__))
 #endif
 
 #ifndef __must_check

diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h
@@ -203,7 +203,7 @@ struct elog_event_data_wake {
 	uint32_t instance;
 } __packed;
 
-/* Chrome OS related events */
+/* ChromeOS related events */
 #define ELOG_TYPE_CROS_DEVELOPER_MODE     0xa0
 #define ELOG_TYPE_CROS_RECOVERY_MODE      0xa1
 #define  ELOG_CROS_RECOVERY_MODE_BUTTON    0x02
@@ -305,7 +305,7 @@ struct elog_event_mem_cache_update {
 #define ELOG_TYPE_MI_HRPC                 0xb4
 #define ELOG_TYPE_MI_HR                   0xb5
 
-/* Chrome OS diagnostics-related events */
+/* ChromeOS diagnostics-related events */
 #define ELOG_TYPE_CROS_DIAGNOSTICS        0xb6
 #define  ELOG_CROS_LAUNCH_DIAGNOSTICS      0x01
 

diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c
@@ -170,7 +170,8 @@ static int te_relocate(uintptr_t new_addr, void *te)
 			printk(FSP_DBG_LVL, "reloc type %x offset %zx\n",
 				type, offset);
 
-			if (type == EFI_IMAGE_REL_BASED_HIGHLOW) {
+			if (type == EFI_IMAGE_REL_BASED_HIGHLOW ||
+					type == EFI_IMAGE_REL_BASED_DIR64) {
 				uint32_t *reloc_addr;
 				uint32_t val;
 

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -165,7 +165,7 @@ enum timestamp_id {
 	TS_KERNEL_START = 1101,
 	TS_KERNEL_DECOMPRESSION = 1102,
 
-	/* 1200-1300: Chrome OS Hypervisor */
+	/* 1200-1300: ChromeOS Hypervisor */
 	TS_CRHV_BOOT = 1200,
 	TS_CRHV_PLATFORM_INIT = 1201,
 	TS_CRHV_SERVICES_STARTED = 1202,
@@ -247,10 +247,10 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_EC_HASH_READY, 0, "EC vboot hash ready"),
 	TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, 0, "waiting for EC to allow higher power draw"),
 	TS_NAME_DEF(TS_EC_SYNC_END, 0, "finished EC software sync"),
-	TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load Chrome OS VPD"),
+	TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load ChromeOS VPD"),
 	TS_NAME_DEF(TS_COPYVPD_RO_END, TS_COPYVPD_RW_END,
-		    "finished loading Chrome OS VPD (RO)"),
-	TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading Chrome OS VPD (RW)"),
+		    "finished loading ChromeOS VPD (RO)"),
+	TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading ChromeOS VPD (RW)"),
 	TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END,
 		    "started TPM enable update"),
 	TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"),
@@ -344,7 +344,7 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"),
 	TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"),
 
-	/* Chrome OS hypervisor */
+	/* ChromeOS hypervisor */
 	TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
 	TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),
 	TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"),

diff --git a/src/commonlib/include/commonlib/tpm_log_serialized.h b/src/commonlib/include/commonlib/tpm_log_serialized.h
@@ -147,7 +147,7 @@ typedef struct {
 #define EV_NONHOST_INFO			0x00000011
 #define EV_OMIT_BOOT_DEVICE_EVENTS	0x00000012
 
-static const char *tpm_event_types[] __unused = {
+static const char *tpm_event_types[] __maybe_unused = {
 	[EV_PREBOOT_CERT]		= "Reserved",
 	[EV_POST_CODE]			= "POST code",
 	[EV_UNUSED]			= "Unused",

diff --git a/src/commonlib/region.c b/src/commonlib/region.c
@@ -222,7 +222,7 @@ void xlate_window_init(struct xlate_window *window, const struct region_device *
 }
 
 static void *mdev_mmap(const struct region_device *rd, size_t offset,
-			size_t size __unused)
+			size_t size __always_unused)
 {
 	const struct mem_region_device *mdev;
 
@@ -231,8 +231,8 @@ static void *mdev_mmap(const struct region_device *rd, size_t offset,
 	return &mdev->base[offset];
 }
 
-static int mdev_munmap(const struct region_device *rd __unused,
-			void *mapping __unused)
+static int mdev_munmap(const struct region_device *rd __always_unused,
+			void *mapping __always_unused)
 {
 	return 0;
 }
@@ -368,7 +368,8 @@ static void *xlate_mmap(const struct region_device *rd, size_t offset,
 	return rdev_mmap(xlwindow->access_dev, offset, size);
 }
 
-static int xlate_munmap(const struct region_device *rd __unused, void *mapping __unused)
+static int xlate_munmap(const struct region_device *rd __always_unused,
+			void *mapping __always_unused)
 {
 	/*
 	 * xlate_region_device does not keep track of the access device that was used to service

diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
@@ -3,3 +3,7 @@
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
+
+romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
+postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
+ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/hpet.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -39,7 +38,7 @@ void amd_initcpuio(void)
 	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32) MsrReg;
+	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Send all IO (0000-FFFF) to southbridge. */

diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
+#include <amdblocks/smm.h>
 #include <console/console.h>
-#include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
-#include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <acpi/acpi.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
 static void model_14_init(struct device *dev)
@@ -76,9 +77,7 @@ static void model_14_init(struct device *dev)
 	wrmsr(NB_CFG_MSR, msr);
 
 	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
+	lock_smm();
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/hpet.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -10,10 +9,10 @@
 
 void amd_initcpuio(void)
 {
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
+	UINT64 MsrReg;
+	UINT32 PciData;
+	PCI_ADDR PciAddress;
+	AMD_CONFIG_PARAMS StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);

diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -1,15 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
+#include <amdblocks/smm.h>
 #include <console/console.h>
-#include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
-#include <cpu/x86/smm.h>
-#include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <acpi/acpi.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <device/device.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
 static void model_15_init(struct device *dev)
@@ -93,9 +94,7 @@ static void model_15_init(struct device *dev)
 	}
 
 	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
+	lock_smm();
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/hpet.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -10,43 +9,43 @@
 
 void amd_initcpuio(void)
 {
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
+	UINT64 MsrReg;
+	UINT32 PciData;
+	PCI_ADDR PciAddress;
+	AMD_CONFIG_PARAMS StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
 	PciData = 1;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
 	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 	 * set to non-posted regions.
 	 */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
 	PciData |= 1 << 7;    /* set NP (non-posted) bit */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
 	PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
 	PciData = 0x00FECF00; /* last address before non-posted range */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
 	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
 	PciData = 0x0000F000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -1,14 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
+#include <amdblocks/smm.h>
 #include <console/console.h>
-#include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
-#include <device/device.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <acpi/acpi.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
 static void model_16_init(struct device *dev)
@@ -76,9 +77,7 @@ static void model_16_init(struct device *dev)
 	wrmsr(NB_CFG_MSR, msr);
 
 	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
+	lock_smm();
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -16,8 +16,8 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
 	uint32_t uma_base = top_of_cacheable;
 	uint32_t uma_size = topmem - top_of_cacheable;
 
-	printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
-			__func__, uma_size, uma_base);
+	printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", __func__, uma_size,
+	       uma_base);
 
-	uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
+	uma_resource_kb(nb, idx, uma_base / KiB, uma_size / KiB);
 }
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/hpet.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
@@ -11,10 +10,10 @@
 
 void amd_initcpuio(void)
 {
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
+	UINT64 MsrReg;
+	UINT32 PciData;
+	PCI_ADDR PciAddress;
+	AMD_CONFIG_PARAMS StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);

diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -1,16 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/smm.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
-#include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <smp/node.h>
 
 static void model_16_init(struct device *dev)
@@ -44,9 +45,7 @@ static void model_16_init(struct device *dev)
 	wrmsr(NB_CFG_MSR, msr);
 
 	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
+	lock_smm();
 
 	amd_update_microcode_from_cbfs();
 

diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c
@@ -18,33 +18,33 @@
 #define F16H_MPB_MAX_SIZE 3458
 #define F16H_MPB_DATA_OFFSET 32
 
- /*
-  * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
-  *	Microcode Patch Block
-  *		Microcode Header
-  *		Microcode "Blob"
-  *		...
-  *		...
-  *		(end of file)
-  *
-  *
-  * MICROCODE HEADER (offset 0 bytes from start of file)
-  * Total size = 32 bytes
-  *	[0:3]	Date code		(32 bits)
-  *	[4:7]	Patch level		(32 bits)
-  *	[8:9]	Microcode patch data ID (16 bits)
-  *	[10:15]	Reserved		(48 bits)
-  *	[16:19]	Chipset 1 device ID	(32 bits)
-  *	[20:23]	Chipset 2 device ID	(32 bits)
-  *	[24:25]	Processor Revisions ID	(16 bits)
-  *	[26]	Chipset 1 revision ID	(8 bits)
-  *	[27]	Chipset 2 revision ID	(8 bits)
-  *	[28:31]	Reserved		(32 bits)
-  *
-  * MICROCODE BLOB (offset += 32)
-  * Total size = m bytes
-  *
-  */
+/*
+ * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
+ *	Microcode Patch Block
+ *		Microcode Header
+ *		Microcode "Blob"
+ *		...
+ *		...
+ *		(end of file)
+ *
+ *
+ * MICROCODE HEADER (offset 0 bytes from start of file)
+ * Total size = 32 bytes
+ *	[0:3]	Date code		(32 bits)
+ *	[4:7]	Patch level		(32 bits)
+ *	[8:9]	Microcode patch data ID (16 bits)
+ *	[10:15]	Reserved		(48 bits)
+ *	[16:19]	Chipset 1 device ID	(32 bits)
+ *	[20:23]	Chipset 2 device ID	(32 bits)
+ *	[24:25]	Processor Revisions ID	(16 bits)
+ *	[26]	Chipset 1 revision ID	(8 bits)
+ *	[27]	Chipset 2 revision ID	(8 bits)
+ *	[28:31]	Reserved		(32 bits)
+ *
+ * MICROCODE BLOB (offset += 32)
+ * Total size = m bytes
+ *
+ */
 
 struct microcode {
 	uint32_t date_code;
@@ -63,7 +63,7 @@ struct microcode {
 
 	uint8_t reserved2[4];
 
-	uint8_t m_patch_data[F16H_MPB_MAX_SIZE-F16H_MPB_DATA_OFFSET];
+	uint8_t m_patch_data[F16H_MPB_MAX_SIZE - F16H_MPB_DATA_OFFSET];
 } __packed;
 
 static void apply_microcode_patch(const struct microcode *m)
@@ -76,18 +76,17 @@ static void apply_microcode_patch(const struct microcode *m)
 
 	wrmsr(MSR_PATCH_LOADER, msr);
 
-	printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n",
-		m->patch_id);
+	printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
 
 	msr = rdmsr(IA32_BIOS_SIGN_ID);
 	new_patch_id = msr.lo;
 
 	if (new_patch_id == m->patch_id)
 		printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n",
-			new_patch_id);
+		       new_patch_id);
 	else
 		printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n",
-			new_patch_id);
+		       new_patch_id);
 }
 
 static uint16_t get_equivalent_processor_rev_id(void)
@@ -98,7 +97,7 @@ static uint16_t get_equivalent_processor_rev_id(void)
 }
 
 static void amd_update_microcode(const void *ucode, size_t ucode_len,
-				uint16_t equivalent_processor_rev_id)
+				 uint16_t equivalent_processor_rev_id)
 {
 	const struct microcode *m;
 	const uint8_t *c = ucode;
@@ -122,8 +121,7 @@ void amd_update_microcode_from_cbfs(void)
 		return;
 	}
 
-	if (ucode_len > F16H_MPB_MAX_SIZE ||
-	    ucode_len < F16H_MPB_DATA_OFFSET) {
+	if (ucode_len > F16H_MPB_MAX_SIZE || ucode_len < F16H_MPB_DATA_OFFSET) {
 		printk(BIOS_DEBUG, "microcode file invalid. Skipping updates.\n");
 		return;
 	}

diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
@@ -1,3 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
+
+romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
+postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
+ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c
diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c
@@ -43,8 +43,7 @@ void smm_init(void)
 
 	enable_cache();
 	/* copy the real SMM handler */
-	memcpy((void *)SMM_BASE, _binary_smm_start,
-		_binary_smm_end - _binary_smm_start);
+	memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start);
 	wbinvd();
 	disable_cache();
 

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
@@ -54,5 +54,4 @@ void __noreturn romstage_main(void)
 
 	prepare_and_run_postcar();
 	/* We do not return here. */
-	die("failed to load postcar\n");
 }
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
@@ -313,7 +313,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * CPU_BCLK;

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
@@ -68,14 +68,36 @@ static inline u32 read_microcode_rev(void)
 
 #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
 
-void intel_microcode_load_unlocked(const void *microcode_patch)
+static int load_microcode(const struct microcode *ucode_patch)
 {
 	u32 current_rev;
 	msr_t msr;
+
+	msr.lo = (unsigned long)ucode_patch + sizeof(struct microcode);
+	msr.hi = 0;
+	wrmsr(IA32_BIOS_UPDT_TRIG, msr);
+
+	current_rev = read_microcode_rev();
+	if (current_rev == ucode_patch->rev) {
+		printk(BIOS_INFO, "microcode: updated to revision "
+		    "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
+		    ucode_patch->date & 0xffff, (ucode_patch->date >> 24) & 0xff,
+		    (ucode_patch->date >> 16) & 0xff);
+		return 0;
+	}
+
+	return -1;
+}
+
+void intel_microcode_load_unlocked(const void *microcode_patch)
+{
+	u32 current_rev;
 	const struct microcode *m = microcode_patch;
 
-	if (!m)
+	if (!m) {
+		printk(BIOS_WARNING, "microcode: failed because no ucode was found\n");
 		return;
+	}
 
 	current_rev = read_microcode_rev();
 
@@ -93,20 +115,9 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
 	}
 #endif
 
-	msr.lo = (unsigned long)m + sizeof(struct microcode);
-	msr.hi = 0;
-	wrmsr(IA32_BIOS_UPDT_TRIG, msr);
-
-	current_rev = read_microcode_rev();
-	if (current_rev == m->rev) {
-		printk(BIOS_INFO, "microcode: updated to revision "
-		    "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
-		    m->date & 0xffff, (m->date >> 24) & 0xff,
-		    (m->date >> 16) & 0xff);
-		return;
-	}
-
-	printk(BIOS_INFO, "microcode: Update failed\n");
+	printk(BIOS_INFO, "microcode: load microcode patch\n");
+	if (load_microcode(m) < 0)
+		printk(BIOS_ERR, "microcode: Update failed\n");
 }
 
 uint32_t get_current_microcode_rev(void)
@@ -206,7 +217,6 @@ static const void *find_cbfs_microcode(void)
 			struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
 
 			for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
-
 				if ((sig == entry->sig) && (pf & entry->pf)) {
 					return ucode_updates;
 				}
@@ -250,6 +260,24 @@ void intel_update_microcode_from_cbfs(void)
 	spin_unlock(&microcode_lock);
 }
 
+void intel_reload_microcode(void)
+{
+	if (!CONFIG(RELOAD_MICROCODE_PATCH))
+		return;
+
+	const struct microcode *m = intel_microcode_find();
+
+	if (!m) {
+		printk(BIOS_WARNING, "microcode: failed because no ucode was found\n");
+		return;
+	}
+
+	printk(BIOS_INFO, "microcode: Re-load microcode patch\n");
+
+	if (load_microcode(m) < 0)
+		printk(BIOS_ERR, "microcode: Re-load failed\n");
+}
+
 #if ENV_RAMSTAGE
 __weak int soc_skip_ucode_update(u32 current_patch_id,
 	u32 new_patch_id)

diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c
@@ -185,7 +185,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * IRONLAKE_BCLK + ratio / 3;

diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
@@ -286,7 +286,6 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
 		clock = ratio * SANDYBRIDGE_BCLK;

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -324,7 +324,6 @@ static void model_206ax_report(void)
 
 static void model_206ax_init(struct device *cpu)
 {
-
 	/* Clear out pending MCEs */
 	/* This should only be done on a cold boot */
 	mca_clear_status();

diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -89,7 +89,6 @@ static void configure_misc(void)
 	msr = rdmsr(IA32_PECI_CTL);
 	msr.lo |= 1;
 	wrmsr(IA32_PECI_CTL, msr);
-
 }
 
 #define PIC_SENS_CFG	0x1aa

diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c
@@ -244,7 +244,6 @@ int read_l2(u32 address)
 	/* If OK then get the result from BBL_CR_ADDR */
 	msr = rdmsr(BBL_CR_ADDR);
 	return (msr.lo >> 0x15);
-
 }
 
 /* Write data into the L2 controller register at address */
@@ -270,7 +269,6 @@ int write_l2(u32 address, u32 data)
 	 */
 
 	for (i = 0; i < v2; i++) {
-
 		u32 data1, data2;
 		// Bits legend
 		// data1   = ffffffff
@@ -352,7 +350,6 @@ int calculate_l2_cache_size(void)
 		 */
 		for (cache_setting = BBLCR3_L2_SIZE_256K;
 		     cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) {
-
 			eax = bblcr3 | cache_setting;
 			msr.lo = eax;
 			wrmsr(BBL_CR_CTL3, msr);
@@ -726,7 +723,6 @@ int p6_configure_l2_cache(void)
 	/* Write to all cache lines to initialize */
 
 	while (cache_size > 0) {
-
 		/* Each cache line is 32 bytes. */
 		cache_size -= 32;
 

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -31,10 +31,16 @@ config DEFAULT_X2APIC_RUNTIME
 	help
 	  Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_RUNTIME.
 
+config DEFAULT_X2APIC_LATE_WORKAROUND
+	def_bool n
+	help
+	  Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_LATE_WORKAROUND.
+
 choice LAPIC_ACCESS_MODE
 	prompt "APIC operation mode"
 	default X2APIC_ONLY if DEFAULT_X2APIC
 	default X2APIC_RUNTIME if DEFAULT_X2APIC_RUNTIME
+	default X2APIC_LATE_WORKAROUND if DEFAULT_X2APIC_LATE_WORKAROUND
 	default XAPIC_ONLY
 
 config XAPIC_ONLY
@@ -51,6 +57,17 @@ config X2APIC_RUNTIME
 	bool
 	depends on PARALLEL_MP
 
+config X2APIC_LATE_WORKAROUND
+	prompt "Use XAPIC for AP bringup, then change to X2APIC"
+	bool
+	depends on PARALLEL_MP && MAX_CPUS < 256
+	help
+	  Choose this option if the platform supports dynamic switching between
+	  XAPIC to X2APIC. The initial Application Processors (APs) are configured
+	  in XAPIC mode at reset and later enable X2APIC as a CPU feature.
+	  All access mechanisms between XAPIC (mmio) and X2APIC (msr) switches
+	  at runtime when this option is enabled.
+
 endchoice
 
 config UDELAY_LAPIC

diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
@@ -9,10 +9,10 @@
 #include <smp/node.h>
 #include <stdint.h>
 
-void enable_lapic(void)
+void enable_lapic_mode(bool try_set_x2apic)
 {
 	uintptr_t apic_base;
-	bool use_x2apic;
+	bool use_x2apic = false;
 	msr_t msr;
 
 	msr = rdmsr(LAPIC_BASE_MSR);
@@ -30,12 +30,8 @@ void enable_lapic(void)
 	apic_base = msr.lo & LAPIC_BASE_MSR_ADDR_MASK;
 	ASSERT(apic_base == LAPIC_DEFAULT_BASE);
 
-	if (CONFIG(XAPIC_ONLY)) {
-		use_x2apic = false;
-	} else {
+	if (try_set_x2apic)
 		use_x2apic = !!(cpu_get_feature_flags_ecx() & CPUID_X2APIC);
-		ASSERT(CONFIG(X2APIC_RUNTIME) || use_x2apic);
-	}
 
 	if (use_x2apic == !!(msr.lo & LAPIC_BASE_MSR_X2APIC_MODE)) {
 		printk(BIOS_INFO, "LAPIC 0x%x in %s mode.\n", lapicid(),
@@ -52,6 +48,16 @@ void enable_lapic(void)
 
 }
 
+void enable_lapic(void)
+{
+	bool try_set_x2apic = true;
+
+	if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND))
+		try_set_x2apic = false;
+
+	enable_lapic_mode(try_set_x2apic);
+}
+
 void disable_lapic(void)
 {
 	msr_t msr;

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -334,7 +334,6 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
 
 		udelay(10);
 	}
-
 }
 
 static void wait_other_cpus_stop(struct bus *cpu_bus)

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
@@ -675,23 +675,23 @@ struct mp_state {
 	size_t perm_smsize;
 	size_t smm_save_state_size;
 	uintptr_t reloc_start32_offset;
-	int do_smm;
+	bool do_smm;
 } mp_state;
 
-static int is_smm_enabled(void)
+static bool is_smm_enabled(void)
 {
 	return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm;
 }
 
 static void smm_disable(void)
 {
-	mp_state.do_smm = 0;
+	mp_state.do_smm = false;
 }
 
 static void smm_enable(void)
 {
 	if (CONFIG(HAVE_SMI_HANDLER))
-		mp_state.do_smm = 1;
+		mp_state.do_smm = true;
 }
 
 /*

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
@@ -343,7 +343,6 @@ static void commit_fixed_mtrrs(void)
 		wrmsr(msr_index[i], fixed_msrs[i]);
 	enable_cache();
 	fixed_mtrrs_hide_amd_rwdram();
-
 }
 
 void x86_setup_fixed_mtrrs_no_enable(void)

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -822,36 +822,38 @@ void show_all_devs_resources(int debug_level, const char *msg)
 	}
 }
 
-void fixed_mem_resource(struct device *dev, unsigned long index,
-			unsigned long basek, unsigned long sizek,
-			unsigned long type)
+const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
+				uint64_t base, uint64_t size, unsigned long flags)
 {
 	struct resource *resource;
-
-	if (!sizek)
-		return;
+	if (!size)
+		return NULL;
 
 	resource = new_resource(dev, index);
-	resource->base = ((resource_t)basek) << 10;
-	resource->size = ((resource_t)sizek) << 10;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-		 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	resource->base = base;
+	resource->size = size;
+	resource->flags = IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
+	resource->flags |= flags;
+
+	printk(BIOS_SPEW, "dev: %s, index: 0x%lx, base: 0x%llx, size: 0x%llx\n",
+	       dev_path(dev), resource->index, resource->base, resource->size);
 
-	resource->flags |= type;
+	return resource;
 }
 
-void fixed_io_resource(struct device *dev, unsigned long index,
-			unsigned long base, unsigned long size)
+const struct resource *lower_ram_end(struct device *dev, unsigned long index, uint64_t end)
 {
-	struct resource *resource;
+	return ram_from_to(dev, index, 0, end);
+}
 
-	resource = new_resource(dev, index);
-	resource->base = (resource_t)base;
-	resource->size = (resource_t)size;
-	resource->limit = resource->base + resource->size - 1;
-	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED |
-		 IORESOURCE_STORED | IORESOURCE_ASSIGNED |
-		 IORESOURCE_RESERVE;
+const struct resource *upper_ram_end(struct device *dev, unsigned long index, uint64_t end)
+{
+	if (end <= 4ull * GiB)
+		return NULL;
+
+	printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (end - 4ull * GiB) / MiB);
+
+	return ram_from_to(dev, index, 4ull * GiB, end);
 }
 
 void mmconf_resource(struct device *dev, unsigned long index)
-Original file line number
+Diff line change
@@ Expand Up @@
     		udelay(10);
     	}
     }
     static void wait_other_cpus_stop(struct bus *cpu_bus)
@@ Expand Down @@