480 changes: 0 additions & 480 deletions Documentation/Kconfig.tex
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30 changes: 3 additions & 27 deletions Documentation/Makefile
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Expand Up @@ -7,7 +7,7 @@ PDFLATEX=pdflatex -t a4

FIGS=codeflow.pdf hypertransport.pdf

all: corebootPortingGuide.pdf Kconfig.pdf
all: corebootPortingGuide.pdf

SVG2PDF=$(shell which svg2pdf)
INKSCAPE=$(shell which inkscape)
Expand Down Expand Up @@ -39,41 +39,17 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
$(PDFLATEX) corebootBuildingGuide.tex

Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
$(PDFLATEX) $<

# quick, somebody! make me a macro!
mainboardkconfig.tex: ../src/mainboard/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@

skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@

cpukconfig.tex: ../src/cpu/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@

socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@

sphinx:
$(MAKE) -f Makefile.sphinx html

clean-sphinx:
$(MAKE) -f Makefile.sphinx clean

clean: clean-sphinx
rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex
rm -f *.aux *.idx *.log *.toc *.out $(FIGS)

distclean: clean
rm -f corebootPortingGuide.pdf Kconfig.pdf
rm -f corebootPortingGuide.pdf

livesphinx:
$(MAKE) -f Makefile.sphinx livehtml
5 changes: 3 additions & 2 deletions Documentation/Makefile.sphinx
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Expand Up @@ -57,9 +57,10 @@ html:

.PHONY: livehtml
livehtml:
$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
@echo "Starting sphinx-autobuild. The HTML pages are in $(BUILDDIR)."
@echo "Press Ctrl-C to stop."
@echo
@echo "Autobuild finished. The HTML pages are in $(BUILDDIR)."
$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)

.PHONY: dirhtml
dirhtml:
Expand Down
8 changes: 8 additions & 0 deletions Documentation/arch/index.md
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@@ -0,0 +1,8 @@
# Architecture-specific documentation

This section contains documentation about coreboot on specific CPU
architectures.

## RISC-V

- [RISC-V documentation](riscv/index.md)
21 changes: 10 additions & 11 deletions Documentation/arch/riscv/index.md
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@@ -1,6 +1,6 @@
# RISCV architecture documentation
# RISC-V architecture documentation

This section contains documentation about coreboot on RISCV architecture.
This section contains documentation about coreboot on RISC-V architecture.

## Mode usage
All stages run in M mode.
Expand All @@ -17,7 +17,7 @@ will have been done. These payloads rely on the SBI and can not replace it.
## Stage handoff protocol
On entry to a stage or payload,
* all harts are running.
* A0 is the hart ID
* A0 is the hart ID.
* A1 is the pointer to the Flattened Device Tree (FDT).

## Additional payload handoff requirements
Expand All @@ -27,21 +27,20 @@ The location of cbmem should be placed in a node in the FDT.
Traps are delegated in the ramstage.

## SMP within a stage
At the beginning of each stage, all harts save 0 are spinning in a loop on a semaphore.
At the end of the stage harts 1..max are released by changing the
semaphore.
At the beginning of each stage, all harts save 0 are spinning in a loop on
a semaphore. At the end of the stage harts 1..max are released by changing
the semaphore.

A possible way to do this is to have a pointer to a struct containing variables, e.g.
A possible way to do this is to have a pointer to a struct containing
variables, e.g.

```c
struct blocker {
void (*fn)(); // never returns
}
```

The hart blocks until fn is non-null, and then calls it.
If fn returns we will panic if possible, but behavior
is largely undefined.
The hart blocks until fn is non-null, and then calls it. If fn returns, we
will panic if possible, but behavior is largely undefined.

Only hart 0 runs through most of the code in each stage.

18 changes: 12 additions & 6 deletions Documentation/conf.py
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@@ -1,5 +1,6 @@
# -*- coding: utf-8 -*-
import subprocess
from recommonmark.parser import CommonMarkParser

# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
Expand Down Expand Up @@ -156,9 +157,14 @@
'Miscellaneous'),
]

source_parsers = {
'.md': 'recommonmark.parser.CommonMarkParser',
}
enable_auto_toc_tree = True

class MyCommonMarkParser(CommonMarkParser):
# remove this hack once upsteam RecommonMark supports inline code
def visit_code(self, mdnode):
from docutils import nodes
n = nodes.literal(mdnode.literal, mdnode.literal)
self.current_node.append(n)

# Documents to append as an appendix to all manuals.
#
Expand All @@ -176,14 +182,14 @@
#
# texinfo_no_detailmenu = False

enable_auto_toc_tree = True


def setup(app):
from recommonmark.transform import AutoStructify
app.add_source_parser('.md', MyCommonMarkParser)

app.add_config_value('recommonmark_config', {
'enable_auto_toc_tree': True,
'enable_auto_doc_ref': True,
'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
'enable_eval_rst': True,
'url_resolver': lambda url: '/' + url
}, True)
Expand Down
28 changes: 28 additions & 0 deletions Documentation/flash_tutorial/ext_power.md
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@@ -0,0 +1,28 @@
# Flashing firmware externally supplying direct power

**WARNING:** Never use a high current rated power supply, like PC ATX power
supply. It'll literally melt your PCB traces on short circuit.

On some mainboards the flash IC Vcc pin is connected to a diode, which prevents
powering the rest of the board.

![][flash_ic_diode]

Please have a look at the mainboard specific documentation for details.

On those boards it's safe to use a programmer and supply power externally.

**WARNING:** Verify that you apply the correct voltage!

## USB programmer
USB programmers are usually current limited by the host USB hub. On USB 2.0
ports the limit is 500mA, which is sufficient to power the flash. Those are
the best choice as they are stateless and have a fast power on reset cycle.

## Single board computers (like BeagleBone Black / RPi)
Be careful when connecting a flash chip, especially when using a Pomona
test-clip. A short circuit or overcurrent (250mA) causes a brown-out reset,
resulting in a reboot of the running operating system (and possible loss of
remote shell).

[flash_ic_diode]: flash_ic_diode.svg
23 changes: 23 additions & 0 deletions Documentation/flash_tutorial/ext_standalone.md
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@@ -0,0 +1,23 @@
# Flashing firmware standalone

If none of the other methods work, there are three possibilities:

## Desolder
You must remove or desolder the flash IC before you can flash it.
It's recommended to solder a socket in place of the flash IC.

When flashing the IC, always connect all input pins.
If in doubt, pull /WP, /HOLD, /RESET and alike up towards Vcc.

## SPI flash emulator
If you are a developer, you might want to use an [EM100Pro] instead, which sets
the onboard flash on hold, and allows to run custom firmware.
It provides a very fast development cycle without actually writing to flash.

## SPI flash overwrite
It is possible to set the onboard flash on hold and use another flash chip.
Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC
low, and /HOLD of your replacement flash IC high.


[EM100Pro]: https://www.dediprog.com/product/EM100Pro
61 changes: 61 additions & 0 deletions Documentation/flash_tutorial/flash_ic_diode.svg
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105 changes: 105 additions & 0 deletions Documentation/flash_tutorial/index.md
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@@ -0,0 +1,105 @@
# Flashing firmware tutorial

Updating the firmware is possible using the **internal method**, where the updates
happen from a running system, or using the **external method**, where the system
is in a shut down state and an external programmer is attached to write into the
flash IC.

## Contents

* [Flashing internaly](int_flashrom.md)
* [Flashing firmware standalone](ext_standalone.md)
* [Flashing firmware externally supplying direct power](ext_power.md)
* [Flashing firmware externally without supplying direct power](no_ext_power.md)

## General advice

* It's recommended to only flash the BIOS region.
* Always verify the firmware image.
* If you flash externally and have transmission errors:
* Use short wires
* Reduce clock frequency
* Check power supply
* Make sure that there are no other bus masters (EC, ME, SoC, ...)

## Internal method

This method using [flashrom] is available on many platforms, as long as they
aren't locked down.

There are various protection schemes that make it impossible to modify or
replace a firmware from a running system. coreboot allows to disable these
mechanisms, making it possible to overwrite (or update) the firmware from a
running system.

Usually you must use the **external method** once to install a retrofitted
coreboot and then you can use the **internal method** for future updates.

There are multiple ways to update the firmware:
* Using flashrom's *internal* programmer to directly write into the firmware
flash IC, running on the target machine itself
* A proprietary software to update the firmware, running on the target machine
itself
* A UEFI firmware update capsule

More details on flashrom's
* [internal programmer](int_flashrom.md)

## External method

External flashing is possible on many platforms, but requires disassembling
the target hardware. You need to buy a flash programmer, that
exposes the same interface as your flash IC (likely SPI).

Please also have a look at the mainboard-specific documentation for details.

After exposing the firmware flash IC, read the schematics and use one of the
possible methods:

* [Flashing firmware standalone](ext_standalone.md)
* [Flashing firmware externally supplying direct power](ext_power.md)
* [Flashing firmware externally without supplying direct power](no_ext_power.md)

**WARNING:** Using the wrong method or accidentally using the wrong pinout might
permanently damage your hardware!

## Using a layout file
On platforms where the flash IC is shared with other components you might want
to write only a part of the flash IC. On Intel for example there are IFD, ME and
GBE which don't need to be updated to install coreboot.
To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD
untouched, you can use a layout file, which can be created using ifdtool

```bash
ifdtool -f rom.layout coreboot.rom
```

and looks similar to:

```
00000000:00000fff fd
00500000:00bfffff bios
00003000:004fffff me
00001000:00002fff gbe
```

By specifying *-l* and *-i* [flashrom] writes a single region:
```bash
flashrom -l rom.layout -i bios -w coreboot.rom -p <programmer>
```

## Using an IFD to determine the layout
flashrom version 1.0 supports reading the layout from the IFD (first 4KiB of
the ROM). You don't need to manually specify a layout it, but it only works
under the following conditions:

* Only available on Intel ICH7+
* There's only one flash IC when flashing externally

```bash
flashrom --ifd -i bios -w coreboot.rom -p <programmer>
```

**TODO** explain FMAP regions, normal/fallback mechanism, flash lock mechanisms

[flashrom]: https://www.flashrom.org/Flashrom
19 changes: 19 additions & 0 deletions Documentation/flash_tutorial/int_flashrom.md
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@@ -0,0 +1,19 @@
# Flashing firmware internally

**WARNING:** If you flash a broken firmware and have no recovery mechanism, you
must use the **external method** to flash a working firmware again.

## Using flashrom
This method does only work on Linux, if it isn't locked down.
You may also need to boot with 'iomem=relaxed' in the kernel command
line if CONFIG_IO_STRICT_DEVMEM is set.


For more details please also check [flashrom's wiki].
Use the programmer *internal* to flash *coreboot.rom* internally:

```bash
flashrom -p internal -w coreboot.rom
```

[flashrom's wiki]: https://www.flashrom.org/Flashrom
22 changes: 22 additions & 0 deletions Documentation/flash_tutorial/no_ext_power.md
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@@ -0,0 +1,22 @@
# Flashing firmware externally supplying no power

On some mainboards the flash IC's Vcc pin is connected to the internal
power-rail, powering the entire board if the flash IC is powered externally.
Likely it powers other chips which access the flash IC, preventing the external
programmer from reading/writing the chip. It also violates the components'
power sequence, bringing the ICs into an undefined state.

![][flash_ic_no_diode]

Please have a look at the mainboard specific documentation for details.

On those boards it's recommended to use a programmer without supplying power
externally.

The key to read and write the flash IC is to put the machine into *S3* sleep-
state or *S5* sleep-state *maybe* with Wake-On-LAN enabled.
Another option that sometimes works is to keep the device in reset. This method requires
knowledge of the board schematics and might require hardware modifications.
Use a multimeter to make sure the flash IC is powered in those sleep states.

[flash_ic_no_diode]: flash_ic_no_diode.svg
16 changes: 8 additions & 8 deletions Documentation/getting_started/gerrit_guidelines.md
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Expand Up @@ -13,8 +13,8 @@ here, please discuss it in the mailing list to get this document updated.
Don't just assume that it's okay, even if someone on IRC says it is.


Summary:
--------
Summary
-------
These are the expectations for committing, reviewing, and submitting code
into coreboot git and gerrit. While breaking individual rules may not have
immediate consequences, the coreboot leadership may act on repeated or
Expand All @@ -33,8 +33,8 @@ addresses.
* Don’t submit patches that you know will break other platforms.


More detail:
------------
More detail
-----------
* Don't violate the licenses. If you're submitting code that you didn't
write yourself, make sure the license is compatible with the license of the
project you're submitting the changes to. If you’re submitting code that
Expand Down Expand Up @@ -98,8 +98,8 @@ must at least provide a path that will allow other platforms to continue
working.


Recommendations for gerrit activity:
------------------------------------
Recommendations for gerrit activity
-----------------------------------
These guidelines are less strict than the ones listed above. These are more
of the “good idea” variety. You are requested to follow the below
guidelines, but there will probably be no actual consequences if they’re
Expand Down Expand Up @@ -251,8 +251,8 @@ The script 'util/gitconfig/rebase.sh' can be used to help automate this.
Other tags such as 'Commit-Queue' can simply be removed.


Expectations contributors should have:
--------------------------------------
Expectations contributors should have
-------------------------------------
* Don't expect that people will review your patch unless you ask them to.
Adding other people as reviewers is the easiest way. Asking for reviews for
individual patches in the IRC channel, or by sending a direct request to an
Expand Down
34 changes: 34 additions & 0 deletions Documentation/getting_started/writing_documentation.md
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Expand Up @@ -20,6 +20,9 @@ Please follow this official [guide] to install sphinx.
You will also need python-recommonmark for sphinx to be able to handle
markdown documenation.

The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and
recommonmark 0.4.0.

### Optional

Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly!
Expand Down Expand Up @@ -47,6 +50,11 @@ Documentation:
12. Shouldn't cover implementation details; for details, the code is the
reference.

## Referencing markdown documents

Starting with Sphinx 1.6 recommonmark's *auto_doc_ref* feature is broken.
To reference documents use the TOC tree or inline RST code.

## Markdown and Tables

Under Sphinx markdown tables are not supported. Therefore you can use following
Expand All @@ -66,6 +74,32 @@ code block to write tables in reStructuredText and embed them into the markdown:
+------------+------------+-----------+
``` #just a code block is enough

## TocTree

To make sure that all documents are included into the final documentation, you
must reference each document from at least one *toctree*. The *toctree* must
only reference files in the same folder or in subfolders !
To create a toctree, simply use a bullet list or numbered list with a single
reference. References in regular text aren't considered as *toctree* .
This feature is enabled by recommonmark's *enable_auto_toc_tree* .

**Example toctree:**

```
* [Chapter 1](chapter1.md)
* [Chapter 2](chapter2.md)
* [Subchapter](sub/index.md)
```

```
1. [Chapter 1](chapter1.md)
2. [Chapter 2](chapter2.md)
```

If you do only reference the document, but do not include it in any toctree,
you'll see the following warning:
**WARNING: document isn't included in any toctree**

[coreboot]: https://coreboot.org
[Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation
[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
Expand Down
2 changes: 2 additions & 0 deletions Documentation/index.md
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Expand Up @@ -15,6 +15,7 @@ Contents:
* [ABI data consumption](abi-data-consumption.md)
* [GPIO toggling in ACPI AML](acpi/gpio.md)
* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
* [Architecture-specific documentation](arch/index.md)
* [Northbridge-specific documentation](northbridge/index.md)
* [System on Chip-specific documentation](soc/index.md)
* [Mainboard-specific documentation](mainboard/index.md)
Expand All @@ -23,3 +24,4 @@ Contents:
* [Vendorcode-specific documentation](vendorcode/index.md)
* [Utilities](util.md)
* [Release notes for past releases](releases/index.md)
* [Flashing firmware tutorial](flash_tutorial/index.md)
2 changes: 1 addition & 1 deletion Documentation/lessons/lesson1.md
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Expand Up @@ -144,7 +144,7 @@ hybrid configuration which may or may not work as expected.
### Step 6 summary - Build coreboot
You may notice that a number of other pieces are downloaded at the beginning of
the build process. These are the git submodules used in various coreboot builds.
By default, the BLOBS submodule is not downloaded. This git submodule may be
By default, the _blobs_ submodule is not downloaded. This git submodule may be
required for other builds for microcode or other binaries. To enable downloading
this submodule, select the option "Allow use of binary-only repository" in the
"General Setup" menu of Kconfig
Expand Down
43 changes: 27 additions & 16 deletions Documentation/lib/payloads/fit.md
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Expand Up @@ -25,7 +25,7 @@ The section must be named in order to be found by the FIT parser:

The FIT parser needs architecure support.
### aarch64
The source code can be found in ''src/arch/arm64/fit.c''.
The source code can be found in `src/arch/arm64/fit.c`.

On aarch64 the kernel (a section named 'kernel') must be in **Image**
format and it needs a devicetree (a section named 'fdt') to boot.
Expand Down Expand Up @@ -83,7 +83,7 @@ If no matching compat string is found, the default config is chosen.
## Building FIT image
The FIT image has to be built by calling ''mkimage''. You can use
The FIT image has to be built by calling `mkimage`. You can use
the following example configuration:
```
Expand Down Expand Up @@ -122,17 +122,17 @@ the following example configuration:
};
};
ramdisk-1 {
description = "Compressed Initramfs";
data = /incbin/("initramfs.cpio.xz");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "none";
load = <00000000>;
entry = <00000000>;
hash-1 {
algo = "sha1";
};
description = "Compressed Initramfs";
data = /incbin/("initramfs.cpio.xz");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "none";
load = <00000000>;
entry = <00000000>;
hash-1 {
algo = "sha1";
};
};
};

Expand All @@ -148,9 +148,20 @@ the following example configuration:
};
```
It includes a compressed initrd **initramfs.cpio.xz**, which will be
decompressed by the Linux kernel, a compressed kernel **Image.lzma**, which will
be decompressed by the FIT loader and an uncompressed devicetree blob.
Save it as ITS file `config.its` along with the other files defined here:
* target.dtb
* initramfs.cpio.xz
* Image.lzma
Generate the `uImage` that will be included into the CBFS by calling
```bash
mkimage -f config.its uImage
```

The generated file includes a compressed initrd **initramfs.cpio.xz**, which
will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**,
which will be decompressed by the FIT loader and an uncompressed devicetree blob.

[uImage.FIT]: https://raw.githubusercontent.com/u-boot/u-boot/master/doc/uImage.FIT/howto.txt
[U-Boot]: https://www.denx.de/wiki/U-Boot
23 changes: 23 additions & 0 deletions Documentation/mainboard/emulation/spike-riscv.md
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@@ -0,0 +1,23 @@
# Spike RISC-V emulator

[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.


## Installation

- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/>
- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>,
which are necessary in order to have a serial console
- Compile `riscv-fesvr` and then `riscv-isa-sim`


## Building coreboot and running it in Spike

- Configure coreboot and run `make` as usual
- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
convert coreboot to an ELF that Spike can load
- Run `spike -m1024 build/coreboot.elf`


[Spike]: https://github.com/riscv/riscv-isa-sim
[RISC-V]: https://riscv.org/
40 changes: 35 additions & 5 deletions Documentation/mainboard/gigabyte/ga-h61m-s2pv.md
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Expand Up @@ -9,27 +9,57 @@ from [Gigabyte].
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
| Socketed flash | No |
+---------------------+------------+
| Model | MX25L3206E |
+---------------------+------------+
| Size | 4 MiB |
+---------------------+------------+
| In circuit flashing | yes |
| In circuit flashing | Yes |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Write protection | No |
+---------------------+------------+
| Dual BIOS feature | Yes |
+---------------------+------------+
| Internal flashing | yes |
| Internal flashing | Yes |
+---------------------+------------+
```

### Internal programming

The main SPI flash can be accessed using [flashrom].
The main SPI flash can be accessed using [flashrom]. The DualBIOS backup flash
chip is accessible as well using the `dualbiosindex` programmer parameter.
Since the flash recovery mechanism works even with coreboot installed on the
main flash chip (it still restores the vendor UEFI though), it is useful to
leave the backup chip untouched.

### Notes about the original firmware

The original IFD defines the BIOS region as the whole flash chip. While this is
not an issue if flashing a complete image, it confuses flashrom and trashes the
flash chip's contents when using the --ifd option. However, this can be easily
fixed by reading the IFD with flashrom, editing the correct values into it with
ifdtool and then reflashing it.

Create a layout.txt with the following contents:

00000000:00000fff fd
00180000:003fffff bios
00001000:0017ffff me

After that, simply run:

```bash
sudo flashrom -p internal --ifd -i fd -r ifd.rom
ifdtool -n layout.txt ifd.rom
sudo flashrom -p internal --ifd -i fd -w ifd.rom.new
```

After flashing, power cycle the computer to ensure the new IFD is being used.
If only a reboot is done, the old IFD layout is still seen by flashrom, even if
the IFD on the flash chip is correctly defining the new region layout.

## Technology

Expand All @@ -43,7 +73,7 @@ The main SPI flash can be accessed using [flashrom].
+------------------+--------------------------------------------------+
| SuperIO | ITE IT8728F |
+------------------+--------------------------------------------------+
| EC | |
| EC | None |
+------------------+--------------------------------------------------+
| Coprocessor | Intel ME |
+------------------+--------------------------------------------------+
Expand Down
24 changes: 24 additions & 0 deletions Documentation/mainboard/index.md
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Expand Up @@ -10,6 +10,12 @@ This section contains documentation about coreboot on specific mainboards.

- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)

## Emulation

The boards in this section are not real mainboards, but emulators.

- [Spike RISC-V emulator](emulation/spike-riscv.md)

## Foxconn

- [D41S](foxconn/d41s.md)
Expand All @@ -18,10 +24,28 @@ This section contains documentation about coreboot on specific mainboards.

- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)

## Open Cellular

- [Elgon](opencellular/elgon.md)

## HP

- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)

## Lenovo

- [T4xx common](lenovo/t4xx_series.md)

### Sandy Bridge series

- [T420](lenovo/t420.md)
- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md)

### Ivy Bridge series

- [T430](lenovo/t430.md)
- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)

## SiFive

- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
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@@ -0,0 +1,16 @@
# Lenovo T420

## Flashing instructions
You have to disassemble the whole device, as the flash IC is on the bottom
of the mainboard.

For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and

```eval_rst
:doc:`../../flash_tutorial/ext_power`
```

Steps to access the flash IC are described here [T4xx series].

[T4xx series]: t4xx_series.md
[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md
15 changes: 15 additions & 0 deletions Documentation/mainboard/lenovo/t430.md
View file
@@ -0,0 +1,15 @@
# Lenovo T430

## Flashing instructions
You have to disassemble the whole device, as the flash ICs are on the bottom
of the mainboard.

For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and
```eval_rst
:doc:`../../flash_tutorial/ext_power`
```

Steps to access the flash IC are described here [T4xx series].

[T4xx series]: t4xx_series.md
[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md
20 changes: 20 additions & 0 deletions Documentation/mainboard/lenovo/t4xx_series.md
View file
@@ -0,0 +1,20 @@
# Lenovo T4xx series disassembly instructions

A skilled engineer takes around 40 minutes to disassemble, flash and reassemble
the whole device.

## Steps to access the flash IC

* Unplug the main battery
* Remove the harddisk, CDROM, ExpressCard, SIM-card, SDcard, SmartCard, ...
* Open the bottom flap and remove the keyboard screw
* Remove the keyboard
* Remove the screen
* Remove the top enclosure
* Remove the CMOS battery
* Remove the speakers
* Remove WWAN and WIFI card
* Remove the CPU fan
* Unplug the power cable
* Remove the bottom enclosure
* Flip the mainboard and remove the main frame
48 changes: 48 additions & 0 deletions Documentation/mainboard/lenovo/xx20_series.md
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@@ -0,0 +1,48 @@
# Lenovo Sandy Bridge series

## Flashing coreboot
```eval_rst
+---------------------+--------------------+
| Type | Value |
+=====================+====================+
| Socketed flash | no |
+---------------------+--------------------+
| Size | 8 MiB |
+---------------------+--------------------+
| In circuit flashing | Yes |
+---------------------+--------------------+
| Package | SOIC-8 |
+---------------------+--------------------+
| Write protection | No |
+---------------------+--------------------+
| Dual BIOS feature | No |
+---------------------+--------------------+
| Internal flashing | Yes |
+---------------------+--------------------+
```

## Installation instructions
* Update the EC firmware, as there's no support for EC updates in coreboot.
* Do **NOT** accidently swap pins or power on the board while a SPI flasher
is connected. It will destroy your device.
* It's recommended to only flash the BIOS region. In that case you don't
need to extract blobs from vendor firmware.
If you want to flash the whole chip, you need blobs when building
coreboot.
* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space
usable by coreboot.
* ROM chip size should be set to 8MiB.

```eval_rst
Please also have a look at :doc:`../../flash_tutorial/index`.
```

## Flash layout
There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions.
On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
region. The update is then written into the EC once.

![][fl]

[fl]: flashlayout_xx20.svg

76 changes: 76 additions & 0 deletions Documentation/mainboard/lenovo/xx30_series.md
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@@ -0,0 +1,76 @@
# Lenovo Ivy Bridge series

## Flashing coreboot
```eval_rst
+---------------------+--------------------------------+
| Type | Value |
+=====================+================================+
| Socketed flash | no |
+---------------------+--------------------------------+
| Size | 8 MiB + 4MiB |
+---------------------+--------------------------------+
| In circuit flashing | Yes |
+---------------------+--------------------------------+
| Package | SOIC-8 |
+---------------------+--------------------------------+
| Write protection | No |
+---------------------+--------------------------------+
| Dual BIOS feature | No |
+---------------------+--------------------------------+
| Internal flashing | Yes |
+---------------------+--------------------------------+
```

## Installation instructions
* Update the EC firmware, as there's no support for EC updates in coreboot.
* Do **NOT** accidently swap pins or power on the board while a SPI flasher
is connected. It will permanently brick your device.
* It's recommended to only flash the BIOS region. In that case you don't
need to extract blobs from vendor firmware.
If you want to flash the whole chip, you need blobs when building
coreboot.
* The *Flash layout* shows that by default 7MiB of space are available for
the use with coreboot.
* In that case you only want to use a part of the BIOS region that must not
exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
* ROM chip size should be set to 12MiB.

```eval_rst
Please also have a look at :doc:`../../flash_tutorial/index`.
```

## Splitting the coreboot.rom

To split the coreboot.rom into two images (one for the 8MiB and one for the
4 MiB flash IC), run the following commands:

```bash
dd of=top.rom bs=1M if=build/coreboot.rom skip=8
dd of=bottom.rom bs=1M if=build/coreboot.rom count=8
```

That gives one ROM for each flash IC, where *top.rom* is the upper part of the
flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part
of the flash image, that resides on the 8 MiB flash.

## Dumping a full ROM

If you flash externally you need to read both flash chips to get two images
(one for the 8MiB and one for the 4 MiB flash IC), and then run the following
command to concatenate the files:

```bash
cat bottom.rom top.rom > firmware.rom
```

## Flash layout
There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and
BIOS region. These two flash ICs appear as a single 12MiB when flashing
internally.
On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
region. The update is then written into the EC once.

![][fl]

[fl]: flashlayout_xx30.svg

84 changes: 84 additions & 0 deletions Documentation/mainboard/opencellular/elgon.md
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@@ -0,0 +1,84 @@
# Elgon

This page describes how to run coreboot on the [Elgon] compute board
from [OpenCellular].

## TODO

* Add hard reset control

## Flashing coreboot

```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Model | W25Q128 |
+---------------------+------------+
| Size | 16 MiB |
+---------------------+------------+
| In circuit flashing | yes |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Write protection | No |
+---------------------+------------+
| Dual BIOS feature | No |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
```

### Internal programming

The SPI flash can be accessed using [flashrom].

### External programming

The EVT board does have a pinheader to flash the SOIC-8 in circuit.
Directly connecting a Pomona test-clip on the flash is also possible.

**Total board view of EVT**

![][elgon1]

[elgon1]: elgon1.jpg

**Closeup view of SOIC-8 flash IC and USB serial connector of EVT (marked blue)**

![][elgon2]

[elgon2]: elgon2.jpg


**SPI header (marked blue)**

![][elgon_conn_j9_pcb]

[elgon_conn_j9_pcb]: elgon_conn_j9_pcb.jpg

**SPI header pinout**

Dediprog compatible pinout.

![][elgon_conn_j9]

[elgon_conn_j9]: elgon_conn_j9.png

## Technology

```eval_rst
+---------------+----------------------------------------+
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
+---------------+----------------------------------------+
| CPU | Cavium ARMv8-Quadcore `CN81XX`_ |
+---------------+----------------------------------------+
.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
```

[Elgon]: https://github.com/Telecominfraproject/OpenCellular
[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
[flashrom]: https://flashrom.org/Flashrom
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4 changes: 2 additions & 2 deletions Documentation/mainboard/sifive/hifive-unleashed.md
View file
Expand Up @@ -96,8 +96,8 @@ console in certain situations.

[HiFive Unleashed]: https://www.crowdsupply.com/sifive/hifive-unleashed
[SiFive]: https://www.sifive.com/
[Getting Started Guide]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-getting-started-guide/
[Getting Started Guide]: https://sifive.cdn.prismic.io/sifive%2Ffa3a584a-a02f-4fda-b758-a2def05f49f9_hifive-unleashed-getting-started-guide-v1p1.pdf
[RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd
[OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a68e90381cc/bsp/env/freedom-u500-unleashed/openocd.cfg
[flashrom]: https://flashrom.org/Flashrom
[schematics]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-schematics/
[schematics]: https://sifive.cdn.prismic.io/sifive%2Ff7173056-bf37-4407-87cb-d5ab76abf61a_hifive-unleashed-a00-schematics.pdf
2 changes: 1 addition & 1 deletion Documentation/northbridge/intel/sandybridge/nri_features.md
View file
Expand Up @@ -8,7 +8,7 @@
* There might be errors to fix.
* Position in romstage doesn't matter.
2. mrc.bin raminit
* Closed Source (aka BLOB)
* Closed Source (aka blob)
* No known errors.
* Needs to be placed at fixed offset in romstage.

Expand Down
42 changes: 42 additions & 0 deletions Documentation/northbridge/intel/sandybridge/nri_registers.md
View file
Expand Up @@ -1522,13 +1522,20 @@ Please handle with care !
| 24:27| tWR |
+-----------+------------------------------------------------------------------+
| 29 | Command 3-state options |
| | |
| | - 0: Drive when channel is active, tri-state when inactive, |
| | |
| | - 1: Always drive command bus |
| | |
+-----------+------------------------------------------------------------------+
| 30:31| CMD stretch, |
| | |
| | - 00b: 1N, |
| | |
| | - 10b: 2N, |
| | |
| | - 11b: 3N |
| | |
+-----------+------------------------------------------------------------------+
```

Expand Down Expand Up @@ -1896,14 +1903,23 @@ Please handle with care !
| | plus burst length. |
+-----------+------------------------------------------------------------------+
| 8:10| PDWN_mode, selects the mode of power-down: |
| | |
| | - 0x0: No power down, |
| | |
| | - 0x1: APD, |
| | |
| | - 0x2: PPD, |
| | |
| | - 0x3: APD+PPD, |
| | |
| | - 0x4: Reserved, |
| | |
| | - 0x5: Reserved, |
| | |
| | - 0x6: PPD-DLLoff, |
| | |
| | - 0x7: APD+PPD+DLLof |
| | |
+-----------+------------------------------------------------------------------+
```

Expand Down Expand Up @@ -1973,19 +1989,31 @@ Please handle with care !
| Bit | Description |
+===========+==================================================================+
| 0:1| CH_A, defines the largest channel. |
| | |
| | - 00b: Channel 0, |
| | |
| | - 01b: Channel 1, |
| | |
| | - 10b: Channel 2 |
| | |
+-----------+------------------------------------------------------------------+
| 2:3| CH_B, defines the mid-size channel. |
| | |
| | - 00b: Channel 0, |
| | |
| | - 01b: Channel 1, |
| | |
| | - 10b: Channel 2 |
| | |
+-----------+------------------------------------------------------------------+
| 2:3| CH_C, defines the smallest channel. |
| | |
| | - 00b: Channel 0, |
| | |
| | - 01b: Channel 1, |
| | |
| | - 10b: Channel 2, CH_C is 10 if only 2 channels are supported |
| | |
+-----------+------------------------------------------------------------------+
```

Expand All @@ -2002,8 +2030,11 @@ Please handle with care !
| 0:7| DIMMA size in 256 MB multiples |
+-----------+------------------------------------------------------------------+
| 16 | DIMM A select (DAS) Slot to DIMM mapping, |
| | |
| | - 0: DIMMA, DIMMB, |
| | |
| | - 1: DIMMB, DIMMA |
| | |
+-----------+------------------------------------------------------------------+
| 17 | DIMM A number of ranks |
+-----------+------------------------------------------------------------------+
Expand All @@ -2025,9 +2056,13 @@ Please handle with care !
| | 20-27 to use for high rank interleave |
+-----------+------------------------------------------------------------------+
| 24:25| ECC, |
| | |
| | - 00b: No ECC active, |
| | |
| | - 01b: ECC is active on IO, |
| | |
| | - 11b: ECC is active on both IO and ECC logic |
| | |
+-----------+------------------------------------------------------------------+
```

Expand Down Expand Up @@ -2121,7 +2156,9 @@ Please handle with care !
| Bit | Description |
+===========+==================================================================+
| 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = |
| | |
| | ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] |
| | |
+-----------+------------------------------------------------------------------+
```

Expand All @@ -2138,7 +2175,9 @@ Please handle with care !
| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
+-----------+------------------------------------------------------------------+
| 8 | - 1: 100Mhz reference clock (Ivy Bridge only) |
| | |
| | - 0: 133Mhz reference clock |
| | |
+-----------+------------------------------------------------------------------+
| 31 | PLL busy |
+-----------+------------------------------------------------------------------+
Expand All @@ -2155,8 +2194,11 @@ Please handle with care !
| Bit | Description |
+===========+==================================================================+
| 0:7| Active multiplier: |
| | |
| | - 100Mhz [7,12], |
| | |
| | - 133Mhz [3,19] |
| | |
+-----------+------------------------------------------------------------------+
```

Expand Down
2 changes: 1 addition & 1 deletion Documentation/releases/index.md
View file
Expand Up @@ -12,6 +12,6 @@ Release notes for previous releases

Upcoming release
----------------
* [4.9 - November 2018](coreboot-4.9-relnotes.md)

Please add to the release notes as changes are added:
* [4.9 - November 2018](coreboot-4.9-relnotes.md)
4 changes: 2 additions & 2 deletions Documentation/soc/cavium/cn81xx/index.md
View file
Expand Up @@ -41,8 +41,8 @@ or romstage until DRAM has been set up. At the end of romstage the cachelines
are unlocked and the contents are flushed to DRAM.
Locked cachelines are never evicted.

The CAR setup is done in '''bootblock_custom.S''' and thus doesn't use the common
aarch64 '''bootblock.S''' code.
The CAR setup is done in `bootblock_custom.S` and thus doesn't use the common
aarch64 `bootblock.S` code.

## DRAM setup

Expand Down
3 changes: 3 additions & 0 deletions Documentation/util.md
View file
Expand Up @@ -77,6 +77,9 @@ partial deblobbing of Intel ME/TXE firmware images `Python`
* __nvidia__ - nvidia blob parsers
* __nvramtool__ - Reads and writes coreboot parameters and displaying
information from the coreboot table in CMOS/NVRAM. `C`
* __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo
ThinkPads. PMH7 is used for switching on and off the power of some
devices on the board such as dGPU. `C`
* __post__ - Userspace utility that can be used to test POST cards. `C`
* __qualcomm__ - CMM script to debug Qualcomm coreboot environments.
`CMM`
Expand Down
6 changes: 3 additions & 3 deletions Documentation/vendorcode/cavium/bdk.md
View file
@@ -1,7 +1,7 @@
# Cavium's BDK

## BDK
A part of Cavium's BDK can be found in '''src/vendorcode/cavium/bdk'''.
A part of Cavium's BDK can be found in `src/vendorcode/cavium/bdk`.
It does the **DRAM init** in romstage and the **PCIe**, **QLM**, **SLI**,
**PHY**, **BGX**, **SATA** init in ramstage.

Expand All @@ -11,9 +11,9 @@ compatible. The devicetree stores key-value pairs (see **bdk-devicetree.h**
for implementation details), where the key and the value are stored as strings.

The key-value pairs must be advertised in romstage and ramstage using the
'''bdk_config_set_fdt()''' method.
`bdk_config_set_fdt()` method.

The tool '''util/cavium/devicetree_convert.py''' can be used to convert a
The tool `util/cavium/devicetree_convert.py` can be used to convert a
devicetree to a key-value array.

## Modifications
Expand Down
5 changes: 3 additions & 2 deletions MAINTAINERS
View file
Expand Up @@ -124,10 +124,11 @@ M: Ronald Minnich <rminnich@gmail.com>
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
S: Maintained
F: src/arch/riscv/
F: src/soc/lowrisc
F: src/soc/sifive/
F: src/soc/ucb/
F: src/mainboard/emulation/*-riscv/
F: src/mainboard/lowrisc
F: src/mainboard/sifive/
F: util/riscv/

POWER8 ARCHITECTURE
M: Ronald Minnich <rminnich@gmail.com>
Expand Down
3 changes: 2 additions & 1 deletion Makefile.inc
View file
Expand Up @@ -195,7 +195,7 @@ ifeq ($(CONFIG_USE_BLOBS),y)
# this is necessary because 3rdparty/blobs is update=none, and so is ignored
# unless explicitly requested and enabled through --checkout
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
ifeq ($(CONFIG_MAINBOARD_USES_FSP2_0),y)
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
endif
endif
Expand Down Expand Up @@ -378,6 +378,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include
VBOOT_SOURCE ?= 3rdparty/vboot
CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
CPPFLAGS_common += -include $(src)/include/kconfig.h
CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
CPPFLAGS_common += -I3rdparty
CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\"

Expand Down
15 changes: 15 additions & 0 deletions configs/config.google_reef_cros
View file
@@ -0,0 +1,15 @@
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_REEF=y
CONFIG_CHROMEOS=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
CONFIG_ELOG_GSMI=y
CONFIG_ELOG_BOOT_COUNT=y
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
CONFIG_SPI_FLASH_SMM=y
# CONFIG_CONSOLE_SERIAL is not set
CONFIG_CMOS_POST=y
CONFIG_CMOS_POST_OFFSET=0x70
CONFIG_CMOS_POST_EXTRA=y
CONFIG_PAYLOAD_NONE=y
6 changes: 3 additions & 3 deletions configs/config.pcengines_apu1
View file
@@ -1,16 +1,16 @@
CONFIG_LOCALVERSION="v4.8.0.5"
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU1=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
CONFIG_IPXE_MASTER=y
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu2
View file
@@ -1,14 +1,13 @@
CONFIG_LOCALVERSION="v4.8.0.5"
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu3
View file
@@ -1,14 +1,13 @@
CONFIG_LOCALVERSION="v4.8.0.5"
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu4
View file
@@ -1,14 +1,13 @@
CONFIG_LOCALVERSION="v4.8.0.5"
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu5
View file
@@ -1,14 +1,13 @@
CONFIG_LOCALVERSION="v4.8.0.5"
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
Expand Down
4 changes: 3 additions & 1 deletion payloads/Kconfig
View file
Expand Up @@ -30,6 +30,7 @@ config PAYLOAD_ELF

config PAYLOAD_FIT
bool "A FIT payload"
depends on ARCH_ARM64
select PAYLOAD_FIT_SUPPORT
help
Select this option if you have a payload image (a FIT file) which
Expand All @@ -41,6 +42,7 @@ config PAYLOAD_FIT

config PAYLOAD_BAYOU
bool "Bayou"
depends on ARCH_X86
help
Select this option if you want to set bayou as your primary
payload.
Expand All @@ -64,7 +66,7 @@ config PAYLOAD_FILE
choice
prompt "Payload compression algorithm"
default COMPRESSED_PAYLOAD_LZMA
depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT
depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
help
Choose the compression algorithm for the chosen payloads.
You can choose between LZMA and LZ4.
Expand Down
6 changes: 3 additions & 3 deletions payloads/coreinfo/cbfs_module.c
View file
Expand Up @@ -69,7 +69,7 @@ static struct cbfile *getfile(struct cbfile *f)
return NULL;
if (f->magic == LARCHIVE_MAGIC)
return f;
f = (void *)f + ntohl(header->align);
f = (struct cbfile *)((u8 *)f + ntohl(header->align));
}
}

Expand All @@ -81,8 +81,8 @@ static struct cbfile *firstfile(void)

static struct cbfile *nextfile(struct cbfile *f)
{
f = (void *)f + ALIGN(ntohl(f->len) + ntohl(f->offset),
ntohl(header->align));
f = (struct cbfile *)((u8 *)f + ALIGN(ntohl(f->len) + ntohl(f->offset),
ntohl(header->align)));
return getfile(f);
}

Expand Down
1 change: 1 addition & 0 deletions payloads/external/FILO/Kconfig.name
View file
@@ -1,5 +1,6 @@
config PAYLOAD_FILO
bool "FILO"
depends on ARCH_X86
help
Select this option if you want to build a coreboot image
with a FILO payload. If you don't know what this is
Expand Down
5 changes: 1 addition & 4 deletions payloads/external/LinuxBoot/Kconfig
View file
Expand Up @@ -129,11 +129,8 @@ config LINUXBOOT_UROOT_FILES
initramfs.

config PAYLOAD_USERSPACE
string "LinuxBoot initramfs"
string
default "payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz"
help
The initramfs to use with the compiled kernel.
Useful for debugging or custom initramfs.

endif
endif
9 changes: 4 additions & 5 deletions payloads/external/LinuxBoot/Makefile
View file
Expand Up @@ -33,7 +33,7 @@ endif

OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy

all: payload
all: linuxboot

toolchain:
if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \
Expand All @@ -45,15 +45,14 @@ $(kernel_dir)/.config:
echo " WWW Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
mkdir -p $(kernel_dir)
ifeq ("$(wildcard $(kernel_dir)/README)","")
wget -qO- $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1
curl -s $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1
endif

config: $(kernel_dir)/.config
echo " CONFIG Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
ifneq ($(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE),)
cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config
endif
ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
else ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
cp x86/defconfig $(kernel_dir)/.config
else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
cp x86_64/defconfig $(kernel_dir)/.config
Expand Down Expand Up @@ -96,7 +95,7 @@ $(PWD)/$(CONFIG_PAYLOAD_USERSPACE):
echo "Building without u-root support"
endif

payload: $(project_dir)/kernel-image $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)
linuxboot: $(project_dir)/kernel-image $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)

clean:
if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi
Expand Down
1 change: 0 additions & 1 deletion payloads/external/LinuxBoot/arm64/defconfig
View file
Expand Up @@ -114,7 +114,6 @@ CONFIG_NET_DEVLINK=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_EXTRA_FIRMWARE="cpt8x-mc-ae.out cpt8x-mc-se.out"
CONFIG_DMA_CMA=y
CONFIG_MTD=y
CONFIG_MTD_NAND=y
Expand Down
14 changes: 12 additions & 2 deletions payloads/external/LinuxBoot/targets/u-root.mk
View file
Expand Up @@ -14,17 +14,27 @@

uroot_git_repo=https://github.com/u-root/u-root.git
uroot_dir=$(project_dir)/go/src/github.com/u-root/u-root
go_check=$(shell command -v go 1>/dev/null 2>&1 && echo go)
go_version=$(shell go version | sed -nr 's/.*go([0-9]+\.[0-9]+.?[0-9]?).*/\1/p' )
go_version_major=$(shell echo $(go_version) | sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\1/p')
go_version_minor=$(shell echo $(go_version) | sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\2/p')

project_dir=$(shell pwd)/linuxboot
project_name=u-root
go_path_dir=$(shell pwd)/linuxboot/go

all: build

check:
ifneq ($(go_check),go)
ifeq ("$(go_version)","")
printf "\n<<Please install Golang >= 1.9 for u-root mode>>\n\n"
exit 1
endif
ifeq ($(shell if [ $(go_version_major) -eq 1 ]; then echo y; fi),y)
ifeq ($(shell if [ $(go_version_minor) -lt 9 ]; then echo y; fi),y)
printf "\n Golang version $(go_version) currently installed.\n\
<<Please install Golang >= 1.9 for u-root mode>>\n\n"
exit 1
endif
endif
mkdir -p $(project_dir)/go/src/github.com/u-root

Expand Down
7 changes: 7 additions & 0 deletions payloads/external/LinuxBoot/x86_64/defconfig
View file
Expand Up @@ -99,6 +99,13 @@ CONFIG_SATA_AHCI=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
# CONFIG_SERIAL_8250_EXAR is not set
# CONFIG_SERIAL_8250_LPSS is not set
# CONFIG_SERIAL_8250_MID is not set
# CONFIG_SERIAL_8250_PNP is not set
CONFIG_SERIAL_8250=y
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_HW_RANDOM_AMD is not set
# CONFIG_HW_RANDOM_VIA is not set
Expand Down
1 change: 1 addition & 0 deletions payloads/external/linux/Kconfig.name
View file
@@ -1,5 +1,6 @@
config PAYLOAD_LINUX
bool "A Linux payload"
depends on ARCH_X86 || ARCH_ARM
help
Select this option if you have a Linux bzImage which coreboot
should run as soon as the basic hardware initialization
Expand Down
1 change: 1 addition & 0 deletions payloads/external/tianocore/Kconfig.name
View file
@@ -1,5 +1,6 @@
config PAYLOAD_TIANOCORE
bool "Tianocore coreboot payload package"
depends on ARCH_X86
help
Select this option if you want to build a coreboot image
with a Tianocore payload. If you don't know what this is
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/tianocore/Makefile
View file
Expand Up @@ -69,7 +69,7 @@ $(project_dir)/.version_$(TAG-y): fetch
for patch in $(CURDIR)/patches/*.patch; do \
echo "Applying $$patch"; \
cd $(project_dir); \
git am --keep-cr $$patch || \
git am --keep-cr --ignore-space-change $$patch || \
( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \
done; \
if ! [ "$(TAG-y)" = "origin/master" ] ; then \
Expand Down
63 changes: 35 additions & 28 deletions ...ches/05_CorebootPayloadPkg_noserial.patch → ...use-serial-output-for-Release-build.patch
View file
@@ -1,39 +1,46 @@
From 77f75370d6fbfefb04456f6e1c32c85d4bac8bf5 Mon Sep 17 00:00:00 2001
From: Matt Devo <matt.devillier@gmail.com>
Date: Thu, 23 Feb 2017 14:11:14 -0600
Subject: [PATCH] CorebootPayloadPkg: don't use serial output
From 147174ea833e14ef68a8c5f1366cfbd1468dd1c8 Mon Sep 17 00:00:00 2001
From: Wonkyu Kim <wonkyu.kim@intel.com>
Date: Wed, 10 Oct 2018 10:59:51 -0700
Subject: [PATCH] CorebootPayloadPkg: don't use serial output for Release build

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 2 +-
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 4 ++++
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 4 ++++
2 files changed, 8 insertions(+)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 1d80fc4f5c..ce360c9e9e 100644
index 6ddd64faf7a5..2e7055815add 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -261,7 +261,7 @@
#
################################################################################
[PcdsFeatureFlag]
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
@@ -261,7 +261,11 @@
#
################################################################################
[PcdsFeatureFlag]
+!if $(TARGET) == DEBUG
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 52b26eb3d0..a27b0873a1 100644
index 19c203e6cbb6..b00b7b0e1134 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -261,7 +261,7 @@
#
################################################################################
[PcdsFeatureFlag]
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
@@ -261,7 +261,11 @@
#
################################################################################
[PcdsFeatureFlag]
+!if $(TARGET) == DEBUG
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
--
2.13.2.725.g09c95d1e9-goog
2.17.1

14 changes: 9 additions & 5 deletions payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch
View file
@@ -1,13 +1,16 @@
From ef89b11ce6f93c96fbd1753a8006dd9c3da212e0 Mon Sep 17 00:00:00 2001
From 336ce69129206ea6cb5bea2a99c5f00e77850518 Mon Sep 17 00:00:00 2001
From: ReddestDream <reddestdream@gmail.com>
Date: Wed, 3 May 2017 00:13:28 -0400
Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being
overwritten

Exclude the bottom 4kb from being included in System Memory HoB
---
CorebootModulePkg/CbSupportPei/CbSupportPei.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
index 262e6b9..d3c5723 100755
index 831de89b21d1..e84b9b55288a 100755
--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c
+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
@@ -261,8 +261,9 @@ CbPeiEntryPoint (
Expand All @@ -20,7 +23,8 @@ index 262e6b9..d3c5723 100755
+ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000),
+ (UINT64)(0xA0000 - 0x1000)
);


--
2.17.0


--
2.14.0
18 changes: 1 addition & 17 deletions payloads/libpayload/arch/arm/gdb.c
View file
Expand Up @@ -39,23 +39,7 @@ static struct exception_state sentinel_exception_state;

static int gdb_exception_hook(u32 type)
{
/*
* If we were not resumed we are in deep trouble here. GDB probably told
* us to do something stupid and caused a reentrant exception. All we
* can do is just blindly send an error code and keep going. Eventually
* GDB will tell us to resume and we return right back to the original
* exception state ("jumping over" all the nested ones).
*/
if (gdb_state.connected && !gdb_state.resumed) {
static const char error_code[] = "E22"; /* EINVAL? */
static const struct gdb_message tmp_reply = {
.buf = (u8 *)error_code,
.used = sizeof(error_code),
.size = sizeof(error_code),
};
gdb_send_reply(&tmp_reply);
gdb_command_loop(gdb_state.signal); /* preserve old signal */
} else {
if (!gdb_handle_reentrant_exception()) {
if (type >= ARRAY_SIZE(type_to_signal) || !type_to_signal[type])
return 0;
exception_state_ptr = &sentinel_exception_state;
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/arch/arm64/Makefile.inc
View file
Expand Up @@ -30,8 +30,6 @@
CFLAGS += -march=armv8-a
arm64_asm_flags =

subdirs-y += lib/

head.o-y += head.S
libc-y += main.c sysinfo.c
libc-y += timer.c coreboot.c util.S
Expand Down
4 changes: 2 additions & 2 deletions payloads/libpayload/arch/arm64/cache.c
View file
Expand Up @@ -39,7 +39,7 @@
void tlb_invalidate_all(void)
{
/* TLBIALL includes dTLB and iTLB on systems that have them. */
tlbiall_current();
tlbiall_el2();
dsb();
isb();
}
Expand Down Expand Up @@ -119,7 +119,7 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)

void cache_sync_instructions(void)
{
uint32_t sctlr = raw_read_sctlr_current();
uint32_t sctlr = raw_read_sctlr_el2();
if (sctlr & SCTLR_C)
dcache_clean_all(); /* includes trailing DSB (assembly) */
else if (sctlr & SCTLR_I)
Expand Down
19 changes: 10 additions & 9 deletions payloads/libpayload/arch/arm64/exception.c
View file
Expand Up @@ -31,6 +31,8 @@
#include <libpayload.h>
#include <stdint.h>

u64 exception_stack[0x200] __attribute__((aligned(16)));
u64 *exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
extern unsigned int test_exc;

struct exception_handler_info
Expand All @@ -39,7 +41,7 @@ struct exception_handler_info
};

static exception_hook hook;
struct exception_state *exception_state;
struct exception_state exception_state;

static struct exception_handler_info exceptions[EXC_COUNT] = {
[EXC_SYNC_SP0] = { "_sync_sp_el0" },
Expand Down Expand Up @@ -81,21 +83,19 @@ static void print_regs(struct exception_state *state)

printf("ELR = 0x%016llx ESR = 0x%08llx\n",
state->elr, state->esr);
printf("FAR = 0x%016llx SPSR = 0x%08x\n",
raw_read_far_current(), raw_read_spsr_current());
printf("FAR = 0x%016llx SPSR = 0x%08llx\n",
raw_read_far_el2(), raw_read_spsr_el2());
for (i = 0; i < 30; i += 2) {
printf("X%02d = 0x%016llx X%02d = 0x%016llx\n",
i, state->regs[i], i + 1, state->regs[i + 1]);
}
printf("X30 = 0x%016llx SP = 0x%016llx\n",
state->regs[30], raw_read_sp_el0());
state->regs[30], state->sp);
}

void exception_dispatch(struct exception_state *state, int idx);
void exception_dispatch(struct exception_state *state, int idx)
{
exception_state = state;

if (idx >= EXC_COUNT) {
printf("Bad exception index %d.\n", idx);
} else {
Expand All @@ -110,7 +110,7 @@ void exception_dispatch(struct exception_state *state, int idx)
}
print_regs(state);
/* Few words below SP in case we need state from a returned function. */
dump_stack(raw_read_sp_el0() - 32, 512);
dump_stack(state->sp - 32, 512);

if (test_exc) {
state->elr += 4;
Expand All @@ -123,8 +123,9 @@ void exception_dispatch(struct exception_state *state, int idx)

void exception_init(void)
{
extern void* exception_table;
set_vbar(&exception_table);
extern uint64_t exception_table[];
raw_write_vbar_el2((uintptr_t)exception_table);
exception_set_state_ptr(&exception_state);
}

void exception_install_hook(exception_hook h)
Expand Down
163 changes: 100 additions & 63 deletions payloads/libpayload/arch/arm64/exception_asm.S
View file
Expand Up @@ -27,24 +27,25 @@
* SUCH DAMAGE.
*/

#define __ASSEMBLY__
#include <arch/lib_helpers.h>

.text
#include <arch/asm.h>
#include <arch/exception.h>

/* Macro for exception entry
* Store x30 before any branch
* Branch to exception_prologue to save rest of the registers
* Branch to exception_prologue to save rest and switch stacks
* Move exception id into x1
* Branch to exception_handler
* Branch to exception_dispatch (exception C entry point)
* Branch to exception_return to return from exception
*/
.macro eentry lbl id
.align 7
\lbl:
stp x30, xzr, [sp, #-16]!
/* Note: SP points to exception_state (see exception_set_state_ptr) */
str x30, [sp, #EXCEPTION_STATE_REG(30)]
bl exception_prologue
mov x1, \id
bl exception_handler
bl exception_dispatch
b exception_return
.endm

/* Exception table has 16 entries and each of 128 bytes
Expand Down Expand Up @@ -73,64 +74,100 @@ eentry irq_elx_32,#13
eentry fiq_elx_32,#14
eentry serror_elx_32,#15

exception_prologue:
/* Save all registers x0-x29 */
stp x28, x29, [sp, #-16]!
stp x26, x27, [sp, #-16]!
stp x24, x25, [sp, #-16]!
stp x22, x23, [sp, #-16]!
stp x20, x21, [sp, #-16]!
stp x18, x19, [sp, #-16]!
stp x16, x17, [sp, #-16]!
stp x14, x15, [sp, #-16]!
stp x12, x13, [sp, #-16]!
stp x10, x11, [sp, #-16]!
stp x8, x9, [sp, #-16]!
stp x6, x7, [sp, #-16]!
stp x4, x5, [sp, #-16]!
stp x2, x3, [sp, #-16]!
stp x0, x1, [sp, #-16]!

/* Save the exception reason on stack */
read_current x1, esr

/* Save the return address on stack */
read_current x0, elr
stp x0, x1, [sp, #-16]!
/* This code must match the layout of struct exception_state (minus x30) */
ENTRY(exception_prologue)
/* Save registers x0-x29 */
stp x28, x29, [sp, #EXCEPTION_STATE_REG(28)]
stp x26, x27, [sp, #EXCEPTION_STATE_REG(26)]
stp x24, x25, [sp, #EXCEPTION_STATE_REG(24)]
stp x22, x23, [sp, #EXCEPTION_STATE_REG(22)]
stp x20, x21, [sp, #EXCEPTION_STATE_REG(20)]
stp x18, x19, [sp, #EXCEPTION_STATE_REG(18)]
stp x16, x17, [sp, #EXCEPTION_STATE_REG(16)]
stp x14, x15, [sp, #EXCEPTION_STATE_REG(14)]
stp x12, x13, [sp, #EXCEPTION_STATE_REG(12)]
stp x10, x11, [sp, #EXCEPTION_STATE_REG(10)]
stp x8, x9, [sp, #EXCEPTION_STATE_REG(8)]
stp x6, x7, [sp, #EXCEPTION_STATE_REG(6)]
stp x4, x5, [sp, #EXCEPTION_STATE_REG(4)]
stp x2, x3, [sp, #EXCEPTION_STATE_REG(2)]
stp x0, x1, [sp, #EXCEPTION_STATE_REG(0)]

/* Save the stack pointer and SPSR */
mrs x1, sp_el0
mrs x0, spsr_el2
stp x0, x1, [sp, #EXCEPTION_STATE_SPSR]

/* Save return address (ELR) and exception syndrome */
mrs x1, esr_el2
mrs x0, elr_el2
stp x0, x1, [sp, #EXCEPTION_STATE_ELR]

/* Now switch to the actual exception stack. Keep a pointer to the
exception_state structure in x0 as an argument for dispatch(). */
mov x0, sp
adrp x1, exception_stack_end
ldr x1, [x1, :lo12:exception_stack_end]
msr SPSel, #0
mov sp, x1

ret
ENDPROC(exception_prologue)

exception_handler:
/* Save address of saved registers into x0
* This acts as first argument to exception_dispatch
*/
mov x0, sp
bl exception_dispatch

/* Pop return address saved on stack */
ldp x0, x1, [sp], #16
write_current elr, x0, x2
write_current esr, x1, x2
/* Pop exception reason saved on stack, followed by regs x0-x30 */
ldp x0, x1, [sp], #16
ldp x2, x3, [sp], #16
ldp x4, x5, [sp], #16
ldp x6, x7, [sp], #16
ldp x8, x9, [sp], #16
ldp x10, x11, [sp], #16
ldp x12, x13, [sp], #16
ldp x14, x15, [sp], #16
ldp x16, x17, [sp], #16
ldp x18, x19, [sp], #16
ldp x20, x21, [sp], #16
ldp x22, x23, [sp], #16
ldp x24, x25, [sp], #16
ldp x26, x27, [sp], #16
ldp x28, x29, [sp], #16
ldp x30, xzr, [sp], #16
ENTRY(exception_return)
/* Switch SP back to the exception_state structure */
msr SPSel, #1

/* Restore return address (ELR) -- skip ESR (unneeded for return) */
ldr x0, [sp, #EXCEPTION_STATE_ELR]
msr elr_el2, x0

/* Restore stack pointer and SPSR */
ldp x0, x1, [sp, #EXCEPTION_STATE_SPSR]
msr spsr_el2, x0
msr sp_el0, x1

/* Restore all registers (x0-x30) */
ldp x0, x1, [sp, #EXCEPTION_STATE_REG(0)]
ldp x2, x3, [sp, #EXCEPTION_STATE_REG(2)]
ldp x4, x5, [sp, #EXCEPTION_STATE_REG(4)]
ldp x6, x7, [sp, #EXCEPTION_STATE_REG(6)]
ldp x8, x9, [sp, #EXCEPTION_STATE_REG(8)]
ldp x10, x11, [sp, #EXCEPTION_STATE_REG(10)]
ldp x12, x13, [sp, #EXCEPTION_STATE_REG(12)]
ldp x14, x15, [sp, #EXCEPTION_STATE_REG(14)]
ldp x16, x17, [sp, #EXCEPTION_STATE_REG(16)]
ldp x18, x19, [sp, #EXCEPTION_STATE_REG(18)]
ldp x20, x21, [sp, #EXCEPTION_STATE_REG(20)]
ldp x22, x23, [sp, #EXCEPTION_STATE_REG(22)]
ldp x24, x25, [sp, #EXCEPTION_STATE_REG(24)]
ldp x26, x27, [sp, #EXCEPTION_STATE_REG(26)]
ldp x28, x29, [sp, #EXCEPTION_STATE_REG(28)]
ldr x30, [sp, #EXCEPTION_STATE_REG(30)]

/* Return from exception */
eret
ENDPROC(exception_return)

.global set_vbar
set_vbar:
write_current vbar, x0, x1
/*
* We have two stack pointers on AArch64: SP_EL0 (which despite the
* naming is used in all ELs) and SP_EL2. We can select which one to
* use by writing to SPSel. Normally we're using SP_EL0, but on
* exception entry it automatically switches to SP_EL2.
*
* It is important for exception reentrancy to switch back to SP_EL0
* while handling the exception. We only need SP_EL2 for the assembly
* exception entry and exit code that stores all register state
* (including the old SP_EL0, before we switch to the real exception
* stack). Rather than having yet another stack to push/pop those
* register values on so that we can later sort them into the
* exception_state structure, it's much easier to just make SP_EL2 point
* directly to exception_state and just use it as a normal base register
* rather than a real stack. This function sets that up.
*/
ENTRY(exception_set_state_ptr)
msr SPSel, #1
mov sp, x0
msr SPSel, #0
ret
ENDPROC(exception_set_state_ptr)
96 changes: 88 additions & 8 deletions payloads/libpayload/arch/arm64/gdb.c
View file
Expand Up @@ -18,40 +18,120 @@

struct gdb_regs
{
u64 x[32];
u64 x[31];
u64 sp; /* shares encoding 0b11111 with XZR in insns */
u64 pc; /* no longer encoded as a GPR in AArch64! */
u32 spsr;
struct fp_reg
{
u64 quad[2];
} __packed f[32];
u32 fpcr;
u64 low;
u64 high;
} __packed v[32];
u32 fpsr;
u32 spsr;
u32 fpcr;
} __packed;

/* Scratch value to write reentrant exception states to. We never read it. */
static struct exception_state sentinel_exception_state;

static int gdb_exception_hook(u32 type)
{
return -1;
if (!gdb_handle_reentrant_exception()) {
u8 signal;

if (type >= EXC_SYNC_SPX) {
printf("Impossible exception type: %d!\n", type);
return 0;
}

if (type == EXC_IRQ_SP0 || type == EXC_FIQ_SP0)
signal = GDB_SIGINT;
else switch (exception_state.ec) {
case ESR_EC_UNKNOWN:
signal = GDB_SIGILL;
break;
case ESR_EC_SVC_64: /* gdb_arch_enter() uses SVC */
case ESR_EC_SS_SAME: /* single-step causes this one */
case ESR_EC_BKPT_64: /* GDB itself likes to insert BRKs */
signal = GDB_SIGTRAP;
break;
default:
/* We mostly expect INSN_ABT, DATA_ABT and SERROR here,
but it makes for a good catchall signal anyway. */
signal = GDB_SIGSEGV;
/* GDB itself doesn't read out the ESR, so print it to
help people understand unexpected exceptions. But we
can't print anything if GDB is not connected yet. */
if (gdb_state.connected)
printf("Remote-GDB Exception %d, ESR: %#08x\n",
type, (uint32_t)exception_state.esr);
}

exception_set_state_ptr(&sentinel_exception_state);
gdb_command_loop(signal);
}

exception_set_state_ptr(&exception_state);

return 1;
}

void gdb_arch_init(void)
{
exception_install_hook(&gdb_exception_hook);
raw_write_oslar_el1(0); /* Disable OS lock (whatever that is) */
raw_write_mdcr_el2(MDCR_TDE); /* Route debug exceptions to EL2 */
raw_write_mdscr_el1(MDSCR_KDE); /* Enable debugging of current EL */
}

void gdb_arch_enter(void)
{
u64 *sp;

asm volatile ("mov %0, sp" : "=r"(sp) );

/* Avoid reentrant exceptions, just call the hook if in one already.
This is mostly important when gdb_enter() is called as result of an
exception (as part of the halt() at the end). */
if (sp >= exception_stack && sp <= exception_stack_end)
gdb_exception_hook(EXC_SYNC_SP0);
else /* BRK doesn't adjust ELR, so using SVC makes things easier. */
asm volatile ("svc #0");
}

int gdb_arch_set_single_step(int on)
{
/* GDB seems to only need this on x86, ARM works fine without it. */
return -1;
raw_write_mdscr_el1(MDSCR_KDE | (on ? MDSCR_SS : 0));
exception_state.pstate.ss = !!on;
return 0;
}

void gdb_arch_encode_regs(struct gdb_message *message)
{
gdb_message_encode_bytes(message, &exception_state.regs,
sizeof(exception_state.regs));
gdb_message_encode_bytes(message, &exception_state.sp,
sizeof(exception_state.sp));
gdb_message_encode_bytes(message, &exception_state.elr,
sizeof(exception_state.elr));
gdb_message_encode_bytes(message, &exception_state.spsr,
sizeof(exception_state.spsr));
gdb_message_encode_zero_bytes(message,
sizeof(struct gdb_regs) - offsetof(struct gdb_regs, v));
}

void gdb_arch_decode_regs(int offset, struct gdb_message *message)
{
gdb_message_decode_bytes(message, offset,
&exception_state.regs, sizeof(exception_state.regs));
offset += sizeof(exception_state.regs) * 2;
gdb_message_decode_bytes(message, offset,
&exception_state.sp, sizeof(exception_state.sp));
offset += sizeof(exception_state.sp) * 2;
gdb_message_decode_bytes(message, offset,
&exception_state.elr, sizeof(exception_state.elr));
offset += sizeof(exception_state.elr) * 2;
gdb_message_decode_bytes(message, offset,
&exception_state.spsr, sizeof(exception_state.spsr));
offset += sizeof(exception_state.spsr) * 2;
}
12 changes: 0 additions & 12 deletions payloads/libpayload/arch/arm64/head.S
View file
Expand Up @@ -38,18 +38,8 @@ ENTRY(_entry)
ldr x1, 1f
str x0, [x1]

/* Setup exception stack */
ldr x1, 3f
msr SPSel, #1
isb

mov sp, x1

/* Setup new stack */
ldr x1, 2f
msr SPSel, #0
isb

mov sp, x1

/* Let's rock. */
Expand All @@ -63,5 +53,3 @@ ENDPROC(_entry)
.quad cb_header_ptr
2:
.quad _stack
3:
.quad _exc_stack
33 changes: 0 additions & 33 deletions payloads/libpayload/arch/arm64/lib/Makefile.inc
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90 changes: 0 additions & 90 deletions payloads/libpayload/arch/arm64/lib/cache.c
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40 changes: 0 additions & 40 deletions payloads/libpayload/arch/arm64/lib/clock.c
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