diff --git a/Documentation/coding_style.md b/Documentation/coding_style.md
diff --git a/Documentation/code_of_conduct.md → Documentation/community/code_of_conduct.md b/Documentation/code_of_conduct.md → Documentation/community/code_of_conduct.md
diff --git a/Documentation/community/conferences.md b/Documentation/community/conferences.md
@@ -0,0 +1,19 @@
+# Conferences
+The coreboot community is present at a number of conferences over the year,
+usually at [FOSDEM](https://fosdem.org), [OSFC](https://osfc.io), and the
+[Chaos Communication Congress](https://events.ccc.de/congress/).
+
+The kind of presence differs, but there's usually a booth or other kind of
+gathering where everybody is welcome to say hello and to learn more about
+coreboot.
+
+Depending on the nature of the conference, coreboot developers might bring
+their development kit with them and conduct development sessions.
+
+## Upcoming events
+
+TODO: add them
+
+## Talks
+
+TODO: link to recorded talks
diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md
@@ -0,0 +1,18 @@
+# Our forums
+
+The coreboot community has various venues to help each other and discuss the
+direction of our project.
+
+## Mailing list
+
+The first address for coreboot related discussion is our mailing list.
+You can subscribe on its
+[information page](https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org/) and
+read its
+[archives](https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/).
+
+## IRC
+
+We also have a
+[real time chat](https://webchat.freenode.net?channels=%23coreboot)
+on the Freenode IRC network's #coreboot channel.
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -9,7 +9,10 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Rookie Guide](lessons/index.md)
-* [Code of Conduct](code_of_conduct.md)
+* [Coding Style](coding_style.md)
+* [Code of Conduct](community/code_of_conduct.md)
+* [Community forums](community/forums.md)
+* [coreboot at conferences](community/conferences.md)
 * [Timestamps](timestamp.md)
 * [Intel IFD Binary Extraction](Binary_Extraction.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)

diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md
@@ -0,0 +1,8 @@
+# Qemu RISC-V emulator
+
+## Building coreboot and running it in Qemu
+
+- Configure coreboot and run `make` as usual
+- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
+  convert coreboot to an ELF that Qemu can load
+- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -19,6 +19,7 @@ This section contains documentation about coreboot on specific mainboards.
 The boards in this section are not real mainboards, but emulators.
 
 - [Spike RISC-V emulator](emulation/spike-riscv.md)
+- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
 
 ## Intel
 
@@ -48,12 +49,15 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Lenovo
 
+- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
 - [T4xx common](lenovo/t4xx_series.md)
+- [X2xx common](lenovo/x2xx_series.md)
 
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)
 - [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md)
+- [x1](lenovo/x1.md)
 
 ### Ivy Bridge series
 

diff --git a/Documentation/mainboard/lenovo/t4xx_series.md b/Documentation/mainboard/lenovo/t4xx_series.md
@@ -3,6 +3,8 @@
 A skilled engineer takes around 40 minutes to disassemble, flash and reassemble
 the whole device.
 
+Read their [Hardware Maintenance Manual](thinkpad_hmm.md) for detailed steps.
+
 ## Steps to access the flash IC
 
 * Unplug the main battery

diff --git a/Documentation/mainboard/lenovo/thinkpad_hmm.md b/Documentation/mainboard/lenovo/thinkpad_hmm.md
@@ -0,0 +1,6 @@
+# Obtain Hardware Maintenance Manual of ThinkPads
+
+You are suggested obtain the "Hardware Maintenance Manual" for your corresponding
+model as a guidance. Some can be found from [Hardware Specifications of ThinkWiki].
+
+[Hardware Specifications of ThinkWiki]: https://www.thinkwiki.org/wiki/Hardware_Specifications
diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md
@@ -0,0 +1,24 @@
+# Lenovo X1
+
+## Flashing instructions
+
+![x1_flash_ic](x1_flash_ic.jpg)
+
+You have to remove the keyboard in order to access the flash IC (the chip
+inside the red circle on the picture above), as it is under the wider
+cable (already detached from MB in the picture) connecting the keyboard
+to the mainboard.
+
+The flash IC can be a SOIC-8 one or a WSON-8 one, and may be covered with
+a piece of insulation tape.
+
+For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and
+
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+
+Steps to access the flash IC are described here [X2xx series].
+
+[X2xx series]: x2xx_series.md
+[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md
diff --git a/Documentation/mainboard/lenovo/x1_flash_ic.jpg b/Documentation/mainboard/lenovo/x1_flash_ic.jpg
diff --git a/Documentation/mainboard/lenovo/x2xx_series.md b/Documentation/mainboard/lenovo/x2xx_series.md
@@ -0,0 +1,12 @@
+# Lenovo x2xx series disassembly instructions
+
+Removing the keyboard and palmrest would allow you to access the flash chip.
+
+Read their [Hardware Maintenance Manual](thinkpad_hmm.md) for detailed steps.
+
+## Steps to access the flash IC
+
+* Unplug the main battery
+* Remove the keyboard
+* Remove the palmrest
+
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -9,6 +9,7 @@ Release notes for previous releases
 * [4.6 - April 2017](coreboot-4.6-relnotes.md)
 * [4.7 - January 2018](coreboot-4.7-relnotes.md)
 * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.9 - December 2018](coreboot-4.9-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -20,4 +21,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.9 - November 2018](coreboot-4.9-relnotes.md)
+* [4.10 - April 2019](coreboot-4.10-relnotes.md)
diff --git a/Makefile b/Makefile
@@ -44,17 +44,20 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
 
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
+KCONFIG_AUTOADS := $(obj)/cb-config.ads
 KCONFIG_AUTOHEADER := $(obj)/config.h
 KCONFIG_AUTOCONFIG := $(obj)/auto.conf
 KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
 KCONFIG_SPLITCONFIG := $(obj)/config
 KCONFIG_TRISTATE := $(obj)/tristate.conf
 KCONFIG_NEGATIVES := 1
 KCONFIG_STRICT := 1
+KCONFIG_PACKAGE := CB.Config
 
 COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
 COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
 COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
+COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
 
 # directory containing the toplevel Makefile.inc
 TOPLEVEL := .
@@ -179,6 +182,12 @@ real-all: real-target
 $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf
 	+$(MAKE) oldconfig
 
+$(KCONFIG_AUTOCONFIG): $(KCONFIG_AUTOHEADER)
+	true
+
+$(KCONFIG_AUTOADS): $(KCONFIG_AUTOCONFIG) $(objutil)/kconfig/toada
+	$(objutil)/kconfig/toada CB.Config <$< >$@
+
 # Add a new class of source/object files to the build system
 add-class= \
 	$(eval $(1)-srcs:=) \

diff --git a/Makefile.inc b/Makefile.inc
@@ -198,6 +198,11 @@ forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/
 ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
 forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
 endif
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y)
+ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y)
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
+endif
+endif
 endif
 UPDATED_SUBMODULES:=1
 COREBOOT_EXPORTS += UPDATED_SUBMODULES
@@ -378,6 +383,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include
 VBOOT_SOURCE ?= 3rdparty/vboot
 CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
+CPPFLAGS_common += -include $(src)/include/rules.h
 CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
 CPPFLAGS_common += -I3rdparty
 CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\"
@@ -1054,7 +1060,7 @@ ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
 	$(FIT_OPTIONS)
 endif
 
-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y)
+ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y)
 	@printf "    UPDATE-FIT\n"
 	$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
 	$(FIT_OPTIONS)

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.1"
+CONFIG_LOCALVERSION="v4.9.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU1=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.1"
+CONFIG_LOCALVERSION="v4.9.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.1"
+CONFIG_LOCALVERSION="v4.9.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.1"
+CONFIG_LOCALVERSION="v4.9.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.1"
+CONFIG_LOCALVERSION="v4.9.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y

diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig
@@ -219,7 +219,7 @@ endif #LINUXBOOT_UROOT
 
 endif #LINUXBOOT_BUILD_INITRAMFS
 
-choice LINUXBOOT_INITRAMFS_COMPRESSION
+choice
 	prompt "Initramfs compression format"
 	default LINUXBOOT_INITRAMFS_COMPRESSION_XZ
 

diff --git a/src/Kconfig b/src/Kconfig
@@ -782,6 +782,18 @@ config DEBUG_ACPI
 
 	  If unsure, say N.
 
+config DEBUG_CONSOLE_INIT
+	bool "Debug console initialisation code"
+	default n
+	help
+	  With this option printk()'s are attempted before console hardware
+	  initialisation has been completed. Your mileage may vary.
+
+	  Typically you will need to modify source in console_hw_init() such
+	  that a working console appears before the one you want to debug.
+
+	  If unsure, say N.
+
 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
 # printk(BIOS_DEBUG, ...) calls.
 config REALMODE_DEBUG
@@ -949,16 +961,6 @@ config DEBUG_SPI_FLASH
 	help
 	  This option enables additional SPI flash related debug messages.
 
-config DEBUG_USBDEBUG
-	bool "Output verbose USB 2.0 EHCI debug dongle messages"
-	default n
-	depends on USBDEBUG
-	help
-	  This option enables additional USB 2.0 debug dongle related messages.
-
-	  Select this to debug the connection of usbdebug dongle. Note that
-	  you need some other working console to receive the messages.
-
 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
 # Only visible with the right southbridge and loglevel.
 config DEBUG_INTEL_ME
@@ -1089,36 +1091,6 @@ config MAX_REBOOT_CNT
 	  with the normal image enabled before assuming the normal image is defective
 	  and switching to the fallback image.
 
-config CREATE_BOARD_CHECKLIST
-	bool
-	default n
-	help
-	  When selected, creates a webpage showing the implementation status for
-	  the board.  Routines highlighted in green are complete, yellow are
-	  optional and red are required and must be implemented.  A table is
-	  produced for each stage of the boot process except the bootblock.  The
-	  red items may be used as an implementation checklist for the board.
-
-config MAKE_CHECKLIST_PUBLIC
-	bool
-	default n
-	help
-	  When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
-	  is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
-	  directory.
-
-config CHECKLIST_DATA_FILE_LOCATION
-	string
-	help
-	  Location of the <stage>_complete.dat and <stage>_optional.dat files
-	  that are consumed during checklist processing.  <stage>_complete.dat
-	  contains the symbols that are expected to be in the resulting image.
-	  <stage>_optional.dat is a subset of <stage>_complete.dat and contains
-	  a list of weak symbols which the resulting image may consume.  Other
-	  symbols contained only in <stage>_complete.dat will be flagged as
-	  required and not implemented if a weak implementation is found in the
-	  resulting image.
-
 config UNCOMPRESSED_RAMSTAGE
 	bool
 

diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
@@ -19,6 +19,7 @@
 #include <arch/transition.h>
 #include <arm_tf.h>
 #include <assert.h>
+#include <bootmem.h>
 #include <cbfs.h>
 #include <program_loading.h>
 

diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
@@ -19,7 +19,6 @@
 #include <arch/transition.h>
 #include <arm_tf.h>
 #include <program_loading.h>
-#include <rules.h>
 #include <string.h>
 
 static void run_payload(struct prog *prog)

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
@@ -11,10 +11,49 @@ config RISCV_ABI
 config RISCV_CODEMODEL
 	string
 
-config ARCH_BOOTBLOCK_RISCV
+config ARCH_RISCV_M_DISABLED
+	bool
+
+config ARCH_RISCV_M
+	# Whether a SOC implements M mode.
+	# M mode is the most privileged mode, it is
+	# the equivalent in some ways of x86 SMM mode
+	# save that in M mode it is impossible to turn
+	# on paging.
+	# While the spec requires it, there is at least
+	# one implementation that will not have it due
+	# to security concerns.
+	bool
+	default n if ARCH_RISCV_M_DISABLED
+	default y
+
+config ARCH_RISCV_S
+	# S (supervisor) mode is for kernels. It is optional.
+	bool
+	default n
+
+config ARCH_RISCV_U
+	# U (user) mode is for programs.
+	bool
+	default n
+
+config ARCH_RISCV_RV64
 	bool
 	default n
 	select ARCH_RISCV
+
+config ARCH_RISCV_RV32
+	bool
+	default n
+	select ARCH_RISCV
+
+config ARCH_RISCV_PMP
+	bool
+	default n
+
+config ARCH_BOOTBLOCK_RISCV
+	bool
+	default n
 	select C_ENVIRONMENT_BOOTBLOCK
 
 config ARCH_VERSTAGE_RISCV

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
@@ -26,10 +26,21 @@ check-ramstage-overlap-regions += stack
 endif
 
 riscv_flags = -I$(src)/arch/riscv/
+
+ifeq ($(CONFIG_ARCH_RISCV_RV64),y)
+_rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64
+else
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
+_rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32
+else
+$(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32")
+endif
+endif
+
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
 else
-riscv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64
+riscv_flags += $(_rv_flags)
 endif
 
 riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
@@ -56,7 +67,7 @@ bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += smp.c
 bootblock-y += misc.c
-bootblock-y += pmp.c
+bootblock-$(ARCH_RISCV_PMP) += pmp.c
 bootblock-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
@@ -85,7 +96,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
 romstage-y += boot.c
 romstage-y += stages.c
 romstage-y += misc.c
-romstage-y += pmp.c
+romstage-$(ARCH_RISCV_PMP) += pmp.c
 romstage-y += smp.c
 romstage-y += \
 	$(top)/src/lib/memchr.c \
@@ -126,8 +137,8 @@ ramstage-y += misc.c
 ramstage-y += smp.c
 ramstage-y += boot.c
 ramstage-y += tables.c
-ramstage-y += payload.S
-ramstage-y += pmp.c
+ramstage-y += payload.c
+ramstage-$(ARCH_RISCV_PMP) += pmp.c
 ramstage-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \

diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
@@ -17,37 +17,39 @@
 #include <vm.h>
 #include <arch/boot.h>
 #include <arch/encoding.h>
-#include <rules.h>
 #include <console/console.h>
 #include <arch/smp/smp.h>
+#include <mcall.h>
 
 /*
  * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM.
  * Presumably this FDT is also in ROM.
  *
  * This pointer is only used in ramstage!
  */
-const void *rom_fdt;
 
 static void do_arch_prog_run(struct prog *prog)
 {
-	void (*doit)(void *) = prog_entry(prog);
-	void riscvpayload(const void *fdt, void *payload);
+	void (*doit)(int hart_id, void *fdt);
+	int hart_id;
+	void *fdt = prog_entry_arg(prog);
+
+	/*
+	 * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS
+	 * instead.
+	 */
+	if (fdt == NULL)
+		fdt = HLS()->fdt;
 
 	if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
-		/*
-		 * FIXME: This is wrong and will crash. Linux can't (in early
-		 * boot) access memory that's before its own loading address.
-		 * We need to copy the FDT to a place where Linux can access it.
-		 */
-		const void *fdt = rom_fdt;
-
-		printk(BIOS_SPEW, "FDT is at %p\n", fdt);
-		printk(BIOS_SPEW, "OK, let's go\n");
-		riscvpayload(fdt, doit);
+		run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S);
+		return;
 	}
 
-	doit(prog_entry_arg(prog));
+	doit = prog_entry(prog);
+	hart_id = HLS()->hart_id;
+
+	doit(hart_id, fdt);
 }
 
 void arch_prog_run(struct prog *prog)

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
@@ -50,6 +50,7 @@ _start:
 
 	# initialize hart-local storage
 	csrr a0, mhartid
+	csrrw a1, mscratch, zero
 	call hls_init
 
 	li   a0, CONFIG_RISCV_WORKING_HARTID

diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h
@@ -16,6 +16,12 @@
 #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H
 #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H
 
-extern const void *rom_fdt;
+#include <program_loading.h>
+
+#define RISCV_PAYLOAD_MODE_U 0
+#define RISCV_PAYLOAD_MODE_S 1
+#define RISCV_PAYLOAD_MODE_M 3
+
+void run_payload(struct prog *prog, void *fdt, int payload_mode);
 
 #endif
diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h
@@ -18,6 +18,7 @@
 
 #include <main_decl.h>
 
-void stage_entry(void) __attribute__((section(".text.stage_entry")));
+void stage_entry(int hart_id, void *fdt)
+	__attribute__((section(".text.stage_entry")));
 
 #endif
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
@@ -52,9 +52,14 @@ typedef struct {
 	int ipi_pending;
 	uint64_t *timecmp;
 	uint64_t *time;
+	void *fdt;
 	struct blocker entry;
 } hls_t;
 
+_Static_assert(
+	sizeof(hls_t) == HLS_SIZE,
+	"HLS_SIZE must equal to sizeof(hls_t)");
+
 #define MACHINE_STACK_TOP() ({ \
 	/* coverity[uninit_use] : FALSE */ \
 	register uintptr_t sp asm ("sp"); \
@@ -66,7 +71,8 @@ typedef struct {
 
 #define MACHINE_STACK_SIZE RISCV_PGSIZE
 
-void hls_init(uint32_t hart_id); // need to call this before launching linux
+// need to call this before launching linux
+void hls_init(uint32_t hart_id, void *fdt);
 
 /* This function is used to initialize HLS()->time/HLS()->timecmp  */
 void mtime_init(void);

diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c
@@ -34,10 +34,11 @@
 
 int mcalldebug; // set this interactively for copious debug.
 
-void hls_init(uint32_t hart_id)
+void hls_init(uint32_t hart_id, void *fdt)
 {
 	printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS());
 	memset(HLS(), 0, sizeof(*HLS()));
+	HLS()->fdt = fdt;
 	HLS()->hart_id = hart_id;
 
 	mtime_init();

diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc
+ * Copyright (C) 2018 HardenedLinux
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/boot.h>
+#include <arch/encoding.h>
+#include <console/console.h>
+
+void run_payload(struct prog *prog, void *fdt, int payload_mode)
+{
+	void (*doit)(int hart_id, void *fdt) = prog_entry(prog);
+	int hart_id = read_csr(mhartid);
+	uintptr_t status = read_csr(mstatus);
+	status &= ~MSTATUS_MPIE;
+	status &= ~MSTATUS_MPP;
+	switch (payload_mode) {
+	case RISCV_PAYLOAD_MODE_U:
+		break;
+	case RISCV_PAYLOAD_MODE_S:
+		status |= MSTATUS_SPP;
+		break;
+	case RISCV_PAYLOAD_MODE_M:
+		doit(hart_id, fdt);
+		return;
+	default:
+		die("wrong privilege level for payload");
+		break;
+	}
+	write_csr(mstatus, status);
+	write_csr(mepc, doit);
+	asm volatile(
+		"mv a0, %0\n\t"
+		"mv a1, %0\n\t"
+		"mret" ::"r"(hart_id),
+		"r"(fdt)
+		: "a0", "a1");
+}
diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c
@@ -29,18 +29,18 @@
 #include <arch/stages.h>
 #include <arch/smp/smp.h>
 #include <rules.h>
+#include <mcall.h>
 
-void stage_entry(void)
+void stage_entry(int hart_id, void *fdt)
 {
-	smp_pause(CONFIG_RISCV_WORKING_HARTID);
-
 	/*
 	 * Save the FDT pointer before entering ramstage, because mscratch
 	 * might be overwritten in the trap handler, and there is code in
 	 * ramstage that generates misaligned access faults.
 	 */
-	if (ENV_RAMSTAGE)
-		rom_fdt = (const void *)read_csr(mscratch);
+	HLS()->hart_id = hart_id;
+	HLS()->fdt = fdt;
+	smp_pause(CONFIG_RISCV_WORKING_HARTID);
 
 	main();
 }
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
@@ -57,6 +57,7 @@ static void print_trap_information(const trapframe *tf)
 {
 	const char *previous_mode;
 	bool mprv = !!(tf->status & MSTATUS_MPRV);
+	int hart_id = read_csr(mhartid);
 
 	/* Leave some space around the trap message */
 	printk(BIOS_DEBUG, "\n");
@@ -69,6 +70,7 @@ static void print_trap_information(const trapframe *tf)
 				(void *)tf->cause);
 
 	previous_mode = mstatus_to_previous_mode(read_csr(mstatus));
+	printk(BIOS_DEBUG, "Hart ID:            %d\n", hart_id);
 	printk(BIOS_DEBUG, "Previous mode:      %s%s\n",
 			previous_mode, mprv? " (MPRV)":"");
 	printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc);

diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
@@ -22,7 +22,6 @@
 #include <timestamp.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
-#include <rules.h>
 #include <symbols.h>
 
 #if ENV_RAMSTAGE || ENV_POSTCAR

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
@@ -19,9 +19,11 @@
 .global _stack
 .global _estack
 
+/* Stack alignment is not enforced with rmodule loader, reserve one
+ * extra CPU such that alignment can be enforced on entry. */
 .align CONFIG_STACK_SIZE
 _stack:
-.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE
+.space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE
 _estack:
 #if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 .global thread_stacks
@@ -70,8 +72,9 @@ _start:
 	rep
 	stosl
 
-	/* set new stack */
+	/* Set new stack with enforced alignment. */
 	movl	$_estack, %esp
+	andl	$(~(CONFIG_STACK_SIZE-1)), %esp
 
 #if IS_ENABLED(CONFIG_COOP_MULTITASKING)
 	/* Push the thread pointer. */

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -67,7 +67,8 @@
 	_car_drivers_storage_end = .;
 #endif
 	_car_ehci_dbg_info_start = .;
-        . += 64;
+	/* Reserve sizeof(struct ehci_dbg_info). */
+        . += 80;
         _car_ehci_dbg_info_end = .;
 	/* _car_global_start and _car_global_end provide symbols to per-stage
 	 * variables that are not shared like the timestamp and the pre-ram

diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <arch/acpi.h>
 #include <arch/ebda.h>
 #include <commonlib/endian.h>
 #include <console/console.h>
@@ -104,6 +105,9 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
 
 void setup_default_ebda(void)
 {
+	if (acpi_is_wakeup_s3())
+		return;
+
 	setup_ebda(DEFAULT_EBDA_LOWMEM,
 		   DEFAULT_EBDA_SEGMENT,
 		   DEFAULT_EBDA_SIZE);

diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
@@ -19,7 +19,6 @@
 #include <console/streams.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/lapic.h>
-#include <rules.h>
 #include <stdint.h>
 #include <string.h>
 

diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
@@ -35,7 +35,6 @@ SECTIONS
 	/* This section might be better named .setup */
 	.rom ROMLOC : {
 		_rom = .;
-		ap_sipi_vector = .;
 		*(.rom.text);
 		*(.rom.data);
 		*(.rom.data.*);
@@ -54,9 +53,7 @@ SECTIONS
 		(CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
 
 	/* Post-check proper SIPI vector. */
-	_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0),
-		"Bad SIPI vector alignment");
-	_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR),
+	_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff),
 		"Address mismatch on AP_SIPI_VECTOR");
 
 	/DISCARD/ : {

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
@@ -57,7 +57,6 @@
 
 #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
 #include <stdint.h>
-#include <rules.h>
 #include <commonlib/helpers.h>
 #include <device/device.h>
 #include <uuid.h>

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
@@ -16,7 +16,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
 
 /*
  * EFLAGS bits

diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
@@ -18,7 +18,6 @@
 
 #include <arch/symbols.h>
 #include <stdlib.h>
-#include <rules.h>
 
 #if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
 asm(".section .car.global_data,\"w\",@nobits");

diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h
@@ -31,7 +31,6 @@
 #define _ARCH_EXCEPTION_H
 
 #include <arch/cpu.h>
-#include <rules.h>
 
 #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
 asmlinkage void exception_init(void);

diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
@@ -16,7 +16,6 @@
 
 #include <endian.h>
 #include <stdint.h>
-#include <rules.h>
 #include <device/pci_type.h>
 
 /*
@@ -235,12 +234,6 @@ static inline int __ffs(u32 value)
 
 #ifdef __SIMPLE_DEVICE__
 
-#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
-	(((SEGBUS) & 0xFFF) << 20) | \
-	(((DEV) & 0x1F) << 15) | \
-	(((FN) & 0x07) << 12) | \
-	((WHERE) & 0xFFF))
-
 #define PCI_DEV(SEGBUS, DEV, FN) ( \
 	(((SEGBUS) & 0xFFF) << 20) | \
 	(((DEV) & 0x1F) << 15) | \

diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
@@ -16,15 +16,14 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-#include <rules.h>
 
 #if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
 /* No .data or .bss sections. Cache as RAM is handled separately. */
 #define ARCH_STAGE_HAS_DATA_SECTION 0
 #define ARCH_STAGE_HAS_BSS_SECTION 0
 #endif
 
-#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
+#if (CONFIG_RAMTOP == 0)
 # error "CONFIG_RAMTOP not configured"
 #endif
 

diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h
@@ -35,6 +35,9 @@ extern char _car_stack_end[];
 #define _car_stack_size (_car_stack_end - _car_stack_start)
 
 extern char _car_ehci_dbg_info_start[];
+extern char _car_ehci_dbg_info_end[];
+#define _car_ehci_dbg_info_size \
+	(_car_ehci_dbg_info_end - _car_ehci_dbg_info_start)
 
 /*
  * The _car_relocatable_data_[start|end] symbols cover CAR data which is

diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c
@@ -19,57 +19,57 @@
  */
 
 #if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
-#define CONFIG_CMD(bus, devfn, where)	(0x80000000 | (bus << 16) | \
+#define CONF_CMD(bus, devfn, where)	(0x80000000 | (bus << 16) | \
 					(devfn << 8) | (where & ~3))
 #else
-#define CONFIG_CMD(bus, devfn, where)	(0x80000000 | (bus << 16) | \
+#define CONF_CMD(bus, devfn, where)	(0x80000000 | (bus << 16) | \
 					(devfn << 8) | ((where & 0xff) & ~3) |\
 					((where & 0xf00)<<16))
 #endif
 
 static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn,
 				      int where)
 {
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(CONF_CMD(bus, devfn, where), 0xCF8);
 	return inb(0xCFC + (where & 3));
 }
 
 static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn,
 					int where)
 {
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(CONF_CMD(bus, devfn, where), 0xCF8);
 	return inw(0xCFC + (where & 2));
 }
 
 static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn,
 					int where)
 {
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(CONF_CMD(bus, devfn, where), 0xCF8);
 	return inl(0xCFC);
 }
 
 static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn,
 				    int where, uint8_t value)
 {
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(CONF_CMD(bus, devfn, where), 0xCF8);
 	outb(value, 0xCFC + (where & 3));
 }
 
 static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn,
 				     int where, uint16_t value)
 {
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(CONF_CMD(bus, devfn, where), 0xCF8);
 	outw(value, 0xCFC + (where & 2));
 }
 
 static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn,
 				     int where, uint32_t value)
 {
-	outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
+	outl(CONF_CMD(bus, devfn, where), 0xCF8);
 	outl(value, 0xCFC);
 }
 
-#undef CONFIG_CMD
+#undef CONF_CMD
 
 const struct pci_bus_operations pci_cf8_conf1 = {
 	.read8 = pci_conf1_read_config8,

diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
@@ -14,7 +14,6 @@
  */
 
 #include <random.h>
-#include <rules.h>
 
 /*
  * Intel recommends that applications attempt 10 retries in a tight loop

diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c
@@ -21,15 +21,14 @@ uint64_t timestamp_get(void)
 	return rdtscll();
 }
 
-unsigned long __weak tsc_freq_mhz(void)
-{
-	/* Default to not knowing TSC frequency. cbmem will have to fallback
-	 * on trying to determine it in userspace. */
-	return 0;
-}
-
 int timestamp_tick_freq_mhz(void)
 {
 	/* Chipsets that have a constant TSC provide this value correctly. */
-	return tsc_freq_mhz();
+	if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+		return tsc_freq_mhz();
+
+	/* Filling tick_freq_mhz = 0 in timestamps-table will trigger
+	 * userspace utility to try deduce it from the running system.
+	 */
+	return 0;
 }
diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #if ENV_RAMSTAGE
 #define __SIMPLE_DEVICE__		1
 #endif

diff --git a/src/console/Kconfig b/src/console/Kconfig
@@ -1,9 +1,12 @@
 menu "Console"
 
+config NO_BOOTBLOCK_CONSOLE
+	bool
+
 config BOOTBLOCK_CONSOLE
 	bool "Enable early (bootblock) console output."
-	depends on C_ENVIRONMENT_BOOTBLOCK
-	default n
+	depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE
+	default y
 	help
 	  Use console during the bootblock if supported
 
@@ -37,6 +40,13 @@ config CONSOLE_SERIAL
 	  shown on the following menu line. Supporting multiple different types
 	  of UARTs in one build is not supported.
 
+config FIXED_UART_FOR_CONSOLE
+	bool
+	help
+	  Select to remove the prompt from UART_FOR_CONSOLE in case a
+	  specific UART has to be used (e.g. when the platform code
+	  performs dangerous configurations).
+
 if CONSOLE_SERIAL
 
 	comment "I/O mapped, 8250-compatible"
@@ -49,7 +59,8 @@ if CONSOLE_SERIAL
 	depends on HAVE_UART_SPECIAL
 
 config UART_FOR_CONSOLE
-	int "Index for UART port to use for console"
+	int
+	prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE
 	default 0
 	help
 	  Select an I/O port to use for serial console:

diff --git a/src/console/console.c b/src/console/console.c
@@ -22,7 +22,6 @@
 #include <console/usb.h>
 #include <console/spi.h>
 #include <console/flash.h>
-#include <rules.h>
 
 void console_hw_init(void)
 {

diff --git a/src/console/init.c b/src/console/init.c
@@ -20,7 +20,6 @@
 #include <console/streams.h>
 #include <device/pci.h>
 #include <option.h>
-#include <rules.h>
 #include <version.h>
 
 /* Mutable console log level only allowed when RAM comes online. */
@@ -72,6 +71,9 @@ asmlinkage void console_init(void)
 {
 	init_log_level();
 
+	if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT))
+		car_set_var(console_inited, 1);
+
 #if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE)
 	if (!ENV_SMM && !ENV_RAMSTAGE)
 		pci_early_bridge_init();
@@ -81,6 +83,7 @@ asmlinkage void console_init(void)
 
 	car_set_var(console_inited, 1);
 
-	printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n",
-	       coreboot_version, coreboot_extra_version, coreboot_build);
+	printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n",
+	       coreboot_version, coreboot_extra_version, coreboot_build,
+	       get_log_level());
 }
diff --git a/src/console/post.c b/src/console/post.c
@@ -20,7 +20,6 @@
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
 #include <smp/spinlock.h>
-#include <rules.h>
 
 /* Write POST information */
 

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
@@ -42,12 +42,6 @@ config SMP
 	  This option is used to enable certain functions to make coreboot
 	  work correctly on symmetric multi processor (SMP) systems.
 
-config AP_SIPI_VECTOR
-	hex
-	default 0xfffff000
-	help
-	  This must equal address of ap_sipi_vector from bootblock build.
-
 config	MMX
 	bool
 	help
@@ -84,14 +78,43 @@ config USES_MICROCODE_HEADER_FILES
 	  This is selected by a board or chipset to set the default for the
 	  microcode source choice to a list of external microcode headers
 
+config MICROCODE_BLOB_NOT_IN_BLOB_REPO
+	bool
+	help
+	  Selected by platforms that don't maintain microcode updates in the
+	  blobs repo yet.
+
+config MICROCODE_BLOB_NOT_HOOKED_UP
+	bool
+	help
+	  Selected by platforms that haven't hooked microcode updates up yet.
+
+config MICROCODE_BLOB_UNDISCLOSED
+	bool
+	help
+	  Selected by work-in-progress platforms that don't have microcode
+	  updates available yet.
+
+config USE_CPU_MICROCODE_CBFS_BINS
+	bool
+	help
+	  Automatically selected below to add binary microcode files
+	  (`cpu_microcode_bins` in the makefiles) to CBFS.
+
 choice
 	prompt "Include CPU microcode in CBFS" if ARCH_X86
 	default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
-	default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS
-	default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
+	default CPU_MICROCODE_CBFS_NONE if MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
+					   MICROCODE_BLOB_NOT_HOOKED_UP || \
+					   MICROCODE_BLOB_UNDISCLOSED
+	depends on SUPPORT_CPU_UCODE_IN_CBFS
 
-config CPU_MICROCODE_CBFS_GENERATE
+config CPU_MICROCODE_CBFS_DEFAULT_BINS
 	bool "Generate from tree"
+	select USE_CPU_MICROCODE_CBFS_BINS
+	depends on !(MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
+		     MICROCODE_BLOB_NOT_HOOKED_UP || \
+		     MICROCODE_BLOB_UNDISCLOSED)
 	help
 	  Select this option if you want microcode updates to be assembled when
 	  building coreboot and included in the final image as a separate CBFS
@@ -102,8 +125,27 @@ config CPU_MICROCODE_CBFS_GENERATE
 
 	  If unsure, select this option.
 
+config CPU_MICROCODE_CBFS_EXTERNAL_BINS
+	bool "Include external microcode binary"
+	select USE_CPU_MICROCODE_CBFS_BINS
+	depends on !CPU_MICROCODE_MULTIPLE_FILES
+	help
+	  Select this option if you want to include external binary files
+	  in the CPUs native format. They will be included as a separate
+	  file in CBFS.
+
+	  A word of caution: only select this option if you are sure the
+	  microcode that you have is newer than the microcode shipping with
+	  coreboot.
+
+	  The microcode file may be removed from the ROM image at a later
+	  time with cbfstool, if desired.
+
+	  If unsure, and applicable, select "Generate from tree"
+
 config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
 	bool "Include external microcode header files"
+	depends on !CPU_MICROCODE_MULTIPLE_FILES
 	help
 	  Select this option if you want to include external c header files
 	  containing the CPU microcode. This will be included as a separate
@@ -116,25 +158,17 @@ config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
 	  The microcode file may be removed from the ROM image at a later
 	  time with cbfstool, if desired.
 
-	  If unsure, select "Generate from tree"
+	  If unsure, and applicable, select "Generate from tree"
 
 config CPU_MICROCODE_CBFS_NONE
 	bool "Do not include microcode updates"
 	help
 	  Select this option if you do not want CPU microcode included in CBFS.
-	  Note that for some CPUs, the microcode is hard-coded into the source
-	  tree and is not loaded from CBFS. In this case, microcode will still
-	  be updated. There is a push to move all microcode to CBFS, but this
-	  change is not implemented for all CPUs.
-
-	  This option currently applies to:
-	    - Intel SandyBridge/IvyBridge
-	    - VIA Nano
 
 	  Microcode may be added to the ROM image at a later time with cbfstool,
 	  if desired.
 
-	  If unsure, select "Generate from tree"
+	  If unsure, and applicable, select "Generate from tree"
 
 	  The GOOD:
 	  Microcode updates intend to solve issues that have been discovered
@@ -168,8 +202,6 @@ endchoice
 
 config CPU_MICROCODE_MULTIPLE_FILES
 	bool
-	default n
-	depends on CPU_MICROCODE_CBFS_GENERATE
 	help
 	  Select this option to install separate microcode container files into
 	  CBFS instead of using the traditional monolithic microcode file format.
@@ -183,7 +215,7 @@ config CPU_MICROCODE_HEADER_FILES
 
 config CPU_UCODE_BINARIES
 	string "Microcode binary path and filename"
-	depends on CPU_MICROCODE_CBFS_GENERATE || AGESA_UCODE_EXPERIMENTAL
+	depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS || AGESA_UCODE_EXPERIMENTAL
 	default ""
 	help
 	  Some platforms have microcode in the blobs directory, and these can

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
@@ -17,7 +17,7 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
 ################################################################################
 
 ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
+cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
 endif
 
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
@@ -29,6 +29,11 @@ $(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER
 	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
 endif
 
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
+cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
+endif
+# otherwise `cpu_microcode_bins` should be filled by platform makefiles
+
 # We just mash all microcode binaries together into one binary to rule them all.
 # This approach assumes that the microcode binaries are properly padded, and
 # their headers specify the correct size. This works fairly well on isolatied
@@ -44,14 +49,15 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
 		fi; \
 	done; \
 	if [ -n "$$NO_MICROCODE_FILE" ]; then \
-		if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)" ]; then \
+		if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
 			echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
 		fi; \
 		false; \
 	fi
+	$(if $^,,false) # fail if no file is given at all
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	@echo $(cpu_microcode_bins)
-	cat /dev/null $+ > $@
+	cat $^ > $@
 
 cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
 cpu_microcode_blob.bin-type := microcode

diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig
@@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_RAMSTAGE_ARMV7
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_UART_SPECIAL
-	select BOOTBLOCK_CONSOLE
 	select UART_OVERRIDE_REFCLK
 	select BOOT_DEVICE_NOT_SPI_FLASH
 

diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000

diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 36
 
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000

diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x100000

diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 40
 
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x100000

diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
@@ -9,7 +9,7 @@ config CPU_AMD_MODEL_10XXX
 	select UDELAY_LAPIC
 	select HAVE_MONOTONIC_TIMER
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE
+	select CPU_MICROCODE_MULTIPLE_FILES
 	select ACPI_HUGE_LOWMEM_BACKUP
 
 if CPU_AMD_MODEL_10XXX

diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -15,11 +15,11 @@ ramstage-y += monotonic_timer.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
 
 # Microcode for Family 10h, 11h, 12h, and 14h
-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
+cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
 microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
 microcode_amd.bin-type := microcode
 
 # Microcode for Family 15h
-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
+cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
 microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
 microcode_amd_fam15h.bin-type := microcode
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -147,9 +147,6 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
 	// here assume the OS don't change our apicid
 	u32 ap_apicid;
 
-	u8 nvram;
-	bool multicore;
-
 	u32 nodes;
 	u32 disable_siblings;
 	u32 cores_found;
@@ -158,13 +155,12 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
 	/* get_nodes define in ht_wrapper.c */
 	nodes = get_nodes();
 
-	multicore = true;
-	if (get_option(&nvram, "multi_core") == CB_SUCCESS)
-		multicore = !!nvram;
-
-	disable_siblings = 0;
-	if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || !multicore)
+	if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||
+	    read_option(multi_core, 0) != 0) {	// 0 means multi core
 		disable_siblings = 1;
+	} else {
+		disable_siblings = 0;
+	}
 
 	for (i = 0; i < nodes; i++) {
 		if ((node >= 0) && (i != node))
@@ -639,17 +635,11 @@ static void setup_remote_node(u8 node)
 //it is running on core0 of node0
 void start_other_cores(uint32_t bsp_apicid)
 {
-	u8 nvram;
 	u32 nodes;
 	u32 nodeid;
-	bool multicore;
 
 	// disable multi_core
-	multicore = true;
-	if (get_option(&nvram, "multi_core") == CB_SUCCESS)
-		multicore = !!nvram;
-
-	if (!multicore)  {
+	if (read_option(multi_core, 0) != 0)  {
 		printk(BIOS_DEBUG, "Skip additional core init\n");
 		return;
 	}

diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
@@ -23,18 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x100000

diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
@@ -23,18 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 48
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x100000

diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
 	int
 	default 40
 
-config CBB
-	hex
-	default 0x0
-
-config CDB
-	hex
-	default 0x18
-
 config XIP_ROM_SIZE
 	hex
 	default 0x100000

diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
@@ -22,16 +22,14 @@ source src/cpu/intel/slot_1/Kconfig
 source src/cpu/intel/socket_BGA956/Kconfig
 source src/cpu/intel/socket_BGA1284/Kconfig
 source src/cpu/intel/socket_FCBGA559/Kconfig
-source src/cpu/intel/socket_FCBGA1023/Kconfig
 source src/cpu/intel/socket_mFCPGA478/Kconfig
 source src/cpu/intel/socket_mPGA478MN/Kconfig
 source src/cpu/intel/socket_mPGA604/Kconfig
 source src/cpu/intel/socket_441/Kconfig
-source src/cpu/intel/socket_LGA1155/Kconfig
 source src/cpu/intel/socket_LGA775/Kconfig
-source src/cpu/intel/socket_rPGA988B/Kconfig
-source src/cpu/intel/socket_rPGA989/Kconfig
 # Architecture specific features
 source src/cpu/intel/fit/Kconfig
 source src/cpu/intel/turbo/Kconfig
 source src/cpu/intel/common/Kconfig
+source src/cpu/intel/microcode/Kconfig
+source src/cpu/intel/car/non-evict/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
@@ -8,17 +8,13 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA1023) += socket_FCBGA1023
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -177,11 +177,11 @@ addrsize_set_high:
 
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
-	pushl	%eax 	/* BIST */
+	pushl	%eax	/* BIST */
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
-	pushl	%eax 	/* tsc[31:0] */
+	pushl	%eax	/* tsc[31:0] */
 
 before_c_entry:
 	post_code(0x29)

diff --git a/src/cpu/intel/car/non-evict/Kconfig b/src/cpu/intel/car/non-evict/Kconfig
@@ -0,0 +1,5 @@
+config CPU_HAS_L2_ENABLE_MSR
+	bool
+	help
+	  Select this in Kconfig of CPU sockets/SOC where the CPU
+	  has an MSR to enable the L2 CPU cache
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -24,6 +24,7 @@
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
 #define NoEvictMod_MSR 0x2e0
+#define BBL_CR_CTL3_MSR 0x11e
 
 .global bootblock_pre_c_entry
 
@@ -114,6 +115,17 @@ addrsize_set_high:
 	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
 
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRR_PHYS_BASE(1), %ecx
+	xorl	%edx, %edx
+	movl	$CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRR_PHYS_MASK(1), %ecx
+	rdmsr
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	wrmsr
+
 	post_code(0x25)
 
 	/* Enable MTRR. */
@@ -122,12 +134,48 @@ addrsize_set_high:
 	orl	$MTRR_DEF_TYPE_EN, %eax
 	wrmsr
 
+#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
+	/*
+	 * Enable the L2 cache. Currently this assumes that this
+	 * only affect socketed CPU's for which this is always valid,
+	 * hence the static preprocesser.
+	 */
+	movl	$BBL_CR_CTL3_MSR, %ecx
+	rdmsr
+	orl	$0x100, %eax
+	wrmsr
+#endif
+
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	invd
 	movl	%eax, %cr0
 
+#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+update_microcode:
+	/* put the return address in %esp */
+	movl	$end_microcode_update, %esp
+	jmp	update_bsp_microcode
+end_microcode_update:
+#endif
+	/* Disable caching to change MTRR's. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	/* Clear the mask valid to disable the MTRR */
+	movl	$MTRR_PHYS_MASK(1), %ecx
+	rdmsr
+	andl	$(~MTRR_PHYS_MASK_VALID), %eax
+	wrmsr
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	invd
+	movl	%eax, %cr0
+
 	/* enable the 'no eviction' mode */
 	movl	$NoEvictMod_MSR, %ecx
 	rdmsr
@@ -154,15 +202,9 @@ addrsize_set_high:
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-	/* Enable cache for our code in Flash because we do XIP here */
-	movl	$MTRR_PHYS_BASE(1), %ecx
-	xorl	%edx, %edx
-	movl	$CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
-	wrmsr
-
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	rdmsr
-	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
 	post_code(0x28)
@@ -181,11 +223,11 @@ addrsize_set_high:
 
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
-	pushl	%eax 	/* BIST */
+	pushl	%eax	/* BIST */
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
-	pushl	%eax 	/* tsc[31:0] */
+	pushl	%eax	/* tsc[31:0] */
 
 before_c_entry:
 	post_code(0x29)

diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -166,11 +166,11 @@ addrsize_set_high:
 
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
-	pushl	%eax 	/* BIST */
+	pushl	%eax	/* BIST */
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
-	pushl	%eax 	/* tsc[31:0] */
+	pushl	%eax	/* tsc[31:0] */
 
 before_c_entry:
 	post_code(0x29)

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,7 +23,10 @@
 
 /* Macro to access Local APIC registers at default base. */
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#define START_IPI_VECTOR	((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)
+#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+/* Fixed location, ASSERTED in failover.ld if it changes. */
+.set ap_sipi_vector_in_rom, 0xff
+#endif
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -180,7 +183,8 @@ hyper_threading_cpu:
 
 	/* Send Start IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
-	movl	$(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax
+	movl	$(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP), %eax
+	orl	$ap_sipi_vector_in_rom, %eax
 1:	movl	%eax, (%edi)
 	movl	$0x30, %ecx
 2:	pause
@@ -297,21 +301,32 @@ no_msr_11e:
 
 	post_code(0x2c)
 
+	/* Cache the whole rom to fetch microcode updates */
+	movl	$MTRR_PHYS_BASE(1), %ecx
+	xorl	%edx, %edx
+	movl	$CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRR_PHYS_MASK(1), %ecx
+	rdmsr
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	wrmsr
+
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	invd
 	movl	%eax, %cr0
 
-	/* Clear the cache memory region. This will also fill up the cache. */
-	cld
-	xorl	%eax, %eax
-	movl	$CACHE_AS_RAM_BASE, %edi
-	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
-	rep	stosl
-
+#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+	update_microcode:
+	/* put the return address in %esp */
+	movl	$end_microcode_update, %esp
+	jmp	update_bsp_microcode
+	end_microcode_update:
+#endif
 	post_code(0x2d)
-	/* Enable Cache-as-RAM mode by disabling cache. */
+	/* Disable caching to change MTRR's. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
@@ -326,8 +341,16 @@ no_msr_11e:
 	movl	$1, %eax
 	cpuid
 	cmp	$0xf, %ah
-	je	skip_cache_rom
+	jne	cache_rom
 
+disable_cache_rom:
+	movl	$MTRR_PHYS_MASK(1), %ecx
+	rdmsr
+	andl	$(~MTRR_PHYS_MASK_VALID), %eax
+	wrmsr
+	jmp	fill_cache
+
+cache_rom:
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
@@ -345,14 +368,21 @@ no_msr_11e:
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
 
-skip_cache_rom:
-
+fill_cache:
 	post_code(0x2e)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	invd
 	movl	%eax, %cr0
 
+	/* Clear the cache memory region. This will also fill up the cache. */
+	cld
+	xorl	%eax, %eax
+	movl	$CACHE_AS_RAM_BASE, %edi
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
+	rep	stosl
+
 	/* Setup the stack. */
 	mov	$_car_stack_end, %esp
 
@@ -363,11 +393,11 @@ skip_cache_rom:
 
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
-	pushl	%eax 	/* BIST */
+	pushl	%eax	/* BIST */
 	movd	%mm2, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
-	pushl	%eax 	/* tsc[31:0] */
+	pushl	%eax	/* tsc[31:0] */
 
 before_c_entry:
 	post_code(0x2f)

diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
@@ -1 +1,5 @@
 ramstage-y += common_init.c
+romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
+ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
+postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/fsb.h>
+#include <console/console.h>
+#include <commonlib/helpers.h>
+
+int get_ia32_fsb(void)
+{
+	struct cpuinfo_x86 c;
+	static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
+	static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
+	msr_t msr;
+	int ret = -2;
+
+	get_fms(&c, cpuid_eax(1));
+	switch (c.x86) {
+	case 0x6:
+		switch (c.x86_model) {
+		case 0xe:  /* Core Solo/Duo */
+		case 0x1c: /* Atom */
+			ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			break;
+		case 0xf:  /* Core 2 or Xeon */
+		case 0x17: /* Enhanced Core */
+			ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			break;
+		case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
+		case 0x3c: /* Haswell BCLK fixed at 100MHz */
+		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+			ret = 100;
+			break;
+		}
+		break;
+	case 0xf: /* Netburst */
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
+		switch (c.x86_model) {
+		case 0x2:
+			ret = f2x_fsb[(msr.lo >> 16) & 7];
+			break;
+		case 0x3:
+		case 0x4:
+		case 0x6:
+			ret = core2_fsb[(msr.lo >> 16) & 7];
+			break;
+		}
+	}
+	if (ret == -1)
+		printk(BIOS_ERR, "FSB not found\n");
+	if (ret == -2)
+		printk(BIOS_ERR, "CPU not supported\n");
+	return ret;
+}
+
+/**
+ * @brief Returns three times the FSB clock in MHz
+ *
+ * The result of calculations with the returned value shall be divided by 3.
+ * This helps to avoid rounding errors.
+ */
+int get_ia32_fsb_x3(void)
+{
+	const int fsb = get_ia32_fsb();
+
+	if (fsb > 0)
+		return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100);
+
+	printk(BIOS_ERR, "FSB not supported or not found\n");
+	return -1;
+}
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -26,9 +26,11 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
+	select MMX
 	select SSE2
 	select UDELAY_LAPIC
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select MICROCODE_BLOB_NOT_IN_BLOB_REPO
 	select PARALLEL_CPU_INIT
 	select TSC_SYNC_MFENCE
 	select LAPIC_MONOTONIC_TIMER

diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -17,6 +17,14 @@ ramstage-y += model_406dx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
 
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../turbo
+
 ramstage-y += acpi.c
 
 CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
@@ -0,0 +1,7 @@
+config MICROCODE_UPDATE_PRE_RAM
+	bool
+	depends on SUPPORT_CPU_UCODE_IN_CBFS
+	default y if C_ENVIRONMENT_BOOTBLOCK
+	help
+	  Select this option if you want to update the microcode
+	  during the cache as ram setup.
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
@@ -1,8 +1,5 @@
-################################################################################
-## One small file with the awesome super-power of updating the CPU microcode
-## directly from CBFS. You have been WARNED!!!
-################################################################################
+bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S
+romstage-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S
+
 ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
 romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
-
-cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
@@ -27,7 +27,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
-#include <rules.h>
 
 #if !defined(__PRE_RAM__)
 #include <smp/spinlock.h>
@@ -89,8 +88,12 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
 	current_rev = read_microcode_rev();
 
 	/* No use loading the same revision. */
-	if (current_rev == m->rev)
+	if (current_rev == m->rev) {
+#if !defined(__ROMCC__)
+		printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n");
+#endif
 		return;
+	}
 
 #if ENV_RAMSTAGE
 	/*SoC specific check to update microcode*/
@@ -104,11 +107,19 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
 	msr.hi = 0;
 	wrmsr(IA32_BIOS_UPDT_TRIG, msr);
 
+	current_rev = read_microcode_rev();
+	if (current_rev == m->rev) {
 #if !defined(__ROMCC__)
-	printk(BIOS_DEBUG, "microcode: updated to revision "
+		printk(BIOS_INFO, "microcode: updated to revision "
 		    "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
 		    m->date & 0xffff, (m->date >> 24) & 0xff,
 		    (m->date >> 16) & 0xff);
+#endif
+		return;
+	}
+
+#if !defined(__ROMCC__)
+	printk(BIOS_INFO, "microcode: Update failed\n");
 #endif
 }
 

diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
@@ -1,4 +1,5 @@
 ramstage-y += model_1067x_init.c
+ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1

diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -19,14 +19,13 @@
 #include <device/device.h>
 #include <string.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/mp.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
+#include <cpu/intel/smm/gen1/smi.h>
 #include <cpu/intel/common/common.h>
 #include "chip.h"
 
@@ -278,26 +277,16 @@ static void model_1067x_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
-	intel_update_microcode_from_cbfs();
-
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Setup MTRRs */
-	x86_setup_mtrrs();
-	x86_mtrr_check();
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Initialize the APIC timer */
 	init_timer();
 
-	/* Set virtualization based on Kconfig option */
-	set_vmx_and_lock();
-
 	/* Configure C States */
 	configure_c_states(quad);
 
@@ -313,9 +302,6 @@ static void model_1067x_init(struct device *cpu)
 
 	/* PIC thermal sensor control */
 	configure_pic_thermal_sensors(tm2, quad);
-
-	/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *               2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/mp.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include <cpu/intel/common/common.h>
+
+/* Parallel MP initialization support. */
+static const void *microcode_patch;
+
+static void pre_mp_init(void)
+{
+	/* Setup MTRRs based on physical address size. */
+	x86_setup_mtrrs_with_detect();
+	x86_mtrr_check();
+}
+
+static int get_cpu_count(void)
+{
+	const struct cpuid_result cpuid1 = cpuid(1);
+	const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+	printk(BIOS_DEBUG, "CPU has %u cores.\n", cores);
+
+	return cores;
+}
+
+/* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL
+   to enable SMRR so configure IA32_FEATURE_CONTROL early on */
+static void pre_mp_smm_init(void)
+{
+	smm_initialize();
+}
+
+#define SMRR_SUPPORTED (1 << 11)
+
+static void per_cpu_smm_trigger(void)
+{
+	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+		set_feature_ctrl_vmx();
+		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+		/* We don't care if the lock is already setting
+		   as our smm relocation handler is able to handle
+		   setups where SMRR is not enabled here. */
+		if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
+			printk(BIOS_INFO,
+			       "Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
+		ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+		wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+	} else {
+		set_vmx_and_lock();
+	}
+
+	/* Relocate the SMM handler. */
+	smm_relocate();
+
+	/* After SMM relocation a 2nd microcode load is required. */
+	intel_microcode_load_unlocked(microcode_patch);
+}
+
+static void post_mp_init(void)
+{
+	/* Now that all APs have been relocated as well as the BSP let SMIs
+	 * start flowing. */
+	southbridge_smm_init();
+
+	/* Lock down the SMRAM space. */
+	smm_lock();
+}
+
+static const struct mp_ops mp_ops = {
+	.pre_mp_init = pre_mp_init,
+	.get_cpu_count = get_cpu_count,
+	.get_smm_info = smm_info,
+	.pre_mp_smm_init = pre_mp_smm_init,
+	.per_cpu_smm_trigger = per_cpu_smm_trigger,
+	.relocation_handler = smm_relocation_handler,
+	.post_mp_init = post_mp_init,
+};
+
+void bsp_init_and_start_aps(struct bus *cpu_bus)
+{
+	if (mp_init_with_smm(cpu_bus, &mp_ops))
+		printk(BIOS_ERR, "MP initialization failure.\n");
+}
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
@@ -2,5 +2,6 @@ ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -17,12 +17,9 @@
 #include <device/device.h>
 #include <string.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include <cpu/intel/common/common.h>
@@ -84,33 +81,20 @@ static void model_106cx_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
-	intel_update_microcode_from_cbfs();
-
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Setup MTRRs */
-	x86_setup_mtrrs();
-	x86_mtrr_check();
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-	/* Set virtualization based on Kconfig option */
-	set_vmx_and_lock();
-
 	/* Configure C States */
 	configure_c_states();
 
 	/* Configure Enhanced SpeedStep and Thermal Sensors */
 	configure_misc();
 
 	/* TODO: PIC thermal sensor control */
-
-	/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
@@ -77,7 +77,6 @@ void intel_model_2065x_finalize_smm(void);
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
-void smm_relocate(void);
 #endif
 
 #endif
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
@@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
+	select MMX
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
@@ -23,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+	select PARALLEL_MP
 
 config BOOTBLOCK_CPU_INIT
 	string

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
@@ -3,6 +3,14 @@ subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
 subdirs-y += ../common
 
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../turbo
+
 ramstage-y += acpi.c
 
 ramstage-y += common.c

diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
@@ -22,6 +22,7 @@
 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
 #define SANDYBRIDGE_BCLK		100
 
+#define CORE_THREAD_COUNT_MSR		0x35
 #define MSR_FEATURE_CONFIG		0x13c
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)
@@ -109,7 +110,6 @@ void intel_model_206ax_finalize_smm(void);
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
-void smm_relocate(void);
 #endif
 int get_platform_id(void);
 

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <assert.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <string.h>
@@ -24,6 +25,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
@@ -426,83 +428,6 @@ static void configure_mca(void)
 		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 }
 
-int cpu_get_apic_id_map(int *apic_id_map)
-{
-	struct cpuid_result result;
-	unsigned int threads_per_package, threads_per_core, i, shift = 0;
-
-	/* Logical processors (threads) per core */
-	result = cpuid_ext(0xb, 0);
-	threads_per_core = result.ebx & 0xffff;
-
-	/* Logical processors (threads) per package */
-	result = cpuid_ext(0xb, 1);
-	threads_per_package = result.ebx & 0xffff;
-
-	if (threads_per_core == 1)
-		shift++;
-
-	for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; i++)
-		apic_id_map[i] = i << shift;
-
-	return threads_per_package;
-}
-
-/*
- * Initialize any extra cores/threads in this package.
- */
-static void intel_cores_init(struct device *cpu)
-{
-	struct cpuid_result result;
-	unsigned int threads_per_package, threads_per_core, i;
-
-	/* Logical processors (threads) per core */
-	result = cpuid_ext(0xb, 0);
-	threads_per_core = result.ebx & 0xffff;
-
-	/* Logical processors (threads) per package */
-	result = cpuid_ext(0xb, 1);
-	threads_per_package = result.ebx & 0xffff;
-
-	/* Only initialize extra cores from BSP */
-	if (cpu->path.apic.apic_id)
-		return;
-
-	printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n",
-	       cpu->path.apic.apic_id, threads_per_package/threads_per_core,
-	       threads_per_core);
-
-	for (i = 1; i < threads_per_package; ++i) {
-		struct device_path cpu_path;
-		struct device *new;
-
-		/* Build the CPU device path */
-		cpu_path.type = DEVICE_PATH_APIC;
-		cpu_path.apic.apic_id =
-			cpu->path.apic.apic_id + i;
-
-		/* Update APIC ID if no hyperthreading */
-		if (threads_per_core == 1)
-			cpu_path.apic.apic_id <<= 1;
-
-		/* Allocate the new CPU device structure */
-		new = alloc_dev(cpu->bus, &cpu_path);
-		if (!new)
-			continue;
-
-		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
-		       cpu->path.apic.apic_id,
-		       new->path.apic.apic_id);
-
-		/* Start the new CPU */
-		if (is_smp_boot() && !start_cpu(new)) {
-			/* Record the error in cpu? */
-			printk(BIOS_ERR, "CPU %u would not start!\n",
-			       new->path.apic.apic_id);
-		}
-	}
-}
-
 static void model_206ax_report(void)
 {
 	static const char *const mode[] = {"NOT ", ""};
@@ -536,18 +461,12 @@ static void model_206ax_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	intel_update_microcode_from_cbfs();
-
 	/* Clear out pending MCEs */
 	configure_mca();
 
 	/* Print infos */
 	model_206ax_report();
 
-	/* Setup MTRRs based on physical address size */
-	x86_setup_mtrrs_with_detect();
-	x86_mtrr_check();
-
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
@@ -578,9 +497,75 @@ static void model_206ax_init(struct device *cpu)
 
 	/* Enable Turbo */
 	enable_turbo();
+}
+
+/* MP initialization support. */
+static const void *microcode_patch;
 
-	/* Start up extra cores */
-	intel_cores_init(cpu);
+static void pre_mp_init(void)
+{
+	/* Setup MTRRs based on physical address size. */
+	x86_setup_mtrrs_with_detect();
+	x86_mtrr_check();
+}
+
+static int get_cpu_count(void)
+{
+	msr_t msr;
+	int num_threads;
+	int num_cores;
+
+	msr = rdmsr(CORE_THREAD_COUNT_MSR);
+	num_threads = (msr.lo >> 0) & 0xffff;
+	num_cores = (msr.lo >> 16) & 0xffff;
+	printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
+	       num_cores, num_threads);
+
+	return num_threads;
+}
+
+static void get_microcode_info(const void **microcode, int *parallel)
+{
+	microcode_patch = intel_microcode_find();
+	*microcode = microcode_patch;
+	*parallel = 1;
+}
+
+static void per_cpu_smm_trigger(void)
+{
+	/* Relocate the SMM handler. */
+	smm_relocate();
+
+	/* After SMM relocation a 2nd microcode load is required. */
+	intel_microcode_load_unlocked(microcode_patch);
+}
+
+static void post_mp_init(void)
+{
+	/* Now that all APs have been relocated as well as the BSP let SMIs
+	 * start flowing. */
+	southbridge_smm_init();
+
+	/* Lock down the SMRAM space. */
+	smm_lock();
+}
+
+
+static const struct mp_ops mp_ops = {
+	.pre_mp_init = pre_mp_init,
+	.get_cpu_count = get_cpu_count,
+	.get_smm_info = smm_info,
+	.get_microcode_info = get_microcode_info,
+	.pre_mp_smm_init = smm_initialize,
+	.per_cpu_smm_trigger = per_cpu_smm_trigger,
+	.relocation_handler = smm_relocation_handler,
+	.post_mp_init = post_mp_init,
+};
+
+void bsp_init_and_start_aps(struct bus *cpu_bus)
+{
+	if (mp_init_with_smm(cpu_bus, &mp_ops))
+		printk(BIOS_ERR, "MP initialization failure.\n");
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
@@ -2,5 +2,6 @@ ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+ramstage-y += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -18,11 +18,8 @@
 #include <device/device.h>
 #include <string.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/hyperthreading.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -118,26 +115,16 @@ static void model_6ex_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
-	intel_update_microcode_from_cbfs();
-
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Setup MTRRs */
-	x86_setup_mtrrs();
-	x86_mtrr_check();
-
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-	/* Set virtualization based on Kconfig option */
-	set_vmx_and_lock();
-
 	/* Configure C States */
 	configure_c_states();
 
@@ -146,9 +133,6 @@ static void model_6ex_init(struct device *cpu)
 
 	/* PIC thermal sensor control */
 	configure_pic_thermal_sensors();
-
-	/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
@@ -1,6 +1,7 @@
 ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -18,11 +18,8 @@
 #include <device/device.h>
 #include <string.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/hyperthreading.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -132,26 +129,16 @@ static void model_6fx_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
-	intel_update_microcode_from_cbfs();
-
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Setup MTRRs */
-	x86_setup_mtrrs();
-	x86_mtrr_check();
-
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
-	/* Set virtualization based on Kconfig option */
-	set_vmx_and_lock();
-
 	/* Configure C States */
 	configure_c_states();
 
@@ -160,9 +147,6 @@ static void model_6fx_init(struct device *cpu)
 
 	/* PIC thermal sensor control */
 	configure_pic_thermal_sensors();
-
-	/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
 ramstage-y += model_6xx_init.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_66x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,4 +1,5 @@
 ramstage-y += model_f3x_init.c
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -24,7 +24,7 @@ static void model_f3x_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	if (!intel_ht_sibling()) {
+	if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
 		/* MTRRs are shared between threads */
 		x86_setup_mtrrs();
 		x86_mtrr_check();
@@ -37,7 +37,8 @@ static void model_f3x_init(struct device *cpu)
 	setup_lapic();
 
 	/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
+	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+		intel_sibling_init(cpu);
 };
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,4 +1,5 @@
 ramstage-y += model_f4x_init.c
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -13,31 +13,16 @@
 
 #include <device/device.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 
 static void model_f4x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	if (!intel_ht_sibling()) {
-		/* MTRRs are shared between threads */
-		x86_setup_mtrrs();
-		x86_mtrr_check();
-
-		/* Update the microcode */
-		intel_update_microcode_from_cbfs();
-	}
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
-
-	/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
 };
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
@@ -11,6 +11,10 @@
  * GNU General Public License for more details.
  */
 
+#include <device/device.h>
+
+void bsp_init_and_start_aps(struct bus *cpu_bus);
+
 /* These helpers are for performing SMM relocation. */
 void southbridge_smm_init(void);
 void southbridge_trigger_smi(void);
@@ -19,3 +23,14 @@ u32 northbridge_get_tseg_base(void);
 u32 northbridge_get_tseg_size(void);
 int cpu_get_apic_id_map(int *apic_id_map);
 void northbridge_write_smram(u8 smram);
+
+bool cpu_has_alternative_smrr(void);
+
+/* parallel MP helper functions */
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size);
+void smm_initialize(void);
+void southbridge_smm_clear_state(void);
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+			uintptr_t staggered_smbase);
+void smm_relocate(void);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -22,10 +22,12 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>
+#include <smp/node.h>
 #include "smi.h"
 
 #define SMRR_SUPPORTED (1 << 11)
@@ -56,17 +58,31 @@ struct smm_relocation_params {
 static struct smm_relocation_params smm_reloc_params;
 static void *default_smm_area = NULL;
 
-static void write_smrr(struct smm_relocation_params *relo_params)
+/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
+   differently. The MSR are at different location from the rest
+   and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
+bool cpu_has_alternative_smrr(void)
 {
 	struct cpuinfo_x86 c;
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return false;
+	switch (c.x86_model) {
+	case 0xf:
+	case 0x17: /* core2 */
+	case 0x1c: /* Bonnell */
+		return true;
+	default:
+		return false;
+	}
+}
 
+static void write_smrr(struct smm_relocation_params *relo_params)
+{
 	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
 	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-	/* Both model_6fx and model_1067x SMRR function slightly differently
-	   from the rest. The MSR are at different location from the rest
-	   and need to be explicitly enabled. */
-	get_fms(&c, cpuid_eax(1));
-	if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {
+
+	if (cpu_has_alternative_smrr()) {
 		msr_t msr;
 		msr = rdmsr(IA32_FEATURE_CONTROL);
 		/* SMRR enabled and feature locked */
@@ -132,7 +148,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
 
 	/* Write SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (mtrr_cap.lo & SMRR_SUPPORTED)
+	if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0)
 		write_smrr(relo_params);
 
 	southbridge_clear_smi_status();
@@ -171,7 +187,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 		/* On model_6fx and model_1067x bits [0:11] on smrr_base
 		   are reserved */
 		get_fms(&c, cpuid_eax(1));
-		if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
+		if (cpu_has_alternative_smrr())
 			params->smrr_base.lo = (params->smram_base & rmask);
 		else
 			params->smrr_base.lo = (params->smram_base & rmask)
@@ -335,3 +351,82 @@ void smm_lock(void)
 
 	northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);
 }
+
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		size_t *smm_save_state_size)
+{
+	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+	fill_in_relocation_params(&smm_reloc_params);
+
+	if (CONFIG_IED_REGION_SIZE != 0)
+		setup_ied_area(&smm_reloc_params);
+
+	*perm_smbase = smm_reloc_params.smram_base;
+	*perm_smsize = smm_reloc_params.smram_size;
+	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
+}
+
+void smm_initialize(void)
+{
+	/* Clear the SMM state in the southbridge. */
+	southbridge_smm_clear_state();
+
+	/*
+	 * Run the relocation handler for on the BSP to check and set up
+	 * parallel SMM relocation.
+	 */
+	smm_initiate_relocation();
+}
+
+/* The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here. */
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase)
+{
+	msr_t mtrr_cap;
+	struct smm_relocation_params *relo_params = &smm_reloc_params;
+	em64t101_smm_state_save_area_t *save_state;
+	u32 smbase = staggered_smbase;
+	u32 iedbase = relo_params->ied_base;
+
+	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+
+	/* Make appropriate changes to the save state map. */
+	if (CONFIG_IED_REGION_SIZE != 0)
+		printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
+		       smbase, iedbase);
+	else
+		printk(BIOS_DEBUG, "New SMBASE=0x%08x\n",
+		       smbase);
+
+	save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
+			sizeof(*save_state));
+	save_state->smbase = smbase;
+	save_state->iedbase = iedbase;
+
+	/* Write EMRR and SMRR MSRs based on indicated support. */
+	mtrr_cap = rdmsr(MTRR_CAP_MSR);
+	if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0)
+		write_smrr(relo_params);
+}
+
+/*
+ * The default SMM entry can happen in parallel or serially. If the
+ * default SMM entry is done in parallel the BSP has already setup
+ * the saving state to each CPU's MSRs. At least one save state size
+ * is required for the initial SMM entry for the BSP to determine if
+ * parallel SMM relocation is even feasible.
+ */
+void smm_relocate(void)
+{
+	/*
+	 * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
+	 * shall take place. Run the relocation handler a second time on the
+	 * BSP to do the final move. For APs, a relocation handler always
+	 * needs to be run.
+	 */
+	if (!boot_cpu())
+		smm_initiate_relocation();
+}
diff --git a/src/cpu/intel/socket_FCBGA1023/Kconfig b/src/cpu/intel/socket_FCBGA1023/Kconfig
diff --git a/src/cpu/intel/socket_FCBGA1023/Makefile.inc b/src/cpu/intel/socket_FCBGA1023/Makefile.inc
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -1,5 +1,7 @@
 config CPU_INTEL_SOCKET_FCBGA559
 	bool
+	help
+	  Select this socket on Intel Pineview
 
 if CPU_INTEL_SOCKET_FCBGA559
 
@@ -8,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
+	select CPU_HAS_L2_ENABLE_MSR
 
 config DCACHE_RAM_BASE
 	hex

diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -8,7 +8,7 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
-postcar-y += ../car/p4-netburst/exit_car.S
+cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+postcar-y += ../car/non-evict/exit_car.S
 
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_LGA1155/Kconfig b/src/cpu/intel/socket_LGA1155/Kconfig
diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -10,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select SSE
 	select UDELAY_TSC
 	select SIPI_VECTOR_IN_ROM
+	select C_ENVIRONMENT_BOOTBLOCK
 
 # mPGA604 are usually Intel Netburst CPUs which should have SSE2
 # but the ramtest.c code on the Dell S1850 seems to choke on
@@ -26,4 +27,8 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
 endif # CPU_INTEL_SOCKET_MPGA604
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -7,6 +7,8 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+
 postcar-y += ../car/p4-netburst/exit_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig
diff --git a/src/cpu/intel/socket_rPGA988B/Makefile.inc b/src/cpu/intel/socket_rPGA988B/Makefile.inc
diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
diff --git a/src/cpu/intel/socket_rPGA989/Makefile.inc b/src/cpu/intel/socket_rPGA989/Makefile.inc
diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig
@@ -5,7 +5,6 @@ config CPU_TI_AM335X
 	select ARCH_RAMSTAGE_ARMV7
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_UART_SPECIAL
-	select BOOTBLOCK_CONSOLE
 	select GENERIC_UDELAY
 	select UART_OVERRIDE_REFCLK
 	select BOOT_DEVICE_NOT_SPI_FLASH

diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
@@ -28,6 +28,14 @@
  */
 
 #include <arch/rom_segs.h>
+
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
+    IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
+ * Startup IPI message without RAM.
+ */
+.align 4096
+#endif
 .code16
 .globl _start16bit
 .type _start16bit, @function

diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld
@@ -1,2 +1,3 @@
 	gdtptr16_offset = gdtptr16 & 0xffff;
 	nullidt_offset = nullidt & 0xffff;
+	ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff;
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
@@ -15,7 +15,6 @@
 
 #include <arch/rom_segs.h>
 #include <cpu/x86/post_code.h>
-#include <rules.h>
 #include <arch/x86/gdt_init.S>
 
 	.code32

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <arch/cpu.h>
 #include <arch/early_variables.h>
+#include <cpu/intel/fsb.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
@@ -44,53 +45,13 @@ static u32 g_timer_fsb CAR_GLOBAL;
 
 static int set_timer_fsb(void)
 {
-	struct cpuinfo_x86 c;
-	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
-	int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
-	int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
-	msr_t msr;
-
-	get_fms(&c, cpuid_eax(1));
-	switch (c.x86) {
-	case 0x6:
-		switch (c.x86_model) {
-		case 0xe:  /* Core Solo/Duo */
-		case 0x1c: /* Atom */
-			car_set_var(g_timer_fsb,
-				core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
-			return 0;
-		case 0xf:  /* Core 2 or Xeon */
-		case 0x17: /* Enhanced Core */
-			car_set_var(g_timer_fsb,
-				core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
-			return 0;
-		case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
-		case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
-		case 0x3c: /* Haswell BCLK fixed at 100MHz */
-		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
-			car_set_var(g_timer_fsb, 100);
-			return 0;
-		default:
-			car_set_var(g_timer_fsb, 200);
-			return 0;
-		}
-	case 0xf: /* Netburst */
-		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
-		switch (c.x86_model) {
-		case 0x2:
-			car_set_var(g_timer_fsb,
-				f2x_fsb[(msr.lo >> 16) & 7]);
-			return 0;
-		case 0x3:
-		case 0x4:
-		case 0x6:
-			car_set_var(g_timer_fsb,
-				core2_fsb[(msr.lo >> 16) & 7]);
-			return 0;
-		}  /* default: fallthrough */
-	default:
-		return -1;
+	int ia32_fsb = get_ia32_fsb();
+
+	if (ia32_fsb > 0) {
+		car_set_var(g_timer_fsb, ia32_fsb);
+		return 0;
 	}
+	return -1;
 }
 
 static inline u32 get_timer_fsb(void)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -263,13 +263,11 @@ volatile unsigned int secondary_cpu_index;
 int start_cpu(struct device *cpu)
 {
 	struct cpu_info *info;
-	unsigned long stack_end;
-	unsigned long stack_base;
-	unsigned long *stack;
+	uintptr_t stack_top;
+	uintptr_t stack_base;
 	unsigned long apicid;
 	unsigned int index;
 	unsigned long count;
-	int i;
 	int result;
 
 	spin_lock(&start_cpu_lock);
@@ -280,25 +278,23 @@ int start_cpu(struct device *cpu)
 	/* Get an index for the new processor */
 	index = ++last_cpu_index;
 
-	/* Find end of the new processor's stack */
-	stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) -
-			sizeof(struct cpu_info);
-
-	stack_base = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*(index+1));
-	printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index,
-		(void *)stack_base, (void *)stack_end);
-	/* poison the stack */
-	for (stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++)
-		stack[i/sizeof(*stack)] = 0xDEADBEEF;
-	stacks[index] = stack;
+	/* Find boundaries of the new processor's stack */
+	stack_top = ALIGN_DOWN((uintptr_t)_estack, CONFIG_STACK_SIZE);
+	stack_top -= (CONFIG_STACK_SIZE*index);
+	stack_base = stack_top - CONFIG_STACK_SIZE;
+	stack_top -= sizeof(struct cpu_info);
+	printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_top %p\n", index,
+		(void *)stack_base, (void *)stack_top);
+	stacks[index] = (void *)stack_base;
+
 	/* Record the index and which CPU structure we are using */
-	info = (struct cpu_info *)stack_end;
+	info = (struct cpu_info *)stack_top;
 	info->index = index;
 	info->cpu   = cpu;
 	thread_init_cpu_info_non_bsp(info);
 
 	/* Advertise the new stack and index to start_cpu */
-	secondary_stack = stack_end;
+	secondary_stack = stack_top;
 	secondary_cpu_index = index;
 
 	/* Until the CPU starts up report the CPU is not enabled */
-Original file line number
+Diff line change
@@ Expand Up / @@ -14,7 +14,6 @@ @@
      */
     #include <random.h>
-    #include <rules.h>
     /*
      * Intel recommends that applications attempt 10 retries in a tight loop
@@ Expand Down @@