| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,83 @@ | ||
| # Star LabTop Mk III | ||
|
|
||
| ## Specs | ||
|
|
||
| - CPU (full processor specs available at https://ark.intel.com) | ||
| - Intel i7-8550u (Kaby Lake Refresh) | ||
| - EC | ||
| - ITE IT8987E | ||
| - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys | ||
| - Battery | ||
| - Charger, using AC adapter or USB-C PD | ||
| - Suspend / resume | ||
| - GPU | ||
| - Intel UHD Graphics 620 | ||
| - GOP driver is recommended, VBT is provided | ||
| - eDP 13-inch 1920x1080 LCD | ||
| - HDMI video | ||
| - USB-C DisplayPort video | ||
| - Memory | ||
| - 8GB on-board | ||
| - Networking | ||
| - 8265 PCIe WiFi / Bluetooth soldered to PCBA | ||
| - Sound | ||
| - Realtek ALC256 | ||
| - Internal speakers | ||
| - Internal microphone | ||
| - Combined headphone / microphone 3.5-mm jack | ||
| - HDMI audio | ||
| - USB-C DisplayPort audio | ||
| - Storage | ||
| - M.2 PCIe SSD | ||
| - RTS5129 MicroSD card reader | ||
| - USB | ||
| - 1280x720 CCD camera | ||
| - USB 3.1 Gen 2 Type-C (left) | ||
| - USB 3.1 Gen 2 Type-A (left) | ||
| - USB 3.1 Gen 1 Type-A (right) | ||
|
|
||
| ## Building coreboot | ||
|
|
||
| ### Preliminaries | ||
|
|
||
| Prior to building coreboot the following files are required: | ||
| * Intel Flash Descriptor file (descriptor.bin) | ||
| * Intel Management Engine firmware (me.bin) | ||
|
|
||
| The below are optional: | ||
| - Splash screen image in Windows 3.1 BMP format (Logo.bmp) | ||
|
|
||
| These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. | ||
|
|
||
| ### Build | ||
|
|
||
| The following commands will build a working image: | ||
|
|
||
| ```bash | ||
| make distclean | ||
| make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl | ||
| make | ||
| ``` | ||
|
|
||
| ## Flashing coreboot | ||
|
|
||
| ```eval_rst | ||
| +---------------------+------------+ | ||
| | Type | Value | | ||
| +=====================+============+ | ||
| | Socketed flash | no | | ||
| +---------------------+------------+ | ||
| | Vendor | Gigadevice | | ||
| +---------------------+------------+ | ||
| | Model | 25Q128JVSQ | | ||
| +---------------------+------------+ | ||
| | Size | 8 MiB | | ||
| +---------------------+------------+ | ||
| | Package | SOIC-8 | | ||
| +---------------------+------------+ | ||
| | Internal flashing | yes | | ||
| +---------------------+------------+ | ||
| | External flashing | yes | | ||
| +---------------------+------------+ | ||
| Please see [here](../common/flashing.md) for instructions on how to flash with fwupd. |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,19 +1,345 @@ | ||
| coreboot 4.17 | ||
| ======================================================================== | ||
|
|
||
| The coreboot 4.17 release was done on June 3, 2022. | ||
|
|
||
| Since the 4.16 release, we've had over 1300 new commits by around 150 | ||
| contributors. Of those people, roughly 15 were first-time contributors. | ||
|
|
||
| As always, we appreciate everyone who has contributed and done the hard | ||
| work to make the coreboot project successful. | ||
|
|
||
|
|
||
| Major Bugfixes in this release | ||
| ------------------------------ | ||
| * [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264) | ||
|
|
||
|
|
||
| New Mainboards | ||
| -------------- | ||
|
|
||
| * Clevo L140MU / L141MU / L142MU | ||
| * Dell Precision T1650 | ||
| * Google Craask | ||
| * Google Gelarshie | ||
| * Google Kuldax | ||
| * Google Mithrax | ||
| * Google Osiris | ||
| * HP Z220 CMT Workstation | ||
| * Star Labs LabTop Mk III (i7-8550u) | ||
| * Star Labs LabTop Mk IV (i3-10110U and i7-10710U) | ||
| * Star Labs Lite Mk III (N5000) | ||
| * Star Labs Lite Mk IV (N5030) | ||
|
|
||
|
|
||
| Removed Mainboards | ||
| ------------------ | ||
|
|
||
| * Google Deltan | ||
| * Google Deltaur | ||
|
|
||
| Significant or interesting changes | ||
| ---------------------------------- | ||
|
|
||
| These changes are a few that were selected as a sampling of particularly | ||
| interesting commits. | ||
|
|
||
|
|
||
| ### CBMEM init hooks changed | ||
|
|
||
| Instead of having per stage x_CBMEM_INIT_HOOK, we now have only 2 hooks: | ||
| * CBMEM_CREATION_HOOK: Used only in the first stage that creates cbmem, | ||
| typically romstage. For instance code that migrates data from cache | ||
| as ram to dram would use this hook. | ||
| * CBMEM_READY_HOOK: Used in every stage that has cbmem. An example would | ||
| be initializing the cbmem console by appending to what previous stages | ||
| logged. | ||
| The reason for this change is improved flexibility with regards to which | ||
| stage initializes cbmem. | ||
|
|
||
|
|
||
| ### Payloads | ||
|
|
||
| * SeaBIOS: Update stable release from 1.14.0 to 1.16.0 | ||
| * iPXE: Update stable release from 2019.3 to 2022.1 | ||
| * Add "GRUB2 atop SeaBIOS" aka "SeaGRUB" option, which builds GRUB2 as a | ||
| secondary payload for SeaBIOS with GRUB2 set as the default boot | ||
| entry. This allows GRUB2 to use BIOS callbacks provided by SeaBIOS as | ||
| a fallback method to access hardware that the native GRUB2 payload | ||
| cannot access. | ||
| * Add option to build SeaBIOS and GRUB2 as secondary payloads | ||
| * Add new coreDOOM payload. See commit message below. | ||
|
|
||
|
|
||
| ### payloads/external: Add support for coreDOOM payload | ||
|
|
||
| coreDOOM is a port of DOOM to libpayload, based on the doomgeneric | ||
| source port. It renders the game to the coreboot linear framebuffer, | ||
| and loads WAD files from CBFS. | ||
|
|
||
|
|
||
| ### cpu/x86/smm_module_load: Rewrite setup_stub | ||
|
|
||
| This code was hard to read as it did too much and had a lot of state | ||
| to keep track of. | ||
|
|
||
| It also looks like the staggered entry points were first copied and | ||
| only later the parameters of the first stub were filled in. This | ||
| means that only the BSP stub is actually jumping to the permanent | ||
| smihandler. On the APs the stub would jump to wherever c_handler | ||
| happens to point to, which is likely 0. This effectively means that on | ||
| APs it's likely easy to have arbitrary code execution in SMM which is a | ||
| security problem. | ||
|
|
||
| Note: This patch fixes CVE-2022-29264 for the 4.17 release. | ||
|
|
||
|
|
||
| ### cpu/x86/smm_module_loader.c: Rewrite setup | ||
|
|
||
| This code is much easier to read if one does not have to keep track of | ||
| mutable variables. | ||
|
|
||
| This also fixes the alignment code on the TSEG smihandler setup code. | ||
| It was aligning the code upwards instead of downwards which would cause | ||
| it to encroach a part of the save state. | ||
|
|
||
|
|
||
| ### cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub | ||
|
|
||
| The sinkhole exploit exists in placing the lapic base such that it | ||
| messes with GDT. This can be mitigated by checking the lapic MSR | ||
| against the current program counter. | ||
|
|
||
|
|
||
| ### cpu/x86/64bit: Generate static page tables from an assembly file | ||
|
|
||
| This removes the need for a tool to generate simple identity pages. | ||
| Future patches will link this page table directly into the stages on | ||
| some platforms so having an assembly file makes a lot of sense. | ||
|
|
||
| This also optimizes the size of the page of each 4K page by placing | ||
| the PDPE_table below the PDE. | ||
|
|
||
|
|
||
| ### cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI | ||
|
|
||
| This change will allow the SMI handler to write to the cbmem console | ||
| buffer. Normally SMIs can only be debugged using some kind of serial | ||
| port (UART). By storing the SMI logs into cbmem we can debug SMIs using | ||
| 'cbmem -1'. Now that these logs are available to the OS we could also | ||
| verify there were no errors in the SMI handler. | ||
|
|
||
| Since SMM can write to all of DRAM, we can't trust any pointers | ||
| provided by cbmem after the OS has booted. For this reason we store the | ||
| cbmem console pointer as part of the SMM runtime parameters. The cbmem | ||
| console is implemented as a circular buffer so it will never write | ||
| outside of this area. | ||
|
|
||
|
|
||
| ### security/tpm/crtm: Add a function to measure the bootblock on SoC level | ||
|
|
||
| On platforms where the bootblock is not included in CBFS anymore | ||
| because it is part of another firmware section (IFWI or a different | ||
| CBFS), the CRTM measurement fails. | ||
|
|
||
| This patch adds a new function to provide a way at SoC level to measure | ||
| the bootblock. Following patches will add functionality to retrieve the | ||
| bootblock from the SoC related location and measure it from there. | ||
| In this way the really executed code will be measured. | ||
|
|
||
|
|
||
| ### soc/amd/common/block/psp: Add platform secure boot support | ||
|
|
||
| Add Platform Secure Boot (PSB) enablement via the PSP if it is not | ||
| already enabled. Upon receiving psb command, PSP will program PSB fuses | ||
| as long as BIOS signing key token is valid. | ||
| Refer to the AMD PSB user guide doc# 56654, Revision# 1.00. | ||
| Unfortunately this document is only available with NDA customers. | ||
|
|
||
|
|
||
| ### drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler | ||
|
|
||
| This patch implements coreboot native debug handler to manage the FSP | ||
| event messages. | ||
|
|
||
| 'FSP Event Handlers' feature introduced in FSP to generate event | ||
| messages to aid in the debugging of firmware issues. This eliminates | ||
| the need for FSP to directly write debug messages to the UART and FSP | ||
| might not need to know the board related UART port configuration. | ||
| Instead FSP signals the bootloader to inform it of a new debug message. | ||
| This allows the coreboot to provide board specific methods of reporting | ||
| debug messages, example: legacy UART or LPSS UART etc. | ||
|
|
||
| This implementation has several advantages as: | ||
| 1. FSP relies on XIP 'DebugLib' driver even while printing FSP-S debug | ||
| messages, hence, without ROM being cached, post 'romstage' would | ||
| results into sluggish boot with FSP debug enabled. | ||
| This patch utilities coreboot native debug implementation which is | ||
| XIP during FSP-M and relocatable to DRAM based resource for FSP-S. | ||
|
|
||
| 2. This patch simplifies the FSP DebugLib implementation and remove the | ||
| need to have serial port library. Instead coreboot 'printk' can be | ||
| used for display FSP serial messages. Additionally, unifies the debug | ||
| library between coreboot and FSP. | ||
|
|
||
| 3. This patch is also useful to get debug prints even with FSP | ||
| non-serial image (refer to 'Note' below) as FSP PEIMs are now | ||
| leveraging coreboot debug library instead FSP 'NULL' DebugLib | ||
| reference for release build. | ||
|
|
||
| 4. Can optimize the FSP binary size by removing the DebugLib dependency | ||
| from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary | ||
| size is reduced by ~100KB+ and FSP-S debug library size is also | ||
| reduced by ~300KB+ (FSP-S debug and release binary size is exactly | ||
| same with this code changes). The total savings is ~400KB for each | ||
| FSP copy, and in case of Chrome AP firmware with 3 copies, the total | ||
| savings would be 400KB * 3 = ~1.2MB. | ||
|
|
||
| Note: Need to modify FSP source code to remove 'MDEPKG_NDEBUG' as | ||
| compilation flag for release build and generate FSP binary with non-NULL | ||
| FSP debug wrapper module injected (to allow FSP event handler to execute | ||
| even with FSP non-serial image) in the final FSP.fd. | ||
|
|
||
|
|
||
| ### security/tpm: Add vendor-specific tis functions to read/write TPM regs | ||
|
|
||
| In order to abstract bus-specific logic from TPM logic, the prototype | ||
| for two vendor-specific tis functions are added in this | ||
| patch. tis_vendor_read() can be used to read directly from TPM | ||
| registers, and tis_vendor_write() can be used to write directly to TPM | ||
| registers. | ||
|
|
||
|
|
||
| ### arch/x86: Add support for catching null dereferences through debug regs | ||
|
|
||
| This commit adds support for catching null dereferences and execution | ||
| through x86's debug registers. This is particularly useful when running | ||
| 32-bit coreboot as paging is not enabled to catch these through page | ||
| faults. This commit adds three new configs to support this feature: | ||
| DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and | ||
| DEBUG_NULL_DEREF_HALT. | ||
|
|
||
|
|
||
| ### drivers/i2c/generic: Add support for i2c device detection | ||
|
|
||
| Add 'detect' flag which can be attached to devices which may or may not | ||
| be present at runtime, and for which coreboot should probe the i2c bus | ||
| to confirm device presence prior to adding an entry for it in the SSDT. | ||
|
|
||
| This is useful for boards which may utilize touchpads/touchscreens from | ||
| multiple vendors, so that only the device(s) present are added to the | ||
| SSDT. This relieves the burden from the OS to detect/probe if a device | ||
| is actually present and allows the OS to trust the ACPI _STA value. | ||
|
|
||
|
|
||
| ### util/cbmem: Add FlameGraph-compatible timestamps output | ||
|
|
||
| Flame graphs are used to visualize hierarchical data, like call stacks. | ||
| Timestamps collected by coreboot can be processed to resemble | ||
| profiler-like output, and thus can be feed to flame graph generation | ||
| tools. | ||
|
|
||
| Generating flame graph using https://github.com/brendangregg/FlameGraph: | ||
| ``` | ||
| cbmem -S > trace.txt | ||
| FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg | ||
| ``` | ||
|
|
||
|
|
||
| ### src/console/Kconfig: Add option to disable loglevel prefix | ||
|
|
||
| This patch adds an option to disable loglevel prefixes. This patch helps | ||
| to achieve clear messages when low loglevel is used and very few | ||
| messages are displayed on a terminal. This option also allows to | ||
| maintain compatibility with log readers and continuous integration | ||
| systems that depend on fixed log content. | ||
|
|
||
| If the code contains: | ||
| printk(BIOS_DEBUG, "This is a debug message!\n") | ||
| it will show as: | ||
| [DEBUG] This is a debug message! | ||
| but if the Kconfig contains: | ||
| CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n | ||
| the same message will show up as | ||
| This is a debug message! | ||
|
|
||
|
|
||
| ### util/cbmem: add an option to append timestamp | ||
|
|
||
| Add an option to the cbmem utility that can be used to append an entry | ||
| to the cbmem timestamp table from userspace. This is useful for | ||
| bookkeeping of post-coreboot timing information while still being able | ||
| to use cbmem-based tooling for processing the generated data. | ||
|
|
||
|
|
||
| `-a | --add-timestamp ID: append timestamp with ID\n` | ||
|
|
||
|
|
||
| Additional changes | ||
| ------------------ | ||
|
|
||
| The following are changes across a number of patches, or changes worth | ||
| noting, but not needing a full description. | ||
|
|
||
| * As always, general documentation, code cleanup, and refactoring | ||
| * Remove doxygen config files and targets | ||
| * Get clang compile working for all x86 platforms | ||
| * Work on updating checkpatch to match the current Linux version | ||
| * Timestamps: Rename timestamps to make names more consistent | ||
| * Continue updating ACPI code to ASL 2.0 | ||
| * Remove redundant or unnecessary headers from C files | ||
| * arch/x86/acpi_bert_storage.c: Use a common implementation | ||
| * Postcar stage improvements | ||
| * arch/x86/acpi: Consolidate POST code handling | ||
| * intel/common: Enable ROM caching in ramstage | ||
| * vendorcode/amd/agesa: Fix improper use of .data (const is important) | ||
| * sandybridge & gm45: Support setting PCI bars above 4G | ||
|
|
||
|
|
||
| Plans for Code Deprecation | ||
| -------------------------- | ||
|
|
||
|
|
||
| ### Intel Icelake | ||
|
|
||
| Intel Icelake is unmaintained. Also, the only user of this platform ever was | ||
| the CRB board. From the looks of it the code never was ready for production as | ||
| only engineering sample CPUIDs are supported. | ||
|
|
||
| Thus, to reduce the maintanence overhead for the community, it is deprecated | ||
| from this release on and support for the following components will be dropped | ||
| with the release 4.19. | ||
|
|
||
| * Intel Icelake SoC | ||
| * Intel Icelake RVP mainboard | ||
|
|
||
|
|
||
| ### LEGACY_SMP_INIT | ||
|
|
||
| As of release 4.18 (August 2022) we plan to deprecate LEGACY_SMP_INIT. | ||
| This also includes the codepath for SMM_ASEG. This code is used to start | ||
| APs and do some feature programming on each AP, but also set up SMM. | ||
| This has largely been superseded by PARALLEL_MP, which should be able to | ||
| cover all use cases of LEGACY_SMP_INIT, with little code changes. The | ||
| reason for deprecation is that having 2 codepaths to do the virtually | ||
| the same increases maintenance burden on the community a lot, while also | ||
| being rather confusing. | ||
|
|
||
| No platforms in the tree have any hardware limitations that would block | ||
| migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase. | ||
|
|
||
|
|
||
| Statistics | ||
| ---------- | ||
|
|
||
| - Total Commits: 1305 | ||
| - Average Commits per day: 13.42 | ||
| - Total lines added: 51422 | ||
| - Average lines added per commit: 39.40 | ||
| - Number of patches adding more than 100 lines: 59 | ||
| - Average lines added per small commit: 24.73 | ||
| - Total lines removed: 66206 | ||
| - Average lines removed per commit: 50.73 | ||
| - Total difference between added and removed: -14784 | ||
| - Total authors: 146 | ||
| - New authors: 17 |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,56 @@ | ||
| Upcoming release - coreboot 4.18 | ||
| ================================ | ||
|
|
||
| The 4.18 release is planned for August 2022. | ||
|
|
||
| Update this document with changes that should be in the release notes. | ||
|
|
||
| * Please use Markdown. | ||
| * See the past few release notes for the general format. | ||
| * The chip and board additions and removals will be updated right | ||
| before the release, so those do not need to be added. | ||
|
|
||
| Significant changes | ||
| ------------------- | ||
|
|
||
| ### Add significant changes here | ||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
|
||
| Plans for Code Deprecation | ||
| -------------------------- | ||
|
|
||
|
|
||
| ### Intel Icelake | ||
|
|
||
| Intel Icelake code will be removed following the 4.19 release, planned | ||
| for November 2022. This consists of the Intel Icelake SOC and Intel | ||
| Icelake RVP mainboard | ||
|
|
||
| Intel Icelake is unmaintained. Also, the only user of this platform ever | ||
| was the CRB board. From the looks of it the code never was ready for | ||
| production as only engineering sample CPUIDs are supported. This reduces | ||
| the maintanence overhead for the coreboot project. | ||
|
|
||
|
|
||
| ### LEGACY_SMP_INIT | ||
|
|
||
| Legacy SMP init will be removed from the coreboot master branch | ||
| immediately following this release. Anyone looking for the latest | ||
| version of the code should find it on the 4.18 branch. | ||
|
|
||
| This also includes the codepath for SMM_ASEG. This code is used to start | ||
| APs and do some feature programming on each AP, but also set up SMM. | ||
| This has largely been superseded by PARALLEL_MP, which should be able to | ||
| cover all use cases of LEGACY_SMP_INIT, with little code changes. The | ||
| reason for deprecation is that having 2 codepaths to do the virtually | ||
| the same increases maintenance burden on the community a lot, while also | ||
| being rather confusing. |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,210 @@ | ||
| Intel Pad to Macro (intelp2m) converter | ||
| ======================================= | ||
|
|
||
| This utility allows one to convert the configuration DW0/1 register | ||
| values from an inteltool dump to coreboot macros. | ||
|
|
||
| ```bash | ||
| cd util/intelp2m | ||
| make | ||
| ./intelp2m -h | ||
| ./intelp2m -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ### Platforms | ||
|
|
||
| It is possible to use templates for parsing inteltool.log files. | ||
| To specify such a pattern, use the option `-t <template number>`. | ||
|
|
||
| ```text | ||
| -t | ||
| template type number | ||
| 0 - inteltool.log (default) | ||
| 1 - gpio.h | ||
| 2 - your template | ||
| ``` | ||
|
|
||
| For example, using template type 1, you can parse gpio.h from an | ||
| existing board in the coreboot project. | ||
|
|
||
| ```bash | ||
| ./intelp2m -t 1 -file coreboot/src/mainboard/yourboard/gpio.h | ||
| ``` | ||
|
|
||
| You can also add a template to 'parser/template.go' for your file type | ||
| with the configuration of the pads. | ||
|
|
||
| platform type is set using the -p option (Sunrise by default): | ||
|
|
||
| ```text | ||
| -p string | ||
| set up a platform | ||
| snr - Sunrise PCH with Skylake/Kaby Lake CPU | ||
| lbg - Lewisburg PCH with Xeon SP CPU | ||
| apl - Apollo Lake SoC | ||
| cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC | ||
| adl - AlderLake PCH | ||
| (default "snr") | ||
| ``` | ||
|
|
||
| ```bash | ||
| ./intelp2m -p <platform> -file path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ### Packages | ||
|
|
||
| ![][pckgs] | ||
|
|
||
| [pckgs]: gopackages.png | ||
|
|
||
| ### Bit fields in macros | ||
|
|
||
| Use the `-fld=cb` option to only generate a sequence of bit fields in | ||
| a new macro: | ||
|
|
||
| ```bash | ||
| ./intelp2m -fld cb -p apl -file ../apollo-inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| _PAD_CFG_STRUCT(GPIO_37, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_TRIG(OFF), \ | ||
| PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */ | ||
| ``` | ||
| ### Raw DW0, DW1 register value | ||
| To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register | ||
| values you need to use the -fld=raw option: | ||
| ```bash | ||
| ./intelp2m -fld raw -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), | ||
| ``` | ||
| ```bash | ||
| ./intelp2m -iiii -fld raw -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| /* GPP_A10 - CLKOUT_LPC1 */ | ||
| /* DW0: 0x44000500, DW1: 0x00000000 */ | ||
| /* DW0: 0x04000100 - IGNORED */ | ||
| /* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */ | ||
| _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000), | ||
| ``` | ||
| ### Macro Check | ||
| After generating the macro, the utility checks all used | ||
| fields of the configuration registers. If some field has been | ||
| ignored, the utility generates field macros. To not check | ||
| macros, use the -n option: | ||
| ```bash | ||
| ./intelp2m -n -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| In this case, some fields of the configuration registers | ||
| DW0 will be ignored. | ||
|
|
||
| ```c | ||
| PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), | ||
| PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), | ||
| ``` | ||
| ### Information level | ||
| The utility can generate additional information about the bit | ||
| fields of the DW0 and DW1 configuration registers. Using the | ||
| options -i, -ii, -iii, -iiii you can set the info level from | ||
| 1 to 4: | ||
| ```bash | ||
| ./intelp2m -i -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),\ | ||
| PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), /* LPSS_UART0_TXD */ | ||
| ``` | ||
| ```bash | ||
| ./intelp2m -ii -file /path/to/inteltool.log | ||
| ./intelp2m -iii -file /path/to/inteltool.log | ||
| ./intelp2m -iiii -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| /* GPIO_39 - LPSS_UART0_TXD */ | ||
| /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) | ||
| /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii) | ||
| /* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, | ||
| DISPUPD), */ --> (iiii) | ||
| _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), | ||
| PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), | ||
| ``` | ||
| If the -n switch was used and macros was generated without checking: | ||
| ```c | ||
| /* GPIO_39 - LPSS_UART0_TXD */ --> (i) | ||
| /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) | ||
| /* DW0: PAD_TRIG(OFF) - IGNORED */ --> (iii) | ||
| /* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | | ||
| PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */ --> (iiii) | ||
| PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, \ | ||
| DISPUPD), | ||
| ``` | ||
|
|
||
| ### Ignoring Fields | ||
|
|
||
| Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields | ||
| from it that are not in the corresponding PAD_CFG_*() macro: | ||
|
|
||
| ```bash | ||
| ./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| /* GPIO_39 - LPSS_UART0_TXD */ | ||
| /* DW0: 0x44000400, DW1: 0x00003100 */ | ||
| /* DW0: PAD_TRIG(OFF) - IGNORED */ | ||
| /* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, | ||
| TxLASTRxE, DISPUPD), */ | ||
| _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), \ | ||
| PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), | ||
| ``` | ||
| ### FSP-style macro | ||
| The utility allows one to generate macros that include fsp/edk2-platform | ||
| style bitfields: | ||
| ```bash | ||
| ./intelp2m -i -fld fsp -p lbg -file ../crb-inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, | ||
| GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, | ||
| GpioPadConfigLock }, /* GPIO */ | ||
| ``` | ||
| ```bash | ||
| ./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log | ||
| ``` | ||
|
|
||
| ```c | ||
| /* GPP_A12 - GPIO */ | ||
| /* DW0: 0x80880102, DW1: 0x00000000 */ | ||
| /* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */ | ||
| { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut, | ||
| GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone, | ||
| GpioPadConfigLock }, | ||
| ``` | ||
| ### Supported Chipsets | ||
| Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,30 @@ | ||
| CONFIG_LOCALVERSION="v4.17.0.1" | ||
| CONFIG_VENDOR_PCENGINES=y | ||
| CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" | ||
| CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 | ||
| CONFIG_BOARD_PCENGINES_APU7=y | ||
| CONFIG_BOTTOMIO_POSITION=0xD0000000 | ||
| CONFIG_UART_PCI_ADDR=0x0 | ||
| CONFIG_HUDSON_SATA_MODE=2 | ||
| CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 | ||
| CONFIG_NO_GFX_INIT=y | ||
| CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 | ||
| CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 | ||
| CONFIG_TPM2=y | ||
| CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y | ||
| CONFIG_CONSOLE_USE_ANSI_ESCAPES=n | ||
| CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n | ||
| CONFIG_POST_IO_PORT=0x80 | ||
| CONFIG_SEABIOS_REVISION=y | ||
| CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" | ||
| CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y | ||
| CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" | ||
| CONFIG_SEABIOS_DEBUG_LEVEL=0 | ||
| CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 | ||
| CONFIG_SEABIOS_NO_OPROMS=y | ||
| CONFIG_MEMTEST_SECONDARY_PAYLOAD=y | ||
| CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y | ||
| CONFIG_MEMTEST_REVISION=y | ||
| CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2" | ||
| CONFIG_SORTBOOTORDER_REVISION=y | ||
| CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.24" |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,9 +1,22 @@ | ||
| config PAYLOAD_GRUB2 | ||
| bool "GRUB2" | ||
| depends on ARCH_X86 || ARCH_ARM | ||
| select PAYLOAD_BUILD_GRUB2 | ||
| help | ||
| Select this option if you want to build a coreboot image | ||
| with a GRUB2 payload. If you don't know what this is | ||
| about, just leave it enabled. | ||
|
|
||
| See https://coreboot.org/Payloads for more information. | ||
|
|
||
| config PAYLOAD_SEAGRUB | ||
| bool "GRUB2 atop SeaBIOS" | ||
| depends on ARCH_X86 | ||
| select PAYLOAD_BUILD_SEABIOS | ||
| select GRUB2_SECONDARY_PAYLOAD | ||
| help | ||
| Select this option if you want to build a coreboot image | ||
| with a GRUB2 payload running atop SeaBIOS to improve its | ||
| hardware compatibility. | ||
|
|
||
| See https://coreboot.org/Payloads for more information. |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1 @@ | ||
| /rom@img/grub2 |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| if COREDOOM_SECONDARY_PAYLOAD | ||
|
|
||
| config COREDOOM_WAD_FILE | ||
| string "DOOM WAD file" | ||
| depends on COREDOOM_SECONDARY_PAYLOAD | ||
| default "doom.wad" | ||
| help | ||
| Add a WAD file to be loaded by coreDOOM. | ||
|
|
||
| A WAD file contains all the game data for the Doom-engine, and | ||
| is required to play the game. | ||
|
|
||
| A list of the WAD files included in the official games can be | ||
| found here: https://doomwiki.org/wiki/IWAD | ||
| These WADs can be extracted from copies of the game that you | ||
| own, and the shareware WADs may be freely downloaded from the | ||
| internet. | ||
|
|
||
| For a completely free (as in freedom) experience, the Freedoom | ||
| project (https://freedoom.github.io) provides original game | ||
| content under the BSD license. Other WADs not mentioned here are | ||
| also available and may be found from various sources such as | ||
| the internet and copies of other games using the Doom engine. | ||
|
|
||
| endif |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| ## SPDX-License-Identifier: GPL-2.0-only | ||
| project_git_repo=https://github.com/nic3-14159/coreDOOM.git | ||
| project_dir=coredoom | ||
|
|
||
| unexport KCONFIG_AUTOHEADER | ||
| unexport KCONFIG_AUTOCONFIG | ||
| unexport KCONFIG_DEPENDENCIES | ||
| unexport KCONFIG_SPLITCONFIG | ||
| unexport KCONFIG_TRISTATE | ||
| unexport KCONFIG_NEGATIVES | ||
|
|
||
| all: coredoom | ||
|
|
||
| checkout: | ||
| test -d coredoom || \ | ||
| git clone $(project_git_repo) $(project_dir) | ||
| cd $(project_dir) && \ | ||
| git checkout libpayload_port | ||
|
|
||
| coredoom: libpayload | ||
| $(MAKE) -C $(project_dir)/doomgeneric | ||
|
|
||
| libpayload: checkout | ||
| cp libpayload-config ../../libpayload/.config && \ | ||
| cd ../../libpayload && $(MAKE) olddefconfig && $(MAKE) && \ | ||
| $(MAKE) DESTDIR=../external/coreDOOM/coredoom/doomgeneric install | ||
|
|
||
| clean: | ||
| test -d coredoom && $(MAKE) -C coredoom/doomgeneric clean || exit 0 | ||
|
|
||
| distclean: | ||
| rm -rf coredoom | ||
|
|
||
| .PHONY: checkout coredoom clean distclean |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,13 @@ | ||
| # CONFIG_LP_MULTIBOOT is not set | ||
| CONFIG_LP_HEAP_SIZE=67108864 | ||
| CONFIG_LP_STACK_SIZE=16384 | ||
| CONFIG_LP_BASE_ADDRESS=0x00100000 | ||
| # CONFIG_LP_CURSES is not set | ||
| CONFIG_LP_SERIAL_IOBASE=0x3f8 | ||
| CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y | ||
| # CONFIG_LP_PCI is not set | ||
| # CONFIG_LP_NVRAM is not set | ||
| CONFIG_LP_TIMER_GENERIC_REG=0x0 | ||
| CONFIG_LP_TIMER_GENERIC_HIGH_REG=0x0 | ||
| # CONFIG_LP_STORAGE is not set | ||
| # CONFIG_LP_USB_MSC is not set |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,67 @@ | ||
| /* | ||
| * | ||
| * Copyright (C) 2008 Advanced Micro Devices, Inc. | ||
| * Copyright (C) 2008 coresystems GmbH | ||
| * | ||
| * Redistribution and use in source and binary forms, with or without | ||
| * modification, are permitted provided that the following conditions | ||
| * are met: | ||
| * 1. Redistributions of source code must retain the above copyright | ||
| * notice, this list of conditions and the following disclaimer. | ||
| * 2. Redistributions in binary form must reproduce the above copyright | ||
| * notice, this list of conditions and the following disclaimer in the | ||
| * documentation and/or other materials provided with the distribution. | ||
| * 3. The name of the author may not be used to endorse or promote products | ||
| * derived from this software without specific prior written permission. | ||
| * | ||
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | ||
| * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
| * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | ||
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
| * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
| * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
| * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
| * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
| * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
| * SUCH DAMAGE. | ||
| */ | ||
|
|
||
| #include <libpayload.h> | ||
| #include <pci.h> | ||
|
|
||
| u8 pci_read_config8(pcidev_t dev, u16 reg) | ||
| { | ||
| outl(dev | (reg & ~3), 0xCF8); | ||
| return inb(0xCFC + (reg & 3)); | ||
| } | ||
|
|
||
| u16 pci_read_config16(pcidev_t dev, u16 reg) | ||
| { | ||
| outl(dev | (reg & ~3), 0xCF8); | ||
| return inw(0xCFC + (reg & 3)); | ||
| } | ||
|
|
||
| u32 pci_read_config32(pcidev_t dev, u16 reg) | ||
| { | ||
| outl(dev | (reg & ~3), 0xCF8); | ||
| return inl(0xCFC + (reg & 3)); | ||
| } | ||
|
|
||
| void pci_write_config8(pcidev_t dev, u16 reg, u8 val) | ||
| { | ||
| outl(dev | (reg & ~3), 0xCF8); | ||
| outb(val, 0xCFC + (reg & 3)); | ||
| } | ||
|
|
||
| void pci_write_config16(pcidev_t dev, u16 reg, u16 val) | ||
| { | ||
| outl(dev | (reg & ~3), 0xCF8); | ||
| outw(val, 0xCFC + (reg & 3)); | ||
| } | ||
|
|
||
| void pci_write_config32(pcidev_t dev, u16 reg, u32 val) | ||
| { | ||
| outl(dev | (reg & ~3), 0xCF8); | ||
| outl(val, 0xCFC + (reg & 3)); | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,46 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
|
||
| #include <libpayload.h> | ||
| #include <pci.h> | ||
|
|
||
| u8 pci_read_config8(pcidev_t dev, u16 reg) | ||
| { | ||
| uintptr_t cfg_base = pci_map_bus(dev); | ||
|
|
||
| return read8((void *)(cfg_base | reg)); | ||
| } | ||
|
|
||
| u16 pci_read_config16(pcidev_t dev, u16 reg) | ||
| { | ||
| uintptr_t cfg_base = pci_map_bus(dev); | ||
|
|
||
| return read16((void *)(cfg_base | (reg & ~1))); | ||
| } | ||
|
|
||
| u32 pci_read_config32(pcidev_t dev, u16 reg) | ||
| { | ||
| uintptr_t cfg_base = pci_map_bus(dev); | ||
|
|
||
| return read32((void *)(cfg_base | (reg & ~3))); | ||
| } | ||
|
|
||
| void pci_write_config8(pcidev_t dev, u16 reg, u8 val) | ||
| { | ||
| uintptr_t cfg_base = pci_map_bus(dev); | ||
|
|
||
| write8((void *)(cfg_base | reg), val); | ||
| } | ||
|
|
||
| void pci_write_config16(pcidev_t dev, u16 reg, u16 val) | ||
| { | ||
| uintptr_t cfg_base = pci_map_bus(dev); | ||
|
|
||
| write16((void *)(cfg_base | (reg & ~1)), val); | ||
| } | ||
|
|
||
| void pci_write_config32(pcidev_t dev, u16 reg, u32 val) | ||
| { | ||
| uintptr_t cfg_base = pci_map_bus(dev); | ||
|
|
||
| write32((void *)(cfg_base | (reg & ~3)), val); | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
|
||
| #include <libpayload.h> | ||
| #include <pci.h> | ||
|
|
||
| #define PCIE_CFGNUM_REG 0x140 | ||
| #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) | ||
| #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) | ||
| #define PCIE_CFG_OFFSET_ADDR 0x1000 | ||
| #define PCIE_CFG_HEADER(bus, devfn) \ | ||
| (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) | ||
|
|
||
| uintptr_t pci_map_bus(pcidev_t dev) | ||
| { | ||
| u32 devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev); | ||
| u32 val = PCIE_CFG_HEADER(PCI_BUS(dev), devfn); | ||
| write32((void *)(lib_sysinfo.pcie_ctrl_base + PCIE_CFGNUM_REG), val); | ||
|
|
||
| return lib_sysinfo.pcie_ctrl_base + PCIE_CFG_OFFSET_ADDR; | ||
| } |
