423 changes: 423 additions & 0 deletions configs/pcengines_apu5.config
View file

Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions src/Kconfig
View file
Expand Up @@ -661,7 +661,7 @@ config FILO_MASTER
bool "HEAD"
help
Newest FILO version

endchoice

config ELTAN_FILO_TAG
Expand All @@ -671,7 +671,7 @@ config ELTAN_FILO_TAG
string "FILO TAG"
default "c315cb219587cde2143c3c6e7471b1214a532ed6"
help
Specify the FILO tag to check out
Specify the FILO tag to check out

config MENULST_FILE
depends on PAYLOAD_FILO
Expand Down Expand Up @@ -752,10 +752,10 @@ config LINUX_INITRD

config SORTBOOTORDER
bool "sortbootorder"
depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3
depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5
default y
help
APU2/3 setup utility
APU series setup utility

endmenu

Expand Down Expand Up @@ -1159,13 +1159,13 @@ config REG_SCRIPT
config MAX_REBOOT_CNT
int
default 3

#
# used but not defined
#
config VBOOT_VERIFY_FIRMWARE
bool
bool

config CHROMEOS
bool
bool

5 changes: 5 additions & 0 deletions src/mainboard/pcengines/Kconfig
View file
Expand Up @@ -10,12 +10,17 @@ config BOARD_PCENGINES_APU2
config BOARD_PCENGINES_APU3
bool "APU3"

config BOARD_PCENGINES_APU5
bool "APU5"

endchoice

source "src/mainboard/pcengines/apu2/Kconfig"

source "src/mainboard/pcengines/apu3/Kconfig"

source "src/mainboard/pcengines/apu5/Kconfig"

config MAINBOARD_VENDOR
string
default "PC Engines"
Expand Down
168 changes: 168 additions & 0 deletions src/mainboard/pcengines/apu5/BiosCallOuts.c
View file
@@ -0,0 +1,168 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/pi/BiosCallOuts.h>
#include "Ids.h"
//#include "OptionsIds.h"
#include "heapManager.h"
#include "FchPlatform.h"
#include "cbfs.h"
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#include "imc.h"
#endif
#include "hudson.h"
#include <stdlib.h>
#include <fchgpio.h>
#include "apu5.h"
#include <spd_cache.h> // for the apu2_ReadSpd_from_cbfs function
#include "bios_knobs.h"

static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);

const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
{AGESA_READ_SPD, apu2_ReadSpd_from_cbfs },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);

//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }


/*
* Hardware Monitor Fan Control
* Hardware limitation:
* HWM will fail to read the input temperature via I2C if other
* software switches the I2C address. AMD recommends using IMC
* to control fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = FALSE;
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
}

/**
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
* such Azalia, SATA, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "\n%s in INIT RESET\n", __func__ );
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;


} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

/* Azalia Controller OEM Codec Table Pointer */
/* Azalia Controller Front Panel OEM Table Pointer */

// No audio support in this system
FchParams->Azalia.AzaliaEnable = AzDisable;

/* Fan Control */
oem_fan_control(FchParams);

/* XHCI configuration */
FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;

/* EHCI configuration */
FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->Usb.Ehci1Enable = check_ehci0();
FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.

/* sata configuration */
FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
FchParams->Sata.SataDevSlpPort1 = 0;

FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
case SataRaid:
case SataAhci:
case SataAhci7804:
case SataLegacyIde:
FchParams->Sata.SataIdeMode = FALSE;
break;
case SataIde2Ahci:
case SataIde2Ahci7804:
default: /* SataNativeIde */
FchParams->Sata.SataIdeMode = TRUE;
break;
}
}
printk(BIOS_DEBUG, "Done\n");

return AGESA_SUCCESS;
}


AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
int index = 0;

if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
if (info->SocketId != 0)
return AGESA_UNSUPPORTED;
if (info->DimmId != 0)
return AGESA_UNSUPPORTED;

/* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/

if ( ReadFchGpio(APU5_SPD_STRAP0_GPIO) ) index |= BIT0;
if ( ReadFchGpio(APU5_SPD_STRAP1_GPIO) ) index |= BIT1;

printk(BIOS_INFO, "Reading SPD index %d\n", index);

if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
die("No SPD data\n");

Status = AGESA_SUCCESS;
#endif
return Status;
}
264 changes: 264 additions & 0 deletions src/mainboard/pcengines/apu5/HYNIX-2G-1333.spd.hex
View file
@@ -0,0 +1,264 @@
# PCEngines 2Gb 1333

# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 128
01

# 1 SPD Revision
# 0x13 = Revision 1.3
13

# 2 Key Byte / DRAM Device Type
# bits[7:0]: 0x0b = DDR3 SDRAM
0B

# 3 Key Byte / Module Type
# bits[3:0]: 3 = SO-DIMM
# bits[3:0]: 8 = 72b-SO-DIMM
# bits[7:4]: reserved
03

# 4 SDRAM CHIP Density and Banks
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
03

# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
# bits[5:3]: 4 = 16 Row Address Bits
# bits[5:3]: 3 = 15 Row Address Bits
# bits[5:3]: 2 = 14 Row Address Bits
# bits[7:6]: reserved
19

# 6 Module Nominal Voltage, VDD
# bit0 : 0 = 1.5 V operable
# bit1 : 0 = NOT 1.35 V operable
# bit2 : 0 = NOT 1.25 V operable
# bits[7:3]: reserved
00

# 7 Module Organization
# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
01

# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
# bits[4:3]: 0 = 0 bits (no bus width extension)
# bits[4:3]: 1 = 8 bits (for ECC)
# bits[7:5]: reserved
03

# 9 Fine Timebase (FTB) Dividend / Divisor
# bits[3:0]: 0x02 divisor
# bits[7:4]: 0x05 dividend
# 5 / 2 = 2.5ps
52

# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
# 1 / 8 = .125 ns
01 08

# 12 SDRAM Minimum Cycle Time (tCKmin)
# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
0C

# 13 Reserved
00

# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
# Cas Latencies of 11 - 5 are supported
7E 00

# 16 Minimum CAS Latency Time (tAAmin)
# 0x6C = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 17 Minimum Write Recovery Time (tWRmin)
# 0x78 = tWR of 15ns - All DDR3 speed grades
78

# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
# 0x6E = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
# 0x30 = 6.0ns
# 0x38 = 7.0ns
# 0x3C = 7.5ns
30

# 20 Minimum Row Precharge Delay Time (tRPmin)
# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69

# 21 Upper Nibbles for tRAS and tRC
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
11

# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
# 0x120 = 36ns - DDR3-1333 (see byte 21)
# 0x120 = 36ns - DDR3
20

# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
# 0x289 = 49.125ns - DDR3-1333
89

# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
# 0x820 = 260ns - for 4 Gigabit chips
00 05

# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
3C

# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
3C

# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
00 F0

# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
# bit7 : 1 = DLL Off mode supported
83

# 31 SDRAM Thermal and Refresh Options
# bit0 : 1 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
01

# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
00

# 33 SDRAM Device Type
# bits[1:0]: 0 = Signal Loading not specified
# bits[3:2]: reserved
# bits[6:4]: 0 = Die count not specified
# bit7 : 0 = Standard Monolithic DRAM Device
00

# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
00

# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
00

# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
00

# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
00

# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
00

# 39 40 (reserved)
00 00

# 41 tMAW, MAC
# 8K*tREFI / 200k
86

# 42 - 47 (reserved)
00 00 00 00 00 00

# 48 - 55 (reserved)
00 00 00 00 00 00 00 00

# 56 - 59 (reserved)
00 00 00 00

# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
00

# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
00

# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
# revision B4
61

# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
# bits[7:1]: reserved
00

# 64 - 71 (reserved)
00 00 00 00 00 00 00 00

# 72 - 79 (reserved)
00 00 00 00 00 00 00 00

# 80 - 87 (reserved)
00 00 00 00 00 00 00 00

# 88 - 95 (reserved)
00 00 00 00 00 00 00 00

# 96 - 103 (reserved)
00 00 00 00 00 00 00 00

# 104 - 111 (reserved)
00 00 00 00 00 00 00 00

# 112 - 116 (reserved)
00 00 00 00 00

# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
# 0x0001 = AMD
00 01

# 119 Module ID: Module Manufacturing Location - OEM specified
00

# 120 Module ID: Module Manufacture Year in BCD
# 0x15 = 2015
15

# 121 Module ID: Module Manufacture week
# 0x44 = 44th week
44

# 122 - 125: Module Serial Number
00 00 00 00

# 126 - 127: Cyclical Redundancy Code
b6 73

261 changes: 261 additions & 0 deletions src/mainboard/pcengines/apu5/HYNIX-4G-1333-ECC.spd.hex
View file
@@ -0,0 +1,261 @@
# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix

# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 128
01

# 1 SPD Revision -
# 0x13 = Revision 1.3
13
# 2 Key Byte / DRAM Device Type
# bits[7:0]: 0x0b = DDR3 SDRAM
0B

# 3 Key Byte / Module Type
# bits[3:0]: 3 = SO-DIMM
# bits[3:0]: 8 = 72b-SO-DIMM
# bits[7:4]: reserved
08

# 4 SDRAM CHIP Density and Banks
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
04

# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
# bits[5:3]: 4 = 16 Row Address Bits
# bits[5:3]: 3 = 15 Row Address Bits
# bits[5:3]: 2 = 14 Row Address Bits
# bits[7:6]: reserved
21

# 6 Module Nominal Voltage, VDD
# bit0 : 0 = 1.5 V operable
# bit1 : 0 = NOT 1.35 V operable
# bit2 : 0 = NOT 1.25 V operable
# bits[7:3]: reserved
00

# 7 Module Organization
# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
01

# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
# bits[4:3]: 0 = 0 bits (no bus width extension)
# bits[4:3]: 1 = 8 bits (for ECC)
# bits[7:5]: reserved
0B

# 9 Fine Timebase (FTB) Dividend / Divisor
# bits[3:0]: 0x02 divisor
# bits[7:4]: 0x05 dividend
# 5 / 2 = 2.5 ps
52

# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
# 1 / 8 = .125 ns
01 08

# 12 SDRAM Minimum Cycle Time (tCKmin)
# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
0C

# 13 Reserved
00

# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
# Cas Latencies of 11 - 5 are supported
7E 00

# 16 Minimum CAS Latency Time (tAAmin)
# 0x6C = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 17 Minimum Write Recovery Time (tWRmin)
# 0x78 = tWR of 15ns - All DDR3 speed grades
78

# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
# 0x6E = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
# 0x30 = 6ns
# 0x38 = 7.0ns
# 0x3C = 7.5ns
30

# 20 Minimum Row Precharge Delay Time (tRPmin)
# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69

# 21 Upper Nibbles for tRAS and tRC
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
11

# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
# 0x120 = 36ns - DDR3-1333 (see byte 21)
# 0x120 = 36ns - DDR3
20

# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
# 0x28C = 49.5ns - DDR3-1333
# 0x289 = 49.125ns - DDR3-1333
89

# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
# 0x820 = 260ns - for 4 Gigabit chips
20 08

# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
3C

# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
3C

# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
00 F0

# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
# bit7 : 1 = DLL Off mode supported
83

# 31 SDRAM Thermal and Refresh Options
# bit0 : 1 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
01

# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
00

# 33 SDRAM Device Type
# bits[1:0]: 0 = Signal Loading not specified
# bits[3:2]: reserved
# bits[6:4]: 0 = Die count not specified
# bit7 : 0 = Standard Monolithic DRAM Device
00

# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
00
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
00
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
00
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
00
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
00

# 39 40 (reserved)
00 00

# 41 tMAW, MAC
# 8K*tREFI / 200k
86

# 42 - 47 (reserved)
00 00 00 00 00 00

# 48 - 55 (reserved)
00 00 00 00 00 00 00 00

# 56 - 59 (reserved)
00 00 00 00

# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
00

# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
00

# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
# revision B4
61

# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
# bits[7:1]: reserved
00

# 64 - 71 (reserved)
00 00 00 00 00 00 00 00

# 72 - 79 (reserved)
00 00 00 00 00 00 00 00

# 80 - 87 (reserved)
00 00 00 00 00 00 00 00

# 88 - 95 (reserved)
00 00 00 00 00 00 00 00

# 96 - 103 (reserved)
00 00 00 00 00 00 00 00

# 104 - 111 (reserved)
00 00 00 00 00 00 00 00

# 112 - 116 (reserved)
00 00 00 00 00

# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
# 0x0001 = AMD
00 01

# 119 Module ID: Module Manufacturing Location - oem specified
00

# 120 Module ID: Module Manufacture Year in BCD
# 0x15 = 2015
# 121 Module ID: Module Manufacture week
# 0x44 = 44th week
15 44

# 122 - 125: Module Serial Number
00 00 00 00

# 126 - 127: Cyclical Redundancy Code
67 94




262 changes: 262 additions & 0 deletions src/mainboard/pcengines/apu5/HYNIX-4G-1333-NOECC.spd.hex
View file
@@ -0,0 +1,262 @@
# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix

# SPD contents for APU 4GB DDR3 NO ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 128
01

# 1 SPD Revision -
# 0x13 = Revision 1.3
13

# 2 Key Byte / DRAM Device Type
# bits[7:0]: 0x0b = DDR3 SDRAM
0B

# 3 Key Byte / Module Type
# bits[3:0]: 3 = SO-DIMM
# bits[3:0]: 8 = 72b-SO-DIMM
# bits[7:4]: reserved
03

# 4 SDRAM CHIP Density and Banks
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
04

# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
# bits[5:3]: 4 = 16 Row Address Bits
# bits[5:3]: 3 = 15 Row Address Bits
# bits[5:3]: 2 = 14 Row Address Bits
# bits[7:6]: reserved
21

# 6 Module Nominal Voltage, VDD
# bit0 : 0 = 1.5 V operable
# bit1 : 0 = NOT 1.35 V operable
# bit2 : 0 = NOT 1.25 V operable
# bits[7:3]: reserved
00

# 7 Module Organization
# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
01

# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
# bits[4:3]: 0 = 0 bits (no bus width extension)
# bits[4:3]: 1 = 8 bits (for ECC)
# bits[7:5]: reserved
03

# 9 Fine Timebase (FTB) Dividend / Divisor
# bits[3:0]: 0x02 divisor
# bits[7:4]: 0x05 dividend
# 5 / 2 = 2.5 ps
52

# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
# 1 / 8 = .125 ns
01 08

# 12 SDRAM Minimum Cycle Time (tCKmin)
# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
0C

# 13 Reserved
00

# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
# Cas Latencies of 11 - 5 are supported
7E 00

# 16 Minimum CAS Latency Time (tAAmin)
# 0x6C = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 17 Minimum Write Recovery Time (tWRmin)
# 0x78 = tWR of 15ns - All DDR3 speed grades
78

# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
# 0x6E = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
# 0x30 = 6ns
# 0x38 = 7.0ns
# 0x3C = 7.5ns
30

# 20 Minimum Row Precharge Delay Time (tRPmin)
# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69

# 21 Upper Nibbles for tRAS and tRC
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
11

# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
# 0x120 = 36ns - DDR3-1333 (see byte 21)
# 0x120 = 36ns - DDR3
20

# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
# 0x28C = 49.5ns - DDR3-1333
# 0x289 = 49.125ns - DDR3-1333
89

# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
# 0x820 = 260ns - for 4 Gigabit chips
20 08

# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
3C

# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
3C

# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
00 F0

# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
# bit7 : 1 = DLL Off mode supported
83

# 31 SDRAM Thermal and Refresh Options
# bit0 : 1 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
01

# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
00

# 33 SDRAM Device Type
# bits[1:0]: 0 = Signal Loading not specified
# bits[3:2]: reserved
# bits[6:4]: 0 = Die count not specified
# bit7 : 0 = Standard Monolithic DRAM Device
00

# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
00
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
00
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
00
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
00
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
00

# 39 40 (reserved)
00 00

# 41 tMAW, MAC
# 8K*tREFI / 200k
86

# 42 - 47 (reserved)
00 00 00 00 00 00

# 48 - 55 (reserved)
00 00 00 00 00 00 00 00

# 56 - 59 (reserved)
00 00 00 00

# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
00

# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
00

# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
# revision B4
61

# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
# bits[7:1]: reserved
00

# 64 - 71 (reserved)
00 00 00 00 00 00 00 00

# 72 - 79 (reserved)
00 00 00 00 00 00 00 00

# 80 - 87 (reserved)
00 00 00 00 00 00 00 00

# 88 - 95 (reserved)
00 00 00 00 00 00 00 00

# 96 - 103 (reserved)
00 00 00 00 00 00 00 00

# 104 - 111 (reserved)
00 00 00 00 00 00 00 00

# 112 - 116 (reserved)
00 00 00 00 00

# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
# 0x0001 = AMD
00 01

# 119 Module ID: Module Manufacturing Location - oem specified
00

# 120 Module ID: Module Manufacture Year in BCD
# 0x15 = 2015
# 121 Module ID: Module Manufacture week
# 0x44 = 44th week
15 44

# 122 - 125: Module Serial Number
00 00 00 00

# 126 - 127: Cyclical Redundancy Code
09 ff




141 changes: 141 additions & 0 deletions src/mainboard/pcengines/apu5/Kconfig
View file
@@ -0,0 +1,141 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2016 Eltan B.V.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#

if BOARD_PCENGINES_APU5

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
# select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
# select GFXUMA # disable graphics
select SPD_CACHE
select HUDSON_DISABLE_IMC
# select HAVE_OPTION_TABLE # Removed the CMOS support as the boot
# select USE_OPTION_TABLE # order can be fixed now.
# select HAVE_CMOS_DEFAULT
select USE_CBMEM_FILE_OVERRIDE

config MAINBOARD_DIR
string
default pcengines/apu5

config MAINBOARD_PART_NUMBER
string
default "PC Engines apu5"

config SVI2_SLOW_SPEED
bool "SVI2 slow speed"
default n
help
Used when there are problems switching the VRM speed. By default
speed is 20 Mhz

config SVI_WAIT_COMP_DIS
bool "Disable SVI2 controller waits for command completion"
default y
help
SVI2 controller will not wait for command completion from VRM

config HW_MEM_HOLE_SIZEK
hex
default 0x200000

config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11

config RAMTOP
hex
default 0x1000000

config HEAP_SIZE
hex
default 0xc0000

config ACPI_SSDTX_NUM
int
default 0

config RAMBASE
hex
default 0x200000

#config ONBOARD_VGA_IS_PRIMARY
# bool
# default y

config HUDSON_LEGACY_FREE
bool
default y

config HUDSON_XHCI_ENABLE
bool
default y

config DRIVERS_PS2_KEYBOARD
bool
default n

config AGESA_HEAP_MEMTEST
bool
default y

config VGA_ROM_RUN
bool
default n

config DUMP_GPIO_CONFIGURATION
bool "Dump FCH GPIO configuration in board finalize"
default n

config DUMP_CLOCK_CONFIGURATION
bool "Dump FCH MISC configuration in board finalize"
default n

config DUMP_LINK_CONFIGURATION
bool "Dump PCIe LINK configuration in board finalize"
default n

config INCLUDE_SGABIOS
bool "Include the SGABIOS for serial console"
default y

config FORCE_CONSOLE
bool "always enable serial console"
default n
help
by default serial console is only enabled when pressing S1

endif # BOARD_PCENGINES_APU5
102 changes: 102 additions & 0 deletions src/mainboard/pcengines/apu5/Makefile.inc
View file
@@ -0,0 +1,102 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2016 Eltan B.V.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#

romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
romstage-y += bios_knobs.c

ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ramstage-y += bios_knobs.c

# WIV20150202 add ramtest
cbfs-files-y += img/memtest
img/memtest-file := payloads/eltan/memtest86+/memtest501.serial.com1.nospd.eltan-elf
img/memtest-position := 0xcd900
img/memtest-type := payload
# WIV20150202 add ramtest

cbfs-files-y += bootorder_map
bootorder_map-file := bootorder_map
bootorder_map-type := raw

cbfs-files-y += bootorder_def
bootorder_def-file := bootorder_def
bootorder_def-type := raw

# WIV20150205 add ipxe
#cbfs-files-y += genroms/pxe.rom
#genroms/pxe.rom-file := payloads/eltan/ipxe/10ec8168.rom
#genroms/pxe.rom-type := raw
# WIV20150205 add ipxe

# WIV20150126 add boot order
cbfs-files-y += bootorder
bootorder-file := src/mainboard/$(MAINBOARDDIR)/bootorder
bootorder-type := raw
bootorder-align := 0x1000

cbfs-files-y += etc/boot-menu-message
etc/boot-menu-message-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-message
etc/boot-menu-message-type := raw

cbfs-files-y += etc/boot-menu-key
etc/boot-menu-key-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-key
etc/boot-menu-key-type := raw

cbfs-files-y += etc/boot-menu-wait
etc/boot-menu-wait-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-wait
etc/boot-menu-wait-type := raw
# WIV20150126 end add boot order

# WIV20141001 START ADD SPD FROM FILE
## DIMM SPD for on-board memory
SPD_BIN = $(obj)/spd.bin

# Order of names in SPD_SOURCES is important!
SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC
#SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-NOECC

SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)

# Include spd rom data
$(SPD_BIN): $(SPD_DEPS) src/mainboard/$(MAINBOARDDIR)/Makefile.inc
echo " create SPD $@"
for f in $(SPD_DEPS); \
do for c in $$(cat $$f | grep -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@

cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
# WIV20141001 END ADD SPD FROM FILE

cbfs-files-$(CONFIG_INCLUDE_SGABIOS) += vgaroms/sgabios.bin
vgaroms/sgabios.bin-file := payloads/eltan/sgabios/sgabios.rom
vgaroms/sgabios.bin-type := raw

cbfs-files-$(CONFIG_INCLUDE_SGABIOS) += etc/screen-and-debug
etc/screen-and-debug-file := payloads/eltan/sgabios/screen-and-debug
etc/screen-and-debug-type := raw

72 changes: 72 additions & 0 deletions src/mainboard/pcengines/apu5/OptionsIds.h
View file
@@ -0,0 +1,72 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/**
* @file
*
* IDS Option File
*
* This file is used to switch on/off IDS features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
*/
#ifndef _OPTION_IDS_H_
#define _OPTION_IDS_H_

/**
*
* This file generates the defaults tables for the Integrated Debug Support
* Module. The documented build options are imported from a user controlled
* file for processing. The build options for the Integrated Debug Support
* Module are listed below:
*
* IDSOPT_IDS_ENABLED
* IDSOPT_ERROR_TRAP_ENABLED
* IDSOPT_CONTROL_ENABLED
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/

//#define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_CONTROL_ENABLED TRUE

//#define IDSOPT_TRACING_ENABLED TRUE
//#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
//#define IDS_DEBUG_PRINT_MASK (FCH_TRACE_ALL) // We just want to see the FCH stuff now
//#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_TRACING_CONSOLE_REDIRECT_IO TRUE

//#define IDSOPT_PERF_ANALYSIS TRUE
//#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
126 changes: 126 additions & 0 deletions src/mainboard/pcengines/apu5/PlatformGnbPcie.c
View file
@@ -0,0 +1,126 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#include <northbridge/amd/pi/agesawrapper.h>

#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE

const PCIe_PORT_DESCRIPTOR PortList [] = {
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x01, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x02, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x03, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x04, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x05, 0)
}
};

const PCIe_DDI_DESCRIPTOR DdiList [] = {
/* DP0 to HDMI0/DP */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
},
/* DP1 to FCH */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
},
/* DP2 to HDMI1/DP */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
},
};

const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList
};

/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
}
31 changes: 31 additions & 0 deletions src/mainboard/pcengines/apu5/PlatformGnbPcieComplex.h
View file
@@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H

#include <Porting.h>
#include <AGESA.h>

VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);

#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
84 changes: 84 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/gpe.asl
View file
@@ -0,0 +1,84 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
}

/* Temp warning (TWarn) event */
Method(_L09) {
/* DBGO("\\_GPE\\_L09\n") */
/* Notify (\_TZ.TZ00, 0x80) */
}

/* USB controller PME# */
Method(_L0B) {
/* DBGO("\\_GPE\\_L0B\n") */
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Method(_L10) {
/* DBGO("\\_GPE\\_L10\n") */
}

/* ExtEvent1 SCI event */
Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */
}

/* GPIO0 or GEvent8 event */
Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

// /* Azalia SCI event */
// Method(_L1B) {
// /* DBGO("\\_GPE\\_L1B\n") */
// Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
// Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
// }
} /* End Scope GPE */
1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu5/acpi/ide.asl
View file
@@ -0,0 +1 @@
/* No IDE functionality */
41 changes: 41 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/mainboard.asl
View file
@@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */

Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */

Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */

/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */
Name(PMOD, One) /* Assume APIC */

/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) {
, 11,
USBS, 1,
}
475 changes: 475 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/pci_int.asl
View file

Large diffs are not rendered by default.

217 changes: 217 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/routing.asl
View file
@@ -0,0 +1,217 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "routing.asl"
}
*/

/* Routing is in System Bus scope */
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - F16 Host Controller */

/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 },


/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },

/* FCH devices */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },

#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 0, INTC, 0 },

#else // CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },

Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 1, INTB, 0 },

Package(){0x0016FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 1, INTB, 0 },
#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, INTC, 0 },
Package(){0x0010FFFF, 1, INTB, 0 },

/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },

})

Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - F15 Host Controller */

/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, 0, 44 },
Package(){0x0001FFFF, 1, 0, 45 },

/* Bus 0, Dev 2 - PCIe Bridges */
Package(){0x0002FFFF, 0, 0, 24 },
Package(){0x0002FFFF, 1, 0, 25 },
Package(){0x0002FFFF, 2, 0, 26 },
Package(){0x0002FFFF, 3, 0, 27 },


/* SB devices in APIC mode */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */

Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 0, 0, 18 },

#else //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0012FFFF, 1, 0, 17 },

Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 17 },

Package(){0x0016FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 1, 0, 17 },
#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, 0, 0x12},
Package(){0x0010FFFF, 1, 0, 0x11},

/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, 0, 19 },

})

Name(PS2, Package(){
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})

/* GFX */
Name(PS4, Package(){
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, 0, 24 },
Package(){0x0000FFFF, 1, 0, 25 },
Package(){0x0000FFFF, 2, 0, 26 },
Package(){0x0000FFFF, 3, 0, 27 },
})

/* GPP 0 */
Name(PS5, Package(){
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
Package(){0x0000FFFF, 0, 0, 28 },
Package(){0x0000FFFF, 1, 0, 29 },
Package(){0x0000FFFF, 2, 0, 30 },
Package(){0x0000FFFF, 3, 0, 31 },
})

/* GPP 1 */
Name(PS6, Package(){
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
Package(){0x0000FFFF, 0, 0, 32 },
Package(){0x0000FFFF, 1, 0, 33 },
Package(){0x0000FFFF, 2, 0, 34 },
Package(){0x0000FFFF, 3, 0, 35 },
})

/* GPP 2 */
Name(PS7, Package(){
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
Package(){0x0000FFFF, 0, 0, 36 },
Package(){0x0000FFFF, 1, 0, 37 },
Package(){0x0000FFFF, 2, 0, 38 },
Package(){0x0000FFFF, 3, 0, 39 },
})

/* GPP 3 */
Name(PS8, Package(){
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS8, Package(){
Package(){0x0000FFFF, 0, 0, 40 },
Package(){0x0000FFFF, 1, 0, 41 },
Package(){0x0000FFFF, 2, 0, 42 },
Package(){0x0000FFFF, 3, 0, 43 },
})
1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu5/acpi/sata.asl
View file
@@ -0,0 +1 @@
/* No SATA functionality */
27 changes: 27 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/si.asl
View file
@@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

Scope(\_SI) {
Method(_SST, 1) {
/* DBGO("\\_SI\\_SST\n") */
/* DBGO(" New Indicator state: ") */
/* DBGO(Arg0) */
/* DBGO("\n") */
}
} /* End Scope SI */
97 changes: 97 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/sleep.asl
View file
@@ -0,0 +1,97 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/* Wake status package */
Name(WKST,Package(){Zero, Zero})

/*
* \_PTS - Prepare to Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2, etc
*
*s Exit:
* -none-
*
* The _PTS control method is executed at the beginning of the sleep process
* for S1-S5. The sleeping value is passed to the _PTS control method. This
* control method may be executed a relatively long time before entering the
* sleep state and the OS may abort the operation without notification to
* the ACPI driver. This method cannot modify the configuration or power
* state of any device in the system.
*/

External(\_SB.APTS, MethodObj)
External(\_SB.AWAK, MethodObj)

Method(_PTS, 1) {
/* DBGO("\\_PTS\n") */
/* DBGO("From S0 to S") */
/* DBGO(Arg0) */
/* DBGO("\n") */

/* Clear wake status structure. */
Store(0, Index(WKST,0))
Store(0, Index(WKST,1))
Store(7, UPWS)
\_SB.APTS(Arg0)
} /* End Method(\_PTS) */

/*
* \_BFS OEM Back From Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* -none-
*/
Method(\_BFS, 1) {
/* DBGO("\\_BFS\n") */
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
}

/*
* \_WAK System Wake method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* Return package of 2 DWords
* Dword 1 - Status
* 0x00000000 wake succeeded
* 0x00000001 Wake was signaled but failed due to lack of power
* 0x00000002 Wake was signaled but failed due to thermal condition
* Dword 2 - Power Supply state
* if non-zero the effective S-state the power supply entered
*/
Method(\_WAK, 1) {
/* DBGO("\\_WAK\n") */
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
Store(1,USBS)

\_SB.AWAK(Arg0)

Return(WKST)
} /* End Method(\_WAK) */
31 changes: 31 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/superio.asl
View file
@@ -0,0 +1,31 @@
/* We don't have a real SIO but lets define the serial port here, this is where it belongs */

Device (COM1) {
Name (_HID, EISAID ("PNP0501"))
Name (_UID, 1)
Name (_ADR, 0)

Method (_STA, 0, NotSerialized) {
Return (0x0F)
}

Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
IRQNoFlags () {4}
// IRQNoFlags () {}
})

Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
// IRQNoFlags () {4}
IRQNoFlags () {}
}
EndDependentFn ()
})
}



1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu5/acpi/thermal.asl
View file
@@ -0,0 +1 @@
/* No thermal zone functionality */
41 changes: 41 additions & 0 deletions src/mainboard/pcengines/apu5/acpi/usb_oc.asl
View file
@@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/* simple name description */
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "usb.asl"
}
*/

/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
Name(UOM2, 0)
Name(UOM3, 7)
Name(UOM4, 2)
Name(UOM5, 2)
Name(UOM6, 6)
Name(UOM7, 2)
Name(UOM8, 6)
Name(UOM9, 6)

289 changes: 289 additions & 0 deletions src/mainboard/pcengines/apu5/acpi_tables.c
View file
@@ -0,0 +1,289 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

//#include "agesawrapper.h"
#include <northbridge/amd/pi/agesawrapper.h>

#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam16.h>

//extern const unsigned char AmlCode[];
//
//unsigned long acpi_fill_mcfg(unsigned long current)
//{
// /* Just a dummy */
// return current;
//}

unsigned long acpi_fill_madt(unsigned long current)
{
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);

/* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0);

/* TODO: Remove the hardcode */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
0xFEC20000, 24);

current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */

/* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
/* 1: LINT1 connect to NMI */

return current;
}

#if FALSE
unsigned long acpi_fill_hest(acpi_hest_t *hest)
{
void *addr, *current;

/* Skip the HEST header. */
current = (void *)(hest + 1);

addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
if (addr != NULL)
current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);

addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
if (addr != NULL)
current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);

return (unsigned long)current;
}

unsigned long acpi_fill_slit(unsigned long current)
{
/* Not implemented */
return current;
}

unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}

unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
{
int lens;
msr_t msr;
char pscope[] = "\\_SB.PCI0";

lens = acpigen_write_scope(pscope);
msr = rdmsr(TOP_MEM);
lens += acpigen_write_name_dword("TOM1", msr.lo);
msr = rdmsr(TOP_MEM2);
/*
* Since XP only implements parts of ACPI 2.0, we can't use a qword
* here.
* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
* slide 22ff.
* Shift value right by 20 bit to make it fit into 32bit,
* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
*/
lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
acpigen_patch_len(lens - 1);
return (unsigned long) (acpigen_get_current());
}

unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
acpi_header_t *alib;
acpi_header_t *ivrs;
acpi_hest_t *hest;

/* Align ACPI tables to 16 bytes */
start = ALIGN(start, 16);
current = start;

printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);

/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);

/* clear all table memory */
memset((void *)start, 0, current - start);

acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);

/* DSDT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; /* it will used by fadt */
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);

/* FACS */ /* it needs 64 byte alignment */
current = ALIGN(current, 64);
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; /* it will be used by fadt */
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);

/* FADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);

acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);

/*
* We explicitly add these tables later on:
*/
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);

/* If we want to use HPET Timers Linux wants an MADT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);

/* HEST */
current = ALIGN(current, 8);
hest = (acpi_hest_t *)current;
acpi_write_hest((void *)current);
acpi_add_table(rsdp, (void *)current);
current += ((acpi_header_t *)current)->length;

current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
if (ivrs != NULL) {
memcpy((void *)current, ivrs, ivrs->length);
ivrs = (acpi_header_t *) current;
current += ivrs->length;
acpi_add_table(rsdp, ivrs);
} else {
printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
}

/* SRAT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current;
current += srat->header.length;
acpi_add_table(rsdp, srat);
} else {
printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
}

/* SLIT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current;
current += slit->header.length;
acpi_add_table(rsdp, slit);
} else {
printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
}

/* ALIB */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
if (alib != NULL) {
memcpy((void *)current, alib, alib->length);
alib = (acpi_header_t *) current;
current += alib->length;
acpi_add_table(rsdp, (void *)alib);
}
else {
printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
}

/* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
/* SSDT */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current;
current += ssdt->length;
}
else {
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
}
acpi_add_table(rsdp,ssdt);

printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);

printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;

acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
current += ssdt->length;
acpi_add_table(rsdp, ssdt);

printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
#endif //FALSE
760 changes: 760 additions & 0 deletions src/mainboard/pcengines/apu5/agesawrapper.c
View file

Large diffs are not rendered by default.

62 changes: 62 additions & 0 deletions src/mainboard/pcengines/apu5/agesawrapper.h
View file
@@ -0,0 +1,62 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#ifndef _AGESAWRAPPER_H_
#define _AGESAWRAPPER_H_

#include <stdint.h>
#include "Porting.h"
#include "AGESA.h"
#include "PlatformMemoryConfiguration.h"

/* Define AMD APU and SoC SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS

enum {
PICK_DMI, /* DMI Interface */
PICK_PSTATE, /* Acpi Pstate SSDT Table */
PICK_SRAT, /* SRAT Table */
PICK_SLIT, /* SLIT Table */
PICK_WHEA_MCE, /* WHEA MCE table */
PICK_WHEA_CMC, /* WHEA CMV table */
PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */
};

AGESA_STATUS agesawrapper_amdinitreset(void);
AGESA_STATUS agesawrapper_amdinitearly(void);
AGESA_STATUS agesawrapper_amdinitenv(void);
AGESA_STATUS agesawrapper_amdinitlate(void);
AGESA_STATUS agesawrapper_amdinitpost(void);
AGESA_STATUS agesawrapper_amdinitmid(void);
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus);
AGESA_STATUS agesawrapper_amdinitmmio(void);
AGESA_STATUS agesawrapper_amdinitcpuio(void);
void *agesawrapper_getlateinitptr(int pick);
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, void *ConfigPtr);
AGESA_STATUS agesawrapper_amdS3Save(void);
AGESA_STATUS agesawrapper_amdinitresume(void);
AGESA_STATUS agesawrapper_amds3laterestore(void);

AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
AGESA_STATUS agesawrapper_fchs3laterestore(void);

#endif /* _AGESAWRAPPER_H_ */
60 changes: 60 additions & 0 deletions src/mainboard/pcengines/apu5/apu5.h
View file
@@ -0,0 +1,60 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#include <agesawrapper.h>

#define APU5_SPD_STRAP0_GPIO 0x40 // GPIO49
#define APU5_SPD_STRAP0_FUNC Function2
#define APU5_SPD_STRAP1_GPIO 0x41 // GPIO50
#define APU5_SPD_STRAP1_FUNC Function2
#define APU5_SIM1RST_L_GPIO 0x42 // GPIO51
#define APU5_SIM1RST_L_FUNC Function2
#define APU5_SIM2RST_L_GPIO 0x43 // DEVSLP[0]/GPIO55
#define APU5_SIM2RST_L_FUNC Function3
#define APU5_LED1_L_GPIO 0x44 // GPIO57
#define APU5_LED1_L_FUNC Function1
#define APU5_LED2_L_GPIO 0x45 // GPIO58
#define APU5_LED2_L_FUNC Function1
#define APU5_LED3_L_GPIO 0x46 // DEVSLP[1]/GPIO59
#define APU5_LED3_L_FUNC Function3
#define APU5_SIM3RST_L_GPIO 0x47 // GPIO64
#define APU5_SIM3RST_L_FUNC Function2
#define APU5_SIMSWAP1_GPIO 0x48 // GPIO68
#define APU5_SIMSWAP1_FUNC Function0
#define APU5_SKR_GPIO 0x5B // SPKR/GPIO66
#define APU5_SKR_FUNC Function0
#define APU5_PROCHOT_GPIO 0x4D // GPIO71
#define APU5_PROCHOT_FUNC Function0
#define APU5_SIMSWAP2_GPIO 0x59 // GENINT1_L/GPIO32
#define APU5_SIMSWAP2_FUNC Function0
#define APU5_SIMSWAP3_GPIO 0x5A // GENINT2_L/GPIO33
#define APU5_SIMSWAP3_FUNC Function0












194 changes: 194 additions & 0 deletions src/mainboard/pcengines/apu5/bios_knobs.c
View file
@@ -0,0 +1,194 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 3mdeb
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <console/console.h>
#include <cbfs_core.h>
#include "bios_knobs.h"

#define BOOTORDER_FILE "bootorder"

static char * findstr(const char *s, const char *pattern)
{
char *result = (char *) s;
char *lpattern = (char *) pattern;

while (*result && *pattern ) {
if ( *lpattern == 0) // the pattern matches return the pointer
return result;
if ( *result == 0) // We're at the end of the file content but don't have a patter match yet
return NULL;
if (*result == *lpattern ) {
// The string matches, simply advance
result++;
lpattern++;
} else {
// The string doesn't match restart the pattern
result++;
lpattern = (char *) pattern;
}
}

return NULL;
}

static u8 check_knob_value(const char *s)
{
const char *boot_file = NULL;
size_t boot_file_len = 0;
char * token = NULL;

boot_file = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, BOOTORDER_FILE, CBFS_TYPE_RAW, &boot_file_len);
if (boot_file == NULL)
printk(BIOS_EMERG, "file [%s] not found in CBFS\n", BOOTORDER_FILE);
if (boot_file_len < 4096)
printk(BIOS_EMERG, "Missing bootorder data.\n");
if (boot_file == NULL || boot_file_len < 4096)
return -1;

token = findstr( boot_file, s );

if (token) {
if (*token == '0') return 0;
if (*token == '1') return 1;
}

return -1;
}

#if CONFIG_FORCE_CONSOLE
bool check_console(void)
{
return true;
}
#else //CONFIG_FORCE_CONSOLE
bool check_console(void)
{
u8 scon;

//
// Find the serial console item
//
scon = check_knob_value("scon");

switch (scon) {
case 0:
return false;
break;
case 1:
return true;
break;
default:
printk(BIOS_EMERG, "Missing or invalid scon knob, enable console.\n");
break;
}

return true;
}
#endif //CONFIG_FORCE_CONSOLE

static bool check_uart(char uart_letter)
{
u8 uarten;

switch (uart_letter) {
case 'c':
uarten = check_knob_value("uartc");
break;
case 'd':
uarten = check_knob_value("uartd");
break;
default:
uarten = -1;
break;
}

switch (uarten) {
case 0:
return false;
break;
case 1:
return true;
break;
default:
printk(BIOS_EMERG, "Missing or invalid uart knob, disable port.\n");
break;
}

return false;
}

inline bool check_uartc(void)
{
return check_uart('c');
}

inline bool check_uartd(void)
{
return check_uart('d');
}

bool check_ehci0(void)
{
u8 ehci0;

//
// Find the serial console item
//
ehci0 = check_knob_value("ehcien");

switch (ehci0) {
case 0:
return false;
break;
case 1:
return true;
break;
default:
printk(BIOS_EMERG, "Missing or invalid ehci0 knob, enable ehci0.\n");
break;
}

return true;
}

bool check_mpcie2_clk(void)
{
u8 mpcie2_clk;

//
// Find the serial console item
//
mpcie2_clk = check_knob_value("mpcie2_clk");

switch (mpcie2_clk) {
case 0:
return false;
break;
case 1:
return true;
break;
default:
printk(BIOS_EMERG, "Missing or invalid mpcie2_clk knob, forcing CLK of mPCIe2 slot is not enabled .\n");
break;
}

return false;
}
38 changes: 38 additions & 0 deletions src/mainboard/pcengines/apu5/bios_knobs.h
View file
@@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 3mdeb
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#ifndef _BIOS_KNOBS_H
#define _BIOS_KNOBS_H

bool check_console(void);
bool check_uartc(void);
bool check_uartd(void);
bool check_ehci0(void);
bool check_mpcie2_clk(void);

#endif








6 changes: 6 additions & 0 deletions src/mainboard/pcengines/apu5/board_info.txt
View file
@@ -0,0 +1,6 @@
Board name: PC Engines APU5
Board URL:
Category: customer
ROM protocol: SPI
ROM socketed: n
Flashrom support: n
Binary file added src/mainboard/pcengines/apu5/boot-menu-key
View file
Binary file not shown.
1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu5/boot-menu-message
View file
@@ -0,0 +1 @@
Press F10 key now for boot menu, N for PXE boot
Binary file added src/mainboard/pcengines/apu5/boot-menu-wait
View file
Binary file not shown.
Binary file added src/mainboard/pcengines/apu5/bootorder
View file
Binary file not shown.
10 changes: 10 additions & 0 deletions src/mainboard/pcengines/apu5/bootorder_def
View file
@@ -0,0 +1,10 @@
/pci@i0cf8/usb@10/usb-*@1
/pci@i0cf8/usb@10/usb-*@2
/pci@i0cf8/usb@10/usb-*@3
/pci@i0cf8/usb@10/usb-*@4
/pci@i0cf8/*@14,7
/pci@i0cf8/*@11/drive@0/disk@0
/pci@i0cf8/*@11/drive@1/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
/rom@genroms/pxe.rom
10 changes: 10 additions & 0 deletions src/mainboard/pcengines/apu5/bootorder_map
View file
@@ -0,0 +1,10 @@
a USB 1 / USB 2 SS and HS
a USB 1 / USB 2 SS and HS
a USB 1 / USB 2 SS and HS
a USB 1 / USB 2 SS and HS
b SDCARD
c mSATA
d SATA
e mPCIe1 SATA1 and SATA2
e mPCIe1 SATA1 and SATA2
f iPXE
13 changes: 13 additions & 0 deletions src/mainboard/pcengines/apu5/cmos.default
View file
@@ -0,0 +1,13 @@
boot_option=Fallback
last_boot=Fallback
ECC_memory=Disable
hw_scrubber=Disable
interleave_chip_selects=Disable
max_mem_clock=400Mhz
multi_core=Enable
power_on_after_fail=Disable
slow_cpu=off
nmi=Disable
boot_devices='uda1'
baud_rate=115200
debug_level=Spew
129 changes: 129 additions & 0 deletions src/mainboard/pcengines/apu5/cmos.layout
View file
@@ -0,0 +1,129 @@
#*****************************************************************************
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#*****************************************************************************

entries

#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail

# SHOULD MATCH CONFIG_CMOS_SKIP_PXE_LOC 0x32 and MASK 0x2 :: ELTAN SEABIOS
401 1 e 11 network_boot

412 4 e 6 debug_level

## ETHERBOOT
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
## ETHERBOOT

440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu

#FILO
# coreboot config options: bootloader
448 256 s 0 boot_devices
#FILO

728 256 h 0 user_data

984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved

enumerations

#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%

checksums

checksum 392 983 984
96 changes: 96 additions & 0 deletions src/mainboard/pcengines/apu5/devicetree.cb
View file
@@ -0,0 +1,96 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2013 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
chip northbridge/amd/pi/00730F01/root_complex
device cpu_cluster 0 on
chip cpu/amd/pi/00730F01
device lapic 0 on end
end
end

device domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/pi/00730F01 # CPU side of HT root complex

chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
device pci 2.1 on end # mPCIe slot 2 (on GFX lane)
device pci 2.2 on end # LAN3
device pci 2.3 on end # LAN2
device pci 2.4 on end # LAN1
device pci 2.5 on end # mPCIe slot 1
device pci 8.0 on end # Platform Security Processor
end #chip northbridge/amd/pi/00730F01

chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
device pci 11.0 on end # SATA
device pci 12.0 on end # USB EHCI0 usb[0:3]
device pci 13.0 on end # USB EHCI1 usb[4:7]
device pci 14.0 on end # SM
# disabled device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.10 on
# UART C is conditionally turned on
io 0x60 = 0x3e8
irq 0x70 = 4
end
device pnp 2e.11 on
# UART D is conditionally turned on
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 on end
device pnp 2e.107 on end
device pnp 2e.607 off end
device pnp 2e.e off end
end # SIO NCT5104D
end # LPC 0x439d

device pci 14.7 on end # SD
device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
end #chip southbridge/amd/pi/hudson

device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end

end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
end #domain
end #northbridge/amd/pi/00730F01/root_complex