diff --git a/Documentation/codeflow.svg b/Documentation/codeflow.svg
diff --git a/Documentation/conf.py b/Documentation/conf.py
@@ -1,4 +1,5 @@
 # -*- coding: utf-8 -*-
+import subprocess
 
 # Add any paths that contain templates here, relative to this directory.
 templates_path = ['_templates']
@@ -11,17 +12,17 @@
 
 # General information about the project.
 project = u'coreboot'
-copyright = u'the coreboot project'
+copyright = u'CC-by 4.0 the coreboot project'
 author = u'the coreboot project'
 
 # The version info for the project you're documenting, acts as replacement for
 # |version| and |release|, also used in various other places throughout the
 # built documents.
 #
-# The short X.Y version.
-version = u'4.7'
 # The full version, including alpha/beta/rc tags.
-release = u'4.7' # TODO: use 'git describe'
+release = subprocess.check_output(('git', 'describe'))
+# The short X.Y version.
+version = release.split("-")[0]
 
 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.
@@ -119,7 +120,7 @@
 #
 # latex_appendices = []
 
-# It false, will not define \strong, \code, 	itleref, \crossref ... but only
+# If false, will not define \strong, \code,	itleref, \crossref ... but only
 # \sphinxstrong, ..., \sphinxtitleref, ... To help avoid clash with user added
 # packages.
 #

diff --git a/Documentation/build_system.md → ...mentation/getting_started/build_system.md b/Documentation/build_system.md → ...mentation/getting_started/build_system.md
diff --git a/Documentation/gerrit_guidelines.md → ...tion/getting_started/gerrit_guidelines.md b/Documentation/gerrit_guidelines.md → ...tion/getting_started/gerrit_guidelines.md
diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md
@@ -0,0 +1,8 @@
+# Getting Started
+
+* [Build System](build_system.md)
+* [Submodules](submodules.md)
+* [Kconfig](kconfig.md)
+* [Gerrit Guidelines](gerrit_guidelines.md)
+* [Documentation License](license.md)
+* [Writing Documentation](writing_documentation.md)
diff --git a/Documentation/core/Kconfig.md → Documentation/getting_started/kconfig.md b/Documentation/core/Kconfig.md → Documentation/getting_started/kconfig.md
diff --git a/Documentation/getting_started/license.md b/Documentation/getting_started/license.md
diff --git a/Documentation/submodules.md → Documentation/getting_started/submodules.md b/Documentation/submodules.md → Documentation/getting_started/submodules.md
diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md
@@ -0,0 +1,74 @@
+# coreboot documentation guidelines
+
+> Documentation is like sex: when it is good, it is very, very good;
+> and when it is bad, it is better than nothing.
+
+That said please always try to write documentation! One problem in the
+firmware development is the missing documentation. In this document
+you will get a brief introduction how to write, submit and publish
+documenation to coreboot.
+
+## Preparations
+
+coreboot uses [Sphinx] documentation tool. We prefer the markdown format
+over reStructuredText so only embedded ReST is supported. Checkout the
+[Markdown Guide] for more information.
+
+### Install Sphinx
+
+Please follow this official [guide].
+
+### Optional
+
+Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly!
+
+## Basic and simple rules
+
+The following rules should be followed in order to get it at least reviewed
+on [review.coreboot.org].
+
+Documentation:
+
+1.  Must be written in **markdown** with **embedded reStructuredText**
+    format.
+2.  Must be written in **English**.
+3.  Must be placed into **Documentation/** directory subfolder.
+4.  Should follow the same directory structure as **src/** when practical.
+5.  Must be referenced from within other markdown files
+6.  The commit must follow the [Gerrit Guidelines].
+7.  Must have all **lowercase filenames**.
+8.  Running text should have a visible width of about **72 chars**.
+9.  Should not **duplicate** documentation, but reference it instead.
+10.  Must not include the same picture in multiple markdown files.
+11.  Images should be kept small. They should be under 700px in width, as
+     the current theme doesn't allow bigger images.
+12.  Shouldn't cover implementation details; for details, the code is the
+     reference.
+
+## Markdown and Tables
+
+Under Sphinx markdown tables are not supported. Therefore you can use following
+code block to write tables in reStructuredText and embed them into the markdown:
+
+    ```eval_rst
+    +------------+------------+-----------+
+    | Header 1   | Header 2   | Header 3  |
+    +============+============+===========+
+    | body row 1 | column 2   | column 3  |
+    +------------+------------+-----------+
+    | body row 2 | Cells may span columns.|
+    +------------+------------+-----------+
+    | body row 3 | Cells may  | - Cells   |
+    +------------+ span rows. | - contain |
+    | body row 4 |            | - blocks. |
+    +------------+------------+-----------+
+    ``` #just a code block is enough
+
+[coreboot]: https://coreboot.org
+[Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation
+[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
+[guide]: http://www.sphinx-doc.org/en/stable/install.html
+[Sphinx]: http://www.sphinx-doc.org/en/master/
+[Markdown Guide]: https://www.markdownguide.org/
+[Gerrit Guidelines]: https://doc.coreboot.org/gerrit_guidelines.html
+[review.coreboot.org]: https://review.coreboot.org
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -1,5 +1,4 @@
-Welcome to coreboot's documentation!
-====================================
+# Welcome to the coreboot documentation
 
 This is the developer documentation for [coreboot](https://coreboot.org).
 It is built from Markdown files in the
@@ -8,16 +7,16 @@ directory in the source code.
 
 Contents:
 
-* [Lesson 2: Submitting a patch to coreboot.org](Lesson2.md)
-* [Gerrit Etiquette and Guidelines](gerrit_guidelines.md)
-* [coreboot's build system](build_system.md)
-* [Kconfig in coreboot](core/Kconfig.md)
-* [Use of git submodules in coreboot](submodules.md)
+* [Getting Started](getting_started/index.md)
+* [Rookie Guide](lessons/index.md)
 * [Timestamps](timestamp.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
 * [ABI data consumption](abi-data-consumption.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
-* [Sandy Bridge Raminit](Intel/NativeRaminit/Sandybridge.md)
+* [Northbridge-specific documentation](northbridge/index.md)
+* [System on Chip-specific documentation](soc/index.md)
 * [Mainboard-specific documentation](mainboard/index.md)
 * [SuperIO-specific documentation](superio/index.md)
+* [Vendorcode-specific documentation](vendorcode/index.md)
+* [Release notes for past releases](releases/index.md)
diff --git a/Documentation/lessons/index.md b/Documentation/lessons/index.md
@@ -0,0 +1,4 @@
+# Rookie Guide
+
+* [Lesson 1: Starting from scratch](lesson1.md)
+* [Lesson 2: Submitting a patch to coreboot.org](lesson2.md)
diff --git a/Documentation/lessons/lesson1.md b/Documentation/lessons/lesson1.md
@@ -0,0 +1,168 @@
+coreboot lesson 1 - Starting from scratch
+=========================================
+
+From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for
+a very basic build:
+
+Download, configure, and build coreboot
+---------------------------------------
+
+### Step 1 - Install tools and libraries needed for coreboot
+    $ sudo apt-get install -y bison build-essential curl flex git gnat-5 libncurses5-dev m4 zlib1g-dev
+
+### Step 2 - Download coreboot source tree
+    $ git clone https://review.coreboot.org/coreboot
+    $ cd coreboot
+
+### Step 3 - Build the coreboot toolchain
+Please note that this can take a significant amount of time
+
+    $ make crossgcc-i386 CPUS=$(nproc)
+
+Also note that you can possibly use your system toolchain, but the results are
+not reproducible, and may have issues, so this is not recommended.  See step 5
+to use your system toolchain.
+
+### Step 4 - Build the payload - coreinfo
+    $ make -C payloads/coreinfo olddefconfig
+    $ make -C payloads/coreinfo
+
+### Step 5 - Configure the build
+
+##### Configure your mainboard
+    $ make menuconfig
+       select 'Mainboard' menu
+       Beside 'Mainboard vendor' should be '(Emulation)'
+       Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'
+       select < Exit >
+These should be the default selections, so if anything else was set, run
+`make distclean` to remove your old config file and start over.
+
+##### Optionally use your system toolchain (Again, not recommended)
+       select 'General Setup' menu
+       select 'Allow building with any toolchain'
+       select < Exit >
+
+##### Select the payload
+       select 'Payload' menu
+       select 'Add a Payload'
+       choose 'An Elf executable payload'
+       select 'Payload path and filename'
+       enter 'payloads/coreinfo/build/coreinfo.elf'
+       select < Exit >
+       select < Exit >
+       select < Yes >
+
+##### check your configuration (optional step):
+
+    $ make savedefconfig
+    $ cat defconfig
+
+There should only be two lines (or 3 if you're using the system toolchain):
+
+    CONFIG_PAYLOAD_ELF=y
+    CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
+
+### Step 6 - build coreboot
+    $ make
+
+At the end of the build, you should see:
+
+    Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)
+
+This means your build was successful. The output from the build is in the build
+directory. build/coreboot.rom is the full rom file.
+
+Test the image using QEMU
+-------------------------
+
+### Step 7 - Install QEMU
+    $ sudo apt-get install -y qemu
+
+### Step 8 - Run QEMU
+Start QEMU, and point it to the ROM you just built:
+
+    $ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+
+You should see the serial output of coreboot in the original console window, and
+a new window will appear running the coreinfo payload.
+
+Summary
+-------
+
+### Step 1 summary - Install tools and libraries needed for coreboot
+You installed the minimum additional requirements for ubuntu to download and
+build coreboot. Ubuntu already has most of the other tools that would be
+required installed by default.
+
+* `build-essential` is the basic tools for doing builds.  It comes pre-installed
+on some Ubuntu flavors, and not on others.
+* `git` is needed to download coreboot from the coreboot git repository.
+* `libncurses5-dev` is needed to build the menu for 'make menuconfig'
+* `m4, bison, curl, flex, gnat-5, zlib1g-dev` are needed to build the coreboot
+toolchain.
+
+If you started with a different distribution, you might need to install many
+other items which vary by distribution.
+
+### Step 2 summary - Download coreboot source tree
+This will download a 'read-only' copy of the coreboot tree. This just means
+that if you made changes to the coreboot tree, you couldn't immediately
+contribute them back to the community. To pull a copy of coreboot that would
+allow you to contribute back, you would first need to sign up for an account on
+gerrit.
+
+### Step 3 summary - Build the coreboot toolchain.
+This builds one of the coreboot cross-compiler toolchains for X86 platforms.
+Because of the variability of compilers and the other required tools between
+the various operating systems that coreboot can be built on, coreboot supplies
+and uses its own cross-compiler toolchain to build the binaries that end up as
+part of the coreboot ROM. The toolchain provided by the operating system (the
+'host toolchain') is used to build various tools that will run on the local
+system during the build process.
+
+### Step 4 summary - Build the payload
+To actually do anything useful with coreboot, you need to build a payload to
+include in the rom. The idea behind coreboot is that it does the minimum amount
+possible before passing control of the machine to a payload. There are various
+payloads such as grub or SeaBIOS that are typically used to boot the operating
+system. Instead, we used coreinfo, a small demonstration payload that allows the
+user to look at various things such as memory and the contents of coreboot's
+cbfs - the pieces that make up the coreboot rom.
+
+### Step 5 summary - Configure the build
+This step configures coreboot's build options using the menuconfig interface to
+Kconfig. Kconfig is the same configuration program used by the linux kernel. It
+allows you to enable, disable, and change various values to control the coreboot
+build process, including which mainboard(motherboard) to use, which toolchain to
+use, and how the runtime debug console should be presented and saved.
+Anytime you change mainboards in Kconfig, you should always run `make distclean`
+before running `make menuconfig`. Due to the way that Kconfig works, values will
+be kept from the previous mainboard if you skip the clean step. This leads to a
+hybrid configuration which may or may not work as expected.
+
+### Step 6 summary - Build coreboot
+You may notice that a number of other pieces are downloaded at the beginning of
+the build process. These are the git submodules used in various coreboot builds.
+By default, the BLOBS submodule is not downloaded. This git submodule may be
+required for other builds for microcode or other binaries. To enable downloading
+this submodule, select the option "Allow use of binary-only repository" in the
+"General Setup" menu of Kconfig
+This attempts to build the coreboot rom. The rom file itself ends up in the
+build directory as 'coreboot.rom'. At the end of the build process, the build
+displayed the contents of the rom file.
+
+### Step 7 summary - Install QEMU
+QEMU is a processor emulator which we can use to show coreboot
+
+### Step 8 summary - Run QEMU
+Here's the command line broken down:
+* `qemu-system-x86_64`
+This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
+ISA bridge.
+* `-bios build/coreboot.rom`
+Use the bios rom image that we just built. If this is left off, the standard
+SeaBIOS image that comes with QEMU is used.
+* `-serial stdio`
+Send the serial output to the console. This allows you to view the coreboot
+debug output.
diff --git a/Documentation/Lesson2.md → Documentation/lessons/lesson2.md b/Documentation/Lesson2.md → Documentation/lessons/lesson2.md
diff --git a/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg
diff --git a/Documentation/mainboard/cavium/cn8100_sff_evb.md b/Documentation/mainboard/cavium/cn8100_sff_evb.md
@@ -0,0 +1,76 @@
+# CN81xx Evaluation-board SFF
+
+## Specs
+
+* 3 mini PCIe slots
+* 4 SATA ports
+* one USB3.0 A connector
+* 20Pin JTAG
+* 4 Gigabit Ethernet
+* 2 SFP+ connectors
+* PCIe x4 slot
+* UART over USB
+* eMMC Flash or MicroSD card slot for on-board storage
+* 1 Slot with DDR-4 memory with ECC support
+* SPI flash
+* MMC and uSD-card
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | no             |
++---------------------+----------------+
+| Model               | Micron 25Q128A |
++---------------------+----------------+
+| Size                | 8 MiB          |
++---------------------+----------------+
+| In circuit flashing | no             |
++---------------------+----------------+
+| Package             | SOIC-8         |
++---------------------+----------------+
+| Write protection    | No             |
++---------------------+----------------+
+| Dual BIOS feature   | No             |
++---------------------+----------------+
+| Internal flashing   | ?              |
++---------------------+----------------+
+```
+
+## Notes about the hardware
+
+1. Cavium connected *GPIO10* to a global reset line.
+   It's unclear which chips are connected, but at least the PHY and SATA chips
+   are connected.
+
+2. The 4 QLMs can be configured using DIP switches (SW1). That means only a
+   subset of of the available connectors is working at time.
+
+3. The boot source can be configure using DIP switches (SW1).
+
+4. The core and system clock frequency can be configured using DIP switches
+   (SW3 / SW2).
+
+5. The JTAG follows Cavium's own protocol. Support for it is missing in
+   OpenOCD. You have to use ARMs official hardware and software.
+
+## Technology
+
+```eval_rst
++---------------+----------------------------------------+
+| SoC           | :doc:`../../soc/cavium/cn81xx/index`   |
++---------------+----------------------------------------+
+| CPU           | Cavium ARMv8-Quadcore `CN81XX`_        |
++---------------+----------------------------------------+
+
+.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
+
+```
+
+## Picture
+
+![][cn81xx_board]
+
+[cn81xx_board]: cavium_cn81xx_sff_evb.jpg
diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md
@@ -0,0 +1,54 @@
+# Gigabyte GA-H61M-S2PV
+
+This page describes how to run coreboot on the [Gigabyte GA-H61M-S2PV] desktop
+from [Gigabyte].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MX25L3206E |
++---------------------+------------+
+| Size                | 4 MiB      |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | Yes        |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom].
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| SuperIO          | ITE IT8728F                                      |
++------------------+--------------------------------------------------+
+| EC               |                                                  |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Gigabyte GA-H61M-S2PV]: https://www.gigabyte.com/us/Motherboard/GA-H61M-S2PV-rev-10
+[Gigabyte]: https://www.gigabyte.com
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md
@@ -60,19 +60,19 @@ as otherwise there's not enough space near the flash.
 ## Technology
 
 ```eval_rst
-+------------------+--------------------------------------+
-| Northbridge      | Sandy Bridge                         |
-+------------------+--------------------------------------+
-| Southbridge      | bd82x6x                              |
-+------------------+--------------------------------------+
-| CPU              | model_206ax                          |
-+------------------+--------------------------------------+
-| SuperIO          | :doc:`../../superio/nuvoton/npcd378` |
-+------------------+--------------------------------------+
-| EC               |                                      |
-+------------------+--------------------------------------+
-| Coprocessor      | Intel ME                             |
-+------------------+--------------------------------------+
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| SuperIO          | :doc:`../../superio/nuvoton/npcd378`             |
++------------------+--------------------------------------------------+
+| EC               |                                                  |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
 ```
 
 [Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -2,10 +2,18 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
-## SiFive
+## Cavium
 
-- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
+- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
+
+## Gigabyte
+
+- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
 
 ## HP
 
 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
+
+## SiFive
+
+- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
diff --git a/Documentation/northbridge/index.md b/Documentation/northbridge/index.md
@@ -0,0 +1,7 @@
+# Northbridge-specific documentation
+
+This section contains documentation about coreboot on specific northbridges.
+
+## Vendor
+
+- [Intel](intel/index.md)
diff --git a/Documentation/northbridge/intel/index.md b/Documentation/northbridge/intel/index.md
@@ -0,0 +1,7 @@
+# Intel Northbridge-specific documentation
+
+This section contains documentation about coreboot on specific Intel Northbridges.
+
+## Platforms
+
+- [Sandy Bridge](sandybridge/index.md)
diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md
@@ -0,0 +1,8 @@
+# Intel Sandy Bridge-specific documentation
+
+This section contains documentation about coreboot on specific Intel "Sandy Bridge" northbridge.
+
+## Topics
+
+- [Native Ram Initialization](nri.md)
+- [RAM initialization feature matrix](nri_features.md)
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md
@@ -0,0 +1,135 @@
+# Sandy Bridge Raminit
+
+## Introduction
+
+This documentation is intended to document the closed source memory controller
+hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
+
+The memory initialization code has to take care of lots of duties:
+1. Selection of operating frequency
+* Selection of common timings
+* Applying frequency specific compensation values
+* Read training of all populated channels
+* Write training of all populated channels
+* Adjusting delay networks of address and command signals
+* DQS training of all populated channels
+* Programming memory map
+* Report DRAM configuration
+* Error handling
+
+## Definitions
+```eval_rst
++---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
++=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| timA    | IO phase: The phase delay of the IO signals                       | 1/64th DCK | [0-512)      |
++---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | Mhz        | 100, 133     |
++---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
++---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+```
+
+## (Inoffical) register documentation
+- [Sandy Bride - Register documentation](nri_registers.md)
+
+## Frequency selection
+- [Sandy Bride - Frequency selection](nri_freq.md)
+
+## Read training
+- [Sandy Bride - Read training](nri_read.md)
+
+### SMBIOS type 17
+The SMBIOS specification allows to report the memory configuration in use.
+On GNU/Linux you can run `# dmidecode -t 17` to view it.
+Example output of dmidecode:
+
+```
+Handle 0x0045, DMI type 17, 34 bytes
+    Memory Device
+	Array Handle: 0x0042
+	Error Information Handle: Not Provided
+	Total Width: 64 bits
+	Data Width: 64 bits
+	Size: 8192 MB
+	Form Factor: DIMM
+	Set: None
+	Locator: ChannelB-DIMM0
+	Bank Locator: BANK 2
+	Type: DDR3
+	Type Detail: Synchronous
+	Speed: 933 MHz
+	Manufacturer: 0420
+	Serial Number: 00000000
+	Asset Tag: 9876543210
+	Part Number: F3-1866C9-8GSR
+	Rank: 2
+	Configured Clock Speed: 933 MHz
+```
+The memory frequency printed by dmidecode is the active memory frequency. It's
+**not** the double datarate and it's **not** the one encoded maximum frequency
+in each DIMM's SPD.
+
+> **Note:** This feature is available since coreboot 4.4
+
+### MRC cache
+The name *MRC cache* might be missleading as in case of *Native ram init*
+there's no MRC, but for historical reasons it's still named *MRC cache*.
+The MRC cache is part of flash memory that is writeable by coreboot.
+At the end of the boot process coreboot will write the RAM training results to
+flash for future use, as RAM training is time intensive. Storing the results
+allows to boot faster on normal boot and allows to support S3 resume,
+as the RAM training results can't be stored in RAM (you need to configure
+the memory controller first to access RAM).
+
+The MRC cache needs to be invalidated in case the memory configuration has
+been changed. To detect a changed memory configuration the CRC16 of each DIMM
+is stored to MRC cache.
+> **Note:** This feature is available since coreboot 4.4
+
+### Error handling
+As of writing the only supported error handling is to disable the failing
+channel and restart the memory training sequence. It's very likely to succeed,
+as memory channels operate independent of each other.
+In case no DIMM could be initilized coreboot will halt. The screen will stay
+black until you power of your device. On some platforms there's additional
+feedback to indicate such an event.
+
+If you find `dmidecode -t 17` to report only half of the memory installed,
+it's likely that a fatal memory init failure had happened.
+It is assumed, that a working board with less physical memory, is much better,
+than a board that doesn't boot at all.
+
+> **Note:** This feature is available since coreboot 4.5
+
+Try to swap memory modules and or try to use a different vendor. If nothing
+helps you could have a look at capter [Debuggin] or report a ticket
+at [ticket.coreboot.org]. Please provide a full RAM init log,
+that has been captured using EHCI debug.
+
+To enable extensive RAM training logging enable the Kconfig option
+`DEBUG_RAM_SETUP`
+#### Lenovo Thinkpads
+Lenovo Thinkpads do have an additional feature to indicate that RAM init has
+failed and coreboot has died (it calls die() on fatal error, thus the name).
+The Kconfig options
+`H8_BEEP_ON_DEATH`
+`H8_FLASH_LEDS_ON_DEATH`
+enable blinking LEDs and enable a beep to indicate death.
+
+> **Note:** This feature is available since coreboot 4.7
+
+## Debugging
+It's recommended to use an external debugger, such as serial or EHCI debug
+dongle. In case of failing memory init the board might not boot at all,
+preventing you from using CBMEM.
diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md
@@ -0,0 +1,89 @@
+# RAM initialization feature matrix
+
+## Options
+
+1.  Native raminit
+    * Open Source
+    * Native Raminit is working for most frequencies on most boards.
+    * There might be errors to fix.
+    * Position in romstage doesn't matter.
+2.  mrc.bin raminit
+    * Closed Source (aka BLOB)
+    * No known errors.
+    * Needs to be placed at fixed offset in romstage.
+
+## Native raminit implemented features
+
+```eval_rst
++---------------------------+----------------------+-------------+---------+---------------------+
+| Option                    |            Supported | Implemented | Working | Description         |
++===========================+======================+=============+=========+=====================+
+| **Supported channels**                                                                         |
++---------------------------+----------------------+-------------+---------+---------------------+
+| single and dual channel   |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+| Up to 4 slots             |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+| Up to 4 ranks per channel |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+| **Supported frequencies**                                                                      |
++---------------------------+----------------------+-------------+---------+---------------------+
+|        DDR3-1066 (533MHz) |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|        DDR3-1600 (800MHz) |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|        DDR3-1866 (933MHz) |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|       DDR3-2133 (1066MHz) |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|        DDR3-1400 (700MHz) | yes (IvyBridge only) |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|        DDR3-1800 (900MHz) | yes (IvyBridge only) |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|       DDR3-2000 (1000MHz) | yes (IvyBridge only) |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|       DDR3-2200 (1100MHz) | yes (IvyBridge only) |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|       DDR3-2400 (1200MHz) | yes (IvyBridge only) |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|        DDR3-1800 (900MHz) | yes (IvyBridge only) |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+| **Supported CAS latencies**                                                                    |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                       CL6 |                  yes |         yes |       ? |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                       CL7 |                  yes |         yes |       ? |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                       CL8 |                  yes |         yes |       ? |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                       CL9 |                  yes |         yes |       ? |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                      CL10 |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                      CL11 |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                      CL12 |                  yes |         yes |       ? | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                      CL13 |                  yes |         yes |     yes | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                      CL14 |                  yes |         yes |       ? | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                      CL15 |                  yes |         yes |       ? | Since coreboot 4.6  |
++---------------------------+----------------------+-------------+---------+---------------------+
+| **MRC cache (stored timings of last training)**                                                |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                        S3 |                  yes |         yes |     yes |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+|               normal boot |                  yes |         yes |     yes | reset on CRC16 diff |
++---------------------------+----------------------+-------------+---------+---------------------+
+| **XMP support**                                                                                |
++---------------------------+----------------------+-------------+---------+---------------------+
+|             XMP Profile 1 |                  yes |         yes |     yes | only 1.5 V profiles |
++---------------------------+----------------------+-------------+---------+---------------------+
+|             XMP Profile 2 |                  yes |         yes |      no |       not activated |
++---------------------------+----------------------+-------------+---------+---------------------+
+| **ECC support**                                                                                |
++---------------------------+----------------------+-------------+---------+---------------------+
+|                       ECC |                  yes |          no |         |                     |
++---------------------------+----------------------+-------------+---------+---------------------+
+```
diff --git a/...n/Intel/NativeRaminit/Sandybridge_freq.md → ...northbridge/intel/sandybridge/nri_freq.md b/...n/Intel/NativeRaminit/Sandybridge_freq.md → ...northbridge/intel/sandybridge/nri_freq.md
diff --git a/...n/Intel/NativeRaminit/Sandybridge_read.md → ...northbridge/intel/sandybridge/nri_read.md b/...n/Intel/NativeRaminit/Sandybridge_read.md → ...northbridge/intel/sandybridge/nri_read.md
diff --git a/...el/NativeRaminit/SandyBridge_registers.md → ...bridge/intel/sandybridge/nri_registers.md b/...el/NativeRaminit/SandyBridge_registers.md → ...bridge/intel/sandybridge/nri_registers.md
diff --git a/...ativeRaminit/timA_lane0-3_adjust_fine.png → .../sandybridge/timA_lane0-3_adjust_fine.png b/...ativeRaminit/timA_lane0-3_adjust_fine.png → .../sandybridge/timA_lane0-3_adjust_fine.png
diff --git a/...iveRaminit/timA_lane0-3_discover_420x.png → ...andybridge/timA_lane0-3_discover_420x.png b/...iveRaminit/timA_lane0-3_discover_420x.png → ...andybridge/timA_lane0-3_discover_420x.png
diff --git a/...Intel/NativeRaminit/timA_lane0-3_rt53.png → ...e/intel/sandybridge/timA_lane0-3_rt53.png b/...Intel/NativeRaminit/timA_lane0-3_rt53.png → ...e/intel/sandybridge/timA_lane0-3_rt53.png
diff --git a/...Intel/NativeRaminit/timA_lane0-3_rt54.png → ...e/intel/sandybridge/timA_lane0-3_rt54.png b/...Intel/NativeRaminit/timA_lane0-3_rt54.png → ...e/intel/sandybridge/timA_lane0-3_rt54.png
diff --git a/...Intel/NativeRaminit/timA_lane0-3_rt55.png → ...e/intel/sandybridge/timA_lane0-3_rt55.png b/...Intel/NativeRaminit/timA_lane0-3_rt55.png → ...e/intel/sandybridge/timA_lane0-3_rt55.png
diff --git a/Documentation/releases/coreboot-4.1-relnotes.md b/Documentation/releases/coreboot-4.1-relnotes.md
@@ -0,0 +1,58 @@
+Announcing coreboot 4.1
+=======================
+
+Dear coreboot community,
+
+It has been more than 5 years since we have "released" coreboot 4.0.
+That last release marked some very important milestones that we
+originally prototyped in the abandoned LinuxBIOS v3 efforts, like the
+coreboot filesystem (CBFS), Kconfig support, and (strictly) separate
+device trees, build logic and configuration.
+
+Since then there have been as many significant original developments,
+such as support for many new architectures (ARM, ARM64, MIPS, RISC-V),
+and related architectural changes like access to non-memory mapped SPI
+flash, or better insight about the internals of coreboot at runtime
+through the cbmem console, timestamp collection, or code coverage
+support.
+
+It became clear that a new release is overdue. With our new release
+process only slowly getting in shape, I decided to take a random commit
+and call it 4.1.
+
+The release itself happens at an arbitrary point in time, but will serve
+as a starting point for other activities that require some kind of
+starting point to build on, described below.
+
+Future releases will happen more frequently, and with more guarantees
+about the state of the release, like having a cool down phase where
+boards can be tested and so on. I plan to create a release every three
+months, so the changes between any two release don't become too
+overwhelming.
+
+With the release of coreboot 4.1, you get an announcement (this email),
+a git tag (4.1), and tar archives at http://www.coreboot.org/releases/,
+for the coreboot sources and the redistributable blobs.
+
+Starting with coreboot 4.1, we will maintain a high level changelog and
+'flag days' document. The latter will provide a concise list of changes
+which went into coreboot that require chipset or mainboard code to
+change to keep it working with the latest upstream coreboot.
+
+For the time being, I will run these efforts, but I'll happily share
+documentation duties with somebody else. It is a great opportunity to
+keep track of things, learn about the project and its design and various
+internals, while contributing to the project without the need to code.
+
+Please contact me (for example by email or on IRC) if you're interested,
+and we'll work out how to collaborate on this.
+
+The process should enable users of coreboot to follow releases if they
+want a more static base to build on, while making it easier to follow
+along with new developments by providing upgrade documentation.
+
+Since moving away from a rolling (non-)release model is new for
+coreboot, things may still be a bit rough around the edges, but I'll
+provide support for any issues that arise from the release process.
+
+Patrick
diff --git a/Documentation/releases/coreboot-4.2-relnotes.md b/Documentation/releases/coreboot-4.2-relnotes.md
@@ -0,0 +1,182 @@
+Announcing coreboot 4.2
+=======================
+
+Halloween 2015 release - just as scary as that sounds
+
+Dear coreboot community,
+today marks the release of coreboot 4.2, the second release on our time
+based release schedule. Since 4.1 there were 936 commits by 90 authors,
+increasing the code base by approximately 17000 lines of code. We saw 35
+new contributors - welcome to coreboot! More than 34 developers were
+active as reviewers in that period. Thanks go to all contributors who
+helped shape this release.
+
+As with 4.1, the release tarballs are available at
+http://www.coreboot.org/releases/. There's also a 4.2 tag and branch in
+the git repository.
+
+This marks the first release that features a changelog comparing it to
+the previous release. There was some limited testing to make sure that
+the code is usable, and it boots on some devices. A structured test plan
+will only become part of the release procedure of future versions. I'm
+grateful to Martin for assembling this release's changelog.
+
+This is also the first release that will be followed by the removal of
+old, unused code. There will be a policy on how to announce deprecation
+and removal of mainboard and chipset code for future releases.
+
+Regards,
+Patrick
+
+Log of commit d5e6618a4f076610e683b174c4dd5108d960c785 to
+commit 439a527014fa0cb3e4ef60ba59e5c57c737b4444
+
+Changes between 4.1 and 4.2
+---------------------------
+
+### Build system:
+* Store a minimized coreboot config file in cbfs instead of the full
+  config
+* Store the payload config and revision in CBFS when that info is
+  available
+* Add -compression option for cbfs-files-y. Valid entries are now -file,
+  -type, -align, and -compression
+* Change Microcode inclusion method from building .h files to pre-built
+  binaries
+* Update Builder tests for each commit to test utilities and run lint
+  tools
+* Many other small makefile and build changes and fixes
+* Remove expert mode as a Kconfig option
+
+### Utilities:
+* Many fixes and updates to many utilities (158 total commits)
+* ifdtool: Update for skylake, handle region masks correctly
+* crossgcc: Update to gcc 5.2.0
+* kconfig: Add strict mode to fail on kconfig errors and warnings
+* vgabios: Significant fixes to remove issues in linking into coreboot
+  code
+* Add script to parse MAINTAINERS file
+* Add Kconfig lint tool
+* Create a common library to share coreboot routines with utilities
+
+#### Significant changes and cleanup to cbfstool (81 commits)
+* Update cbfstool to change the internal location of FSP binaries when
+  adding them
+* Decompress stage files on extraction and turn them into ELF binaries
+* Header sizes are now variable, containing extended attributes
+* Add compression tags to all cbfs headers so all cbfs files can be
+  compressed
+* Add and align CBFS components in one pass instead of two
+* Add XIP support for X86 to relocate the romstage when it'™s added
+* Removed locate command as it'™s no longer needed
+* Add bootblock and cbfs_header file types so the master header knows
+  about them
+* Prefer FMAP data to CBFS master header if FMAP data exists
+* Add hashes to cbfs file metadata for verification of images
+
+### Payloads:
+* SeaBIOS: update stable release from 1.7.5 to 1.8.2
+* Libpayload had some significant changes (61 commits). Major changes:
+* Add support for fmap tables
+* Add support for SuperSpeed (3.0) USB hubs
+* Updates and bugfixes for DesignWare OTG controller (DWC2)
+* Add video_printf to print text with specified foreground & background
+  colors
+* Updates to match changes to cbfs/cbfstool
+* Add cbgfx, a library to show graphics and text on a display
+* Read cbfs offset and size from sysinfo when available
+
+### Vendorcode:
+* fsp_baytrail: Support Baytrail FSP Gold 4 release
+* AMD binary PI: add support for fan control
+* Work to get AMD AGESA to compile correctly as 64-bit code
+* Add standalone (XIP) verstage support for x86 to verify romstage
+
+### Mainboards:
+* New Mainboards:
+* apple/macbookair4_2 * Sandy/Ivy Bridge with Panther / Cougar point
+chipset
+* asus/kgpe-d16 - AMD Family 10, SB700/SR5650 platform
+* emulation/spike-riscv - RISCV virtualized platform
+* google/chell - Intel Skylake chrome platform
+* google/cyan - Intel Braswell chrome platform
+* google/glados - Intel Skylake chrome platform
+* google/lars - Intel Skylake chrome platform
+* intel/kunimitsu - Intel Skylake chrome platform
+* intel/sklrvp - Intel Skylake reference platform
+* intel/strago - Intel Braswell chrome platform
+* Cleanups of many mainboards - several patches each for:
+* amd/bettong
+* getac/p470
+* google/auron, google/smaug and google/veyron_rialto
+* pcengines/apu1
+* siemens/mc_tcu3
+* Combine the google/veyron_(jerry, mighty, minnie, pinkie, shark &
+  speedy) mainboards into the single google/veyron mainboard directory
+
+### Console:
+* Add EM100 ˜hyper term" spi console support in ramstage & smm
+* Add console support for verstage
+
+### ARM:
+* armv7: use asm coded memory operations for 32/16 bit read/write
+* Many cleanups to the nvidia tegra chips (40 patches)
+
+### RISC-V:
+* Add trap handling
+* Add virtual Memory setup
+
+### X86:
+* Remove and re-add Rangeley and Ivy Bridge / panther point FSP
+  platforms
+* Update microcode update parser to use stock AMD microcode blobs from
+  CBFS
+* ACPI: Align FACS to 64 byte boundary. Fixes FWTS error
+* AMD/SB700: Init devices in early boot, restore power state after power
+  failure. Add IDE/SATA asl code
+* Add initial support for AMD Socket G34 processors
+* Add tick frequency to timestamp table to calculate boot times more
+  accurately
+* Unify X86 romstage / ramstage linking to match other platforms
+* Start preparing X86 bootblock for non-memory-mapped BIOS media
+* cpu/amd/car: Add Suspend to RAM (S3) support
+* Native VGA init fixes on several platforms
+* Significant updates to FSP 1.1 code for cleanup and cbfstool changes
+* SMMhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG to
+  prevent the memory sinkhole smm hack
+
+### Drivers:
+* Add native text mode support for the Aspeed AST2050
+* w83795: Add support for for fan control and voltage monitoring
+* Intel GMA ACPI consolidation and improvements
+* Set up the 8254 timer before running option ROMs
+* Resource allocator: Page align memory mapped PCI resources
+
+### Lib:
+* Derive fmap name from offset/size
+* Several edid fixes
+* Updates to cbfs matching changes in cbfstool
+
+Submodules:
+----------
+### 3rdparty/blobs:
+Total commits: 16
+Log of commit 61d663e3 to commit aab093f0
+* AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)
+* AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1)
+* Update microcode to binary blobs. Remove old .h microcode files
+
+### 3rdparty/arm-trusted-firmware:
+* No Changes
+
+### 3rdparty/vboot:
+Total commits: 41
+Log of commit fbf631c8 to commit d6723ed1
+* Update the code to determine the write protect line gpio value
+* Several updates to futility and image_signing scripts
+* Update crossystem to accommodate Android mosys location
+* Support reboot requested by secdata
+* Add NV flag to default boot legacy OS
+
+### util/nvidia/cbootimage:
+* No Changes
diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md
@@ -0,0 +1,183 @@
+Announcing coreboot 4.3
+=======================
+
+The "Oh, has FOSDEM started?" release
+
+Dear coreboot community,
+
+today marks the release of coreboot 4.3, the third release on our time
+based release schedule. Since the last release, 1030 commits by 114
+authors added a net total of 17500 lines to the source code. Thank you
+to all who contributed!
+
+The release tarballs are available at http://www.coreboot.org/releases/.
+There's also a 4.3 tag and branch in the git repository.
+
+Besides the usual addition of new mainboards (14) and chipsets
+(various), a big theme of the development since 4.2 was cleaning up the
+code: 20 mainboards were removed that aren't on the market for years
+(and even hard to get on Ebay). For several parts of the tree, we
+established tighter controls, making errors out of what were warnings
+(and cleaning up the code to match) and provided better tests for
+various aspects of the tree, and in general tried to establish a more
+consistent structure across the code base.
+
+Besides that, we had various improvements across the tree, each
+important when using the hardware, but to numerous for individual shout
+outs. Martin compiled a list that's best posted verbatim. Thanks Martin!
+
+Log of commit 529fd81f640fa514ea4c443dd561086e7c582a64 to commit
+1bf5e6409678d04fd15f9625460078853118521c for a total of 1030 commits:
+
+Mainboards
+----------
+
+### Added 14 mainboards
+
+* asus/kfsn4-dre_k8: Native init Dual AMD K8 CPUs & Nvidia CK804
+  southbridge
+* esd/atom15: Bay Trail SOC mainboard using Intel's FSP
+* gigabyte/ga-g41m-es2l: Intel Core 2 / Native init x4x NB / I82801GX SB
+* google/guado: Intel Broadwell chromebox (Asus Chromebox CN62)
+* google/oak: Mediatek MT8173 SoC chromebook
+* google/tidus: Intel Broadwell chromebox (Lenovo ThinkCentre Chromebox)
+* google/veyron_emile: Rockchip RK3288 SoC board
+* intel/d510mo: Native init Intel Pineview with Intel I82801GX
+  southbridge
+* intel/littleplains: Intel Atom c2000 (Rangeley) SoC board
+* intel/stargo2: Intel Ivy Bridge / Cave Creek usint Intel's FSP
+* lenovo/r400: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
+* lenovo/t500: Intel Core 2 / Native init GM45 NB / Intel I82801IX SB
+* purism/librem13: Intel Broadwell Laptop using Intel MRC
+* sunw/ultra40m2: Native init Dual AMD K8 Processors & Nvidia MCP55 SB
+
+### Removed 20 mainboards
+
+* arima/hdama
+* digitallogic/adl855pc
+* ibm/e325, e326
+* intel/sklrvp
+* iwill/dk8s2, dk8x
+* newisys/khepri
+* tyan/s2735, s2850, s2875, s2880, s2881 & s2882
+* tyan/s2885, s2891, s2892, s2895, s4880 & s4882
+
+### Improvements to mainboards
+
+* amd/bettong: fixes to Interrupts, Memory config, S4, EMMC, UARTS
+* asus/kgpe-d16: IOMMU and memory fixes, Add CMOS options, Enable GART
+* intel/strago: GPIO, DDR, & SD config, FSP updates, Clock fixes
+* ACPI fixes across various platforms
+* Many individual fixes to other mainboards
+
+### Continued updates for the Intel Skylake platform
+
+* google/chell, glados, & lars: FSP & Memory updates, Add Fan & NHLT
+  support
+* intel/kunimitsu: FSP & GPIO updates, Add Fan & NHLT (audio) support
+
+Build system
+------------
+* Update build to use FMAP based firmware layout with multiple cbfs
+  sections
+* Enable Kconfig strict mode - Kconfig warnings are no longer allowed.
+* Enable ACPI warnings are errors in IASL - warnings are no longer
+  allowed.
+* Tighten checking on toolchains and give feedback to users if there are
+  issues
+* Updates to get the ADA compiler to work correctly for coreboot
+* Various improvements to Makefiles and build scripts
+* Cleanup of CBFS file handling
+
+Utilities
+---------
+* cleanups and improvements to many of the utilities
+* cbfstool: Many fixes and extensions to integrate with FMAP
+* Add amdfwtool to combine AMD firmware blobs instead of using shell
+  scripts.
+* Toolchain updates: new versions of GMP & MPFR. Add ADA.
+* Updates for building on NetBSD & OS X
+
+Payloads
+--------
+* SeaBIOS: Update stable release to 1.9.0
+* coreinfo: fix date, hide cursor, use crosscompiler to build
+* libpayload: updates for cbfs, XHCI and DesignWare HCD controllers
+
+ARM
+---
+* Added 1 soc: mediatek/mt8173
+* Various fixes for ARM64 platforms
+
+X86
+---
+* Added 2 northbridges: intel/pineview & x4x
+* Removed 1 northbridge: intel/i440lx
+* Added 1 southbridge: intel/fsp_i89xx
+* Removed 2 southbridge(s): intel/esb6300 & i82801cx
+* Rename amd/model_10xxx to family_10h-family_15h.
+* ACPI: fix warnings, Add functions for IVRS, DMAR I/O-APIC and HPET
+  entries
+* Work in many areas fixing issues compiling in 64-bit
+* Numerous other fixes across the tree
+
+Areas with significant work on updates and fixes
+------------------------------------------------
+* cpu/amd/model_fxx
+* intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode
+* nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other
+  changes
+* nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other
+  changes
+* nb/intel/sandybridge: Add IOMMU & ACPI DMAR support, Memory cleanup
+* soc/intel/braswell: FSP & ACPI updates, GPIO & clock Fixes
+* soc/intel/fsp_baytrail: GPIO, microcode and Interrupt updates.
+* soc/intel/skylake: FSP, Power/Thermal & GPIO Updates, Add NHLT support
+* sb/amd/sb700: Add ACPI & CMOS Setting support, SATA & clock Fixes
+
+MIPS
+----
+* Imgtec Pistachio: Memory, PLL & I2C fixes, add reset
+
+SuperIO
+-------
+* Expand functionality for ite/it8718f & nuvoton/nct5572d superio
+  devices
+
+### Added 3 SIOs
+
+* intel/i8900
+* winbond/w83667hg-a & wpcd376i
+
+### Removed 6 SIOs
+
+* fintek/f71889
+* ite/it8661f
+* nsc/pc8374 & pc97307
+* nuvoton/nct6776
+* smsc/fdc37m60x
+
+Lib
+---
+* Several updates for reading EDID tables
+
+MISC
+----
+* Commonlib: continued updates for cbfs changes
+* Work on getting license headers on all coreboot files
+* Drop the third paragraph of GPL copyright header across all of
+  coreboot
+
+Submodules
+----------
+* 3rdparty/blobs: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)
+
+coreboot statistics
+-------------------
+Total commits: 1030
+Total authors: 114
+New authors: 46
+Total Reviewers: 41
+Total lines added: 88255
+Total lines removed: -70735
+Total delta: 17520
diff --git a/Documentation/releases/coreboot-4.4-relnotes.md b/Documentation/releases/coreboot-4.4-relnotes.md
@@ -0,0 +1,110 @@
+Announcing coreboot 4.4
+=======================
+
+We are happy to announce the release of coreboot 4.4.  This is our
+fourth quarterly release.  Since the last release, we've had 850 commits
+by 90 authors adding 59000 lines to the codebase.
+
+The release tarballs are available at https://www.coreboot.org/releases/
+There is a 4.4 tag and branch in the git repository.
+
+Log of commit 3141eac900 to commit 588ccaa9a7
+
+Major areas that received significant changes in for this release:
+* Build system (30 commits) - Add postcar stage, 'timeless' builds,
+  extend site-local, test toolchain by version string, update
+  dependencies, catch ACPI errors, add additional macros.
+* Toolchain updates (40+ patches) - Update IASL to v20160318 , LLVM to
+  v3.7.1, add GNU make, add nds32le GCC compiler
+* Lint tools (30 patches) - Update existing lint utilities, add lint
+  tests for executable bit, make sure site-local isn't committed, add
+  test to break all lint tests.
+* Payloads (60 commits) - Fixes for libpayload, coreinfo and nvramcui,
+  add new payloads, see below.
+* Maintainers file - (8 patches) - continue adding maintainers for
+  various areas.
+* Documentation for adding Intel FSP-based platforms (20 commits)
+
+Mainboards
+----------
+### Added 9 mainboards
+* asus/kcma-d8
+* emulation/qemu-power8
+* google/auron_paine
+* google/gru
+* intel/amenia
+* intel/apollolake_rvp
+* intel/camelbackmountain_fsp
+* intel/galileo
+* lenovo/t420
+
+### Existing boards with significant updates
+* asus/kgpe-d16
+* google/oak
+* google/chell
+* intel/kunimitsu
+
+Changes in chips
+----------------
+### Added 1 new architecture
+* power8
+
+### Added 1 processor
+* qemu-power8
+
+### Added 5 socs
+* intel/apollolake
+* intel/fsp_broadwell_de
+* intel/quark
+* marvell/armada38x
+* rockchip/rk3399
+
+### Existing chip areas with many changes
+* cpuamd/mct_ddr3
+* drivers/intel/fsp2_0
+* northbridge/intel/sandybridge/raminit
+* soc/intel/apollolake
+* soc/intel/fsp_baytrail
+* soc/intel/skylake
+* soc/mediatek/mt8173
+
+### Added 1 new vendorcode directory
+* siemens
+
+Submodules
+----------
+### Added 1 submodule
+* chromeec
+
+### Updated 3 submodules
+* 3rdparty/arm-trusted-firmware (329 commits)
+* 3rdparty/vboot (28 commits)
+* util/nvidia/cbootimage (13 commits)
+
+Other
+-----
+### Added 4 payloads
+* depthcharge: For ChromeOS verified boot
+* iPXE: For network booting
+* Memtest86+: Updated with fixes for correctly testing coreboot with
+  payloads
+* U-Boot (Experimental): Alternate payload for booting an OS
+
+### Added 6 utilities
+* archive - Concatenates files into a single blob with an indexed header
+* chromeos - Download and extract blobs from a ChromeOS image
+* futility - vboot Firmware utility
+* intelmetool - Shows information about the Intel ME on a platform.
+* marvell/doimage_mv - No usage notes
+* post - Simple utility to test post cards
+
+coreboot statistics
+-------------------
+* Total Commits:          850
+* Total authors:           90
+* New authors:             28
+* Total Reviewers:         40
+* Total Submitters:        17
+* Total lines added:    74054
+* Total lines removed: -15056
+* Total difference:     58998
diff --git a/Documentation/releases/coreboot-4.5-relnotes.md b/Documentation/releases/coreboot-4.5-relnotes.md
@@ -0,0 +1,214 @@
+Announcing coreboot 4.5
+=======================
+
+We are happy to announce the release of coreboot 4.5
+
+The 4.5 release covers commit 80a3df260767 to commit 0bc12abc2b26.
+
+This release is the first since the project switched from doing
+quarterly releases to doing biannual releases.  The next release will be
+in April of 2017.
+
+Since the last release in April, the coreboot project has had 1889
+commits by 119 authors.
+
+The release tarballs and gpg signatures are available in the usual place
+at https://www.coreboot.org/downloads
+
+There is a 4.5 tag in the git repository, and a branch will be created
+as needed.
+
+
+Areas with significant updates
+------------------------------
+
+### Toolchain (29 commits)
+* Updated mpfr version from 3.1.3 to 3.1.4
+* Updated gcc version from 5.2.0 to 5.3.0
+* Updated binutils version from 2.25 to 2.26.1 & Fix aarch64 build
+  problem
+* Updated gdb version from 7.9.1 to 7.11
+* Updated iasl version from 20160318 to 20160831
+* Updated python version from 3.4.3 to 3.5.1
+* Updated expat version from 2.1.0 to 2.1.1
+* Updated llvm / clang version from 3.7.1 to 3.8.0
+* Updated make version from 4.1 to 4.2.1
+
+### Build system (32 commits)
+* Updates for cbfstool / fmap changes
+* Order per-region files to optimize placement success
+* Add support for the ADA language and toolchain.
+
+### Utilities (103 commits)
+* Lint - Update checkpatch.pl, add tools  to find non-ascii &
+  unprintable chars and to verify a single newline at the end of files
+* cbfstool - Update for Linux payloads, Honor FSP modules addresses, fix
+  elf parsing
+* Sconfig - Add 10 bit addressing mode for i2c devices, add generic
+  device type, support strings, pass in devicetree filename
+* General code cleanup (197 commits)
+* Cleaning up code formatting and whitespace
+* Fix spelling & capitalization
+* Removing commented out code
+* Transition away from device_t
+
+### TPM (55 commits)
+* Add support for Trusted Platform Module 2.0
+* SPI & refactored I2C TPM driver
+
+### Drivers (54 commits)
+* Add ACPI support in several drivers
+* coreboot_tables -  Extend serial port description
+* Elog - refactor, add debug info
+* I2C - add generic driver,
+* SPI - Add new chip support, major refactoring, don't assume SPI flash
+  boot device
+
+### Lib (33 commits)
+* Add real-time-clock functions
+* Add RW boot device construct
+* reg_script updates: add to bootblock, add xor support, add display
+  support
+* Timestamp fixes & updates
+
+### Vendorcode
+* AMD (14 commits) - Cleanup, add libagesa.a builds, remove unused code.
+* Google (22 commits) - VBoot2 updates and cleanup
+* Intel (86 commits) - Add Intel FSP 2.0, update Broadwell DE support
+
+### Payloads (37 commits)
+* Subpayload support got extend and is enabled by default.
+* nvramcui: refactor, update build
+* SeaBIOS: Update stable version to 1.9.3, add bootorder file
+* iPXE: Update stable version to the last commit of July 2016
+* Fix broken linux boot sequence
+
+Mainboard changes
+-----------------
+
+### Added 13 mainboards, plus a few mainboard variants not included here
+* ADI RCC-DFF networking board (adi/rcc-dff) - intel/rangeley SoC
+* AMD Evaluation Board DB-FT3B-LC (amd/db-ft3b-lc) - amd/00730F01
+  (Family 16h  Models 30h-3Fh (Mullins)) CPU
+* AMD f2950 / TONK 1201/2 Board (amd/f2950) - amd/geode_lx CPU
+* Apple iMAC 5.2 (apple/imac52) - intel/i945 CPU
+* Unibap Development Kit ODE E21XX - amd/00730F01 (Family 16h Models
+  30h-3Fh (Mullins)) CPU
+* elmex/pcm205400 - amd/Family_14 CPU
+* elmex/pcm205401 - amd/Family_14 CPU
+* Lenovo N21 chromebook (google/enguarde) - intel/baytrail SoC
+* google/gale - Qualcomm IPQ40XX SoC
+* AOpen Chromebox (google/ninja) - intel/baytrail SoC
+* google/reef - intel/apollolake SoC
+* Acer Chromebox CXI2 (google/rikku) - intel/Broadwell SoC
+* google/rotor - marvell/MVMAP2315 SoC
+
+### Removed 5 mainboards:
+These were all development boards not available to the public.
+* google/bolt - intel/haswell - removed in commit 139314b
+* google/rush - nvidia/tegra132 - removed in commit e67cd9e
+* google/rush_ryu - nvidia/tegra132 - removed in commit 0c63415
+* google/slippy - intel/haswell - removed in commit bc24b85
+* intel/amenia - intel/apollolake - removed in commit c2586db
+
+### Existing boards with significant updates
+* asus/kgpe-d16 - amd/socket_G34 - Add TPM support, enable secondary
+  serial port
+* emulation/spike-riscv: RISC-V -clean up, use generic bootblock, look
+  for  CBFS in RAM, reimplement SBI
+* google/gru - rockchip/RK3399 SoC (76 commits) - Board bringup
+* google/oak - mediatek/mt8173 SoC- Add Elm variant, update memory,
+  configure display, initialize touchscreen gpio
+* intel/galilleo- intel/quark SoC (14 commits) - Board bringup, add
+  galileo gen1 support, switch to FSP2.0
+* intel/minnowmax - intel/fsp_baytrail SoC - Enable all PCIe ports,
+  Program GPIO for power LED
+* lenovo/x60 - intel/socket_mPGA478 - init GPIOs before dock check, add
+  hda verb table
+* siemens/mc_bdx1 - intel/fsp_broadwell_de SoC - Add external RTC, Set
+  up MAC addresses, Update IRQs
+* siemens/mc_tcu3 - intel/fsp_baytrail SoC - cleanup & LCD panel updates
+
+Changes in chips
+----------------
+### Moved 3 northbridge/southbridge pairs to soc:
+* dmp/vortex86ex
+* intel/sch
+* rdc/r8610
+
+### Added 2 socs:
+* marvell/mvmap2315 (12 commits)
+* qualcomm/ipq40xx (22 commits)
+
+### Removed 1 soc:
+* nvidia/tegra132 - removed in commit 9ba0699
+
+### Added 2 sios:
+* nuvoton/nct6776
+* nuvoton/nct6791d
+
+### ARM (34 commits)
+* Add armv7-r configuration
+
+#### rockchip/rk3399 (73 commits)
+* Bringup, memory updates
+
+### RISC-V (40 commits)
+* Improve and refactor trap handling
+
+### X86 (225 commits)
+
+### ACPI (40 commits)
+* Add support for writing various entries and descriptor
+  types, Add common definitions, Use 'GOOG' id for coreboot table
+* amd/mct_ddr3 northbridge: Support non-ECC DIMMs, Update SMBIOS,
+  various fixes
+* arch/x86: many postcar stage updates, add common ACPI definitions,
+  Support "weak" BIST and timestamp save routines
+* intel/apollolake SoC (211 commits) - Chip bringup, Update bootblock
+* intel/common: ACPI updates, Add smihandler, LPSS I2C driver, and  IGD
+  OpRegion support
+* intel/fsp_broadwell_de: IRQ fixes, SPI message fixes, Add DMAR table
+  to ACPI
+* intel/gm45 northbridge: Fix text mode init, enable vesa framebuffer,
+  use VGA if connected
+* intel/i945 northbridge: add native VGA init, Update divisor
+  calculations
+* intel/quark SoC (62 commits) - Chip bringup, add Fsp2.0 support,
+  updates for serial console
+* intel/skylake CPU (61 commits) - Finished Skylake bringup, start
+  updating for Kabylake FSP
+* intel/x4x northbridge (13 commits) - Memory & Graphics updates
+
+Submodules
+----------
+Updated 4 submodules
+* 3rdparty/blobs (6 commits)
+* 3rdparty/arm-trusted-firmware (425 commits)
+* 3rdparty/vboot (61 commits)
+* 3rdparty/chromeec/ (676 commits)
+
+Tested boards
+-------------
+The following boards were tested for this release:
+* asrock/e350m1                 4.4-1890
+* asus/kfsn4-dre                4.4-1698 / 4.5-17
+* asus/kgpe-d16                 4.4-1802 / 4.5-17
+* emulation/qemu-q35            4.4-1698 / 4.5-8
+* gigabyte/ga-b75m-d3v          4.4-1757
+* google/peppy                  4.4-1882
+* lenovo/g505s                  4.4-1739
+* lenovo/x201                   4.4-1886
+* lenovo/x220                   4.4-1746 / 4.5-17
+
+coreboot statistics
+-------------------
+* Total Commits:            1889
+* Average Commits per day: 10.92
+* Total authors:             119
+* New authors:                47
+* Total Reviewers:            67
+* Total Submitters:           19
+* Total lines added:      164950
+* Total lines removed:   -182737
+* Total difference:       -17787
diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md
diff --git a/Documentation/releases/coreboot-4.7-relnotes.md b/Documentation/releases/coreboot-4.7-relnotes.md
@@ -0,0 +1,197 @@
+coreboot 4.7 release notes
+==========================
+
+The 4.7 release covers commit 0a4a4f7ae4 to commit fd470f7163
+Since the last release in April 2017, the coreboot project had 2573 commits by 150 authors.
+
+There is a pgp signed 4.7 tag in the git repository, and a branch will be created as needed.
+
+
+New chipsets
+------------
+
+* AMD Stoney Ridge
+* Intel i82801jx Southbridge (ICH10)
+* Intel Denverton and Denverton-NS
+* Work has started on Intel Cannon Lake
+
+Added 47 mainboards & variants:
+-------------------
+
+* Acer Chromebook 14 CB3-431 [google/edgar]           Intel Braswell
+* Acer Chromebook 15 CB3-532 [google/banon]           Intel Braswell
+* Acer Chromebook N7 C731 [google/relm]               Intel Braswell
+* ASRock B75 Pro3-M                                   Intel Ivy Bridge
+* ASRock G41C-GS R2.0                                 Intel G41/ICH7
+* Asus AM1I-A                                         AMD Kabini
+* Asus Chromebook C202SA/C300SA/C301SA (google/terra) Intel Braswell
+* Biostar A68N-5200                                   AMD Kabini
+* Compulab Intense-PC                                 Intel Ivy Bridge
+* Dell Chromebook 11 3180/3189 (google/kefka)         Intel Braswell
+* Foxconn G41S-K                                      Intel G41/ICH7
+* Google Coral                                        Intel Apollo Lake
+* Google Grunt                                        AMD Stoney Ridge
+* Google Kahlee                                       AMD Stoney Ridge
+* Google Meowth                                       Intel Cannon Lake
+* Google Nami                                         Intel Kaby Lake
+* Google Nautilus                                     Intel Kaby Lake
+* Google Nefario                                      Rockchip RK3399
+* Google Rainier                                      Rockchip RK3399
+* Google Soraka                                       Intel Kaby Lake
+* Google Zoombini                                     Intel Cannon Lake
+* HP Chromebook 11 G5 (google/setzer)                 Intel Braswell
+* HP EliteBook 2570p                                  Intel Ivy Bridge
+* HP EliteBook 2760p                                  Intel Sandy Bridge
+* HP EliteBook 8460p                                  Intel Sandy Bridge
+* HP EliteBook 8470p                                  Intel Ivy Bridge
+* HP EliteBook Revolve 810 G1                         Intel Ivy Bridge
+* Intel Cannnlake RVPU                                Intel Cannon Lake
+* Intel Cannonlake RVPY                               Intel Cannon Lake
+* Intel D410PT                                        Intel Atom D410
+* Intel DG43GT                                        Intel G43/ICH10
+* Intel GLKRVP                                        Intel Gemini Lake
+* Intel Harcuvar                                      Intel Denverton
+* Intel NUC DCP847SKE                                 Intel Sandy Bridge
+* Intel Saddle Brook reference board                  Intel Skylake
+* Lenovo N22/N42 Chromebook (google/reks)             Intel Braswell
+* Lenovo T430                                         Intel Ivy Bridge
+* Lenovo Thinkpad 11e/Yoga Chromebook G3
+  (google/ultima)                                     Intel Braswell
+* Lenovo ThinkPad X131e                               Intel Sandy Bridge
+* Lenovo Z61T                                         Intel i945/ICH7
+* PC Engines APU3                                     AMD Steppe Eagle
+* PC Engines APU4                                     AMD Steppe Eagle
+* PC Engines APU5                                     AMD Steppe Eagle
+* Purism Librem 13 v2                                 Intel Skylake
+* Purism Librem 15 v3                                 Intel Skylake
+* Samsung Chromebook 3 (google/celes)                 Intel Braswell
+* White label Chromebook (google/wizpig)              Intel Braswell
+* WinNET G170                                         VIA CN700
+
+Removed 2 mainboards
+--------------
+
+* Biferos Bifferboard
+* Google Cosmos
+
+New Embedded Controller
+-----------------------
+
+* KBC1126 used in HP EliteBooks
+
+General changes
+---------------
+
+* Integrate me_cleaner
+* Add flashconsole implementation
+* Build Tianocore UEFI payload from upstream source
+* Remove CMOS NVRAM configurable baud rates
+* A common mrc_cache driver to store romstage settings in SPI flash
+
+Google ChromeOS devices:
+------------------------
+
+* Add ACPI USB port definitions for many boards
+* Fix preprocessor guards for LPC TPM
+* Remove non-existent IRQ for LPC TPM
+* Fix LED control for mccloud
+* Enable keyboard backlight at boot on equipped boards
+* Fix ACPI data for non-google EC's to improve Windows compatibility
+* Add missing SPD files for chell, fixing support for > 4GB boards
+
+Lenovo Thinkpads:
+-----------------
+
+* Add support for passive cooling
+* Add ACPI fan control
+* Add BDC detection and power saving
+* Unify hybrid graphics and improved power saving
+
+Intel Braswell:
+---------------
+
+* Add support for all outstanding Braswell ChromeOS devices
+* Update FSP 1.1 header to v1.1.7.0
+* Adjust FSP header revision check to be less stringent
+* Upstream numerous commits from Chromium tree
+* Fix ACPI scope for I2C devices
+* Fix SPI write after flash lockdown set
+
+Legacy Intel Boards:
+--------------------
+
+* Unify Intel VBT handling
+* Add support for loading external VBT
+* Provide the VBT through Intel OpRegion method on all platforms
+* Fix low memory corruption on S3 resume path
+
+Intel Sandy Bridge:
+------------------
+
+* Add a Kconfig option to ignore XMP max DIMMs
+* Add Kconfig option for max. DRAM frequency fuses
+* Advertise correct DRAM frequency on Ivy Bridge
+* Improve CAS/frequency selection
+* Use command rate 2T on channels with two DIMMs installed for improved
+stability
+
+Intel X4X:
+----------
+
+* Fix booting with FSB800 DDR667 combination
+* Rework ram DQS receiver enable training sequence
+* Rework and fix SPD reading and decoding
+* Allow external GPU to take VGA cycles
+
+Intel GM45:
+-----------
+
+* Improve compatibility with mixed DIMMs
+* Add romstage timings
+* Set the display backlight PWM correctly
+
+Intel Pineview:
+---------------
+
+* Enable remapping of memory to allow for 4G or more memory
+
+Intel I440BX
+------------
+
+* Implement early CBMEM support
+* Fix RAM init programming
+
+AMD AGESA
+---------
+
+* Move boards to early CBMEM and add timestamps
+* Refactor boards away from using agesawrapper
+* Wipe unused sources under vendorcode
+* Re-enable ACPI S3 after fixing low memory corruptions
+
+AMD binaryPI
+------------
+
+* Move boards to early CBMEM
+* Continue work on cleaning up headers
+
+libgfxinit
+----------
+
+* Support new hardware: Broxton/APL (DP and HDMI only), Skylake
+* Handle framebuffer mapping in the library
+* Make DP training more compatible and tolerant
+* Enhance compatibility for VGA adaptors
+
+intelmetool
+-----------
+
+* Add support for Sunrise Point LP
+* Add Intel Boot Guard detection
+
+Toolchain
+---------
+
+* buildgcc now verifies downloaded files against hashes
+* Improve GNAT detection
+* Update binutils to 2.29.1
diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md
@@ -0,0 +1,179 @@
+coreboot 4.8 & 4.8.1 release notes
+==================================
+
+The 4.8.1 release contains 2 commits: 5f0b80b880 and 6794ce02d4.  This
+minor release fixes an issue with adding payloads. The 4.8 release
+covers commit 6dd2f69878 to commit ebdeb4d07d
+
+Since the last release, the coreboot project had 1198 commits by 124
+authors.
+
+There are PGP signed 4.8 and 4.8.1 tags in the git repository.  A branch
+for 4.8 releases (4.8_branch) has been created.
+
+A big thank you to everyone involved in making this release happen. We
+couldn't have done this without the 35 new commit authors, the
+experienced developers, the many reviewers, documentation writers and
+the fantastic community supporting users on both the mailing list and
+the IRC channel.
+
+In general, this has been a calm release cycle. Several old devices were
+removed from the master branch early in the release, as they hinder
+development and nobody stepped up doing the porting effort or was
+willing to test coreboot on them. If there is the desire to get a board
+back, it isn't lost as it’s still in the git history.
+
+Intel i945 platform
+-------------------
+* On Intel 945 devices, native graphics initialization is now skipped
+saving around 100 ms during resume from S3. The OS drivers need to be
+able to handle that. Linux’ i915 driver is able to handle it, but not
+the frame buffer driver.
+
+AMD Stoney Ridge
+----------------------------------
+* Significant cleanup from older AGESA based platforms
+* Fixes to get S3 working
+* Updates to GPIO code to match other modern coreboot chips
+* AGESA interface cleanup - Use native coreboot functions when
+possible
+
+Lenovo mainboards
+-----------------
+* Started integration of VBT (Video Bios Table) binary files to
+support native graphics initialisation
+
+Internal changes
+----------------
+* Rename of payload type 'payload' to 'simple_elf'
+* Progress in removing typedef device_t
+* Migrated all Intel platforms to a common VBT codebase
+* Ongoing cleanup of whitespace, spelling and formatting
+* Support for PCI in ramstage on non-x86
+* Ongoing Intel platform code deduplication
+
+Console changes
+---------------
+* Reduce default loglevel to DEBUG
+* Introduce a way for mainboard to override the loglevel
+* Restrict console messages to after console initialization
+
+Fixed Bugs
+----------
+* qemu-i440fx: Fix ACPI checksum corruption
+* intelmetool: Fix crash, support ME11+ platforms, fix bootguard
+detection
+* tpm: Fix TPM software stack vulnerability in tlcl_read() for TPM 1.2 (https://github.com/nccgroup/TPMGenie)
+* asrock/b75pro3-m: Fixed HDMI
+* Intel/ibexpeak: Fix missing ACPI PIRQ entries
+* Intel/nehalem: Fix freeze during chipset lockdown
+
+Payloads
+--------
+* Bumped SeaBIOS to 1.11.1
+* Improved TianoCore integration
+
+Security
+--------
+* Start of refactoring the TPM software stack
+* Introduced coreboot security section in kconfig
+* VBoot & TPM code moved into src/security
+
+Intelmetool
+-----------
+* Add Intel Boot Guard status support
+
+Documentation
+-------------
+* Switch from Hugo to Sphinx for the Documentation
+* Working on markdown documentation for https://doc.coreboot.org
+
+Added 17 mainboards
+-------------------
+* Asus MAXIMUS_IV_GENE_Z                               Intel Sandybridge
+* Google ATLAS                                         Intel Kabylake
+* Google BIP                                           Intel Geminilake
+* Google CHEZA                                         Qualcomm SDM845
+* Google NOCTURNE                                      Intel Kabylake
+* Google OCTOPUS                                       Intel Geminilake
+* Google PHASER                                        Intel Geminilake
+* Google YORP                                          Intel Geminilake
+* HP 8770W                                             Intel Ivybridge
+* HP FOLIO_9470M                                       Intel Ivybridge
+* Intel KBLRVP8                                        Intel Skylake
+* Lenovo W520                                          Intel Sandybridge
+* OCP MONOLAKE                                         Intel Broadwell DE
+* OCP WEDGE100S                                        Intel Broadwell DE
+* Purism Librem 15 v2                                  Intel Broadwell
+* Scaleway TAGADA                                      Intel Denverton
+* SiFive HIFIVE_UNLEASHED                              SiFive FU540
+
+Removed 39 mainboards
+---------------------
+* Abit BE6_II_V2_0
+* AMD DINAR
+* AMD RUMBA
+* Asus DSBF
+* Asus MEW_AM
+* Asus MEW_VM
+* A-trend ATC_6220
+* A-trend ATC_6240
+* AZZA PT_6IBD
+* Biostar M6TBA
+* Compaq DESKPRO_EN_SFF_P600
+* DMP EX
+* ECS P6IWP_FE
+* Gigabyte GA_6BXC
+* Gigabyte GA_6BXE
+* HP E_VECTRA_P2706T
+* Intel D810E2CB
+* Intel EAGLEHEIGHTS
+* Intel MTARVON
+* Intel TRUXTON
+* Iwave RAINBOW_G6
+* Lanner EM8510
+* Lippert FRONTRUNNER
+* Mitac 6513WU
+* MSI MS_6119
+* MSI MS_6147
+* MSI MS_6156
+* MSI MS_6178
+* NEC POWERMATE_2000
+* Nokia IP530
+* RCA RM4100
+* Soyo SY_6BA_PLUS_III
+* Supermicro H8QGI
+* Supermicro H8SCM
+* Supermicro X7DB8
+* Thomson IP1000
+* Tyan S1846
+* Tyan S8226
+* Wyse S50
+
+Added 2 socs
+------------
+* Qualcomm sdm845
+* SiFive fu540
+
+Removed 2 socs
+--------------
+* DMP vortex86ex
+* Intel sch
+
+Removed 5 processors
+--------------------
+* AMD agesa-family15
+* AMD geode-gx2
+* Intel ep80579
+* Intel model-f0x
+* Intel model-f1x
+
+Statistics
+----------
+* Total commits: 1198
+* Average Commits per day: 9.85
+* Total authors: 124
+* New authors: 35
+* Total lines added: 386113
+* Total lines removed: 291201
+* Total lines difference: 94912
diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md
@@ -0,0 +1,30 @@
+coreboot 4.9 release notes
+==========================
+
+The 4.9 release is planned for November 2018
+
+Update this document with changes that should be in the release
+notes.
+* Please use Markdown.
+* See the [4.7](coreboot-4.7-relnotes.md) and [4.8](coreboot-4.8.1-relnotes.md)
+ release notes for the general format.
+* The chip and board additions and removals will be updated right
+before the release, so those do not need to be added.
+
+
+
+General changes
+---------------
+
+* Various code cleanups
+ * Removed `device_t` in favor of `struct device*` in ramstage code
+ * Improve adherence to coding style
+* Expand use of the postcar stage
+* Add bootblock compression capability: on systems that copy the bootblock
+  from very slow flash to ERAM, allow adding a stub that decompresses the
+  bootblock into ERAM to minimize the amount of flash reads
+
+Toolchain
+---------
+
+* Update IASL to version 10280531
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -0,0 +1,16 @@
+Release notes for previous releases
+===================================
+
+### * [4.1 - July 2015](coreboot-4.1-relnotes.md)
+### * [4.2 - October 2015](coreboot-4.2-relnotes.md)
+### * [4.3 - January 2016](coreboot-4.3-relnotes.md)
+### * [4.4 - May 2016](coreboot-4.4-relnotes.md)
+### * [4.5 - October 2016](coreboot-4.5-relnotes.md)
+### * [4.6 - April 2017](coreboot-4.6-relnotes.md)
+### * [4.7 - January 2018](coreboot-4.7-relnotes.md)
+### * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+
+Upcoming release
+----------------
+### * [4.9 - November 2018](coreboot-4.9-relnotes.md)
+Please add to the release notes as changes are added:
diff --git a/Documentation/soc/cavium/bootflow.md b/Documentation/soc/cavium/bootflow.md
@@ -0,0 +1,19 @@
+# Cavium bootflow
+
+The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller.
+It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get
+the position of the bootstage in flash. It then loads 192KiB from flash into
+L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as
+the signature of the bootstage isn't verified.
+The **BOOTROM** can do AES decryption for obfuscation or verify the signature
+of the bootstage. Both features aren't used and won't be described any further.
+
+* The typical position of bootstage in flash is at address **0x20000**.
+* The entry point in physical DRAM is at address **0x100000**.
+
+## Layout
+
+![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow]
+
+[cavium_bootflow]: cavium_bootflow.png
+
diff --git a/Documentation/soc/cavium/cavium_bootflow.png b/Documentation/soc/cavium/cavium_bootflow.png
diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md
@@ -0,0 +1,119 @@
+# Cavium CN81xx documentation
+
+## Reference code
+
+```eval_rst
+The Cavium reference code is called `BDK`_ (board development kit) and is part
+of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot.
+```
+
+## SOC code
+
+The SOC folder contains functions for:
+* TWSI
+* UART
+* TIMER
+* SPI
+* MMU
+* DRAM
+* CLOCK
+* GPIO
+* Secondary CPUs
+* PCI
+
+All other hardware is initilized by the BDK code, which is invoked from
+ramstage.
+
+## Notes about the hardware
+
+Cavium SoC do **not** have embedded SRAM. The **BOOTROM** setups the
+L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed
+location. It then jumps to the firmware.
+
+```eval_rst
+For more details have a look at `Cavium CN8XXX Bootflow`_.
+```
+
+## CAR setup
+
+For Cache-as-RAM we only need to lock the cachelines which are used by bootblock
+or romstage until DRAM has been set up. At the end of romstage the cachelines
+are unlocked and the contents are flushed to DRAM.
+Locked cachelines are never evicted.
+
+The CAR setup is done in '''bootblock_custom.S''' and thus doesn't use the common
+aarch64 '''bootblock.S''' code.
+
+## DRAM setup
+
+```eval_rst
+The DRAM setup is done by the `BDK`_.
+```
+
+## PCI setup
+
+The PCI setup is done using the MMCONF mechanism.
+Besides configuring device visibility (secure/unsecure) the MSI-X interrupts
+needs to be configured.
+
+## Devicetree patching
+
+The Linux devicetree needs to be patched, depending on the available hardware
+and their configuration. Some values depends on fuses, some on user selectable
+configuration.
+
+The following SoC specific fixes are made:
+
+1. Fix SCLK
+2. Fix UUA refclock
+3. Remove unused PEM entries
+4. Remove unused QLM entries
+5. Set local MAC address
+
+## CN81xx quirks
+
+The CN81xx needs some quirks that are not documented or hidden in the code.
+
+### Violation of PCI spec
+
+**Problem:**
+
+* The PCI device 01:01.0 is disabled, but a multifunction device.
+* The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot
+  PCI allocator.
+
+**Solution:**
+
+The PCI Bus 0 and 1 are scanned manually in SOC's PCI code.
+
+
+### Crash accessing SLI memory
+
+**Problem:**
+
+The SLI memory region decodes to attached PCIe devices.
+Accessing the memory region results in 'Data Abort Exception' if the link of the
+PCIe device never had been enabled.
+
+**Solution:**
+
+Enable the PCIe link at least once. (You can disabling the link and the SLI
+memory reads as 0xffffffff.)
+
+
+### RNG Data Abort Exception
+
+**Problem:**
+
+'Data Abort Exception' on accessing the enabled RNG.
+
+**Solution**:
+
+Read the BDK_RNM_CTL_STATUS register at least once after writing it.
+
+
+```eval_rst
+.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
+.. _Cavium CN8XXX Bootflow: ../bootflow.html
+.. _BDK: ../../../vendorcode/cavium/bdk.html
+```
diff --git a/Documentation/soc/cavium/index.md b/Documentation/soc/cavium/index.md
@@ -0,0 +1,8 @@
+# Cavium SOC-specific documentation
+
+This section contains documentation about coreboot on specific Cavium SOCs.
+
+## Platforms
+
+- [CN81xx series](cn81xx/index.md)
+- [CN8xxx bootflow](bootflow.md)
diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md
@@ -0,0 +1,8 @@
+# SOC-specific documentation
+
+This section contains documentation about coreboot on specific SOCs.
+
+## Vendor
+
+- [Cavium](cavium/index.md)
+- [Intel](intel/index.md)
diff --git a/Documentation/soc/intel/code_development_model/code_development_model.md b/Documentation/soc/intel/code_development_model/code_development_model.md
@@ -0,0 +1,101 @@
+# Intel common code development strategy
+
+## Introduction
+
+This document captures the development strategy for Intel SOC code development
+of coreboot. As Intel keeps advancing hardware development and as new generation
+SoCs are developed, we need to add support for these SOCs into coreboot.
+
+We add this support inside the “soc/intel/soc_name” folder. This folder contains
+all the files which are related to a particular SoC.
+
+While there might be still duplicated code lying across SoCs, this document
+captures our efforts of putting as much code into shared directories across all
+Intel SoCs and of what can't be put into common code due to the possibility of
+future changes.
+
+## Design principal
+
+Any Intel coreboot project can be split into 3 parts:
+1. SoC = contains all the IP/component initialization code
+2. Mainboard = OEM/Reference boards, build based on underlying SoC support
+3. FSP = Intel firmware support package to abstract all restricted SoC registers
+from the open source code.
+
+Historically, we used to copy "X-1" generation SoC code into "X" new SoC while
+adding support for the new SoC. This resulted in having duplicated
+initialization code in both projects. This method increased redundant code
+across multiple SoCs and also it increased overhead for reviewers and
+maintainers.
+
+To solve this issue, we started following the converged IP model. The Intel
+silicon team uses the same IP/controller across various Intel SoCs. For example,
+the LPSS based UART controller is the same across all SoC products. Thus the
+"converged IP model" was propsed as the new firmware development model to create
+a common IP library across multiple SoC products and create BIOS/firmware for
+future SoCs. This will make development much simpler by using those common APIs
+based on the different configurations.
+
+## Common Code Development and Status
+
+Intel's proposed "converged IP model", also called as "common code phase 1.0",
+has reduced the number of lines of code in a single SoC folder by over 50%.
+
+We continue to analyze the code to see what can still be moved to common and try
+to reduce the footprint of the code in each SoC folder. With the current Intel
+SoC development model,the PCH has been made into a separate component for the
+big core SoCs. Intel hardware design has started following the model where the
+same PCH is used across multiple SoCs, which gives us an opportunity to make
+code more common across SoCs which use the same PCH. As part of this idea,
+common code phase 1.1 has emerged and we will try to create PCH binding for SoCs
+and thus further reduce the footprint of SoC code.
+
+Common code phase 1.1 will make code more modular for big core SoCs but there
+is still some scope to make code flow common across small core and big core
+SoCs. We will take this up as a part of common code phase 2.0 and make code flow
+common across small core and big core SoCs which will again help us to reduce
+the footprint of code as well as have a more unified code flow for all Intel
+SoCs.
+
+Here's a table which summarizes common code phase and status:
+```eval_rst
++----------------+---------------------------------------------+--------------+
+|   Common code  |           summary                           |   status     |
+|     phase      |                                             |              |
++================+=============================================+==============+
+|     1.0        |follow "converged IP model" as described     |Majority of   |
+|                |above and create common IP code which can be |the code is   |
+|                |used across multiple socs                    |common now.   |
+|                |                                             |A few patches |
+|                |                                             |are in review |
++----------------+---------------------------------------------+--------------+
+|     1.1        |Create PCH binding for big core SoCs. SoCs   |In development|
+|                |having same PCH can use common code.         |Base patch    |
+|                |                                             |merged        |
++----------------+---------------------------------------------+--------------+
+|     2.0        |Use common stage files (bootblock, romstage) |In development|
+|                |across small core and big core SoCs. This    |              |
+|                |will unify flow for all Intel SoCs.          |              |
++----------------+---------------------------------------------+--------------+
+```
+## Common code structure
+
+Code design after common code in coreboot will look as follows:
+
+**coreboot common code structure**
+![coreboot_common_code_structure][coreboot_common_code_design]
+
+[coreboot_common_code_design]: coreboot_common_code_design.png
+
+There will be still some duplicated files left in each SOC folder and we may
+copy across a SOC as a base but these files are subject to change as
+development continues.
+
+## Benefits
+
+1. coreboot will have less redundant code which is spread across multiple SOCs
+as of now.
+2. Design will be easier to understand by the community since code flow will be
+the same for all the Intel SoCs.
+3. Since we are aligning the software code design with the hardware philosophy,
+it will be easier to map why each change was done in code/SOC.
diff --git a/Documentation/soc/intel/code_development_model/coreboot_common_code_design.png b/Documentation/soc/intel/code_development_model/coreboot_common_code_design.png
diff --git a/.../MultiProcessorInit/MultiProcessorInit.md → ...n/soc/intel/icelake/MultiProcessorInit.md b/.../MultiProcessorInit/MultiProcessorInit.md → ...n/soc/intel/icelake/MultiProcessorInit.md
diff --git a/...rInit/coreboot_publish_mp_service_api.png → ...elake/coreboot_publish_mp_service_api.png b/...rInit/coreboot_publish_mp_service_api.png → ...elake/coreboot_publish_mp_service_api.png
diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md
@@ -0,0 +1,7 @@
+# Intel Ice Lake SOC-specific documentation
+
+This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
+
+## Multiprocessor Init
+
+- [Multiprocessor Init](MultiProcessorInit.md)
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
@@ -0,0 +1,7 @@
+# Intel SOC-specific documentation
+
+This section contains documentation about coreboot on specific Intel SOCs.
+
+## Platforms
+
+- [Ice Lake/9th Gen Core-i series](icelake/index.md)
diff --git a/Documentation/vendorcode/cavium/bdk.md b/Documentation/vendorcode/cavium/bdk.md
@@ -0,0 +1,30 @@
+# Cavium's BDK
+
+## BDK
+A part of Cavium's BDK can be found in '''src/vendorcode/cavium/bdk'''.
+It does the **DRAM init** in romstage and the **PCIe**, **QLM**, **SLI**,
+**PHY**, **BGX**, **SATA** init in ramstage.
+
+## Devicetree
+The BDK does use it's own devicetree, as coreboot's devicetree isn't
+compatible. The devicetree stores key-value pairs (see **bdk-devicetree.h**
+for implementation details), where the key and the value are stored as strings.
+
+The key-value pairs must be advertised in romstage and ramstage using the
+'''bdk_config_set_fdt()''' method.
+
+The tool '''util/cavium/devicetree_convert.py''' can be used to convert a
+devicetree to a key-value array.
+
+## Modifications
+
+* The BDK has been modified to compile under coreboot's toolchain.
+* Removed FDT devicetree support.
+* Dropped files that aren't required for SoC bringup
+* Added Kconfig values for verbose console output
+
+## Debugging
+
+You can enable verbose console output in *menuconfig*:
+
+Go to **Chipset**, **BDK** and enable one or multiple stages.
diff --git a/Documentation/vendorcode/cavium/index.md b/Documentation/vendorcode/cavium/index.md
@@ -0,0 +1,8 @@
+# Cavium vendorcode-specific documentation
+
+This section contains documentation about coreboot on Cavium specific
+vendorcode.
+
+## Sections
+
+- [BDK](bdk.md)
diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md
@@ -0,0 +1,7 @@
+# Vendorcode-specific documentation
+
+This section contains documentation about coreboot on specific vendorcode.
+
+## Vendor
+
+- [Cavium](cavium/index.md)
diff --git a/Makefile.inc b/Makefile.inc
@@ -25,6 +25,7 @@ endif
 CONFIG_CBFS_PREFIX:=$(call strip_quotes,$(CONFIG_CBFS_PREFIX))
 CONFIG_FMDFILE:=$(call strip_quotes,$(CONFIG_FMDFILE))
 CONFIG_DEVICETREE:=$(call strip_quotes, $(CONFIG_DEVICETREE))
+CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE))
 
 #######################################################################
 # misleadingly named, this is the coreboot version
@@ -154,29 +155,19 @@ ws_to_under=$(shell echo '$1' | tr ' \t' '_')
 # Helper functions for ramstage postprocess
 spc :=
 spc +=
-$(spc) :=
-$(spc) +=
 comma := ,
 
-# files-in-dir-recursive,dir,files
-files-in-dir-recursive=$(filter $(1)%,$(2))
+# Returns all files and dirs below `dir` (recursively).
+# files-below-dir,dir,files
+files-below-dir=$(filter $(1)%,$(2))
 
-# parent-dir,dir/
-parent-dir=$(dir $(if $(patsubst /%,,$(1)),,/)$(subst $( ),/,$(strip $(subst /, ,$(1)))))
-
-# filters out exactly the directory specified
-# filter-out-dir,dir_to_keep,dirs
-filter-out-dir=$(filter-out $(1),$(2))
-
-# filters out dir_to_keep and all its parents
-# filter-out-dirs,dir_to_keep,dirs
-filter-out-dirs=$(if $(filter-out ./ /,$(1)),$(call filter-out-dirs,$(call parent-dir,$(1)),$(call filter-out-dir,$(1),$(2))),$(call filter-out-dir,$(1),$(2)))
-
-# dir-wildcards,dirs
-dir-wildcards=$(addsuffix %,$(1))
+# Returns all dirs below `dir` (recursively).
+# dirs-below-dir,dir,files
+dirs-below-dir=$(filter-out $(1),$(sort $(dir $(call files-below-dir,$(1),$(2)))))
 
+# Returns all files directly in `dir` (non-recursively).
 # files-in-dir,dir,files
-files-in-dir=$(filter-out $(call dir-wildcards,$(call filter-out-dirs,$(1),$(sort $(dir $(2))))),$(call files-in-dir-recursive,$(1),$(2)))
+files-in-dir=$(filter-out $(addsuffix %,$(call dirs-below-dir,$(1),$(2))),$(call files-below-dir,$(1),$(2)))
 
 #######################################################################
 # reduce command line length by linking the objects of each
@@ -391,11 +382,15 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
 CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time
-CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
-CFLAGS_common += -fno-delete-null-pointer-checks -fconserve-stack
+CFLAGS_common += -Wno-packed-not-aligned
+CFLAGS_common += -fno-delete-null-pointer-checks
+# Don't add these GCC specific flags when running scan-build
+ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
+CFLAGS_common += -fconserve-stack
+endif
 endif
 
 ADAFLAGS_common += -gnatp
@@ -554,12 +549,19 @@ $(obj)/config.h: $(objutil)/kconfig/conf
 # needed objects that every mainboard uses
 # Creation of these is architecture and mainboard independent
 DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_DEVICETREE)
+
+ifneq ($(CONFIG_OVERRIDE_DEVICETREE),)
+
+OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_DEVICETREE)
+
+endif
+
 DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c
 
-$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(objutil)/sconfig/sconfig
+$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig
 	@printf "    SCONFIG    $(subst $(src)/,,$(<))\n"
 	mkdir -p $(dir $(DEVICETREE_STATIC_C))
-	$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C)
+	$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE)
 
 ramstage-y+=$(DEVICETREE_STATIC_C)
 romstage-y+=$(DEVICETREE_STATIC_C)

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -9,6 +9,7 @@ CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="10ec,8168"
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -6,6 +6,7 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,157b"
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -4,6 +4,7 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,1539"
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -4,6 +4,7 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,1539"
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -4,6 +4,7 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_PXE_ROM_ID="8086,1539"
+# CONFIG_PXE_SERIAL_CONSOLE is not set
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y

diff --git a/payloads/Kconfig b/payloads/Kconfig
@@ -8,6 +8,17 @@ choice
 	default PAYLOAD_NONE if NO_DEFAULT_PAYLOAD || !ARCH_X86
 	default PAYLOAD_SEABIOS if ARCH_X86
 
+config PAYLOAD_FIT
+	bool "A FIT payload"
+	select PAYLOAD_FIT_SUPPORT
+	help
+	  Select this option if you have a payload image (a FIT file) which
+	  coreboot should run as soon as the basic hardware initialization
+	  is completed.
+
+	  You will be able to specify the location and file name of the
+	  payload image later.
+
 config PAYLOAD_NONE
 	bool "None"
 	help
@@ -44,15 +55,16 @@ source "payloads/bayou/Kconfig"
 
 config PAYLOAD_FILE
 	string "Payload path and filename"
-	depends on PAYLOAD_ELF
-	default "payload.elf"
+	depends on PAYLOAD_ELF || PAYLOAD_FIT
+	default "payload.elf" if PAYLOAD_ELF
+	default "uImage" if PAYLOAD_FIT
 	help
 	  The path and filename of the ELF executable file to use as payload.
 
 choice
 	prompt "Payload compression algorithm"
 	default COMPRESSED_PAYLOAD_LZMA
-	depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
+	depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT
 	help
 	  Choose the compression algorithm for the chosen payloads.
 	  You can choose between LZMA and LZ4.
@@ -82,6 +94,16 @@ config PAYLOAD_IS_FLAT_BINARY
 	  Add the payload to cbfs as a flat binary type instead of as an
 	  elf payload
 
+config PAYLOAD_FIT_SUPPORT
+	bool "FIT support"
+	default n
+	default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64)
+	select FLATTENED_DEVICE_TREE
+	help
+	  Select this option if your payload is of type FIT.
+	  Enables FIT parser and devicetree patching. The FIT is non
+	  self-extracting and needs to have a compatible compression format.
+
 config COMPRESS_SECONDARY_PAYLOAD
 	bool "Use LZMA compression for secondary payloads"
 	default y

diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
@@ -37,6 +37,7 @@ payloads/external/sortbootorder \
 payloads/external/sgabios \
 payloads/external/tianocore \
 payloads/external/GRUB2 \
+payloads/external/LinuxBoot \
 
 payloads/coreinfo/build/coreinfo.elf coreinfo:
 	$(MAKE) -C payloads/coreinfo defaultbuild

diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c
@@ -29,6 +29,7 @@
 #define COMPONENT_CBFSHEADER	0x02
 #define COMPONENT_STAGE		0x10
 #define COMPONENT_SELF		0x20
+#define COMPONENT_FIT		0x21
 #define COMPONENT_OPTIONROM	0x30
 #define COMPONENT_RAW		0x50
 #define COMPONENT_MICROCODE	0x53
@@ -190,6 +191,9 @@ static int cbfs_module_redraw(WINDOW * win)
 	case COMPONENT_SELF:
 		mvwprintw(win, row++, 38, "simple ELF");
 		break;
+	case COMPONENT_FIT:
+		mvwprintw(win, row++, 38, "FIT");
+		break;
 	case COMPONENT_OPTIONROM:
 		mvwprintw(win, row++, 38, "optionrom");
 		break;