diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex
diff --git a/Documentation/community/services.md b/Documentation/community/services.md
@@ -0,0 +1,45 @@
+# Accounts on coreboot.org
+
+There are a number of places where you can benefit from creaating an account
+in our community. Since there is no single sign-on system in place (at this
+time), they come with their own setup routines.
+
+## Gerrit code review
+We exchange and review patches to the code using our [Gerrit code review
+system](https://review.coreboot.org).
+
+It allows logging in with a Google or GitHub account using OAuth2 as well
+as with any OpenID provider that you may already use.
+
+On the [settings screen](https://review.coreboot.org/settings) you can register
+all your email addresses you intend to use in the context of coreboot
+development so that commits with your email address in them are associated with
+you properly.
+
+### https push access
+When using the https URLs to git repositories, you can push with the "HTTP
+Credentials" you can have Gerrit generate for you on that page. By default,
+git uses `$HOME/.netrc` for http authentication data, so add a line there
+stating:
+
+    machine review.coreboot.org login $your-user-name password $your-password
+
+### Gerrit user avatar
+To setup an avatar to show in Gerrit, clone the avatars repository at
+https://review.coreboot.org/gerrit-avatars.git and add a file named
+$your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)).
+The image must be provided in JPEG format, must be square and have at most 50000
+bytes.
+
+After you push for review, the system will automatically verify your change
+and, if adhering to these constraints, approve it. You can then immediately
+submit it.
+
+## Issue tracker
+We have an [issue tracker](https://ticket.coreboot.org) that is used for
+coreboot and related code, such as libpayload, as well as for the project's
+infrastructure.
+
+It can be helpful to refer to issues we track there in commit messages:
+
+    Fixes: https://ticket.coreboot.org/issues/$id
diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md
@@ -1,6 +1,6 @@
 # coreboot architecture
 
-## Overwiew
+## Overview
 ![][architecture]
 
 [architecture]: comparision_coreboot_uefi.svg

diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md
@@ -46,11 +46,11 @@ clarification, see the Developer's Certificate of Origin in the coreboot
 * Let non-trivial patches sit in a review state for at least 24 hours
 before submission. Remember that there are coreboot developers in timezones
 all over the world, and everyone should have a chance to contribute.
-Trivial patches would be things like whitespace changes or spelling fixes.
-In general, small changes that don’t impact the final binary output. The
+Trivial patches would be things like whitespace changes or spelling fixes,
+in general those that don’t impact the final binary output. The
 24-hour period would start at submission, and would be restarted at any
 update which significantly changes any part of the patch. Patches can be
-'Fast-tracked' and submitted in under this 24 hour with the agreement of at
+'Fast-tracked' and submitted in under 24 hours with the agreement of at
 least 3 +2 votes.
 
 * Do not +2 patches that you authored or own, even for something as trivial

diff --git a/Documentation/Binary_Extraction.md → Documentation/ifdtool/binary_extraction.md b/Documentation/Binary_Extraction.md → Documentation/ifdtool/binary_extraction.md
diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md
@@ -0,0 +1,5 @@
+
+Contents:
+
+* [Intel IFD Binary Extraction](binary_extraction.md)
+* [IFD Layout](layout.md)
diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md
@@ -0,0 +1,66 @@
+# IFD Layout
+
+A coreboot image for an Intel SoC contains two separate definitions of the
+layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and
+sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md).
+
+The FMAP should define all of the of the regions defined by the IFD to ensure
+that those regions are accounted for by coreboot and will not be accidentally
+modified.
+
+## IFD mapping
+
+The names of the IFD regions in the FMAP should follow the convention of
+starting with the prefix `SI_` which stands for `silicon initialization` as a
+way to categorize anything required by the SoC but not provided by coreboot.
+
+|IFD Region index|IFD Region name|FMAP Name|Notes|
+|---|---|---|---|
+|0|Flash Descriptor|SI_DESC|Always the top 4KB of flash|
+|1|BIOS|SI_BIOS|This is the region that contains coreboot|
+|2|Intel ME|SI_ME||
+|3|Gigabit Ethernet|SI_GBE||
+|4|Platform Data|SI_PDR||
+|8|EC Firmware|SI_EC|Most Chrome OS devices do not use this region; EC firmware is stored BIOS region of flash|
+
+## Validation
+
+The ifdtool can be used to manipulate a firmware image with a IFD. This tool
+will not take into account the FMAP while modifying the image which can lead to
+unexpected and hard to debug issues with the firmware image. For example if the
+ME region is defined at 6 MB in the IFD but the FMAP only allocates 4 MB for the
+ME, then when the ME is added by the ifdtool 6 MB will be written which could
+overwrite 2 MB of the BIOS.
+
+In order to validate that the FMAP and the IFD are compatible the ifdtool
+provides --validate (-t) option. `ifdtool -t` will read both the IFD and the
+FMAP in the image and for every non empty region in the IFD if that region is
+defined in the FMAP but the offset or size is different then the tool will
+return an error.
+
+Example:
+
+```console
+foo@bar:~$ ifdtool -t bad_image.bin
+Region mismatch between bios and SI_BIOS
+ Descriptor region bios:
+  offset: 0x00400000
+  length: 0x01c00000
+ FMAP area SI_BIOS:
+  offset: 0x00800000
+  length: 0x01800000
+Region mismatch between me and SI_ME
+ Descriptor region me:
+  offset: 0x00103000
+  length: 0x002f9000
+ FMAP area SI_ME:
+  offset: 0x00103000
+  length: 0x006f9000
+Region mismatch between pd and SI_PDR
+ Descriptor region pd:
+  offset: 0x003fc000
+  length: 0x00004000
+ FMAP area SI_PDR:
+  offset: 0x007fc000
+  length: 0x00004000
+```
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -161,15 +161,15 @@ for example OpenBSD, is probably the closest cousin of our approach.
 Contents:
 
 * [Getting Started](getting_started/index.md)
-* [Rookie Guide](lessons/index.md)
+* [Tutorial](tutorial/index.md)
 * [Coding Style](coding_style.md)
 * [Project Ideas](contributing/project_ideas.md)
 * [Code of Conduct](community/code_of_conduct.md)
 * [Community forums](community/forums.md)
+* [Project services](community/services.md)
 * [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
-* [Intel IFD Binary Extraction](Binary_Extraction.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Adding devices to a device tree](acpi/devicetree.md)

diff --git a/Documentation/lessons/index.md b/Documentation/lessons/index.md
diff --git a/Documentation/mainboard/amd/padmelon/padmelon.jpg b/Documentation/mainboard/amd/padmelon/padmelon.jpg
diff --git a/Documentation/mainboard/amd/padmelon/padmelon.md b/Documentation/mainboard/amd/padmelon/padmelon.md
@@ -0,0 +1,80 @@
+# Padmelon board
+
+## Specs (with Merlin Falcon SOC)
+
+* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
+  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
+* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
+  code is specific for Merlin Falcon SOC. Some specs will change if not
+  using Merlin Falcon.
+* One half mini PCI-Express slot on back side of mainboard
+* One PCI Express® 3.0 x8 slot
+* Two SATA3 ports with 6Gb/s data transfer rate
+* Two USB 2.0 ports at rear panel
+* Two USB 3.0 ports at rear panel
+* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
+* 6-channel High-Definition audio from Realtek ALC662 codec
+* One soldered down SPI flash with dediprog header
+
+## Mainboard
+
+![mainboard][padmelon]
+
+Three items are marked in this picture
+1. dediprog header
+2. memory dimms, address 0xA0 and 0xA4
+3. SATA cables connected to motherboard
+
+## Back panel
+
+![back panel][padmelon_io]
+
+* The lower serial port is UART A (debug serial)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------------------+
+| Type                | Value              |
++=====================+====================+
+| Socketed flash      | no                 |
++---------------------+--------------------+
+| Model               | Macronix MX256435E |
++---------------------+--------------------+
+| Size                | 8 MiB              |
++---------------------+--------------------+
+| Flash programing    | dediprog header    |
++---------------------+--------------------+
+| Package             | SOIC-8             |
++---------------------+--------------------+
+| Write protection    | No                 |
++---------------------+--------------------+
+```
+
+## Technology
+
+```eval_rst
++---------------+------------------------------+
+| Fan control   | Using fintek F81803A         |
++---------------+------------------------------+
+| CPU           | Merlin Falcon (see reference)|
++---------------+------------------------------+
+```
+
+## Description of pictures within this document
+
+```eval_rst
++----------------------------+----------------------------------------+
+|padmelon.jpg                | Motherboard with components identified |
++----------------------------+----------------------------------------+
+|padmelon_io.jpg             | Back panel picture                     |
++----------------------------+----------------------------------------+
+```
+
+## Reference
+
+[Merlin Falcon BKDG][merlinfalcon]
+
+[merlinfalcon]: ../../../soc/amd/family15h.md
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg
diff --git a/Documentation/mainboard/amd/padmelon/padmelon_io.jpg b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -2,18 +2,21 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
+## AMD
+- [padmelon](amd/padmelon/padmelon.md)
+
+## ASRock
+
+- [H81M-HDS](asrock/h81m-hds.md)
+- [H110M-DVS](asrock/h110m-dvs.md)
+
 ## ASUS
 
 - [F2A85-M](asus/f2a85-m.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 
-## ASRock
-
-- [H81M-HDS](asrock/h81m-hds.md)
-- [H110M-DVS](asrock/h110m-dvs.md)
-
 ## Cavium
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
@@ -26,12 +29,6 @@ The boards in this section are not real mainboards, but emulators.
 - [Qemu RISC-V emulator](emulation/qemu-riscv.md)
 - [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
 
-## Intel
-
-- [DG43GT](intel/dg43gt.md)
-- [IceLake RVP](intel/icelake_rvp.md)
-- [KBLRVP11](intel/kblrvp11.md)
-
 ## Facebook
 
 - [FBG-1701](facebook/fbg1701.md)
@@ -48,11 +45,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Dragonegg](google/dragonegg.md)
 
-## Open Cellular
-
-- [Elgon](opencellular/elgon.md)
-- [Rotundu](opencellular/rotundu.md)
-
 ## HP
 
 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
@@ -63,17 +55,19 @@ The boards in this section are not real mainboards, but emulators.
 - [EliteBook common](hp/elitebook_series.md)
 - [EliteBook 8760w](hp/8760w.md)
 
+## Intel
+
+- [DG43GT](intel/dg43gt.md)
+- [IceLake RVP](intel/icelake_rvp.md)
+- [KBLRVP11](intel/kblrvp11.md)
+
 ## Lenovo
 
 - [Mainboard codenames](lenovo/codenames.md)
 - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
-## Portwell
-
-- [PQ7-M107](portwell/pq7-m107.md)
-
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)
@@ -92,17 +86,23 @@ The boards in this section are not real mainboards, but emulators.
 
 - [MS-7707](msi/ms7707/ms7707.md)
 
+## Open Cellular
+
+- [Elgon](opencellular/elgon.md)
+- [Rotundu](opencellular/rotundu.md)
+
 ## PC Engines
 
+- [APU1](pcengines/apu1.md)
 - [APU2](pcengines/apu2.md)
 
-## Roda
+## Portwell
 
-- [RK9 Flash Header](roda/rk9/flash_header.md)
+- [PQ7-M107](portwell/pq7-m107.md)
 
-## PC Engines
+## Roda
 
-- [APU1](pcengines/apu1.md)
+- [RK9 Flash Header](roda/rk9/flash_header.md)
 
 ## SiFive
 
@@ -111,7 +111,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Supermicro
 
 - [X10SLM+-F](supermicro/x10slm-f.md)
-- [X11SSH-TF](supermicro/x11ssh-tf.md)
+- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
 
 ## UP
 

diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md
@@ -12,7 +12,7 @@ Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
 
 ```eval_rst
 If you haven't already, build the coreboot toolchain as described in
-:doc:`../../lessons/lesson1`.
+:doc:`../../tutorial/part1`.
 ```
 
 A fully working image should be possible so long as you have the
@@ -135,7 +135,7 @@ for caveats.
   can't be used for temperature readings.
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, but the required driver doesn't exist
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS, and hence the OS can do fan control.

diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -0,0 +1,61 @@
+# X11 LGA1151 series
+
+The [Supermicro X11 LGA1151 series] are mostly the same boards with some minor differences in
+internal and external interfaces like available PCIe slots, NICs (1 GbE, 10 GbE), IPMI, RAID
+Controller etc.
+
+## Supported boards
+
+- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
+
+## Required proprietary blobs
+
+- [Intel FSP2.0]
+- Intel ME
+
+## De-blobbing
+
+- [Intel FSP2.0] can not be removed as long as there is no free replacement
+- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space)
+- Intel Ethernet Controller Firmware can be removed when it's extended functionality is not
+  needed. For more details refer to the respective datasheet (e.g 333016-008 for I210).
+- Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC]
+
+## Flashing coreboot
+
+Look at the [flashing tutorial] and the board-specific section.
+
+## Known issues
+
+These issues apply to all boards. Have a look at the board-specific issues, too.
+
+- Intel SGX causes secondary APs to crash (disabled for now) when HT is enabled (Fix is WIP CB:35312)
+- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
+
+## ToDo
+
+- Fix issues above
+- Fix issues in board specific sections
+- Fix TODOs mentioned in code
+- Add more boards! :-)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Kaby Lake                                  |
++------------------+--------------------------------------------------+
+| PCH              | Intel C232/C236                                  |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel SPS (server version of the ME)             |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+[Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
+[OpenBMC]: https://www.openbmc.org/
+[flashrom]: https://flashrom.org/Flashrom
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
@@ -0,0 +1,90 @@
+# Supermicro X11SSH-TF
+
+This section details how to run coreboot on the [Supermicro X11SSH-TF].
+
+## Flashing coreboot
+
+The board can be flashed externally using *some* programmers. The CH341 was found working, while
+Dediprog didn't detect the chip.
+
+The flash IC can be found between the two PCIe slots near the southbridge:
+![](x11ssh-tf_flash.jpg)
+
+## BMC (IPMI)
+
+This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides
+in a 32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This chip is an
+[MX25L25635F].
+
+## Tested and working
+
+- USB ports
+- Ethernet
+- SATA ports
+- RS232 external
+- ECC DRAM detection
+- PCIe slots
+- M.2 2280 NVMe slot
+- BMC (IPMI)
+- VGA on Aspeed
+- TPM on TPM expansion header
+
+## Known issues
+
+See general issue section.
+
+## ToDo
+
+- Fix TODOs mentioned in code
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Kaby Lake                                  |
++------------------+--------------------------------------------------+
+| PCH              | Intel C236                                       |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel SPS (server version of the ME)             |
++------------------+--------------------------------------------------+
+| Super I/O        | ASPEED AST2400                                   |
++------------------+--------------------------------------------------+
+| Ethernet         | 2x Intel® X550 10GBase-T Ethernet                |
+|                  | 1x dedicated BMC                                 |
++------------------+--------------------------------------------------+
+| PCIe slots       | 1x 3.0 x8                                        |
+|                  | 1x 3.0 x2 (in x4)                                |
+|                  | 1x 3.0 M.2 2260 x4 (Key M, with S-ATA)           |
++------------------+--------------------------------------------------+
+| USB slots        | 2x USB 2.0 (ext)                                 |
+|                  | 2x USB 3.0 (ext)                                 |
+|                  | 1x USB 3.0 (int)                                 |
+|                  | 1x dual USB 3.0 header                           |
+|                  | 2x dual USB 2.0 header                           |
++------------------+--------------------------------------------------+
+| SATA slots       | 8x SATA III                                      |
++------------------+--------------------------------------------------+
+| Other slots      | 1x RS232 (ext)                                   |
+|                  | 1x RS232 header                                  |
+|                  | 1x TPM header                                    |
+|                  | 1x Power SMB header                              |
+|                  | 6x PWM Fan connector                             |
+|                  | 2x I-SGPIO                                       |
+|                  | 2x S-ATA DOM Power connector                     |
+|                  | 1x XDP Port                                      |
+|                  | 1x External BMC I2C Header (for IPMI card)       |
+|                  | 1x Chassis Intrusion Header                      |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+- [Supermicro X11SSH-TF]
+- [Board manual]
+
+[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
+[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[IPMI]: ../../../../drivers/ipmi_kcs.md
+[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
+[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
diff --git a/...ion/mainboard/supermicro/x11ssh_flash.jpg → ...1151-series/x11ssh-tf/x11ssh-tf_flash.jpg b/...ion/mainboard/supermicro/x11ssh_flash.jpg → ...1151-series/x11ssh-tf/x11ssh-tf_flash.jpg
diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11ssh-tf.md
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -10,6 +10,7 @@ Release notes for previous releases
 * [4.7 - January 2018](coreboot-4.7-relnotes.md)
 * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
 * [4.9 - December 2018](coreboot-4.9-relnotes.md)
+* [4.10 - July 2019](coreboot-4.10-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -21,4 +22,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.10 - April 2019](coreboot-4.10-relnotes.md)
+* [4.11 - October 2019](coreboot-4.11-relnotes.md)
diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md
@@ -0,0 +1,49 @@
+# AMD Family 15h [SOC|Processors]
+
+## Abstract
+
+Family 15h is a line of AMD x86 products first introduced in 2011. The initial
+microarchitecture, codenamed "Bulldozer", introduced the concept of a "Compute
+Unit" (CU) where some parts of the processor are shared between two cores and
+some parts are unique for each core. Family 15h offerings matured into various
+models with increased performance and features targeting Enterprise, Client,
+and Embedded designs. Notice that a particular model can address more than one
+market(see models references below).
+
+## Introduction
+
+The first CU designs were 2 x86 cores with separate integer processors but
+sharing cache, code branch prediction engine and floating point processor. A die
+can have up to 8 CU. The floating point processor is composed of two symmetrical
+128-bit FMAC. Provided each x86 core is doing 128-bit floating point arithmetic,
+they both do floating point simultaneously. If one is doing 256-bit floating
+point, the other x86 core can't do floating point simultaneously. Later models
+changed how resources were shared, and introduced other performance improvements.
+
+Family 15h products range from SOCs to 3-chip solutions. Devices designed to
+contain on-die graphics (including headless) are commonly referred to as APUs,
+not CPUs.
+
+Later SOCs include a Platform Security Processor (PSP), a small ARM processor
+responsible for security related measures: For example, if secure boot is
+enabled, the cores will not exit reset until the BIOS image within the SPI
+flash is authenticated through its OEM signature, thus ensuring that only OEM
+produced BIOS can run the platform.
+
+Support in coreboot for modern AMD products is based on AMD’s reference code:
+AMD Generic Encapsulated Software Architecture (AGESA™). AGESA contains the
+code for enabling DRAM, configuring proprietary core logic, assistance with
+generating ACPI tables, and other features.
+
+While coreboot contains support for most models, some implementations use a
+separate cpu/north/south bridge directory structure. Newer products for models
+60h-6Fh (Merlin Falcon) and 70h-7Fh (Stoney Ridge) rely on modern SOC directory
+structure.
+
+## References
+
+1. [Models 00h-0Fh BKDG](https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf)
+2. [Models 10h-1Fh BKDG](https://www.amd.com/system/files/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf)
+3. [Models 30h-3Fh BKDG](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
+4. [Models 60h-6Fh BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf)
+5. [Models 70h-7Fh BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf)
diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md
@@ -4,5 +4,6 @@ This section contains documentation about coreboot on specific AMD SOCs.
 
 ## Technology
 
+- [Family 15h](family15h.md)
 - [Family 17h](family17h.md)
 
diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md
@@ -19,7 +19,7 @@ I/O range and ISA IRQ number.
 
 This example is based on AST2400.
 
-```code
+```
 # Add a "container" for proper ACPI code generation
 chip superio/common
   device pnp 2e.0 on # just for the base device, not for the LDNs

diff --git a/Documentation/tutorial/index.md b/Documentation/tutorial/index.md
@@ -0,0 +1,4 @@
+# Tutorial
+
+* [Part 1: Starting from scratch](part1.md)
+* [Part 2: Submitting a patch to coreboot.org](part2.md)
diff --git a/Documentation/lessons/lesson1.md → Documentation/tutorial/part1.md b/Documentation/lessons/lesson1.md → Documentation/tutorial/part1.md
@@ -1,5 +1,5 @@
-coreboot Lesson 1: Starting from scratch
-========================================
+Tutorial, part 1: Starting from scratch
+===========================================
 
 From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for
 a very basic build:

diff --git a/Documentation/lessons/lesson2.md → Documentation/tutorial/part2.md b/Documentation/lessons/lesson2.md → Documentation/tutorial/part2.md
@@ -1,4 +1,4 @@
-# coreboot Lesson 2: Submitting a patch to coreboot.org
+# Tutorial, part 2: Submitting a patch to coreboot.org
 
 ## Part 1: Setting up an account at coreboot.org
 

diff --git a/Documentation/util.md b/Documentation/util.md
@@ -47,7 +47,7 @@ Controller (EC). `C`
 * __genprof__ - Format function tracing logs `Bash` `C`
 * __gitconfig__ - Initialize git repository submodules install git
 hooks `Bash`
-* __ifdtool__ - Extract and dump Intel Firmware Descriptor information
+* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information
 `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`

diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md
@@ -5,3 +5,4 @@ This section contains documentation about coreboot on specific vendorcode.
 ## Vendor
 
 - [Cavium](cavium/index.md)
+- [Eltan](eltan/index.md)
diff --git a/Makefile b/Makefile
@@ -30,6 +30,9 @@
 ## SUCH DAMAGE.
 ##
 
+ifneq ($(words $(CURDIR)),1)
+    $(error Error: Path to the main directory cannot contain spaces)
+endif
 top := $(CURDIR)
 src := src
 srck := $(top)/util/kconfig
@@ -42,6 +45,12 @@ absobj := $(abspath $(obj))
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
 COREBOOT_EXPORTS += top src srck obj objutil objk
 
+# reproducible builds
+LANG:=C
+LC_ALL:=C
+TZ:=UTC0
+COREBOOT_EXPORTS += LANG LC_ALL TZ
+
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
 KCONFIG_AUTOADS := $(obj)/cb-config.ads

diff --git a/Makefile.inc b/Makefile.inc
@@ -504,7 +504,7 @@ $(build_h): $$(shell $$(build_h_check))
 	@printf "    GEN        build.h\n"
 	mv $< $@
 
-build-dirs:
+build-dirs $(objcbfs) $(objgenerated):
 	mkdir -p $(objcbfs) $(objgenerated)
 
 #######################################################################
@@ -591,11 +591,12 @@ OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_D
 endif
 
 DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c
+DEVICETREE_STATIC_H := $(obj)/static.h
 
 $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig
 	@printf "    SCONFIG    $(subst $(src)/,,$(<))\n"
 	mkdir -p $(dir $(DEVICETREE_STATIC_C))
-	$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE)
+	$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE)
 
 ramstage-y+=$(DEVICETREE_STATIC_C)
 romstage-y+=$(DEVICETREE_STATIC_C)
@@ -706,7 +707,7 @@ $(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.raw.elf
 	$(OBJCOPY_bootblock) -O binary $< $@
 
 ifneq ($(CONFIG_HAVE_BOOTBLOCK),y)
-$(objcbfs)/bootblock.bin:
+$(objcbfs)/bootblock.bin: $(objcbfs)
 	dd if=/dev/zero of=$@ bs=64 count=1
 endif
 

diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial
@@ -4,3 +4,5 @@ CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_CONSOLE_POST=y
 CONFIG_LINEAR_FRAMEBUFFER=y
 # CONFIG_CONSOLE_SERIAL is not set
+CONFIG_BOOTSPLASH=y
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.1"
+CONFIG_LOCALVERSION="v4.10.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_NO_GFX_INIT=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.1"
+CONFIG_LOCALVERSION="v4.10.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y

diff --git a/configs/config.pcengines_apu2_vboot b/configs/config.pcengines_apu2_vboot
@@ -1,6 +1,5 @@
-CONFIG_LOCALVERSION="v4.10.0.1"
+CONFIG_LOCALVERSION="v4.10.0.2"
 CONFIG_VENDOR_PCENGINES=y
-CONFIG_CBFS_SIZE=0x20C000
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_VBOOT=y
 CONFIG_BOARD_PCENGINES_APU2=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.1"
+CONFIG_LOCALVERSION="v4.10.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.1"
+CONFIG_LOCALVERSION="v4.10.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.1"
+CONFIG_LOCALVERSION="v4.10.0.2"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y

diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c
@@ -198,8 +198,13 @@ static void redraw_module(struct coreinfo_cat *cat)
 
 static void handle_category_key(struct coreinfo_cat *cat, int key)
 {
-	if (key >= 'a' && key <= 'z') {
-		int index = key - 'a';
+	if ((key >= 'a' && key <= 'z') || (key >= 'A' && key <= 'Z')) {
+		int index;
+		if (key >= 'A' && key <= 'Z') {
+			index = key - 'A';
+		} else {
+			index = key - 'a';
+		}
 		if (index < cat->count) {
 			cat->cur = index;
 			redraw_module(cat);

diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk
@@ -29,6 +29,8 @@ tarball_dir:=$(project_dir)/tarball
 decompress_flag=.done
 
 OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy
+KERNEL_MAKE_FLAGS = \
+	ARCH=$(ARCH-y)
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y)
 	kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION)
@@ -90,15 +92,15 @@ ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG),y)
 else
 	cp $(ARCH-y)/defconfig $(kernel_dir)/.config
 endif
-	$(MAKE) -C $(kernel_dir) olddefconfig ARCH=$(ARCH-y)
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) olddefconfig
 
 build: $(kernel_dir)/.config
 	@echo "    MAKE       Linux $(kernel_version)"
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
-	$(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) bzImage
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) bzImage
 else
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
-	$(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) vmlinux
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) vmlinux
 endif
 endif
 

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -29,6 +29,11 @@ endif
 ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y)
 PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config
 $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf
+ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),)
+  BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE)
+else
+  BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER))))
+endif
 #TODO: Figure out version
 endif
 
@@ -158,7 +163,7 @@ endif
 
 payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL)
 	$(MAKE) -C payloads/external/depthcharge \
-		BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) \
+		BOARD=$(BOARD) \
 		MFLAGS= MAKEFLAGS= \
 		DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \
 		DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \

diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig
@@ -35,6 +35,11 @@ config PAYLOAD_FILE
 	string
 	default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf"
 
+config MAINBOARD_DEPTHCHARGE
+	string ""
+	help
+	   Override BOARD setting for depthcharge
+
 config LP_DEFCONFIG_OVERRIDE
 	bool "Use default libpayload config"
 	help

diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c
@@ -50,8 +50,7 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info)
 
 static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
-	info->mrc_cache = phys_to_virt(cbmem->cbmem_tab);
+	info->mrc_cache = get_cbmem_ptr(ptr);
 }
 
 int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)

diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c
@@ -35,15 +35,39 @@
 /* assume that host_to_device is overwritten if necessary */
 #define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp)
 /* status (and status change) bits */
-#define PORT_CONNECTION 0x1
-#define PORT_ENABLE 0x2
-#define PORT_RESET 0x10
+#define PORT_CONNECTION		0x01
+#define PORT_ENABLE		0x02
+#define PORT_SUSPEND		0x04
+#define PORT_OVER_CURRENT	0x08
+#define PORT_RESET		0x10
+#define BH_PORT_RESET		0x20
+#define PORT_LINK_STATE		0x40
+#define PORT_CONFIG_ERROR	0x80
 /* feature selectors (for setting / clearing features) */
-#define SEL_PORT_RESET 0x4
-#define SEL_PORT_POWER 0x8
-#define SEL_C_PORT_CONNECTION 0x10
+#define SEL_PORT_RESET		0x04
+#define SEL_PORT_POWER		0x08
+#define SEL_C_PORT_CONNECTION	0x10
+#define SEL_C_PORT_ENABLE	0x11
+#define SEL_C_PORT_SUSPEND	0x12
+#define SEL_C_PORT_OVER_CURRENT	0x13
+#define SEL_C_PORT_RESET	0x14
+#define SEL_C_PORT_LINK_STATE	0x19
+#define SEL_C_PORT_CONFIG_ERROR	0x1a
+#define SEL_C_BH_PORT_RESET	0x1d
 /* request type (USB 3.0 hubs only) */
-#define SET_HUB_DEPTH 12
+#define SET_HUB_DEPTH		12
+
+static endpoint_t *
+usb_hub_interrupt_ep(usbdev_t *const dev)
+{
+	int i;
+	for (i = 0; i < dev->num_endp; ++i) {
+		if (dev->endpoints[i].type == INTERRUPT &&
+				dev->endpoints[i].direction == IN)
+			return &dev->endpoints[i];
+	}
+	return NULL;
+}
 
 static int
 usb_hub_port_status_changed(usbdev_t *const dev, const int port)
@@ -169,13 +193,99 @@ usb_hub_port_initialize(usbdev_t *const dev, const int port)
 		return;
 	if (buf[1] & PORT_CONNECTION)
 		clear_feature(dev, port, SEL_C_PORT_CONNECTION, DR_PORT);
-	if (buf[0] & PORT_CONNECTION)
+	if (buf[0] & PORT_CONNECTION) {
+		usb_debug("usbhub: Port coldplug at %d\n", port);
 		generic_hub_scanport(dev, port);
+	}
+}
+
+static int
+usb_hub_handle_port_change(usbdev_t *const dev, const int port)
+{
+	static const struct {
+		unsigned short change_bit;
+		unsigned short clear_sel;
+	} change_bits[] = {
+		{ PORT_CONNECTION,	SEL_C_PORT_CONNECTION	},
+		{ PORT_ENABLE,		SEL_C_PORT_ENABLE	},
+		{ PORT_SUSPEND,		SEL_C_PORT_SUSPEND	},
+		{ PORT_OVER_CURRENT,	SEL_C_PORT_OVER_CURRENT	},
+		{ PORT_RESET,		SEL_C_PORT_RESET	},
+		{ BH_PORT_RESET,	SEL_C_BH_PORT_RESET	},
+		{ PORT_LINK_STATE,	SEL_C_PORT_LINK_STATE	},
+		{ PORT_CONFIG_ERROR,	SEL_C_PORT_CONFIG_ERROR	},
+	};
+	int ret = 0;
+	unsigned int i;
+	unsigned short checked_bits = 0;
+	unsigned short buf[2] = { 0, 0 };
+
+	ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Second word holds the change bits. The interrupt transfer shows
+	 * a logical or of these bits, so we have to clear them all.
+	 */
+	for (i = 0; i < ARRAY_SIZE(change_bits); ++i) {
+		if (buf[1] & change_bits[i].change_bit)
+			clear_feature(dev, port, change_bits[i].clear_sel, DR_PORT);
+		checked_bits |= change_bits[i].change_bit;
+	}
+	if (buf[1] & ~checked_bits)
+		usb_debug("usbhub: Spurious change bit at port %d\n", port);
+
+	/* Now, handle connection changes. */
+	if (buf[1] & PORT_CONNECTION) {
+		usb_debug("usbhub: Port change at %d\n", port);
+		ret = generic_hub_scanport(dev, port);
+	}
+	return ret;
+}
+
+static void
+usb_hub_poll(usbdev_t *const dev)
+{
+	unsigned int port, i;
+	u8 buf[32] = { 0 };
+	const u8 *ibuf;
+
+	/* First, gather all change bits from finished interrupt transfers. */
+	const size_t port_bytes = MIN(ARRAY_SIZE(buf),
+			div_round_up(GEN_HUB(dev)->num_ports + 1, 8));
+	while ((ibuf = dev->controller->poll_intr_queue(GEN_HUB(dev)->data))) {
+		for (i = 0; i < port_bytes; ++i)
+			buf[i] |= ibuf[i];
+	}
+
+	for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) {
+		/* ports start at bit1; bit0 is hub status change */
+		if (buf[port / 8] & (1 << (port % 8))) {
+			if (usb_hub_handle_port_change(dev, port) < 0)
+				return;
+		}
+	}
+}
+
+static void
+usb_hub_destroy(usbdev_t *const dev)
+{
+	endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev);
+	dev->controller->destroy_intr_queue(intr_ep, GEN_HUB(dev)->data);
+	generic_hub_destroy(dev);
 }
 
 void
 usb_hub_init(usbdev_t *const dev)
 {
+	endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev);
+	if (!intr_ep) {
+		usb_debug("usbhub: ERROR: No interrupt-in endpoint found\n");
+		return;
+	}
+
+	/* Get number of ports from hub decriptor */
 	int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */
 	hub_descriptor_t desc;	/* won't fit the whole thing, we don't care */
 	if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type,
@@ -187,10 +297,38 @@ usb_hub_init(usbdev_t *const dev)
 
 	if (is_usb_speed_ss(dev->speed))
 		usb_hub_set_hub_depth(dev);
-	if (generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops) < 0)
+
+	/*
+	 * Register interrupt transfer:
+	 *   one bit per port + one bit for the hub,
+	 *   20 transfers in the queue, like our HID driver,
+	 *   one transfer per 256ms
+	 */
+	void *const intrq = dev->controller->create_intr_queue(
+			intr_ep, intr_ep->maxpacketsize, 20, 256);
+	if (!intrq) {
+		usb_detach_device(dev->controller, dev->address);
+		return;
+	}
+
+	/*
+	 * Limit the number of ports by the max packet size of
+	 * the interrupt endpoint. This shouldn't be necessary
+	 * but prevents a potential overflow in usb_hub_poll().
+	 */
+	const unsigned int num_ports =
+		MIN(desc.bNbrPorts, intr_ep->maxpacketsize * 8 - 1);
+	if (generic_hub_init(dev, num_ports, &usb_hub_ops)) {
+		dev->controller->destroy_intr_queue(intr_ep, intrq);
+		usb_detach_device(dev->controller, dev->address);
 		return;
+	}
 
 	int port;
-	for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port)
+	for (port = 1; port <= num_ports; ++port)
 		usb_hub_port_initialize(dev, port);
+
+	GEN_HUB(dev)->data = intrq;
+	dev->poll = usb_hub_poll;
+	dev->destroy = usb_hub_destroy;
 }
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
@@ -78,6 +78,7 @@ enum {
 	CB_TAG_VBOOT_WORKBUF		= 0x0034,
 	CB_TAG_MMC_INFO			= 0x0035,
 	CB_TAG_TCPA_LOG			= 0x0036,
+	CB_TAG_FMAP			= 0x0037,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
@@ -394,4 +395,6 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
+/* Helper functions */
+void *get_cbmem_ptr(unsigned char *ptr);
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
@@ -128,6 +128,9 @@ struct sysinfo_t {
 	uint32_t mtc_size;
 	void	*chromeos_vpd;
 	int	mmc_early_wake_status;
+
+	/* Pointer to FMAP cache in CBMEM */
+	void	*fmap_cache;
 };
 
 extern struct sysinfo_t lib_sysinfo;

diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
@@ -42,6 +42,12 @@
 /* === Parsing code === */
 /* This is the generic parsing code. */
 
+void *get_cbmem_ptr(unsigned char *ptr)
+{
+	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
+	return phys_to_virt(cbmem->cbmem_tab);
+}
+
 static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 {
 	struct cb_memory *mem = ptr;
@@ -128,20 +134,17 @@ static void cb_parse_mac_addresses(unsigned char *ptr,
 
 static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info)
 {
-	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
-	info->tstamp_table = phys_to_virt(cbmem->cbmem_tab);
+	info->tstamp_table = get_cbmem_ptr(ptr);
 }
 
 static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info)
 {
-	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
-	info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab);
+	info->cbmem_cons = get_cbmem_ptr(ptr);
 }
 
 static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info)
 {
-	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
-	info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab);
+	info->acpi_gnvs = get_cbmem_ptr(ptr);
 }
 
 static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info)
@@ -193,8 +196,7 @@ static void cb_parse_string(unsigned char *ptr, char **info)
 
 static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
-	info->wifi_calibration = phys_to_virt(cbmem->cbmem_tab);
+	info->wifi_calibration = get_cbmem_ptr(ptr);
 }
 
 static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info)
@@ -235,8 +237,12 @@ static void cb_parse_boot_media_params(unsigned char *ptr,
 
 static void cb_parse_vpd(void *ptr, struct sysinfo_t *info)
 {
-	struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr;
-	info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab);
+	info->chromeos_vpd = get_cbmem_ptr(ptr);
+}
+
+static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info)
+{
+	info->fmap_cache = get_cbmem_ptr(ptr);
 }
 
 #if CONFIG(LP_TIMER_RDTSC)
@@ -412,6 +418,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_VPD:
 			cb_parse_vpd(ptr, info);
 			break;
+		case CB_TAG_FMAP:
+			cb_parse_fmap_cache(ptr, info);
+			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;

diff --git a/src/Kconfig b/src/Kconfig
@@ -346,8 +346,18 @@ config OVERRIDE_DEVICETREE
 	  Examples: "devicetree.variant-override.cb"
 	            "variant/devicetree-override.cb"
 
+config FMDFILE
+	string "fmap description file in fmd format"
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
+	default ""
+	help
+	  The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
+	  but in some cases more complex setups are required.
+	  When an fmd is specified, it overrides the default format.
+
 config CBFS_SIZE
 	hex "Size of CBFS filesystem in ROM"
+	depends on FMDFILE = ""
 	# Default value set at the end of the file
 	help
 	  This is the part of the ROM actually managed by CBFS, located at the
@@ -356,16 +366,8 @@ config CBFS_SIZE
 	  to span the whole ROM on all but Intel systems that use an Intel Firmware
 	  Descriptor.  It can be overridden to make coreboot live alongside other
 	  components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
-	  binaries.
-
-config FMDFILE
-	string "fmap description file in fmd format"
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
-	default ""
-	help
-	  The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
-	  but in some cases more complex setups are required.
-	  When an fmd is specified, it overrides the default format.
+	  binaries. This symbol should only be used to generate a default FMAP and
+	  is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
 
 endmenu
 
@@ -986,7 +988,7 @@ config X86EMU_DEBUG_IO
 config X86EMU_DEBUG_TIMINGS
 	bool "Output timing information"
 	default n
-	depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
+	depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
 	help
 	  Print timing information needed by i915tool.
 

diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h
@@ -18,7 +18,9 @@
 
 static inline void *car_get_var_ptr(void *var) { return var; }
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
 #define car_set_var(var, val) do { (var) = (val); } while (0)
 
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+
 #endif
diff --git a/src/arch/arm/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h
@@ -14,16 +14,6 @@
 #ifndef ARCH_ARM_PCI_OPS_H
 #define ARCH_ARM_PCI_OPS_H
 
-#include <stdint.h>
-#include <device/pci_type.h>
-
-#ifdef __SIMPLE_DEVICE__
-u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
-u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
-u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
-void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val);
-void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val);
-void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val);
-#endif
+#include <device/pci_mmio_cfg.h>
 
 #endif
diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c
@@ -18,32 +18,75 @@
 #include <bl31.h>
 #include <bootmem.h>
 #include <cbfs.h>
+#include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
 
-/*
- * TODO: Many of these structures are currently unused. Better not fill them out
- * to make future changes fail fast, rather than try to come up with content
- * that might turn out to not make sense. Implement later as required.
- *
-static image_info_t bl31_image_info;
-static image_info_t bl32_image_info;
-static image_info_t bl33_image_info;
- */
-static entry_point_info_t bl32_ep_info;
-static entry_point_info_t bl33_ep_info;
-static bl31_params_t bl31_params;
+#include <arm-trusted-firmware/include/export/common/bl_common_exp.h>
+
+static entry_point_info_t bl32_ep_info = {
+	.h = {
+		.type = PARAM_EP,
+		.version = PARAM_VERSION_1,
+		.size = sizeof(bl32_ep_info),
+		.attr = EP_SECURE,
+	},
+};
+static entry_point_info_t bl33_ep_info = {
+	.h = {
+		.type = PARAM_EP,
+		.version = PARAM_VERSION_1,
+		.size = sizeof(bl33_ep_info),
+		.attr = EP_NON_SECURE,
+	},
+};
+
+static bl_params_node_t bl32_params_node = {
+	.image_id = BL32_IMAGE_ID,
+	.ep_info = &bl32_ep_info,
+};
+static bl_params_node_t bl33_params_node = {
+	.image_id = BL33_IMAGE_ID,
+	.ep_info = &bl33_ep_info,
+};
+
+static bl_params_t bl_params = {
+	.h = {
+		.type = PARAM_BL_PARAMS,
+		.version = PARAM_VERSION_2,
+		.size = sizeof(bl_params),
+		.attr = 0,
+	},
+	.head = &bl33_params_node,
+};
+
+static struct bl_aux_param_header *bl_aux_params;
 
-void __weak *soc_get_bl31_plat_params(bl31_params_t *params)
+/* Only works when using the default soc_get_bl31_plat_params() below. */
+void register_bl31_aux_param(struct bl_aux_param_header *param)
 {
-	/* Default weak implementation. */
-	return NULL;
+	param->next = (uintptr_t)bl_aux_params;
+	bl_aux_params = param;
+}
+
+/* Default implementation. All newly added SoCs should use this if possible! */
+__weak void *soc_get_bl31_plat_params(void)
+{
+	static struct bl_aux_param_uint64 cbtable_param = {
+		.h = { .type = BL_AUX_PARAM_COREBOOT_TABLE, },
+	};
+	if (!cbtable_param.value) {
+		cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE);
+		if (cbtable_param.value)
+			register_bl31_aux_param(&cbtable_param.h);
+	}
+	return bl_aux_params;
 }
 
 void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 {
 	struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31");
-	void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL;
+	void (*bl31_entry)(bl_params_t *params, void *plat_params) = NULL;
 
 	if (prog_locate(&bl31))
 		die("BL31 not found");
@@ -52,8 +95,6 @@ void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 		die("BL31 load failed");
 	bl31_entry = prog_entry(&bl31);
 
-	SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
-
 	if (CONFIG(ARM64_USE_SECURE_OS)) {
 		struct prog bl32 = PROG_INIT(PROG_BL32,
 					     CONFIG_CBFS_PREFIX"/secure_os");
@@ -64,27 +105,21 @@ void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 		if (cbfs_prog_stage_load(&bl32))
 			die("BL32 load failed");
 
-		SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_1,
-			       PARAM_EP_SECURE);
 		bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32);
 		bl32_ep_info.spsr = SPSR_EXCEPTION_MASK |
 				get_eret_el(EL1, SPSR_USE_L);
-		bl31_params.bl32_ep_info = &bl32_ep_info;
+		bl33_params_node.next_params_info = &bl32_params_node;
 	}
 
-	bl31_params.bl33_ep_info = &bl33_ep_info;
-
-	SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_1, PARAM_EP_NON_SECURE);
 	bl33_ep_info.pc = payload_entry;
 	bl33_ep_info.spsr = payload_spsr;
 	bl33_ep_info.args.arg0 = payload_arg0;
 
-	/* May update bl31_params if necessary. */
-	void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params);
+	void *bl31_plat_params = soc_get_bl31_plat_params();
 
 	/* MMU disable will flush cache, so passed params land in memory. */
 	raw_write_daif(SPSR_EXCEPTION_MASK);
 	mmu_disable();
-	bl31_entry(&bl31_params, bl31_plat_params);
+	bl31_entry(&bl_params, bl31_plat_params);
 	die("BL31 returned!");
 }
diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h
@@ -18,7 +18,9 @@
 
 static inline void *car_get_var_ptr(void *var) { return var; }
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
 #define car_set_var(var, val) do { (var) = (val); } while (0)
 
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+
 #endif
diff --git a/src/arch/arm64/include/arm_tf_temp.h b/src/arch/arm64/include/arm_tf_temp.h
diff --git a/src/arch/arm64/include/bl31.h b/src/arch/arm64/include/bl31.h
@@ -16,13 +16,17 @@
 
 #include <types.h>
 
-/* TODO: Pull in directly from ARM TF once its headers have been reorganized. */
-#include <arm_tf_temp.h>
+#include <arm-trusted-firmware/include/export/lib/bl_aux_params/bl_aux_params_exp.h>
 
 /* Load and enter BL31, set it up to exit to payload according to arguments. */
 void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr);
 
-/* Return platform-specific bl31_plat_params. May update bl31_params. */
-void *soc_get_bl31_plat_params(bl31_params_t *bl31_params);
+/* Return platform-specific bl31_plat_params. SoCs should avoid overriding this
+   and stick with the default BL aux parameter framework if possible. */
+void *soc_get_bl31_plat_params(void);
+
+/* Add a BL aux parameter to the list to be passed to BL31. Only works for SoCs
+   that use the default soc_get_bl31_plat_params() implementation. */
+void register_bl31_aux_param(struct bl_aux_param_header *param);
 
 #endif /* __BL31_H__ */
diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h
@@ -19,7 +19,9 @@
 
 static inline void *car_get_var_ptr(void *var) { return var; }
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
 #define car_set_var(var, val) { (var) = (val); }
 
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+
 #endif /* __MIPS_ARCH_EARLY_VARIABLES_H */
diff --git a/src/arch/mips/include/arch/header.ld b/src/arch/mips/include/arch/header.ld
@@ -19,7 +19,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 ENTRY(_start)
 #else
 ENTRY(stage_entry)

diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h
@@ -14,16 +14,6 @@
 #ifndef ARCH_MIPS_PCI_OPS_H
 #define ARCH_MIPS_PCI_OPS_H
 
-#include <stdint.h>
-#include <device/pci_type.h>
-
-#ifdef __SIMPLE_DEVICE__
-u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
-u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
-u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
-void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val);
-void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val);
-void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val);
-#endif
+#include <device/pci_mmio_cfg.h>
 
 #endif
diff --git a/src/arch/ppc64/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h
@@ -19,8 +19,9 @@
 #define CAR_MIGRATE(migrate_fn_)
 static inline void *car_get_var_ptr(void *var) { return var; }
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
-
 #define car_set_var(var, val) do { (var) = (val); } while (0)
 
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+
 #endif
diff --git a/src/arch/ppc64/include/arch/header.ld b/src/arch/ppc64/include/arch/header.ld
@@ -19,7 +19,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#ifdef __BOOTBLOCK__
+#if ENV_BOOTBLOCK
 ENTRY(_start)
 #else
 ENTRY(stage_entry)

diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h
@@ -21,7 +21,9 @@
 #define CAR_MIGRATE(migrate_fn_)
 static inline void *car_get_var_ptr(void *var) { return var; }
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
 #define car_set_var(var, val) do { (var) = (val); } while (0)
 
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+
 #endif
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
@@ -1,8 +1,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2009-2010 coresystems GmbH
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -1,11 +1,6 @@
-################################################################################
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
-## Copyright (C) 2009-2010 coresystems GmbH
-## Copyright (C) 2009 Ronald G. Minnich
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.
@@ -166,7 +161,7 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch
 $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
 # The open quote in the subst messes with syntax highlighting. Fix it - ")
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
-	$(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
+	$(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
 		$< > $(objgenerated)/bootblock.inc.d
 	$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
 

diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
@@ -1,22 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * coreboot ACPI Table support
- * written by Stefan Reinauer <stepan@openbios.org>
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2005-2009 coresystems GmbH
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
- * Raptor Engineering
- * Copyright (C) 2016-2019 Siemens AG
- *
- * ACPI FADT, FACS, and DSDT table support added by
- * Nick Barker <nick.barker9@btinternet.com>, and those portions
- * Copyright (C) 2004 Nick Barker
- *
- * Copyright (C) 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
- * 2005.9 yhlu add SRAT table generation
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -25,6 +9,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * coreboot ACPI Table support
  */
 
 /*
@@ -51,6 +37,8 @@
 #include <version.h>
 #include <commonlib/sort.h>
 
+static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp);
+
 u8 acpi_checksum(u8 *table, u32 length)
 {
 	u8 ret = 0;
@@ -1274,9 +1262,51 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* Align ACPI tables to 16byte */
 	current = acpi_align_current(current);
 
+	/* Special case for qemu */
 	fw = fw_cfg_acpi_tables(current);
-	if (fw)
+	if (fw) {
+		rsdp = NULL;
+		/* Find RSDP. */
+		for (void *p = (void *)current; p < (void *)fw; p += 16) {
+			if (valid_rsdp((acpi_rsdp_t *)p)) {
+				rsdp = p;
+				break;
+			}
+		}
+		if (!rsdp)
+			return fw;
+
+		/* Add BOOT0000 for Linux google firmware driver */
+		printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+		ssdt = (acpi_header_t *)fw;
+		current = (unsigned long)ssdt + sizeof(acpi_header_t);
+
+		memset((void *)ssdt, 0, sizeof(acpi_header_t));
+
+		memcpy(&ssdt->signature, "SSDT", 4);
+		ssdt->revision = get_acpi_table_revision(SSDT);
+		memcpy(&ssdt->oem_id, OEM_ID, 6);
+		memcpy(&ssdt->oem_table_id, oem_table_id, 8);
+		ssdt->oem_revision = 42;
+		memcpy(&ssdt->asl_compiler_id, ASLC, 4);
+		ssdt->asl_compiler_revision = asl_revision;
+		ssdt->length = sizeof(acpi_header_t);
+
+		acpigen_set_current((char *) current);
+
+		/* Write object to declare coreboot tables */
+		acpi_ssdt_write_cbtable();
+
+		/* (Re)calculate length and checksum. */
+		ssdt->length = current - (unsigned long)ssdt;
+		ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+
+		acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+
+		acpi_add_table(rsdp, ssdt);
+
 		return fw;
+	}
 
 	dsdt_file = cbfs_boot_map_with_leak(
 				     CONFIG_CBFS_PREFIX "/dsdt.aml",

diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpi/statdef.asl b/src/arch/x86/acpi/statdef.asl
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Advanced Micro Devices, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpi_pld.c b/src/arch/x86/acpi_pld.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2018 Google LLC
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2005-2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -62,12 +60,6 @@ int acpi_is_wakeup_s4(void)
 	acpi_handoff_wakeup();
 	return (acpi_slp_type == ACPI_S4);
 }
-
-void acpi_fail_wakeup(void)
-{
-	if (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2)
-		acpi_slp_type = ACPI_S0;
-}
 #endif /* ENV_RAMSTAGE */
 
 #define WAKEUP_BASE 0x600

diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
@@ -1,10 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
- * Raptor Engineering
- * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- * Copyright (C) 2016 Intel Corp.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -35,11 +32,11 @@ _start:
 	/* reset stack pointer to CAR stack */
 	mov	$_car_stack_end, %esp
 
-	/* clear CAR_GLOBAL area as it is not shared */
+	/* clear .bss section as it is not shared */
 	cld
 	xor	%eax, %eax
-	movl	$(_car_global_end), %ecx
-	movl	$(_car_global_start), %edi
+	movl	$(_ebss), %ecx
+	movl	$(_bss), %edi
 	sub	%edi, %ecx
 	shrl	$2, %ecx
 	rep	stosl

diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
@@ -1,15 +1,6 @@
 /*
- * This is the modern bootblock. It is used by platforms which select
- * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime
- * setup. The actual setup is done by hardware-specific code.
- *
- * It provides a bootflow similar to other architectures, and thus is considered
- * to be the modern approach.
- *
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +10,14 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * This is the modern bootblock. It is used by platforms which select
+ * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime
+ * setup. The actual setup is done by hardware-specific code.
+ *
+ * It provides a bootflow similar to other architectures, and thus is considered
+ * to be the modern approach.
+ *
  */
 
 #include <cpu/x86/cr.h>
@@ -48,11 +47,10 @@ bootblock_protected_mode_entry:
 	/* MMX registers required here */
 
 	/* BIST result in eax */
-	movl	%eax, %ebx
+	movd	%eax, %mm0
 
 	/* Get an early timestamp */
 	rdtsc
-	movd	%ebx, %mm0
 	movd	%eax, %mm1
 	movd	%edx, %mm2
 #endif

diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -1,10 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- * Copyright 2015 Google Inc
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -60,36 +56,35 @@
 	. += 32;
 	_epdpt = .;
 #endif
-	_car_relocatable_data_start = .;
-	/* The timestamp implementation relies on this storage to be around
-	 * after migration. One of the fields indicates not to use it as the
-	 * backing store once cbmem comes online. Therefore, this data needs
-	 * to reside in the migrated area (between _car_relocatable_data_start
-	 * and _car_relocatable_data_end). */
+
 	TIMESTAMP(., 0x200)
+
 	_car_ehci_dbg_info_start = .;
 	/* Reserve sizeof(struct ehci_dbg_info). */
         . += 80;
         _car_ehci_dbg_info_end = .;
-	/* _car_global_start and _car_global_end provide symbols to per-stage
+
+	/* _bss and _ebss provide symbols to per-stage
 	 * variables that are not shared like the timestamp and the pre-ram
 	 * cbmem console. This is useful for clearing this area on a per-stage
 	 * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
-	_car_global_start = .;
+
+	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+	_bss = .;
 #if ENV_STAGE_HAS_BSS_SECTION
 	/* Allow global uninitialized variables for stages without CAR teardown. */
 	*(.bss)
 	*(.bss.*)
 	*(.sbss)
 	*(.sbss.*)
 #else
-	/* .car.global_data objects only around when
-	 * CONFIG_CAR_GLOBAL_MIGRATION is employed. */
+	_car_global_start = .;
 	*(.car.global_data);
+	_car_global_end = .;
 #endif
 	. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
-	_car_global_end = .;
-	_car_relocatable_data_end = .;
+	_ebss = .;
+	_car_unallocated_start = .;
 
 #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;

diff --git a/src/arch/x86/cbfs_and_run.c b/src/arch/x86/cbfs_and_run.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
@@ -13,7 +13,6 @@
 
 #include <stdlib.h>
 #include <cbmem.h>
-#include <arch/acpi.h>
 
 #if CONFIG(CBMEM_TOP_BACKUP)
 
@@ -35,13 +34,3 @@ void *cbmem_top(void)
 }
 
 #endif /* CBMEM_TOP_BACKUP */
-
-/* Something went wrong, our high memory area got wiped */
-void cbmem_fail_resume(void)
-{
-#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME)
-	/* ACPI resume needs to be cleared in the fail-to-recover case, but that
-	 * condition is only handled during ramstage. */
-	acpi_fail_wakeup();
-#endif
-}
diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2017 Google, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; version 2 of

diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; version 2 of

diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
@@ -1,14 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
- * Raptor Engineering
- * Copyright (C) 2016 Siemens AG
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -940,7 +932,6 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
 	acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
 
 /* For ACPI S3 support. */
-void acpi_fail_wakeup(void);
 void acpi_resume(void *wake_vec);
 void mainboard_suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
@@ -983,7 +974,7 @@ static inline int acpi_s3_resume_allowed(void)
 
 #if CONFIG(HAVE_ACPI_RESUME)
 
-#ifdef __PRE_RAM__
+#if ENV_ROMSTAGE_OR_BEFORE
 static inline int acpi_is_wakeup_s3(void)
 {
 	return (acpi_get_sleep_type() == ACPI_S3);

diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016 Google, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2018 Google LLC
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
@@ -1,10 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
- * Raptor Engineering
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Advanced Micro Devices, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/cbconfig.h b/src/arch/x86/include/arch/cbconfig.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
@@ -158,6 +158,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
 
 #define CPUID_FEATURE_PAE (1 << 6)
 #define CPUID_FEATURE_PSE36 (1 << 17)
+#define CPUID_FEAURE_HTT (1 << 28)
 
 // Intel leaf 0x4, AMD leaf 0x8000001d EAX
 
@@ -214,7 +215,8 @@ static inline bool cpu_is_intel(void)
 	return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON);
 }
 
-#ifndef __SIMPLE_DEVICE__
+#ifndef __ROMCC__
+/* romcc does not support anonymous structs. */
 
 struct device;
 
@@ -258,9 +260,8 @@ static inline struct cpu_info *cpu_info(void)
 	);
 	return ci;
 }
-#endif
 
-#ifndef __ROMCC__ // romcc is segfaulting in some cases
+/* romcc is segfaulting in some cases. */
 struct cpuinfo_x86 {
 	uint8_t	x86;		/* CPU family */
 	uint8_t	x86_vendor;	/* CPU vendor */

diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -22,6 +20,15 @@
 
 #if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION)
 
+/*
+ * The _car_global_[start|end]symbols cover CAR data which is relocatable
+ * once memory comes online. Variables with CAR_GLOBAL decoration
+ * reside within this region.
+ */
+extern char _car_global_start[];
+extern char _car_global_end[];
+#define _car_global_size (_car_global_end - _car_global_start)
+
 asm(".section .car.global_data,\"w\",@nobits");
 asm(".previous");
 #ifdef __clang__
@@ -33,28 +40,34 @@ asm(".previous");
 /* Get the correct pointer for the CAR global variable. */
 void *car_get_var_ptr(void *var);
 
-/* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/
-void *car_sync_var_ptr(void *var);
-
 /* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */
 int car_active(void);
 
 /* Get and set a primitive type global variable. */
 #define car_get_var(var) \
 	(*(typeof(var) *)car_get_var_ptr(&(var)))
-#define car_sync_var(var) \
-	(*(typeof(var) *)car_sync_var_ptr(&(var)))
 #define car_set_var(var, val)	car_get_var(var) = (val)
 
+/* Get and set a CAR_GLOBAL pointing elsewhere inside CAR. */
+#if !CONFIG(PLATFORM_USES_FSP1_0)
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+#else
+void *car_get_reloc_ptr(void *var);
+void car_set_reloc_ptr(void *var, void *val);
+#define car_get_ptr(var) car_get_reloc_ptr(&(var))
+#define car_set_ptr(var, val) car_set_reloc_ptr(&(var), (val))
+#endif
+
 static inline size_t car_data_size(void)
 {
-	size_t car_size = _car_relocatable_data_size;
-	return ALIGN_UP(car_size, 64);
+	size_t car_size = _car_global_size;
+	return ALIGN(car_size, 64);
 }
 
 static inline size_t car_object_offset(void *ptr)
 {
-	return (char *)ptr - &_car_relocatable_data_start[0];
+	return (char *)ptr - &_car_global_start[0];
 }
 
 #else
@@ -66,8 +79,9 @@ static inline size_t car_object_offset(void *ptr)
 
 #define CAR_GLOBAL
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
 #define car_set_var(var, val)	(var) = (val)
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
 
 static inline void *car_get_var_ptr(void *var)
 {

diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; version 2 of

diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2013 Google Inc.
- *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:

diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/interrupt.h b/src/arch/x86/include/arch/interrupt.h
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2009 Libra Li <libra.li@technexion.com>
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or

diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/memory_clear.h b/src/arch/x86/include/arch/memory_clear.h
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 9elements Agency GmbH
- * Copyright (C) 2019 Facebook Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h
@@ -1,10 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- * Copyright (C) 2012 Patrick Georgi <patrick@georgi-clan.de>
- * Copyright (C) 2010 Stefan Reinauer <stepan@coreboot.org>
- *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation, either version 2 of the License, or

diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
@@ -88,4 +88,13 @@ void run_postcar_phase(struct postcar_frame *pcf);
  */
 void late_car_teardown(void);
 
+/*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+void postcar_enable_tseg_cache(struct postcar_frame *pcf);
+
 #endif /* __ARCH_ROMSTAGE_H__ */
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016 Intel Corp.
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -27,31 +24,18 @@ extern char _car_region_end[];
 #define _car_region_size (_car_region_end - _car_region_start)
 
 /*
- * This is the stack used under CONFIG_C_ENVIRONMENT_BOOTBLOCK for
- * all stages that execute when cache-as-ram is up.
+ * This is the stack area used for all stages that execute when cache-as-ram
+ * is up. Area is not cleared in between stages.
  */
 extern char _car_stack_start[];
 extern char _car_stack_end[];
 #define _car_stack_size (_car_stack_end - _car_stack_start)
 
+extern char _car_unallocated_start[];
+
 extern char _car_ehci_dbg_info_start[];
 extern char _car_ehci_dbg_info_end[];
 #define _car_ehci_dbg_info_size \
 	(_car_ehci_dbg_info_end - _car_ehci_dbg_info_start)
 
-/*
- * The _car_relocatable_data_[start|end] symbols cover CAR data which is
- * relocatable once memory comes online. Variables with CAR_GLOBAL decoration
- * reside within this region. The _car_global_[start|end] is a subset of the
- * relocatable region which excludes the timestamp region because of
- * intricacies in the timestamp code.
- */
-extern char _car_relocatable_data_start[];
-extern char _car_relocatable_data_end[];
-#define _car_relocatable_data_size \
-	(_car_relocatable_data_end - _car_relocatable_data_start)
-extern char _car_global_start[];
-extern char _car_global_end[];
-#define _car_global_size (_car_global_end - _car_global_start)
-
 #endif
diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corp.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/include/smm.h b/src/arch/x86/include/smm.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2018 Google LLC
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c
@@ -1,6 +1,4 @@
 /*
- * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation,
- * Inc.
  * This file is part of the GNU C Library.
  *
  * This program is free software; you can redistribute it and/or

diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
- * Copyright (C) 2010 Stefan Reinauer <stepan@coreboot.org>
- *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation, either version 2 of the License, or

diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -33,7 +31,10 @@ void main(void)
 
 	console_init();
 
-	/* Recover cbmem so infrastruture using it is functional. */
+	/*
+	 * CBMEM needs to be recovered because timestamps rely on
+	 * the cbmem infrastructure being around. Explicitly recover it.
+	 */
 	cbmem_initialize();
 
 	timestamp_add_now(TS_START_POSTCAR);

diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -19,6 +17,7 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <rmodule.h>
 #include <romstage_handoff.h>
@@ -189,6 +188,23 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
 	stage_cache_add(STAGE_POSTCAR, prog);
 }
 
+/*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+void postcar_enable_tseg_cache(struct postcar_frame *pcf)
+{
+	uintptr_t smm_base;
+	size_t smm_size;
+
+	smm_region(&smm_base, &smm_size);
+	postcar_frame_add_mtrr(pcf, smm_base, smm_size,
+				MTRR_TYPE_WRBACK);
+}
+
 void run_postcar_phase(struct postcar_frame *pcf)
 {
 	struct prog prog =

diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2017 Intel Corporation.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
@@ -1,11 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
- * Raptor Engineering
- * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
- * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; version 2 of

diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
@@ -1,10 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2003 Eric Biederman
- * Copyright (C) 2005 Steve Magnani
- * Copyright (C) 2008-2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/thread_switch.S b/src/arch/x86/thread_switch.S
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2013 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/verstage.c b/src/arch/x86/verstage.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S
@@ -1,9 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2015 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
Original file line number	Diff line number	Diff line change
Expand Up		@@ -4,5 +4,6 @@ This section contains documentation about coreboot on specific AMD SOCs.

		## Technology

		- [Family 15h](family15h.md)
		- [Family 17h](family17h.md)
Original file line number	Diff line number	Diff line change
Expand Up		@@ -5,3 +5,4 @@ This section contains documentation about coreboot on specific vendorcode.
		## Vendor

		- [Cavium](cavium/index.md)
		- [Eltan](eltan/index.md)