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7 changes: 6 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -13,6 +13,10 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)

## [Unreleased]

## [v4.16.0.2] - 2022-03-29
### Changed
- Rebased with official coreboot repository commit 66f99f7f

## [v4.16.0.1] - 2022-02-11
### Changed
- Rebased with official coreboot repository commit b4ba289f
Expand Down Expand Up @@ -563,7 +567,8 @@ redundant code which was similar for APU2/3/5 boards.
- turn off D4 and D5 leds on boot
- enable power on after power failure

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.16.0.1...develop
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.16.0.2...develop
[v4.16.0.2]: https://github.com/pcengines/coreboot/compare/v4.16.0.1...v4.16.0.2
[v4.16.0.1]: https://github.com/pcengines/coreboot/compare/v4.15.0.3...v4.16.0.1
[v4.15.0.3]: https://github.com/pcengines/coreboot/compare/v4.15.0.2...v4.15.0.3
[v4.15.0.2]: https://github.com/pcengines/coreboot/compare/v4.15.0.1...v4.15.0.2
Expand Down
2 changes: 1 addition & 1 deletion Documentation/community/code_of_conduct.md
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Expand Up @@ -115,4 +115,4 @@ Our arbitration team consists of the following people
This Code of Conduct is distributed under
a [Creative Commons Attribution-ShareAlike
license](http://creativecommons.org/licenses/by-sa/3.0/). It is based
on the [Citizen Code of Conduct](http://citizencodeofconduct.org/)
on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofconduct.org/)
2 changes: 1 addition & 1 deletion Documentation/community/conferences.md
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Expand Up @@ -14,7 +14,7 @@ their development kit with them and conduct development sessions.

[Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_facebook/) by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebook.mp4)) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03)

[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018)
[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/congress/2018/wiki/index.php/Main_Page)
([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27)

[coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018
Expand Down
7 changes: 5 additions & 2 deletions Documentation/contributing/coding_style.md
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Expand Up @@ -966,11 +966,14 @@ References
The C Programming Language, Second Edition by Brian W. Kernighan and
Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
(paperback), 0-13-110370-9 (hardback). URL:
<http://cm.bell-labs.com/cm/cs/cbook/>
<https://duckduckgo.com/?q=isbn+0-13-110362-8> or
<https://www.google.com/search?q=isbn+0-13-110362-8.


The Practice of Programming by Brian W. Kernighan and Rob Pike.
Addison-Wesley, Inc., 1999. ISBN 0-201-61586-X. URL:
<http://cm.bell-labs.com/cm/cs/tpop/>
<https://duckduckgo.com/?q=ISBN+0-201-61586-X> or
<https://www.google.com/search?q=ISBN+0-201-61586-X>

GNU manuals - where in compliance with K&R and this text - for cpp, gcc,
gcc internals and indent, all available from
Expand Down
32 changes: 29 additions & 3 deletions Documentation/contributing/gsoc.md
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Expand Up @@ -33,6 +33,25 @@ Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
framework for initial hardware initialization and you can help us succeed.


## Collection of official GSoC guides & documents

* [Timeline][GSoC Timeline]

* [Roles and Responsibilities][GSoC Roles and Responsibilities]

* [Contributor Guide][GSoC Contributor Guide]

* [Contributor Advice][GSoC Contributor Advice]

* [Mentor Guide][GSoC Mentor Guide]

* [FAQ][GSoC FAQ]

* [Rules][GSoC Rules]

* [Glossary][GSoC Glossary]


## Contributor requirements & commitments

Google Summer of Code is a significant time commitment for you. Medium-sized
Expand Down Expand Up @@ -72,8 +91,8 @@ amount of spare time. If this is not the case, then you should not apply.
process and common issues.

* Get signed up for Gerrit and push at least one patch to Gerrit for review.
Check Easy projects or ask for simple tasks on the [mailing list] or on our
other [community forums] if you need ideas.
Check the [easy project list][Project ideas] or ask for simple tasks on
the [mailing list] or on our other [community forums] if you need ideas.


### During the program
Expand Down Expand Up @@ -241,9 +260,16 @@ questions.
[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
[Getting started]: ../getting_started/index.md
[Tutorial]: ../tutorial/index.md
[Flashing firmware tutorial]: ../flash_tutorial/index.md
[Flashing firmware tutorial]: ../tutorial/flashing_firmware/index.md
[Coding style]: coding_style.md
[Code of Conduct]: ../community/code_of_conduct.md
[Language style]: ../community/language_style.md
[Project ideas]: project_ideas.md
[GSoC Timeline]: https://developers.google.com/open-source/gsoc/timeline
[GSoC Roles and Responsibilities]: https://developers.google.com/open-source/gsoc/help/responsibilities
[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
[GSoC Contributor Advice]: https://developers.google.com/open-source/gsoc/help/student-advice
[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor
[GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
[GSoC Rules]: https://summerofcode.withgoogle.com/rules
[GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
18 changes: 18 additions & 0 deletions Documentation/contributing/project_ideas.md
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Expand Up @@ -20,6 +20,24 @@ doubt if you can bring yourself up to speed in a required time frame
with the projects. We can then try together to figure out if you're a
good match for a project, even when requirements might not all be met.

## Easy projects

This is a collection of tasks which don't require deep knowledge on
coreboot itself. If you are a beginner and want to get familiar with the
the project and the code base, or if you just want to get your hands
dirty with some easy tasks, then these are for you.

* Resolve static analysis issues reported by [scan-build] and
[Coverity scan]. More details on the page for
[Coverity scan integration].

* Resolve issues reported by the [linter][Linter issues]

[scan-build]: https://coreboot.org/scan-build/
[Coverity scan]: https://scan.coverity.com/projects/coreboot
[Coverity scan integration]: ../infrastructure/coverity.md
[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt

## Provide toolchain binaries
Our crossgcc subproject provides a uniform compiler environment for
working on coreboot and related projects. Sadly, building it takes hours,
Expand Down
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1 change: 0 additions & 1 deletion Documentation/getting_started/index.md
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Expand Up @@ -4,6 +4,5 @@
* [Build System](build_system.md)
* [Submodules](submodules.md)
* [Kconfig](kconfig.md)
* [Documentation License](license.md)
* [Writing Documentation](writing_documentation.md)
* [Setting up GPIOs](gpio.md)
2 changes: 1 addition & 1 deletion Documentation/getting_started/writing_documentation.md
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Expand Up @@ -159,5 +159,5 @@ TOC tree.
[guide]: http://www.sphinx-doc.org/en/stable/install.html
[Sphinx]: http://www.sphinx-doc.org/en/master/
[Markdown Guide]: https://www.markdownguide.org/
[Gerrit Guidelines]: gerrit_guidelines.md
[Gerrit Guidelines]: ../contributing/gerrit_guidelines.md
[review.coreboot.org]: https://review.coreboot.org
2 changes: 1 addition & 1 deletion Documentation/index.md
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Expand Up @@ -190,4 +190,4 @@ Contents:
* [Utilities](util.md)
* [coreboot infrastructure](infrastructure/index.md)
* [Release notes](releases/index.md)
* [Flashing firmware tutorial](flash_tutorial/index.md)
* [Documentation License](documentation_license.md)
2 changes: 1 addition & 1 deletion Documentation/infrastructure/builders.md
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Expand Up @@ -61,7 +61,7 @@ coreboot project has 3 active jenkins build machines.
There are a number of builds handled by the coreboot jenkins builders,
for a number of different projects - coreboot, flashrom, memtest86+,
em100, etc. Many of these have builders for their current master branch
as well as gerrit and coverity builds.
as well as Gerrit and [Coverity](coverity.md) builds.

You can see all the builds here:
[https://qa.coreboot.org/](https://qa.coreboot.org/)
Expand Down
103 changes: 103 additions & 0 deletions Documentation/infrastructure/coverity.md
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@@ -0,0 +1,103 @@
# Coverity Scan for open source firmware

## What’s Coverity and Coverity Scan?

Coverity is a static analysis tool. It hooks into the build process
and in addition to the compiler creating object files, Coverity collects
information about the code. That data is then processed in a separate pass
to identify common programming errors, like out of bounds accesses in C.

Coverity Scan is an online service for Open Source projects providing this
analysis for free. The analysis pass is done on their servers and issues
can be handled in their [web UI](https://scan.coverity.com/).

The Scan service has some quotas based on code size to avoid overloading
the system, but even at one build per week, that’s usually good enough
because the identified issues still need to be triaged and fixed or they
will simply be re-identified next week.

### Triage?

The Web UI looks a bit like an issue tracker, even if it’s not a very
good one. It’s possible to mark identified issues as valid or invalid,
and annotate them with metadata which CLs fix them. The latter isn’t
strictly necessary because Coverity Scan simply marks issues it can’t
find anymore as fixed, but at times it helped identify issues that made
a comeback.

### Alternatives

There’s also clang’s scan-build, which is fully open-source, and
finds different issues. As such, it’s less of an alternative and more
of a complement.

There’s a regular run of that for coreboot but not for the other projects
hosted at coreboot.org.

One downside is that it emits a bunch of HTML to report on issues,
but there’s no interactivity (e.g. marking issues solved), no way
to merge multiple builds (e.g. multiple board builds of a single tree)
or a simple way to extract burndown charts and the like from that.

#### Looking for a project?

On the upside, it can emit the data in a machine readable format, so if
anybody needs a project, a scan-build web-frontend like Coverity Scan would
be feasible without having to go through scan-build’s guts, just by parsing
text files - plus all the stateful and web parts to build on top.

## Logging into Coverity Scan

Coverity Scan needs an account. It supports its own accounts and GitHub
OAuth.

Access to the dashboards needs approval: Request and you shall receive.

## coreboot & friends and Coverity Scan

coreboot, flashrom, Chromium EC and other projects of that family have
been made Coverity aware, that is, their build systems support building
with a custom compiler configuration passed in “just right” to enable
Coverity to add its hooks.

The public coreboot CI system at
[https://qa.coreboot.org/](https://qa.coreboot.org/) regularly does
builds with Coverity and sends them off to Coverity Scan.

Specifically, it covers:

* Chromium EC: [Coverity Scan site][crECCoverity] ([build job][crECBuildJob])
* coreboot: [Coverity Scan site][corebootCoverity] ([build job][corebootBuildJob]), [scan-build output][corebootScanBuild] ([build job][corebootScanBuildJob])
* em100: [Coverity Scan site][em100Coverity] ([build job][em100BuildJob])
* fcode-utils: [Coverity Scan site][fcodeUtilsCoverity] ([build job][fcodeUtilsBuildJob])
* flashrom: [Coverity Scan site][flashromCoverity] ([build job][flashromBuildJob])
* memtest86+: [Coverity Scan site][memtestCoverity] ([build job][memtestBuildJob])
* vboot: [Coverity Scan site][vbootCoverity] ([build job][vbootBuildJob])

[crECCoverity]: https://scan.coverity.com/projects/chromium-ec
[corebootCoverity]: https://scan.coverity.com/projects/coreboot
[em100Coverity]: https://scan.coverity.com/projects/em100
[fcodeUtilsCoverity]: https://scan.coverity.com/projects/fcode-utils
[flashromCoverity]: https://scan.coverity.com/projects/flashrom
[memtestCoverity]: https://scan.coverity.com/projects/memtest86
[vbootCoverity]: https://scan.coverity.com/projects/vboot

[corebootScanBuild]: https://www.coreboot.org/scan-build/

[crECBuildJob]: https://qa.coreboot.org/view/coverity/job/ChromeEC-Coverity/
[corebootBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot-coverity/
[corebootScanBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot_scanbuild/
[em100BuildJob]: https://qa.coreboot.org/view/coverity/job/em100-coverity/
[fcodeUtilsBuildJob]: https://qa.coreboot.org/view/coverity/job/fcode-utils-coverity/
[flashromBuildJob]: https://qa.coreboot.org/view/coverity/job/flashrom-coverity/
[memtestBuildJob]: https://qa.coreboot.org/view/coverity/job/memtest86plus-coverity/
[vbootBuildJob]: https://qa.coreboot.org/view/coverity/job/vboot-coverity/

Some projects (e.g. Chromium EC) build a different subset of boards on
each run, ensuring that everything is analyzed eventually. The downside
is that coverity issues pop up and disappear somewhat randomly as they
are discovered and go unnoticed in a later build.

More projects that are hosted on review.coreboot.org (potentially as a
mirror, like vboot and EC) could be served through that pipeline. Reach
out to {stepan,patrick,martin}@coreboot.org.
1 change: 1 addition & 0 deletions Documentation/infrastructure/index.md
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Expand Up @@ -4,3 +4,4 @@ This section contains documentation about coreboot infrastructure

## Jenkins builders and builds
* [Setting up Jenkins build machines](builders.md)
* [Coverity Scan integration](coverity.md)
2 changes: 1 addition & 1 deletion Documentation/mainboard/acer/g43t-am3.md
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Expand Up @@ -124,7 +124,7 @@ $ sudo flashrom \

```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
:doc:`../../tutorial/flashing_firmware/index`.
```

### External flashing
Expand Down
4 changes: 2 additions & 2 deletions Documentation/mainboard/asrock/h110m-dvs.md
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Expand Up @@ -58,7 +58,7 @@ The main SPI flash can be accessed using [flashrom]. By default, only
the BIOS region of the flash is writable. If you wish to change any
other region, such as the Management Engine or firmware descriptor, then
an external programmer is required (unless you find a clever way around
the flash protection). More information about this [here](../../flash_tutorial/index.md).
the flash protection). More information about this [here](../../tutorial/flashing_firmware/index.md).

### External programming

Expand Down Expand Up @@ -131,4 +131,4 @@ facing towards the bottom of the board.
[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
[MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2064Mb,%20v1.4.pdf
[flashrom]: https://flashrom.org/Flashrom
[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
[H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
2 changes: 1 addition & 1 deletion Documentation/mainboard/asrock/h77pro4-m.md
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Expand Up @@ -115,7 +115,7 @@ region is not readable even by the host.

```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
:doc:`../../tutorial/flashing_firmware/index`.
```

## Hardware monitoring and fan control
Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/asrock/h81m-hds.md
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Expand Up @@ -130,4 +130,4 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
[flashrom]: https://flashrom.org/Flashrom
[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
[Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
6 changes: 3 additions & 3 deletions Documentation/mainboard/asus/f2a85-m.md
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Expand Up @@ -190,9 +190,9 @@ This version is usable for all the GPUs.
- [Board manual]
- Flash chip datasheet [W25Q64FV]

[ASUS F2A85-M]: https://www.asus.com/Motherboards/F2A85M/
[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
[ASUS F2A85-M]: https://web.archive.org/web/20160320065008/http://www.asus.com/Motherboards/F2A85M/
[Board manual]: https://web.archive.org/web/20211028063105/https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
[flashrom]: https://flashrom.org/Flashrom
[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
[W25Q64FV]: https://web.archive.org/web/20220127184640/https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
2 changes: 1 addition & 1 deletion Documentation/mainboard/asus/p5q.md
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Expand Up @@ -130,5 +130,5 @@ You can also control the CPU fan with similar rules:
echo 2000 >/sys/class/hwmon/hwmon2/pwm1_tolerance

[ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
[this guide]: ../../tutorial/flashing_firmware/int_flashrom.md
[kernel docs]: https://www.kernel.org/doc/Documentation/hwmon/w83627ehf.rst
2 changes: 1 addition & 1 deletion Documentation/mainboard/asus/p8h61-m_lx.md
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Expand Up @@ -106,6 +106,6 @@ region is not readable even by the host.
- [Flash chip datasheet][W25Q32BV]

[ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
[W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
[flashrom]: https://flashrom.org/Flashrom
[Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip
6 changes: 3 additions & 3 deletions Documentation/mainboard/emulation/qemu-riscv.md
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@@ -1,8 +1,8 @@
# Qemu RISC-V emulator
# QEMU RISC-V emulator

## Building coreboot and running it in Qemu
## Building coreboot and running it in QEMU

- Configure coreboot and run `make` as usual
- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
convert coreboot to an ELF that Qemu can load
convert coreboot to an ELF that QEMU can load
- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`
2 changes: 1 addition & 1 deletion Documentation/mainboard/gigabyte/ga-g41m-es2l.md
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Expand Up @@ -142,7 +142,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)

```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
:doc:`../../tutorial/flashing_firmware/index`.
```

### Do backup
Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/hp/2560p.md
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Expand Up @@ -94,6 +94,6 @@ Schematic of this laptop can be found on [Lab One].

[HP EliteBook 2560p]: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201
[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03011618
[flashing tutorial]: ../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
[Lab One]: https://www.laboneinside.com/hp-elitebook-2560p-schematic-diagram/
[bug #141]: https://ticket.coreboot.org/issues/141
12 changes: 8 additions & 4 deletions Documentation/mainboard/index.md
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Expand Up @@ -48,10 +48,11 @@ This section contains documentation about coreboot on specific mainboards.
The boards in this section are not real mainboards, but emulators.

- [Spike RISC-V emulator](emulation/spike-riscv.md)
- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
- [Qemu x86 Q35](emulation/qemu-q35.md)
- [Qemu x86 PC](emulation/qemu-i440fx.md)
- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
- [QEMU x86 Q35](emulation/qemu-q35.md)
- [QEMU x86 PC](emulation/qemu-i440fx.md)
- [QEMU POWER9](emulation/qemu-power9.md)

## Facebook

Expand Down Expand Up @@ -179,10 +180,13 @@ The boards in this section are not real mainboards, but emulators.

## Star Labs Systems

- [LabTop Mk IV](starlabs/labtop_cml.md)
- [StarLite Mk III](starlabs/lite_glk.md)
- [StarBook Mk V](starlabs/starbook_tgl.md)

## Supermicro

- [X9SAE](supermicro/x9sae.md)
- [X10SLM+-F](supermicro/x10slm-f.md)
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
Expand Down
4 changes: 2 additions & 2 deletions Documentation/mainboard/lenovo/Ivy_Bridge_series.md
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Expand Up @@ -38,7 +38,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
* ROM chip size should be set to 12MiB.

```eval_rst
Please also have a look at :doc:`../../flash_tutorial/index`.
Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
```

## Splitting the coreboot.rom
Expand Down Expand Up @@ -90,4 +90,4 @@ Tests on Lenovo W530 showed no issues with a stripped and shrunken ME firmware.


[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
[external programmer]: ../../flash_tutorial/index.md
[external programmer]: ../../tutorial/flashing_firmware/index.md
4 changes: 2 additions & 2 deletions Documentation/mainboard/lenovo/Sandy_Bridge_series.md
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Expand Up @@ -70,5 +70,5 @@ the remaining space for the `bios` partition.


[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
[external programmer]: ../../flash_tutorial/index.md
[flashing tutorial]: ../../flash_tutorial/index.md
[external programmer]: ../../tutorial/flashing_firmware/index.md
[flashing tutorial]: ../../tutorial/flashing_firmware/index.md
9 changes: 6 additions & 3 deletions Documentation/mainboard/lenovo/ivb_internal_flashing.md
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Expand Up @@ -353,9 +353,12 @@ Verify that it worked:

Bingo!

Now you can [flash internally](/flash_tutorial/int_flashrom.md).
Remember to flash only the `bios` region (use `--ifd -i bios -N`
flashrom arguments). `fd` and `me` are still locked.
Now you can [flash internally]. Remember to flash only the `bios` region
(use `--ifd -i bios -N` flashrom arguments). `fd` and `me` are still
locked.

Note that you should have an external SPI programmer as a backup method.
It will help you recover if you flash non-working ROM by mistake.


[flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/t410.md
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Expand Up @@ -37,7 +37,7 @@ The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG.
Do not rely on dots painted in the corner of the chip (such as the blue dot
pictured) to orient the pins!

[Flashing tutorial](../../flash_tutorial/no_ext_power.md)
[Flashing tutorial](../../tutorial/flashing_firmware/no_ext_power.md)

Steps to access the flash IC are described here [T4xx series].

Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/t420.md
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Expand Up @@ -53,5 +53,5 @@ Steps to access the flash IC are described here [T4xx series].
* Suspend (Windows 10)

[T4xx series]: t4xx_series.md
[flashing tutorial]: ../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/t430.md
View file
Expand Up @@ -9,6 +9,6 @@ the general [flashing tutorial].

Steps to access the flash IC are described here [T4xx series].

[flashing tutorial]: ../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
[T4xx series]: t4xx_series.md
[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/w530.md
View file
Expand Up @@ -22,5 +22,5 @@ the general [flashing tutorial].

[w530-2]: w530-2.jpg

[flashing tutorial]: ../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
[T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/x1.md
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Expand Up @@ -18,5 +18,5 @@ the general [flashing tutorial].
Steps to access the flash IC are described here [X2xx series].

[X2xx series]: x2xx_series.md
[flashing tutorial]: ../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
[T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/x230s.md
View file
Expand Up @@ -16,4 +16,4 @@ is located at the circled place.

Unlike [most Ivy Bridge ThinkPads](Ivy_Bridge_series.md), X230s has a single 16MiB SPI flash chip.

The general [flashing tutorial](../../flash_tutorial/index.md) has more details.
The general [flashing tutorial](../../tutorial/flashing_firmware/index.md) has more details.
2 changes: 1 addition & 1 deletion Documentation/mainboard/lenovo/x301.md
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Expand Up @@ -43,5 +43,5 @@ Tested:
Linux payload (Heads) and SeaBIOS.


[flashing tutorial]: ../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

3 changes: 2 additions & 1 deletion Documentation/mainboard/msi/ms7707/ms7707.md
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Expand Up @@ -74,7 +74,7 @@ seconds. Setting the jumper alone is not enough (the Fintek is VBAT backed).
Put all back in place and restart the board. It might need 1-2 AC power cycles
to reinitialize (running at full fan speed - don't panic).
* External flashing has been tested with RPi2 without main power connected.
3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html).
3.3V provided by RPi2. Read more about [flashing methods].
* In case of going back to proprietary BIOS create/save CMOS settings as early
as possible (do not leave BIOS on first start without saving settings).
The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state
Expand Down Expand Up @@ -110,3 +110,4 @@ needed (internally re-routed already).
[Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
[Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html
[flashlayout]: flashlayout.svg
[flashing methods]: ../../../tutorial/flashing_firmware/index.md
2 changes: 1 addition & 1 deletion Documentation/mainboard/prodrive/hermes.md
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Expand Up @@ -49,6 +49,6 @@ The board features:
## Extra links

[flashrom]: https://flashrom.org/Flashrom
[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
[AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440
71 changes: 71 additions & 0 deletions Documentation/mainboard/starlabs/common/flashing.md
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@@ -0,0 +1,71 @@
# Flashing with fwupd

#### **Requirements:**

* fwupd version 1.5.6 or later
* The battery must be charged to at least 30%
* The charger must be connected (either USB-C or DC Jack)
* BIOS Lock must be disabled
* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)

**fwupd 1.5.6 or later**
To check the version of **fwupd** you have installed, open a terminal window and enter the below command:

```
fwupdmgr --version
```

This will show the version number. **1.5.6** or greater will work.
![fwupd version](fwupdVersion.png)
On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:

```
sudo add-apt-repository ppa:starlabs/ppa
sudo apt update
sudo apt install fwupd
```

On Manjaro:

```
sudo pacman -Sy fwupd-git flashrom-starlabs
```

Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.

**Disable BIOS Lock**
BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:

1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
3\. Press `Enter` to change this setting from **Enabled** to **Disabled**

![Disable BIOS Lock](BiosLock.jpg)

4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.

#### **Switching Branch**

Switching branch refers to changing from AMI firmware to coreboot, or vice versa.

First, check for new firmware files with the below terminal command:

```
fwupdmgr refresh --force
```

Then, to change branch, enter the below terminal command:

```
fwupdmgr switch-branch
```

You can then select which branch you would like to use, by typing in the corresponding number:
![Switch Branch](SwitchBranch.png)
You will be prompted to confirm, press `y` to continue or `n` to cancel.

Once the switch has been completed, you will be prompted to restart.

The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.

You can switch branch at any time.
87 changes: 87 additions & 0 deletions Documentation/mainboard/starlabs/labtop_cml.md
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@@ -0,0 +1,87 @@
# Star LabTop Mk IV

## Specs

- CPU (full processor specs available at https://ark.intel.com)
- Intel i7-10710U (Comet Lake)
- Intel i3-10110U (Comet Lake)
- EC
- ITE IT8987E
- Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
- Battery
- Charger, using AC adapter or USB-C PD
- Suspend / resume
- GPU
- Intel UHD Graphics 620
- GOP driver is recommended, VBT is provided
- eDP 13-inch 1920x1080 LCD
- HDMI video
- USB-C DisplayPort video
- Memory
- 16GB on-board *1
- Networking
- AX201 CNVi WiFi / Bluetooth soldered to PCBA
- Sound
- Realtek ALC256
- Internal speakers
- Internal microphone
- Combined headphone / microphone 3.5-mm jack
- HDMI audio
- USB-C DisplayPort audio
- Storage
- M.2 PCIe SSD
- RTS5129 MicroSD card reader
- USB
- 1280x720 CCD camera
- USB 3.1 Gen 2 Type-C (left)
- USB 3.1 Gen 2 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)

[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c`

## Building coreboot

### Preliminaries

Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)

The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)

These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.

### Build

The following commands will build a working image:

```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
make
```

## Flashing coreboot

```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Vendor | Winbond |
+---------------------+------------+
| Model | 25Q128JVSQ |
+---------------------+------------+
| Size | 16 MiB |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
83 changes: 83 additions & 0 deletions Documentation/mainboard/starlabs/lite_glk.md
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@@ -0,0 +1,83 @@
# StarLite Mk III

## Specs
- CPU (full processor specs available at https://ark.intel.com)
- Intel N5000 (Gemini Lake)
- EC
- ITE IT8987E
- Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
- Battery
- Charger, using AC adapter or USB-C PD
- Suspend / resume
- GPU
- Intel UHD Graphics 605
- GOP driver is recommended, VBT is provided
- eDP 11.6-inch 1920x1080 LCD
- HDMI video
- USB-C DisplayPort video
- Memory
- 8GB on-board
- Networking
- 9462 CNVi WiFi / Bluetooth soldered to PCBA
- Sound
- Realtek ALC269
- Internal speakers
- Internal microphone
- Combined headphone / microphone 3.5-mm jack
- HDMI audio
- USB-C DisplayPort audio
- Storage
- M.2 SATA SSD
- RTS5129 MicroSD card reader
- USB
- 640x480 CCD camera
- USB 3.1 Gen 1 Type-C (left)
- USB 3.1 Gen 1 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)

## Building coreboot

### Preliminaries

Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)

The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)

These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.

### Build

The following commands will build a working image:

```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
make
```

## Flashing coreboot

```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Vendor | Gigadevice |
+---------------------+------------+
| Model | GD25LQ64(B)|
+---------------------+------------+
| Size | 8 MiB |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
70 changes: 1 addition & 69 deletions Documentation/mainboard/starlabs/starbook_tgl.md
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Expand Up @@ -83,72 +83,4 @@ make
| External flashing | yes |
+---------------------+------------+
#### **Requirements:**
* fwupd version 1.5.6 or later
* The battery must be charged to at least 30%
* The charger must be connected (either USB-C or DC Jack)
* BIOS Lock must be disabled
* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)
**fwupd 1.5.6 or later**
To check the version of **fwupd** you have installed, open a terminal window and enter the below command:
```
fwupdmgr --version
```
This will show the version number. **1.5.6** or greater will work.
![fwupd version](fwupdVersion.png)
On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
```
sudo add-apt-repository ppa:starlabs/ppa
sudo apt update
sudo apt install fwupd
```
On Manjaro:
```
sudo pacman -Sy fwupd-git flashrom-starlabs
```
Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.
**Disable BIOS Lock**
BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:
1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
![Disable BIOS Lock](BiosLock.jpg)
4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
#### **Switching Branch**
Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
First, check for new firmware files with the below terminal command:
```
fwupdmgr refresh --force
```
Then, to change branch, enter the below terminal command:
```
fwupdmgr switch-branch
```
You can then select which branch you would like to use, by typing in the corresponding number:
![Switch Branch](SwitchBranch.png)
You will be prompted to confirm, press `y` to continue or `n` to cancel.
Once the switch has been completed, you will be prompted to restart.
The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.
You can switch branch at any time.
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
2 changes: 1 addition & 1 deletion Documentation/mainboard/supermicro/x10slm-f.md
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Expand Up @@ -42,7 +42,7 @@ Now, run `make` to build the coreboot image.

```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
:doc:`../../tutorial/flashing_firmware/index`.
```

### Internal programming
Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
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Expand Up @@ -56,6 +56,6 @@ These issues apply to all boards. Have a look at the board-specific issues, too.
[Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
[OpenBMC]: https://www.openbmc.org/
[flashrom]: https://flashrom.org/Flashrom
[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
8 changes: 4 additions & 4 deletions Documentation/mainboard/supermicro/x9sae.md
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Expand Up @@ -41,10 +41,9 @@ first, otherwise ME may write something back and break the firmware you write.
The following command may be used to flash coreboot. (To do so, linux kernel
could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module)

Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is
recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom
arguments), in order to minimize the chances of messing something up in the
beginning.
Now you can [flash internally]. It is recommended to flash only the `bios`
region (use `--ifd -i bios -N` flashrom arguments), in order to minimize the
chances of messing something up in the beginning.

The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy
to do in-system programming, or remove and flash externally if it is socketed.
Expand Down Expand Up @@ -106,3 +105,4 @@ seems that it shall not appear on X9SAE even if it is defined.
[X9SAE-V]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
[W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
[flashrom]: https://flashrom.org/Flashrom
[flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md
2 changes: 1 addition & 1 deletion Documentation/northbridge/intel/sandybridge/me_cleaner.md
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Expand Up @@ -81,4 +81,4 @@ Make sure to include all partitions into the ROM:
* ME
* BIOS

[external programmer]: ../../../flash_tutorial/index.md
[external programmer]: ../../../tutorial/flashing_firmware/index.md
4 changes: 4 additions & 0 deletions Documentation/releases/checklist.md
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@@ -1,3 +1,7 @@
```eval_rst
:orphan:
```

# coreboot Release Process

This document describes our release process and all prerequisites to implement
Expand Down
2 changes: 1 addition & 1 deletion Documentation/releases/coreboot-4.15-relnotes.md
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Expand Up @@ -25,7 +25,7 @@ New mainboards
* Google nipperkin
* Lenovo w541
* Siemens mc_ehl
* SuperMicro x9sae
* Supermicro x9sae
* System76 addw1
* System76 addw2
* System76 bonw14
Expand Down
4 changes: 4 additions & 0 deletions Documentation/releases/templates.md
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@@ -1,3 +1,7 @@
```eval_rst
:orphan:
```

# Communication templates related to release management

## Deprecation notices
Expand Down
1 change: 1 addition & 0 deletions Documentation/security/vboot/list_vboot.md
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Expand Up @@ -206,6 +206,7 @@
- Stout (Lenovo Thinkpad X131e Chromebook)
- Bubs
- Coachz
- Gelarshie
- Homestar
- Kingoftown
- Lazor
Expand Down
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0 ...entation/flash_tutorial/ext_standalone.md → ...orial/flashing_firmware/ext_standalone.md
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0 ...tion/flash_tutorial/flash_ic_no_diode.svg → ...l/flashing_firmware/flash_ic_no_diode.svg
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1 change: 1 addition & 0 deletions Documentation/tutorial/index.md
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Expand Up @@ -4,3 +4,4 @@
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)
2 changes: 1 addition & 1 deletion Documentation/tutorial/part1.md
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Expand Up @@ -12,7 +12,7 @@ Download, configure, and build coreboot
### Step 1 - Install tools and libraries needed for coreboot
$ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
$ sudo pacman -S base-devel curl git gcc-ada ncurses zlib
$ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel
$ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel patch

### Step 2 - Download coreboot source tree
$ git clone https://review.coreboot.org/coreboot
Expand Down
27 changes: 16 additions & 11 deletions MAINTAINERS
View file
Expand Up @@ -298,6 +298,14 @@ M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/intel/d510mo/

INTEL HARCUVAR_CRB MAINBOARD
M: Jeff Daly <jeffd@silicom-usa.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
S: Maintained
F: src/mainboard/intel/harcuvar/

INTEL STRAGO MAINBOARD
M: Hannah Williams <hannah.williams@intel.com>
S: Supported
Expand All @@ -322,7 +330,6 @@ F: src/mainboard/kontron/mal10/

LENOVO MAINBOARDS
M: Alexander Couzens <lynxis@fe80.eu>
M: Patrick Rudolph <siro@das-labor.org>
S: Maintained
F: src/mainboard/lenovo/

Expand Down Expand Up @@ -574,7 +581,6 @@ F: src/southbridge/amd/
F: src/include/cpu/amd/

INTEL SUPPORT
M: Patrick Rudolph <siro@das-labor.org>
S: Maintained
F: src/vendorcode/intel/
F: src/cpu/intel/
Expand All @@ -584,15 +590,6 @@ F: src/soc/intel/
F: src/drivers/intel/
F: src/include/cpu/intel/

INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: Michal Motyl <michalx.motyl@intel.com>
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
S: Maintained
F: src/mainboard/intel/harcuvar/
F: src/soc/intel/denverton_ns/

INTEL FSP 1.1
M: Lee Leahy <leroy.p.leahy@intel.com>
M: Huang Jin <huang.jin@intel.com>
Expand Down Expand Up @@ -672,6 +669,14 @@ S: Maintained
F: /src/soc/intel/braswell/
F: /src/vendorcode/intel/fsp/fsp1_1/braswell/

INTEL DENVERTON-NS SOC
M: Jeff Daly <jeffd@silicom-usa.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
S: Maintained
F: src/soc/intel/denverton_ns/

INTEL TIGERLAKE SOC
M: Tim Wawrzynczak <twawrzynczak@chromium.org>
S: Maintained
Expand Down
1 change: 1 addition & 0 deletions Makefile
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Expand Up @@ -193,6 +193,7 @@ strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
real-all: real-target

# must come rather early
.SECONDARY:
.SECONDEXPANSION:
.DELETE_ON_ERROR:

Expand Down
7 changes: 5 additions & 2 deletions Makefile.inc
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Expand Up @@ -791,11 +791,14 @@ endif
$(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
cp $< $@

$(objcbfs)/%.elf: $(objcbfs)/%.debug
$(objcbfs)/%.map: $(objcbfs)/%.debug
$(eval class := $(call find-class,$(@F)))
$(NM_$(class)) -n $< | sort > $(basename $@).map

$(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
$(eval class := $(call find-class,$(@F)))
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
cp $< $@.tmp
$(NM_$(class)) -n $@.tmp | sort > $(basename $@).map
$(OBJCOPY_$(class)) --strip-debug $@.tmp
$(OBJCOPY_$(class)) --add-gnu-debuglink=$< $@.tmp
mv $@.tmp $@
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_CBFS_SIZE=0x00200000
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,157b"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.1"
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/SeaBIOS/Kconfig
View file
Expand Up @@ -5,7 +5,7 @@ choice
default SEABIOS_STABLE

config SEABIOS_STABLE
bool "1.14.0"
bool "1.16.0"
help
Stable SeaBIOS version
config SEABIOS_MASTER
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/SeaBIOS/Makefile
View file
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0
TAG-$(CONFIG_SEABIOS_STABLE)=d239552ce7220e448ae81f41515138f7b9e3c4db
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)

project_git_repo=https://github.com/pcengines/seabios.git
Expand Down
4 changes: 2 additions & 2 deletions payloads/external/iPXE/Kconfig
View file
Expand Up @@ -31,12 +31,12 @@ choice
depends on BUILD_IPXE

config IPXE_STABLE
bool "2019.3"
bool "2022.1"
help
iPXE uses a rolling release with no stable version, for
reproducibility, use the last commit of a given month as the
'stable' version.
This is iPXE from the end of March, 2019.
This is iPXE from the end of January, 2022.

config IPXE_MASTER
bool "master"
Expand Down
4 changes: 2 additions & 2 deletions payloads/external/iPXE/Makefile
View file
@@ -1,8 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only

# 2019.3 - Last commit of March 2019
# 2022.1 - Last commit of January 2022
# When updating, change the name both here and in payloads/external/iPXE/Kconfig
STABLE_COMMIT_ID=ebf2eaf515e46abd43bc798e7e4ba77bfe529218
STABLE_COMMIT_ID=6ba671acd922ee046b257c5119b8a0f64d275473

TAG-$(CONFIG_IPXE_MASTER)=origin/master
TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID)
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/tianocore/Kconfig
View file
Expand Up @@ -127,7 +127,7 @@ config TIANOCORE_BOOT_MANAGER_ESCAPE
the default key of F2.

config TIANOCORE_BOOT_TIMEOUT
int
int "Set the timeout for boot menu prompt"
default 2
help
The length of time in seconds for which the boot splash/menu prompt will be displayed.
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/tianocore/Makefile
View file
Expand Up @@ -53,7 +53,7 @@ ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
endif
# PLATFORM_BOOT_TIMEOUT = 3
ifneq ($(TIANOCORE_BOOT_TIMEOUT),)
ifneq ($(CONFIG_TIANOCORE_BOOT_TIMEOUT),)
BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
endif
# SIO_BUS_ENABLE = FALSE
Expand Down
8 changes: 8 additions & 0 deletions payloads/libpayload/bin/lpgcc
View file
Expand Up @@ -182,6 +182,14 @@ trygccoption -fno-stack-protector
_CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
_CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"

if [ "$CONFIG_LP_VBOOT_LIB" = y ]; then
if [ "$CONFIG_LP_VBOOT_TPM2_MODE" = y ]; then
_CFLAGS="$_CFLAGS -DTPM2_MODE"
else
_CFLAGS="$_CFLAGS -DTPM1_MODE"
fi
fi

_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections"

if [ $DOLINK -eq 0 ]; then
Expand Down
36 changes: 24 additions & 12 deletions payloads/libpayload/drivers/cbmem_console.c
View file
Expand Up @@ -80,11 +80,28 @@ void cbmem_console_write(const void *buffer, size_t count)
do_write(buffer, count);
}

static void snapshot_putc(char *console, uint32_t *cursor, char c)
{
/* This is BIOS_LOG_IS_MARKER() from coreboot. Due to stupid
licensing restrictions, we can't use it directly. */
if (c >= 0x10 && c <= 0x18)
return;

/* Slight memory corruption may occur between reboots and give us a few
unprintable characters like '\0'. Replace them with '?' on output. */
if (!isprint(c) && !isspace(c))
console[*cursor] = '?';
else
console[*cursor] = c;

*cursor += 1;
}

char *cbmem_console_snapshot(void)
{
const struct cbmem_console *const console_p = phys_to_virt(cbmem_console_p);
char *console_c;
uint32_t size, cursor, overflow;
uint32_t size, cursor, overflow, newc, oldc;

if (!console_p) {
printf("ERROR: No cbmem console found in coreboot table\n");
Expand All @@ -104,24 +121,19 @@ char *cbmem_console_snapshot(void)
size);
return NULL;
}
console_c[size] = '\0';

newc = 0;
if (overflow) {
if (cursor >= size) {
printf("ERROR: CBMEM console struct is corrupted\n");
return NULL;
}
memcpy(console_c, console_p->body + cursor, size - cursor);
memcpy(console_c + size - cursor, console_p->body, cursor);
} else {
memcpy(console_c, console_p->body, size);
for (oldc = cursor; oldc < size; oldc++)
snapshot_putc(console_c, &newc, console_p->body[oldc]);
}

/* Slight memory corruption may occur between reboots and give us a few
unprintable characters like '\0'. Replace them with '?' on output. */
for (cursor = 0; cursor < size; cursor++)
if (!isprint(console_c[cursor]) && !isspace(console_c[cursor]))
console_c[cursor] = '?';
for (oldc = 0; oldc < size && oldc < cursor; oldc++)
snapshot_putc(console_c, &newc, console_p->body[oldc]);
console_c[newc] = '\0';

return console_c;
}
2 changes: 1 addition & 1 deletion payloads/libpayload/include/fmap.h
View file
Expand Up @@ -7,6 +7,6 @@
#include <stddef.h>

/* Looks for area with |name| in FlashMap. Requires lib_sysinfo.fmap_cache. */
cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size);
enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size);

#endif /* _FMAP_H */
1 change: 1 addition & 0 deletions payloads/libpayload/include/libpayload.h
View file
Expand Up @@ -46,6 +46,7 @@
#include <libpayload-config.h>
#include <cbgfx.h>
#include <commonlib/bsd/fmap_serialized.h>
#include <commonlib/bsd/mem_chip_info.h>
#include <ctype.h>
#include <die.h>
#include <endian.h>
Expand Down
1 change: 1 addition & 0 deletions payloads/libpayload/include/sysinfo.h
View file
Expand Up @@ -83,6 +83,7 @@ struct sysinfo_t {
uintptr_t compiler;
uintptr_t linker;
uintptr_t assembler;
uintptr_t mem_chip_base;

uintptr_t cb_version;

Expand Down
3 changes: 3 additions & 0 deletions payloads/libpayload/libc/coreboot.c
View file
Expand Up @@ -260,6 +260,9 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
case CBMEM_ID_TYPE_C_INFO:
info->type_c_info = cbmem_entry->address;
break;
case CBMEM_ID_MEM_CHIP_INFO:
info->mem_chip_base = cbmem_entry->address;
break;
default:
break;
}
Expand Down
6 changes: 3 additions & 3 deletions payloads/libpayload/libc/fmap.c
View file
Expand Up @@ -38,8 +38,8 @@
/* Private fmap cache. */
static struct fmap *_fmap_cache;

static cb_err_t fmap_find_area(struct fmap *fmap, const char *name, size_t *offset,
size_t *size)
static enum cb_err fmap_find_area(struct fmap *fmap, const char *name, size_t *offset,
size_t *size)
{
for (size_t i = 0; i < le32toh(fmap->nareas); ++i) {
if (strncmp((const char *)fmap->areas[i].name, name, FMAP_STRLEN) != 0)
Expand Down Expand Up @@ -71,7 +71,7 @@ static bool fmap_setup_cache(void)
return false;
}

cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size)
{
if (!_fmap_cache && !fmap_setup_cache())
return CB_ERR;
Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/libcbfs/cbfs.c
View file
Expand Up @@ -48,7 +48,7 @@ ssize_t _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mda
return CB_ERR;

size_t data_offset;
cb_err_t err = CB_CBFS_CACHE_FULL;
enum cb_err err = CB_CBFS_CACHE_FULL;
if (cbd->mcache_size)
err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size, name, mdata,
&data_offset);
Expand Down
20 changes: 10 additions & 10 deletions payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c
View file
Expand Up @@ -40,7 +40,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)

static size_t test_fmap_offset = 0;
static size_t test_fmap_size = 0;
static cb_err_t test_fmap_result = CB_SUCCESS;
static enum cb_err test_fmap_result = CB_SUCCESS;

static void set_fmap_locate_area_results(size_t offset, size_t size, size_t result)
{
Expand All @@ -49,15 +49,15 @@ static void set_fmap_locate_area_results(size_t offset, size_t size, size_t resu
test_fmap_result = result;
}

cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size)
{
*offset = test_fmap_offset;
*size = test_fmap_size;
return test_fmap_result;
}

cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
{
assert_non_null(mcache);
assert_true(mcache_size > 0 && mcache_size % CBFS_MCACHE_ALIGNMENT == 0);
Expand All @@ -66,7 +66,7 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *

check_expected(name);

cb_err_t ret = mock_type(cb_err_t);
enum cb_err ret = mock_type(enum cb_err);
if (ret != CB_SUCCESS)
return ret;

Expand All @@ -75,7 +75,7 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
return CB_SUCCESS;
}

static void expect_cbfs_mcache_lookup(const char *name, cb_err_t err,
static void expect_cbfs_mcache_lookup(const char *name, enum cb_err err,
const union cbfs_mdata *mdata, size_t data_offset_out)
{
expect_string(cbfs_mcache_lookup, name, name);
Expand All @@ -87,13 +87,13 @@ static void expect_cbfs_mcache_lookup(const char *name, cb_err_t err,
}
}

cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash)
enum cb_err cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash)
{
assert_non_null(dev);
check_expected(name);

cb_err_t ret = mock_type(cb_err_t);
enum cb_err ret = mock_type(enum cb_err);
if (ret != CB_SUCCESS)
return ret;

Expand All @@ -102,7 +102,7 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_o
return CB_SUCCESS;
}

static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata,
static void expect_cbfs_lookup(const char *name, enum cb_err err, const union cbfs_mdata *mdata,
size_t data_offset_out)
{
expect_string(cbfs_lookup, name, name);
Expand Down
14 changes: 7 additions & 7 deletions payloads/libpayload/tests/libcbfs/cbfs-verification-test.c
View file
Expand Up @@ -53,19 +53,19 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
return 0;
}

cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
{
return CB_CBFS_CACHE_FULL;
}

cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash)
enum cb_err cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash)
{
assert_non_null(dev);
check_expected(name);

cb_err_t ret = mock_type(cb_err_t);
enum cb_err ret = mock_type(enum cb_err);
if (ret != CB_SUCCESS)
return ret;

Expand All @@ -74,7 +74,7 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_o
return CB_SUCCESS;
}

static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata,
static void expect_cbfs_lookup(const char *name, enum cb_err err, const union cbfs_mdata *mdata,
size_t data_offset_out)
{
expect_string(cbfs_lookup, name, name);
Expand All @@ -91,7 +91,7 @@ const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, siz
return mock_ptr_type(void *);
}

cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size)
enum cb_err fmap_locate_area(const char *name, size_t *offset, size_t *size)
{
*offset = 0;
*size = 0;
Expand Down
10 changes: 10 additions & 0 deletions spd/lp5/memory_parts.json
View file
Expand Up @@ -49,6 +49,16 @@
"ranksPerChannel": 1,
"speedMbps": 6400
}
},
{
"name": "MT62F2G32D8DR-031 WT:B",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 8,
"bitWidthPerChannel": 8,
"ranksPerChannel": 2,
"speedMbps": 6400
}
}
]
}
1 change: 1 addition & 0 deletions spd/lp5/set-0/parts_spd_manifest.generated.txt
View file
Expand Up @@ -6,3 +6,4 @@ MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex
H9JCNNNBK3MLYR-N6E,spd-1.hex
MT62F2G32D8DR-031 WT:B,spd-4.hex
32 changes: 32 additions & 0 deletions spd/lp5/set-0/spd-4.hex
View file
@@ -0,0 +1,32 @@
23 10 13 0E 15 22 F9 08 00 00 00 00 09 01 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1 change: 1 addition & 0 deletions spd/lp5/set-1/parts_spd_manifest.generated.txt
View file
Expand Up @@ -6,3 +6,4 @@ MT62F1G32D4DR-031 WT:B,spd-2.hex
H9JCNNNCP3MLYR-N6E,spd-2.hex
K3LKBKB0BM-MGCP,spd-3.hex
H9JCNNNBK3MLYR-N6E,spd-1.hex
MT62F2G32D8DR-031 WT:B,spd-4.hex
4 changes: 2 additions & 2 deletions spd/lp5/set-1/spd-1.hex
View file
@@ -1,11 +1,11 @@
23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand Down
4 changes: 2 additions & 2 deletions spd/lp5/set-1/spd-2.hex
View file
@@ -1,11 +1,11 @@
23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand Down
4 changes: 2 additions & 2 deletions spd/lp5/set-1/spd-3.hex
View file
@@ -1,11 +1,11 @@
23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand Down
32 changes: 32 additions & 0 deletions spd/lp5/set-1/spd-4.hex
View file
@@ -0,0 +1,32 @@
23 11 13 0E 85 21 F9 18 00 40 00 00 09 02 00 00
00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
31 changes: 15 additions & 16 deletions src/acpi/acpi.c
View file
Expand Up @@ -13,22 +13,22 @@
* in coreboot.
*/

#include <console/console.h>
#include <string.h>
#include <acpi/acpi.h>
#include <acpi/acpi_ivrs.h>
#include <acpi/acpigen.h>
#include <arch/hpet.h>
#include <arch/mmio.h>
#include <device/pci.h>
#include <cbfs.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <commonlib/sort.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cbfs.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <pc80/mc146818rtc.h>
#include <string.h>
#include <types.h>
#include <version.h>
#include <commonlib/sort.h>
#include <pc80/mc146818rtc.h>

static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp);

Expand Down Expand Up @@ -224,15 +224,6 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
return lapic_nmi->length;
}

__weak uintptr_t cpu_get_lapic_addr(void)
{
/*
* If an architecture does not support LAPIC, this weak implementation returns LAPIC
* addr as 0.
*/
return 0;
}

void acpi_create_madt(acpi_madt_t *madt)
{
acpi_header_t *header = &(madt->header);
Expand Down Expand Up @@ -1591,6 +1582,13 @@ void preload_acpi_dsdt(void)
cbfs_preload(file);
}

static uintptr_t coreboot_rsdp;

uintptr_t get_coreboot_rsdp(void)
{
return coreboot_rsdp;
}

unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
Expand Down Expand Up @@ -1698,6 +1696,7 @@ unsigned long write_acpi_tables(unsigned long start)

/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
coreboot_rsdp = (uintptr_t)rsdp;
current += sizeof(acpi_rsdp_t);
current = acpi_align_current(current);
rsdt = (acpi_rsdt_t *) current;
Expand Down
6 changes: 6 additions & 0 deletions src/arch/arm/include/armv4/arch/mmio.h
View file
Expand Up @@ -24,6 +24,9 @@ static inline uint32_t read32(const void *addr)
return *(volatile uint32_t *)addr;
}

/* Not supported */
uint64_t read64(const void *addr);

static inline void write8(void *addr, uint8_t val)
{
*(volatile uint8_t *)addr = val;
Expand All @@ -39,4 +42,7 @@ static inline void write32(void *addr, uint32_t val)
*(volatile uint32_t *)addr = val;
}

/* Not supported */
void write64(void *addr, uint64_t val);

#endif /* __ARCH_MMIO_H__ */
6 changes: 6 additions & 0 deletions src/arch/arm/include/armv7/arch/mmio.h
View file
Expand Up @@ -29,6 +29,9 @@ static inline uint32_t read32(const void *addr)
return *(volatile uint32_t *)__builtin_assume_aligned(addr, sizeof(uint32_t));
}

/* Not supported */
uint64_t read64(const void *addr);

static inline void write8(void *addr, uint8_t val)
{
dmb();
Expand All @@ -50,4 +53,7 @@ static inline void write32(void *addr, uint32_t val)
dmb();
}

/* Not supported */
void write64(void *addr, uint64_t val);

#endif /* __ARCH_MMIO_H__ */
2 changes: 1 addition & 1 deletion src/arch/arm64/romstage.c
View file
Expand Up @@ -12,7 +12,7 @@ __weak void platform_romstage_postram(void) { /* no-op */ }

void main(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
timestamp_add_now(TS_ROMSTAGE_START);

console_init();
exception_init();
Expand Down
6 changes: 3 additions & 3 deletions src/arch/x86/bootblock_normal.c
View file
Expand Up @@ -12,7 +12,7 @@ static const char *get_fallback(const char *stagelist)
return ++stagelist;
}

int legacy_romstage_select_and_load(struct prog *romstage)
enum cb_err legacy_romstage_select_and_load(struct prog *romstage)
{
static const char *default_filenames = "normal/romstage\0fallback/romstage";
const char *boot_candidate;
Expand All @@ -24,8 +24,8 @@ int legacy_romstage_select_and_load(struct prog *romstage)

if (do_normal_boot()) {
romstage->name = boot_candidate;
if (!cbfs_prog_stage_load(romstage))
return 0;
if (cbfs_prog_stage_load(romstage) == CB_SUCCESS)
return CB_SUCCESS;
}

romstage->name = get_fallback(boot_candidate);
Expand Down
40 changes: 0 additions & 40 deletions src/arch/x86/include/arch/mmio.h
View file
Expand Up @@ -45,44 +45,4 @@ static __always_inline void write64(volatile void *addr, uint64_t value)
*((volatile uint64_t *)(addr)) = value;
}

static __always_inline uint8_t read8p(const uintptr_t addr)
{
return read8((void *)addr);
}

static __always_inline uint16_t read16p(const uintptr_t addr)
{
return read16((void *)addr);
}

static __always_inline uint32_t read32p(const uintptr_t addr)
{
return read32((void *)addr);
}

static __always_inline uint64_t read64p(const uintptr_t addr)
{
return read64((void *)addr);
}

static __always_inline void write8p(const uintptr_t addr, const uint8_t value)
{
write8((void *)addr, value);
}

static __always_inline void write16p(const uintptr_t addr, const uint16_t value)
{
write16((void *)addr, value);
}

static __always_inline void write32p(const uintptr_t addr, const uint32_t value)
{
write32((void *)addr, value);
}

static __always_inline void write64p(const uintptr_t addr, const uint64_t value)
{
write64((void *)addr, value);
}

#endif /* __ARCH_MMIO_H__ */
2 changes: 1 addition & 1 deletion src/arch/x86/postcar.c
View file
Expand Up @@ -30,7 +30,7 @@ void main(void)
if (!cbmem_online())
cbmem_initialize();

timestamp_add_now(TS_START_POSTCAR);
timestamp_add_now(TS_POSTCAR_START);

display_mtrrs();

Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/postcar_loader.c
View file
Expand Up @@ -192,7 +192,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
load_postcar_cbfs(&prog, pcf);

/* As postcar exist, it's end of romstage here */
timestamp_add_now(TS_END_ROMSTAGE);
timestamp_add_now(TS_ROMSTAGE_END);

console_time_report();

Expand Down
14 changes: 7 additions & 7 deletions src/commonlib/bsd/cbfs_mcache.c
View file
Expand Up @@ -40,8 +40,8 @@ struct cbfs_mcache_build_args {
int count;
};

static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata,
size_t already_read, void *arg)
static enum cb_err build_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata,
size_t already_read, void *arg)
{
struct cbfs_mcache_build_args *args = arg;
union mcache_entry *entry = args->mcache;
Expand All @@ -62,8 +62,8 @@ static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mda
return CB_CBFS_NOT_FOUND;
}

cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size,
struct vb2_hash *metadata_hash)
enum cb_err cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size,
struct vb2_hash *metadata_hash)
{
struct cbfs_mcache_build_args args = {
.mcache = mcache,
Expand All @@ -73,7 +73,7 @@ cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size,
};

assert(size > sizeof(uint32_t) && IS_ALIGNED((uintptr_t)mcache, CBFS_MCACHE_ALIGNMENT));
cb_err_t ret = cbfs_walk(dev, build_walker, &args, metadata_hash, 0);
enum cb_err ret = cbfs_walk(dev, build_walker, &args, metadata_hash, 0);
union mcache_entry *entry = args.mcache;
if (ret == CB_CBFS_NOT_FOUND) {
ret = CB_SUCCESS;
Expand All @@ -88,8 +88,8 @@ cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size,
return ret;
}

cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
{
const size_t namesize = strlen(name) + 1; /* Count trailing \0 so we can memcmp() it. */
const void *end = mcache + mcache_size;
Expand Down
28 changes: 14 additions & 14 deletions src/commonlib/bsd/cbfs_private.c
View file
Expand Up @@ -3,8 +3,8 @@
#include <commonlib/bsd/cbfs_private.h>
#include <assert.h>

static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer,
const size_t devsize)
static enum cb_err read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_file *buffer,
const size_t devsize)
{
DEBUG("Looking for next file @%#zx...\n", *offset);
*offset = ALIGN_UP(*offset, CBFS_ALIGNMENT);
Expand All @@ -22,10 +22,10 @@ static cb_err_t read_next_header(cbfs_dev_t dev, size_t *offset, struct cbfs_fil
return CB_CBFS_NOT_FOUND;
}

cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset,
const union cbfs_mdata *mdata,
size_t already_read, void *arg),
void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags flags)
enum cb_err cbfs_walk(cbfs_dev_t dev, enum cb_err (*walker)(cbfs_dev_t dev, size_t offset,
const union cbfs_mdata *mdata,
size_t already_read, void *arg),
void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags flags)
{
const bool do_hash = CBFS_ENABLE_HASHING && metadata_hash;
const size_t devsize = cbfs_dev_size(dev);
Expand All @@ -39,8 +39,8 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
}

size_t offset = 0;
cb_err_t ret_header;
cb_err_t ret_walker = CB_CBFS_NOT_FOUND;
enum cb_err ret_header;
enum cb_err ret_walker = CB_CBFS_NOT_FOUND;
union cbfs_mdata mdata;
while ((ret_header = read_next_header(dev, &offset, &mdata.h, devsize)) == CB_SUCCESS) {
const uint32_t attr_offset = be32toh(mdata.h.attributes_offset);
Expand Down Expand Up @@ -113,8 +113,8 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
return ret_walker;
}

cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src,
size_t already_read, cbfs_dev_t dev, size_t offset)
enum cb_err cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src,
size_t already_read, cbfs_dev_t dev, size_t offset)
{
/* First, copy the stuff that cbfs_walk() already read for us. */
memcpy(dst, src, already_read);
Expand All @@ -135,8 +135,8 @@ struct cbfs_lookup_args {
size_t *data_offset_out;
};

static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata,
size_t already_read, void *arg)
static enum cb_err lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata,
size_t already_read, void *arg)
{
struct cbfs_lookup_args *args = arg;
/* Check if the name we're looking for could fit, then we can safely memcmp() it. */
Expand All @@ -152,8 +152,8 @@ static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_md
return CB_SUCCESS;
}

cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash)
enum cb_err cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash)
{
struct cbfs_lookup_args args = {
.mdata_out = mdata_out,
Expand Down
3 changes: 0 additions & 3 deletions src/commonlib/bsd/include/commonlib/bsd/cb_err.h
View file
Expand Up @@ -42,7 +42,4 @@ enum cb_err {
CB_CBFS_CACHE_FULL = -403, /**< Metadata cache overflowed */
};

/* Don't typedef the enum directly, so the size is unambiguous for serialization. */
typedef int32_t cb_err_t;

#endif /* _COMMONLIB_BSD_CB_ERR_H_ */
24 changes: 12 additions & 12 deletions src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
View file
Expand Up @@ -78,24 +78,24 @@ enum cbfs_walk_flags {
* CB_SUCCESS/<other> - First non-CB_CBFS_NOT_FOUND code returned by walker()
* CB_CBFS_NOT_FOUND - walker() returned CB_CBFS_NOT_FOUND for every file in the CBFS
*/
cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t offset,
const union cbfs_mdata *mdata,
size_t already_read, void *arg),
void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags);
enum cb_err cbfs_walk(cbfs_dev_t dev, enum cb_err (*walker)(cbfs_dev_t dev, size_t offset,
const union cbfs_mdata *mdata,
size_t already_read, void *arg),
void *arg, struct vb2_hash *metadata_hash, enum cbfs_walk_flags);

/*
* Helper function that can be used by a |walker| callback to cbfs_walk() to copy the metadata
* of a file into a permanent buffer. Will copy the |already_read| metadata from |src| into
* |dst| and load remaining metadata from |dev| as required.
*/
cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src,
size_t already_read, cbfs_dev_t dev, size_t offset);
enum cb_err cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *src,
size_t already_read, cbfs_dev_t dev, size_t offset);

/* Find a file named |name| in the CBFS on |dev|. Copy its metadata (including attributes)
* into |mdata_out| and pass out the offset to the file data on the CBFS device.
* Verify the metadata with |metadata_hash| if provided. */
cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash);
enum cb_err cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash);

/* Both base address and size of CBFS mcaches must be aligned to this value! */
#define CBFS_MCACHE_ALIGNMENT sizeof(uint32_t) /* Largest data type used in CBFS */
Expand All @@ -105,15 +105,15 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_o
* CB_CBFS_CACHE_FULL, the mcache is still valid and can be used, but lookups may return
* CB_CBFS_CACHE_FULL for files that didn't fit to indicate that the caller needs to fall back
* to cbfs_lookup(). */
cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size,
struct vb2_hash *metadata_hash);
enum cb_err cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size,
struct vb2_hash *metadata_hash);

/*
* Find a file named |name| in a CBFS metadata cache and copy its metadata into |mdata_out|.
* Pass out offset to the file data (on the original CBFS device used for cbfs_mcache_build()).
*/
cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out);
enum cb_err cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out);

/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */
size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size);
Expand Down
28 changes: 28 additions & 0 deletions src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
View file
@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: BSD-3-Clause */

#ifndef _COMMONLIB_BSD_MEM_CHIP_INFO_H_
#define _COMMONLIB_BSD_MEM_CHIP_INFO_H_

enum mem_chip_type {
MEM_CHIP_DDR3 = 0x30,
MEM_CHIP_LPDDR3 = 0x38,
MEM_CHIP_DDR4 = 0x40,
MEM_CHIP_LPDDR4 = 0x48,
MEM_CHIP_LPDDR4X = 0x49,
};

struct mem_chip_info {
uint8_t type; /* enum mem_chip_type */
uint8_t num_channels;
uint8_t reserved[6];
struct mem_chip_channel {
uint64_t density;
uint8_t io_width;
uint8_t manufacturer_id;
uint8_t revision_id[2];
uint8_t reserved[4];
uint8_t serial_id[8]; /* LPDDR5 only */
} channel[0];
};

#endif /* _COMMONLIB_BSD_MEM_CHIP_INFO_H_ */
12 changes: 12 additions & 0 deletions src/commonlib/include/commonlib/coreboot_tables.h
View file
Expand Up @@ -85,6 +85,7 @@ enum {
LB_TAG_BOARD_CONFIG = 0x0040,
LB_TAG_ACPI_CNVS = 0x0041,
LB_TAG_TYPE_C_INFO = 0x0042,
LB_TAG_ACPI_RSDP = 0x0043,
/* The following options are CMOS-related */
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,
Expand Down Expand Up @@ -574,4 +575,15 @@ struct lb_tpm_physical_presence {
uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */
uint8_t ppi_version; /* BCD encoded */
} __packed;


/*
* Handoff the ACPI RSDP
*/
struct lb_acpi_rsdp {
uint32_t tag;
uint32_t size;
struct lb_uint64 rsdp_pointer; /* Address of the ACPI RSDP */
};

#endif
264 changes: 132 additions & 132 deletions src/commonlib/include/commonlib/timestamp_serialized.h
View file
Expand Up @@ -19,23 +19,23 @@ struct timestamp_table {
} __packed;

enum timestamp_id {
TS_START_ROMSTAGE = 1,
TS_BEFORE_INITRAM = 2,
TS_AFTER_INITRAM = 3,
TS_END_ROMSTAGE = 4,
TS_START_VBOOT = 5,
TS_END_VBOOT = 6,
TS_START_COPYRAM = 8,
TS_END_COPYRAM = 9,
TS_START_RAMSTAGE = 10,
TS_START_BOOTBLOCK = 11,
TS_END_BOOTBLOCK = 12,
TS_START_COPYROM = 13,
TS_END_COPYROM = 14,
TS_START_ULZMA = 15,
TS_END_ULZMA = 16,
TS_START_ULZ4F = 17,
TS_END_ULZ4F = 18,
TS_ROMSTAGE_START = 1,
TS_INITRAM_START = 2,
TS_INITRAM_END = 3,
TS_ROMSTAGE_END = 4,
TS_VBOOT_START = 5,
TS_VBOOT_END = 6,
TS_COPYRAM_START = 8,
TS_COPYRAM_END = 9,
TS_RAMSTAGE_START = 10,
TS_BOOTBLOCK_START = 11,
TS_BOOTBLOCK_END = 12,
TS_COPYROM_START = 13,
TS_COPYROM_END = 14,
TS_ULZMA_START = 15,
TS_ULZMA_END = 16,
TS_ULZ4F_START = 17,
TS_ULZ4F_END = 18,
TS_DEVICE_ENUMERATE = 30,
TS_DEVICE_CONFIGURE = 40,
TS_DEVICE_ENABLE = 50,
Expand All @@ -50,8 +50,8 @@ enum timestamp_id {
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
TS_START_POSTCAR = 100,
TS_END_POSTCAR = 101,
TS_POSTCAR_START = 100,
TS_POSTCAR_END = 101,
TS_DELAY_START = 110,
TS_DELAY_END = 111,
TS_READ_UCODE_START = 112,
Expand All @@ -60,67 +60,67 @@ enum timestamp_id {
TS_ELOG_INIT_END = 115,

/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
TS_START_COPYVER = 501,
TS_END_COPYVER = 502,
TS_START_TPMINIT = 503,
TS_END_TPMINIT = 504,
TS_START_VERIFY_SLOT = 505,
TS_END_VERIFY_SLOT = 506,
TS_START_HASH_BODY = 507,
TS_DONE_LOADING = 508,
TS_DONE_HASHING = 509,
TS_END_HASH_BODY = 510,
TS_START_TPMPCR = 511,
TS_END_TPMPCR = 512,
TS_START_TPMLOCK = 513,
TS_END_TPMLOCK = 514,
TS_START_EC_SYNC = 515,
TS_COPYVER_START = 501,
TS_COPYVER_END = 502,
TS_TPMINIT_START = 503,
TS_TPMINIT_END = 504,
TS_VERIFY_SLOT_START = 505,
TS_VERIFY_SLOT_END = 506,
TS_HASH_BODY_START = 507,
TS_LOADING_END = 508,
TS_HASHING_END = 509,
TS_HASH_BODY_END = 510,
TS_TPMPCR_START = 511,
TS_TPMPCR_END = 512,
TS_TPMLOCK_START = 513,
TS_TPMLOCK_END = 514,
TS_EC_SYNC_START = 515,
TS_EC_HASH_READY = 516,
TS_EC_POWER_LIMIT_WAIT = 517,
TS_END_EC_SYNC = 518,
TS_START_COPYVPD = 550,
TS_END_COPYVPD_RO = 551,
TS_END_COPYVPD_RW = 552,
TS_START_TPM_ENABLE_UPDATE = 553,
TS_END_TPM_ENABLE_UPDATE = 554,
TS_EC_SYNC_END = 518,
TS_COPYVPD_START = 550,
TS_COPYVPD_RO_END = 551,
TS_COPYVPD_RW_END = 552,
TS_TPM_ENABLE_UPDATE_START = 553,
TS_TPM_ENABLE_UPDATE_END = 554,

/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
TS_AGESA_INIT_RESET_START = 900,
TS_AGESA_INIT_RESET_DONE = 901,
TS_AGESA_INIT_RESET_END = 901,
TS_AGESA_INIT_EARLY_START = 902,
TS_AGESA_INIT_EARLY_DONE = 903,
TS_AGESA_INIT_EARLY_END = 903,
TS_AGESA_INIT_POST_START = 904,
TS_AGESA_INIT_POST_DONE = 905,
TS_AGESA_INIT_POST_END = 905,
TS_AGESA_INIT_ENV_START = 906,
TS_AGESA_INIT_ENV_DONE = 907,
TS_AGESA_INIT_ENV_END = 907,
TS_AGESA_INIT_MID_START = 908,
TS_AGESA_INIT_MID_DONE = 909,
TS_AGESA_INIT_MID_END = 909,
TS_AGESA_INIT_LATE_START = 910,
TS_AGESA_INIT_LATE_DONE = 911,
TS_AGESA_INIT_LATE_END = 911,
TS_AGESA_INIT_RTB_START = 912,
TS_AGESA_INIT_RTB_DONE = 913,
TS_AGESA_INIT_RTB_END = 913,
TS_AGESA_INIT_RESUME_START = 914,
TS_AGESA_INIT_RESUME_DONE = 915,
TS_AGESA_INIT_RESUME_END = 915,
TS_AGESA_S3_LATE_START = 916,
TS_AGESA_S3_LATE_DONE = 917,
TS_AGESA_S3_LATE_END = 917,
TS_AGESA_S3_FINAL_START = 918,
TS_AGESA_S3_FINAL_DONE = 919,
TS_AGESA_S3_FINAL_END = 919,
TS_AMD_APOB_READ_START = 920,
TS_AMD_APOB_ERASE_START = 921,
TS_AMD_APOB_WRITE_START = 922,
TS_AMD_APOB_DONE = 923,
TS_AMD_APOB_END = 923,

/* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */
TS_ME_INFORM_DRAM_WAIT = 940,
TS_ME_INFORM_DRAM_DONE = 941,
TS_ME_BEFORE_END_OF_POST = 942,
TS_ME_AFTER_END_OF_POST = 943,
TS_ME_BOOT_STALL_DONE = 944,
TS_ME_INFORM_DRAM_START = 940,
TS_ME_INFORM_DRAM_END = 941,
TS_ME_END_OF_POST_START = 942,
TS_ME_END_OF_POST_END = 943,
TS_ME_BOOT_STALL_END = 944,
TS_ME_ICC_CONFIG_START = 945,
TS_ME_HOST_BOOT_PREP_DONE = 946,
TS_ME_HOST_BOOT_PREP_END = 946,
TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
TS_START_CSE_FW_SYNC = 948,
TS_END_CSE_FW_SYNC = 949,
TS_CSE_FW_SYNC_START = 948,
TS_CSE_FW_SYNC_END = 949,

/* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */
TS_FSP_MEMORY_INIT_START = 950,
Expand All @@ -129,12 +129,12 @@ enum timestamp_id {
TS_FSP_TEMP_RAM_EXIT_END = 953,
TS_FSP_SILICON_INIT_START = 954,
TS_FSP_SILICON_INIT_END = 955,
TS_FSP_BEFORE_ENUMERATE = 956,
TS_FSP_AFTER_ENUMERATE = 957,
TS_FSP_BEFORE_FINALIZE = 958,
TS_FSP_AFTER_FINALIZE = 959,
TS_FSP_BEFORE_END_OF_FIRMWARE = 960,
TS_FSP_AFTER_END_OF_FIRMWARE = 961,
TS_FSP_ENUMERATE_START = 956,
TS_FSP_ENUMERATE_END = 957,
TS_FSP_FINALIZE_START = 958,
TS_FSP_FINALIZE_END = 959,
TS_FSP_END_OF_FIRMWARE_START = 960,
TS_FSP_END_OF_FIRMWARE_END = 961,
TS_FSP_MULTI_PHASE_SI_INIT_START = 962,
TS_FSP_MULTI_PHASE_SI_INIT_END = 963,
TS_FSP_MEMORY_INIT_LOAD = 970,
Expand All @@ -161,7 +161,7 @@ enum timestamp_id {
TS_VB_READ_KERNEL_DONE = 1050,
TS_VB_VBOOT_DONE = 1100,

TS_START_KERNEL = 1101,
TS_KERNEL_START = 1101,
TS_KERNEL_DECOMPRESSION = 1102,
};

Expand All @@ -171,23 +171,23 @@ static const struct timestamp_id_to_name {
} timestamp_ids[] = {
/* Marker to report base_time. */
{ 0, "1st timestamp" },
{ TS_START_ROMSTAGE, "start of romstage" },
{ TS_BEFORE_INITRAM, "before RAM initialization" },
{ TS_AFTER_INITRAM, "after RAM initialization" },
{ TS_END_ROMSTAGE, "end of romstage" },
{ TS_START_VBOOT, "start of verified boot" },
{ TS_END_VBOOT, "end of verified boot" },
{ TS_START_COPYRAM, "starting to load ramstage" },
{ TS_END_COPYRAM, "finished loading ramstage" },
{ TS_START_RAMSTAGE, "start of ramstage" },
{ TS_START_BOOTBLOCK, "start of bootblock" },
{ TS_END_BOOTBLOCK, "end of bootblock" },
{ TS_START_COPYROM, "starting to load romstage" },
{ TS_END_COPYROM, "finished loading romstage" },
{ TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" },
{ TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" },
{ TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" },
{ TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" },
{ TS_ROMSTAGE_START, "start of romstage" },
{ TS_INITRAM_START, "before RAM initialization" },
{ TS_INITRAM_END, "after RAM initialization" },
{ TS_ROMSTAGE_END, "end of romstage" },
{ TS_VBOOT_START, "start of verified boot" },
{ TS_VBOOT_END, "end of verified boot" },
{ TS_COPYRAM_START, "starting to load ramstage" },
{ TS_COPYRAM_END, "finished loading ramstage" },
{ TS_RAMSTAGE_START, "start of ramstage" },
{ TS_BOOTBLOCK_START, "start of bootblock" },
{ TS_BOOTBLOCK_END, "end of bootblock" },
{ TS_COPYROM_START, "starting to load romstage" },
{ TS_COPYROM_END, "finished loading romstage" },
{ TS_ULZMA_START, "starting LZMA decompress (ignore for x86)" },
{ TS_ULZMA_END, "finished LZMA decompress (ignore for x86)" },
{ TS_ULZ4F_START, "starting LZ4 decompress (ignore for x86)" },
{ TS_ULZ4F_END, "finished LZ4 decompress (ignore for x86)" },
{ TS_DEVICE_ENUMERATE, "device enumeration" },
{ TS_DEVICE_CONFIGURE, "device configuration" },
{ TS_DEVICE_ENABLE, "device enable" },
Expand All @@ -209,31 +209,31 @@ static const struct timestamp_id_to_name {
{ TS_ELOG_INIT_START, "started elog init" },
{ TS_ELOG_INIT_END, "finished elog init" },

{ TS_START_COPYVER, "starting to load verstage" },
{ TS_END_COPYVER, "finished loading verstage" },
{ TS_START_TPMINIT, "starting to initialize TPM" },
{ TS_END_TPMINIT, "finished TPM initialization" },
{ TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" },
{ TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" },
{ TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " },
{ TS_DONE_LOADING, "finished loading body" },
{ TS_DONE_HASHING, "finished calculating body hash (SHA2)" },
{ TS_END_HASH_BODY, "finished verifying body signature (RSA)" },
{ TS_START_TPMPCR, "starting TPM PCR extend" },
{ TS_END_TPMPCR, "finished TPM PCR extend" },
{ TS_START_TPMLOCK, "starting locking TPM" },
{ TS_END_TPMLOCK, "finished locking TPM" },
{ TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" },
{ TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" },
{ TS_COPYVER_START, "starting to load verstage" },
{ TS_COPYVER_END, "finished loading verstage" },
{ TS_TPMINIT_START, "starting to initialize TPM" },
{ TS_TPMINIT_END, "finished TPM initialization" },
{ TS_VERIFY_SLOT_START, "starting to verify keyblock/preamble (RSA)" },
{ TS_VERIFY_SLOT_END, "finished verifying keyblock/preamble (RSA)" },
{ TS_HASH_BODY_START, "starting to verify body (load+SHA2+RSA) " },
{ TS_LOADING_END, "finished loading body" },
{ TS_HASHING_END, "finished calculating body hash (SHA2)" },
{ TS_HASH_BODY_END, "finished verifying body signature (RSA)" },
{ TS_TPMPCR_START, "starting TPM PCR extend" },
{ TS_TPMPCR_END, "finished TPM PCR extend" },
{ TS_TPMLOCK_START, "starting locking TPM" },
{ TS_TPMLOCK_END, "finished locking TPM" },
{ TS_TPM_ENABLE_UPDATE_START, "started TPM enable update" },
{ TS_TPM_ENABLE_UPDATE_END, "finished TPM enable update" },

{ TS_START_COPYVPD, "starting to load Chrome OS VPD" },
{ TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
{ TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" },
{ TS_COPYVPD_START, "starting to load Chrome OS VPD" },
{ TS_COPYVPD_RO_END, "finished loading Chrome OS VPD (RO)" },
{ TS_COPYVPD_RW_END, "finished loading Chrome OS VPD (RW)" },

{ TS_START_EC_SYNC, "starting EC software sync" },
{ TS_EC_SYNC_START, "starting EC software sync" },
{ TS_EC_HASH_READY, "EC vboot hash ready" },
{ TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" },
{ TS_END_EC_SYNC, "finished EC software sync" },
{ TS_EC_SYNC_END, "finished EC software sync" },

{ TS_DC_START, "depthcharge start" },
{ TS_RO_PARAMS_INIT, "RO parameter init" },
Expand All @@ -247,45 +247,45 @@ static const struct timestamp_id_to_name {
{ TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" },
{ TS_VB_VBOOT_DONE, "finished vboot kernel verification" },
{ TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" },
{ TS_START_KERNEL, "jumping to kernel" },
{ TS_KERNEL_START, "jumping to kernel" },

/* AMD related timestamps */
{ TS_AGESA_INIT_RESET_START, "calling AmdInitReset" },
{ TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" },
{ TS_AGESA_INIT_RESET_END, "back from AmdInitReset" },
{ TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" },
{ TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" },
{ TS_AGESA_INIT_EARLY_END, "back from AmdInitEarly" },
{ TS_AGESA_INIT_POST_START, "calling AmdInitPost" },
{ TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" },
{ TS_AGESA_INIT_POST_END, "back from AmdInitPost" },
{ TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" },
{ TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" },
{ TS_AGESA_INIT_ENV_END, "back from AmdInitEnv" },
{ TS_AGESA_INIT_MID_START, "calling AmdInitMid" },
{ TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" },
{ TS_AGESA_INIT_MID_END, "back from AmdInitMid" },
{ TS_AGESA_INIT_LATE_START, "calling AmdInitLate" },
{ TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" },
{ TS_AGESA_INIT_LATE_END, "back from AmdInitLate" },
{ TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" },
{ TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" },
{ TS_AGESA_INIT_RTB_END, "back from AmdInitRtb/AmdS3Save" },
{ TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" },
{ TS_AGESA_INIT_RESUME_DONE, "back from AmdInitResume" },
{ TS_AGESA_INIT_RESUME_END, "back from AmdInitResume" },
{ TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" },
{ TS_AGESA_S3_LATE_DONE, "back from AmdS3LateRestore" },
{ TS_AGESA_S3_LATE_END, "back from AmdS3LateRestore" },
{ TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" },
{ TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" },
{ TS_AGESA_S3_FINAL_END, "back from AmdS3FinalRestore" },
{ TS_AMD_APOB_READ_START, "starting APOB read" },
{ TS_AMD_APOB_ERASE_START, "starting APOB erase" },
{ TS_AMD_APOB_WRITE_START, "starting APOB write" },
{ TS_AMD_APOB_DONE, "finished APOB" },
{ TS_AMD_APOB_END, "finished APOB" },

/* Intel ME related timestamps */
{ TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"},
{ TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"},
{ TS_ME_BEFORE_END_OF_POST, "before sending EOP to ME"},
{ TS_ME_AFTER_END_OF_POST, "after sending EOP to ME"},
{ TS_ME_BOOT_STALL_DONE, "CSE sent 'Boot Stall Done' to PMC"},
{ TS_ME_INFORM_DRAM_START, "waiting for ME acknowledgement of raminit"},
{ TS_ME_INFORM_DRAM_END, "finished waiting for ME response"},
{ TS_ME_END_OF_POST_START, "before sending EOP to ME"},
{ TS_ME_END_OF_POST_END, "after sending EOP to ME"},
{ TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"},
{ TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"},
{ TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"},
{ TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"},
{ TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"},
{ TS_START_CSE_FW_SYNC, "starting CSE firmware sync"},
{ TS_END_CSE_FW_SYNC, "finished CSE firmware sync"},
{ TS_CSE_FW_SYNC_START, "starting CSE firmware sync"},
{ TS_CSE_FW_SYNC_END, "finished CSE firmware sync"},
{ TS_ME_ROM_START, "CSME ROM started execution"},

/* FSP related timestamps */
Expand All @@ -297,20 +297,20 @@ static const struct timestamp_id_to_name {
{ TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" },
{ TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit" },
{ TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit" },
{ TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" },
{ TS_FSP_AFTER_ENUMERATE,
{ TS_FSP_ENUMERATE_START, "calling FspNotify(AfterPciEnumeration)" },
{ TS_FSP_ENUMERATE_END,
"returning from FspNotify(AfterPciEnumeration)" },
{ TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" },
{ TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" },
{ TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" },
{ TS_FSP_AFTER_END_OF_FIRMWARE,
{ TS_FSP_FINALIZE_START, "calling FspNotify(ReadyToBoot)" },
{ TS_FSP_FINALIZE_END, "returning from FspNotify(ReadyToBoot)" },
{ TS_FSP_END_OF_FIRMWARE_START, "calling FspNotify(EndOfFirmware)" },
{ TS_FSP_END_OF_FIRMWARE_END,
"returning from FspNotify(EndOfFirmware)" },

{ TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M" },
{ TS_FSP_SILICON_INIT_LOAD, "loading FSP-S" },

{ TS_START_POSTCAR, "start of postcar" },
{ TS_END_POSTCAR, "end of postcar" },
{ TS_POSTCAR_START, "start of postcar" },
{ TS_POSTCAR_END, "end of postcar" },
};

#endif
2 changes: 1 addition & 1 deletion src/cpu/intel/car/romstage.c
View file
Expand Up @@ -60,7 +60,7 @@ static void romstage_main(void)

asmlinkage void car_stage_entry(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
timestamp_add_now(TS_ROMSTAGE_START);

/* Assumes the hardware was set up during the bootblock */
console_init();
Expand Down
19 changes: 19 additions & 0 deletions src/cpu/intel/common/common.h
View file
Expand Up @@ -47,4 +47,23 @@ void configure_dca_cap(void);
*/
void set_energy_perf_bias(u8 policy);

/*
* Check energy performance preference and HWP capabilities from Thermal and
* Power Management Leaf CPUID.
*/
bool check_energy_perf_cap(void);

/*
* Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical
* thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to
* prefer energy efficiency.
*/
void set_energy_perf_pref(u8 pref);

/*
* Instructs the CPU to use EPP hints. This means that any energy policies set
* up in `set_energy_perf_bias` will be ignored afterwards.
*/
void enable_energy_perf_pref(void);

#endif
45 changes: 44 additions & 1 deletion src/cpu/intel/common/common_init.c
View file
Expand Up @@ -5,9 +5,12 @@
#include <console/console.h>
#include <cpu/intel/msr.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/turbo.h>
#include "common.h"

#define CPUID_6_ECX_EPB (1 << 3)
#define CPUID_6_ECX_EPB (1 << 3)
#define CPUID_6_ENGERY_PERF_PREF (1 << 10)
#define CPUID_6_HWP (1 << 7)

void set_vmx_and_lock(void)
{
Expand Down Expand Up @@ -182,3 +185,43 @@ void set_energy_perf_bias(u8 policy)
msr_unset_and_set(IA32_ENERGY_PERF_BIAS, ENERGY_POLICY_MASK, epb);
printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", epb);
}

/*
* Check energy performance preference and HWP capabilities from Thermal and
* Power Management Leaf CPUID
*/
bool check_energy_perf_cap(void)
{
const u32 cap = cpuid_eax(CPUID_LEAF_PM);
if (!(cap & CPUID_6_ENGERY_PERF_PREF))
return false;
if (!(cap & CPUID_6_HWP))
return false;
return true;
}

/*
* Instructs the CPU to use EPP hints. This means that any energy policies set
* up in `set_energy_perf_bias` will be ignored afterwards.
*/
void enable_energy_perf_pref(void)
{
msr_t msr = rdmsr(IA32_PM_ENABLE);
if (!(msr.lo & HWP_ENABLE)) {
/* Package-scoped MSR */
printk(BIOS_DEBUG, "HWP_ENABLE: energy-perf preference in favor of energy-perf bias\n");
msr_set(IA32_PM_ENABLE, HWP_ENABLE);
}
}

/*
* Set the IA32_HWP_REQUEST Energy-Performance Preference bits on the logical
* thread. 0 is a hint to the HWP to prefer performance, and 255 is a hint to
* prefer energy efficiency.
* This function needs to be called when HWP_ENABLE is set.
*/
void set_energy_perf_pref(u8 pref)
{
msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK,
pref << IA32_HWP_REQUEST_EPP_SHIFT);
}
14 changes: 14 additions & 0 deletions src/cpu/x86/smm/smm_module_handler.c
View file
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/io.h>
#include <console/cbmem_console.h>
#include <console/console.h>
#include <commonlib/region.h>
#include <cpu/x86/smm.h>
Expand Down Expand Up @@ -48,6 +49,12 @@ static void smi_release_lock(void)
);
}

void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out)
{
*buffer_out = smm_runtime.cbmemc;
*size_out = smm_runtime.cbmemc_size;
}

void io_trap_handler(int smif)
{
/* If a handler function handled a given IO trap, it
Expand Down Expand Up @@ -150,6 +157,8 @@ asmlinkage void smm_handler_start(void *arg)

smi_backup_pci_address();

smm_soc_early_init();

console_init();

printk(BIOS_SPEW, "\nSMI# #%d\n", cpu);
Expand Down Expand Up @@ -179,6 +188,8 @@ asmlinkage void smm_handler_start(void *arg)
die("SMM Handler caused a stack overflow\n");
}

smm_soc_exit();

smi_release_lock();

/* De-assert SMI# signal to allow another SMI */
Expand All @@ -199,3 +210,6 @@ void __weak mainboard_smi_gpi(u32 gpi_sts) {}
int __weak mainboard_smi_apmc(u8 data) { return 0; }
void __weak mainboard_smi_sleep(u8 slp_typ) {}
void __weak mainboard_smi_finalize(void) {}

void __weak smm_soc_early_init(void) {}
void __weak smm_soc_exit(void) {}
12 changes: 12 additions & 0 deletions src/cpu/x86/smm/smm_module_loader.c
View file
Expand Up @@ -5,6 +5,7 @@
#include <stdint.h>
#include <string.h>
#include <rmodule.h>
#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <commonlib/helpers.h>
#include <console/console.h>
Expand Down Expand Up @@ -479,6 +480,7 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size,
void *fxsave_area;
size_t total_size = 0;
uintptr_t base; /* The base for the permanent handler */
const struct cbmem_entry *cbmemc;

if (CONFIG(SMM_ASEG))
return smm_load_module_aseg(smram_base, smram_size, params);
Expand Down Expand Up @@ -557,6 +559,14 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size,
handler_mod_params->num_cpus = params->num_cpus;
handler_mod_params->gnvs_ptr = (uintptr_t)acpi_get_gnvs();

if (CONFIG(CONSOLE_CBMEM) && (cbmemc = cbmem_entry_find(CBMEM_ID_CONSOLE))) {
handler_mod_params->cbmemc = cbmem_entry_start(cbmemc);
handler_mod_params->cbmemc_size = cbmem_entry_size(cbmemc);
} else {
handler_mod_params->cbmemc = 0;
handler_mod_params->cbmemc_size = 0;
}

printk(BIOS_DEBUG, "%s: smram_start: 0x%lx\n", __func__, smram_base);
printk(BIOS_DEBUG, "%s: smram_end: %lx\n", __func__, smram_base + smram_size);
printk(BIOS_DEBUG, "%s: handler start %p\n",
Expand All @@ -577,6 +587,8 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size,
printk(BIOS_DEBUG, "%s: per_cpu_save_state_size = 0x%x\n", __func__,
handler_mod_params->save_state_size);
printk(BIOS_DEBUG, "%s: num_cpus = 0x%x\n", __func__, handler_mod_params->num_cpus);
printk(BIOS_DEBUG, "%s: cbmemc = %p, cbmemc_size = %#x\n", __func__,
handler_mod_params->cbmemc, handler_mod_params->cbmemc_size);
printk(BIOS_DEBUG, "%s: total_save_state_size = 0x%x\n", __func__,
(handler_mod_params->save_state_size * handler_mod_params->num_cpus));

Expand Down
8 changes: 8 additions & 0 deletions src/device/Kconfig
View file
Expand Up @@ -906,6 +906,14 @@ config SOFTWARE_I2C
I2C controller is not (yet) available. The platform code needs to
provide bindings to manually toggle I2C lines.

config I2C_TRANSFER_TIMEOUT_US
int "I2C transfer timeout in microseconds"
default 500000
help
Timeout for a read/write transfers on the I2C bus, that is, the
maximum time a device could stretch clock bits before the transfer
is aborted and an error returned.

config RESOURCE_ALLOCATOR_V3
bool
default n
Expand Down
26 changes: 13 additions & 13 deletions src/device/pci_device.c
View file
Expand Up @@ -1499,23 +1499,25 @@ static void pci_bridge_route(struct bus *link, scan_state state)
{
struct device *dev = link->dev;
struct bus *parent = dev->bus;
u32 reg, buses = 0;
uint8_t primary, secondary, subordinate;

if (state == PCI_ROUTE_SCAN) {
link->secondary = parent->subordinate + 1;
link->subordinate = link->secondary + dev->hotplug_buses;
}

if (state == PCI_ROUTE_CLOSE) {
buses |= 0xfeff << 8;
primary = 0;
secondary = 0xff;
subordinate = 0xfe;
} else if (state == PCI_ROUTE_SCAN) {
buses |= parent->secondary & 0xff;
buses |= ((u32) link->secondary & 0xff) << 8;
buses |= 0xff << 16; /* MAX PCI_BUS number here */
primary = parent->secondary;
secondary = link->secondary;
subordinate = 0xff; /* MAX PCI_BUS number here */
} else if (state == PCI_ROUTE_FINAL) {
buses |= parent->secondary & 0xff;
buses |= ((u32) link->secondary & 0xff) << 8;
buses |= ((u32) link->subordinate & 0xff) << 16;
primary = parent->secondary;
secondary = link->secondary;
subordinate = link->subordinate;
}

if (state == PCI_ROUTE_SCAN) {
Expand All @@ -1530,11 +1532,9 @@ static void pci_bridge_route(struct bus *link, scan_state state)
* transactions will not be propagated by the bridge if it is not
* correctly configured.
*/

reg = pci_read_config32(dev, PCI_PRIMARY_BUS);
reg &= 0xff000000;
reg |= buses;
pci_write_config32(dev, PCI_PRIMARY_BUS, reg);
pci_write_config8(dev, PCI_PRIMARY_BUS, primary);
pci_write_config8(dev, PCI_SECONDARY_BUS, secondary);
pci_write_config8(dev, PCI_SUBORDINATE_BUS, subordinate);

if (state == PCI_ROUTE_FINAL) {
pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd);
Expand Down
2 changes: 1 addition & 1 deletion src/device/pci_rom.c
View file
Expand Up @@ -276,7 +276,7 @@ pci_rom_write_acpi_tables(const struct device *device, unsigned long current,
return current;

/* AMD/ATI uses VFCT */
if (device->vendor == PCI_VENDOR_ID_ATI) {
if (device->vendor == PCI_VID_ATI) {
acpi_vfct_t *vfct;

current = ALIGN_UP(current, 8);
Expand Down
22 changes: 11 additions & 11 deletions src/drivers/amd/agesa/eventlog.c
View file
Expand Up @@ -28,69 +28,69 @@ static const struct agesa_mapping entrypoint[] = {
.func = AMD_INIT_RESET,
.name = "AmdInitReset",
.entry_id = TS_AGESA_INIT_RESET_START,
.exit_id = TS_AGESA_INIT_RESET_DONE,
.exit_id = TS_AGESA_INIT_RESET_END,
},
{
.func = AMD_INIT_EARLY,
.name = "AmdInitEarly",
.entry_id = TS_AGESA_INIT_EARLY_START,
.exit_id = TS_AGESA_INIT_EARLY_DONE,
.exit_id = TS_AGESA_INIT_EARLY_END,
},
{
.func = AMD_INIT_POST,
.name = "AmdInitPost",
.entry_id = TS_AGESA_INIT_POST_START,
.exit_id = TS_AGESA_INIT_POST_DONE,
.exit_id = TS_AGESA_INIT_POST_END,
},
{
.func = AMD_INIT_RESUME,
.name = "AmdInitResume",
.entry_id = TS_AGESA_INIT_RESUME_START,
.exit_id = TS_AGESA_INIT_RESUME_DONE,
.exit_id = TS_AGESA_INIT_RESUME_END,
},
{
.func = AMD_INIT_ENV,
.name = "AmdInitEnv",
.entry_id = TS_AGESA_INIT_ENV_START,
.exit_id = TS_AGESA_INIT_ENV_DONE,
.exit_id = TS_AGESA_INIT_ENV_END,
},
{
.func = AMD_INIT_MID,
.name = "AmdInitMid",
.entry_id = TS_AGESA_INIT_MID_START,
.exit_id = TS_AGESA_INIT_MID_DONE,
.exit_id = TS_AGESA_INIT_MID_END,
},
{
.func = AMD_INIT_LATE,
.name = "AmdInitLate",
.entry_id = TS_AGESA_INIT_LATE_START,
.exit_id = TS_AGESA_INIT_LATE_DONE,
.exit_id = TS_AGESA_INIT_LATE_END,
},
{
.func = AMD_S3LATE_RESTORE,
.name = "AmdS3LateRestore",
.entry_id = TS_AGESA_S3_LATE_START,
.exit_id = TS_AGESA_S3_LATE_DONE,
.exit_id = TS_AGESA_S3_LATE_END,
},
#if !defined(AMD_S3_SAVE_REMOVED)
{
.func = AMD_S3_SAVE,
.name = "AmdS3Save",
.entry_id = TS_AGESA_INIT_RTB_START,
.exit_id = TS_AGESA_INIT_RTB_DONE,
.exit_id = TS_AGESA_INIT_RTB_END,
},
#endif
{
.func = AMD_S3FINAL_RESTORE,
.name = "AmdS3FinalRestore",
.entry_id = TS_AGESA_S3_FINAL_START,
.exit_id = TS_AGESA_S3_FINAL_DONE,
.exit_id = TS_AGESA_S3_FINAL_END,
},
{
.func = AMD_INIT_RTB,
.name = "AmdInitRtb",
.entry_id = TS_AGESA_INIT_RTB_START,
.exit_id = TS_AGESA_INIT_RTB_DONE,
.exit_id = TS_AGESA_INIT_RTB_END,
},
};

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6 changes: 3 additions & 3 deletions src/drivers/amd/agesa/romstage.c
View file
Expand Up @@ -40,7 +40,7 @@ static void romstage_main(void)

fill_sysinfo(cb);

timestamp_add_now(TS_START_ROMSTAGE);
timestamp_add_now(TS_ROMSTAGE_START);

board_BeforeAgesa(cb);

Expand All @@ -55,14 +55,14 @@ static void romstage_main(void)

agesa_execute_state(cb, AMD_INIT_EARLY);

timestamp_add_now(TS_BEFORE_INITRAM);
timestamp_add_now(TS_INITRAM_START);

if (!cb->s3resume)
agesa_execute_state(cb, AMD_INIT_POST);
else
agesa_execute_state(cb, AMD_INIT_RESUME);

timestamp_add_now(TS_AFTER_INITRAM);
timestamp_add_now(TS_INITRAM_END);

/* Work around AGESA setting all memory as WB on normal
* boot path.
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/aspeed/ast2050/ast2050.c
View file
Expand Up @@ -60,6 +60,6 @@ static struct device_operations aspeed_ast2050_ops = {

static const struct pci_driver aspeed_ast2050_driver __pci_driver = {
.ops = &aspeed_ast2050_ops,
.vendor = PCI_VENDOR_ID_ASPEED,
.device = PCI_DEVICE_ID_ASPEED_AST2050_VGA,
.vendor = PCI_VID_ASPEED,
.device = PCI_DID_ASPEED_AST2050_VGA,
};
2 changes: 1 addition & 1 deletion src/drivers/broadcom/bcm57xx_aspm_disable.c
View file
Expand Up @@ -27,6 +27,6 @@ static const unsigned short pci_device_ids[] = {

static const struct pci_driver bcm57xx_aspm_fixup __pci_driver = {
.ops = &bcm57xx_aspm_fixup_ops,
.vendor = PCI_VENDOR_ID_BROADCOM,
.vendor = PCI_VID_BROADCOM,
.devices = pci_device_ids,
};
4 changes: 2 additions & 2 deletions src/drivers/generic/bayhub/bh720.c
View file
Expand Up @@ -108,13 +108,13 @@ static struct device_operations bh720_ops = {
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_O2_BH720,
PCI_DID_O2_BH720,
0
};

static const struct pci_driver bayhub_bh720 __pci_driver = {
.ops = &bh720_ops,
.vendor = PCI_VENDOR_ID_O2,
.vendor = PCI_VID_O2,
.devices = pci_device_ids,
};

Expand Down
4 changes: 2 additions & 2 deletions src/drivers/generic/bayhub_lv2/lv2.c
View file
Expand Up @@ -70,13 +70,13 @@ static struct device_operations lv2_ops = {
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_O2_LV2,
PCI_DID_O2_LV2,
0
};

static const struct pci_driver bayhub_lv2 __pci_driver = {
.ops = &lv2_ops,
.vendor = PCI_VENDOR_ID_O2,
.vendor = PCI_VID_O2,
.devices = pci_device_ids,
};

Expand Down
4 changes: 2 additions & 2 deletions src/drivers/genesyslogic/gl9750/gl9750.c
View file
Expand Up @@ -35,13 +35,13 @@ static struct device_operations gl9750_ops = {
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_GLI_9750,
PCI_DID_GLI_9750,
0
};

static const struct pci_driver genesyslogic_gl9750 __pci_driver = {
.ops = &gl9750_ops,
.vendor = PCI_VENDOR_ID_GLI,
.vendor = PCI_VID_GLI,
.devices = pci_device_ids,
};

Expand Down