25 changes: 3 additions & 22 deletions src/Kconfig
View file
Expand Up @@ -154,9 +154,7 @@ config COMPRESS_RAMSTAGE
depends on HAVE_RAMSTAGE
# Default value set at the end of the file
help
Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow link (i.e. SPI).
Compress ramstage to save memory in the flash image.

config COMPRESS_PRERAM_STAGES
bool "Compress romstage and verstage with LZ4"
Expand Down Expand Up @@ -463,6 +461,7 @@ endmenu
menu "Security"

source "src/security/Kconfig"
source "src/vendorcode/eltan/security/Kconfig"

endmenu

Expand Down Expand Up @@ -528,22 +527,6 @@ config RESUME_PATH_SAME_AS_BOOT
same path as a regular boot. e.g. an x86 system runs from the
reset vector at 0xfffffff0 on both resume and warm/cold boot.

config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
bool
default n

config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
bool
default n
help
This should be enabled on certain plaforms, such as the AMD
SR565x, that cannot handle concurrent CBFS accesses from
multiple APs during early startup.

config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
bool
default n

config NO_MONOTONIC_TIMER
def_bool n

Expand Down Expand Up @@ -1194,9 +1177,7 @@ config BOOTBLOCK_CUSTOM
# src/lib/bootblock.c#main() C entry point.
bool

config C_ENVIRONMENT_BOOTBLOCK
# To be selected by arch or platform if a C environment is available during the
# bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
config ROMCC_BOOTBLOCK
bool

###############################################################################
Expand Down
6 changes: 2 additions & 4 deletions src/arch/arm/Kconfig
View file
Expand Up @@ -4,7 +4,6 @@ config ARCH_ARM
config ARCH_BOOTBLOCK_ARM
bool
select ARCH_ARM
select C_ENVIRONMENT_BOOTBLOCK

config ARCH_VERSTAGE_ARM
bool
Expand All @@ -17,10 +16,9 @@ config ARCH_ROMSTAGE_ARM
config ARCH_RAMSTAGE_ARM
bool
select ARCH_ARM
select RAMSTAGE_CBMEM_TOP_ARG

source src/arch/arm/armv4/Kconfig
source src/arch/arm/armv7/Kconfig
source "src/arch/arm/armv4/Kconfig"
source "src/arch/arm/armv7/Kconfig"

config ARM_LPAE
bool
Expand Down
26 changes: 0 additions & 26 deletions src/arch/arm/include/arch/early_variables.h
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59 changes: 0 additions & 59 deletions src/arch/arm/include/armv7/arch/types.h
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4 changes: 1 addition & 3 deletions src/arch/arm64/Kconfig
View file
Expand Up @@ -4,7 +4,6 @@ config ARCH_ARM64
config ARCH_BOOTBLOCK_ARM64
bool
select ARCH_ARM64
select C_ENVIRONMENT_BOOTBLOCK

config ARCH_VERSTAGE_ARM64
bool
Expand All @@ -17,9 +16,8 @@ config ARCH_ROMSTAGE_ARM64
config ARCH_RAMSTAGE_ARM64
bool
select ARCH_ARM64
select RAMSTAGE_CBMEM_TOP_ARG

source src/arch/arm64/armv8/Kconfig
source "src/arch/arm64/armv8/Kconfig"

if ARCH_ARM64

Expand Down
30 changes: 15 additions & 15 deletions src/arch/arm64/armv8/cpu.S
View file
Expand Up @@ -99,15 +99,14 @@ ENDPROC(mmu_disable)

/*
* Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a
* known state regarding caches/SCTLR/PSTATE. Completely invalidates
* known state regarding caches/SCTLR/SCR/PSTATE. Completely invalidates
* icache/dcache, disables MMU and dcache (if active), and enables unaligned
* accesses, icache and branch prediction (if inactive). Seeds the stack and
* initializes SP_EL0. Clobbers R22 and R23.
* accesses, icache. Seeds stack and initializes SP_EL0. Clobbers R22 and R23.
*/
ENTRY(arm64_init_cpu)
/* Initialize PSTATE (unmask all exceptions, select SP_EL0). */
/* Initialize PSTATE (mask all exceptions, select SP_EL0). */
msr SPSel, #0
msr DAIFClr, #0xf
msr DAIFSet, #0xf

/* TODO: This is where we'd put non-boot CPUs into WFI if needed. */

Expand All @@ -116,24 +115,25 @@ ENTRY(arm64_init_cpu)
/* TODO: Assert that we always start running at EL3 */
mrs x22, sctlr_el3

/* Activate ICache (12) already for speed during cache flush below. */
orr x22, x22, #(1 << 12)
/* Activate ICache already for speed during cache flush below. */
orr x22, x22, #SCTLR_I
msr sctlr_el3, x22
isb

/* Invalidate dcache */
bl dcache_invalidate_all

/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
and x22, x22, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
/* Activate Stack Alignment (3) because why not */
orr x22, x22, #(1 << 3)
/* Set to little-endian (25) */
and x22, x22, # ~(1 << 25)
/* Deactivate write-xor-execute enforcement (19) */
and x22, x22, # ~(1 << 19)
/* Reinitialize SCTLR from scratch to known-good state.
This may disable MMU or DCache. */
ldr w22, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA)
msr sctlr_el3, x22

/* Initialize SCR to unmask all interrupts (so that if we get a spurious
IRQ/SError we'll see it when it happens, not hang in BL31). This will
only have an effect after we DAIFClr in exception_init(). */
mov x22, #SCR_RES1 | SCR_IRQ | SCR_FIQ | SCR_EA
msr scr_el3, x22

/* Invalidate icache and TLB for good measure */
ic iallu
tlbi alle3
Expand Down
12 changes: 9 additions & 3 deletions src/arch/arm64/armv8/exception.c
View file
Expand Up @@ -34,9 +34,10 @@
#include <arch/exception.h>
#include <arch/transition.h>
#include <console/console.h>
#include <console/uart.h>
#include <arch/lib_helpers.h>

uint8_t exception_stack[0x200] __attribute__((aligned(16)));
uint8_t exception_stack[2*KiB] __attribute__((aligned(16)));

static const char *exception_names[NUM_EXC_VIDS] = {
[EXC_VID_CUR_SP_EL0_SYNC] = "_sync_sp_el0",
Expand Down Expand Up @@ -131,8 +132,13 @@ int exception_handler_unregister(uint64_t vid, struct exception_handler *h)

static void print_exception_info(struct exc_state *state, uint64_t idx)
{
if (idx < NUM_EXC_VIDS)
printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]);
/* Poor man's sign of life in case printk() is shot. */
__uart_tx_byte('\r');
__uart_tx_byte('\n');
__uart_tx_byte('!');

printk(BIOS_DEBUG, "\nexception %s\n",
idx < NUM_EXC_VIDS ? exception_names[idx] : "_unknown");

print_regs(state);
/* Few words below SP in case we need state from a returned function. */
Expand Down
26 changes: 0 additions & 26 deletions src/arch/arm64/include/arch/early_variables.h
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This file was deleted.

22 changes: 1 addition & 21 deletions src/arch/arm64/include/armv8/arch/cache.h
View file
Expand Up @@ -32,33 +32,13 @@
#ifndef ARM_ARM64_CACHE_H
#define ARM_ARM64_CACHE_H

/* SCTLR_ELx common bits */
#define SCTLR_M (1 << 0) /* MMU enable */
#define SCTLR_A (1 << 1) /* Alignment check enable */
#define SCTLR_C (1 << 2) /* Data/unified cache enable */
#define SCTLR_SA (1 << 3) /* Stack alignment check enable */
#define SCTLR_I (1 << 12) /* Instruction cache enable */
#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
#define SCTLR_EE (1 << 25) /* Exception endianness */

/* SCTLR_EL1 bits */
#define SCTLR_EL1_CP15B (1 << 5) /* CP15 barrier enable */
#define SCTLR_EL1_ITD (1 << 7) /* IT disable */
#define SCTLR_EL1_SED (1 << 8) /* SETEND disable */
#define SCTLR_EL1_UMA (1 << 9) /* User mask access */
#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */
#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */
#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */
#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */
#include <arch/lib_helpers.h>

#ifndef __ASSEMBLER__

#include <stddef.h>
#include <stdint.h>
#include <arch/barrier.h>
#include <arch/lib_helpers.h>

/* dcache clean by virtual address to PoC */
void dcache_clean_by_mva(void const *addr, size_t len);
Expand Down
99 changes: 33 additions & 66 deletions src/arch/arm64/include/armv8/arch/lib_helpers.h
View file
Expand Up @@ -38,79 +38,46 @@
#define SPSR_DEBUG (1 << 9)
#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)

#define SCR_NS_SHIFT 0
#define SCR_NS_MASK (1 << SCR_NS_SHIFT)
#define SCR_NS_ENABLE (1 << SCR_NS_SHIFT)
#define SCR_NS_DISABLE (0 << SCR_NS_SHIFT)
#define SCR_NS SCR_NS_ENABLE
#define SCR_RES1 (0x3 << 4)
#define SCR_IRQ_SHIFT 2
#define SCR_IRQ_MASK (1 << SCR_IRQ_SHIFT)
#define SCR_IRQ_ENABLE (1 << SCR_IRQ_SHIFT)
#define SCR_IRQ_DISABLE (0 << SCR_IRQ_SHIFT)
#define SCR_FIQ_SHIFT 2
#define SCR_FIQ_MASK (1 << SCR_FIQ_SHIFT)
#define SCR_FIQ_ENABLE (1 << SCR_FIQ_SHIFT)
#define SCR_FIQ_DISABLE (0 << SCR_FIQ_SHIFT)
#define SCR_EA_SHIFT 3
#define SCR_EA_MASK (1 << SCR_EA_SHIFT)
#define SCR_EA_ENABLE (1 << SCR_EA_SHIFT)
#define SCR_EA_DISABLE (0 << SCR_EA_SHIFT)
#define SCR_SMD_SHIFT 7
#define SCR_SMD_MASK (1 << SCR_SMD_SHIFT)
#define SCR_SMD_DISABLE (1 << SCR_SMD_SHIFT)
#define SCR_SMD_ENABLE (0 << SCR_SMD_SHIFT)
#define SCR_HVC_SHIFT 8
#define SCR_HVC_MASK (1 << SCR_HVC_SHIFT)
#define SCR_HVC_DISABLE (0 << SCR_HVC_SHIFT)
#define SCR_HVC_ENABLE (1 << SCR_HVC_SHIFT)
#define SCR_SIF_SHIFT 9
#define SCR_SIF_MASK (1 << SCR_SIF_SHIFT)
#define SCR_SIF_ENABLE (1 << SCR_SIF_SHIFT)
#define SCR_SIF_DISABLE (0 << SCR_SIF_SHIFT)
#define SCR_RW_SHIFT 10
#define SCR_RW_MASK (1 << SCR_RW_SHIFT)
#define SCR_LOWER_AARCH64 (1 << SCR_RW_SHIFT)
#define SCR_LOWER_AARCH32 (0 << SCR_RW_SHIFT)
#define SCR_ST_SHIFT 11
#define SCR_ST_MASK (1 << SCR_ST_SHIFT)
#define SCR_ST_ENABLE (1 << SCR_ST_SHIFT)
#define SCR_ST_DISABLE (0 << SCR_ST_SHIFT)
#define SCR_TWI_SHIFT 12
#define SCR_TWI_MASK (1 << SCR_TWI_SHIFT)
#define SCR_TWI_ENABLE (1 << SCR_TWI_SHIFT)
#define SCR_TWI_DISABLE (0 << SCR_TWI_SHIFT)
#define SCR_TWE_SHIFT 13
#define SCR_TWE_MASK (1 << SCR_TWE_SHIFT)
#define SCR_TWE_ENABLE (1 << SCR_TWE_SHIFT)
#define SCR_TWE_DISABLE (0 << SCR_TWE_SHIFT)
#define SCR_NS (1 << 0) /* EL0/1 are non-secure */
#define SCR_IRQ (1 << 1) /* Take IRQs in EL3 */
#define SCR_FIQ (1 << 2) /* Take FIQs in EL3 */
#define SCR_EA (1 << 3) /* Take EA/SError in EL3 */
#define SCR_SMD (1 << 7) /* Disable SMC instruction */
#define SCR_HCE (1 << 8) /* Enable HVC instruction */
#define SCR_SIF (1 << 9) /* Forbid insns from NS memory */
#define SCR_RW (1 << 10) /* Lower ELs are AArch64 */
#define SCR_ST (1 << 11) /* Don't trap secure CNTPS */
#define SCR_TWI (1 << 12) /* Trap WFI to EL3 */
#define SCR_TWE (1 << 13) /* Trap WFE to EL3 */
#define SCR_TLOR (1 << 14) /* Trap LOR accesses to EL3 */
#define SCR_TERR (1 << 15) /* Trap ERR accesses to EL3 */
#define SCR_APK (1 << 16) /* Don't trap ptrauth keys */
#define SCR_API (1 << 17) /* Don't trap ptrauth insn */
#define SCR_EEL2 (1 << 18) /* Enable secure EL2 */
#define SCR_EASE (1 << 19) /* Sync EAs use SError vector */
#define SCR_NMEA (1 << 20) /* Disallow EL3 SError masking */
#define SCR_FIEN (1 << 21) /* Don't trap EXRPFG */
#define SCR_RES1 (3 << 4)

#define HCR_RW_SHIFT 31
#define HCR_LOWER_AARCH64 (1 << HCR_RW_SHIFT)
#define HCR_LOWER_AARCH32 (0 << HCR_RW_SHIFT)

#define SCTLR_MMU_ENABLE 1
#define SCTLR_MMU_DISABLE 0
#define SCTLR_ACE_SHIFT 1
#define SCTLR_ACE_ENABLE (1 << SCTLR_ACE_SHIFT)
#define SCTLR_ACE_DISABLE (0 << SCTLR_ACE_SHIFT)
#define SCTLR_CACHE_SHIFT 2
#define SCTLR_CACHE_ENABLE (1 << SCTLR_CACHE_SHIFT)
#define SCTLR_CACHE_DISABLE (0 << SCTLR_CACHE_SHIFT)
#define SCTLR_SAE_SHIFT 3
#define SCTLR_SAE_ENABLE (1 << SCTLR_SAE_SHIFT)
#define SCTLR_SAE_DISABLE (0 << SCTLR_SAE_SHIFT)
#define SCTLR_M (1 << 0) /* MMU enable */
#define SCTLR_A (1 << 1) /* Alignment check enable */
#define SCTLR_C (1 << 2) /* Data/unified cache enable */
#define SCTLR_SA (1 << 3) /* Stack alignment check enable */
#define SCTLR_NAA (1 << 6) /* non-aligned access STA/LDR */
#define SCTLR_I (1 << 12) /* Instruction cache enable */
#define SCTLR_ENDB (1 << 13) /* Pointer auth (data B) */
#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
#define SCTLR_IESB (1 << 21) /* Implicit error sync event */
#define SCTLR_EE (1 << 25) /* Exception endianness (BE) */
#define SCTLR_ENDA (1 << 27) /* Pointer auth (data A) */
#define SCTLR_ENIB (1 << 30) /* Pointer auth (insn B) */
#define SCTLR_ENIA (1 << 31) /* Pointer auth (insn A) */
#define SCTLR_RES1 ((0x3 << 4) | (0x1 << 11) | (0x1 << 16) | \
(0x1 << 18) | (0x3 << 22) | (0x3 << 28))
#define SCTLR_ICE_SHIFT 12
#define SCTLR_ICE_ENABLE (1 << SCTLR_ICE_SHIFT)
#define SCTLR_ICE_DISABLE (0 << SCTLR_ICE_SHIFT)
#define SCTLR_WXN_SHIFT 19
#define SCTLR_WXN_ENABLE (1 << SCTLR_WXN_SHIFT)
#define SCTLR_WXN_DISABLE (0 << SCTLR_WXN_SHIFT)
#define SCTLR_ENDIAN_SHIFT 25
#define SCTLR_LITTLE_END (0 << SCTLR_ENDIAN_SHIFT)
#define SCTLR_BIG_END (1 << SCTLR_ENDIAN_SHIFT)

#define CPTR_EL3_TCPAC_SHIFT (31)
#define CPTR_EL3_TTA_SHIFT (20)
Expand Down
1 change: 0 additions & 1 deletion src/arch/arm64/include/armv8/arch/mmio.h
View file
Expand Up @@ -17,7 +17,6 @@
#ifndef __ARCH_MMIO_H__
#define __ARCH_MMIO_H__

#include <endian.h>
#include <stdint.h>
#include <arch/barrier.h>
#include <arch/lib_helpers.h>
Expand Down
32 changes: 6 additions & 26 deletions src/arch/arm64/transition.c
View file
Expand Up @@ -17,14 +17,6 @@
#include <arch/transition.h>
#include <assert.h>

/* Litte-endian, No XN-forced, Instr cache disabled,
* Stack alignment disabled, Data and unified cache
* disabled, Alignment check disabled, MMU disabled
*/
#define SCTLR_MASK (SCTLR_MMU_DISABLE | SCTLR_ACE_DISABLE | \
SCTLR_CACHE_DISABLE | SCTLR_SAE_DISABLE | SCTLR_RES1 | \
SCTLR_ICE_DISABLE | SCTLR_WXN_DISABLE | SCTLR_LITTLE_END)

void __weak exc_dispatch(struct exc_state *exc_state, uint64_t id)
{
/* Default weak implementation does nothing. */
Expand Down Expand Up @@ -54,7 +46,6 @@ void transition_to_el2(void *entry, void *arg, uint64_t spsr)
struct exc_state exc_state;
struct elx_state *elx = &exc_state.elx;
struct regs *regs = &exc_state.regs;
uint32_t sctlr;

regs->x[X0_INDEX] = (uint64_t)arg;
elx->elr = (uint64_t)entry;
Expand All @@ -70,19 +61,10 @@ void transition_to_el2(void *entry, void *arg, uint64_t spsr)
*/
assert(get_el_from_spsr(spsr) == EL2 && !(spsr & SPSR_ERET_32));

/* Initialize SCR with defaults for running without secure monitor. */
raw_write_scr_el3(SCR_TWE_DISABLE | /* don't trap WFE */
SCR_TWI_DISABLE | /* don't trap WFI */
SCR_ST_ENABLE | /* allow secure timer access */
SCR_LOWER_AARCH64 | /* lower level is AArch64 */
SCR_SIF_DISABLE | /* disable secure ins. fetch */
SCR_HVC_ENABLE | /* allow HVC instruction */
SCR_SMD_ENABLE | /* disable SMC instruction */
SCR_RES1 | /* reserved-1 bits */
SCR_EA_DISABLE | /* disable ext. abort trap */
SCR_FIQ_DISABLE | /* disable FIQ trap to EL3 */
SCR_IRQ_DISABLE | /* disable IRQ trap to EL3 */
SCR_NS_ENABLE); /* lower level is non-secure */
/* Initialize SCR with defaults for running without secure monitor
(disable all traps, enable all instructions, run NS at AArch64). */
raw_write_scr_el3(SCR_FIEN | SCR_API | SCR_APK | SCR_ST | SCR_RW |
SCR_HCE | SCR_SMD | SCR_RES1 | SCR_NS);

/* Initialize CPTR to not trap anything to EL3. */
raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
Expand All @@ -92,10 +74,8 @@ void transition_to_el2(void *entry, void *arg, uint64_t spsr)
raw_write_elr_el3(elx->elr);
raw_write_spsr_el3(elx->spsr);

/* SCTLR: Initialize EL with selected properties */
sctlr = raw_read_sctlr_el2();
sctlr &= SCTLR_MASK;
raw_write_sctlr_el2(sctlr);
/* SCTLR: Initialize EL with everything disabled */
raw_write_sctlr_el2(SCTLR_RES1);

/* SP_ELx: Initialize stack pointer */
raw_write_sp_el2(elx->sp_elx);
Expand Down
5 changes: 4 additions & 1 deletion src/arch/arm64/transition_asm.S
View file
Expand Up @@ -154,7 +154,7 @@ ENDPROC(exc_exit)

/*
* exception_init_asm: Initialize VBAR and point SP_EL3 to exception stack.
* x0 = end of exception stack
* Also unmask aborts now that we can report them. x0 = end of exception stack
*/
ENTRY(exception_init_asm)
msr SPSel, #SPSR_USE_H
Expand All @@ -163,6 +163,9 @@ ENTRY(exception_init_asm)

adr x0, exc_vectors
msr vbar_el3, x0

msr DAIFClr, #0xf

dsb sy
isb
ret
Expand Down
39 changes: 0 additions & 39 deletions src/arch/mips/Kconfig
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93 changes: 0 additions & 93 deletions src/arch/mips/Makefile.inc
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53 changes: 0 additions & 53 deletions src/arch/mips/ashldi3.c
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23 changes: 0 additions & 23 deletions src/arch/mips/boot.c
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42 changes: 0 additions & 42 deletions src/arch/mips/bootblock.S
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42 changes: 0 additions & 42 deletions src/arch/mips/bootblock_simple.c
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114 changes: 0 additions & 114 deletions src/arch/mips/cache.c
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24 changes: 0 additions & 24 deletions src/arch/mips/include/arch/bootblock_common.h
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23 changes: 0 additions & 23 deletions src/arch/mips/include/arch/byteorder.h
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48 changes: 0 additions & 48 deletions src/arch/mips/include/arch/cache.h
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26 changes: 0 additions & 26 deletions src/arch/mips/include/arch/cbconfig.h
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172 changes: 0 additions & 172 deletions src/arch/mips/include/arch/cpu.h
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19 changes: 0 additions & 19 deletions src/arch/mips/include/arch/exception.h
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53 changes: 0 additions & 53 deletions src/arch/mips/include/arch/mmu.h
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19 changes: 0 additions & 19 deletions src/arch/mips/include/arch/pci_ops.h
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22 changes: 0 additions & 22 deletions src/arch/mips/include/arch/stages.h
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59 changes: 0 additions & 59 deletions src/arch/mips/include/arch/types.h
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98 changes: 0 additions & 98 deletions src/arch/mips/mmu.c
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23 changes: 0 additions & 23 deletions src/arch/mips/stages.c
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28 changes: 0 additions & 28 deletions src/arch/mips/tables.c
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2 changes: 0 additions & 2 deletions src/arch/ppc64/Kconfig
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@@ -1,12 +1,10 @@
config ARCH_PPC64
bool
select RAMSTAGE_CBMEM_TOP_ARG

config ARCH_BOOTBLOCK_PPC64
bool
select ARCH_PPC64
select BOOTBLOCK_CUSTOM
select C_ENVIRONMENT_BOOTBLOCK

config ARCH_VERSTAGE_PPC64
bool
Expand Down
27 changes: 0 additions & 27 deletions src/arch/ppc64/include/arch/early_variables.h
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1 change: 0 additions & 1 deletion src/arch/riscv/Kconfig
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Expand Up @@ -77,7 +77,6 @@ config ARCH_RISCV_PMP
config ARCH_BOOTBLOCK_RISCV
bool
default n
select C_ENVIRONMENT_BOOTBLOCK

config ARCH_VERSTAGE_RISCV
bool
Expand Down
9 changes: 3 additions & 6 deletions src/arch/riscv/boot.c
View file
Expand Up @@ -36,7 +36,7 @@ struct arch_prog_run_args {

static void do_arch_prog_run(struct arch_prog_run_args *args)
{
int hart_id;
int hart_id = HLS()->hart_id;
struct prog *prog = args->prog;
void *fdt = HLS()->fdt;

Expand All @@ -49,11 +49,8 @@ static void do_arch_prog_run(struct arch_prog_run_args *args)
else
run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S);
} else {
void (*doit)(int hart_id, void *fdt) = prog_entry(prog);

hart_id = HLS()->hart_id;

doit(hart_id, fdt);
void (*doit)(int hart_id, void *fdt, void *arg) = prog_entry(prog);
doit(hart_id, fdt, prog_entry_arg(prog));
}

die("Failed to run stage");
Expand Down
29 changes: 0 additions & 29 deletions src/arch/riscv/include/arch/early_variables.h
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7 changes: 7 additions & 0 deletions src/arch/riscv/ramstage.S
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Expand Up @@ -20,6 +20,13 @@
.section ".text._start", "ax", %progbits
.globl _start
_start:
/* cbmem_top is passed via a2 */
la t0, _cbmem_top_ptr
#if __riscv_xlen == 32
sw a2, (t0)
#elif __riscv_xlen == 64
sd a2, (t0)
#endif
# initialize stack point for each hart
# and the stack must be page-aligned.
# 0xDEADBEEF used to check stack overflow
Expand Down
29 changes: 14 additions & 15 deletions src/arch/x86/Kconfig
View file
Expand Up @@ -16,15 +16,14 @@ config ARCH_X86
default n
select PCI
select RELOCATABLE_MODULES
select RAMSTAGE_CBMEM_TOP_ARG

# stage selectors for x86

config ARCH_BOOTBLOCK_X86_32
bool
default n
select ARCH_X86
select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK

config ARCH_VERSTAGE_X86_32
bool
Expand All @@ -48,7 +47,7 @@ config ARCH_BOOTBLOCK_X86_64
bool
default n
select ARCH_X86
select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK

config ARCH_VERSTAGE_X86_64
bool
Expand Down Expand Up @@ -88,6 +87,16 @@ config AP_IN_SIPI_WAIT
default n
depends on ARCH_X86 && SMP

config X86_RESET_VECTOR
hex
depends on ARCH_X86
default 0xfffffff0
help
Specify the location of the x86 reset vector. In traditional devices
this must match the architectural reset vector to produce a bootable
image. Nontraditional designs may use this to position the reset
vector into its desired location.

config RESET_VECTOR_IN_RAM
bool
depends on ARCH_X86
Expand Down Expand Up @@ -149,15 +158,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE
help
Increase this value if preram cbmem console is getting truncated

config EARLY_EBDA_INIT
bool
default n
help
Initialize BIOS EBDA area early in romstage to allow bootloader to
use this region for storing data which can be available across
various stages. If user is selecting this option then its users
responsibility to perform EBDA initialization call during romstage.

config PC80_SYSTEM
bool
default y if ARCH_X86
Expand Down Expand Up @@ -209,7 +209,7 @@ config ID_SECTION_OFFSET
hex
default 0x80

# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK.
# 64KiB default bootblock size
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x10000
Expand All @@ -229,7 +229,6 @@ config VERSTAGE_ADDR
config POSTCAR_STAGE
def_bool y
depends on ARCH_X86
depends on !CAR_GLOBAL_MIGRATION

config VERSTAGE_DEBUG_SPINLOOP
bool
Expand All @@ -249,7 +248,7 @@ config ROMSTAGE_DEBUG_SPINLOOP
choice
prompt "Bootblock behaviour"
default BOOTBLOCK_SIMPLE
depends on !C_ENVIRONMENT_BOOTBLOCK
depends on ROMCC_BOOTBLOCK

config BOOTBLOCK_SIMPLE
bool "Always load fallback"
Expand Down
22 changes: 10 additions & 12 deletions src/arch/x86/Makefile.inc
View file
Expand Up @@ -116,7 +116,7 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-y += id.S
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h

ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)

bootblock-y += bootblock_crt0.S

Expand All @@ -128,7 +128,7 @@ endif

bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S

else # !C_ENVIRONMENT_BOOTBLOCK
else # ROMCC_BOOTBLOCK

# x86-specific linker flags
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
Expand All @@ -147,9 +147,9 @@ $(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock
bootblock-y += bootblock.ld
$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld

bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__
ifeq ($(CONFIG_SSE),y)
bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__
endif

# This is a hack in case there are no per chipset linker files.
Expand All @@ -165,9 +165,9 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch
$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
# The open quote in the subst messes with syntax highlighting. Fix it - ")
@printf " ROMCC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
$< > $(objgenerated)/bootblock.inc.d
$(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \
$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \
$< -o $(objgenerated)/bootblock_romcc.c
$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@

Expand All @@ -178,7 +178,7 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs)
$(filter-out %.ld,$(bootblock-objs)) \
-T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld)

endif # C_ENVIRONMENT_BOOTBLOCK
endif # ROMCC_BOOTBLOCK


endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
Expand Down Expand Up @@ -223,10 +223,10 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
# gdt_init.S is included by entry32.inc when romstage is the first C
# environment.
romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
romstage-y += gdt_init.S
endif
romstage-y += cbmem.c
romstage-y += cbfs_and_run.c
romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
romstage-y += memmove.c
Expand Down Expand Up @@ -260,8 +260,6 @@ postcar-generic-ccopts += -D__POSTCAR__

postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
postcar-y += gdt_init.S
postcar-y += cbfs_and_run.c
postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c
postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
postcar-y += exit_car.S
Expand Down
1 change: 1 addition & 0 deletions src/arch/x86/acpi_device.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <arch/acpigen.h>
#include <device/device.h>
#include <device/path.h>
#include <stdlib.h>
#if CONFIG(GENERIC_GPIO_LIB)
#include <gpio.h>
#endif
Expand Down
13 changes: 6 additions & 7 deletions src/arch/x86/assembly_entry.S
View file
Expand Up @@ -13,14 +13,13 @@

#include <rules.h>

#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if !CONFIG(ROMCC_BOOTBLOCK)

/*
* This path is for stages that are post bootblock when employing
* CONFIG_C_ENVIRONMENT_BOOTBLOCK. The gdt is reloaded to accommodate
* platforms that are executing out of CAR. In order to continue with
* C code execution one needs to set stack pointer and clear CAR_GLOBAL
* variables that are stage specific.
* This path is for stages that are post bootblock. The gdt is reloaded
* to accommodate platforms that are executing out of CAR. In order to
* continue with C code execution one needs to set stack pointer and
* clear .bss variables that are stage specific.
*/
.section ".text._start", "ax", @progbits
.global _start
Expand All @@ -30,7 +29,7 @@ _start:
call gdt_init

/* reset stack pointer to CAR stack */
mov $_car_stack_end, %esp
mov $_ecar_stack, %esp

/* clear .bss section as it is not shared */
cld
Expand Down
3 changes: 1 addition & 2 deletions src/arch/x86/bootblock_crt0.S
View file
Expand Up @@ -11,8 +11,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This is the modern bootblock. It is used by platforms which select
* C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime
* This is the modern bootblock. It prepares the system for C environment runtime
* setup. The actual setup is done by hardware-specific code.
*
* It provides a bootflow similar to other architectures, and thus is considered
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/bootblock_romcc.S
View file
Expand Up @@ -20,7 +20,7 @@
* - timestamp.inc: store TSC in MMX registers
* - generated/bootblock.inc: ROMCC part of the bootblock
*
* This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it
* This is used on platforms which select ROMCC_BOOTBLOCK, and it
* tries to do the absolute minimum before walking CBFS and jumping to romstage.
*
* This file assembles the bootblock program by the order of the includes. Thus,
Expand Down
37 changes: 14 additions & 23 deletions src/arch/x86/car.ld
View file
Expand Up @@ -36,10 +36,10 @@
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .;
#if !CONFIG(ROMCC_BOOTBLOCK)
_car_stack = .;
. += CONFIG_DCACHE_BSP_STACK_SIZE;
_car_stack_end = .;
_ecar_stack = .;
#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that
Expand All @@ -59,15 +59,19 @@

TIMESTAMP(., 0x200)

_car_ehci_dbg_info_start = .;
#if !CONFIG(NO_FMAP_CACHE)
FMAP_CACHE(., FMAP_SIZE)
#endif

_car_ehci_dbg_info = .;
/* Reserve sizeof(struct ehci_dbg_info). */
. += 80;
_car_ehci_dbg_info_end = .;
_ecar_ehci_dbg_info = .;

/* _bss and _ebss provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
* cbmem console. This is useful for clearing this area on a per-stage
* basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
* basis when more than one stage uses cache-as-ram. */

. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
Expand All @@ -77,18 +81,14 @@
*(.bss.*)
*(.sbss)
*(.sbss.*)
#else
_car_global_start = .;
*(.car.global_data);
_car_global_end = .;
#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_ebss = .;
_car_unallocated_start = .;

#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .;
_car_stack_end = _car_region_end;
#if CONFIG(ROMCC_BOOTBLOCK)
_car_stack = .;
_ecar_stack = _car_region_end;
#endif
_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
}
Expand All @@ -102,21 +102,12 @@
.illegal_globals . : {
*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
#if CONFIG(CAR_GLOBAL_MIGRATION)
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
#else
/* In case something sneaks through when it shouldn't. */
*(.car.global_data);
#endif
}

_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if !CONFIG(ROMCC_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif
20 changes: 0 additions & 20 deletions src/arch/x86/cbfs_and_run.c
View file

This file was deleted.

48 changes: 1 addition & 47 deletions src/arch/x86/ebda.c
View file
Expand Up @@ -24,58 +24,12 @@ static void *get_ebda_start(void)
return (void *)((uintptr_t)DEFAULT_EBDA_SEGMENT << 4);
}

static bool is_length_valid(size_t dlength)
{
/* Check if input data length is > DEFAULT_EBDA_SIZE */
if (dlength > DEFAULT_EBDA_SIZE)
return false;

/* Valid data length */
return true;
}

/*
* EBDA area is representing a 1KB memory area just below
* the top of conventional memory (below 1MB)
*/

/*
* write_ebda_data is a wrapper function to write into EBDA area
*
* data = data to be written into EBDA area
* length = input data size.
*/
void write_ebda_data(const void *data, size_t length)
{
void *ebda;

if (!is_length_valid(length))
die("Input data length is > EBDA default size (1KiB)!");

ebda = get_ebda_start();

memcpy(ebda, data, length);
}

/*
* read_ebda_data is a wrapper function to read from EBDA area
*
* data = data read from EBDA area based on input size
* length = read data size.
*/
void read_ebda_data(void *data, size_t length)
{
void *ebda;

if (!is_length_valid(length))
die("Input data length is > EBDA default size (1KiB)!");

ebda = get_ebda_start();

memcpy(data, ebda, length);
}

void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
static void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
{
u16 low_memory_kb;
u16 ebda_kb;
Expand Down
17 changes: 7 additions & 10 deletions src/arch/x86/exception.c
View file
Expand Up @@ -12,7 +12,6 @@
*/

#include <arch/cpu.h>
#include <arch/early_variables.h>
#include <arch/exception.h>
#include <commonlib/helpers.h>
#include <console/console.h>
Expand Down Expand Up @@ -569,7 +568,7 @@ static const uintptr_t intr_entries[] = {
(uintptr_t)vec16, (uintptr_t)vec17, (uintptr_t)vec18, (uintptr_t)vec19,
};

static struct intr_gate idt[ARRAY_SIZE(intr_entries)] __aligned(8) CAR_GLOBAL;
static struct intr_gate idt[ARRAY_SIZE(intr_entries)] __aligned(8);

static inline uint16_t get_cs(void)
{
Expand Down Expand Up @@ -620,21 +619,19 @@ asmlinkage void exception_init(void)
{
int i;
uint16_t segment;
struct intr_gate *gates;

segment = get_cs();
gates = car_get_var_ptr(idt);

/* Initialize IDT. */
for (i = 0; i < ARRAY_SIZE(idt); i++) {
gates[i].offset_0 = intr_entries[i];
gates[i].segsel = segment;
gates[i].flags = IGATE_FLAGS;
gates[i].offset_1 = intr_entries[i] >> 16;
idt[i].offset_0 = intr_entries[i];
idt[i].segsel = segment;
idt[i].flags = IGATE_FLAGS;
idt[i].offset_1 = intr_entries[i] >> 16;
#if ENV_X86_64
gates[i].offset_2 = intr_entries[i] >> 32;
idt[i].offset_2 = intr_entries[i] >> 32;
#endif
}

load_idt(gates, sizeof(idt));
load_idt(idt, sizeof(idt));
}
2 changes: 1 addition & 1 deletion src/arch/x86/failover.ld
View file
Expand Up @@ -14,7 +14,7 @@
ENTRY(_start)

MEMORY {
rom : ORIGIN = 0xffff0000, LENGTH = 64K
rom : ORIGIN = CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K
}

TARGET(binary)
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/id.ld
View file
Expand Up @@ -12,7 +12,7 @@
*/

SECTIONS {
. = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
. = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 0x10;
.id (.): {
KEEP(*(.id))
}
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/include/arch/acpigen.h
View file
Expand Up @@ -87,7 +87,7 @@ enum {
BANK_FIELD_OP = 0x87,
DATA_REGION_OP = 0x88,
ROOT_PREFIX = 0x5C,
PARENT_PREFIX = 0x5D,
PARENT_PREFIX = 0x5E,
LOCAL0_OP = 0x60,
LOCAL1_OP = 0x61,
LOCAL2_OP = 0x62,
Expand Down
5 changes: 2 additions & 3 deletions src/arch/x86/include/arch/cache.h
View file
Expand Up @@ -31,13 +31,12 @@
#ifndef ARCH_CACHE_H
#define ARCH_CACHE_H

#include <arch/early_variables.h>
#include <cpu/x86/cache.h>

/* Executing WBINVD when running out of CAR would not be good, prevent that. */
static inline void dcache_clean_invalidate_all(void)
{
if (!car_active())
if (!ENV_CACHE_AS_RAM)
wbinvd();
}
static inline void dcache_clean_all(void)
Expand All @@ -47,7 +46,7 @@ static inline void dcache_clean_all(void)
}
static inline void dcache_invalidate_all(void)
{
if (!car_active())
if (!ENV_CACHE_AS_RAM)
invd();
}

Expand Down
11 changes: 4 additions & 7 deletions src/arch/x86/include/arch/cpu.h
View file
Expand Up @@ -14,8 +14,7 @@
#ifndef ARCH_CPU_H
#define ARCH_CPU_H

#include <stdint.h>
#include <stddef.h>
#include <types.h>

/*
* EFLAGS bits
Expand Down Expand Up @@ -211,8 +210,7 @@ int cpu_have_cpuid(void);

static inline bool cpu_is_amd(void)
{
return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)
|| CONFIG(SOC_AMD_COMMON) || CONFIG(CPU_AMD_MODEL_10XXX);
return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
}

static inline bool cpu_is_intel(void)
Expand Down Expand Up @@ -290,9 +288,8 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
#define asmlinkage __attribute__((regparm(0)))

/*
* When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry()
* is the symbol jumped to for each stage after bootblock using
* cache-as-ram.
* When not using a romcc bootblock the car_stage_entry() is the symbol
* jumped to for each stage after bootblock using cache-as-ram.
*/
asmlinkage void car_stage_entry(void);

Expand Down
98 changes: 0 additions & 98 deletions src/arch/x86/include/arch/early_variables.h
View file

This file was deleted.

21 changes: 0 additions & 21 deletions src/arch/x86/include/arch/ebda.h
View file
Expand Up @@ -27,27 +27,6 @@
#define DEFAULT_EBDA_SEGMENT 0xF600
#define DEFAULT_EBDA_SIZE 0x400

void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size);
void setup_default_ebda(void);

/*
* This read/write API only allows and assumes
* a single EBDA structure type for a platform.
*/

/*
* write_ebda_data is a wrapper function to write into EBDA area
*
* data = data to be written into EBDA area
* length = input data size.
*/
void write_ebda_data(const void *data, size_t length);
/*
* read_ebda_data is a wrapper function to read from EBDA area
*
* data = data read from EBDA area based on input size
* length = read data size.
*/
void read_ebda_data(void *data, size_t length);

#endif
26 changes: 6 additions & 20 deletions src/arch/x86/include/arch/smp/spinlock.h
View file
Expand Up @@ -14,11 +14,6 @@
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H

#if !defined(__PRE_RAM__) \
|| CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
|| CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
|| CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)

/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
*/
Expand All @@ -27,23 +22,14 @@ typedef struct {
volatile unsigned int lock;
} spinlock_t;

#ifdef __PRE_RAM__
spinlock_t *romstage_console_lock(void);
void initialize_romstage_console_lock(void);
spinlock_t *romstage_nvram_cbfs_lock(void);
void initialize_romstage_nvram_cbfs_lock(void);
spinlock_t *romstage_microcode_cbfs_lock(void);
void initialize_romstage_microcode_cbfs_lock(void);
#endif

#define SPIN_LOCK_UNLOCKED { 1 }

#ifndef __PRE_RAM__
#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE

#if STAGE_HAS_SPINLOCKS

#define DECLARE_SPIN_LOCK(x) \
static spinlock_t x = SPIN_LOCK_UNLOCKED;
#else
#define DECLARE_SPIN_LOCK(x)
#endif

/*
* Simple spin lock operations. There are two variants, one clears IRQ's
Expand Down Expand Up @@ -93,7 +79,7 @@ static __always_inline void cpu_relax(void)
__asm__ __volatile__("rep;nop" : : : "memory");
}

#else /* !__PRE_RAM__ */
#else

#define DECLARE_SPIN_LOCK(x)
#define barrier() do {} while (0)
Expand All @@ -103,6 +89,6 @@ static __always_inline void cpu_relax(void)
#define spin_unlock(lock) do {} while (0)
#define cpu_relax() do {} while (0)

#endif /* !__PRE_RAM__ */
#endif

#endif /* ARCH_SMP_SPINLOCK_H */
4 changes: 0 additions & 4 deletions src/arch/x86/include/arch/stages.h
View file
Expand Up @@ -14,8 +14,4 @@
#ifndef __ARCH_STAGES_H
#define __ARCH_STAGES_H

#include <arch/cpu.h>

asmlinkage void copy_and_run(void);

#endif
12 changes: 6 additions & 6 deletions src/arch/x86/include/arch/symbols.h
View file
Expand Up @@ -27,15 +27,15 @@ extern char _car_region_end[];
* This is the stack area used for all stages that execute when cache-as-ram
* is up. Area is not cleared in between stages.
*/
extern char _car_stack_start[];
extern char _car_stack_end[];
#define _car_stack_size (_car_stack_end - _car_stack_start)
extern char _car_stack[];
extern char _ecar_stack[];
#define _car_stack_size (_ecar_stack - _car_stack)

extern char _car_unallocated_start[];

extern char _car_ehci_dbg_info_start[];
extern char _car_ehci_dbg_info_end[];
extern char _car_ehci_dbg_info[];
extern char _ecar_ehci_dbg_info[];
#define _car_ehci_dbg_info_size \
(_car_ehci_dbg_info_end - _car_ehci_dbg_info_start)
(_ecar_ehci_dbg_info - _car_ehci_dbg_info)

#endif
5 changes: 2 additions & 3 deletions src/arch/x86/memlayout.ld
View file
Expand Up @@ -49,9 +49,8 @@ SECTIONS

#include EARLY_MEMLAYOUT
#elif ENV_BOOTBLOCK
/* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains
* the logic for the romcc linking. */
BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1,
/* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */
BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
CONFIG_C_ENV_BOOTBLOCK_SIZE)

#include EARLY_MEMLAYOUT
Expand Down
2 changes: 2 additions & 0 deletions src/arch/x86/postcar_loader.c
View file
Expand Up @@ -228,6 +228,8 @@ void run_postcar_phase(struct postcar_frame *pcf)
/* As postcar exist, it's end of romstage here */
timestamp_add_now(TS_END_ROMSTAGE);

console_time_report();

prog_set_arg(&prog, cbmem_top());

prog_run(&prog);
Expand Down
33 changes: 21 additions & 12 deletions src/arch/x86/smbios.c
View file
Expand Up @@ -550,16 +550,6 @@ static int get_socket_type(void)
return 0x13;
if (CONFIG(CPU_INTEL_SOCKET_LGA775))
return 0x15;
if (CONFIG(CPU_AMD_SOCKET_AM2R2))
return 0x17;
if (CONFIG(CPU_AMD_SOCKET_F_1207))
return 0x18;
if (CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA))
return 0x1a;
if (CONFIG(CPU_AMD_SOCKET_AM3))
return 0x1b;
if (CONFIG(CPU_AMD_SOCKET_C32_NON_AGESA))
return 0x1c;

return 0x02; /* Unknown */
}
Expand Down Expand Up @@ -662,9 +652,28 @@ static int smbios_write_type4(unsigned long *current, int handle)
t->processor_version = smbios_processor_name(t->eos);
t->processor_family = (res.eax > 0) ? 0x0c : 0x6;
t->processor_type = 3; /* System Processor */
t->core_count = (res.ebx >> 16) & 0xff;
/*
* If CPUID leaf 11 is available, calculate "core count" by dividing
* SMT_ID (logical processors in a core) by Core_ID (number of cores).
* This seems to be the way to arrive to a number of cores mentioned on
* ark.intel.com.
*/
if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) {
uint32_t leaf_b_cores = 0, leaf_b_threads = 0;
res = cpuid_ext(0xb, 1);
leaf_b_cores = res.ebx;
res = cpuid_ext(0xb, 0);
leaf_b_threads = res.ebx;
/* if hyperthreading is not available, pretend this is 1 */
if (leaf_b_threads == 0) {
leaf_b_threads = 1;
}
t->core_count = leaf_b_cores / leaf_b_threads;
} else {
t->core_count = (res.ebx >> 16) & 0xff;
}
/* Assume we enable all the cores always, capped only by MAX_CPUS */
t->core_enabled = MAX(t->core_count, CONFIG_MAX_CPUS);
t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS);
t->l1_cache_handle = 0xffff;
t->l2_cache_handle = 0xffff;
t->l3_cache_handle = 0xffff;
Expand Down
37 changes: 0 additions & 37 deletions src/arch/x86/tables.c
View file
Expand Up @@ -194,41 +194,6 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
#define FORWARDING_TABLE_ADDR ((uintptr_t)0x500)
static uintptr_t forwarding_table = FORWARDING_TABLE_ADDR;

/*
* For EARLY_EBDA_INIT the BDA area will be wiped on the resume path which
* has the forwarding table entry. Therefore, when tables are written an
* entry is placed in cbmem that can be restored on OS resume to the proper
* location.
*/
static void stash_forwarding_table(uintptr_t addr, size_t sz)
{
void *cbmem_addr = cbmem_add(CBMEM_ID_CBTABLE_FWD, sz);

if (cbmem_addr == NULL) {
printk(BIOS_ERR, "Unable to allocate CBMEM forwarding entry.\n");
return;
}

memcpy(cbmem_addr, (void *)addr, sz);
}

static void restore_forwarding_table(void *dest)
{
const struct cbmem_entry *fwd_entry;

fwd_entry = cbmem_entry_find(CBMEM_ID_CBTABLE_FWD);

if (fwd_entry == NULL) {
printk(BIOS_ERR, "Unable to restore CBMEM forwarding entry.\n");
return;
}

memcpy(dest, cbmem_entry_start(fwd_entry), cbmem_entry_size(fwd_entry));
}

BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
restore_forwarding_table, (void *)FORWARDING_TABLE_ADDR);

void arch_write_tables(uintptr_t coreboot_table)
{
size_t sz;
Expand All @@ -250,8 +215,6 @@ void arch_write_tables(uintptr_t coreboot_table)

sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table);

stash_forwarding_table(forwarding_table, sz);

forwarding_table += sz;
/* Align up to page boundary for historical consistency. */
forwarding_table = ALIGN_UP(forwarding_table, 4*KiB);
Expand Down
5 changes: 2 additions & 3 deletions src/commonlib/include/commonlib/cbfs.h
View file
Expand Up @@ -32,14 +32,13 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
static inline void cbfs_file_data(struct region_device *data,
const struct cbfsf *file)
{
rdev_chain(data, &file->data, 0, region_device_sz(&file->data));
rdev_chain_full(data, &file->data);
}

static inline void cbfs_file_metadata(struct region_device *metadata,
const struct cbfsf *file)
{
rdev_chain(metadata, &file->metadata, 0,
region_device_sz(&file->metadata));
rdev_chain_full(metadata, &file->metadata);
}

/*
Expand Down
1 change: 1 addition & 0 deletions src/commonlib/include/commonlib/cbmem_id.h
View file
Expand Up @@ -79,6 +79,7 @@
#define CBMEM_ID_ROM2 0x524f4d32
#define CBMEM_ID_ROM3 0x524f4d33
#define CBMEM_ID_FMAP 0x464d4150
#define CBMEM_ID_FSP_LOGO 0x4c4f474f

#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
Expand Down
18 changes: 17 additions & 1 deletion src/commonlib/include/commonlib/region.h
View file
Expand Up @@ -73,7 +73,6 @@ ssize_t rdev_eraseat(const struct region_device *rd, size_t offset,
int rdev_chain(struct region_device *child, const struct region_device *parent,
size_t offset, size_t size);


/* A region_device operations. */
struct region_device_ops {
void *(*mmap)(const struct region_device *, size_t, size_t);
Expand Down Expand Up @@ -123,6 +122,11 @@ static inline size_t region_sz(const struct region *r)
return r->size;
}

static inline size_t region_end(const struct region *r)
{
return region_offset(r) + region_sz(r);
}

static inline const struct region *region_device_region(
const struct region_device *rdev)
{
Expand All @@ -139,12 +143,24 @@ static inline size_t region_device_offset(const struct region_device *rdev)
return region_offset(region_device_region(rdev));
}

static inline size_t region_device_end(const struct region_device *rdev)
{
return region_end(region_device_region(rdev));
}

/* Memory map entire region device. Same semantics as rdev_mmap() above. */
static inline void *rdev_mmap_full(const struct region_device *rd)
{
return rdev_mmap(rd, 0, region_device_sz(rd));
}

static inline int rdev_chain_full(struct region_device *child,
const struct region_device *parent)
{
/* Chain full size of parent. */
return rdev_chain(child, parent, 0, region_device_sz(parent));
}

/*
* Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0
* when child is not within the parent's region.
Expand Down
9 changes: 9 additions & 0 deletions src/commonlib/include/commonlib/timestamp_serialized.h
View file
Expand Up @@ -79,6 +79,10 @@ enum timestamp_id {
TS_END_TPMPCR = 512,
TS_START_TPMLOCK = 513,
TS_END_TPMLOCK = 514,
TS_START_EC_SYNC = 515,
TS_EC_HASH_READY = 516,
TS_EC_POWER_LIMIT_WAIT = 517,
TS_END_EC_SYNC = 518,
TS_START_COPYVPD = 550,
TS_END_COPYVPD_RO = 551,
TS_END_COPYVPD_RW = 552,
Expand Down Expand Up @@ -202,6 +206,11 @@ static const struct timestamp_id_to_name {
{ TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" },
{ TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" },

{ TS_START_EC_SYNC, "starting EC software sync" },
{ TS_EC_HASH_READY, "EC vboot hash ready" },
{ TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" },
{ TS_END_EC_SYNC, "finished EC software sync" },

{ TS_DC_START, "depthcharge start" },
{ TS_RO_PARAMS_INIT, "RO parameter init" },
{ TS_RO_VB_INIT, "RO vboot init" },
Expand Down
5 changes: 0 additions & 5 deletions src/commonlib/region.c
View file
Expand Up @@ -15,11 +15,6 @@
#include <commonlib/region.h>
#include <string.h>

static inline size_t region_end(const struct region *r)
{
return region_sz(r) + region_offset(r);
}

int region_is_subregion(const struct region *p, const struct region *c)
{
if (region_offset(c) < region_offset(p))
Expand Down
13 changes: 6 additions & 7 deletions src/commonlib/storage/pci_sdhci.c
View file
Expand Up @@ -12,7 +12,6 @@
* GNU General Public License for more details.
*/

#include <arch/early_variables.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Expand All @@ -32,22 +31,22 @@ int sdhci_controller_init(struct sdhci_ctrlr *sdhci_ctrlr, void *ioaddr)

struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr)
{
static bool sdhci_init_done CAR_GLOBAL;
static struct sdhci_ctrlr sdhci_ctrlr CAR_GLOBAL;
static bool sdhci_init_done;
static struct sdhci_ctrlr sdhci_ctrlr;

if (car_get_var(sdhci_init_done) == true) {
if (sdhci_init_done == true) {
sdhc_error("Error: SDHCI is already initialized.\n");
return NULL;
}

if (sdhci_controller_init(car_get_var_ptr(&sdhci_ctrlr), ioaddr)) {
if (sdhci_controller_init(&sdhci_ctrlr, ioaddr)) {
sdhc_error("Error: SDHCI initialization failed.\n");
return NULL;
}

car_set_var(sdhci_init_done, true);
sdhci_init_done = true;

return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr);
return &sdhci_ctrlr.sd_mmc_ctrlr;
}

struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev)
Expand Down
1 change: 1 addition & 0 deletions src/commonlib/storage/sdhci_adma.c
View file
Expand Up @@ -19,6 +19,7 @@
#include <console/console.h>
#include <delay.h>
#include <endian.h>
#include <stdlib.h>
#include <string.h>

#include "sdhci.h"
Expand Down
6 changes: 3 additions & 3 deletions src/console/Kconfig
View file
Expand Up @@ -5,7 +5,7 @@ config NO_BOOTBLOCK_CONSOLE

config BOOTBLOCK_CONSOLE
bool "Enable early (bootblock) console output."
depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE
depends on !ROMCC_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE
default y
help
Use console during the bootblock if supported
Expand Down Expand Up @@ -88,7 +88,7 @@ comment "Serial port base address = 0x2e8"
depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3

config UART_OVERRIDE_BAUDRATE
boolean
bool
help
Set to "y" when the platform overrides the baudrate by providing
a get_uart_baudrate routine.
Expand Down Expand Up @@ -303,7 +303,7 @@ config SPI_CONSOLE
drivers are written.

config CONSOLE_OVERRIDE_LOGLEVEL
boolean
bool
help
Set to "y" when the platform overrides the loglevel by providing
a get_console_loglevel routine.
Expand Down
9 changes: 4 additions & 5 deletions src/console/init.c
View file
Expand Up @@ -12,7 +12,6 @@
* GNU General Public License for more details.
*/

#include <arch/early_variables.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <console/uart.h>
Expand All @@ -24,12 +23,12 @@
/* Mutable console log level only allowed when RAM comes online. */
#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION

static int console_inited CAR_GLOBAL;
static int console_inited;
static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;

static inline int get_log_level(void)
{
if (car_get_var(console_inited) == 0)
if (console_inited == 0)
return -1;
if (CONSOLE_LEVEL_CONST)
return get_console_loglevel();
Expand Down Expand Up @@ -78,14 +77,14 @@ asmlinkage void console_init(void)
init_log_level();

if (CONFIG(DEBUG_CONSOLE_INIT))
car_set_var(console_inited, 1);
console_inited = 1;

if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
pci_early_bridge_init();

console_hw_init();

car_set_var(console_inited, 1);
console_inited = 1;

printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n",
coreboot_version, coreboot_extra_version, coreboot_build,
Expand Down