197 changes: 125 additions & 72 deletions src/drivers/elog/elog.c
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Large diffs are not rendered by default.

1 change: 0 additions & 1 deletion src/drivers/gic/gic.c
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Expand Up @@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>
#include <arch/io.h>
#include <console/console.h>
#include <gic.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/lm63/lm63.c
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@@ -1,4 +1,3 @@
#include <console/console.h>
#include <device/device.h>
#include <device/smbus.h>

Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/pca9538/pca9538.c
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Expand Up @@ -15,7 +15,6 @@

#include <device/i2c_bus.h>
#include <device/device.h>
#include <console/console.h>
#include "pca9538.h"
#include "chip.h"

Expand Down
4 changes: 4 additions & 0 deletions src/drivers/i2c/tpm/Makefile.inc
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Expand Up @@ -2,20 +2,24 @@ ramstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c
romstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c
verstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c
bootblock-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c
postcar-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c

ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c
romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c
verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c
bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c
postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c

ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c
romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c
verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c
bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c
postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c

ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c
romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c
verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c
bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c
postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c

ramstage-$(CONFIG_DRIVER_I2C_TPM_ACPI) += chip.c
1 change: 0 additions & 1 deletion src/drivers/i2c/w83793/w83793.c
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Expand Up @@ -15,7 +15,6 @@
*/

#include <stdint.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <device/device.h>
#include "w83793.h"
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_0/hob.c
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Expand Up @@ -16,7 +16,6 @@
#include <types.h>
#include <string.h>
#include <console/console.h>
#include <lib.h> // hexdump
#include "fsp_util.h"


Expand Down
4 changes: 0 additions & 4 deletions src/drivers/intel/fsp1_1/Kconfig
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Expand Up @@ -59,10 +59,6 @@ config FSP_LOC
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

config DISPLAY_FAST_BOOT_DATA
bool "Display fast boot data"
default n

config DISPLAY_HOBS
bool "Display hand-off-blocks (HOBs)"
default n
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_1/fsp_gop.c
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Expand Up @@ -16,7 +16,6 @@
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <fsp/util.h>
#include <lib.h>

int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/intel/fsp1_1/hob.c
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Expand Up @@ -17,11 +17,9 @@
#include <arch/early_variables.h>
#include <arch/hlt.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
#include <ip_checksum.h>
#include <lib.h> // hexdump
#include <string.h>

/* Compares two EFI GUIDs. Returns true of the GUIDs match, false otherwise. */
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/intel/fsp1_1/ramstage.c
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Expand Up @@ -16,8 +16,6 @@

#include <bootmode.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <cbfs.h>
#include <console/console.h>
#include <fsp/memmap.h>
#include <fsp/ramstage.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/intel/fsp1_1/stack.c
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Expand Up @@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_1/vbt.c
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Expand Up @@ -15,7 +15,6 @@
*/

#include <bootmode.h>
#include <cbfs.h>
#include <console/console.h>
#include <drivers/intel/gma/opregion.h>
#include <fsp/ramstage.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/graphics.c
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Expand Up @@ -10,7 +10,6 @@
* (at your option) any later version.
*/

#include <cbfs.h>
#include <console/console.h>
#include <fsp/util.h>
#include <soc/intel/common/vbt.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/hand_off_block.c
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Expand Up @@ -18,7 +18,6 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <inttypes.h>
#include <lib.h>
#include <string.h>

#define HOB_HEADER_LEN 8
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/memory_init.c
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Expand Up @@ -13,7 +13,6 @@

#include <security/vboot/antirollback.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <arch/symbols.h>
#include <assert.h>
#include <cbfs.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/notify.c
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Expand Up @@ -10,7 +10,6 @@
* (at your option) any later version.
*/

#include <arch/cpu.h>
#include <bootstate.h>
#include <console/console.h>
#include <fsp/util.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/silicon_init.c
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Expand Up @@ -10,7 +10,6 @@
* (at your option) any later version.
*/

#include <arch/cpu.h>
#include <cbfs.h>
#include <cbmem.h>
#include <commonlib/fsp.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/upd_display.c
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Expand Up @@ -9,7 +9,6 @@
* (at your option) any later version.
*/

#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/util.h>
#include <lib.h>
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/intel/fsp2_0/util.c
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Expand Up @@ -12,11 +12,9 @@
*/

#include <arch/io.h>
#include <cbfs.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <fsp/util.h>
#include <lib.h>
#include <string.h>

static bool looks_like_fsp_header(const uint8_t *raw_hdr)
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/gma/vbt.c
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Expand Up @@ -16,7 +16,6 @@
*/

#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <string.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/net/ne2k.c
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Expand Up @@ -28,7 +28,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02
*/

#include <arch/io.h>
#include <console/console.h>
#include <console/ne2k.h>
#include <delay.h>
#include <device/device.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/pc80/tpm/Makefile.inc
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@@ -1,3 +1,4 @@
verstage-$(CONFIG_LPC_TPM) += tis.c
romstage-$(CONFIG_LPC_TPM) += tis.c
ramstage-$(CONFIG_LPC_TPM) += tis.c
postcar-$(CONFIG_LPC_TPM) += tis.c
1 change: 0 additions & 1 deletion src/drivers/ricoh/rce822/rce822.c
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Expand Up @@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/siemens/nc_fpga/nc_fpga.c
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Expand Up @@ -14,7 +14,6 @@
*/

#include <types.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/spi/spi_flash.c
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Expand Up @@ -10,7 +10,6 @@
#include <arch/early_variables.h>
#include <assert.h>
#include <boot_device.h>
#include <cbfs.h>
#include <cpu/x86/smm.h>
#include <delay.h>
#include <rules.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/spi/tpm/Makefile.inc
View file
Expand Up @@ -2,3 +2,4 @@ bootblock-$(CONFIG_SPI_TPM) += tis.c tpm.c
verstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
romstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
ramstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
postcar-$(CONFIG_SPI_TPM) += tis.c tpm.c
8 changes: 6 additions & 2 deletions src/drivers/uart/Kconfig
View file
@@ -1,13 +1,15 @@
config DRIVERS_UART
bool
default y if CONSOLE_SERIAL
default n

config DRIVERS_UART_8250IO
# FIXME: Shouldn't have a prompt, should default to n, and
# should be selected by boards that have it instead.
bool "Serial port on SuperIO"
depends on ARCH_X86
default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL
default n if NO_UART_ON_SUPERIO
default y
select DRIVERS_UART

config DRIVERS_UART_8250IO_SKIP_INIT
def_bool n
Expand All @@ -34,6 +36,7 @@ config UART_OVERRIDE_REFCLK
config DRIVERS_UART_8250MEM
bool
default n
select DRIVERS_UART

config DRIVERS_UART_8250MEM_32
bool
Expand All @@ -43,6 +46,7 @@ config DRIVERS_UART_8250MEM_32
config HAVE_UART_SPECIAL
bool
default n
select DRIVERS_UART

config DRIVERS_UART_OXPCIE
bool "Oxford OXPCIe952"
Expand Down
20 changes: 15 additions & 5 deletions src/drivers/uart/uart8250io.c
View file
Expand Up @@ -16,11 +16,13 @@

#include <rules.h>
#include <stdlib.h>
#include <arch/early_variables.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <trace.h>
#include "uart8250reg.h"
#include "mainboard/pcengines/apu2/bios_knobs.h"

/* Should support 8250, 16450, 16550, 16550A type UARTs */

Expand All @@ -33,6 +35,8 @@
#define SINGLE_CHAR_TIMEOUT (50 * 1000)
#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)

static int port_index CAR_GLOBAL;

static int uart8250_can_tx_byte(unsigned base_port)
{
return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE;
Expand Down Expand Up @@ -106,31 +110,37 @@ void uart_init(int idx)
unsigned int div;
div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
if ((check_com2() || idx == 1) &&
!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
car_set_var(port_index, 1);
else
car_set_var(port_index, idx);

uart8250_init(uart_platform_base(car_get_var(port_index)), div);
}
}

void uart_tx_byte(int idx, unsigned char data)
{
uart8250_tx_byte(uart_platform_base(idx), data);
uart8250_tx_byte(uart_platform_base(car_get_var(port_index)), data);
}

unsigned char uart_rx_byte(int idx)
{
return uart8250_rx_byte(uart_platform_base(idx));
return uart8250_rx_byte(uart_platform_base(car_get_var(port_index)));
}

void uart_tx_flush(int idx)
{
uart8250_tx_flush(uart_platform_base(idx));
uart8250_tx_flush(uart_platform_base(car_get_var(port_index)));
}

#if ENV_RAMSTAGE
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baseaddr = uart_platform_base(car_get_var(port_index));
serial.baud = get_uart_baudrate();
serial.regwidth = 1;
serial.input_hertz = uart_platform_refclk();
Expand Down
1 change: 0 additions & 1 deletion src/drivers/uart/util.c
View file
Expand Up @@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <console/uart.h>
#include <types.h>
#include <timer.h>
Expand Down
8 changes: 0 additions & 8 deletions src/drivers/vpd/Kconfig
View file
Expand Up @@ -18,11 +18,3 @@ config VPD
default n
help
Enable support for flash based vital product data.

if VPD

config VPD_DEBUG
bool "Enable VPD debug output"
default n

endif
2 changes: 1 addition & 1 deletion src/drivers/xgi/common/xgi_coreboot.c
View file
Expand Up @@ -379,7 +379,7 @@ int xgifb_modeset(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info)

xgi_fb.reserved_mask_pos = 0;
xgi_fb.reserved_mask_size = 0;
switch(xgifb_info->video_bpp){
switch (xgifb_info->video_bpp) {
case 32:
case 24:
/* packed into 4-byte words */
Expand Down
2 changes: 1 addition & 1 deletion src/ec/google/chromeec/acpi/cros_ec.asl
View file
Expand Up @@ -25,7 +25,7 @@ Device (CREC)
#ifdef EC_ENABLE_SYNC_IRQ
Name (_CRS, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive)
{
EC_SYNC_IRQ
}
Expand Down
18 changes: 17 additions & 1 deletion src/ec/google/chromeec/acpi/ec.asl
View file
Expand Up @@ -52,6 +52,7 @@ Device (EC0)
PATC, 8, // Programmable Auxiliary Trip Commit
CHGL, 8, // Charger Current Limit
TBMD, 1, // Tablet mode
DDPN, 3, // Device DPTF Profile Number
// DFUD must be 0 for the other 31 values to be valid
Offset (0x0a),
DFUD, 1, // Device Features Undefined
Expand Down Expand Up @@ -371,7 +372,7 @@ Device (EC0)
{
Store ("EC: TABLET mode switch Event", Debug)
Notify (CREC, 0x2)
#ifdef EC_ENABLE_TABLET_EVENT
#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
\_SB.DPTF.TPET()
#endif
#ifdef EC_ENABLE_TBMC_DEVICE
Expand Down Expand Up @@ -509,6 +510,21 @@ Device (EC0)
Return (^TBMD)
}

/* Read current Device DPTF Profile Number */
Method (RCDP, 0, NotSerialized)
{
/*
* DDPN = 0 is reserved for backwards compatibility.
* If DDPN == 0 use TBMD to load appropriate DPTF table.
*/
If (LEqual (^DDPN, 0)) {
Return (^TBMD)
} Else {
Subtract (^DDPN, 1, Local0)
Return (Local0)
}
}

#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
/*
* Enable USB Port Power
Expand Down
14 changes: 12 additions & 2 deletions src/ec/google/chromeec/ec.c
View file
Expand Up @@ -611,10 +611,10 @@ int google_chromeec_cbi_get_oem_id(uint32_t *id)
return cbi_get_uint32(id, CBI_TAG_OEM_ID);
}

int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize)
static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag)
{
struct ec_params_get_cbi p = {
.tag = CBI_TAG_DRAM_PART_NUM,
.tag = tag,
};
struct chromeec_command cmd = {
.cmd_code = EC_CMD_GET_CROS_BOARD_INFO,
Expand All @@ -636,6 +636,16 @@ int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize)
return 0;
}

int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize)
{
return cbi_get_string(buf, bufsize, CBI_TAG_DRAM_PART_NUM);
}

int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize)
{
return cbi_get_string(buf, bufsize, CBI_TAG_OEM_NAME);
}

int google_chromeec_get_board_version(uint32_t *version)
{
struct chromeec_command cmd;
Expand Down
1 change: 1 addition & 0 deletions src/ec/google/chromeec/ec.h
View file
Expand Up @@ -84,6 +84,7 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags);
int google_chromeec_cbi_get_oem_id(uint32_t *id);
int google_chromeec_cbi_get_sku_id(uint32_t *id);
int google_chromeec_cbi_get_dram_part_num(char *buf, size_t bufsize);
int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize);

/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource. */
#define MEC_EMI_BASE 0x800
Expand Down
1 change: 1 addition & 0 deletions src/ec/google/chromeec/ec_commands.h
View file
Expand Up @@ -4781,6 +4781,7 @@ enum cbi_data_tag {
CBI_TAG_OEM_ID = 1, /* uint8_t */
CBI_TAG_SKU_ID = 2, /* uint8_t */
CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */
CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */
CBI_TAG_COUNT,
};

Expand Down
2 changes: 0 additions & 2 deletions src/ec/google/chromeec/vstore.c
View file
Expand Up @@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/


#include <console/console.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
Expand Down
2 changes: 0 additions & 2 deletions src/include/cpu/amd/model_10xxx_rev.h
View file
Expand Up @@ -16,8 +16,6 @@
#ifndef __CPU_AMD_MODEL_10XXX_REV_H__
#define __CPU_AMD_MODEL_10XXX_REV_H__

#include <arch/cpu.h>

int init_processor_name(void);

/* place holder for Family 10 revision code */
Expand Down
1 change: 0 additions & 1 deletion src/include/cpu/x86/cr.h
View file
Expand Up @@ -19,7 +19,6 @@
#if !defined(__ASSEMBLER__)

#include <stdint.h>
#include <arch/cpu.h>

/* ROMCC apparently chokes certain clobber registers. */
#if defined(__ROMCC__)
Expand Down
2 changes: 1 addition & 1 deletion src/include/memory_info.h
View file
Expand Up @@ -36,7 +36,7 @@ struct dimm_info {
/*
* SMBIOS (not SPD) device type.
*
* See the smbios.h smbios_memory_device_type enum.
* See the smbios.h smbios_memory_type enum.
*/
uint16_t ddr_type;
uint16_t ddr_frequency;
Expand Down
1 change: 1 addition & 0 deletions src/include/program_loading.h
View file
Expand Up @@ -36,6 +36,7 @@ enum prog_type {
PROG_PAYLOAD,
PROG_BL31,
PROG_BL32,
PROG_POSTCAR,
};

/*
Expand Down
36 changes: 6 additions & 30 deletions src/include/smbios.h
View file
Expand Up @@ -96,36 +96,6 @@ typedef enum {
MEMORY_BUS_WIDTH_MAX = 7,
} smbios_memory_bus_width;

typedef enum {
MEMORY_DEVICE_OTHER = 0x01,
MEMORY_DEVICE_UNKNOWN = 0x02,
MEMORY_DEVICE_DRAM = 0x03,
MEMORY_DEVICE_EDRAM = 0x04,
MEMORY_DEVICE_VRAM = 0x05,
MEMORY_DEVICE_SRAM = 0x06,
MEMORY_DEVICE_RAM = 0x07,
MEMORY_DEVICE_ROM = 0x08,
MEMORY_DEVICE_FLASH = 0x09,
MEMORY_DEVICE_EEPROM = 0x0A,
MEMORY_DEVICE_FEPROM = 0x0B,
MEMORY_DEVICE_EPROM = 0x0C,
MEMORY_DEVICE_CDRAM = 0x0D,
MEMORY_DEVICE_3DRAM = 0x0E,
MEMORY_DEVICE_SDRAM = 0x0F,
MEMORY_DEVICE_SGRAM = 0x10,
MEMORY_DEVICE_RDRAM = 0x11,
MEMORY_DEVICE_DDR = 0x12,
MEMORY_DEVICE_DDR2 = 0x13,
MEMORY_DEVICE_DDR2_FB_DIMM = 0x14,
MEMORY_DEVICE_DDR3 = 0x18,
MEMORY_DEVICE_DBD2 = 0x19,
MEMORY_DEVICE_DDR4 = 0x1A,
MEMORY_DEVICE_LPDDR = 0x1B,
MEMORY_DEVICE_LPDDR2 = 0x1C,
MEMORY_DEVICE_LPDDR3 = 0x1D,
MEMORY_DEVICE_LPDDR4 = 0x1E,
} smbios_memory_device_type;

typedef enum {
MEMORY_FORMFACTOR_OTHER = 0x01,
MEMORY_FORMFACTOR_UNKNOWN = 0x02,
Expand Down Expand Up @@ -167,6 +137,12 @@ typedef enum {
MEMORY_TYPE_DDR2_FBDIMM = 0x14,
MEMORY_TYPE_DDR3 = 0x18,
MEMORY_TYPE_FBD2 = 0x19,
MEMORY_TYPE_DDR4 = 0x1a,
MEMORY_TYPE_LPDDR = 0x1b,
MEMORY_TYPE_LPDDR2 = 0x1c,
MEMORY_TYPE_LPDDR3 = 0x1d,
MEMORY_TYPE_LPDDR4 = 0x1e,
MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f,
} smbios_memory_type;

typedef enum {
Expand Down
2 changes: 1 addition & 1 deletion src/lib/cbmem_common.c
View file
Expand Up @@ -12,7 +12,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>

#include <cbmem.h>
#include <bootstate.h>
#include <rules.h>
Expand Down
1 change: 0 additions & 1 deletion src/lib/hardwaremain.c
View file
Expand Up @@ -32,7 +32,6 @@
#include <reset.h>
#include <boot/tables.h>
#include <program_loading.h>
#include <lib.h>
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#include <arch/acpi.h>
#endif
Expand Down
1 change: 0 additions & 1 deletion src/lib/prog_loaders.c
View file
Expand Up @@ -29,7 +29,6 @@
#include <stage_cache.h>
#include <symbols.h>
#include <timestamp.h>
#include <cbfs.h>
#include <fit_payload.h>

/* Only can represent up to 1 byte less than size_t. */
Expand Down
1 change: 0 additions & 1 deletion src/lib/rmodule.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <lib.h>
#include <console/console.h>
#include <program_loading.h>
#include <rmodule.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/adi/rcc-dff/dsdt.asl
View file
Expand Up @@ -17,7 +17,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/adi/rcc-dff/romstage.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <southbridge/intel/fsp_rangeley/soc.h>
#include <southbridge/intel/fsp_rangeley/gpio.h>
#include <southbridge/intel/fsp_rangeley/romstage.h>
#include <arch/cpu.h>
#include "gpio.h"

static void interrupt_routing_config(void)
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/advansus/a785e-i/Kconfig
View file
Expand Up @@ -46,10 +46,6 @@ config MAX_PHYSICAL_CPUS
int
default 1

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/advansus/a785e-i/romstage.c
View file
Expand Up @@ -18,7 +18,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

#include <lib.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
Expand All @@ -29,7 +28,7 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/bettong/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <southbridge/amd/common/amd_pci_util.h>
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/amd/bettong/romstage.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/bimini_fam10/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_PHYSICAL_CPUS
int
default 2

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/amd/bimini_fam10/romstage.c
View file
Expand Up @@ -24,13 +24,12 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/msr.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/db-ft3b-lc/mptable.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_pci_util.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/db-ft3b-lc/romstage.c
View file
Expand Up @@ -29,7 +29,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/gardenia/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <soc/southbridge.h>
#include <amdblocks/amd_pci_util.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/inagua/BiosCallOuts.c
View file
Expand Up @@ -91,7 +91,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);

switch(MemData->ParameterListPtr->DDR3Voltage){
switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/inagua/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_CPUS
int
default 2

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
2 changes: 0 additions & 2 deletions src/mainboard/amd/lamar/mptable.c
View file
Expand Up @@ -19,11 +19,9 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
#include <northbridge/amd/pi/00630F01/pci_devs.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/lamar/romstage.c
View file
Expand Up @@ -29,7 +29,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <superio/fintek/f81216h/f81216h.h>
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/amd/mahogany_fam10/romstage.c
View file
Expand Up @@ -26,13 +26,12 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/olivehill/Kconfig
View file
Expand Up @@ -44,10 +44,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/olivehill/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/olivehillplus/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/olivehillplus/romstage.c
View file
Expand Up @@ -29,7 +29,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/parmer/Kconfig
View file
Expand Up @@ -44,10 +44,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/parmer/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/parmer/romstage.c
View file
Expand Up @@ -14,7 +14,6 @@
*/

#include <arch/io.h>
#include <arch/cpu.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>

Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/persimmon/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_CPUS
int
default 2

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
View file
Expand Up @@ -150,7 +150,7 @@ unsigned long mainboard_write_acpi_tables(struct device *device,
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); /* pci0 and pci1 are in dsdt */
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
switch (sysconf.hcid[i]) {
case 1:
file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
break;
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View file
Expand Up @@ -151,7 +151,7 @@ void get_bus_conf(void)
/* check hcid type here */
sysconf.hcid[i] = get_hcid(i);

switch(sysconf.hcid[i]) {
switch (sysconf.hcid[i]) {

case 1: /* 8132 */
case 3: /* 8131 */
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
View file
Expand Up @@ -13,7 +13,6 @@

#include <device/device.h>
#include <arch/acpi.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include "mainboard.h"

Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View file
Expand Up @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
if (!(sysconf.pci1234[i] & 0x1))
continue;

switch(sysconf.hcid[i]) {
switch (sysconf.hcid[i]) {
case 1:
case 3:
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
Expand Down Expand Up @@ -137,7 +137,7 @@ static void *smp_write_config_table(void *v)
int jj;
struct device *dev;
struct resource *res;
switch(sysconf.hcid[i]) {
switch (sysconf.hcid[i]) {
case 1:
case 3:
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View file
Expand Up @@ -24,14 +24,13 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <lib.h>
#include <spd.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/south_station/Kconfig
View file
Expand Up @@ -44,10 +44,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/thatcher/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/thatcher/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/amd/thatcher/romstage.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
#include <arch/cpu.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/amd/tilapia_fam10/romstage.c
View file
Expand Up @@ -24,13 +24,12 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/torpedo/BiosCallOuts.c
View file
Expand Up @@ -63,7 +63,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

switch(MemData->ParameterListPtr->DDR3Voltage){
switch (MemData->ParameterListPtr->DDR3Voltage) {
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/torpedo/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/union_station/Kconfig
View file
Expand Up @@ -43,10 +43,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/aopen/dxplplusu/dsdt.asl
View file
Expand Up @@ -18,7 +18,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x04, // DSDT revision: ACPI v4.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20111103 // OEM revision
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/aopen/dxplplusu/romstage.c
View file
Expand Up @@ -16,7 +16,6 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <stdlib.h>
#include <cbmem.h>
#include <console/console.h>
Expand Down
8 changes: 8 additions & 0 deletions src/mainboard/apple/macbook21/devicetree.cb
View file
Expand Up @@ -83,6 +83,11 @@ chip northbridge/intel/i945
end
device pci 1c.0 on end # Ethernet
device pci 1c.1 on end # Atheros WLAN
device pci 1c.2 off end # PCIe #3
device pci 1c.3 off end # PCIe #4
device pci 1c.4 off end # PCIe #5
device pci 1c.5 off end # PCIe #6

device pci 1d.0 on # USB UHCI
subsystemid 0x8086 0x7270
end
Expand All @@ -98,6 +103,9 @@ chip northbridge/intel/i945
device pci 1d.7 on # USB2 EHCI
subsystemid 0x8086 0x7270
end
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x8086 0x7270
end
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/apple/macbook21/dsdt.asl
View file
Expand Up @@ -21,7 +21,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20090419 // OEM revision
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/apple/macbook21/mainboard.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <northbridge/intel/i945/i945.h>
#include <arch/x86/include/arch/acpigen.h>
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/apple/macbook21/romstage.c
View file
Expand Up @@ -24,7 +24,6 @@
#include <device/pnp_def.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <timestamp.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
Expand Down Expand Up @@ -273,9 +272,7 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif

timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);

/* Perform some initialization that must run before stage2 */
early_ich7_init();
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/apple/macbook21/smihandler.c
View file
Expand Up @@ -49,7 +49,7 @@ int mainboard_io_trap_handler(int smif)

int mainboard_smi_apmc(u8 data)
{
switch(data) {
switch (data) {
case APM_CNT_ACPI_ENABLE:
/* route H8SCI to SCI */
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/apple/macbookair4_2/dsdt.asl
View file
Expand Up @@ -17,7 +17,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/apple/macbookair4_2/early_southbridge.c
View file
Expand Up @@ -13,7 +13,6 @@

#include <stdint.h>
#include <string.h>
#include <lib.h>
#include <arch/byteorder.h>
#include <arch/io.h>
#include <device/pci_def.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asrock/b75pro3-m/dsdt.asl
View file
Expand Up @@ -20,7 +20,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/asrock/e350m1/Kconfig
View file
Expand Up @@ -46,10 +46,6 @@ config MAX_CPUS
int
default 2

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
6 changes: 1 addition & 5 deletions src/mainboard/asrock/g41c-gs/Kconfig
View file
Expand Up @@ -62,11 +62,7 @@ config MAINBOARD_PART_NUMBER

config DEVICETREE
string
default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS
default "variants/g41m-s3/devicetree.cb" if BOARD_ASROCK_G41M_S3
default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"

config MAX_CPUS
int
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asrock/g41c-gs/dsdt.asl
View file
Expand Up @@ -19,7 +19,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20090419 // OEM revision
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
View file
Expand Up @@ -151,9 +151,6 @@ chip northbridge/intel/x4x # Northbridge
device i2c 69 on end
end
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end
3 changes: 0 additions & 3 deletions src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
View file
Expand Up @@ -131,9 +131,6 @@ chip northbridge/intel/x4x # Northbridge
device pci 1f.3 on # SMbus
subsystemid 0x1849 0x27da
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end
85 changes: 85 additions & 0 deletions src/mainboard/asrock/h81m-hds/Kconfig
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@@ -0,0 +1,85 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##

if BOARD_ASROCK_H81M_HDS

config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_4096
select CPU_INTEL_HASWELL
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
select NORTHBRIDGE_INTEL_HASWELL
select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776_COM_A
select TSC_MONOTONIC_TIMER

config CBFS_SIZE
hex
default 0x200000

#
# The override of GFX_GMA_CPU_VARIANT should be removed once the patches
# for dynamic CPU detection are merged in libgfxinit.
#
config GFX_GMA_CPU_VARIANT
string
default "Normal"

config MAINBOARD_DIR
string
default asrock/h81m-hds

config MAINBOARD_PART_NUMBER
string
default "H81M-HDS"

config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x8c5c

config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1849

# This is overridden if CMOS is used for configuration values.
config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
bool
default n

config MAX_CPUS
int
default 8

#
# Since this is a desktop board, the assumption is made that most users
# would want CMOS configuration enabled by default.
#
config USE_OPTION_TABLE
bool
default y

endif
2 changes: 2 additions & 0 deletions src/mainboard/asrock/h81m-hds/Kconfig.name
View file
@@ -0,0 +1,2 @@
config BOARD_ASROCK_H81M_HDS
bool "H81M-HDS"
17 changes: 17 additions & 0 deletions src/mainboard/asrock/h81m-hds/Makefile.inc
View file
@@ -0,0 +1,17 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##

ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
0 ...ainboard/intel/cougar_canyon2/acpi/ec.asl → src/mainboard/asrock/h81m-hds/acpi/ec.asl
View file
File renamed without changes.
15 changes: 9 additions & 6 deletions src/cpu/intel/fsp_model_206ax/bootblock.c → ...inboard/asrock/h81m-hds/acpi/platform.asl
View file
@@ -1,21 +1,24 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software; you can redistribute it and/or modify
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <cpu/intel/microcode/microcode.c>
Method(_WAK, 1)
{
Return (Package() { 0, 0 })
}

static void bootblock_cpu_init(void)
Method(_PTS, 1)
{
intel_update_microcode_from_cbfs();
}
26 changes: 26 additions & 0 deletions src/mainboard/asrock/h81m-hds/acpi/superio.asl
View file
@@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define NCT6776_SHOW_PP
#define NCT6776_SHOW_SP1
#define NCT6776_SHOW_KBC
#define NCT6776_SHOW_HWM

#undef NCT6776_SHOW_GPIO

#include <superio/nuvoton/nct6776/acpi/superio.asl>
21 changes: 21 additions & 0 deletions src/mainboard/asrock/h81m-hds/acpi_tables.c
View file
@@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <southbridge/intel/lynxpoint/nvs.h>

void acpi_create_gnvs(global_nvs_t *gnvs)
{
}
7 changes: 7 additions & 0 deletions src/mainboard/asrock/h81m-hds/board_info.txt
View file
@@ -0,0 +1,7 @@
Category: desktop
Board URL: https://www.asrock.com/mb/Intel/H81M-HDS/
ROM package: DIP-8
ROM protocol: SPI
ROM socketed: y
Flashrom support: y
Release year: 2013
4 changes: 4 additions & 0 deletions src/mainboard/asrock/h81m-hds/cmos.default
View file
@@ -0,0 +1,4 @@
boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable
60 changes: 23 additions & 37 deletions src/mainboard/intel/stargo2/cmos.layout → src/mainboard/asrock/h81m-hds/cmos.layout
View file
Expand Up @@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
## Copyright (C) 2014 Vladimir Serbinenko
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
Expand Down Expand Up @@ -36,42 +37,28 @@ entries
#112 8 r 0 diag_rsvd1

# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
#120 264 r 0 unused

# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
384 1 e 3 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?

# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
395 4 e 4 debug_level
#399 1 r 0 unused

# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
#400 8 r 0 reserved for century byte

# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 5 r 0 unused

# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
#544 440 r 0 unused

# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
409 2 e 1 power_on_after_fail

# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
984 16 h 0 check_sum

# -----------------------------------------------------------------

Expand All @@ -80,24 +67,23 @@ enumerations
#ID value text
1 0 Disable
1 1 Enable

2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 AHCI
8 1 Compatible

3 0 Fallback
3 1 Normal

4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew

# -----------------------------------------------------------------
checksums

Expand Down
Binary file added src/mainboard/asrock/h81m-hds/data.vbt
View file
Binary file not shown.
173 changes: 173 additions & 0 deletions src/mainboard/asrock/h81m-hds/devicetree.cb
View file
@@ -0,0 +1,173 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##

chip northbridge/intel/haswell
register "gpu_ddi_e_connected" = "1"

device cpu_cluster 0 on
chip cpu/intel/haswell
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"

device lapic 0 on end
device lapic 0xacac off end
end
end

device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x1849 0x0c00
end

device pci 01.0 on # PCIe graphics
subsystemid 0x1849 0x0c01
end

device pci 02.0 on # VGA controller
subsystemid 0x1849 0x0402
end

device pci 03.0 on # Mini-HD audio
subsystemid 0x1849 0x0c0c
end

chip southbridge/intel/lynxpoint
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8a"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x8a"

register "sata_ahci" = "1"
register "sata_port_map" = "0x33"

register "gen1_dec" = "0x00000295" # Super I/O HWM

device pci 14.0 on # xHCI controller
subsystemid 0x1849 0x8c31
end
device pci 16.0 on # Management Engine interface 1
subsystemid 0x1849 0x8c3a
end
device pci 16.1 off end # Management Engine interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on # EHCI controller #2
subsystemid 0x1849 0x8c2d
end
device pci 1b.0 on # HD audio controller
subsystemid 0x1849 0x7662
end
device pci 1c.0 on # PCIe port #1
subsystemid 0x1849 0x8c10
end
device pci 1c.1 off end # PCIe port #2
device pci 1c.2 off end # PCIe port #3
device pci 1c.3 on # Realtek Gigabit Ethernet
subsystemid 0x1849 0x8c16
chip drivers/net
register "customized_leds" = "0x0824"
device pci 00.0 on
subsystemid 0x1849 0x8168
end
end
end
device pci 1c.4 on # ASMedia USB controller
subsystemid 0x1849 0x8c18
device pci 00.0 on
subsystemid 0x1849 0x1042
end
end
device pci 1c.5 on # PCIe 1x slot
subsystemid 0x1849 0x8c1a
end
device pci 1c.6 off end # PCIe port #7
device pci 1c.7 off end # PCIe port #8
device pci 1d.0 on # EHCI controller #1
subsystemid 0x1849 0x8c26
end
device pci 1f.0 on # LPC bridge
subsystemid 0x1849 0x8c5c

chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel
io 0x60 = 0x0378
irq 0x70 = 7
drq 0x74 = 4 # No DMA
irq 0xf0 = 0x3c # Printer mode
end
device pnp 2e.2 on # UART A
io 0x60 = 0x03f8
irq 0x70 = 4
end
device pnp 2e.3 on # IR
io 0x60 = 0x02f8
irq 0x70 = 3
end
device pnp 2e.5 on # PS/2 KBC
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 1 # Keyboard
irq 0x72 = 12 # Mouse
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GPIO8
device pnp 2e.107 off end # GPIO9
device pnp 2e.8 off end # WDT
device pnp 2e.108 off end # GPIO0
device pnp 2e.208 off end # GPIOA
device pnp 2e.308 off end # GPIO base
device pnp 2e.109 off end # GPIO1
device pnp 2e.209 off end # GPIO2
device pnp 2e.309 off end # GPIO3
device pnp 2e.409 off end # GPIO4
device pnp 2e.509 off end # GPIO5
device pnp 2e.609 off end # GPIO6
device pnp 2e.709 off end # GPIO7
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HWM, LED
io 0x60 = 0x0290
io 0x62 = 0
irq 0x70 = 0
end
device pnp 2e.d off end # VID
device pnp 2e.e off end # CIR wake-up
device pnp 2e.f off end # GPIO PP/OD
device pnp 2e.14 off end # SVID
device pnp 2e.16 off end # Deep sleep
device pnp 2e.17 off end # GPIOA
end
end
device pci 1f.2 on # SATA controller 1
subsystemid 0x1849 0x8c02
end
device pci 1f.3 on # SMBus
subsystemid 0x1849 0x8c22
end
device pci 1f.5 off end # SATA controller 2
device pci 1f.6 off end # Thermal
end
end
end
41 changes: 41 additions & 0 deletions src/mainboard/asrock/h81m-hds/dsdt.asl
View file
@@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, /* DSDT Revision: ACPI v3.0 */
"COREv4", /* OEM ID */
"COREBOOT", /* OEM Table ID */
0x20181031 /* OEM Revision */
)
{
#include "acpi/platform.asl"
#include <southbridge/intel/lynxpoint/acpi/platform.asl>
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
#include <cpu/intel/haswell/acpi/cpu.asl>

Scope (\_SB)
{
Device (PCI0)
{
#include <northbridge/intel/haswell/acpi/haswell.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}
}
31 changes: 31 additions & 0 deletions src/mainboard/asrock/h81m-hds/gma-mainboard.ads
View file
@@ -0,0 +1,31 @@
--
-- This file is part of the coreboot project.
--
-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--

with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;

use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;

private package GMA.Mainboard is

ports : constant Port_List :=
(HDMI1,
HDMI3,
Analog,
others => Disabled);

end GMA.Mainboard;
168 changes: 168 additions & 0 deletions src/mainboard/asrock/h81m-hds/gpio.h
View file
@@ -0,0 +1,168 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#ifndef ASROCK_H81M_HDS_GPIO_H
#define ASROCK_H81M_HDS_GPIO_H

#include <southbridge/intel/common/gpio.h>

static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio31 = GPIO_MODE_GPIO,
};

static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};

static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio12 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_LOW,
.gpio15 = GPIO_LEVEL_LOW,
.gpio24 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
};

static const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio8 = GPIO_RESET_RSMRST,
};

static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio13 = GPIO_INVERT,
};

static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};

static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio42 = GPIO_MODE_GPIO,
.gpio43 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
};

static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio42 = GPIO_DIR_OUTPUT,
.gpio43 = GPIO_DIR_OUTPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio57 = GPIO_DIR_INPUT,
};

static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio35 = GPIO_LEVEL_LOW,
.gpio42 = GPIO_LEVEL_LOW,
.gpio43 = GPIO_LEVEL_LOW,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_HIGH,
};

static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};

static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_GPIO,
};

static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
};

static const struct pch_gpio_set3 pch_gpio_set3_level = {
};

static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};

const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

#endif /* ASROCK_H81M_HDS_GPIO_H */
39 changes: 39 additions & 0 deletions src/mainboard/asrock/h81m-hds/hda_verb.c
View file
@@ -0,0 +1,39 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <device/azalia_device.h>

const u32 cim_verb_data[] = {
0x10ec0662, /* Realtek ALC662 rev1 */
0x18497662, /* Subsystem ID */
11, /* Number of entries */
AZALIA_SUBVENDOR(1, 0x18497662),
AZALIA_PIN_CFG(1, 0x14, 0x01014010),
AZALIA_PIN_CFG(1, 0x15, 0x40000000),
AZALIA_PIN_CFG(1, 0x16, 0x411111f0),
AZALIA_PIN_CFG(1, 0x18, 0x01a19040),
AZALIA_PIN_CFG(1, 0x19, 0x02a19050),
AZALIA_PIN_CFG(1, 0x1a, 0x0181304f),
AZALIA_PIN_CFG(1, 0x1b, 0x02214020),
AZALIA_PIN_CFG(1, 0x1c, 0x411111f0),
AZALIA_PIN_CFG(1, 0x1d, 0x40a4c601),
AZALIA_PIN_CFG(1, 0x1e, 0x411111f0),
};

const u32 pc_beep_verbs[] = {};

AZALIA_ARRAY_SIZES;
29 changes: 29 additions & 0 deletions src/mainboard/asrock/h81m-hds/mainboard.c
View file
@@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <device/device.h>
#include <drivers/intel/gma/int15.h>

static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
131 changes: 131 additions & 0 deletions src/mainboard/asrock/h81m-hds/romstage.c
View file
@@ -0,0 +1,131 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include "gpio.h"

static const struct rcba_config_instruction rcba_config[] = {
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)),
RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),

RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),

RCBA_END_CONFIG,
};

void mainboard_config_superio(void)
{
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);

nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);

/* Select HWM/LED functions instead of floppy functions. */
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);

/* Power RAM in S3 and let the PCH handle power failure actions. */
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe4, 0x70);

/*
* Don't know what's needed here, just set the same as the vendor
* firmware.
*/
pnp_set_logical_device(IR_DEV);
pnp_write_config(IR_DEV, 0xf1, 0x5c);

nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}

void mainboard_romstage_entry(unsigned long bist)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = DEFAULT_PCIEXBAR,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
.system_type = 1, /* desktop/server */
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
.dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */
.dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */
.max_ddr3_freq = 1600,
.usb2_ports = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 2, USB_PORT_BACK_PANEL },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
},
.usb3_ports = {
/* Enable, OCn# */
{ 1, 0 },
{ 1, 0 },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
},
};

struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0],
.bist = bist,
};

romstage_common(&romstage_params);
}
4 changes: 0 additions & 4 deletions src/mainboard/asrock/imb-a180/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asrock/imb-a180/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>

Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/asus/am1i-a/Kconfig
View file
Expand Up @@ -34,10 +34,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 9
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/am1i-a/mptable.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/f2a85-m/BiosCallOuts.c
View file
Expand Up @@ -17,7 +17,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>

#include <cbfs.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <stdlib.h>

Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/asus/f2a85-m/Kconfig
View file
Expand Up @@ -74,10 +74,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config HUDSON_XHCI_FWM
bool
default n
Expand Down
2 changes: 0 additions & 2 deletions src/mainboard/asus/f2a85-m/mptable.c
View file
Expand Up @@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
Expand All @@ -23,7 +22,6 @@
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>


u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/kcma-d8/dsdt.asl
View file
Expand Up @@ -33,7 +33,7 @@
DefinitionBlock (
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
0x02, /* DSDT Revision, needs to be 2 or higher for 64bit */
"ASUS ", /* OEMID */
"COREBOOT", /* TABLE ID */
0x00000001 /* OEM Revision */
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/asus/kcma-d8/resourcemap.c
View file
Expand Up @@ -17,6 +17,8 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>

static void setup_mb_resource_map(void)
{
static const unsigned int fam15h_register_values[] = {
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/asus/kcma-d8/romstage.c
View file
Expand Up @@ -22,16 +22,15 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <cpu/x86/bist.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/kfsn4-dre/get_bus_conf.c
View file
Expand Up @@ -26,7 +26,6 @@
#include <stdlib.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <stdlib.h>

/*
* Global variables for MB layouts and these will be shared by irqtable,
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/asus/kfsn4-dre/romstage.c
View file
Expand Up @@ -25,11 +25,11 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cbmem.h>
#include <cpu/amd/model_10xxx_rev.h>
Expand All @@ -38,7 +38,6 @@
#include <southbridge/amd/common/reset.h>
#include <southbridge/nvidia/ck804/early_smbus.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <cpu/x86/bist.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/kgpe-d16/dsdt.asl
View file
Expand Up @@ -33,7 +33,7 @@
DefinitionBlock (
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
0x02, /* DSDT Revision, needs to be 2 or higher for 64bit */
"ASUS ", /* OEMID */
"COREBOOT", /* TABLE ID */
0x00000001 /* OEM Revision */
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/asus/kgpe-d16/resourcemap.c
View file
Expand Up @@ -17,6 +17,8 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>

static void setup_mb_resource_map(void)
{
static const unsigned int fam15h_register_values[] = {
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/asus/kgpe-d16/romstage.c
View file
Expand Up @@ -22,16 +22,15 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <delay.h>
#include <cpu/x86/lapic.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <cpu/x86/bist.h>
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/asus/m4a78-em/romstage.c
View file
Expand Up @@ -25,13 +25,12 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/asus/m4a785-m/romstage.c
View file
Expand Up @@ -26,13 +26,12 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/asus/m5a88-v/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_PHYSICAL_CPUS
int
default 1

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/asus/m5a88-v/romstage.c
View file
Expand Up @@ -20,18 +20,17 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

#include <lib.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/maximus_iv_gene-z/dsdt.asl
View file
Expand Up @@ -17,7 +17,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, /* DSDT Revision: ACPI v3.0 */
0x02, /* DSDT Revision: ACPI v2.0 and up */
"COREv4", /* OEM ID */
"COREBOOT", /* OEM Table ID */
0x20171231 /* OEM Revision */
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/p2b-ds/romstage.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83977tf/w83977tf.h>
#include <lib.h>
#include <cbmem.h>

#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/p2b-ls/romstage.c
View file
Expand Up @@ -24,7 +24,6 @@
#include <superio/winbond/common/winbond.h>
/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
#include <superio/winbond/w83977tf/w83977tf.h>
#include <lib.h>
#include <cbmem.h>

#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/p2b/romstage.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83977tf/w83977tf.h>
#include <lib.h>
#include <cbmem.h>

#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/p3b-f/romstage.c
View file
Expand Up @@ -24,7 +24,6 @@
#include <superio/winbond/common/winbond.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#include <superio/winbond/w83977tf/w83977tf.h>
#include <lib.h>
#include <cbmem.h>

/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
Expand Down
10 changes: 6 additions & 4 deletions src/mainboard/asus/p5gc-mx/devicetree.cb
View file
Expand Up @@ -62,10 +62,10 @@ chip northbridge/intel/i945
end
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
#device pci 1c.2 off end # PCIe port 3
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
device pci 1c.2 off end # PCIe port 3
device pci 1c.3 off end # PCIe port 4
device pci 1c.4 off end # PCIe port 5
device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on # USB UHCI
ioapic_irq 2 INTA 0x10
end
Expand All @@ -82,6 +82,8 @@ chip northbridge/intel/i945
ioapic_irq 2 INTA 0x10
end
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem

device pci 1f.0 on # LPC bridge
ioapic_irq 2 INTA 0x10
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/p5gc-mx/dsdt.asl
View file
Expand Up @@ -16,7 +16,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20090419 // OEM revision
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/asus/p5gc-mx/romstage.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <arch/acpi.h>
#include <timestamp.h>
#include <superio/winbond/common/winbond.h>
Expand Down Expand Up @@ -235,9 +234,7 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif

timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
timestamp_add_now(TS_AFTER_INITRAM);

/* Perform some initialization that must run before stage2 */
early_ich7_init();
Expand Down
17 changes: 13 additions & 4 deletions src/mainboard/asus/p5qc/Kconfig
View file
Expand Up @@ -14,7 +14,7 @@
# GNU General Public License for more details.
#

if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO
if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO

config BOARD_SPECIFIC_OPTIONS
def_bool y
Expand All @@ -38,16 +38,22 @@ config VARIANT_DIR
string
default "p5qc" if BOARD_ASUS_P5QC
default "p5q_pro" if BOARD_ASUS_P5Q_PRO
default "p5ql_pro" if BOARD_ASUS_P5QL_PRO

config MAINBOARD_PART_NUMBER
string
default "P5QC" if BOARD_ASUS_P5QC
default "P5Q PRO" if BOARD_ASUS_P5Q_PRO
default "P5QL PRO" if BOARD_ASUS_P5QL_PRO

config DEVICETREE
string
default "variants/p5qc/devicetree.cb" if BOARD_ASUS_P5QC
default "variants/p5q_pro/devicetree.cb" if BOARD_ASUS_P5Q_PRO
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"

config GPIO_C
string
default "variants/p5ql_pro/gpio.c" if BOARD_ASUS_P5QL_PRO
default "gpio.c"

config MAX_CPUS
int
Expand All @@ -56,8 +62,11 @@ config MAX_CPUS
# The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable
# bogus disk. Compiling SeaBIOS without ATA support is a workaround.

# The Asus P5QL PRO's Marvell controller (88SE6102-NNC2) does not need this, apparently.

config PAYLOAD_CONFIGFILE
string
default "" if PAYLOAD_SEABIOS && BOARD_ASUS_P5QL_PRO
default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS

endif # BOARD_ASUS_P5QC
endif # BOARD_ASUS_P5Q*
3 changes: 3 additions & 0 deletions src/mainboard/asus/p5qc/Kconfig.name
View file
Expand Up @@ -3,3 +3,6 @@ config BOARD_ASUS_P5QC

config BOARD_ASUS_P5Q_PRO
bool "P5Q PRO"

config BOARD_ASUS_P5QL_PRO
bool "P5QL PRO"
4 changes: 3 additions & 1 deletion src/mainboard/asus/p5qc/Makefile.inc
View file
Expand Up @@ -11,5 +11,7 @@
# GNU General Public License for more details.
#

CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C))

ramstage-y += cstates.c
romstage-y += gpio.c
romstage-y += $(CONFIG_GPIO_C)
2 changes: 1 addition & 1 deletion src/mainboard/asus/p5qc/dsdt.asl
View file
Expand Up @@ -19,7 +19,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x00000001 // OEM revision
Expand Down
127 changes: 127 additions & 0 deletions src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
View file
@@ -0,0 +1,127 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
# Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#

chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller
device pci 2.1 off end # Integrated graphics controller 2
device pci 3.0 off end # ME
device pci 3.1 off end # ME
device pci 3.2 off end # ME
device pci 3.3 off end # ME
device pci 6.0 off end # PEG 2
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"

# Set AHCI mode.
register "sata_port_map" = "0x3f"
register "sata_clock_request" = "0"
register "sata_traffic_monitor" = "0"

# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"

device pci 19.0 off end # GBE
device pci 1a.0 on end # USB
device pci 1a.1 on end # USB
device pci 1a.2 on end # USB
device pci 1a.7 on end # USB
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1
device pci 1c.1 on end # PCIe 2 PCIe x1 Slot #2
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 on end # PCIe 5 Marvell IDE
device pci 1c.5 on end # PCIe 6 Atheros LAN
device pci 1d.0 on end # USB
device pci 1d.1 on end # USB
device pci 1d.2 on end # USB
device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/winbond/w83667hg-a # Super I/O
device pnp 2e.0 on # FDC
# Global registers
irq 0x2a = 0x30
irq 0x2c = 0x22
irq 0x2d = 0x00
io 0x60 = 0x3f0
irq 0x70 = 0x06
end
device pnp 2e.1 off end # LPT1
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2
device pnp 2e.5 on # PS/2 keyboard & mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.106 off end # SPI1
device pnp 2e.107 off end # GPIO6
device pnp 2e.207 off end # GPIO7
device pnp 2e.307 on # GPIO8
irq 0xe4 = 0xfb
irq 0xe5 = 0x82
end
device pnp 2e.407 off end # GPIO9
device pnp 2e.8 off end # WDT
device pnp 2e.108 off end # GPIO1
device pnp 2e.9 off end # GPIO2
device pnp 2e.109 on end # GPIO3
device pnp 2e.209 on # GPIO4
irq 0xf0 = 0xff
irq 0xfe = 0x07
end
device pnp 2e.309 on end # GPIO5
device pnp 2e.a on # ACPI
irq 0xe4 = 0x10 # 3VSBSW# enable
irq 0xe5 = 0x02
irq 0xf2 = 0xfc
end
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 0x0
# IRQ purposefully not assigned to prevent lockups
end
device pnp 2e.c on end # PECI
device pnp 2e.d on end # VID_BUSSEL
device pnp 2e.f on end # GPIO_PP_OD
end
end
device pci 1f.1 off end # PATA/IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMbus
device pci 1f.4 off end
device pci 1f.5 off end # IDE
device pci 1f.6 on end # Thermal
end
end
end
158 changes: 158 additions & 0 deletions src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c
View file
@@ -0,0 +1,158 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <southbridge/intel/common/gpio.h>

static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_GPIO,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_GPIO,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_GPIO,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
};

static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio1 = GPIO_DIR_OUTPUT,
.gpio2 = GPIO_DIR_OUTPUT,
.gpio3 = GPIO_DIR_OUTPUT,
.gpio4 = GPIO_DIR_OUTPUT,
.gpio5 = GPIO_DIR_OUTPUT,
.gpio6 = GPIO_DIR_OUTPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_OUTPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_OUTPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_OUTPUT,
.gpio18 = GPIO_DIR_OUTPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_OUTPUT,
.gpio21 = GPIO_DIR_OUTPUT,
.gpio22 = GPIO_DIR_OUTPUT,
.gpio23 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_OUTPUT,
};

static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio1 = GPIO_LEVEL_HIGH,
.gpio2 = GPIO_LEVEL_HIGH,
.gpio3 = GPIO_LEVEL_HIGH,
.gpio4 = GPIO_LEVEL_HIGH,
.gpio5 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio9 = GPIO_LEVEL_LOW,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_LOW,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio17 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio21 = GPIO_LEVEL_HIGH,
.gpio22 = GPIO_LEVEL_HIGH,
.gpio23 = GPIO_LEVEL_HIGH,
.gpio27 = GPIO_LEVEL_HIGH,
.gpio28 = GPIO_LEVEL_LOW,
};

static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio7 = GPIO_INVERT,
.gpio10 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};

static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
.gpio60 = GPIO_MODE_GPIO,
};

static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio36 = GPIO_DIR_OUTPUT,
.gpio37 = GPIO_DIR_OUTPUT,
.gpio38 = GPIO_DIR_OUTPUT,
.gpio39 = GPIO_DIR_OUTPUT,
.gpio48 = GPIO_DIR_OUTPUT,
.gpio49 = GPIO_DIR_OUTPUT,
.gpio56 = GPIO_DIR_OUTPUT,
.gpio60 = GPIO_DIR_OUTPUT,
};

static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_LOW,
.gpio35 = GPIO_LEVEL_LOW,
.gpio36 = GPIO_LEVEL_HIGH,
.gpio37 = GPIO_LEVEL_HIGH,
.gpio38 = GPIO_LEVEL_HIGH,
.gpio39 = GPIO_LEVEL_HIGH,
.gpio48 = GPIO_LEVEL_LOW,
.gpio49 = GPIO_LEVEL_HIGH,
.gpio56 = GPIO_LEVEL_HIGH,
.gpio57 = GPIO_LEVEL_LOW,
.gpio60 = GPIO_LEVEL_HIGH,
};

const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
};
2 changes: 1 addition & 1 deletion src/mainboard/asus/p8h61-m_lx/dsdt.asl
View file
Expand Up @@ -17,7 +17,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, /* DSDT Revision: ACPI v3.0 */
0x02, /* DSDT Revision: ACPI v2.0 and up */
"COREv4", /* OEM ID */
"COREBOOT", /* OEM Table ID */
0x20171231 /* OEM Revision */
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/p8h61-m_pro/dsdt.asl
View file
Expand Up @@ -17,7 +17,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/avalue/eax-785e/Kconfig
View file
Expand Up @@ -46,10 +46,6 @@ config MAX_PHYSICAL_CPUS
int
default 1

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/avalue/eax-785e/romstage.c
View file
Expand Up @@ -18,18 +18,17 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0

#include <lib.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/x86/lapic.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/bap/ode_e20XX/Kconfig
View file
Expand Up @@ -45,10 +45,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/bap/ode_e20XX/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/bap/ode_e21XX/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/bap/ode_e21XX/romstage.c
View file
Expand Up @@ -29,7 +29,6 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81866d/f81866d.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/biostar/a68n_5200/Kconfig
View file
Expand Up @@ -46,10 +46,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/biostar/a68n_5200/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/agesa/hudson/hudson.h>

Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/biostar/am1ml/Kconfig
View file
Expand Up @@ -47,10 +47,6 @@ config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 10
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/biostar/am1ml/mptable.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <drivers/generic/ioapic/chip.h>
Expand Down
5 changes: 1 addition & 4 deletions src/mainboard/cavium/cn8100_sff_evb/Kconfig
View file
Expand Up @@ -17,7 +17,7 @@ if BOARD_CAVIUM_CN8100_SFF_EVB

config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select BOARD_ROMSIZE_KB_8192
select COMMON_CBFS_SPI_WRAPPER
select RTC
select SOC_CAVIUM_CN81XX
Expand Down Expand Up @@ -61,9 +61,6 @@ config MAX_CPUS
##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
config DEVICETREE
string
default "devicetree.cb"

config MAINBOARD_PART_NUMBER
string
Expand Down
23 changes: 7 additions & 16 deletions src/mainboard/cavium/cn8100_sff_evb/board.fmd
View file
@@ -1,24 +1,15 @@
FLASH@0x0 8M {
WP_RO@0x0 0x400000 {
RO_SECTION@0x0 0x200000 {
WP_RO@0x0 0x800000 {
RO_SECTION@0x0 0x7fc000 {
# 0 - 0x10000 is free for firmware usage.
# bootblock starts at 0x20000
FMAP@0x0 0x1000
# bootblock includes trusted/non-trusted CLIB, CSIB,
# and BL1FWs packaged in
# src/soc/cavium/common/Makefile.inc.
BOOTBLOCK@0x10000 0x70000
FMAP@0x90000 0x1000
COREBOOT(CBFS)@0x100000 0x100000
COREBOOT(CBFS)@0x80000 0x77c000
}
RO_VPD@0x7fc000 0x4000
}
RW_SECTION_A@0x400000 0xe8000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0xe5f00
RW_FWID_A@0xe7f00 0x100
}
RW_UNUSED@0x4e8000 0x8000
RW_ELOG@0x5d8000 0x1000
RW_SHARED@0x5e0000 0x10000 {
SHARED_DATA@0x0 0x10000
}
RW_NVRAM@0x5f0000 0x10000
CONSOLE@0x700000 0x100000
}
1 change: 0 additions & 1 deletion src/mainboard/cavium/cn8100_sff_evb/mainboard.c
View file
Expand Up @@ -25,7 +25,6 @@
#include <soc/uart.h>
#include <console/console.h>
#include <soc/clock.h>
#include <soc/gpio.h>
#include <soc/timer.h>
#include <soc/cpu.h>
#include <soc/sdram.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/compulab/intense_pc/dsdt.asl
View file
Expand Up @@ -20,7 +20,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
0x02, // DSDT revision: ACPI v2.0 and up
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/compulab/intense_pc/romstage.c
View file
Expand Up @@ -14,7 +14,6 @@
*/

#include <stdint.h>
#include <lib.h>
#include <arch/io.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <superio/smsc/sio1007/chip.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/cubietech/cubieboard/romstage.c
View file
Expand Up @@ -24,7 +24,6 @@
*/

#include <arch/stages.h>
#include <cbfs.h>
#include <console/console.h>
#include <cpu/allwinner/a10/clock.h>
#include <cpu/allwinner/a10/gpio.h>
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/elmex/pcm205400/Kconfig
View file
Expand Up @@ -53,10 +53,6 @@ config MAX_CPUS
int
default 2

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11
Expand Down
16 changes: 14 additions & 2 deletions src/mainboard/emulation/qemu-i440fx/Kconfig
View file
Expand Up @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_256
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select BOOTBLOCK_CONSOLE

config MAINBOARD_DIR
string
Expand All @@ -25,12 +26,23 @@ config IRQ_SLOT_COUNT
int
default 6

# Skip the first 64KiB as coreboot table pointer is installed
# at address 0
config DCACHE_RAM_BASE
hex
default 0xd0000
default 0x10000

# Memory at 0xa0000 decodes to VGA
config DCACHE_RAM_SIZE
hex
default 0x10000
default 0x90000

config C_ENV_BOOTBLOCK_SIZE
hex
default 0x4000

config DCACHE_BSP_STACK_SIZE
hex
default 0x4000

endif # BOARD_EMULATION_QEMU_X86_I440FX
3 changes: 2 additions & 1 deletion src/mainboard/emulation/qemu-i440fx/Makefile.inc
View file
@@ -1,3 +1,4 @@
cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
ramstage-y += northbridge.c
ramstage-y += fw_cfg.c
romstage-y += memory.c
ramstage-y += memory.c
3 changes: 0 additions & 3 deletions src/mainboard/emulation/qemu-i440fx/acpi_tables.c
View file
Expand Up @@ -14,14 +14,11 @@
*/

#include <types.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>

#include "fw_cfg.h"
#include "acpi.h"
Expand Down