16 changes: 15 additions & 1 deletion src/drivers/analogix/anx7625/anx7625.c
View file
Expand Up @@ -381,7 +381,7 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0,
(n & 0xff));
/* diff */
ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d);
ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, dt->k_val);

ret |= anx7625_odfc_config(bus, post_divider - 1);

Expand Down Expand Up @@ -804,6 +804,20 @@ static void anx7625_parse_edid(const struct edid *edid,
dt->vback_porch = (edid->mode.vbl - edid->mode.vso -
edid->mode.vspw - edid->mode.vborder);

/*
* The k_val is a ratio to match MIPI input and DP output video clocks.
* Most panels can follow the default value (0x3d).
* IVO panels have smaller variation than DP CTS spec and need smaller
* k_val (0x3b).
*/
if (!strncmp(edid->manufacturer_name, "IVO", 3)) {
dt->k_val = 0x3b;
ANXINFO("detected IVO panel, use k value 0x3b\n");
} else {
dt->k_val = 0x3d;
ANXINFO("set default k value to 0x3d for panel\n");
}

ANXINFO("pixelclock(%d).\n"
" hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n"
" vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
Expand Down
1 change: 1 addition & 0 deletions src/drivers/analogix/anx7625/anx7625.h
View file
Expand Up @@ -350,6 +350,7 @@ struct display_timing {
unsigned int vfront_porch;
unsigned int vback_porch;
unsigned int vsync_len;
unsigned int k_val;
};

int anx7625_dp_start(uint8_t bus, const struct edid *edid);
Expand Down
6 changes: 3 additions & 3 deletions src/drivers/elog/elog.c
View file
Expand Up @@ -246,7 +246,7 @@ static size_t elog_is_event_valid(size_t offset)
if (len < (sizeof(*event) + sizeof(checksum)))
return 0;

if (len > MAX_EVENT_SIZE)
if (len > ELOG_MAX_EVENT_SIZE)
return 0;

event = elog_get_event_buffer(offset, len);
Expand Down Expand Up @@ -613,7 +613,7 @@ int elog_clear(void)
static int elog_find_flash(void)
{
size_t total_size;
size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE;
size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * ELOG_MAX_EVENT_SIZE;
struct region_device *rdev = &elog_state.nv_dev;

elog_debug("%s()\n", __func__);
Expand Down Expand Up @@ -801,7 +801,7 @@ int elog_add_event_raw(u8 event_type, void *data, u8 data_size)

/* Header + Data + Checksum */
event_size = sizeof(*event) + data_size + 1;
if (event_size > MAX_EVENT_SIZE) {
if (event_size > ELOG_MAX_EVENT_SIZE) {
printk(BIOS_ERR, "ELOG: Event(%X) data size too "
"big (%d)\n", event_type, event_size);
return -1;
Expand Down
3 changes: 3 additions & 0 deletions src/drivers/genesyslogic/gl9755/gl9755.c
View file
Expand Up @@ -28,6 +28,9 @@ static void gl9755_enable(struct device *dev)
reg |= CFG2_LAT_L1_64US;
pci_write_config32(dev, CFG2, reg);

/* Disable ASPM L0s support */
pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT);

/* Turn off debug mode to enable SCP/OCP */
pci_and_config32(dev, CFG3, ~SCP_DEBUG);

Expand Down
1 change: 1 addition & 0 deletions src/drivers/genesyslogic/gl9755/gl9755.h
View file
Expand Up @@ -10,6 +10,7 @@
#define CFG2 0x48
#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3))
#define CFG2_LAT_L1_64US ((0x6 << 12) | (0x6 << 3))
#define CFG2_L0S_SUPPORT (0x1 << 6)
#define LTR 0x5C
#define SNOOP_VALUE 0x25
#define SNOOP_SCALE (0x3 << 10)
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/gfx/generic/chip.h
View file
Expand Up @@ -48,6 +48,4 @@ struct drivers_gfx_generic_config {
struct drivers_gfx_generic_device_config device[5];
};

extern struct device *find_gfx_dev(void);

#endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */
11 changes: 0 additions & 11 deletions src/drivers/gfx/generic/generic.c
View file
Expand Up @@ -155,14 +155,3 @@ struct chip_operations drivers_gfx_generic_ops = {
CHIP_NAME("Generic Graphics Device")
.enable_dev = gfx_enable
};

struct device *find_gfx_dev(void)
{
struct device *dev;

for (dev = all_devices; dev; dev = dev->next) {
if (dev->chip_ops && dev->chip_ops == &drivers_gfx_generic_ops)
return dev;
}
return NULL;
}
4 changes: 0 additions & 4 deletions src/drivers/gic/Kconfig
View file

This file was deleted.

1 change: 0 additions & 1 deletion src/drivers/gic/Makefile.inc
View file

This file was deleted.

147 changes: 0 additions & 147 deletions src/drivers/gic/gic.c
View file

This file was deleted.

61 changes: 0 additions & 61 deletions src/drivers/gic/gic.h
View file

This file was deleted.

5 changes: 5 additions & 0 deletions src/drivers/i2c/max98390/chip.h
View file
Expand Up @@ -13,4 +13,9 @@ struct drivers_i2c_max98390_config {
const char *r0_calib_key;
/* The VPD key of temperature during speaker calibration. */
const char *temperature_calib_key;
const char *dsm_param_file_name;
/* slot number where voltage feedback will be received */
uint32_t vmon_slot_no;
/* slot number where current feedback will be received */
uint32_t imon_slot_no;
};
29 changes: 27 additions & 2 deletions src/drivers/i2c/max98390/max98390.c
View file
Expand Up @@ -25,8 +25,9 @@ static void max98390_fill_ssdt(const struct device *dev)
.speed = I2C_SPEED_FAST,
.resource = scope,
};
struct acpi_dp *dp;
struct acpi_dp *dp = NULL;
uint64_t r0_value, temp_value;
char dsm_name[80] = {};

if (!scope)
return;
Expand Down Expand Up @@ -58,11 +59,35 @@ static void max98390_fill_ssdt(const struct device *dev)
dp = acpi_dp_new_table("_DSD");
MAX98390_DP_INT("r0_calib", r0_value);
MAX98390_DP_INT("temperature_calib", temp_value);
acpi_dp_write(dp);
printk(BIOS_INFO, "set dsm_calib properties\n");
}
}

if (CONFIG(CHROMEOS_DSM_PARAM_FILE_NAME)) {
if (config->dsm_param_file_name) {
if (!dp)
dp = acpi_dp_new_table("_DSD");

size_t chars = snprintf(dsm_name, sizeof(dsm_name), "%s_%s_%s.bin",
config->dsm_param_file_name, CONFIG_MAINBOARD_VENDOR,
CONFIG_MAINBOARD_PART_NUMBER);

if (chars >= sizeof(dsm_name))
printk(BIOS_ERR, "ERROR: String too long in %s\n", __func__);

acpi_dp_add_string(dp, "maxim,dsm_param_name", dsm_name);
}
}

if (!dp)
dp = acpi_dp_new_table("_DSD");

acpi_dp_add_integer(dp, "maxim,vmon-slot-no", config->vmon_slot_no);
acpi_dp_add_integer(dp, "maxim,imon-slot-no", config->imon_slot_no);

if (dp)
acpi_dp_write(dp);

acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */

Expand Down
16 changes: 16 additions & 0 deletions src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -274,4 +274,20 @@ config SOC_INTEL_COMMON_FSP_RESET
Common code block to handle platform reset request raised by FSP. The FSP
will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that
a reset is required.

config FSPS_HAS_ARCH_UPD
bool
help
SoC users must select this Kconfig if the `FSPS_UPD` header has architecture
UPD structure as `FSPS_ARCH_UPD`. Typically, platform with FSP 2.2 specification
onwards has support for `FSPS_ARCH_UPD` section as part of `FSPS_UPD` structure.
But there are some exceptions as in TGL, JSL, XEON_SP FSP header doesn't have
support for FSPS_ARCH_UPD.

config FSPS_USE_MULTI_PHASE_INIT
bool
help
SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
execute FspMultiPhaseSiInit() API.

endif
9 changes: 9 additions & 0 deletions src/drivers/intel/fsp2_0/Makefile.inc
View file
Expand Up @@ -110,8 +110,17 @@ endif # CONFIG_FSP_M_FILE
ifeq ($(call strip_quotes,$(CONFIG_FSP_S_FILE)),)
$(error No FSP-S binary file specified.)
endif # CONFIG_FSP_S_FILE
else # CONFIG_ADD_FSP_BINARIES
build_complete:: warn_no_fsp_binaries
endif # CONFIG_ADD_FSP_BINARIES

PHONY+=warn_no_fsp_binaries
warn_no_fsp_binaries:
printf "\n\t** WARNING **\n"
printf "ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP.\n"
printf "The resulting image won't contain the FSP binaries and will not boot unless\n"
printf "they are added later.\n"

subdirs-y += ppi

endif
5 changes: 3 additions & 2 deletions src/drivers/intel/fsp2_0/graphics.c
View file
Expand Up @@ -49,7 +49,8 @@ static const struct fsp_framebuffer {
};


void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar)
void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar,
enum lb_fb_orientation orientation)
{
size_t size;
const struct hob_graphics_info *ginfo;
Expand Down Expand Up @@ -94,7 +95,7 @@ void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar)
.blue_mask_size = fbinfo->blue.size,
.reserved_mask_pos = fbinfo->rsvd.pos,
.reserved_mask_size = fbinfo->rsvd.size,
.orientation = LB_FB_ORIENTATION_NORMAL,
.orientation = orientation,
};

fb_add_framebuffer_info_ex(&fb);
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/intel/fsp2_0/include/fsp/api.h
View file
Expand Up @@ -47,8 +47,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
/* Callbacks for SoC/Mainboard specific overrides */
void platform_fsp_multi_phase_init_cb(uint32_t phase_index);
/* Check if SoC sets EnableMultiPhaseSiliconInit UPD */
int soc_fsp_multi_phase_init_is_enable(void);
/* Check if MultiPhase Si Init is enabled */
bool fsp_is_multi_phase_init_enabled(void);
/*
* The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION
* is employed allowing the mainboard and SoC to supply their own version
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/intel/fsp2_0/include/fsp/graphics.h
View file
Expand Up @@ -11,6 +11,7 @@
* Must be called after PCI enumeration to make sure that the BAR
* doesn't change any more.
*/
void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar);
void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar,
enum lb_fb_orientation orientation);

#endif /* _FSP2_0_GRAPHICS_H_ */
28 changes: 20 additions & 8 deletions src/drivers/intel/fsp2_0/silicon_init.c
View file
Expand Up @@ -29,11 +29,6 @@ void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index)
/* Leave for the SoC/Mainboard to implement if necessary. */
}

int __weak soc_fsp_multi_phase_init_is_enable(void)
{
return 1;
}

/* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2
* has multiple stages as below.
*/
Expand Down Expand Up @@ -77,6 +72,20 @@ static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint3
}
}

bool fsp_is_multi_phase_init_enabled(void)
{
return CONFIG(FSPS_USE_MULTI_PHASE_INIT) &&
(fsps_hdr.multi_phase_si_init_entry_offset != 0);
}

static void fsp_fill_common_arch_params(FSPS_UPD *supd)
{
#if CONFIG(FSPS_HAS_ARCH_UPD)
FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
#endif
}

static void do_silicon_init(struct fsp_header *hdr)
{
FSPS_UPD *upd, *supd;
Expand Down Expand Up @@ -106,6 +115,9 @@ static void do_silicon_init(struct fsp_header *hdr)

memcpy(upd, supd, hdr->cfg_region_size);

/* Fill common settings on behalf of chipset. */
if (CONFIG(FSPS_HAS_ARCH_UPD))
fsp_fill_common_arch_params(upd);
/* Give SoC/mainboard a chance to populate entries */
platform_fsp_silicon_init_params_cb(upd);

Expand Down Expand Up @@ -145,7 +157,7 @@ static void do_silicon_init(struct fsp_header *hdr)
return;

/* Check if SoC user would like to call Multi Phase Init */
if (!soc_fsp_multi_phase_init_is_enable())
if (!fsp_is_multi_phase_init_enabled())
return;

/* Call MultiPhaseSiInit */
Expand All @@ -166,8 +178,8 @@ static void do_silicon_init(struct fsp_header *hdr)
fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status);

/* Execute Multi Phase Execution */
for (int i = 1; i <= multi_phase_get_number.number_of_phases; i++) {
printk(BIOS_SPEW, "Executing Phase %d of FspMultiPhaseSiInit\n", i);
for (uint32_t i = 1; i <= multi_phase_get_number.number_of_phases; i++) {
printk(BIOS_SPEW, "Executing Phase %u of FspMultiPhaseSiInit\n", i);
/*
* Give SoC/mainboard a chance to perform any operation before
* Multi Phase Execution
Expand Down
13 changes: 3 additions & 10 deletions src/drivers/intel/pmc_mux/conn/chip.h
View file
Expand Up @@ -3,24 +3,17 @@
#ifndef __DRIVERS_INTEL_PMC_MUX_CONN_H__
#define __DRIVERS_INTEL_PMC_MUX_CONN_H__

enum typec_orientation {
/* The orientation of the signal follows the orientation of the CC lines. */
TYPEC_ORIENTATION_FOLLOW_CC = 0,
/* The orientation of the signal is fixed to follow CC1 */
TYPEC_ORIENTATION_NORMAL,
/* The orientation of the signal is fixed to follow CC2 */
TYPEC_ORIENTATION_REVERSE,
};
#include <boot/coreboot_tables.h>

struct drivers_intel_pmc_mux_conn_config {
/* 1-based port numbers (from SoC point of view) */
int usb2_port_number;
/* 1-based port numbers (from SoC point of view) */
int usb3_port_number;
/* Orientation of the sideband signals (SBU) */
enum typec_orientation sbu_orientation;
enum type_c_orientation sbu_orientation;
/* Orientation of the High Speed lines */
enum typec_orientation hsl_orientation;
enum type_c_orientation hsl_orientation;
};

/*
Expand Down
74 changes: 70 additions & 4 deletions src/drivers/intel/pmc_mux/conn/conn.c
View file
@@ -1,25 +1,89 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <acpi/acpigen.h>
#include <boot/coreboot_tables.h>
#include <cbmem.h>
#include <console/console.h>
#include <intelblocks/acpi.h>

#include "chip.h"

/* Number of registered connectors */
static size_t total_conn_count;

static void conn_init(struct device *dev)
{
total_conn_count++;
}

static struct type_c_info *conn_get_cbmem_buffer(void)
{
struct type_c_info *info;
size_t size;

info = cbmem_find(CBMEM_ID_TYPE_C_INFO);
if (info)
return info;

size = sizeof(struct type_c_info) + total_conn_count * sizeof(struct type_c_port_info);
info = cbmem_add(CBMEM_ID_TYPE_C_INFO, size);

if (!info)
return NULL;

memset(info, 0, size);
return info;
}

static void conn_write_cbmem_entry(struct device *dev)
{
const struct drivers_intel_pmc_mux_conn_config *config = dev->chip_info;
struct type_c_port_info *port_info;
struct type_c_info *info;
size_t count;

/*
* Do not re-run this code on resume as the cbmem data is populated on boot-up
* (non-S3 path) and stays intact across S3 suspend/resume.
*/
if (acpi_is_wakeup_s3())
return;

info = conn_get_cbmem_buffer();
if (!info || (info->port_count >= total_conn_count)) {
printk(BIOS_ERR, "ERROR: No space for Type-C port info!\n");
return;
}

count = info->port_count;
port_info = &info->port_info[count];
port_info->usb2_port_number = config->usb2_port_number;
port_info->usb3_port_number = config->usb3_port_number;
port_info->sbu_orientation = config->sbu_orientation;
port_info->data_orientation = config->hsl_orientation;

printk(BIOS_INFO, "added type-c port%ld info to cbmem: usb2:%d usb3:%d sbu:%d data:%d\n",
count, port_info->usb2_port_number, port_info->usb3_port_number,
port_info->sbu_orientation, port_info->data_orientation);

info->port_count++;
}

static const char *conn_acpi_name(const struct device *dev)
{
static char name[5];
snprintf(name, sizeof(name), "CON%1X", dev->path.generic.id);
return name;
}

static const char *orientation_to_str(enum typec_orientation ori)
static const char *orientation_to_str(enum type_c_orientation ori)
{
switch (ori) {
case TYPEC_ORIENTATION_NORMAL:
return "normal";
case TYPEC_ORIENTATION_REVERSE:
return "reverse";
case TYPEC_ORIENTATION_FOLLOW_CC: /* Intentional fallthrough */
case TYPEC_ORIENTATION_NONE: /* Intentional fallthrough */
default:
return "";
}
Expand Down Expand Up @@ -52,11 +116,11 @@ static void conn_fill_ssdt(const struct device *dev)
* The kernel assumes that these Type-C signals (SBUs and HSLs) follow the CC lines,
* unless they are explicitly called out otherwise.
*/
if (config->sbu_orientation != TYPEC_ORIENTATION_FOLLOW_CC)
if (config->sbu_orientation != TYPEC_ORIENTATION_NONE)
acpi_dp_add_string(dsd, "sbu-orientation",
orientation_to_str(config->sbu_orientation));

if (config->hsl_orientation != TYPEC_ORIENTATION_FOLLOW_CC)
if (config->hsl_orientation != TYPEC_ORIENTATION_NONE)
acpi_dp_add_string(dsd, "hsl-orientation",
orientation_to_str(config->hsl_orientation));

Expand All @@ -74,6 +138,8 @@ static struct device_operations conn_dev_ops = {
.set_resources = noop_set_resources,
.acpi_name = conn_acpi_name,
.acpi_fill_ssdt = conn_fill_ssdt,
.init = conn_init,
.final = conn_write_cbmem_entry,
};

static void conn_enable(struct device *dev)
Expand Down
2 changes: 2 additions & 0 deletions src/drivers/ipmi/ipmi_kcs_ops.c
View file
Expand Up @@ -386,6 +386,8 @@ static int ipmi_smbios_data(struct device *dev, int *handle,
register_spacing,
0); // no IRQ

len += get_smbios_data(dev, handle, current);

return len;
}
#endif
Expand Down
2 changes: 2 additions & 0 deletions src/drivers/ipmi/ocp/ipmi_ocp.h
View file
Expand Up @@ -3,6 +3,8 @@
#ifndef __IPMI_OCP_H
#define __IPMI_OCP_H

#include <commonlib/bsd/cb_err.h>

#define IPMI_NETFN_OEM 0x30
#define IPMI_OEM_SET_PPIN 0x77
#define IPMI_BMC_SET_POST_START 0x73
Expand Down
6 changes: 6 additions & 0 deletions src/drivers/mipi/Kconfig
View file
Expand Up @@ -27,12 +27,18 @@ config MIPI_PANEL_BOE_TV101WUM_NL6
config MIPI_PANEL_BOE_TV105WUM_NW0
bool

config MIPI_PANEL_BOE_TV110C9M_LL0
bool

config MIPI_PANEL_CMN_P097PFG_SSD2858
bool

config MIPI_PANEL_INX_OTA7290D10P
bool

config MIPI_PANEL_INX_P110ZZD_DF0
bool

config MIPI_PANEL_STA_2081101QFH032011_53G
bool

Expand Down
2 changes: 2 additions & 0 deletions src/drivers/mipi/Makefile.inc
View file
Expand Up @@ -13,10 +13,12 @@ panel-params-$(CONFIG_MIPI_PANEL_BOE_TV101WUM_N53) += panel-BOE_TV101WUM_N53
panel-params-$(CONFIG_MIPI_PANEL_BOE_TV101WUM_NG0) += panel-BOE_TV101WUM_NG0
panel-params-$(CONFIG_MIPI_PANEL_BOE_TV101WUM_NL6) += panel-BOE_TV101WUM_NL6
panel-params-$(CONFIG_MIPI_PANEL_BOE_TV105WUM_NW0) += panel-BOE_TV105WUM_NW0
panel-params-$(CONFIG_MIPI_PANEL_BOE_TV110C9M_LL0) += panel-BOE_TV110C9M_LL0

panel-params-$(CONFIG_MIPI_PANEL_CMN_P097PFG_SSD2858) += panel-CMN_P097PFG_SSD2858

panel-params-$(CONFIG_MIPI_PANEL_INX_OTA7290D10P) += panel-INX_OTA7290D10P
panel-params-$(CONFIG_MIPI_PANEL_INX_P110ZZD_DF0) += panel-INX_P110ZZD_DF0

panel-params-$(CONFIG_MIPI_PANEL_STA_2081101QFH032011_53G) += panel-STA_2081101QFH032011_53G

Expand Down
343 changes: 343 additions & 0 deletions src/drivers/mipi/panel-BOE_TV110C9M_LL0.c
View file
@@ -0,0 +1,343 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mipi/panel.h>

struct panel_serializable_data BOE_TV110C9M_LL0 = {
.edid = {
.ascii_string = "TV110C9M-LL0",
.manufacturer_name = "BOE",
.panel_bits_per_color = 8,
.panel_bits_per_pixel = 24,
.mode = {
.pixel_clock = 166594,
.lvds_dual_channel = 0,
.refresh = 60,
.ha = 1200, .hbl = 76, .hso = 40, .hspw = 8,
.va = 2000, .vbl = 176, .vso = 26, .vspw = 2,
.phsync = '-', .pvsync = '-',
.x_mm = 143, .y_mm = 238,
},
},
.init = {
PANEL_DCS(0xFF, 0x20),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x05, 0xD9),
PANEL_DCS(0x07, 0x78),
PANEL_DCS(0x08, 0x5A),
PANEL_DCS(0x0D, 0x63),
PANEL_DCS(0x0E, 0x91),
PANEL_DCS(0x0F, 0x73),
PANEL_DCS(0x95, 0xEB),
PANEL_DCS(0x96, 0xEB),
PANEL_DCS(0x30, 0x11),
PANEL_DCS(0x6D, 0x66),
PANEL_DCS(0x75, 0xA2),
PANEL_DCS(0x77, 0x3B),
PANEL_DCS(0xB0, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00,
0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9),
PANEL_DCS(0xB1, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01,
0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31),
PANEL_DCS(0xB2, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03,
0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B),
PANEL_DCS(0xB3, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03,
0xFD, 0x03, 0xFF),
PANEL_DCS(0xB4, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00,
0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9),
PANEL_DCS(0xB5, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01,
0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31),
PANEL_DCS(0xB6, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03,
0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B),
PANEL_DCS(0xB7, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03,
0xFD, 0x03, 0xFF),
PANEL_DCS(0xB8, 0x00, 0x08, 0x00, 0x23, 0x00, 0x4D, 0x00, 0x6D, 0x00,
0x89, 0x00, 0xA1, 0x00, 0xB6, 0x00, 0xC9),
PANEL_DCS(0xB9, 0x00, 0xDA, 0x01, 0x13, 0x01, 0x3C, 0x01, 0x7E, 0x01,
0xAB, 0x01, 0xF7, 0x02, 0x2F, 0x02, 0x31),
PANEL_DCS(0xBA, 0x02, 0x67, 0x02, 0xA6, 0x02, 0xD1, 0x03, 0x08, 0x03,
0x2E, 0x03, 0x5B, 0x03, 0x6B, 0x03, 0x7B),
PANEL_DCS(0xBB, 0x03, 0x8E, 0x03, 0xA2, 0x03, 0xB7, 0x03, 0xE7, 0x03,
0xFD, 0x03, 0xFF),
PANEL_DCS(0xFF, 0x21),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0xB0, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00,
0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1),
PANEL_DCS(0xB1, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01,
0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29),
PANEL_DCS(0xB2, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03,
0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73),
PANEL_DCS(0xB3, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03,
0xF5, 0x03, 0xF7),
PANEL_DCS(0xB4, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00,
0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1),
PANEL_DCS(0xB5, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01,
0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29),
PANEL_DCS(0xB6, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03,
0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73),
PANEL_DCS(0xB7, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03,
0xF5, 0x03, 0xF7),
PANEL_DCS(0xB8, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x45, 0x00, 0x65, 0x00,
0x81, 0x00, 0x99, 0x00, 0xAE, 0x00, 0xC1),
PANEL_DCS(0xB9, 0x00, 0xD2, 0x01, 0x0B, 0x01, 0x34, 0x01, 0x76, 0x01,
0xA3, 0x01, 0xEF, 0x02, 0x27, 0x02, 0x29),
PANEL_DCS(0xBA, 0x02, 0x5F, 0x02, 0x9E, 0x02, 0xC9, 0x03, 0x00, 0x03,
0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73),
PANEL_DCS(0xBB, 0x03, 0x86, 0x03, 0x9A, 0x03, 0xAF, 0x03, 0xDF, 0x03,
0xF5, 0x03, 0xF7),
PANEL_DCS(0xFF, 0x24),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x00, 0x00),
PANEL_DCS(0x01, 0x00),
PANEL_DCS(0x02, 0x1C),
PANEL_DCS(0x03, 0x1C),
PANEL_DCS(0x04, 0x1D),
PANEL_DCS(0x05, 0x1D),
PANEL_DCS(0x06, 0x04),
PANEL_DCS(0x07, 0x04),
PANEL_DCS(0x08, 0x0F),
PANEL_DCS(0x09, 0x0F),
PANEL_DCS(0x0A, 0x0E),
PANEL_DCS(0x0B, 0x0E),
PANEL_DCS(0x0C, 0x0D),
PANEL_DCS(0x0D, 0x0D),
PANEL_DCS(0x0E, 0x0C),
PANEL_DCS(0x0F, 0x0C),
PANEL_DCS(0x10, 0x08),
PANEL_DCS(0x11, 0x08),
PANEL_DCS(0x12, 0x00),
PANEL_DCS(0x13, 0x00),
PANEL_DCS(0x14, 0x00),
PANEL_DCS(0x15, 0x00),
PANEL_DCS(0x16, 0x00),
PANEL_DCS(0x17, 0x00),
PANEL_DCS(0x18, 0x1C),
PANEL_DCS(0x19, 0x1C),
PANEL_DCS(0x1A, 0x1D),
PANEL_DCS(0x1B, 0x1D),
PANEL_DCS(0x1C, 0x04),
PANEL_DCS(0x1D, 0x04),
PANEL_DCS(0x1E, 0x0F),
PANEL_DCS(0x1F, 0x0F),
PANEL_DCS(0x20, 0x0E),
PANEL_DCS(0x21, 0x0E),
PANEL_DCS(0x22, 0x0D),
PANEL_DCS(0x23, 0x0D),
PANEL_DCS(0x24, 0x0C),
PANEL_DCS(0x25, 0x0C),
PANEL_DCS(0x26, 0x08),
PANEL_DCS(0x27, 0x08),
PANEL_DCS(0x28, 0x00),
PANEL_DCS(0x29, 0x00),
PANEL_DCS(0x2A, 0x00),
PANEL_DCS(0x2B, 0x00),
PANEL_DCS(0x2D, 0x20),
PANEL_DCS(0x2F, 0x0A),
PANEL_DCS(0x30, 0x44),
PANEL_DCS(0x33, 0x0C),
PANEL_DCS(0x34, 0x32),
PANEL_DCS(0x37, 0x44),
PANEL_DCS(0x38, 0x40),
PANEL_DCS(0x39, 0x00),
PANEL_DCS(0x3A, 0x5D),
PANEL_DCS(0x3B, 0x60),
PANEL_DCS(0x3D, 0x42),
PANEL_DCS(0x3F, 0x06),
PANEL_DCS(0x43, 0x06),
PANEL_DCS(0x47, 0x66),
PANEL_DCS(0x4A, 0x5D),
PANEL_DCS(0x4B, 0x60),
PANEL_DCS(0x4C, 0x91),
PANEL_DCS(0x4D, 0x21),
PANEL_DCS(0x4E, 0x43),
PANEL_DCS(0x51, 0x12),
PANEL_DCS(0x52, 0x34),
PANEL_DCS(0x55, 0x82, 0x02),
PANEL_DCS(0x56, 0x04),
PANEL_DCS(0x58, 0x21),
PANEL_DCS(0x59, 0x30),
PANEL_DCS(0x5A, 0x60),
PANEL_DCS(0x5B, 0x50),
PANEL_DCS(0x5E, 0x00, 0x06),
PANEL_DCS(0x5F, 0x00),
PANEL_DCS(0x65, 0x82),
PANEL_DCS(0x7E, 0x20),
PANEL_DCS(0x7F, 0x3C),
PANEL_DCS(0x82, 0x04),
PANEL_DCS(0x97, 0xC0),
PANEL_DCS(0xB6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
0x05, 0x00, 0x00),
PANEL_DCS(0x91, 0x44),
PANEL_DCS(0x92, 0xA9),
PANEL_DCS(0x93, 0x1A),
PANEL_DCS(0x94, 0x96),
PANEL_DCS(0xD7, 0x55),
PANEL_DCS(0xDA, 0x0A),
PANEL_DCS(0xDE, 0x08),
PANEL_DCS(0xDB, 0x05),
PANEL_DCS(0xDC, 0xA9),
PANEL_DCS(0xDD, 0x22),
PANEL_DCS(0xDF, 0x05),
PANEL_DCS(0xE0, 0xA9),
PANEL_DCS(0xE1, 0x05),
PANEL_DCS(0xE2, 0xA9),
PANEL_DCS(0xE3, 0x05),
PANEL_DCS(0xE4, 0xA9),
PANEL_DCS(0xE5, 0x05),
PANEL_DCS(0xE6, 0xA9),
PANEL_DCS(0x5C, 0x00),
PANEL_DCS(0x5D, 0x00),
PANEL_DCS(0x8D, 0x00),
PANEL_DCS(0x8E, 0x00),
PANEL_DCS(0xB5, 0x90),
PANEL_DCS(0xFF, 0x25),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x05, 0x00),
PANEL_DCS(0x19, 0x07),
PANEL_DCS(0x1F, 0x60),
PANEL_DCS(0x20, 0x50),
PANEL_DCS(0x26, 0x60),
PANEL_DCS(0x27, 0x50),
PANEL_DCS(0x33, 0x60),
PANEL_DCS(0x34, 0x50),
PANEL_DCS(0x3F, 0xE0),
PANEL_DCS(0x40, 0x00),
PANEL_DCS(0x44, 0x00),
PANEL_DCS(0x45, 0x40),
PANEL_DCS(0x48, 0x60),
PANEL_DCS(0x49, 0x50),
PANEL_DCS(0x5B, 0x00),
PANEL_DCS(0x5C, 0x00),
PANEL_DCS(0x5D, 0x00),
PANEL_DCS(0x5E, 0xD0),
PANEL_DCS(0x61, 0x60),
PANEL_DCS(0x62, 0x50),
PANEL_DCS(0xF1, 0x10),
PANEL_DCS(0xFF, 0x2A),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x64, 0x16),
PANEL_DCS(0x67, 0x16),
PANEL_DCS(0x6A, 0x16),
PANEL_DCS(0x70, 0x30),
PANEL_DCS(0xA2, 0xF3),
PANEL_DCS(0xA3, 0xFF),
PANEL_DCS(0xA4, 0xFF),
PANEL_DCS(0xA5, 0xFF),
PANEL_DCS(0xD6, 0x08),
PANEL_DCS(0xFF, 0x26),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x00, 0xA1),
PANEL_DCS(0x02, 0x31),
PANEL_DCS(0x04, 0x28),
PANEL_DCS(0x06, 0x30),
PANEL_DCS(0x0C, 0x16),
PANEL_DCS(0x0D, 0x0D),
PANEL_DCS(0x0F, 0x00),
PANEL_DCS(0x11, 0x00),
PANEL_DCS(0x12, 0x50),
PANEL_DCS(0x13, 0x56),
PANEL_DCS(0x14, 0x57),
PANEL_DCS(0x15, 0x00),
PANEL_DCS(0x16, 0x10),
PANEL_DCS(0x17, 0xA0),
PANEL_DCS(0x18, 0x86),
PANEL_DCS(0x19, 0x0D),
PANEL_DCS(0x1A, 0x7F),
PANEL_DCS(0x1B, 0x0C),
PANEL_DCS(0x1C, 0xBF),
PANEL_DCS(0x22, 0x00),
PANEL_DCS(0x23, 0x00),
PANEL_DCS(0x2A, 0x0D),
PANEL_DCS(0x2B, 0x7F),
PANEL_DCS(0x1D, 0x00),
PANEL_DCS(0x1E, 0x65),
PANEL_DCS(0x1F, 0x65),
PANEL_DCS(0x24, 0x00),
PANEL_DCS(0x25, 0x65),
PANEL_DCS(0x2F, 0x05),
PANEL_DCS(0x30, 0x65),
PANEL_DCS(0x31, 0x05),
PANEL_DCS(0x32, 0x7D),
PANEL_DCS(0x39, 0x00),
PANEL_DCS(0x3A, 0x65),
PANEL_DCS(0x20, 0x01),
PANEL_DCS(0x33, 0x11),
PANEL_DCS(0x34, 0x78),
PANEL_DCS(0x35, 0x16),
PANEL_DCS(0xC8, 0x04),
PANEL_DCS(0xC9, 0x80),
PANEL_DCS(0xCA, 0x4E),
PANEL_DCS(0xCB, 0x00),
PANEL_DCS(0xA9, 0x4C),
PANEL_DCS(0xAA, 0x47),
PANEL_DCS(0xFF, 0x27),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x56, 0x06),
PANEL_DCS(0x58, 0x80),
PANEL_DCS(0x59, 0x75),
PANEL_DCS(0x5A, 0x00),
PANEL_DCS(0x5B, 0x02),
PANEL_DCS(0x5C, 0x00),
PANEL_DCS(0x5D, 0x00),
PANEL_DCS(0x5E, 0x20),
PANEL_DCS(0x5F, 0x10),
PANEL_DCS(0x60, 0x00),
PANEL_DCS(0x61, 0x2E),
PANEL_DCS(0x62, 0x00),
PANEL_DCS(0x63, 0x01),
PANEL_DCS(0x64, 0x43),
PANEL_DCS(0x65, 0x2D),
PANEL_DCS(0x66, 0x00),
PANEL_DCS(0x67, 0x01),
PANEL_DCS(0x68, 0x44),
PANEL_DCS(0x00, 0x00),
PANEL_DCS(0x78, 0x00),
PANEL_DCS(0xC3, 0x00),
PANEL_DCS(0xFF, 0x2A),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x22, 0x2F),
PANEL_DCS(0x23, 0x08),
PANEL_DCS(0x24, 0x00),
PANEL_DCS(0x25, 0x65),
PANEL_DCS(0x26, 0xF8),
PANEL_DCS(0x27, 0x00),
PANEL_DCS(0x28, 0x1A),
PANEL_DCS(0x29, 0x00),
PANEL_DCS(0x2A, 0x1A),
PANEL_DCS(0x2B, 0x00),
PANEL_DCS(0x2D, 0x1A),
PANEL_DCS(0xFF, 0x23),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x00, 0x80),
PANEL_DCS(0x07, 0x00),
PANEL_DCS(0xFF, 0x24),
PANEL_DCS(0xC2, 0x06),
PANEL_DCS(0xFF, 0x10),
PANEL_DCS(0xFF, 0xE0),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x14, 0x60),
PANEL_DCS(0x16, 0xC0),
PANEL_DCS(0xFF, 0xF0),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x3A, 0x08),
PANEL_DCS(0xFF, 0x10),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0xB9, 0x01),
PANEL_DCS(0xFF, 0x20),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x18, 0x40),
PANEL_DCS(0xFF, 0x10),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0xB9, 0x02),
PANEL_DCS(0x35, 0x00),
PANEL_DCS(0x51, 0x00, 0xFF),
PANEL_DCS(0x53, 0x24),
PANEL_DCS(0x55, 0x00),
PANEL_DCS(0xBB, 0x13),
PANEL_DCS(0x3B, 0x03, 0x96, 0x1A, 0x04, 0x04),
PANEL_DELAY(100),
PANEL_DCS(0x11),
PANEL_DELAY(200),
PANEL_DCS(0x29),
PANEL_DELAY(100),
PANEL_END,
},
};
322 changes: 322 additions & 0 deletions src/drivers/mipi/panel-INX_P110ZZD_DF0.c
View file
@@ -0,0 +1,322 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mipi/panel.h>

struct panel_serializable_data INX_P110ZZD_DF0 = {
.edid = {
.ascii_string = "P110ZZD-DF0",
.manufacturer_name = "INX",
.panel_bits_per_color = 8,
.panel_bits_per_pixel = 24,
.mode = {
.pixel_clock = 166594,
.lvds_dual_channel = 0,
.refresh = 60,
.ha = 1200, .hbl = 76, .hso = 40, .hspw = 8,
.va = 2000, .vbl = 176, .vso = 26, .vspw = 1,
.phsync = '-', .pvsync = '-',
.x_mm = 143, .y_mm = 238,
},
},
.init = {
PANEL_DCS(0xFF, 0x20),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x05, 0xD1),
PANEL_DCS(0x0D, 0x63),
PANEL_DCS(0x07, 0x8C),
PANEL_DCS(0x08, 0x4B),
PANEL_DCS(0x0E, 0x91),
PANEL_DCS(0x0F, 0x69),
PANEL_DCS(0x95, 0xFF),
PANEL_DCS(0x96, 0xFF),
PANEL_DCS(0x9D, 0x0A),
PANEL_DCS(0x9E, 0x0A),
PANEL_DCS(0x69, 0x98),
PANEL_DCS(0x75, 0xA2),
PANEL_DCS(0x77, 0xB3),
PANEL_DCS(0xFF, 0x24),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x91, 0x44),
PANEL_DCS(0x92, 0x7A),
PANEL_DCS(0x93, 0x1A),
PANEL_DCS(0x94, 0x40),
PANEL_DCS(0x9A, 0x08),
PANEL_DCS(0x60, 0x96),
PANEL_DCS(0x61, 0xD0),
PANEL_DCS(0x63, 0x70),
PANEL_DCS(0xC2, 0xCF),
PANEL_DCS(0x9B, 0x0F),
PANEL_DCS(0x9A, 0x08),
PANEL_DCS(0x00, 0x03),
PANEL_DCS(0x01, 0x03),
PANEL_DCS(0x02, 0x03),
PANEL_DCS(0x03, 0x03),
PANEL_DCS(0x04, 0x03),
PANEL_DCS(0x05, 0x03),
PANEL_DCS(0x06, 0x22),
PANEL_DCS(0x07, 0x06),
PANEL_DCS(0x08, 0x00),
PANEL_DCS(0x09, 0x1D),
PANEL_DCS(0x0A, 0x1C),
PANEL_DCS(0x0B, 0x13),
PANEL_DCS(0x0C, 0x12),
PANEL_DCS(0x0D, 0x11),
PANEL_DCS(0x0E, 0x10),
PANEL_DCS(0x0F, 0x0F),
PANEL_DCS(0x10, 0x0E),
PANEL_DCS(0x11, 0x0D),
PANEL_DCS(0x12, 0x0C),
PANEL_DCS(0x13, 0x04),
PANEL_DCS(0x14, 0x03),
PANEL_DCS(0x15, 0x03),
PANEL_DCS(0x16, 0x03),
PANEL_DCS(0x17, 0x03),
PANEL_DCS(0x18, 0x03),
PANEL_DCS(0x19, 0x03),
PANEL_DCS(0x1A, 0x03),
PANEL_DCS(0x1B, 0x03),
PANEL_DCS(0x1C, 0x22),
PANEL_DCS(0x1D, 0x06),
PANEL_DCS(0x1E, 0x00),
PANEL_DCS(0x1F, 0x1D),
PANEL_DCS(0x20, 0x1C),
PANEL_DCS(0x21, 0x13),
PANEL_DCS(0x22, 0x12),
PANEL_DCS(0x23, 0x11),
PANEL_DCS(0x24, 0x10),
PANEL_DCS(0x25, 0x0F),
PANEL_DCS(0x26, 0x0E),
PANEL_DCS(0x27, 0x0D),
PANEL_DCS(0x28, 0x0C),
PANEL_DCS(0x29, 0x04),
PANEL_DCS(0x2A, 0x03),
PANEL_DCS(0x2B, 0x03),
PANEL_DCS(0x2F, 0x06),
PANEL_DCS(0x30, 0x32),
PANEL_DCS(0x31, 0x43),
PANEL_DCS(0x33, 0x06),
PANEL_DCS(0x34, 0x32),
PANEL_DCS(0x35, 0x43),
PANEL_DCS(0x37, 0x44),
PANEL_DCS(0x38, 0x40),
PANEL_DCS(0x39, 0x00),
PANEL_DCS(0x3A, 0x01),
PANEL_DCS(0x3B, 0x48),
PANEL_DCS(0x3D, 0x93),
PANEL_DCS(0xAB, 0x44),
PANEL_DCS(0xAC, 0x40),
PANEL_DCS(0x4D, 0x21),
PANEL_DCS(0x4E, 0x43),
PANEL_DCS(0x4F, 0x65),
PANEL_DCS(0x50, 0x87),
PANEL_DCS(0x51, 0x78),
PANEL_DCS(0x52, 0x56),
PANEL_DCS(0x53, 0x34),
PANEL_DCS(0x54, 0x21),
PANEL_DCS(0x55, 0x83),
PANEL_DCS(0x56, 0x08),
PANEL_DCS(0x58, 0x21),
PANEL_DCS(0x59, 0x40),
PANEL_DCS(0x5A, 0x09),
PANEL_DCS(0x5B, 0x48),
PANEL_DCS(0x5E, 0x00, 0x10),
PANEL_DCS(0x5F, 0x00),
PANEL_DCS(0x7A, 0x00),
PANEL_DCS(0x7B, 0x00),
PANEL_DCS(0x7C, 0x00),
PANEL_DCS(0x7D, 0x00),
PANEL_DCS(0x7E, 0x20),
PANEL_DCS(0x7F, 0x3C),
PANEL_DCS(0x80, 0x00),
PANEL_DCS(0x81, 0x00),
PANEL_DCS(0x82, 0x08),
PANEL_DCS(0x97, 0x02),
PANEL_DCS(0xC5, 0x10),
PANEL_DCS(0xDA, 0x05),
PANEL_DCS(0xDB, 0x01),
PANEL_DCS(0xDC, 0x7A),
PANEL_DCS(0xDD, 0x55),
PANEL_DCS(0xDE, 0x27),
PANEL_DCS(0xDF, 0x01),
PANEL_DCS(0xE0, 0x7A),
PANEL_DCS(0xE1, 0x01),
PANEL_DCS(0xE2, 0x7A),
PANEL_DCS(0xE3, 0x01),
PANEL_DCS(0xE4, 0x7A),
PANEL_DCS(0xE5, 0x01),
PANEL_DCS(0xE6, 0x7A),
PANEL_DCS(0xE7, 0x00),
PANEL_DCS(0xE8, 0x00),
PANEL_DCS(0xE9, 0x01),
PANEL_DCS(0xEA, 0x7A),
PANEL_DCS(0xEB, 0x01),
PANEL_DCS(0xEE, 0x7A),
PANEL_DCS(0xEF, 0x01),
PANEL_DCS(0xF0, 0x7A),
PANEL_DCS(0xFF, 0x25),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x05, 0x00),
PANEL_DCS(0xF1, 0x10),
PANEL_DCS(0x1E, 0x00),
PANEL_DCS(0x1F, 0x09),
PANEL_DCS(0x20, 0x46),
PANEL_DCS(0x25, 0x00),
PANEL_DCS(0x26, 0x09),
PANEL_DCS(0x27, 0x46),
PANEL_DCS(0x3F, 0x80),
PANEL_DCS(0x40, 0x00),
PANEL_DCS(0x43, 0x00),
PANEL_DCS(0x44, 0x09),
PANEL_DCS(0x45, 0x46),
PANEL_DCS(0x48, 0x09),
PANEL_DCS(0x49, 0x46),
PANEL_DCS(0x5B, 0x80),
PANEL_DCS(0x5C, 0x00),
PANEL_DCS(0x5D, 0x01),
PANEL_DCS(0x5E, 0x46),
PANEL_DCS(0x61, 0x01),
PANEL_DCS(0x62, 0x46),
PANEL_DCS(0x68, 0x10),
PANEL_DCS(0xFF, 0x26),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x00, 0xA1),
PANEL_DCS(0x02, 0x31),
PANEL_DCS(0x0A, 0xF2),
PANEL_DCS(0x04, 0x28),
PANEL_DCS(0x06, 0x30),
PANEL_DCS(0x0C, 0x16),
PANEL_DCS(0x0D, 0x0D),
PANEL_DCS(0x0F, 0x00),
PANEL_DCS(0x11, 0x00),
PANEL_DCS(0x12, 0x50),
PANEL_DCS(0x13, 0x56),
PANEL_DCS(0x14, 0x57),
PANEL_DCS(0x15, 0x00),
PANEL_DCS(0x16, 0x10),
PANEL_DCS(0x17, 0xA0),
PANEL_DCS(0x18, 0x86),
PANEL_DCS(0x22, 0x00),
PANEL_DCS(0x23, 0x00),
PANEL_DCS(0x19, 0x0D),
PANEL_DCS(0x1A, 0x7F),
PANEL_DCS(0x1B, 0x0C),
PANEL_DCS(0x1C, 0xBF),
PANEL_DCS(0x2A, 0x0D),
PANEL_DCS(0x2B, 0x7F),
PANEL_DCS(0x20, 0x00),
PANEL_DCS(0x1D, 0x00),
PANEL_DCS(0x1E, 0x78),
PANEL_DCS(0x1F, 0x78),
PANEL_DCS(0x2F, 0x03),
PANEL_DCS(0x30, 0x78),
PANEL_DCS(0x33, 0x78),
PANEL_DCS(0x34, 0x66),
PANEL_DCS(0x35, 0x11),
PANEL_DCS(0x39, 0x10),
PANEL_DCS(0x3A, 0x78),
PANEL_DCS(0x3B, 0x06),
PANEL_DCS(0xC8, 0x04),
PANEL_DCS(0xC9, 0x84),
PANEL_DCS(0xCA, 0x4E),
PANEL_DCS(0xCB, 0x00),
PANEL_DCS(0xA9, 0x50),
PANEL_DCS(0xAA, 0x4F),
PANEL_DCS(0xAB, 0x4D),
PANEL_DCS(0xAC, 0x4A),
PANEL_DCS(0xAD, 0x48),
PANEL_DCS(0xAE, 0x46),
PANEL_DCS(0xFF, 0x27),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0xC0, 0x18),
PANEL_DCS(0xC1, 0x00),
PANEL_DCS(0xC2, 0x00),
PANEL_DCS(0x56, 0x06),
PANEL_DCS(0x58, 0x80),
PANEL_DCS(0x59, 0x75),
PANEL_DCS(0x5A, 0x00),
PANEL_DCS(0x5B, 0x02),
PANEL_DCS(0x5C, 0x00),
PANEL_DCS(0x5D, 0x00),
PANEL_DCS(0x5E, 0x20),
PANEL_DCS(0x5F, 0x10),
PANEL_DCS(0x60, 0x00),
PANEL_DCS(0x61, 0x2E),
PANEL_DCS(0x62, 0x00),
PANEL_DCS(0x63, 0x01),
PANEL_DCS(0x64, 0x43),
PANEL_DCS(0x65, 0x2D),
PANEL_DCS(0x66, 0x00),
PANEL_DCS(0x67, 0x01),
PANEL_DCS(0x68, 0x43),
PANEL_DCS(0x98, 0x01),
PANEL_DCS(0xB4, 0x03),
PANEL_DCS(0x9B, 0xBD),
PANEL_DCS(0xA0, 0x90),
PANEL_DCS(0xAB, 0x1B),
PANEL_DCS(0xBC, 0x0C),
PANEL_DCS(0xBD, 0x28),
PANEL_DCS(0xFF, 0x2A),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x22, 0x2F),
PANEL_DCS(0x23, 0x08),
PANEL_DCS(0x24, 0x00),
PANEL_DCS(0x25, 0x65),
PANEL_DCS(0x26, 0xF8),
PANEL_DCS(0x27, 0x00),
PANEL_DCS(0x28, 0x1A),
PANEL_DCS(0x29, 0x00),
PANEL_DCS(0x2A, 0x1A),
PANEL_DCS(0x2B, 0x00),
PANEL_DCS(0x2D, 0x1A),
PANEL_DCS(0x64, 0x96),
PANEL_DCS(0x65, 0x00),
PANEL_DCS(0x66, 0x00),
PANEL_DCS(0x6A, 0x96),
PANEL_DCS(0x6B, 0x00),
PANEL_DCS(0x6C, 0x00),
PANEL_DCS(0x70, 0x92),
PANEL_DCS(0x71, 0x00),
PANEL_DCS(0x72, 0x00),
PANEL_DCS(0xA2, 0x33),
PANEL_DCS(0xA3, 0x30),
PANEL_DCS(0xA4, 0xC0),
PANEL_DCS(0xE8, 0x00),
PANEL_DCS(0xFF, 0xF0),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x3A, 0x08),
PANEL_DCS(0xFF, 0xD0),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x00, 0x33),
PANEL_DCS(0x02, 0x77),
PANEL_DCS(0x08, 0x01),
PANEL_DCS(0x09, 0xBF),
PANEL_DCS(0x28, 0x30),
PANEL_DCS(0x2F, 0x33),
PANEL_DCS(0xFF, 0x23),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x00, 0x80),
PANEL_DCS(0x07, 0x00),
PANEL_DCS(0xFF, 0x20),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0x30, 0x00),
PANEL_DCS(0xFF, 0x10),
PANEL_DCS(0xB9, 0x01),
PANEL_DCS(0xFF, 0x20),
PANEL_DCS(0x18, 0x40),
PANEL_DCS(0xFF, 0x10),
PANEL_DCS(0xB9, 0x02),
PANEL_DCS(0xFF, 0x10),
PANEL_DCS(0xFB, 0x01),
PANEL_DCS(0xBB, 0x13),
PANEL_DCS(0x3B, 0x03, 0x96, 0x1A, 0x04, 0x04),
PANEL_DCS(0x35, 0x00),
PANEL_DCS(0x51, 0x0F, 0xFF),
PANEL_DCS(0x53, 0x24),
PANEL_DELAY(100),
PANEL_DCS(0x11),
PANEL_DELAY(200),
PANEL_DCS(0x29),
PANEL_DELAY(100),
PANEL_END,
},
};
48 changes: 39 additions & 9 deletions src/drivers/mipi/panel.c
View file
Expand Up @@ -7,6 +7,7 @@
cb_err_t mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func)
{
const struct panel_init_command *init = buf;
enum mipi_dsi_transaction type;

/*
* The given commands should be in a buffer containing a packed array of
Expand All @@ -23,25 +24,54 @@ cb_err_t mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_fun

u32 cmd = init->cmd, len = init->len;

switch (cmd) {
case PANEL_CMD_DELAY:
if (cmd == PANEL_CMD_DELAY) {
mdelay(len);
break;
continue;
}

switch (cmd) {
case PANEL_CMD_DCS:
switch (len) {
case 0:
printk(BIOS_ERR, "%s: DCS command length 0?\n", __func__);
return CB_ERR;
case 1:
type = MIPI_DSI_DCS_SHORT_WRITE;
break;
case 2:
type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
break;
default:
type = MIPI_DSI_DCS_LONG_WRITE;
break;
}
break;
case PANEL_CMD_GENERIC:
buf += len;

cb_err_t ret = cmd_func(cmd, init->data, len);
if (ret != CB_SUCCESS)
return ret;
switch (len) {
case 0:
type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
break;
case 1:
type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
break;
case 2:
type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
break;
default:
type = MIPI_DSI_GENERIC_LONG_WRITE;
break;
}
break;

default:
printk(BIOS_ERR, "%s: Unknown command code: %d, "
"abort panel initialization.\n", __func__, cmd);
return CB_ERR;
}

cb_err_t ret = cmd_func(type, init->data, len);
if (ret != CB_SUCCESS)
return ret;
buf += len;
}

return CB_SUCCESS;
Expand Down
4 changes: 3 additions & 1 deletion src/drivers/spi/spi-generic.c
View file
Expand Up @@ -123,8 +123,10 @@ int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
}
}

if (slave->ctrlr == NULL)
if (slave->ctrlr == NULL) {
printk(BIOS_ERR, "Can't find SPI bus %u\n", bus);
return -1;
}

slave->bus = bus;
slave->cs = cs;
Expand Down
6 changes: 3 additions & 3 deletions src/drivers/wifi/generic/acpi.c
View file
Expand Up @@ -450,10 +450,10 @@ static void sar_emit_wtas(struct avg_profile *wtas)
acpigen_write_dword(wtas->revision);
acpigen_write_package(package_size);
acpigen_write_dword(DOMAIN_TYPE_WIFI);
acpigen_write_dword(wtas->tas_selection);
acpigen_write_dword(wtas->tas_list_size);
acpigen_write_byte(wtas->tas_selection);
acpigen_write_byte(wtas->tas_list_size);
for (i = 0; i < MAX_DENYLIST_ENTRY; i++)
acpigen_write_byte(wtas->deny_list_entry[i]);
acpigen_write_word(wtas->deny_list_entry[i]);

acpigen_write_package_end();
acpigen_write_package_end();
Expand Down
10 changes: 6 additions & 4 deletions src/drivers/wifi/generic/smbios.c
View file
Expand Up @@ -9,6 +9,9 @@

static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned long *current)
{
if (dev->vendor != PCI_VENDOR_ID_INTEL)
return 0;

struct smbios_type_intel_wifi {
struct smbios_header header;
u8 str;
Expand All @@ -29,10 +32,9 @@ static int smbios_write_intel_wifi(struct device *dev, int *handle, unsigned lon

int smbios_write_wifi_pcie(struct device *dev, int *handle, unsigned long *current)
{
if (dev->vendor == PCI_VENDOR_ID_INTEL)
return smbios_write_intel_wifi(dev, handle, current);

return 0;
int len = smbios_write_intel_wifi(dev, handle, current);
len += get_smbios_data(dev, handle, current);
return len;
}

int smbios_write_wifi_cnvi(struct device *dev, int *handle, unsigned long *current)
Expand Down
4 changes: 0 additions & 4 deletions src/ec/acpi/ec.c
View file
Expand Up @@ -148,7 +148,3 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg)
ec_cmd_reg = cmd_reg;
ec_data_reg = data_reg;
}

struct chip_operations ec_acpi_ops = {
CHIP_NAME("ACPI Embedded Controller")
};
27 changes: 25 additions & 2 deletions src/ec/google/chromeec/ec_commands.h
View file
Expand Up @@ -1146,7 +1146,7 @@ enum ec_image {
};

/**
* struct ec_response_get_version - Response to the get version command.
* struct ec_response_get_version - Response to the v0 get version command.
* @version_string_ro: Null-terminated RO firmware version string.
* @version_string_rw: Null-terminated RW firmware version string.
* @reserved: Unused bytes; was previously RW-B firmware version string.
Expand All @@ -1155,10 +1155,31 @@ enum ec_image {
struct ec_response_get_version {
char version_string_ro[32];
char version_string_rw[32];
char reserved[32];
char reserved[32]; /* Changed to cros_fwid_ro in version 1 */
uint32_t current_image;
} __ec_align4;

/**
* struct ec_response_get_version_v1 - Response to the v1 get version command.
*
* ec_response_get_version_v1 is a strict superset of ec_response_get_version.
* The v1 response changes the semantics of one field (reserved to cros_fwid_ro)
* and adds one additional field (cros_fwid_rw).
*
* @version_string_ro: Null-terminated RO firmware version string.
* @version_string_rw: Null-terminated RW firmware version string.
* @cros_fwid_ro: Null-terminated RO CrOS FWID string.
* @current_image: One of ec_image.
* @cros_fwid_rw: Null-terminated RW CrOS FWID string.
*/
struct ec_response_get_version_v1 {
char version_string_ro[32];
char version_string_rw[32];
char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */
uint32_t current_image;
char cros_fwid_rw[32]; /* Added in version 1 */
} __ec_align4;

/* Read test */
#define EC_CMD_READ_TEST 0x0003

Expand Down Expand Up @@ -5852,7 +5873,9 @@ struct ec_params_usb_pd_mux_info {
#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */
#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */
#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
Expand Down
4 changes: 2 additions & 2 deletions src/ec/purism/librem-ec/Makefile.inc
View file
@@ -1,6 +1,6 @@
ifeq ($(CONFIG_EC_LIBREM_EC),y)

all-y += librem_ec.c
smm-$(CONFIG_DEBUG_SMI) += librem_ec.c
all-y += ../../system76/ec/system76_ec.c
smm-$(CONFIG_DEBUG_SMI) += ../../system76/ec/system76_ec.c

endif
61 changes: 0 additions & 61 deletions src/ec/purism/librem-ec/librem_ec.c
View file

This file was deleted.

78 changes: 78 additions & 0 deletions src/ec/system76/ec/acpi/battery.asl
View file
Expand Up @@ -96,6 +96,84 @@ Device (BAT0)
Return (PBIF) /* \_SB_.BAT0.PBIF */
}

Name (PBIX, Package ()
{
0, // 0 - Revision
1, // 1 - Power Unit: mAh
0xFFFFFFFF, // 2 - Design Capacity
0xFFFFFFFF, // 3 - Last Full Charge Capacity
1, // 4 - Battery Technology: Rechargeable
0xFFFFFFFF, // 5 - Design Voltage
0, // 6 - Design Capacity of Warning
0, // 7 - Design Capacity of Low
0, // 8 - Cycle Count
98000, // 9 - Measurement Accuracy
0xFFFFFFFF, // 10 - Max Sampling Time
0xFFFFFFFF, // 11 - Min Sampling Time
0xFFFFFFFF, // 12 - Max Averaging Interval
0xFFFFFFFF, // 13 - Min Averaging Interval
0x40, // 14 - Battery Capacity Granularity 1
0x40, // 15 - Battery Capacity Granularity 2
" ", // 16 - Model Number
" ", // 17 - Serial Number
" ", // 18 - Battery Type
" " // 19 - OEM Information
})

Method (IVBX, 0, NotSerialized)
{
PBIX [2] = 0xFFFFFFFF
PBIX [3] = 0xFFFFFFFF
PBIX [5] = 0xFFFFFFFF
PBIX [16] = " "
PBIX [17] = " "
PBIX [18] = " "
PBIX [19] = " "
BFCC = 0
}

Method (UPBX, 0, NotSerialized)
{
If (^^PCI0.LPCB.EC0.BAT0)
{
Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
PBIX [2] = Local0
Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
PBIX [3] = Local0
BFCC = Local0
Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
PBIX [5] = Local0
Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
PBIX [6] = Local0
Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
PBIX [7] = Local0
LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
PBIX [8] = LOCAL0
PBIX [16] = "BAT"
PBIX [17] = "0001"
PBIX [18] = "LION"
PBIX [19] = "Notebook"
}
Else
{
IVBX ()
}
}

// _BIX: Battery Information Extended
Method (_BIX, 0, NotSerialized)
{
If (^^PCI0.LPCB.EC0.ECOK)
{
UPBX ()
}
Else
{
IVBX ()
}
Return (PBIX) /* \_SB_.BAT0.PBIX */
}

Name (PBST, Package (0x04)
{
Zero, // 0 - Battery state
Expand Down
1 change: 1 addition & 0 deletions src/ec/system76/ec/acpi/ec_ram.asl
View file
Expand Up @@ -28,6 +28,7 @@ Field (ERAM, ByteAcc, Lock, Preserve)
Offset (0x3A),
BCW0, 32,
BCL0, 32,
CYC0, 16, // Battery cycle count
Offset (0x68),
ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
Offset (0xC8),
Expand Down
5 changes: 4 additions & 1 deletion src/include/acpi/acpigen.h
View file
Expand Up @@ -441,11 +441,14 @@ void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char
* This function takes as input uuid for the device, set of callbacks and
* argument to pass into the callbacks. Callbacks should ensure that Local0 and
* Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks.
* If the first callback is NULL, then a default implementation of Function 0
* will be autogenerated, returning a package of bits corresponding to the
* function callbacks that are non-NULL.
*/
void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *),
size_t count, void *arg);
void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count);

void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count);
/*
* Generate ACPI AML code for _CPC (Continuous Performance Control).
* Execute the package function once to create a global table, then
Expand Down
1 change: 1 addition & 0 deletions src/include/acpi/acpigen_dptf.h
View file
Expand Up @@ -24,6 +24,7 @@ enum dptf_participant {
DPTF_TEMP_SENSOR_1,
DPTF_TEMP_SENSOR_2,
DPTF_TEMP_SENSOR_3,
DPTF_TPCH,
DPTF_PARTICIPANT_COUNT,
};

Expand Down
1 change: 1 addition & 0 deletions src/include/bootmode.h
View file
Expand Up @@ -11,6 +11,7 @@ int get_recovery_mode_retrain_switch(void);
int clear_recovery_mode_switch(void);
int get_wipeout_mode_switch(void);
int get_lid_switch(void);
int get_ec_is_trusted(void);

/* Return 1 if display initialization is required. 0 if not. */
int display_init_required(void);
Expand Down
3 changes: 1 addition & 2 deletions src/include/console/console.h
View file
Expand Up @@ -3,7 +3,6 @@
#ifndef CONSOLE_CONSOLE_H_
#define CONSOLE_CONSOLE_H_

#include <arch/cpu.h>
#include <commonlib/console/post_codes.h>
#include <console/vtxprintf.h>
#include <stdint.h>
Expand Down Expand Up @@ -48,7 +47,7 @@ static inline int get_console_loglevel(void)
ENV_LIBAGESA || (ENV_SMM && CONFIG(DEBUG_SMI)))

#if __CONSOLE_ENABLE__
asmlinkage void console_init(void);
void console_init(void);
int console_log_level(int msg_level);

int printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
Expand Down
1 change: 1 addition & 0 deletions src/include/cpu/intel/cpu_ids.h
View file
Expand Up @@ -54,5 +54,6 @@
#define CPUID_ALDERLAKE_A0 0x906a0
#define CPUID_ALDERLAKE_A1 0x906a1
#define CPUID_ALDERLAKE_A2 0x906a2
#define CPUID_ALDERLAKE_A3 0x906a4

#endif /* CPU_INTEL_CPU_IDS_H */
23 changes: 8 additions & 15 deletions src/include/device/device.h
View file
Expand Up @@ -175,7 +175,6 @@ void dev_enumerate(void);
void dev_configure(void);
void dev_enable(void);
void dev_initialize(void);
void dev_optimize(void);
void dev_finalize(void);
void dev_finalize_chips(void);
/* Function used to override device state */
Expand Down Expand Up @@ -215,20 +214,6 @@ DEVTREE_CONST struct device *dev_find_path(
enum device_path_type path_type);
struct device *dev_find_lapic(unsigned int apic_id);
int dev_count_cpu(void);

/*
* Signature for matching function that is used by dev_find_matching_device_on_bus() to decide
* if the device being considered is the one that matches the caller's criteria. This function
* is supposed to return true if the provided device matches the criteria, else false.
*/
typedef bool (*match_device_fn)(DEVTREE_CONST struct device *dev);
/*
* Returns the first device on the bus that the match_device_fn returns true for. If no such
* device is found, it returns NULL.
*/
DEVTREE_CONST struct device *dev_find_matching_device_on_bus(const struct bus *bus,
match_device_fn fn);

struct device *add_cpu_device(struct bus *cpu_bus, unsigned int apic_id,
int enabled);
void set_cpu_topology(struct device *cpu, unsigned int node,
Expand Down Expand Up @@ -392,4 +377,12 @@ void scan_smbus(struct device *bus);
void scan_generic_bus(struct device *bus);
void scan_static_bus(struct device *bus);

/* Macro to generate `struct device *` name that points to a device with the given alias. */
#define DEV_PTR(_alias) _dev_##_alias##_ptr

/* Macro to generate weak `struct device *` definition that points to a device with the given
alias. */
#define WEAK_DEV_PTR(_alias) \
__weak DEVTREE_CONST struct device *const DEV_PTR(_alias)

#endif /* DEVICE_H */
4 changes: 2 additions & 2 deletions src/include/device/mmio.h
View file
Expand Up @@ -42,7 +42,7 @@ void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
* bytes of the 'prefix' u32 parameter and any high-order bytes exceeding prefsz
* must be 0. Note that 'size' counts total bytes written, including 'prefsz'.
*/
void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
void buffer_to_fifo32_prefix(const void *buffer, u32 prefix, int prefsz, size_t size,
void *fifo, int fifo_stride, int fifo_width);

/*
Expand All @@ -51,7 +51,7 @@ void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
* registers or 0 to write everything into the same register). fifo_width is
* the amount of bytes written per register (can be 1 through 4).
*/
static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
static inline void buffer_to_fifo32(const void *buffer, size_t size, void *fifo,
int fifo_stride, int fifo_width)
{
buffer_to_fifo32_prefix(buffer, 0, 0, size, fifo,
Expand Down
1 change: 1 addition & 0 deletions src/include/device/pci_ids.h
View file
Expand Up @@ -3880,6 +3880,7 @@
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
#define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa
#define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3

/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
Expand Down
2 changes: 0 additions & 2 deletions src/include/elog.h
View file
Expand Up @@ -6,8 +6,6 @@
#include <commonlib/bsd/elog.h>
#include <stdint.h>

#define MAX_EVENT_SIZE 0x7F

#if CONFIG(ELOG)
/* Eventlog backing storage must be initialized before calling elog_init(). */
extern int elog_init(void);
Expand Down
26 changes: 0 additions & 26 deletions src/include/gic.h
View file

This file was deleted.

112 changes: 112 additions & 0 deletions src/include/mipi/dsi.h
View file
@@ -0,0 +1,112 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __MIPI_DSI_H__
#define __MIPI_DSI_H__

/* MIPI DSI Processor-to-Peripheral transaction types */
enum mipi_dsi_transaction {
MIPI_DSI_V_SYNC_START = 0x01,
MIPI_DSI_V_SYNC_END = 0x11,
MIPI_DSI_H_SYNC_START = 0x21,
MIPI_DSI_H_SYNC_END = 0x31,

MIPI_DSI_COLOR_MODE_OFF = 0x02,
MIPI_DSI_COLOR_MODE_ON = 0x12,
MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,

MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,

MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,

MIPI_DSI_DCS_SHORT_WRITE = 0x05,
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,

MIPI_DSI_DCS_READ = 0x06,

MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,

MIPI_DSI_END_OF_TRANSMISSION = 0x08,

MIPI_DSI_NULL_PACKET = 0x09,
MIPI_DSI_BLANKING_PACKET = 0x19,
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
MIPI_DSI_DCS_LONG_WRITE = 0x39,

MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,

MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,

MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
};

/* MIPI DSI Peripheral-to-Processor transaction types */
enum {
MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
};

/* MIPI DCS commands */
enum {
MIPI_DCS_NOP = 0x00,
MIPI_DCS_SOFT_RESET = 0x01,
MIPI_DCS_GET_DISPLAY_ID = 0x04,
MIPI_DCS_GET_RED_CHANNEL = 0x06,
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
MIPI_DCS_GET_POWER_MODE = 0x0A,
MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
MIPI_DCS_SET_GAMMA_CURVE = 0x26,
MIPI_DCS_SET_DISPLAY_OFF = 0x28,
MIPI_DCS_SET_DISPLAY_ON = 0x29,
MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
MIPI_DCS_SET_TEAR_ON = 0x35,
MIPI_DCS_SET_ADDRESS_MODE = 0x36,
MIPI_DCS_SET_SCROLL_START = 0x37,
MIPI_DCS_EXIT_IDLE_MODE = 0x38,
MIPI_DCS_ENTER_IDLE_MODE = 0x39,
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
MIPI_DCS_READ_DDB_START = 0xA1,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
};

#endif /* __MIPI_DSI_H__ */
3 changes: 2 additions & 1 deletion src/include/mipi/panel.h
View file
Expand Up @@ -4,6 +4,7 @@
#define __MIPI_PANEL_H__

#include <edid.h>
#include <mipi/dsi.h>
#include <types.h>

/* Definitions for cmd in panel_init_command */
Expand All @@ -30,7 +31,7 @@ struct panel_serializable_data {
u8 init[]; /* A packed array of panel_init_command */
};

typedef cb_err_t (*mipi_cmd_func_t)(enum panel_init_cmd cmd, const u8 *data, u8 len);
typedef cb_err_t (*mipi_cmd_func_t)(enum mipi_dsi_transaction type, const u8 *data, u8 len);

/* Parse a command array and call cmd_func() for each entry. Delays get handled internally. */
cb_err_t mipi_panel_parse_init_commands(const void *buf, mipi_cmd_func_t cmd_func);
Expand Down
2 changes: 1 addition & 1 deletion src/include/sar.h
View file
Expand Up @@ -44,7 +44,7 @@ struct avg_profile {
uint8_t revision;
uint8_t tas_selection;
uint8_t tas_list_size;
uint8_t deny_list_entry[MAX_DENYLIST_ENTRY];
uint16_t deny_list_entry[MAX_DENYLIST_ENTRY];
} __packed;

struct dsm_profile {
Expand Down
5 changes: 4 additions & 1 deletion src/include/smbios.h
View file
Expand Up @@ -35,6 +35,9 @@ int smbios_write_type41(unsigned long *current, int *handle,
const char *name, u8 instance, u16 segment,
u8 bus, u8 device, u8 function, u8 device_type);

struct device;
int get_smbios_data(struct device *dev, int *handle, unsigned long *current);

const char *smbios_system_manufacturer(void);
const char *smbios_system_product_name(void);
const char *smbios_system_serial_number(void);
Expand Down Expand Up @@ -825,7 +828,7 @@ enum {
SMBIOS_EVENTLOG_STATUS_FULL = 2, /* Bit 1 */
};

#define SMBIOS_USE_EXTENDED_MAX_CAPACITY (1 << 31)
#define SMBIOS_USE_EXTENDED_MAX_CAPACITY (1ULL << 31)

struct smbios_type16 {
struct smbios_header header;
Expand Down
18 changes: 13 additions & 5 deletions src/lib/Makefile.inc
View file
Expand Up @@ -367,11 +367,19 @@ $(LIB_SPD_BIN): $(LIB_SPD_DEPS)
(echo "HAVE_SPD_IN_CBFS is set but SPD_SOURCES is empty" && exit 1)
test -n "$(LIB_SPD_DEPS)" || \
(echo "SPD_SOURCES is set but no SPD file was found" && exit 1)
for f in $(LIB_SPD_DEPS); \
do for c in $$(cat $$f | grep --binary-files=text -v ^#); \
do printf $$(printf '\\%o' 0x$$c); \
done; \
done > $@
if [ "$(SPD_SOURCES)" = "placeholder" ]; then \
printf '\0'; \
else \
for f in $(LIB_SPD_DEPS); do \
if [ ! -f $$f ]; then \
echo "File not found: $$f" >&2; \
exit 1; \
fi; \
for c in $$(cat $$f | grep --binary-files=text -v ^#); \
do printf $$(printf '\\%o' 0x$$c); \
done; \
done; \
fi > $@

cbfs-files-y += spd.bin
spd.bin-file := $(LIB_SPD_BIN)
Expand Down
1 change: 1 addition & 0 deletions src/lib/coreboot_table.c
View file
Expand Up @@ -253,6 +253,7 @@ static void add_cbmem_pointers(struct lb_header *header)
{CBMEM_ID_DRTM_LOG, LB_TAG_PLATFORM_BLOB_VERSION},
{CBMEM_ID_FMAP, LB_TAG_FMAP},
{CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF},
{CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO},
};
int i;

Expand Down
7 changes: 4 additions & 3 deletions src/lib/hardwaremain.c
View file
Expand Up @@ -23,6 +23,7 @@
#include <thread.h>
#include <timer.h>
#include <timestamp.h>
#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <version.h>

Expand Down Expand Up @@ -55,7 +56,7 @@ struct boot_state {
boot_state_t (*run_state)(void *arg);
void *arg;
int num_samples;
int complete : 1;
bool complete;
};

#define BS_INIT(state_, run_func_) \
Expand All @@ -66,7 +67,7 @@ struct boot_state {
.phases = { { NULL, 0 }, { NULL, 0 } }, \
.run_state = run_func_, \
.arg = NULL, \
.complete = 0, \
.complete = false, \
}
#define BS_INIT_ENTRY(state_, run_func_) \
[state_] = BS_INIT(state_, run_func_)
Expand Down Expand Up @@ -366,7 +367,7 @@ static void bs_walk_state_machine(void)

bs_sample_time(state);

state->complete = 1;
state->complete = true;
}
}

Expand Down
10 changes: 3 additions & 7 deletions src/mainboard/51nb/x210/dsdt.asl
View file
Expand Up @@ -12,11 +12,9 @@ DefinitionBlock(
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"

#include <soc/intel/skylake/acpi/globalnvs.asl>

#include <cpu/intel/common/acpi/cpu.asl>
#include <soc/intel/skylake/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>

Device (\_SB.PCI0)
{
Expand All @@ -25,8 +23,6 @@ DefinitionBlock(
#include "acpi/graphics.asl"
}

#include <southbridge/intel/common/acpi/sleepstates.asl>

// Mainboard specific
#include "acpi/mainboard.asl"
#include "acpi/platform.asl"
}
2 changes: 1 addition & 1 deletion src/mainboard/51nb/x210/gma-mainboard.ads
View file
Expand Up @@ -12,6 +12,6 @@ private package GMA.Mainboard is
(DP1,
DP2,
eDP,
Others => Disabled);
others => Disabled);

end GMA.Mainboard;
1 change: 1 addition & 0 deletions src/mainboard/51nb/x210/romstage.c
View file
Expand Up @@ -36,6 +36,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);

mem_cfg->DqPinsInterleaved = TRUE;
mem_cfg->CaVrefConfig = 2;
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
Expand Down
5 changes: 2 additions & 3 deletions src/mainboard/amd/bilby/devicetree.cb
View file
Expand Up @@ -2,7 +2,7 @@

chip soc/amd/picasso
# ACP Configuration
register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA"
register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_I2S_TDM"

# Set FADT Configuration
register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
Expand Down Expand Up @@ -160,8 +160,7 @@ chip soc/amd/picasso
device ref xgbe_1 off end # integrated Ethernet MAC
end
device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
# chip superio/smsc/sio1036 # optional debug card
end
end # domain

Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/bilby/early_gpio.c
View file
Expand Up @@ -31,5 +31,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {

void mainboard_program_early_gpios(void)
{
program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/bilby/emmc_gpio.c
View file
Expand Up @@ -23,5 +23,5 @@ static const struct soc_amd_gpio emmc_gpios[] = {
/* Don't call this if the board uses the LPC bus. */
void mainboard_program_emmc_gpios(void)
{
program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios));
gpio_configure_pads(emmc_gpios, ARRAY_SIZE(emmc_gpios));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/bilby/gpio.c
View file
Expand Up @@ -23,5 +23,5 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {

void mainboard_program_gpios(void)
{
program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/gardenia/bootblock/bootblock.c
View file
Expand Up @@ -10,5 +10,5 @@ void bootblock_mainboard_early_init(void)
size_t num_gpios;
const struct soc_amd_gpio *gpios;
gpios = early_gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
gpio_configure_pads(gpios, num_gpios);
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/gardenia/mainboard.c
View file
Expand Up @@ -69,7 +69,7 @@ static void mainboard_init(void *chip_info)
size_t num_gpios;
const struct soc_amd_gpio *gpios;
gpios = gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
gpio_configure_pads(gpios, num_gpios);
}

/*************************************************
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/amd/inagua/mainboard.c
View file
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/acpimmio.h>
#include <amdblocks/acpimmio_legacy_gpio100.h>
#include <console/console.h>
#include <device/device.h>
#include <southbridge/amd/common/amd_pci_util.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/majolica/early_gpio.c
View file
Expand Up @@ -14,5 +14,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {

void mainboard_program_early_gpios(void)
{
program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/emmc_gpio.c
View file
Expand Up @@ -23,5 +23,5 @@ static const struct soc_amd_gpio emmc_gpios[] = {
/* Don't call this if the board uses the LPC bus. */
void mainboard_program_emmc_gpios(void)
{
program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios));
gpio_configure_pads(emmc_gpios, ARRAY_SIZE(emmc_gpios));
}
3 changes: 1 addition & 2 deletions src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
View file
Expand Up @@ -149,8 +149,7 @@ chip soc/amd/picasso
device ref xgbe_1 off end # integrated Ethernet MAC
end
device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
# chip superio/smsc/sio1036 # optional debug card
end
end # domain

Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/variants/cereme/early_gpio.c
View file
Expand Up @@ -28,5 +28,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {

void mainboard_program_early_gpios(void)
{
program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/variants/cereme/gpio.c
View file
Expand Up @@ -29,5 +29,5 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {

void mainboard_program_gpios(void)
{
program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
}
3 changes: 1 addition & 2 deletions src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
View file
Expand Up @@ -149,8 +149,7 @@ chip soc/amd/picasso
device ref xgbe_1 off end # integrated Ethernet MAC
end
device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
# chip superio/smsc/sio1036 # optional debug card
end
end # domain

Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c
View file
Expand Up @@ -32,5 +32,5 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {

void mainboard_program_early_gpios(void)
{
program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/variants/mandolin/gpio.c
View file
Expand Up @@ -34,5 +34,5 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {

void mainboard_program_gpios(void)
{
program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/padmelon/bootblock/bootblock.c
View file
Expand Up @@ -46,5 +46,5 @@ void bootblock_mainboard_init(void)
const struct soc_amd_gpio *gpios;

gpios = early_gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
gpio_configure_pads(gpios, num_gpios);
}
2 changes: 1 addition & 1 deletion src/mainboard/amd/padmelon/mainboard.c
View file
Expand Up @@ -98,7 +98,7 @@ static void mainboard_init(void *chip_info)
size_t num_gpios;
const struct soc_amd_gpio *gpios;
gpios = gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
gpio_configure_pads(gpios, num_gpios);
}

/*************************************************
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/amd/south_station/mainboard.c
View file
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/acpimmio.h>
#include <amdblocks/acpimmio_legacy_gpio100.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/amd/thatcher/bootblock.c
View file
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/acpimmio.h>
#include <amdblocks/acpimmio_legacy_gpio100.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <superio/smsc/lpc47n217/lpc47n217.h>
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/asrock/e350m1/devicetree.cb
View file
Expand Up @@ -92,8 +92,8 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 15.1 on end # PCIe PortB: NIC
device pci 15.2 on end # PCIe PortC: USB3
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
device pci 16.0 on end # OHCI mPCIe
device pci 16.2 on end # EHCI mPCIe

# gpp_configuration options
#0000: PortA lanes[3:0]
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/asrock/h110m/romstage.c
View file
Expand Up @@ -22,6 +22,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets));

mem_cfg->DqPinsInterleaved = 1;
mem_cfg->CaVrefConfig = 2;
get_spd_smbus(&blk);
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads
View file
Expand Up @@ -11,6 +11,6 @@ private package GMA.Mainboard is
ports : constant Port_List :=
(HDMI3,
Analog,
Others => Disabled);
others => Disabled);

end GMA.Mainboard;
1 change: 1 addition & 0 deletions src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c
View file
Expand Up @@ -32,6 +32,7 @@ void variant_configure_fspm(FSPM_UPD *mupd)
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);

mem_cfg->DqPinsInterleaved = TRUE;
mem_cfg->CaVrefConfig = 2;
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
Expand Down
10 changes: 2 additions & 8 deletions src/mainboard/facebook/monolith/dsdt.asl
View file
Expand Up @@ -11,13 +11,10 @@ DefinitionBlock(
)
{
#include <acpi/dsdt_top.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>

// global NVS and variables
#include <soc/intel/skylake/acpi/globalnvs.asl>

// CPU
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>

Scope (\_SB) {
Device (PCI0)
Expand All @@ -30,8 +27,5 @@ DefinitionBlock(
#include "acpi/dptf.asl"
}

#include <southbridge/intel/common/acpi/sleepstates.asl>

// Mainboard specific
#include "acpi/mainboard.asl"
}
1 change: 1 addition & 0 deletions src/mainboard/facebook/monolith/romstage.c
View file
Expand Up @@ -19,6 +19,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);

mem_cfg->DqPinsInterleaved = 1;
mem_cfg->CaVrefConfig = 2;
get_spd_smbus(&blk);
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
Expand Down
2 changes: 0 additions & 2 deletions src/mainboard/getac/p470/devicetree.cb
View file
Expand Up @@ -123,8 +123,6 @@ chip northbridge/intel/i945
end
device pnp 4e.b off # HWM
end
chip ec/acpi
end
end

end
Expand Down
6 changes: 6 additions & 0 deletions src/mainboard/google/asurada/chromeos.c
View file
Expand Up @@ -40,3 +40,9 @@ int tis_plat_irq_status(void)
{
return gpio_eint_poll(GPIO_H1_AP_INT);
}

int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. This is active low. */
return !!gpio_get(GPIO_EC_IN_RW);
}
17 changes: 13 additions & 4 deletions src/mainboard/google/asurada/mainboard.c
View file
Expand Up @@ -64,6 +64,12 @@ static void register_reset_to_bl31(void)
register_bl31_aux_param(&param_reset.h);
}

/* Override hs_da_trail for ANX7625 */
void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
{
timing->da_hs_trail += 9;
}

/* Set up backlight control pins as output pin and power-off by default */
static void configure_backlight_and_bridge(void)
{
Expand Down Expand Up @@ -102,10 +108,6 @@ static bool configure_display(void)
printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__);
return false;
}
if (anx7625_dp_start(i2c_bus, &edid) < 0) {
printk(BIOS_ERR, "%s: Can't start display via ANX7625\n", __func__);
return false;
}

const char *name = edid.ascii_string;
if (name[0] == '\0')
Expand All @@ -122,12 +124,19 @@ static bool configure_display(void)
u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
MIPI_DSI_MODE_LPM |
MIPI_DSI_MODE_LINE_END |
MIPI_DSI_MODE_EOT_PACKET);

if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL) < 0) {
printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__);
return false;
}

if (anx7625_dp_start(i2c_bus, &edid) < 0) {
printk(BIOS_ERR, "%s: Can't start display via ANX7625\n", __func__);
return false;
}

mtk_ddp_mode_set(&edid);
fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0);
return true;
Expand Down
13 changes: 13 additions & 0 deletions src/mainboard/google/auron/chromeos.c
View file
Expand Up @@ -8,6 +8,13 @@
/* SPI Write protect is GPIO 16 */
#define CROS_WP_GPIO 58

/* EC_IN_RW is GPIO 25 in samus and 14 otherwise */
#if CONFIG(BOARD_GOOGLE_SAMUS)
#define EC_IN_RW_GPIO 25
#else
#define EC_IN_RW_GPIO 14
#endif

void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
Expand All @@ -32,3 +39,9 @@ void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
return !get_gpio(EC_IN_RW_GPIO);
}
24 changes: 8 additions & 16 deletions src/mainboard/google/auron/variants/auron_paine/pei_data.c
View file
Expand Up @@ -12,29 +12,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->dimm_channel1_disabled = 2;

/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P3: BT */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P4: Port B, CN6 */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);

/* P1: Port A, CN6 */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
Expand Down
24 changes: 8 additions & 16 deletions src/mainboard/google/auron/variants/auron_yuna/pei_data.c
View file
Expand Up @@ -12,29 +12,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->dimm_channel1_disabled = 2;

/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P3: BT */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P4: Port B, CN6 */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);

/* P1: Port A, CN6 */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
Expand Down
24 changes: 8 additions & 16 deletions src/mainboard/google/auron/variants/buddy/pei_data.c
View file
Expand Up @@ -8,29 +8,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->ec_present = 1;

/* P0: Side USB3.0 port, USB3S1 */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_INTERNAL);
/* P1: Rear USB3.0 port, USB3R1 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_INTERNAL);
/* P2: Rear USB3.0 port, USB3R2 */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, 1,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 2, 0x0080, 1, 1, USB_PORT_INTERNAL);
/* P3: Card Reader, CRS1 */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P4: Rear USB2.0 port, USB2R1 */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_INTERNAL);
/* P5: 2D Camera */
pei_data_usb2_port(pei_data, 5, 0x0000, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 5, 0x0000, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P6: VP8 */
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P7: WLAN & BT */
pei_data_usb2_port(pei_data, 7, 0x0000, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 7, 0x0000, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);

/* P1: Side USB3.0 port, USB3S1 */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
Expand Down
24 changes: 8 additions & 16 deletions src/mainboard/google/auron/variants/gandof/pei_data.c
View file
Expand Up @@ -12,29 +12,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->dimm_channel1_disabled = 2;

/* P0: LTE */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P1: POrt A, CN10 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P3: BT */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P4: Port B, CN6 */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, USB_PORT_BACK_PANEL);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);

/* P1: Port A, CN6 */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
Expand Down
24 changes: 8 additions & 16 deletions src/mainboard/google/auron/variants/lulu/pei_data.c
View file
Expand Up @@ -12,29 +12,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->dimm_channel1_disabled = 2;

/* P0: Port B, CN01 (IOBoard) */
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL);
/* P1: Port A, CN01 */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 2,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 1, 0x0040, 1, 2, USB_PORT_BACK_PANEL);
/* P2: CCD */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P3: BT */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_MINI_PCIE);
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
/* P4: Empty */
pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);
/* P5: EMPTY */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);
/* P6: SD Card */
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_FLEX);
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX);
/* P7: EMPTY */
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);

/* P0: PORTB*/
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
Expand Down
24 changes: 8 additions & 16 deletions src/mainboard/google/auron/variants/samus/pei_data.c
View file
Expand Up @@ -28,29 +28,21 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));

/* P0: HOST PORT */
pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, USB_PORT_BACK_PANEL);
/* P1: HOST PORT */
pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, USB_PORT_BACK_PANEL);
/* P2: RAIDEN */
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P3: SD CARD */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P4: RAIDEN */
pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P5: WWAN (Disabled) */
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP);
/* P6: CAMERA */
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);
/* P7: BT */
pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
USB_PORT_INTERNAL);
pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL);

/* P1: HOST PORT */
pei_data_usb3_port(pei_data, 0, 1, 0, 0);
Expand Down
7 changes: 7 additions & 0 deletions src/mainboard/google/beltino/chromeos.c
View file
Expand Up @@ -65,3 +65,10 @@ void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

int get_ec_is_trusted(void)
{
/* Do not have a Chrome EC involved in entering recovery mode;
Always return trusted. */
return 1;
}
22 changes: 17 additions & 5 deletions src/mainboard/google/brya/Kconfig
View file
@@ -1,10 +1,12 @@
config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n
select ROMSTAGE_SPD_CBFS
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select HAVE_SPD_IN_CBFS
select SYSTEM_TYPE_LAPTOP

config BOARD_GOOGLE_BASEBOARD_BRASK
def_bool n
select SPD_CACHE_IN_FMAP

if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK

Expand Down Expand Up @@ -43,19 +45,25 @@ config BOARD_GOOGLE_BRYA_COMMON
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select SOC_INTEL_COMMON_BLOCK_TCSS

config BASEBOARD_DIR
string
default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA
default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK

config CHROMEOS
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
select EC_GOOGLE_CHROMEEC_SWITCHES
select HAS_RECOVERY_MRC_CACHE
select VBOOT_LID_SWITCH

config CHROMEOS_WIFI_SAR
bool "Enable SAR options for Chrome OS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
select SAR_ENABLE
select USE_SAR

config DEVICETREE
default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"

Expand Down Expand Up @@ -111,8 +119,12 @@ config UART_FOR_CONSOLE
int
default 0

config ROMSTAGE_SPD_CBFS
config HAVE_WWAN_POWER_SEQUENCE
def_bool n
select HAVE_SPD_IN_CBFS
help
Select this if the variant has a WWAN module and requires the poweroff sequence
to be performed on shutdown. Must define WWAN_FCPO, WWAN_RST and WWAN_PERST GPIOs
in variant.h, as well as T1_OFF_MS (time between PERST & RST) and T2_OFF_MS (time
between RST and FCPO).

endif # BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
30 changes: 21 additions & 9 deletions src/mainboard/google/brya/Kconfig.name
View file
@@ -1,52 +1,64 @@
comment "Brya"

config BOARD_GOOGLE_BRYA0
bool "Brya 0"
bool "-> Brya 0"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_INTEL_MIPI_CAMERA
select HAVE_WWAN_POWER_SEQUENCE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES

config BOARD_GOOGLE_BRASK
bool "Brask"
bool "-> Brask"
select BOARD_GOOGLE_BASEBOARD_BRASK
select SOC_INTEL_CRASHLOG
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES

config BOARD_GOOGLE_PRIMUS
bool "-> Primus"
bool "-> Primus"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9755
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES

config BOARD_GOOGLE_GIMBLE
bool "-> Gimble"
bool "-> Gimble"
select BOARD_GOOGLE_BASEBOARD_BRYA
select CHROMEOS_DSM_CALIB if CHROMEOS
select DRIVERS_I2C_MAX98390

config BOARD_GOOGLE_REDRIX
bool "-> Redrix"
bool "-> Redrix"
select BOARD_GOOGLE_BASEBOARD_BRYA
select CHROMEOS_DSM_CALIB if CHROMEOS
select DRIVERS_I2C_MAX98390
select DRIVERS_INTEL_MIPI_CAMERA
select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
select SOC_INTEL_COMMON_BLOCK_IPU
select DRIVERS_GENESYSLOGIC_GL9755
select DRIVERS_GFX_GENERIC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES

config BOARD_GOOGLE_KANO
bool "-> Kano"
bool "-> Kano"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_I2C_MAX98373
select DRIVERS_I2C_NAU8825
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select DRIVERS_INTEL_MIPI_CAMERA
select SOC_INTEL_COMMON_BLOCK_IPU

config BOARD_GOOGLE_TAEKO
bool "-> Taeko"
bool "-> Taeko"
select BOARD_GOOGLE_BASEBOARD_BRYA

config BOARD_GOOGLE_FELWINTER
bool "-> Felwinter"
bool "-> Felwinter"
select BOARD_GOOGLE_BASEBOARD_BRYA

config BOARD_GOOGLE_ANAHERA
bool "-> Anahera"
bool "-> Anahera"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GFX_GENERIC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
4 changes: 2 additions & 2 deletions src/mainboard/google/brya/Makefile.inc
View file
Expand Up @@ -3,7 +3,7 @@ bootblock-y += bootblock.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c

romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
romstage-y += romstage.c

ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
Expand All @@ -15,7 +15,7 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
subdirs-y += variants/$(VARIANT_DIR)
subdirs-y += variants/$(VARIANT_DIR)/memory
subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd
subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd

CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
Expand Down
6 changes: 6 additions & 0 deletions src/mainboard/google/brya/chromeos.c
View file
Expand Up @@ -29,3 +29,9 @@ void mainboard_chromeos_acpi_generate(void)
gpios = variant_cros_gpios(&num);
chromeos_acpi_gpio_generate(gpios, num);
}

int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
return !gpio_get(GPIO_EC_IN_RW);
}
5 changes: 5 additions & 0 deletions src/mainboard/google/brya/chromeos.fmd
View file
Expand Up @@ -21,6 +21,11 @@ FLASH 32M {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for brya variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
Expand Down
4 changes: 3 additions & 1 deletion src/mainboard/google/brya/dsdt.asl
View file
Expand Up @@ -23,7 +23,9 @@ DefinitionBlock(

Scope (\_SB) {
#include "mainboard.asl"

#if CONFIG(HAVE_WWAN_POWER_SEQUENCE)
#include "wwan_power.asl"
#endif
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
Expand Down
14 changes: 10 additions & 4 deletions ...mainboard/google/brya/romstage_spd_cbfs.c → src/mainboard/google/brya/romstage.c
View file
Expand Up @@ -5,16 +5,22 @@
#include <fsp/api.h>
#include <gpio.h>
#include <soc/romstage.h>
#include <string.h>

void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
{
const struct mb_cfg *mem_config = variant_memory_params();
bool half_populated = variant_is_half_populated();
struct mem_spd spd_info;

const struct mem_spd spd_info = {
.topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = variant_memory_sku(),
};
memset(&spd_info, 0, sizeof(spd_info));
variant_get_spd_info(&spd_info);

const struct pad_config *pads;
size_t pads_num;

memcfg_init(m_cfg, mem_config, &spd_info, half_populated);

pads = variant_romstage_gpio_table(&pads_num);
gpio_configure_pads(pads, pads_num);
}
7 changes: 1 addition & 6 deletions src/mainboard/google/brya/spd/Makefile.inc
View file
Expand Up @@ -2,10 +2,5 @@
##

ifneq ($(SPD_SOURCES),)
ifeq ($(SPD_SOURCE_PATH),)
SPD_SOURCE_PATH := src/soc/intel/alderlake/spd
endif

LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), $(SPD_SOURCE_PATH)/$(f))

LIB_SPD_DEPS := $(SPD_SOURCES)
endif
6 changes: 6 additions & 0 deletions src/mainboard/google/brya/variants/anahera/Makefile.inc
View file
@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c

ramstage-y += gpio.c

ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
57 changes: 57 additions & 0 deletions src/mainboard/google/brya/variants/anahera/fw_config.c
View file
@@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <bootstate.h>
#include <console/console.h>
#include <fw_config.h>
#include <gpio.h>

static const struct pad_config dmic_enable_pads[] = {
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0 */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0 */

};

static const struct pad_config dmic_disable_pads[] = {
PAD_NC(GPP_R4, NONE),
PAD_NC(GPP_R5, NONE),
};

static const struct pad_config i2s_enable_pads[] = {
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
};

static const struct pad_config i2s_disable_pads[] = {
PAD_NC(GPP_R0, NONE),
PAD_NC(GPP_R1, NONE),
PAD_NC(GPP_R2, NONE),
PAD_NC(GPP_R3, NONE),
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
};

static void fw_config_handle(void *unused)
{
if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
return;
}

if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) ||
fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682IVS_I2S))) {
printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n");
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);