diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md
@@ -166,3 +166,84 @@ This is a research-heavy project.
 
 ### Mentors
 * Ron Minnich <rminnich@google.com>
+
+## Libpayload based memtest payload
+[Memtest86+](https://www.memtest.org/) has some limitations: first and
+foremost it only works on x86, while it can print to serial console the
+GUI only works in legacy VGA mode.
+
+This project would involve porting the memtest suite to libpayload and
+build a payload around it.
+
+### Requirements
+* coreboot knowledge: Should know how to build coreboot images and
+  include payloads.
+* other knowledge: Knowledge on how dram works is a plus.
+* hardware requirements: Initial work can happen on qemu targets,
+  being able to test on coreboot supported hardware is a plus.
+
+### Mentors
+* TODO
+
+## Fix POST code handling
+coreboot supports writing POST codes to I/O port 80.
+There are various Kconfigs that deal with POST codes, which don't have
+effect on most platforms.
+The code to send POST codes is scattered in C and Assembly, some use
+functions, some use macros and others simply use the `outb` instruction.
+The POST codes are duplicated between stages and aren't documented properly.
+
+
+Tasks:
+* Guard Kconfigs with a *depends on* to only show on supported platforms
+* Remove duplicated Kconfigs
+* Replace `outb(0x80, ...)` with calls to `post_code(...)`
+* Update Documentation/POSTCODES
+* Use defines from console/post_codes.h where possible
+* Drop duplicated POST codes
+* Make use of all possible 255 values
+
+### Requirements
+* knowledge in the coreboot build system and the concept of stages
+* other knowledge: Little experience with C and x86 Assembly
+* hardware requirements: Nothing special
+
+### Mentors
+* Patrick Rudolph <patrick.rudolph@9elements.com>
+* Christian Walter <christian.walter@9elements.com>
+
+## Board status replacement
+The [Board status page](https://coreboot.org/status/board-status.html) allows
+to see last working commit of a board. The page is generated by a cron job
+that runs on a huge git repository.
+
+Build an open source replacement written in Golang using existing tools
+and libraries, consisting of a backend, a frontend and client side
+scripts. The backend should connect to an SQL database with can be
+controlled using a RESTful API. The RESTful API should have basic authentication
+for managment tasks and new board status uploads.
+
+At least one older test result should be keept in the database.
+
+The frontend should use established UI libraries or frameworks (for example
+Angular) to display the current board status, that is if it's working or not
+and some details provided with the last test. If a board isn't working the last
+working commit (if any) should be shown in addition to the broken one.
+
+Provide a script/tool that allows to:
+1. Push mainboard details from coreboot master CI
+2. Push mainboard test results from authenticated users containing
+   * working
+   * commit hash
+   * bootlog (if any)
+   * dmesg (if it's booting)
+   * timestamps (if it's booting)
+   * coreboot config
+
+### Requirements
+* coreboot knowledge: Non-technical, needed to perform requirements analysis
+* software knowledge: Golang, SQL for the backend, JS for the frontend
+
+### Mentors
+* Patrick Rudolph <patrick.rudolph@9elements.com>
+* Christian Walter <christian.walter@9elements.com>
diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md
@@ -65,11 +65,20 @@ board can initialize graphics through *libgfxinit*:
     select MAINBOARD_HAS_LIBGFXINIT
 
 Internal ports share some hardware blocks (e.g. backlight, panel
-power sequencer). Therefore, each board has to select either eDP
-or LVDS as the internal port, if any:
+power sequencer). Therefore, each system with an integrated panel
+should set `GFX_GMA_PANEL_1_PORT` to the respective port, e.g.:
 
-    select GFX_GMA_INTERNAL_IS_EDP	# the default, or
-    select GFX_GMA_INTERNAL_IS_LVDS
+    config GFX_GMA_PANEL_1_PORT
+            default "DP3"
+
+For the most common cases, LVDS and eDP, exists a shorthand, one
+can select either:
+
+    select GFX_GMA_PANEL_1_ON_EDP	# the default, or
+    select GFX_GMA_PANEL_1_ON_LVDS
+
+Some newer chips feature a second block of panel control logic.
+For this, `GFX_GMA_PANEL_2_PORT` can be set.
 
 Boards with a DVI-I connector share the DDC (I2C) pins for both
 analog and digital displays. In this case, *libgfxinit* needs to
@@ -96,7 +105,8 @@ You can select from the following Ports:
 
     type Port_Type is
       (Disabled,	-- optionally terminates the list
-       Internal,	-- either eDP or LVDS as selected in Kconfig
+       LVDS,
+       eDP,
        DP1,
        DP2,
        DP3,
@@ -112,8 +122,7 @@ both DPx and HDMIx should be listed.
 
 A good example is the mainboard Kontron/KTQM77, it features two
 DP++ ports (DP2/HDMI2, DP3/HDMI3), one DVI-I port (HDMI1/Analog),
-eDP and LVDS. Due to the constraints mentioned above, only one of
-eDP and LVDS can be enabled. It defines `ports` as follows:
+eDP and LVDS. It defines `ports` as follows:
 
     ports : constant Port_List :=
       (DP2,
@@ -122,7 +131,8 @@ eDP and LVDS can be enabled. It defines `ports` as follows:
        HDMI2,
        HDMI3,
        Analog,
-       Internal,
+       LVDS,
+       eDP,
        others => Disabled);
 
 The `GMA.gfxinit()` procedure probes for display EDIDs in the

diff --git a/Documentation/mainboard/51nb/x210.jpg b/Documentation/mainboard/51nb/x210.jpg
diff --git a/Documentation/mainboard/51nb/x210.md b/Documentation/mainboard/51nb/x210.md
@@ -0,0 +1,45 @@
+# 51NB X210
+
+## Extracting vendor EC firmware
+
+EC firmware is included in the SPI image. To extract it, run:
+
+``
+dd bs=64K skip=32 count=1 if=bios.rom of=ec.bin
+``
+
+and ensure that you have a file that includes the string "Insyde Software Corp"
+
+## Flashing instructions
+
+This can be performed using the internal SPI controller, even when flashing
+from stock firmware. Use flashrom -p internal and follow the appropriate
+flashrom instructions to force it. Alternatively, external flashing has been
+tested with Dediprog SF100 and SF600 and using a Beaglebone Black. The flash
+is located on the upper side of the motherboard, below the keyboard
+connector. It is circled in red here:
+![](x210.jpg)
+
+## Flashing a subset of the ROM
+
+If you want to flash coreboot without extracting firmware blobs, you can
+flash coreboot without overwriting those blobs. After building coreboot,
+create a layout file with the following content:
+
+```
+00000000:001fffff me
+00200000:0020ffff ec
+00210000:007fffff main
+```
+
+and run flashrom with the "--layout rom.layout --image main" arguments. This
+will flash the main firmware without overwriting the existing EC or ME
+firmware.
+
+## Working
+
+All hardware features are believed to be working, although the SD reader is
+untested. Note that certain hotkeys don't work (including the Thinkvantage
+button) - this is a limitation of the EC firmware, and these keys also
+generate no events under the stock vendor firmware.
+
diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md
@@ -1,6 +1,6 @@
-# ASUS P8Z77-M Pro
+# ASUS P8Z77-M PRO
 
-This page describes how to run coreboot on the [ASUS P8Z77-M Pro]
+This page describes how to run coreboot on the [ASUS P8Z77-M PRO]
 
 ## Flashing coreboot
 
@@ -163,6 +163,6 @@ easy to remove and reflash.
 
 - [Flash chip datasheet][W25Q64FVA1Q]
 
-[ASUS P8Z88-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/
+[ASUS P8Z77-M PRO]: https://www.asus.com/Motherboards/P8Z77M_PRO/
 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
 [flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -2,6 +2,10 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
+## 51NB
+
+- [X210](51nb/x210.md)
+
 ## AMD
 - [padmelon](amd/padmelon/padmelon.md)
 
@@ -71,12 +75,17 @@ The boards in this section are not real mainboards, but emulators.
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
-### Nehalem series
+## Libretrend
+
+- [LT1000](libretrend/lt1000.md)
+
+### Arrandale series
 
 - [T410](lenovo/t410.md)
 
 ### GM45 series
 
+- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
 - [X301](lenovo/x301.md)
 
 ### Sandy Bridge series
@@ -116,6 +125,11 @@ The boards in this section are not real mainboards, but emulators.
 
 - [PQ7-M107](portwell/pq7-m107.md)
 
+## Protectli
+
+- [FW2B / FW4B](protectli/fw2b_fw4b.md)
+- [FW6A / FW6B / FW6C](protectli/fw6.md)
+
 ## Roda
 
 - [RK9 Flash Header](roda/rk9/flash_header.md)
@@ -130,6 +144,10 @@ The boards in this section are not real mainboards, but emulators.
 - [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
 - [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
 
+## System76
+
+- [Lemur Pro](system76/lemp9.md)
+
 ## UP
 
 - [Squared](up/squared/index.md)
diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md
@@ -33,9 +33,7 @@
   usable by coreboot.
 * ROM chip size should be set to 8MiB.
 
-```eval_rst
-Please also have a look at :doc:`../../flash_tutorial/index`.
-```
+Please also have a look at the [flashing tutorial]
 
 ## Flash layout
 There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions.
@@ -46,3 +44,26 @@ region. The update is then written into the EC once.
 
 [fl]: flashlayout_Sandy_Bridge.svg
 
+## Reducing Intel Managment Engine firmware size
+
+It is possible to reduce the Intel ME firmware size to free additional
+space for the `bios` region. This is usually refered to as *cleaning the ME* or
+*stripping the ME*.
+After reducing the Intel ME firmware size you must modify the original IFD
+and then write a full ROM using an [external programmer].
+Have a look at the [me_cleaner] for more information.
+
+Tests on Lenovo X220 showed no issues with a stripped ME firmware.
+
+**Modified flash layout:**
+
+![][fl2]
+
+[fl2]: flashlayout_Sandy_Bridge_stripped_me.svg
+
+The overall size of the `gbe`, `me,` `ifd` region is less than 128KiB, leaving
+the remaining space for the `bios` partition.
+
+
+[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
+[external programmer]: ../../flash_tutorial/index.md
diff --git a/Documentation/mainboard/lenovo/codenames.csv b/Documentation/mainboard/lenovo/codenames.csv
@@ -1,4 +1,6 @@
-t60,magi-5|magi-7|austin-3
+t60,magi (dGPU) | lisa (iGPU)
+z61m,BW2
+z61t,BV2
 t400,malibu-3
 t400s,shinai
 t410,nozomi-1
@@ -16,13 +18,18 @@ w510,kendo-1 workstation
 w520,kendo-3 workstation
 w530,kendo-4 workstation
 w700,n-note
+w701,n-note 3.0 (nico-3)
 x1_carbon_gen1,genesis-1
 x60,ks note
 x61,ks note-3
 x200,mocha-1
+x200s,pecan-1
+x200t,caramel-1
 x201,mocha-3
 x220,dasher-1
+x220t,comet-1
 x230,dasher-2
+x230t,comet-2
 x230s,rogue-1
 x240,rogue-2
 x300,kodachi

diff --git a/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg
diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md
@@ -0,0 +1,164 @@
+# Lenovo X200 / T400 / T500 / X301 common
+
+These models are sold with either 8 MiB or 4 MiB flash chip. You can identify
+the chip in your machine through flashrom:
+```console
+# flashrom -p internal
+```
+
+Note that this does not allow you to determine whether the chip is in a SOIC-8
+or a SOIC-16 package.
+
+## Installing without ME firmware
+
+```eval_rst
+.. Note::
+   **ThinkPad R500** has slightly different flash layout (it doesn't have
+   ``gbe`` region), so the process would be a little different for that model.
+```
+
+On Montevina machines it's possible to disable ME and remove its firmware from
+SPI flash by modifying the flash descriptor. This also makes it possible to use
+the flash region the ME used for `bios` region, allowing for much larger
+payloads.
+
+First of all create a backup of your ROM with an external programmer:
+```console
+# flashrom -p YOUR_PROGRAMMER -r backup.rom
+```
+
+Then, split the IFD regions into separate files with ifdtool. You will need
+`flashregion_3_gbe.bin` later.
+```console
+$ ifdtool -x backup.rom
+```
+
+Now you need to patch the flash descriptor. You can either [modify the one from
+your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
+[generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg).
+
+#### Modifying flash descriptor using ifdtool
+
+Pick the layout according to your chip size from the table below and save it to
+the `new_layout.txt` file:
+
+```eval_rst
++---------------------------+---------------------------+---------------------------+
+| 4 MB chip                 | 8 MB chip                 | 16 MB chip                |
++===========================+===========================+===========================+
+| .. code-block:: none      | .. code-block:: none      | .. code-block:: none      |
+|                           |                           |                           |
+|    00000000:00000fff fd   |    00000000:00000fff fd   |    00000000:00000fff fd   |
+|    00001000:00002fff gbe  |    00001000:00002fff gbe  |    00001000:00002fff gbe  |
+|    00003000:003fffff bios |    00003000:007fffff bios |    00003000:01ffffff bios |
+|    00fff000:00000fff pd   |    00fff000:00000fff pd   |    00fff000:00000fff pd   |
+|    00fff000:00000fff me   |    00fff000:00000fff me   |    00fff000:00000fff me   |
++---------------------------+---------------------------+---------------------------+
+```
+
+The last two lines define `pd` and `me` regions of negative size. This way
+ifdtool will mark those as unused.
+
+Update regions in the flash descrpitor (it was extracted previously with
+`ifdtool -x`):
+```console
+$ ifdtool -n new_layout.txt flashregion_0_flashdescriptor.bin
+```
+
+Set `MeDisable` bit in ICH0 and MCH0 straps:
+```console
+$ ifdtool -M 1 flashregion_0_flashdescriptor.bin.new
+```
+
+Delete previous descriptors and rename the final one:
+```console
+$ rm flashregion_0_flashdescriptor.bin
+$ rm flashregion_0_flashdescriptor.bin.new
+$ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
+```
+
+Continue to the [Configuring coreboot](#configuring-coreboot) section.
+
+#### Creating a new flash descriptor using bincfg
+
+There is a tool to generate a modified flash descriptor called **bincfg**. Go to
+`util/bincfg` and build it:
+```console
+$ cd util/bincfg
+$ make
+```
+
+If your flash is not 8 MB, you need to change values of `flcomp_density1` and
+`flreg1_limit` in the ifd-x200.set file according to following table:
+
+```eval_rst
++-----------------+-------+-------+--------+
+|                 | 4 MB  | 8 MB  | 16 MB  |
++=================+=======+=======+========+
+| flcomp_density1 | 0x3   | 0x4   | 0x5    |
++-----------------+-------+-------+--------+
+| flreg1_limit    | 0x3ff | 0x7ff | 0x1fff |
++-----------------+-------+-------+--------+
+```
+
+Then create the flash descriptor:
+```console
+$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin
+```
+
+#### Configuring coreboot
+
+Now configure coreboot. You need to select correct chip size and specify paths
+to flash descriptor and gbe dump.
+
+```
+Mainboard --->
+    ROM chip size (8192 KB (8 MB)) # According to your chip
+    (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip
+
+Chipset --->
+    [*] Add Intel descriptor.bin file
+    # Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin
+    (/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file
+
+    [*] Add gigabit ethernet configuration
+    (/path/to/flashregion_3_gbe.bin) Path to gigabit ethernet configuration
+```
+
+Then build coreboot and flash whole `build/coreboot.rom` to the chip.
+
+## Installing with ME firmware
+
+To install coreboot and keep ME working, you don't need to do anything special
+with the flash descriptor. Just flash only `bios` externally and don't touch any
+other regions:
+```console
+# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
+```
+
+## Flash layout
+
+The flash layouts of the OEM firmware are as follows:
+
+```eval_rst
++---------------------------------+---------------------------------+
+| 4 MB chip                       | 8 MB chip                       |
++=================================+=================================+
+| .. code-block:: none            | .. code-block:: none            |
+|                                 |                                 |
+|    00000000:00000fff fd         |    00000000:00000fff fd         |
+|    00001000:001f5fff me         |    00001000:005f5fff me         |
+|    001f6000:001f7fff gbe        |    005f6000:005f7fff gbe        |
+|    001f8000:001fffff pd         |    005f8000:005fffff pd         |
+|    00200000:003fffff bios       |    00600000:007fffff bios       |
+|    00290000:002affff ec         |    00690000:006affff ec         |
+|    003e0000:003fffff bootblock  |    007e0000:007fffff bootblock  |
++---------------------------------+---------------------------------+
+```
+
+On each boot of vendor BIOS `ec` area in flash is checked for having firmware
+there, and if there is one, it proceedes to update firmware on H8S/2116 (when
+both external power and main battery are attached). Once update is performed,
+first 64 KB of `ec` area is erased. Visit
+[thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn
+more about how to extract EC firmware from vendor updates.
diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md
@@ -36,10 +36,7 @@ the laptop able to power on.
 - Cannot get the mainboard serial number from the mainboard: the OEM
   UEFI firmware gets the serial number from an "emulated EEPROM" via
   I/O port 0x1630/0x1634, but it's still unknown how to make it work
-
-## Untested
-
-- the dGPU model
+- The dGPU does not currently work in Windows.
 
 ## Working
 
@@ -61,6 +58,7 @@ the laptop able to power on.
 - CMOS options: wlan, trackpoint, fn_ctrl_swap
 - internal flashing when IFD is unlocked
 - using `me_cleaner`
+- dGPU (must be enabled in CMOS options)
 
 [Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p
 [Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf
diff --git a/Documentation/mainboard/libretrend/lt1000.jpg b/Documentation/mainboard/libretrend/lt1000.jpg
diff --git a/Documentation/mainboard/libretrend/lt1000.md b/Documentation/mainboard/libretrend/lt1000.md
@@ -0,0 +1,117 @@
+# Libretrend LT1000
+
+This page describes how to run coreboot on the [Libretrend LT1000] (aka
+Librebox).
+
+![](lt1000.jpg)
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
++-----------------+---------------------------------+---------------------+
+| microcode       | CPU microcode                   | Required            |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done
+automatically by coreboot build system and included into the image) from the
+*3rdparty/fsp* submodule.
+
+Microcode updates are automatically included into the coreboot image by build
+system from the *3rdparty/intel-microcode* submodule.
+
+The mainboard code also contains a VBT file (version 1.00, BDB version 2.09)
+which is automatically included into the image by coreboot build system.
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. It is strongly advised to
+flash only the BIOS region if not having an external programmer, see known
+issues.
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located on the top middle side of the board near the CPU fan,
+between the DIMM slots and the M.2 disk. Use a clip (or solder the wires) to
+program the chip. Specifically, it's a Winbond W25Q64FV (3.3V) -
+[datasheet][W25Q64FV].
+
+## Known issues
+
+- Fastboot (MRC cache) is not working reliably (missing schematics for CPU to
+  DIMM wiring).
+- Flashing ME region with already cleaned ME firmware may lead to platform not
+  booting, flashing full ME firmware is needed to recover.
+- In order to have the USB device wake support from S3 state using the front
+  USB 3.0 ports, one has to move the jumper on DUSB1_PWR_SET header (it will
+  switch the power rails for the USB 3.0 ports).
+- There are 6 unknown GPIO pins on the board.
+
+## Untested
+
+Not all mainboard's peripherals and functions were tested because of lack of
+the cables or not being populated on the board case.
+
+- LVDS header
+- Onboard USB 2.0 and USB 3.0 headers
+- Speakers and mic header
+- SPDIF header
+- Audio header
+- PS/2 header
+- LPT header
+- CIR (infrared header)
+- COM2 port RS485 mode (RS232/RS485 mode is controlled via jumper)
+- SYS_FAN header
+
+## Working
+
+- USB
+- Ethernet
+- Integrated graphics (with libgfxinit) on VGA and HDMI ports
+- flashrom
+- PCIe
+- NVMe
+- WiFi and Bluetooth
+- SATA
+- Serial ports 1-6
+- SMBus
+- HDA (verbs not implemented yet, but works under GNU/Linux (4.15 tested))
+- Initialization with KBL FSP 2.0
+- SeaBIOS payload (version rel-1.13.0)
+- TPM2 ([custom module] connected to LPC DEBUG header)
+- Automatic fan control
+- Platform boots with cleaned ME (MFS partition must be left on SPI flash)
+
+## Technology
+
+The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not
+sold yet). More details on [baseboard site]. Unfortunately the board manual is
+not publicly available.
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Core i7-6500U                              |
++------------------+--------------------------------------------------+
+| PCH              | Skylake-U Premium                                |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE IT8786E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[Libretrend LT1000]: https://libretrend.com/specs/librebox/
+[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[baseboard site]: http://www.minicase.net/product_LR-i7S65T1.html
+[custom module]: https://shop.3mdeb.com/product/tpm2-module-for-librebox/
diff --git a/Documentation/mainboard/protectli/fw2b.jpg b/Documentation/mainboard/protectli/fw2b.jpg
diff --git a/Documentation/mainboard/protectli/fw2b_fw4b.md b/Documentation/mainboard/protectli/fw2b_fw4b.md
@@ -0,0 +1,128 @@
+# Protectli Vault FW2B and FW4B
+
+This page describes how to run coreboot on the [Protectli FW2B] and
+[Protectli FW4B].
+
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| FSP             | Intel Firmware Support Package  | Required            |
++-----------------+---------------------------------+---------------------+
+| microcode       | CPU microcode                   | Required            |
++-----------------+---------------------------------+---------------------+
+| vgabios         | VGA Option ROM                  | Optional            |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP is automatically added by coreboot build system into the image) from the
+`3rdparty/fsp` submodule.
+
+microcode updates are automatically included into the coreboot image by build
+system from the `3rdparty/intel-microcode` submodule.
+
+VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
+stage, it should be included.
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located on the bottom side of the case (the radiator side). One
+has to remove all screws (in order): 4 top cover screws, 4 side cover screws
+(one side is enough), 4 mainboard screws, 3 CPU screws (under the DIMM). Lift
+up the mainboard and turn around it. The flash chip is near the mainboard edge
+close to the Ethernet Controllers. Use a clip (or solder the wires) to program
+the chip. **Watch out on the voltage, the SPI operates at 1.8V!** Specifically,
+it's a Macronix MX25U6435F (1.8V) - [datasheet][MX25U6435F].
+
+## Known issues
+
+- After flashing with external programmer the board will not boot if flashed
+  the BIOS region only. For some reason it is required to flash whole image
+  along with TXE region.
+- USB 3.0 ports get detected very late in SeaBIOS, it needs huge timeout
+  values in order to get the devices detected.
+
+## Untested
+
+Not all mainboard's peripherals and functions were tested because of lack of
+the cables or not being populated on the board case.
+
+- internal USB 2.0 header
+
+## Working
+
+- USB 3.0 front ports (SeaBIOS and Linux)
+- 4 Ethernet ports (2 Ethernet ports on FW2B)
+- 2 HDMI ports with VGA Option ROM
+- 2 HDMI ports with libgfxinit
+- flashrom
+- PCIe WiFi
+- SATA and mSATA
+- Super I/O serial port 0 (RS232 via front RJ45 connector)
+- SMBus (reading SPD from DIMMs)
+- initialization with Braswell FSP
+- SeaBIOS payload (version rel-1.13.0)
+
+- booting Debian, Ubuntu, FreeBSD
+
+## Not working
+
+- mPCIe debug card connected to mSATA (mSATA slot has LPC signals routed,
+  however for some reason the debug card is not powered)
+
+## Technology
+
+The mainboard has two variants: FW2B and FW4B. They have different Braswell
+SoC. The FW2B replaces 2 out of 4 Ethernet Controllers with 4 USB ports
+connected via [FE1.1 USB 2.0 hub].
+
+- FW2B:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Celeron J3060                              |
++------------------+--------------------------------------------------+
+| PCH              | Braswell                                         |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Trusted Execution Engine                   |
++------------------+--------------------------------------------------+
+```
+
+![](fw2b.jpg)
+
+- FW4B:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Celeron J3160                              |
++------------------+--------------------------------------------------+
+| PCH              | Braswell                                         |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Trusted Execution Engine                   |
++------------------+--------------------------------------------------+
+```
+
+![](fw4b.jpg)
+
+[Protectli FW2B]: https://protectli.com/vault-2-port/
+[Protectli FW4B]: https://protectli.com/product/fw4b/
+[MX25U6435F]: https://www.macronix.com/Lists/Datasheet/Attachments/7411/MX25U6435F,%201.8V,%2064Mb,%20v1.5.pdf
+[FE1.1 USB 2.0 hub]: https://cdn-shop.adafruit.com/product-files/2991/FE1.1s+Data+Sheet+(Rev.+1.0).pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/protectli/fw4b.jpg b/Documentation/mainboard/protectli/fw4b.jpg
diff --git a/Documentation/mainboard/protectli/fw6.jpg b/Documentation/mainboard/protectli/fw6.jpg
diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md
@@ -0,0 +1,137 @@
+# Protectli Vault FW6 series
+
+This page describes how to run coreboot on the [Protectli FW6].
+
+![](fw6.jpg)
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
++-----------------+---------------------------------+---------------------+
+| microcode       | CPU microcode                   | Required            |
++-----------------+---------------------------------+---------------------+
+| vgabios         | VGA Option ROM                  | Optional            |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done
+automatically by the coreboot build system and included into the image) from
+the `3rdparty/fsp` submodule.
+
+Microcode updates are automatically included into the coreboot image by build
+system from the `3rdparty/intel-microcode` submodule.
+
+VGA Option ROM is not required to boot, but if one needs graphics in pre-OS
+stage, it should be included (if not using libgfxinit).
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. The first version
+supporting the chipset is flashrom v1.1. Firmware an be easily flashed
+with internal programmer (either BIOS region or full image).
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located on the bottom side of the case (the radiator side). One
+has to remove all screws (in order): 4 top cover screws, 4 side cover screws
+(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up
+the mainboard and turn around it. The flash chip is near the SoC on the DIMM
+slots side. Use a clip (or solder the wires) to program the chip. Specifically,
+it's a Macronix MX25L6406E (3.3V) -[datasheet][MX25L6406E].
+
+## Known issues
+
+- After flashing with external programmer it is always required to reset RTC
+  with jumper or disconnect coin cell temporarily. Only then the platform will
+  boot after flashing.
+- FW6A does not always work reliably with all DIMMs. Linux happens to hang or
+  gives many panics. This issue was present also with vendor BIOS.
+- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs
+  connected). A workaround is to power cycle the board (even a few times) or
+  temporarily disconnect DIMM when platform is powered off.
+- When using libgfxinit and SeaBIOS bootsplash, the red color is dim
+
+## Untested
+
+Not all mainboard's peripherals and functions were tested because of lack of
+the cables or not being populated on the board case.
+
+- Internal USB 2.0 headers
+- Boot with cleaned ME
+
+## Working
+
+- USB 3.0 front ports (SeaBIOS and Linux)
+- 6 Ethernet ports
+- HDMI port with libgfxinit and VGA Option ROM
+- flashrom
+- PCIe WiFi
+- SATA and mSATA
+- Super I/O serial port 0 (RS232 via front RJ45 connector)
+- SMBus (reading SPD from DIMMs)
+- Initialization with KBL FSP 2.0 (with MemoryInit issues)
+- SeaBIOS payload (version rel-1.12.1)
+- Mini PCIe debug card connected to mSATA (mSATA slot has LPC signals routed)
+- Reset switch
+- Booting Debian, Ubuntu, FreeBSD
+
+## Technology
+
+There are 3 variants of FW6 boards: FW6A, FW6B and FW6C. They differ only in
+used SoC.
+
+- FW6A:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Celeron 3865U                              |
++------------------+--------------------------------------------------+
+| PCH              | Kaby Lake U w/ iHDCP2.2 Base                     |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE IT8772E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+- FW6B:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Core i3-7100U                              |
++------------------+--------------------------------------------------+
+| PCH              | Kaby Lake U w/ iHDCP2.2 Premium                  |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE IT8772E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+- FW6C:
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Core i5-7200U                              |
++------------------+--------------------------------------------------+
+| PCH              | Kaby Lake U w/ iHDCP2.2 Premium                  |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE IT8772E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[Protectli FW6]: https://protectli.com/vault-6-port/
+[MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,%2064Mb,%20v1.9.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/northbridge/intel/sandybridge/me_cleaner.md b/Documentation/northbridge/intel/sandybridge/me_cleaner.md
@@ -5,7 +5,7 @@ from the ME firmware partition. In this state the ME errors out and doesn't
 operate any more.
 
 **Using a 'cleaned' ME partition may lead to issues and its use should be
-carefully evaulated.**
+carefully evaluated.**
 
 ## Observations with 'cleaned' ME
 
@@ -18,3 +18,67 @@ carefully evaulated.**
 
 Always test with unmodified IFD and ME section before reporting bugs to the
 coreboot project.
+
+## Tutorial reducing the Intel ME firmware size
+
+By default the cleaned ME firmware will still occupy the same space in
+the firmware image. It's possible to change the firmware partition layout
+and reclaim the space for the use by coreboot.
+With the reduced Intel ME firmware the `ifd`, `gbe` and `me` regions require
+less than 128 KiB of space in the ROM, which leaves the remaining for the
+`bios` region.
+
+This tutorial will guide you through the steps necessary.
+
+### 1. Obtain a full ROM
+
+You need a full and working ROM with a full Intel ME firmware.
+
+### 2. Running me_cleaner
+
+You need to run the *me_cleaner* on a full ROM, here called `fulldump.rom`:
+The full ROM contains:
+* IFD
+* fully working Intel ME
+* GbE (optional)
+* BIOS (any firmware)
+
+Running the command will generate two new files:
+```console
+./util/me_cleaner/me_cleaner.py -D patched_desciptor.bin -M stripped_me.bin fulldump.rom -t -r -S
+```
+
+The generated files are:
+* a patched IFD called `patched_desciptor.bin`
+* stripped Intel ME called `stripped_me.bin`
+
+The patched IFD has the *AltMeDisable* bit set and a modified flash layout.
+
+
+*Note:* coreboot allows to select `CONFIG_ME_CLEANER` as part of the
+build-process, but that doesn't rework the flash layout, it only removes
+files from ME and sets the *AltMeDisable*-bit.
+
+### 3. Build coreboot
+
+1. Now include the two new files from the previous step into coreboot's
+   build system.
+2. Make sure to also increase the CBFS size
+   * 0x7E0000 for a 8MiB ROM
+   * 0xBE0000 for a 12MiB ROM
+   * 0xFE0000 for a 16MiB ROM
+3. Make sure to **not** enable me_cleaner in Kconfig again as
+   you have already run it
+
+### 4. Flashing the ROM
+
+As you have modified the layout you need to write the **full ROM** to flash
+using an [external programmer].
+Make sure to include all partitions into the ROM:
+* IFD
+* EC (might be unused)
+* GbE (might be unused)
+* ME
+* BIOS
+
+[external programmer]: ../../../flash_tutorial/index.md
diff --git a/Documentation/payloads.md b/Documentation/payloads.md
@@ -40,3 +40,15 @@ availability of well-tested, battle-hardened drivers (as compared to
 firmware project drivers that often reinvent the wheel) and the ability to
 define boot policy with familiar tools, no matter if those are shell scripts
 or compiled userland programs written in C, Go or other programming languages.
+
+## Heads
+
+[Heads] is a distribution that bundles coreboot, Linux, busybox and custom
+tools to provide reproducible ROMs. [Heads] aims to provide a secure and
+flexible boot environment for laptops and servers.
+It supports features like measured boot, kexec, GPG, OTP, TLS, firmware
+updates, but only works on a limited amount of mainboards.
+For more details have a look at [heads-wiki].
+
+[Heads]: https://github.com/osresearch/heads
+[heads-wiki]: http://osresearch.net/
diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
@@ -68,6 +68,7 @@ be more frequent than was needed, so we scaled it back to twice a year.
 - [ ] Test the commit selected for release.
 - [ ] Update release notes with actual commit id, push to repo.
 - [ ] Run release script.
+- [ ] Run vboot_list script.
 - [ ] Test the release from the actual release tarballs.
 - [ ] Push signed Tag to repo.
 - [ ] Announce that the release tag is done on IRC.

diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md
@@ -12,6 +12,8 @@ Google's verified boot support consists of:
 
 Google's vboot verifies the firmware and places measurements within the TPM.
 
+- [List of supported Devices](list_vboot.md)
+
 ***
 
 ## Root of Trust

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
@@ -0,0 +1,223 @@
+# VBOOT enabled devices
+
+## Emulation
+- QEMU x86 i440fx/piix4 (aka qemu -M pc)
+- QEMU x86 q35/ich9 (aka qemu -M q35, since v1.4)
+
+## Facebook
+- Facebook Monolith
+
+## Google
+- Auron_Paine (Acer C740 Chromebook)
+- Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))
+- Buddy (Acer Chromebase 24)
+- Gandof (Toshiba Chromebook 2 (2015))
+- Lulu (Dell Chromebook 13 7310)
+- Samus (Google Chromebook Pixel (2015))
+- Mccloud (Acer Chromebox CXI)
+- Monroe (LG Chromebase 22CV241 & 22CB25S)
+- Panther (ASUS Chromebox CN60)
+- Tricky (Dell Chromebox 3010)
+- Zako (HP Chromebox G1)
+- Butterfly (HP Pavilion Chromebook 14)
+- Cheza
+- Banon (Acer Chromebook 15 (CB3-532))
+- Celes (Samsung Chromebook 3)
+- Cyan (Acer Chromebook R11 (C738T))
+- Edgar (Acer Chromebook 14 (CB3-431))
+- Kefka (Dell Chromebook 11 3180/3189)
+- Reks (Lenovo N22/N42 Chromebook)
+- Relm
+- Setzer (HP Chromebook 11 G5)
+- Terra (ASUS Chromebook C202SA/C300SA/C301SA)
+- Ultima (Lenovo Yoga 11e G3)
+- Wizpig
+- Daisy (Samsung Chromebook (2012))
+- DragonEgg
+- Drallion
+- Eve (Google Pixelbook)
+- Fizz
+- Karma
+- Endeavour
+- Foster
+- Gale (Google WiFi)
+- Asuka (Dell Chromebook 13 3380)
+- Caroline (Samsung Chromebook Pro)
+- Cave (Asus Chromebook Flip C302SA)
+- Chell (HP Chromebook 13 G1)
+- Glados Skylake Reference Board
+- Lars (Acer Chromebook 14 for Work (CP5-471))
+- Sentry (Lenovo Thinkpad 13 Chromebook)
+- Kevin (Samsung Chromebook Plus)
+- Gru
+- Bob (Asus Chromebook Flip C101PA)
+- Scarlet
+- Nefario
+- Rainier
+- Akemi
+- Dratini
+- Hatch
+- Jinlon
+- Kohaku
+- Kindred
+- Helios
+- Mushu
+- Palkia
+- Nightfury
+- Puff
+- Helios_Diskswap
+- Stryke
+- Guado (ASUS Chromebox CN62)
+- Jecht
+- Rikku (Acer Chromebox CXI2)
+- Tidus (Lenovo ThinkCentre Chromebox)
+- Aleena
+- Careena
+- Grunt
+- Liara
+- Nuwani
+- Treeya
+- Kukui
+- Krane
+- Kodama
+- Kakadu
+- Flapjack
+- Jacuzzi
+- Juniper
+- Kappa
+- Damu
+- Link (Google Chromebook Pixel (2013))
+- Mistral
+- Nyan
+- Nyan Big (Acer Chromebook 13 (CB5-311))
+- Nyan Blaze (HP Chromebook 14 G3)
+- Oak
+- Elm (Acer Chromebook R13)
+- Hana (Lenovo N23 Yoga Chromebook)
+- Parrot (Acer C7/C710 Chromebook)
+- Peach Pit (Samsung Chromebook 2 11\")
+- Atlas
+- Poppy
+- Nami
+- Nautilus
+- Nocturne
+- Rammus
+- Soraka
+- Banjo (Acer Chromebook 15 (CB3-531))
+- Candy (Dell Chromebook 11 3120)
+- Clapper (Lenovo N20 Chromebook)
+- Enguarde
+- Glimmer (Lenovo ThinkPad 11e Chromebook)
+- Gnawty (Acer Chromebook 11 (CB3-111/131,C730/C730E/C735))
+- Heli (Haier Chromebook G2)
+- Kip (HP Chromebook 11 G3 / G4 / G4 EE)
+- Ninja (AOpen Chromebox Commercial)
+- Orco (Lenovo 100S Chromebook)
+- Quawks (ASUS Chromebook C300)
+- Squawks (ASUS Chromebook C200)
+- Rambi
+- Sumo (AOpen Chromebase Commercial)
+- Swanky (Toshiba Chromebook 2)
+- Winky (Samsung Chromebook 2 (XE500C12))
+- Reef/Electro (Acer Chromebook Spin 11 R751T)
+- Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
+- Sand (Acer Chromebook 15 CB515-1HT/1H)
+- Snappy (HP Chromebook x360 11 G1 EE)
+- Nasher
+- Coral
+- Arcada
+- Sarien
+- Falco (HP Chromebook 14)
+- Leon (Toshiba Chromebook)
+- Peppy (Acer C720/C720P Chromebook)
+- Wolf (Dell Chromebook 11)
+- Smaug (Google Pixel C)
+- Storm (OnHub Router TGR1900)
+- Stout (Lenovo Thinkpad X131e Chromebook)
+- Trogdor
+- Veyron_Jaq (Haier Chromebook 11)
+- Veyron_Jerry (Hisense Chromebook 11)
+- Veyron_Mighty (Haier Chromebook 11(edu))
+- Veyron_Minnie (ASUS Chromebook Flip C100)
+- Veyron_Speedy (ASUS C201 Chromebook)
+- Veyron_Mickey (Asus Chromebit CS10)
+- Veyron_Rialto
+
+## HP
+- Z220 SFF Workstation
+
+## Intel
+- Basking Ridge CRB
+- Cannonlake U LPDDR4 RVP
+- Cannonlake Y LPDDR4 RVP
+- Coffeelake U SO-DIMM DDR4 RVP
+- Coffeelake H SO-DIMM DDR4 RVP11
+- Whiskeylake U DDR4 RVP
+- Coffeelake S U-DIMM DDR4 RVP8
+- Cometlake U DDR4 RVP
+- Emerald Lake 2 CRB
+- Galileo
+- Glkrvp
+- Icelake U DDR4/LPDDR4 RVP
+- Icelake Y LPDDR4 RVP
+- Jasperlake DDR4/LPDDR4 RVP
+- Jasperlake DDR4/LPDDR4 RVP with Chrome EC
+- Kabylake LPDDR3 RVP3
+- Kabylake DDR3L RVP7
+- Kabylake DDR4 RVP8
+- Kabylake DDR4 RVP11
+- Kunimitsu
+- Strago
+- Tigerlake UP3 RVP
+- Tigerlake UP4 RVP
+- Whitetip Mountain 2 CRB
+
+## Lenovo
+- ThinkPad T400
+- ThinkPad T500
+- ThinkPad R400
+- ThinkPad R500
+- ThinkPad W500
+- ThinkPad T410
+- ThinkPad T420
+- ThinkPad T420s
+- ThinkPad T430
+- ThinkPad T430s
+- ThinkPad T431s
+- ThinkPad T440p
+- ThinkPad T520
+- ThinkPad W520
+- ThinkPad T530
+- ThinkPad W530
+- ThinkPad X131e
+- ThinkPad X1 carbon gen 1
+- ThinkPad X200 / X200s / X200t
+- ThinkPad X301
+- ThinkPad X201 / X201i / X201s / X201t
+- ThinkPad X220
+- ThinkPad X220i
+- ThinkPad X1
+- ThinkPad X230
+- ThinkPad X230t
+
+## OpenCellular
+- Elgon (GBCv2)
+
+## SAMSUNG
+- Lumpy
+- Stumpy
+
+## Siemens
+- MC APL1
+- MC APL2
+- MC APL3
+- MC APL4
+- MC APL5
+- MC APL6
+
+## Supermicro
+- X11SSH-TF
+- X11SSM-F
+
+## UP
+- Squared
diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md
@@ -5,6 +5,7 @@ This section contains documentation about coreboot on specific SuperIOs.
 ## Nuvoton
 
 - [NPCD378](nuvoton/npcd378.md)
+- [NCT5539D](nuvoton/nct5539d.md)
 
 ## Common
 - [PNP devices](common/pnp.md)

diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md
@@ -0,0 +1,9 @@
+# NCT5539D SuperIO
+
+The SuperIO has the ID `0xd121` and the source can be found in
+`src/superio/nuvoton/nct5539d/`.
+
+## For developers
+
+The SuperIO generates ACPI using the
+[SSDT generator for generic SuperIOs](../common/ssdt.md).
diff --git a/Documentation/util.md b/Documentation/util.md
@@ -126,8 +126,6 @@ operating system (only Linux at this time). `C`
 * __util_readme__ - Creates README.md of description files in `./util`
 subdirectories `Bash`
 * __vgabios__ - emulated vga driver for qemu `C`
-* __viatool__ - Extract certain configuration bits on VIA chipsets and
-CPUs. `C`
 * __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
 `Go`
 * __xcompile__ - Cross compile setup `Bash`

diff --git a/MAINTAINERS b/MAINTAINERS
@@ -317,12 +317,24 @@ M:	Vlado Cibic <vladocb@protonmail.com>
 S:	Maintained
 F:	src/mainboard/asus/p8z77-m_pro/
 
+LIBRETREND LT1000 MAINBOARD
+M:	Piotr Król <piotr.krol@3mdeb.com>
+M:	Michał Żygowski <michal.zygowski@3mdeb.com>
+S:	Maintained
+F:	src/mainboard/libretrend/lt1000
+
 PC ENGINES ALL MAINBOARDS
 M:	Piotr Król <piotr.krol@3mdeb.com>
 M:	Michał Żygowski <michal.zygowski@3mdeb.com>
 S:	Supported
 F:	src/mainboard/pcengines/
 
+PROTECTLI ALL MAINBOARDS
+M:	Piotr Król <piotr.krol@3mdeb.com>
+M:	Michał Żygowski <michal.zygowski@3mdeb.com>
+S:	Maintained
+F:	src/mainboard/protectli/
+
 SIEMENS MC_xxxx MAINBOARDS
 M:	Werner Zeh <werner.zeh@siemens.com>
 S:	Maintained

diff --git a/Makefile b/Makefile
@@ -42,6 +42,8 @@ objutil ?= $(obj)/util
 objk := $(objutil)/kconfig
 absobj := $(abspath $(obj))
 
+VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib)
+
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
 COREBOOT_EXPORTS += top src srck obj objutil objk
 
@@ -82,6 +84,7 @@ Q:=@
 ifneq ($(V),1)
 ifneq ($(Q),)
 .SILENT:
+MAKEFLAGS += -s
 endif
 endif
 

diff --git a/Makefile.inc b/Makefile.inc
@@ -421,6 +421,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
 CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla
+CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
@@ -1111,6 +1112,7 @@ ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
 	$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
 endif
 ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
+ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
 	@printf "    UPDATE-FIT\n"
 	$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
@@ -1145,8 +1147,8 @@ endif
 
 endif
 
-endif
-
+endif # !CONFIG_UPDATE_IMAGE
+endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 ifeq ($(CONFIG_AGESA_UCODE_EXPERIMENTAL),y)
 	dd if=$(CONFIG_CPU_UCODE_BINARIES) of=$@.tmp bs=1 seek=6665692 count=3424 conv=notrunc 2> /dev/null
 endif

diff --git a/configs/builder/config.intel.cpx.crb b/configs/builder/config.intel.cpx.crb
@@ -0,0 +1,17 @@
+# type this to get working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.cpx.crb
+
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_CEDARISLAND_CRB=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="site-local/cedarisland_crb/ucode-05-06-5a"
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_T_FILE="site-local/cedarisland_crb/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/cedarisland_crb/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/cedarisland_crb/Server_S.fd"
+CONFIG_ME_BIN_PATH="site-local/cedarisland_crb/me.bin"
+CONFIG_IFD_BIN_PATH="site-local/cedarisland_crb/descriptor.bin"
diff --git a/configs/builder/config.ocp.tiogapass b/configs/builder/config.ocp.tiogapass
@@ -0,0 +1,17 @@
+# type this to get working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass
+
+CONFIG_VENDOR_OCP=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_T_FILE="site-local/tiogapass/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/tiogapass/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/tiogapass/Server_S.fd"
+CONFIG_ME_BIN_PATH="site-local/tiogapass/me.bin"
+CONFIG_IFD_BIN_PATH="site-local/tiogapass/descriptor.bin"
+CONFIG_USE_BLOBS=y
diff --git a/configs/config.google_octopus_spi_flash_console b/configs/config.google_octopus_spi_flash_console
@@ -0,0 +1,4 @@
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_OCTOPUS=y
+CONFIG_CONSOLE_SPI_FLASH=y
+# CONFIG_VBOOT_MEASURED_BOOT is not set
diff --git a/configs/config.intel.cfl_rvp11_fsp_car → ...igs/config.intel_coffeelake_rvp11.fsp_car b/configs/config.intel.cfl_rvp11_fsp_car → ...igs/config.intel_coffeelake_rvp11.fsp_car
diff --git a/configs/config.libretrend_lt1000 b/configs/config.libretrend_lt1000
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_LIBRETREND=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_USER_TPM2=y
+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
diff --git a/configs/config.ocp_tiogapass b/configs/config.ocp_tiogapass
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_OCP=y
+CONFIG_BOARD_OCP_TIOGAPASS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.4"
+CONFIG_LOCALVERSION="v4.11.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_NO_GFX_INIT=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.4"
+CONFIG_LOCALVERSION="v4.11.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.4"
+CONFIG_LOCALVERSION="v4.11.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.4"
+CONFIG_LOCALVERSION="v4.11.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.11.0.4"
+CONFIG_LOCALVERSION="v4.11.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -78,7 +78,7 @@ etc/grub.cfg-required := the GRUB runtime configuration file ($(CONFIG_GRUB2_RUN
 # SeaBIOS
 
 SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1)
-payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG)
+payloads/external/SeaBIOS/seabios/out/bios.bin.elf: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/SeaBIOS \
 			HOSTCC="$(HOSTCC)" \
 			CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \
@@ -104,7 +104,7 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG)
 			CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \
 			CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS)
 
-payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios
+payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
 payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
 payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
 

diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
@@ -30,7 +30,6 @@ endchoice
 
 config TIANOCORE_REVISION_ID
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/coreboot-4.7.x-uefi"
 	help
 	   The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master"
 	   for master branch of Tianocore release on github.

diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
@@ -25,8 +25,8 @@ upstream_git_repo=https://github.com/tianocore/edk2
 # STABLE revision is 3mdeb's coreboot uefi (coreboot-4.7.x-uefi) branch
 ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y)
 bootloader=UefiPayloadPkg
-build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS)
-TAG=$(CONFIG_TIANOCORE_REVISION_ID)
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+TAG=upstream/master
 else
 bootloader=CorebootPayloadPkg
 # STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
@@ -46,9 +46,9 @@ TIMER=-DUSE_HPET_TIMER
 endif
 
 ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
-	BUILD_STR=-a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
+	BUILD_STR=-q -a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
 else
-	BUILD_STR=-a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
+	BUILD_STR=-q -a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
 endif
 
 all: clean build

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -257,6 +257,11 @@ config QCS405_SERIAL_CONSOLE
 	depends on SERIAL_CONSOLE
 	default n
 
+config QUALCOMM_QUPV3_SERIAL_CONSOLE
+	bool "Qualcomm QUPV3 serial port driver"
+	depends on SERIAL_CONSOLE
+	default n
+
 config PL011_SERIAL_CONSOLE
 	bool "PL011 compatible serial port driver"
 	depends on 8250_SERIAL_CONSOLE
@@ -315,6 +320,13 @@ config COREBOOT_VIDEO_CONSOLE
 	  Say Y here if coreboot switched to a graphics mode and
 	  your payload wants to use it.
 
+config COREBOOT_VIDEO_CENTERED
+	bool "Center a classic 80x25 console on bigger screens"
+	depends on COREBOOT_VIDEO_CONSOLE
+	help
+	  Say 'y' here if your payload is hardcoded to a 80x25 console. Otherwise
+	  its output would look squeezed into the upper-left corner of the screen.
+
 config FONT_SCALE_FACTOR
 	int "Scale factor for the included font"
 	depends on GEODELX_VIDEO_CONSOLE || COREBOOT_VIDEO_CONSOLE

diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor
@@ -4,3 +4,5 @@ CONFIG_LP_TIMER_ARM64_ARCH=y
 CONFIG_LP_USB=y
 CONFIG_LP_USB_EHCI=y
 CONFIG_LP_USB_XHCI=y
+CONFIG_LP_SERIAL_CONSOLE=y
+CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
@@ -38,6 +38,7 @@ libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c
 libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c
 libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c
 libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/qcs405.c serial/serial.c
+libc-$(CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE) += serial/qcom_qupv3_serial.c serial/serial.c
 libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c
 libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c
 libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c

diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c
@@ -2,6 +2,7 @@
  * This file is part of the libpayload project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -111,23 +112,107 @@ int nvram_updating(void)
  */
 void rtc_read_clock(struct tm *time)
 {
-	memset(time, 0, sizeof(*time));
+	u16 timeout = 10000;
+	u8 statusB;
+	u8 reg8;
 
-	while(nvram_updating());
+	memset(time, 0, sizeof(*time));
 
-	time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1;
-	time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS));
-	time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES));
-	time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY));
-	time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS));
+	while (nvram_updating())
+		if (!timeout--)
+			return;
+
+	statusB = nvram_read(NVRAM_RTC_STATUSB);
+
+	if (!(statusB & NVRAM_RTC_FORMAT_BINARY)) {
+		time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1;
+		time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS));
+		time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES));
+		time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY));
+
+		if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) {
+			reg8 = nvram_read(NVRAM_RTC_HOURS);
+			time->tm_hour = bcd2dec(reg8 & 0x7f);
+			time->tm_hour += (reg8 & 0x80) ? 12 : 0;
+			time->tm_hour %= 24;
+		} else {
+			time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS));
+		}
+		time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR));
+	} else {
+		time->tm_mon = nvram_read(NVRAM_RTC_MONTH) - 1;
+		time->tm_sec = nvram_read(NVRAM_RTC_SECONDS);
+		time->tm_min = nvram_read(NVRAM_RTC_MINUTES);
+		time->tm_mday = nvram_read(NVRAM_RTC_DAY);
+		if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) {
+			reg8 = nvram_read(NVRAM_RTC_HOURS);
+			time->tm_hour = reg8 & 0x7f;
+			time->tm_hour += (reg8 & 0x80) ? 12 : 0;
+			time->tm_hour %= 24;
+		} else {
+			time->tm_hour = nvram_read(NVRAM_RTC_HOURS);
+		}
+		time->tm_year = nvram_read(NVRAM_RTC_YEAR);
+	}
 
 	/* Instead of finding the century register,
 	   we just make an assumption that if the year value is
 	   less then 80, then it is 2000+
 	*/
-
-	time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR));
-
 	if (time->tm_year < 80)
 		time->tm_year += 100;
 }
+
+/**
+ * Write the current time and date to the RTC
+ *
+ * @param time A pointer to a broken-down time structure
+ */
+void rtc_write_clock(const struct tm *time)
+{
+	u16 timeout = 10000;
+	u8 statusB;
+	u8 reg8, year;
+
+	while (nvram_updating())
+		if (!timeout--)
+			return;
+
+	statusB = nvram_read(NVRAM_RTC_STATUSB);
+
+	year = time->tm_year;
+	if (year > 100)
+		year -= 100;
+
+	if (!(statusB & NVRAM_RTC_FORMAT_BINARY)) {
+		nvram_write(dec2bcd(time->tm_mon + 1), NVRAM_RTC_MONTH);
+		nvram_write(dec2bcd(time->tm_sec), NVRAM_RTC_SECONDS);
+		nvram_write(dec2bcd(time->tm_min), NVRAM_RTC_MINUTES);
+		nvram_write(dec2bcd(time->tm_mday), NVRAM_RTC_DAY);
+		if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) {
+			if (time->tm_hour > 12)
+				reg8 = dec2bcd(time->tm_hour - 12) | 0x80;
+			else
+				reg8 = dec2bcd(time->tm_hour);
+		} else {
+			reg8 = dec2bcd(time->tm_hour);
+		}
+		nvram_write(reg8, NVRAM_RTC_HOURS);
+		nvram_write(dec2bcd(year), NVRAM_RTC_YEAR);
+	} else {
+		nvram_write(time->tm_mon + 1, NVRAM_RTC_MONTH);
+		nvram_write(time->tm_sec, NVRAM_RTC_SECONDS);
+		nvram_write(time->tm_min, NVRAM_RTC_MINUTES);
+		nvram_write(time->tm_mday, NVRAM_RTC_DAY);
+		if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) {
+			if (time->tm_hour > 12)
+				reg8 = (time->tm_hour - 12) | 0x80;
+			else
+				reg8 = time->tm_hour;
+		} else {
+			reg8 = time->tm_hour;
+		}
+		nvram_write(reg8, NVRAM_RTC_HOURS);
+		nvram_write(year, NVRAM_RTC_YEAR);
+	}
+}
diff --git a/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c b/payloads/libpayload/drivers/serial/qcom_qupv3_serial.c
@@ -0,0 +1,341 @@
+/*
+ * This file is part of the libpayload project.
+ * Copyright (c) 2020 Qualcomm Technologies.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* For simplicity sake let's rely on coreboot initializing the UART. */
+#include <config.h>
+#include <libpayload.h>
+#include <sys/types.h>
+
+#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK	0x1
+#define RX_FIFO_WC_MSK	0x1FFFFFF
+#define START_UART_TX	0x8000000
+
+union proto_word_len {
+	u32 uart_tx_word_len;
+	u32 spi_word_len;
+};
+
+union proto_tx_trans_len {
+	u32 uart_tx_stop_bit_len;
+	u32 i2c_tx_trans_len;
+	u32 spi_tx_trans_len;
+};
+
+union proto_rx_trans_len {
+	u32 uart_tx_trans_len;
+	u32 i2c_rx_trans_len;
+	u32 spi_rx_trans_len;
+};
+
+struct qup_regs {
+	u32 geni_init_cfg_revision;
+	u32 geni_s_init_cfg_revision;
+	u8  _reserved1[0x10 - 0x08];
+	u32 geni_general_cfg;
+	u32 geni_rx_fifo_ctrl;
+	u8  _reserved2[0x20 - 0x18];
+	u32 geni_force_default_reg;
+	u32 geni_output_ctrl;
+	u32 geni_cgc_ctrl;
+	u32 geni_char_cfg;
+	u32 geni_char_data_n;
+	u8  _reserved3[0x40 - 0x34];
+	u32 geni_status;
+	u32 geni_test_bus_ctrl;
+	u32 geni_ser_m_clk_cfg;
+	u32 geni_ser_s_clk_cfg;
+	u32 geni_prog_rom_ctrl_reg;
+	u8  _reserved4[0x60 - 0x54];
+	u32 geni_clk_ctrl_ro;
+	u32 fifo_if_disable_ro;
+	u32 geni_fw_revision_ro;
+	u32 geni_s_fw_revision_ro;
+	u32 geni_fw_multilock_protns_ro;
+	u32 geni_fw_multilock_msa_ro;
+	u32 geni_fw_multilock_sp_ro;
+	u32 geni_clk_sel;
+	u32 geni_dfs_if_cfg;
+	u8 _reserved5[0x100 - 0x084];
+	u32 geni_cfg_reg0;
+	u32 geni_cfg_reg1;
+	u32 geni_cfg_reg2;
+	u32 geni_cfg_reg3;
+	u32 geni_cfg_reg4;
+	u32 geni_cfg_reg5;
+	u32 geni_cfg_reg6;
+	u32 geni_cfg_reg7;
+	u32 geni_cfg_reg8;
+	u32 geni_cfg_reg9;
+	u32 geni_cfg_reg10;
+	u32 geni_cfg_reg11;
+	u32 geni_cfg_reg12;
+	u32 geni_cfg_reg13;
+	u32 geni_cfg_reg14;
+	u32 geni_cfg_reg15;
+	u32 geni_cfg_reg16;
+	u32 geni_cfg_reg17;
+	u32 geni_cfg_reg18;
+	u8  _reserved6[0x200 - 0x14C];
+	u32 geni_cfg_reg64;
+	u32 geni_cfg_reg65;
+	u32 geni_cfg_reg66;
+	u32 geni_cfg_reg67;
+	u32 geni_cfg_reg68;
+	u32 geni_cfg_reg69;
+	u32 geni_cfg_reg70;
+	u32 geni_cfg_reg71;
+	u32 geni_cfg_reg72;
+	u32 spi_cpha;
+	u32 geni_cfg_reg74;
+	u32 proto_loopback_cfg;
+	u32 spi_cpol;
+	u32 i2c_noise_cancellation_ctl;
+	u32 i2c_monitor_ctl;
+	u32 geni_cfg_reg79;
+	u32 geni_cfg_reg80;
+	u32 geni_cfg_reg81;
+	u32 geni_cfg_reg82;
+	u32 spi_demux_output_inv;
+	u32 spi_demux_sel;
+	u32 geni_byte_granularity;
+	u32 geni_dma_mode_en;
+	u32 uart_tx_trans_cfg_reg;
+	u32 geni_tx_packing_cfg0;
+	u32 geni_tx_packing_cfg1;
+	union proto_word_len word_len;
+	union proto_tx_trans_len tx_trans_len;
+	union proto_rx_trans_len rx_trans_len;
+	u32 spi_pre_post_cmd_dly;
+	u32 i2c_scl_counters;
+	u32 geni_cfg_reg95;
+	u32 uart_rx_trans_cfg;
+	u32 geni_rx_packing_cfg0;
+	u32 geni_rx_packing_cfg1;
+	u32 uart_rx_word_len;
+	u32 geni_cfg_reg100;
+	u32 uart_rx_stale_cnt;
+	u32 geni_cfg_reg102;
+	u32 geni_cfg_reg103;
+	u32 geni_cfg_reg104;
+	u32 uart_tx_parity_cfg;
+	u32 uart_rx_parity_cfg;
+	u32 uart_manual_rfr;
+	u32 geni_cfg_reg108;
+	u32 geni_cfg_reg109;
+	u32 geni_cfg_reg110;
+	u8 _reserved7[0x600 - 0x2BC];
+	u32 geni_m_cmd0;
+	u32 geni_m_cmd_ctrl_reg;
+	u8  _reserved8[0x10 - 0x08];
+	u32 geni_m_irq_status;
+	u32 geni_m_irq_enable;
+	u32 geni_m_irq_clear;
+	u32 geni_m_irq_en_set;
+	u32 geni_m_irq_en_clear;
+	u32 geni_m_cmd_err_status;
+	u32 geni_m_fw_err_status;
+	u8  _reserved9[0x30 - 0x2C];
+	u32 geni_s_cmd0;
+	u32 geni_s_cmd_ctrl_reg;
+	u8  _reserved10[0x40 - 0x38];
+	u32 geni_s_irq_status;
+	u32 geni_s_irq_enable;
+	u32 geni_s_irq_clear;
+	u32 geni_s_irq_en_set;
+	u32 geni_s_irq_en_clear;
+	u8  _reserved11[0x700 - 0x654];
+	u32 geni_tx_fifon;
+	u8  _reserved12[0x780 - 0x704];
+	u32 geni_rx_fifon;
+	u8  _reserved13[0x800 - 0x784];
+	u32 geni_tx_fifo_status;
+	u32 geni_rx_fifo_status;
+	u32 geni_tx_fifo_threshold;
+	u32 geni_tx_watermark_reg;
+	u32 geni_rx_watermark_reg;
+	u32 geni_rx_rfr_watermark_reg;
+	u8  _reserved14[0x900 - 0x818];
+	u32 geni_gp_output_reg;
+	u8  _reserved15[0x908 - 0x904];
+	u32 geni_ios;
+	u32 geni_timestamp;
+	u32 geni_m_gp_length;
+	u32 geni_s_gp_length;
+	u8  _reserved16[0x920 - 0x918];
+	u32 geni_hw_irq_en;
+	u32 geni_hw_irq_ignore_on_active;
+	u8  _reserved17[0x930 - 0x928];
+	u32 geni_hw_irq_cmd_param_0;
+	u8  _reserved18[0xA00 - 0x934];
+	u32 geni_i3c_ibi_cfg_tablen;
+	u8  _reserved19[0xA80 - 0xA04];
+	u32 geni_i3c_ibi_status;
+	u32 geni_i3c_ibi_rd_data;
+	u32 geni_i3c_ibi_search_pattern;
+	u32 geni_i3c_ibi_search_data;
+	u32 geni_i3c_sw_ibi_en;
+	u32 geni_i3c_sw_ibi_en_recover;
+	u8 _reserved20[0xC30 - 0xA98];
+	u32 dma_tx_ptr_l;
+	u32 dma_tx_ptr_h;
+	u32 dma_tx_attr;
+	u32 dma_tx_length;
+	u32 dma_tx_irq_stat;
+	u32 dma_tx_irq_clr;
+	u32 dma_tx_irq_en;
+	u32 dma_tx_irq_en_set;
+	u32 dma_tx_irq_en_clr;
+	u32 dma_tx_length_in;
+	u32 dma_tx_fsm_rst;
+	u32 dma_tx_max_burst_size;
+	u8  _reserved21[0xD30 - 0xC60];
+	u32 dma_rx_ptr_l;
+	u32 dma_rx_ptr_h;
+	u32 dma_rx_attr;
+	u32 dma_rx_length;
+	u32 dma_rx_irq_stat;
+	u32 dma_rx_irq_clr;
+	u32 dma_rx_irq_en;
+	u32 dma_rx_irq_en_set;
+	u32 dma_rx_irq_en_clr;
+	u32 dma_rx_length_in;
+	u32 dma_rx_fsm_rst;
+	u32 dma_rx_max_burst_size;
+	u32 dma_rx_flush;
+	u8  _reserved22[0xE14 - 0xD64];
+	u32 se_irq_high_priority;
+	u32 se_gsi_event_en;
+	u32 se_irq_en;
+	u32 dma_if_en_ro;
+	u32 se_hw_param_0;
+	u32 se_hw_param_1;
+	u32 se_hw_param_2;
+	u32 dma_general_cfg;
+	u8  _reserved23[0x40 - 0x34];
+	u32 dma_debug_reg0;
+	u32 dma_test_bus_ctrl;
+	u32 se_top_test_bus_ctrl;
+	u8 _reserved24[0x1000 - 0x0E4C];
+	u32 se_geni_fw_revision;
+	u32 se_s_fw_revision;
+	u8 _reserved25[0x10-0x08];
+	u32 se_geni_cfg_ramn;
+	u8 _reserved26[0x2000 - 0x1014];
+	u32 se_geni_clk_ctrl;
+	u32 se_dma_if_en;
+	u32 se_fifo_if_disable;
+	u32 se_geni_fw_multilock_protns;
+	u32 se_geni_fw_multilock_msa;
+	u32 se_geni_fw_multilock_sp;
+};
+check_member(qup_regs, geni_clk_sel, 0x7C);
+check_member(qup_regs, geni_cfg_reg108, 0x2B0);
+check_member(qup_regs, geni_dma_mode_en, 0x258);
+check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84);
+check_member(qup_regs, dma_test_bus_ctrl, 0xE44);
+check_member(qup_regs, se_geni_cfg_ramn, 0x1010);
+check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014);
+
+static struct console_input_driver consin = {
+	.havekey = serial_havechar,
+	.getchar = serial_getchar,
+	.input_type = CONSOLE_INPUT_TYPE_UART,
+};
+
+static struct console_output_driver consout = {
+	.putchar = serial_putchar,
+};
+
+static struct qup_regs *uart_base_address(void)
+{
+	return (void *)(uintptr_t)lib_sysinfo.serial->baseaddr;
+}
+
+static void uart_qupv3_tx_flush(void)
+{
+	struct qup_regs *regs = uart_base_address();
+
+	while (read32(&regs->geni_status) & GENI_STATUS_M_GENI_CMD_ACTIVE_MASK)
+		;
+}
+
+static unsigned char uart_qupv3_rx_byte(void)
+{
+	struct qup_regs *regs = uart_base_address();
+
+	if (read32(&regs->geni_rx_fifo_status) & RX_FIFO_WC_MSK)
+		return read32(&regs->geni_rx_fifon) & 0xFF;
+
+	return 0;
+}
+
+static void uart_qupv3_tx_byte(unsigned char data)
+{
+	struct qup_regs *regs = uart_base_address();
+
+	uart_qupv3_tx_flush();
+
+	write32(&regs->rx_trans_len.uart_tx_trans_len, 1);
+	/* Start TX */
+	write32(&regs->geni_m_cmd0, START_UART_TX);
+	write32(&regs->geni_tx_fifon, data);
+}
+
+void serial_putchar(unsigned int data)
+{
+	if (data == 0xa)
+		uart_qupv3_tx_byte(0xd);
+	uart_qupv3_tx_byte(data);
+}
+
+int serial_havechar(void)
+{
+	struct qup_regs *regs = uart_base_address();
+
+	if (read32(&regs->geni_rx_fifo_status) & RX_FIFO_WC_MSK)
+		return 1;
+
+	return 0;
+}
+
+int serial_getchar(void)
+{
+	return uart_qupv3_rx_byte();
+}
+
+void serial_console_init(void)
+{
+	if (!lib_sysinfo.serial)
+		return;
+
+	console_add_output_driver(&consout);
+	console_add_input_driver(&consin);
+}
diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c
@@ -81,7 +81,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg,
 	memcpy(&this->device_descriptor, dd, sizeof(*dd));
 
 	if (p->qhlist == NULL)
-		die("failed to allocate memory for usb device mode");
+		die("failed to allocate memory for USB device mode");
 
 	memset(p->qhlist, 0, sizeof(struct qh) * CI_QHELEMENTS);
 
@@ -102,7 +102,7 @@ static int chipidea_hw_init(struct usbdev_ctrl *this, void *_opreg,
 	p->qhlist[1].config = QH_MPS(64) | QH_NO_AUTO_ZLT | QH_IOS;
 
 	do {
-		debug("waiting for usb phy clk valid: %x\n",
+		debug("waiting for USB phy clk valid: %x\n",
 			readl(&p->opreg->susp_ctrl));
 		mdelay(1);
 	} while ((readl(&p->opreg->susp_ctrl) & (1 << 7)) == 0);

diff --git a/payloads/libpayload/drivers/udc/chipidea_priv.h b/payloads/libpayload/drivers/udc/chipidea_priv.h
@@ -47,7 +47,7 @@ struct chipidea_opreg {
 	uint32_t portsc; // 0x174
 	uint32_t pad178[15];
 	uint32_t devlc; // 0x1b4
-		/* 25:26: host-desired usb version
+		/* 25:26: host-desired USB version
 		 * 23: force full speed */
 	uint32_t pad1b8[16];
 	uint32_t usbmode; // 0x1f8

diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c
@@ -291,7 +291,7 @@ static int ehci_set_async_schedule(ehci_t *ehcic, int enable)
 
 	/* Memory barrier to ensure that all memory accesses before we set the
 	 * async schedule are complete. It was observed especially in the case of
-	 * arm64, that netboot and usb stuff resulted in lots of errors possibly
+	 * arm64, that netboot and USB stuff resulted in lots of errors possibly
 	 * due to CPU reordering. Hence, enforcing strict CPU ordering.
 	 */
 	mb();

diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c
@@ -634,14 +634,14 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr)
 
 /*
  * Should be called by the hub drivers whenever a physical detach occurs
- * and can be called by usb class drivers if they are unsatisfied with a
+ * and can be called by USB class drivers if they are unsatisfied with a
  * malfunctioning device.
  */
 void
 usb_detach_device(hci_t *controller, int devno)
 {
 	/* check if device exists, as we may have
-	   been called yet by the usb class driver */
+	   been called yet by the USB class driver */
 	if (controller->devices[devno]) {
 		controller->devices[devno]->destroy (controller->devices[devno]);
 

diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c
@@ -126,7 +126,7 @@ enum {
 	 * MSC commands can be
 	 *   successful,
 	 *   fail with proper response or
-	 *   fail totally, which results in detaching of the usb device
+	 *   fail totally, which results in detaching of the USB device
 	 *   and immediate cleanup of the usbdev_t structure.
 	 * In the latter case the caller has to make sure, that he won't
 	 * use the device any more.
@@ -703,14 +703,14 @@ usb_msc_poll (usbdev_t *dev)
 		return;
 
 	if (!prev_ready && msc->ready) {
-		usb_debug ("usb msc: not ready -> ready (lun %d)\n", msc->lun);
+		usb_debug ("USB msc: not ready -> ready (lun %d)\n", msc->lun);
 		usb_msc_create_disk (dev);
 	} else if (prev_ready && !msc->ready) {
-		usb_debug ("usb msc: ready -> not ready (lun %d)\n", msc->lun);
+		usb_debug ("USB msc: ready -> not ready (lun %d)\n", msc->lun);
 		usb_msc_remove_disk (dev);
 	} else if (!prev_ready && !msc->ready) {
 		u8 new_lun = (msc->lun + 1) % msc->num_luns;
-		usb_debug("usb msc: not ready (lun %d) -> lun %d\n", msc->lun,
+		usb_debug("USB msc: not ready (lun %d) -> lun %d\n", msc->lun,
 			  new_lun);
 		msc->lun = new_lun;
 	}

diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c
@@ -61,45 +61,42 @@ static const u32 vga_colors[] = {
 	(0xFF << 16) | (0xFF << 8) | 0xFF,
 };
 
-/* Addresses for the various components */
-static unsigned long fbinfo;
-static unsigned long fbaddr;
+struct cb_framebuffer fbinfo;
 static unsigned short *chars;
 
-#define FI ((struct cb_framebuffer *) phys_to_virt(fbinfo))
-#define FB ((unsigned char *) phys_to_virt(fbaddr))
-#define CHARS (chars)
+/* Shorthand for up-to-date virtual framebuffer address */
+#define FB ((unsigned char *)phys_to_virt(fbinfo.physical_address))
 
 static void corebootfb_scroll_up(void)
 {
 	unsigned char *dst = FB;
-	unsigned char *src = FB + (FI->bytes_per_line * font_height);
+	unsigned char *src = FB + (fbinfo.bytes_per_line * font_height);
 	int y;
 
 	/* Scroll all lines up */
-	for(y = 0; y < FI->y_resolution - font_height; y++) {
-		memcpy(dst, src, FI->x_resolution * (FI->bits_per_pixel >> 3));
+	for (y = 0; y < fbinfo.y_resolution - font_height; y++) {
+		memcpy(dst, src, fbinfo.x_resolution * (fbinfo.bits_per_pixel >> 3));
 
-		dst += FI->bytes_per_line;
-		src += FI->bytes_per_line;
+		dst += fbinfo.bytes_per_line;
+		src += fbinfo.bytes_per_line;
 	}
 
 	/* Erase last line */
-	dst = FB + (FI->y_resolution - font_height) * FI->bytes_per_line;
+	dst = FB + (fbinfo.y_resolution - font_height) * fbinfo.bytes_per_line;
 
-	for(; y < FI->y_resolution; y++) {
-		memset(dst, 0, FI->x_resolution * (FI->bits_per_pixel >> 3));
-		dst += FI->bytes_per_line;
+	for (; y < fbinfo.y_resolution; y++) {
+		memset(dst, 0, fbinfo.x_resolution * (fbinfo.bits_per_pixel >> 3));
+		dst += fbinfo.bytes_per_line;
 	}
 
 	/* And update the char buffer */
-	dst = (unsigned char *) CHARS;
-	src = (unsigned char *) (CHARS + coreboot_video_console.columns);
+	dst = (unsigned char *)chars;
+	src = (unsigned char *)(chars + coreboot_video_console.columns);
 	memcpy(dst, src, coreboot_video_console.columns *
 			(coreboot_video_console.rows - 1) * 2);
 	int column;
 	for (column = 0; column < coreboot_video_console.columns; column++)
-		CHARS[(coreboot_video_console.rows - 1) * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8);
+		chars[(coreboot_video_console.rows - 1) * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8);
 
 	cursor_y--;
 }
@@ -110,15 +107,15 @@ static void corebootfb_clear(void)
 	unsigned char *ptr = FB;
 
 	/* Clear the screen */
-	for(row = 0; row < FI->y_resolution; row++) {
-		memset(ptr, 0, FI->x_resolution * (FI->bits_per_pixel >> 3));
-		ptr += FI->bytes_per_line;
+	for (row = 0; row < fbinfo.y_resolution; row++) {
+		memset(ptr, 0, fbinfo.x_resolution * (fbinfo.bits_per_pixel >> 3));
+		ptr += fbinfo.bytes_per_line;
 	}
 
 	/* And update the char buffer */
 	for(row = 0; row < coreboot_video_console.rows; row++)
 		for (column = 0; column < coreboot_video_console.columns; column++)
-			CHARS[row * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8);
+			chars[row * coreboot_video_console.columns + column] = (VGA_COLOR_DEFAULT << 8);
 }
 
 static void corebootfb_putchar(u8 row, u8 col, unsigned int ch)
@@ -133,66 +130,66 @@ static void corebootfb_putchar(u8 row, u8 col, unsigned int ch)
 
 	int x, y;
 
-	if (FI->bits_per_pixel > 8) {
-		bgval = ((((vga_colors[bg] >> 0) & 0xff) >> (8 - FI->blue_mask_size)) << FI->blue_mask_pos) |
-			((((vga_colors[bg] >> 8) & 0xff) >> (8 - FI->green_mask_size)) << FI->green_mask_pos) |
-			((((vga_colors[bg] >> 16) & 0xff) >> (8 - FI->red_mask_size)) << FI->red_mask_pos);
-		fgval = ((((vga_colors[fg] >> 0) & 0xff) >> (8 - FI->blue_mask_size)) << FI->blue_mask_pos) |
-			((((vga_colors[fg] >> 8) & 0xff) >> (8 - FI->green_mask_size)) << FI->green_mask_pos) |
-			((((vga_colors[fg] >> 16) & 0xff) >> (8 - FI->red_mask_size)) << FI->red_mask_pos);
+	if (fbinfo.bits_per_pixel > 8) {
+		bgval = ((((vga_colors[bg] >> 0) & 0xff) >> (8 - fbinfo.blue_mask_size)) << fbinfo.blue_mask_pos) |
+			((((vga_colors[bg] >> 8) & 0xff) >> (8 - fbinfo.green_mask_size)) << fbinfo.green_mask_pos) |
+			((((vga_colors[bg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos);
+		fgval = ((((vga_colors[fg] >> 0) & 0xff) >> (8 - fbinfo.blue_mask_size)) << fbinfo.blue_mask_pos) |
+			((((vga_colors[fg] >> 8) & 0xff) >> (8 - fbinfo.green_mask_size)) << fbinfo.green_mask_pos) |
+			((((vga_colors[fg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos);
 	}
 
 
-	dst = FB + ((row * font_height) * FI->bytes_per_line);
-	dst += (col * font_width * (FI->bits_per_pixel >> 3));
+	dst = FB + ((row * font_height) * fbinfo.bytes_per_line);
+	dst += (col * font_width * (fbinfo.bits_per_pixel >> 3));
 
 	for(y = 0; y < font_height; y++) {
 		for(x = font_width - 1; x >= 0; x--) {
 
-			switch (FI->bits_per_pixel) {
+			switch (fbinfo.bits_per_pixel) {
 			case 8: /* Indexed */
-				dst[(font_width - x) * (FI->bits_per_pixel >> 3)] = font_glyph_filled(ch, x, y) ?  fg : bg;
+				dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3)] = font_glyph_filled(ch, x, y) ?  fg : bg;
 				break;
 			case 16: /* 16 bpp */
-				dst16 = (u16 *)(dst + (font_width - x) * (FI->bits_per_pixel >> 3));
+				dst16 = (u16 *)(dst + (font_width - x) * (fbinfo.bits_per_pixel >> 3));
 				*dst16 = font_glyph_filled(ch, x, y) ? fgval : bgval;
 				break;
 			case 24: /* 24 bpp */
 				if (font_glyph_filled(ch, x, y)) {
-					dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 0] = fgval & 0xff;
-					dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 1] = (fgval >> 8) & 0xff;
-					dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 2] = (fgval >> 16) & 0xff;
+					dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 0] = fgval & 0xff;
+					dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 1] = (fgval >> 8) & 0xff;
+					dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 2] = (fgval >> 16) & 0xff;
 				} else {
-					dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 0] = bgval & 0xff;
-					dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 1] = (bgval >> 8) & 0xff;
-					dst[(font_width - x) * (FI->bits_per_pixel >> 3) + 2] = (bgval >> 16) & 0xff;
+					dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 0] = bgval & 0xff;
+					dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 1] = (bgval >> 8) & 0xff;
+					dst[(font_width - x) * (fbinfo.bits_per_pixel >> 3) + 2] = (bgval >> 16) & 0xff;
 				}
 				break;
 			case 32: /* 32 bpp */
-				dst32 = (u32 *)(dst + (font_width - x) * (FI->bits_per_pixel >> 3));
+				dst32 = (u32 *)(dst + (font_width - x) * (fbinfo.bits_per_pixel >> 3));
 				*dst32 = font_glyph_filled(ch, x, y) ? fgval : bgval;
 				break;
 			}
 		}
 
-		dst += FI->bytes_per_line;
+		dst += fbinfo.bytes_per_line;
 	}
 }
 
 static void corebootfb_putc(u8 row, u8 col, unsigned int ch)
 {
-	CHARS[row * coreboot_video_console.columns + col] = ch;
+	chars[row * coreboot_video_console.columns + col] = ch;
 	corebootfb_putchar(row, col, ch);
 }
 
 static void corebootfb_update_cursor(void)
 {
 	int ch, paint;
 	if(cursor_en) {
-		ch = CHARS[cursor_y * coreboot_video_console.columns + cursor_x];
+		ch = chars[cursor_y * coreboot_video_console.columns + cursor_x];
 		paint = (ch & 0xff) | ((ch << 4) & 0xf000) | ((ch >> 4) & 0x0f00);
 	} else {
-		paint = CHARS[cursor_y * coreboot_video_console.columns + cursor_x];
+		paint = chars[cursor_y * coreboot_video_console.columns + cursor_x];
 	}
 
 	if (cursor_y < coreboot_video_console.rows)
@@ -230,18 +227,23 @@ static int corebootfb_init(void)
 	if (lib_sysinfo.framebuffer == NULL)
 		return -1;
 
-	/* We might have been called before relocation (like FILO does). So
-	   just keep the physical address which won't break on relocation. */
-	fbinfo = virt_to_phys(lib_sysinfo.framebuffer);
+	fbinfo = *lib_sysinfo.framebuffer;
 
-	fbaddr = FI->physical_address;
-	if (fbaddr == 0)
+	if (fbinfo.physical_address == 0)
 		return -1;
 
-	font_init(FI->x_resolution);
-
-	coreboot_video_console.columns = FI->x_resolution / font_width;
-	coreboot_video_console.rows = FI->y_resolution / font_height;
+	font_init(fbinfo.x_resolution);
+
+	/* Draw centered on the framebuffer if requested and feasible, */
+	const int center =
+		IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CENTERED)
+		&& coreboot_video_console.columns * font_width <= fbinfo.x_resolution
+		&& coreboot_video_console.rows * font_height <= fbinfo.y_resolution;
+	/* adapt to the framebuffer size, otherwise. */
+	if (!center) {
+		coreboot_video_console.columns = fbinfo.x_resolution / font_width;
+		coreboot_video_console.rows = fbinfo.y_resolution / font_height;
+	}
 
 	chars = malloc(coreboot_video_console.rows *
 		       coreboot_video_console.columns * 2);
@@ -250,6 +252,17 @@ static int corebootfb_init(void)
 
 	// clear boot splash screen if there is one.
 	corebootfb_clear();
+
+	if (center) {
+		fbinfo.physical_address +=
+			(fbinfo.x_resolution - coreboot_video_console.columns * font_width)
+				/ 2 * fbinfo.bits_per_pixel / 8
+			+ (fbinfo.y_resolution - coreboot_video_console.rows * font_height)
+				/ 2 * fbinfo.bytes_per_line;
+		fbinfo.x_resolution = coreboot_video_console.columns * font_width;
+		fbinfo.y_resolution = coreboot_video_console.rows * font_height;
+	}
+
 	return 0;
 }
 

diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
@@ -130,6 +130,9 @@ static const char _pstruct(key)[]                                        \
 #define NVRAM_RTC_YEAR           9      /**< RTC Year offset in CMOS */
 #define NVRAM_RTC_FREQ_SELECT    10     /**< RTC Update Status Register */
 #define  NVRAM_RTC_UIP           0x80
+#define NVRAM_RTC_STATUSB        11     /**< RTC Status Register B */
+#define  NVRAM_RTC_FORMAT_24HOUR 0x02
+#define  NVRAM_RTC_FORMAT_BINARY 0x04
 
 /** Broken down time structure */
 struct tm {
@@ -148,6 +151,7 @@ u8 nvram_read(u8 addr);
 void nvram_write(u8 val, u8 addr);
 int nvram_updating(void);
 void rtc_read_clock(struct tm *tm);
+void rtc_write_clock(const struct tm *tm);
 /** @} */
 
 /**

diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h
@@ -217,7 +217,7 @@ struct usbdev {
 	hci_t *controller;
 	endpoint_t endpoints[32];
 	int num_endp;
-	int address;		// usb address
+	int address;		// USB address
 	int hub;		// hub, device is attached to
 	int port;		// port where device is attached
 	usb_speed speed;
@@ -263,7 +263,7 @@ struct usbdev_hc {
 	u8* (*poll_intr_queue) (void *queue);
 	void *instance;
 
-	/* set_address():		Tell the usb device its address (xHCI
+	/* set_address():		Tell the USB device its address (xHCI
 					controllers want to do this by
 					themselves). Also, allocate the usbdev
 					structure, initialize enpoint 0

diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h
@@ -64,6 +64,11 @@ static inline __attribute__((always_inline)) uint32_t read32(const volatile void
 	return *((volatile uint32_t *)(addr));
 }
 
+static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr)
+{
+	return *((volatile uint64_t *)(addr));
+}
+
 static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
 {
 	*((volatile uint8_t *)(addr)) = value;
@@ -79,6 +84,11 @@ static inline __attribute__((always_inline)) void write32(volatile void *addr, u
 	*((volatile uint32_t *)(addr)) = value;
 }
 
+static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value)
+{
+	*((volatile uint64_t *)(addr)) = value;
+}
+
 static inline unsigned int inl(int port)
 {
 	unsigned long val;

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -212,9 +212,15 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name)
 		}
 
 		// Move to next file.
-		offset += ntohl(file.len) + ntohl(file.offset);
-		if (offset % CBFS_ALIGNMENT)
-			offset += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT);
+		uint32_t next_offset = offset + ntohl(file.len) + ntohl(file.offset);
+		if (next_offset % CBFS_ALIGNMENT)
+			next_offset += CBFS_ALIGNMENT - (next_offset % CBFS_ALIGNMENT);
+		// Check that offset is strictly monotonic to prevent infinite loop
+		if (next_offset <= offset) {
+			ERROR("ERROR: corrupted CBFS file header at 0x%x.\n", offset);
+			break;
+		}
+		offset = next_offset;
 	}
 	media->close(media);
 	LOG("WARNING: '%s' not found.\n", name);
@@ -309,7 +315,14 @@ void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag)
 			return NULL;
 		}
 		if (ntohl(attr.tag) != tag) {
-			offset += ntohl(attr.len);
+			uint32_t next_offset = offset + ntohl(attr.len);
+			// Check that offset is strictly monotonic to prevent infinite loop
+			if (next_offset <= offset) {
+				ERROR("ERROR: corrupted CBFS attribute at 0x%x.\n", offset);
+				m->close(m);
+				return NULL;
+			}
+			offset = next_offset;
 			continue;
 		}
 		ret = m->map(m, offset, ntohl(attr.len));

diff --git a/payloads/libpayload/liblz4/lz4.c.inc b/payloads/libpayload/liblz4/lz4.c.inc
@@ -150,6 +150,7 @@ FORCE_INLINE int LZ4_decompress_generic(
         if ((length=(token>>ML_BITS)) == RUN_MASK)
         {
             unsigned s;
+            if ((endOnInput) && unlikely(ip>=iend-RUN_MASK)) goto _output_error;   /* overflow detection */
             do
             {
                 s = *ip++;

diff --git a/payloads/libpayload/liblz4/lz4_wrapper.c b/payloads/libpayload/liblz4/lz4_wrapper.c
@@ -141,6 +141,9 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
 	}
 
 	while (1) {
+		if ((size_t)(in - src) + sizeof(struct lz4_block_header) > srcn)
+			break;          /* input overrun */
+
 		struct lz4_block_header b = { .raw = le32toh(*(uint32_t *)in) };
 		in += sizeof(struct lz4_block_header);
 

diff --git a/src/Kconfig b/src/Kconfig
@@ -1,8 +1,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
-## Copyright (C) 2009-2010 coresystems GmbH
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -764,7 +762,7 @@ comment "General Debug Settings"
 config GDB_STUB
 	bool "GDB debugging support"
 	default n
-	depends on CONSOLE_SERIAL
+	depends on DRIVERS_UART
 	help
 	  If enabled, you will be able to set breakpoints for gdb debugging.
 	  See src/arch/x86/lib/c_start.S for details.

diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
@@ -1,16 +1,8 @@
 ################################################################################
 ##
+## SPDX-License-Identifier: GPL-2.0-only
 ## This file is part of the coreboot project.
 ##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
 
 ###############################################################################
 # ARM specific options

diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc
@@ -1,16 +1,8 @@
 ################################################################################
 ##
+## SPDX-License-Identifier: GPL-2.0-only
 ## This file is part of the coreboot project.
 ##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
 ###############################################################################
 
 armv4_flags = -marm -march=armv4t -I$(src)/arch/arm/include/armv4/ \

diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S
@@ -1,16 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 /*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  * Early initialization code for ARM architecture.
  *
  * This file is based off of the OMAP3530/ARM Cortex start.S file from Das

diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c
@@ -1,31 +1,6 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* This file is part of the coreboot project. */
 /*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
  * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R
  *
  * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition

diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
@@ -1,16 +1,8 @@
 ################################################################################
 ##
+## SPDX-License-Identifier: GPL-2.0-only
 ## This file is part of the coreboot project.
 ##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
 ###############################################################################
 
 armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7

diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
@@ -1,22 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
 /*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Early initialization code for ARMv7 architecture.
- *
  * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
  * U-Boot, which itself got the file from armboot.
  */
 
+/* Early initialization code for ARMv7 architecture. */
+
 #include <arch/asm.h>
 
 .arm

diff --git a/src/arch/arm/armv7/bootblock_m.S b/src/arch/arm/armv7/bootblock_m.S
@@ -1,32 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- */
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* This file is part of the coreboot project. */
 
 #include <arch/asm.h>
 

diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
@@ -1,31 +1,6 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* This file is part of the coreboot project. */
 /*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
  * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R
  *
  * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition

diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c
@@ -1,31 +1,6 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* This file is part of the coreboot project. */
 /*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
  * cache.c: Cache maintenance routines for ARMv7-M
  */
 

diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
@@ -1,32 +1,6 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* This file is part of the coreboot project. */
 /*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
- * Copyright (c) 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
  * Optimized assembly for low-level CPU operations on ARMv7 processors.
  *
  * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
-Original file line number
+Diff line change
@@ Expand Up / @@ -12,6 +12,8 @@ Google's verified boot support consists of: @@
     Google's vboot verifies the firmware and places measurements within the TPM.
+    - [List of supported Devices](list_vboot.md)
     ***
     ## Root of Trust
@@ Expand Down @@