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# Gigabyte GA-G41M-ES2L rev 1.1

This page describes how to use coreboot on the [Gigabyte GA-G41M-ES2L rev 1.1](https://www.gigabyte.com/Motherboard/GA-G41M-ES2L-rev-11) mainboard.

This motherboard [also works with Libreboot](https://libreboot.org/docs/install/ga-g41m-es2l.html).

## Technology

```eval_rst
+------------------+--------------------------------------------------+
| Type | Value |
+==================+==================================================+
| BIOS flash chips | 2 x SST25VF080B (8 Mbit SPI) (DUAL BIOS) |
+------------------+--------------------------------------------------+
| Northbridge | Intel G41 |
+------------------+--------------------------------------------------+
| Southbridge | Intel ICH7 |
+------------------+--------------------------------------------------+
| CPU socket | LGA775 |
+------------------+--------------------------------------------------+
| RAM | 2 x DDR2 800, max. 8 GiB |
+------------------+--------------------------------------------------+
| SuperIO | ITE IT8718F-S |
+------------------+--------------------------------------------------+
| Audio | Realtek ALC888B |
+------------------+--------------------------------------------------+
| Network | Realtek RTL8111C PCIe Gigabit Ethernet |
+------------------+--------------------------------------------------+
```

## Preparation

```eval_rst
For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
```

### Devuan 4 Chimaera

This probably works also for any fresh Debian/Ubuntu-based distros.

Install tools and libraries needed for coreboot:

```shell
sudo apt-get -V install bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev wget python2 python-is-python2 flashrom
```

### Get sources

You need about 700 MB disk space for sources only and ~2GB disk space for sources + build results

```shell
git clone --recursive https://review.coreboot.org/coreboot.git
```

### Build toolchain

Your system compilers can be different with versions, tested by coreboot developers.
So, it is recommended to build cross-compilers with special versions, which were tested with coreboot.

It is possible to skip this time-consuming part and use `ANY_TOOLCHAIN=y`, but this not recommended.

You can build them for all platforms: `make crossgcc CPUS=2` but this takes ~2 hours with Intel core2duo E8400.

The best way, probably, is to build cross-compilers for your platform (this takes ~20 minutes with Intel core2duo E8400):

```shell
make crossgcc-i386 CPUS=2
```

### Save MAC-address of internal LAN

Run `ip -c link show`, you will find MAC-address like 6c:f0:49:xx:xx:xx

```
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000
link/ether 6c:f0:49:xx:xx:xx brd ff:ff:ff:ff:ff:ff
```

## Configure

Create file `payloads/external/SeaBIOS/.config_seabios`:

```shell
CONFIG_COREBOOT=y
CONFIG_ATA_DMA=y
CONFIG_VGA_COREBOOT=y
```

Edit file `configs/config.gigabyte_ga-g41m-es2l`, replace `CONFIG_REALTEK_8168_MACADDRESS` value with your MAC-address.

Run

```shell
make defconfig KBUILD_DEFCONFIG="configs/config.gigabyte_ga-g41m-es2l"
```

## Build

Just execute:

```shell
make
```

It takes ~2 minutes with Intel core2duo E8400.

Example of last part in the output:

```
CBFSPRINT coreboot.rom
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 62316 none
cpu_microcode_blob.bin 0xf480 microcode 180224 none
fallback/ramstage 0x3b500 stage 98745 none
vgaroms/seavgabios.bin 0x53700 raw 28672 none
config 0x5a740 raw 301 none
revision 0x5a8c0 raw 675 none
build_info 0x5abc0 raw 103 none
fallback/dsdt.aml 0x5ac80 raw 8447 none
rt8168-macaddress 0x5cdc0 raw 17 none
vbt.bin 0x5ce40 raw 802 LZMA (1899 decompressed)
cmos.default 0x5d1c0 cmos_default 256 none
cmos_layout.bin 0x5d300 cmos_layout 1040 none
fallback/postcar 0x5d740 stage 20844 none
fallback/payload 0x62900 simple elf 70270 none
payload_config 0x73bc0 raw 1699 none
payload_revision 0x742c0 raw 237 none
(empty) 0x74400 null 482904 none
bootblock 0xea280 bootblock 23360 none
HOSTCC cbfstool/ifwitool.o
HOSTCC cbfstool/ifwitool (link)
Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
```

## Flashing coreboot

```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
```

### Do backup

The above commands read the SPI flash chip(s), write into file and then verify content again with the chip:

```shell
sudo flashrom -p internal:dualbiosindex=0 -r m_bios.rom
sudo flashrom -p internal:dualbiosindex=0 -v m_bios.rom
sudo flashrom -p internal:dualbiosindex=1 -r b_bios.rom
sudo flashrom -p internal:dualbiosindex=1 -v b_bios.rom
```

If access error appeared, then add `iomem=relaxed` to Linux kernel parameters and restart your Linux system.

You can also repeat backup and compare checksums manually.

Backup file should be stored elsewhere, so that in case the coreboot build is faulty, some external procedure can be used without having to extract the backup from the target device first.

### Write new flash image

Let's write new image into SPI flash chip, verify checksum again and erase second flash chip:

```shell
sudo flashrom -p internal:dualbiosindex=0 -w build/coreboot.rom
sudo flashrom -p internal:dualbiosindex=0 -v build/coreboot.rom
sudo flashrom -p internal:dualbiosindex=1 -E
```

## Set text mode for GRUB

Update your `/etc/default/grub` with:

```shell
GRUB_TERMINAL=console
```

And recreate GRUB configuration `/boot/grub/grub.cfg` by command

```shell
sudo update-grub
```

## Boot with new firmware

Restart your system:

```shell
sudo shutdown -r now
```

If it is needed, use <kbd>Esc</kbd> key to choose boot device.

Remove `iomem=relaxed` from Linux kernel parameters.

Enjoy!

## Status

```
+-----------------------+--------------------------+--------+-------------------------------+
| coreboot version | Date of sources checkout | Status | Comment |
+-----------------------+--------------------------+--------+-------------------------------+
| 4.13-1531-g2fae1c0494 | 2021-01-28 | Good | |
+-----------------------+--------------------------+--------+-------------------------------+
| 4.13-2182-g6410a0002f | 2021-02-18 | Good | |
+-----------------------+--------------------------+--------+-------------------------------+
```

### Known issues

Lm-sensors shows wrong values from it87:

```
coretemp-isa-0000
Adapter: ISA adapter
Core 0: +27.0°C (high = +80.0°C, crit = +100.0°C)
Core 1: +31.0°C (high = +80.0°C, crit = +100.0°C)
it8718-isa-0290
Adapter: ISA adapter
in0: 1.06 V (min = +0.00 V, max = +4.08 V)
in1: 1.90 V (min = +0.00 V, max = +4.08 V)
in2: 3.34 V (min = +0.00 V, max = +4.08 V)
+5V: 2.96 V (min = +0.00 V, max = +4.08 V)
in4: 224.00 mV (min = +0.00 V, max = +4.08 V)
in5: 4.08 V (min = +0.00 V, max = +4.08 V) ALARM
in6: 4.08 V (min = +0.00 V, max = +4.08 V) ALARM
in7: 3.09 V (min = +0.00 V, max = +4.08 V)
Vbat: 2.82 V
fan1: 1290 RPM (min = 0 RPM)
fan2: 0 RPM (min = 0 RPM)
temp1: -54.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor
temp2: -1.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor
temp3: +44.0°C (low = +0.0°C, high = +127.0°C) sensor = thermal diode
cpu0_vid: +1.100 V
intrusion0: ALARM
```

### Working

- RAM 1,2x1GiB DDR2 PC2-6400 Kingston KTC1G-UDIMM (1.8V, 2Rx8 ?)
- RAM 1x1GiB DDR2 PC2-5300 Brooktree AU1G08E32-667P005 / Apogee AU1G082-667P005 CL6 (1.8V, 2Rx8 ?)
- CPU E8400
- ACPI
- CPU frequency scaling
- flashrom under coreboot
- Gigabit Ethernet
- Hardware monitoring
- Integrated graphics
- SATA
- PCI POST card

### Not working

- SuperIO based fan control: PWM fan speed is not changing in depend of CPU temperature
- RAM 1,2x4GiB DDR2 PC2-6400 Samsung M378T5263AZ3-CF7 (2Rx4 PC2-6400U-666-12-E3)

### Not tested

- KVM virtualization
- Onboard audio
- PCI
- PCIe
- PS/2 keyboard mouse (during payload, bootloader)
- Serial port
- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
- IOMMU

## Interesting facts

`lshw` output is different for BIOS and coreboot.

```shell
diff --side-by-side --ignore-all-space --strip-trailing-cr \
Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt \
Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt
```
306 changes: 306 additions & 0 deletions Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt
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my-desktop
description: Desktop Computer
product: GA-G41M-ES2L
vendor: GIGABYTE
version: 1.0
serial: 123456789
width: 64 bits
capabilities: smbios-3.0.0 dmi-3.0.0 smp vsyscall32
configuration: boot=normal chassis=desktop
*-core
description: Motherboard
product: GA-G41M-ES2L
vendor: GIGABYTE
physical id: 0
version: 1.0
serial: 123456789
*-firmware
description: BIOS
vendor: coreboot
physical id: 0
version: 4.13-1531-g2fae1c0494
date: 01/29/2021
size: 1MiB
capacity: 1MiB
capabilities: pci pcmcia upgrade bootselect acpi
*-cpu
description: CPU
product: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz
vendor: Intel Corp.
physical id: 4
bus info: cpu@0
version: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz
slot: CPU0
size: 2943MHz
capacity: 3GHz
width: 64 bits
capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority vpid dtherm cpufreq
*-cache
description: L2 cache
physical id: 7
slot: CACHE2
size: 6MiB
capacity: 6MiB
capabilities: internal unified
configuration: level=2
*-memory
description: System memory
physical id: 1
size: 2GiB
*-pci
description: Host bridge
product: 4 Series Chipset DRAM Controller
vendor: Intel Corporation
physical id: 100
bus info: pci@0000:00:00.0
version: 03
width: 32 bits
clock: 33MHz
*-pci:0
description: PCI bridge
product: 4 Series Chipset PCI Express Root Port
vendor: Intel Corporation
physical id: 1
bus info: pci@0000:00:01.0
version: 03
width: 32 bits
clock: 33MHz
capabilities: pci pm msi pciexpress normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:24
*-display:0
description: VGA compatible controller
product: 4 Series Chipset Integrated Graphics Controller
vendor: Intel Corporation
physical id: 2
bus info: pci@0000:00:02.0
version: 03
width: 64 bits
clock: 33MHz
capabilities: msi pm vga_controller bus_master cap_list rom
configuration: driver=i915 latency=0
resources: irq:16 memory:90000000-903fffff memory:80000000-8fffffff ioport:20a0(size=8) memory:c0000-dffff
*-display:1 UNCLAIMED
description: Display controller
product: 4 Series Chipset Integrated Graphics Controller
vendor: Intel Corporation
physical id: 2.1
bus info: pci@0000:00:02.1
version: 03
width: 64 bits
clock: 33MHz
capabilities: pm cap_list
configuration: latency=0
resources: memory:90400000-904fffff
*-multimedia
description: Audio device
product: NM10/ICH7 Family High Definition Audio Controller
vendor: Intel Corporation
physical id: 1b
bus info: pci@0000:00:1b.0
version: 01
width: 64 bits
clock: 33MHz
capabilities: pm msi pciexpress bus_master cap_list
configuration: driver=snd_hda_intel latency=0
resources: irq:28 memory:90700000-90703fff
*-pci:1
description: PCI bridge
product: NM10/ICH7 Family PCI Express Port 1
vendor: Intel Corporation
physical id: 1c
bus info: pci@0000:00:1c.0
version: 01
width: 32 bits
clock: 33MHz
capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:25
*-pci:2
description: PCI bridge
product: NM10/ICH7 Family PCI Express Port 2
vendor: Intel Corporation
physical id: 1c.1
bus info: pci@0000:00:1c.1
version: 01
width: 32 bits
clock: 33MHz
capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:26 ioport:1000(size=4096) memory:90600000-906fffff ioport:90500000(size=1048576)
*-network
description: Ethernet interface
product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
vendor: Realtek Semiconductor Co., Ltd.
physical id: 0
bus info: pci@0000:03:00.0
logical name: eth0
version: 02
serial: 6c:f0:49:a3:e3:d5
size: 1Gbit/s
capacity: 1Gbit/s
width: 64 bits
clock: 33MHz
capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation
configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=5.10.0-2-amd64 duplex=full ip=192.168.155.136 latency=0 link=yes multicast=yes port=MII speed=1Gbit/s
resources: irq:17 ioport:1000(size=256) memory:90510000-90510fff memory:90500000-9050ffff memory:90600000-9060ffff
*-usb:0
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #1
vendor: Intel Corporation
physical id: 1d
bus info: pci@0000:00:1d.0
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:23 ioport:2000(size=32)
*-usb:1
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #2
vendor: Intel Corporation
physical id: 1d.1
bus info: pci@0000:00:1d.1
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:19 ioport:2020(size=32)
*-usb:2
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #3
vendor: Intel Corporation
physical id: 1d.2
bus info: pci@0000:00:1d.2
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:18 ioport:2040(size=32)
*-usb:3
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #4
vendor: Intel Corporation
physical id: 1d.3
bus info: pci@0000:00:1d.3
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:16 ioport:2060(size=32)
*-usb:4
description: USB controller
product: NM10/ICH7 Family USB2 EHCI Controller
vendor: Intel Corporation
physical id: 1d.7
bus info: pci@0000:00:1d.7
version: 01
width: 32 bits
clock: 33MHz
capabilities: pm debug ehci bus_master cap_list
configuration: driver=ehci-pci latency=0
resources: irq:23 memory:90704000-907043ff
*-pci:3
description: PCI bridge
product: 82801 PCI Bridge
vendor: Intel Corporation
physical id: 1e
bus info: pci@0000:00:1e.0
version: e1
width: 32 bits
clock: 33MHz
capabilities: pci subtractive_decode bus_master cap_list
*-isa
description: ISA bridge
product: 82801GB/GR (ICH7 Family) LPC Interface Bridge
vendor: Intel Corporation
physical id: 1f
bus info: pci@0000:00:1f.0
version: 01
width: 32 bits
clock: 33MHz
capabilities: isa bus_master cap_list
configuration: driver=lpc_ich latency=0
resources: irq:0
*-ide:0
description: IDE interface
product: 82801G (ICH7 Family) IDE Controller
vendor: Intel Corporation
physical id: 1f.1
bus info: pci@0000:00:1f.1
version: 01
width: 32 bits
clock: 33MHz
capabilities: ide isa_compat_mode pci_native_mode bus_master
configuration: driver=ata_piix latency=0
resources: irq:18 ioport:1f0(size=8) ioport:3f6 ioport:170(size=8) ioport:376 ioport:2080(size=16)
*-ide:1
description: IDE interface
product: NM10/ICH7 Family SATA Controller [IDE mode]
vendor: Intel Corporation
physical id: 1f.2
bus info: pci@0000:00:1f.2
logical name: scsi2
version: 01
width: 32 bits
clock: 66MHz
capabilities: ide pm isa_compat_mode pci_native_mode bus_master cap_list emulated
configuration: driver=ata_piix latency=0
resources: irq:19 ioport:20b8(size=8) ioport:20d0(size=4) ioport:20c0(size=8) ioport:20d4(size=4) ioport:2090(size=16)
*-disk
description: ATA Disk
product: WDC WD5000BPVT-2
vendor: Western Digital
physical id: 0.0.0
bus info: scsi@2:0.0.0
logical name: /dev/sda
version: 1A03
serial: WD-WXD1E71MYND4
size: 465GiB (500GB)
capabilities: gpt-1.00 partitioned partitioned:gpt
configuration: ansiversion=5 guid=868a1c85-f309-4f3d-8282-6b5c4c373275 logicalsectorsize=512 sectorsize=4096
*-serial
description: SMBus
product: NM10/ICH7 Family SMBus Controller
vendor: Intel Corporation
physical id: 1f.3
bus info: pci@0000:00:1f.3
version: 01
width: 32 bits
clock: 33MHz
configuration: driver=i801_smbus latency=0
resources: irq:19 ioport:400(size=32)
*-pnp00:00
product: PnP device PNP0c02
physical id: 2
capabilities: pnp
configuration: driver=system
*-pnp00:01
product: PnP device PNP0103
physical id: 3
capabilities: pnp
configuration: driver=system
*-pnp00:02
product: PnP device PNP0c02
physical id: 5
capabilities: pnp
configuration: driver=system
*-pnp00:03
product: PnP device PNP0b00
physical id: 6
capabilities: pnp
configuration: driver=rtc_cmos
*-pnp00:04
product: PnP device PNP0303
physical id: 7
capabilities: pnp
configuration: driver=i8042 kbd
*-pnp00:05
product: PnP device PNP0f13
physical id: 8
capabilities: pnp
configuration: driver=i8042 aux
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my-desktop
description: Desktop Computer
product: G41M-ES2L
vendor: Gigabyte Technology Co., Ltd.
width: 64 bits
capabilities: smbios-2.4 dmi-2.4 smp vsyscall32
configuration: boot=normal chassis=desktop uuid=00000000-0000-0000-0000-6CF049A3E3D5
*-core
description: Motherboard
product: G41M-ES2L
vendor: Gigabyte Technology Co., Ltd.
physical id: 0
*-firmware
description: BIOS
vendor: Award Software International, Inc.
physical id: 0
version: F9
date: 06/21/2010
size: 128KiB
capacity: 1MiB
capabilities: pci pnp apm upgrade shadowing cdboot bootselect edd int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification
*-cpu
description: CPU
product: Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz
vendor: Intel Corp.
physical id: 4
bus info: cpu@0
version: Intel(R) Core(TM)2 Duo CPU
slot: Socket 775
size: 2631MHz
capacity: 4GHz
width: 64 bits
clock: 333MHz
capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority vpid dtherm cpufreq
*-cache:0
description: L1 cache
physical id: a
slot: Internal Cache
size: 64KiB
capacity: 64KiB
capabilities: synchronous internal write-back
configuration: level=1
*-cache:1
description: L2 cache
physical id: b
slot: External Cache
size: 6MiB
capabilities: synchronous internal write-back
configuration: level=2
*-memory
description: System Memory
physical id: 19
slot: System board or motherboard
size: 2GiB
*-bank:0
description: DIMM 800 MHz (1.2 ns)
physical id: 0
slot: A0
size: 1GiB
width: 64 bits
clock: 800MHz (1.2ns)
*-bank:1
description: DIMM [empty]
physical id: 1
slot: A1
*-bank:2
description: DIMM 800 MHz (1.2 ns)
physical id: 2
slot: A2
size: 1GiB
width: 64 bits
clock: 800MHz (1.2ns)
*-bank:3
description: DIMM [empty]
physical id: 3
slot: A3
*-pci
description: Host bridge
product: 4 Series Chipset DRAM Controller
vendor: Intel Corporation
physical id: 100
bus info: pci@0000:00:00.0
version: 03
width: 32 bits
clock: 33MHz
*-display
description: VGA compatible controller
product: 4 Series Chipset Integrated Graphics Controller
vendor: Intel Corporation
physical id: 2
bus info: pci@0000:00:02.0
version: 03
width: 64 bits
clock: 33MHz
capabilities: msi pm vga_controller bus_master cap_list rom
configuration: driver=i915 latency=0
resources: irq:16 memory:fd800000-fdbfffff memory:d0000000-dfffffff ioport:ff00(size=8) memory:c0000-dffff
*-multimedia
description: Audio device
product: NM10/ICH7 Family High Definition Audio Controller
vendor: Intel Corporation
physical id: 1b
bus info: pci@0000:00:1b.0
version: 01
width: 64 bits
clock: 33MHz
capabilities: pm msi pciexpress bus_master cap_list
configuration: driver=snd_hda_intel latency=0
resources: irq:27 memory:fdff8000-fdffbfff
*-pci:0
description: PCI bridge
product: NM10/ICH7 Family PCI Express Port 1
vendor: Intel Corporation
physical id: 1c
bus info: pci@0000:00:1c.0
version: 01
width: 32 bits
clock: 33MHz
capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:24 ioport:1000(size=4096) memory:7dd00000-7defffff ioport:80000000(size=2097152)
*-pci:1
description: PCI bridge
product: NM10/ICH7 Family PCI Express Port 2
vendor: Intel Corporation
physical id: 1c.1
bus info: pci@0000:00:1c.1
version: 01
width: 32 bits
clock: 33MHz
capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
configuration: driver=pcieport
resources: irq:25 ioport:d000(size=4096) memory:fdd00000-fddfffff ioport:fde00000(size=1048576)
*-network
description: Ethernet interface
product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
vendor: Realtek Semiconductor Co., Ltd.
physical id: 0
bus info: pci@0000:02:00.0
logical name: eth0
version: 02
serial: 6c:f0:49:a3:e3:d5
size: 1Gbit/s
capacity: 1Gbit/s
width: 64 bits
clock: 33MHz
capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation
configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=5.10.0-2-amd64 duplex=full ip=192.168.155.137 latency=0 link=yes multicast=yes port=MII speed=1Gbit/s
resources: irq:17 ioport:de00(size=256) memory:fdeff000-fdefffff memory:fdee0000-fdeeffff memory:fdd00000-fdd0ffff
*-usb:0
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #1
vendor: Intel Corporation
physical id: 1d
bus info: pci@0000:00:1d.0
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:23 ioport:fe00(size=32)
*-usb:1
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #2
vendor: Intel Corporation
physical id: 1d.1
bus info: pci@0000:00:1d.1
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:19 ioport:fd00(size=32)
*-usb:2
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #3
vendor: Intel Corporation
physical id: 1d.2
bus info: pci@0000:00:1d.2
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:18 ioport:fc00(size=32)
*-usb:3
description: USB controller
product: NM10/ICH7 Family USB UHCI Controller #4
vendor: Intel Corporation
physical id: 1d.3
bus info: pci@0000:00:1d.3
version: 01
width: 32 bits
clock: 33MHz
capabilities: uhci bus_master
configuration: driver=uhci_hcd latency=0
resources: irq:16 ioport:fb00(size=32)
*-usb:4
description: USB controller
product: NM10/ICH7 Family USB2 EHCI Controller
vendor: Intel Corporation
physical id: 1d.7
bus info: pci@0000:00:1d.7
version: 01
width: 32 bits
clock: 33MHz
capabilities: pm ehci bus_master cap_list
configuration: driver=ehci-pci latency=0
resources: irq:23 memory:fdfff000-fdfff3ff
*-pci:2
description: PCI bridge
product: 82801 PCI Bridge
vendor: Intel Corporation
physical id: 1e
bus info: pci@0000:00:1e.0
version: e1
width: 32 bits
clock: 33MHz
capabilities: pci subtractive_decode cap_list
*-isa
description: ISA bridge
product: 82801GB/GR (ICH7 Family) LPC Interface Bridge
vendor: Intel Corporation
physical id: 1f
bus info: pci@0000:00:1f.0
version: 01
width: 32 bits
clock: 33MHz
capabilities: isa bus_master cap_list
configuration: driver=lpc_ich latency=0
resources: irq:0
*-ide:0
description: IDE interface
product: 82801G (ICH7 Family) IDE Controller
vendor: Intel Corporation
physical id: 1f.1
bus info: pci@0000:00:1f.1
version: 01
width: 32 bits
clock: 33MHz
capabilities: ide isa_compat_mode pci_native_mode bus_master
configuration: driver=ata_piix latency=0
resources: irq:18 ioport:1f0(size=8) ioport:3f6 ioport:170(size=8) ioport:376 ioport:f800(size=16)
*-ide:1
description: IDE interface
product: NM10/ICH7 Family SATA Controller [IDE mode]
vendor: Intel Corporation
physical id: 1f.2
bus info: pci@0000:00:1f.2
logical name: scsi2
version: 01
width: 32 bits
clock: 66MHz
capabilities: ide pm isa_compat_mode pci_native_mode bus_master cap_list emulated
configuration: driver=ata_piix latency=0
resources: irq:19 ioport:f700(size=8) ioport:f600(size=4) ioport:f500(size=8) ioport:f400(size=4) ioport:f300(size=16)
*-disk
description: ATA Disk
product: WDC WD5000BPVT-2
vendor: Western Digital
physical id: 0.0.0
bus info: scsi@2:0.0.0
logical name: /dev/sda
version: 1A03
serial: WD-WXD1E71MYND4
size: 465GiB (500GB)
capabilities: gpt-1.00 partitioned partitioned:gpt
configuration: ansiversion=5 guid=868a1c85-f309-4f3d-8282-6b5c4c373275 logicalsectorsize=512 sectorsize=4096
*-serial
description: SMBus
product: NM10/ICH7 Family SMBus Controller
vendor: Intel Corporation
physical id: 1f.3
bus info: pci@0000:00:1f.3
version: 01
width: 32 bits
clock: 33MHz
configuration: driver=i801_smbus latency=0
resources: irq:19 ioport:500(size=32)
*-pnp00:00
product: PnP device PNP0c02
physical id: 1
capabilities: pnp
configuration: driver=system
*-pnp00:01
product: PnP device PNP0b00
physical id: 2
capabilities: pnp
configuration: driver=rtc_cmos
*-pnp00:02
product: PnP device PNP0c02
physical id: 3
capabilities: pnp
configuration: driver=system
*-pnp00:03
product: PnP device PNP0c02
physical id: 5
capabilities: pnp
configuration: driver=system
*-pnp00:04
product: PnP device PNP0c01
physical id: 6
capabilities: pnp
configuration: driver=system
2 changes: 1 addition & 1 deletion Documentation/mainboard/hp/8760w.md
View file
Expand Up @@ -36,7 +36,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.

## Flashing instructions

HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the
HP EliteBook 8760w has an 8 MiB SOIC-8 flash chip on the bottom of the
mainboard. You just need to remove the service cover, and use an SOIC-8
clip to read and flash the chip.

Expand Down
2 changes: 2 additions & 0 deletions Documentation/mainboard/index.md
View file
Expand Up @@ -56,6 +56,7 @@ The boards in this section are not real mainboards, but emulators.

## Gigabyte

- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md)
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)

## HP
Expand Down Expand Up @@ -176,6 +177,7 @@ The boards in this section are not real mainboards, but emulators.
## System76

- [Lemur Pro](system76/lemp9.md)
- [Oryx Pro 5](system76/oryp5.md)

## Texas Instruments

Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/intel/kblrvp11.md
View file
Expand Up @@ -60,7 +60,7 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
2. Make sure power supply is disconnected from board.
3. Connect Dediprog SF600 to header at J7H1.
4. Ensure that "currently working on" is in "application memory chip 1"
5. Go to "file" and select the .rom file (16 MB) to program chip1.
5. Go to "file" and select the .rom file (16 MiB) to program chip1.
6. Execute the batch operation to erase and program the chip.

## Technology
Expand Down
18 changes: 10 additions & 8 deletions Documentation/mainboard/lenovo/montevina_series.md
View file
Expand Up @@ -53,7 +53,7 @@ the `new_layout.txt` file:

```eval_rst
+---------------------------+---------------------------+---------------------------+
| 4 MB chip | 8 MB chip | 16 MB chip |
| 4 MiB chip | 8 MiB chip | 16 MiB chip |
+===========================+===========================+===========================+
| .. code-block:: none | .. code-block:: none | .. code-block:: none |
| | | |
Expand Down Expand Up @@ -97,12 +97,12 @@ $ cd util/bincfg
$ make
```

If your flash is not 8 MB, you need to change values of `flcomp_density1` and
If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
`flreg1_limit` in the `ifd-x200.set` file according to following table:

```eval_rst
+-----------------+-------+-------+--------+
| | 4 MB | 8 MB | 16 MB |
| | 4 MiB | 8 MiB | 16 MiB |
+=================+=======+=======+========+
| flcomp_density1 | 0x3 | 0x4 | 0x5 |
+-----------------+-------+-------+--------+
Expand All @@ -112,9 +112,11 @@ If your flash is not 8 MB, you need to change values of `flcomp_density1` and

Then create the flash descriptor:
```console
$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin
$ make gen-ifd-x200
```

It will be saved to the `flashregion_0_fd.bin` file.

#### Configuring coreboot

Now configure coreboot. You need to select correct chip size and specify paths
Expand All @@ -123,11 +125,11 @@ to flash descriptor and gbe dump.
```
Mainboard --->
ROM chip size (8192 KB (8 MB)) # According to your chip
(0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip
(0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MiB chip / 0x1ffd000 for 16 MiB chip
Chipset --->
[*] Add Intel descriptor.bin file
# Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin
# Note: if you used bincfg, specify path to generated util/bincfg/flashregion_0_fd.bin
(/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file
[*] Add gigabit ethernet configuration
Expand All @@ -142,7 +144,7 @@ The flash layouts of the OEM firmware are as follows:

```eval_rst
+---------------------------------+---------------------------------+
| 4 MB chip | 8 MB chip |
| 4 MiB chip | 8 MiB chip |
+=================================+=================================+
| .. code-block:: none | .. code-block:: none |
| | |
Expand All @@ -159,6 +161,6 @@ The flash layouts of the OEM firmware are as follows:
On each boot of vendor BIOS `ec` area in flash is checked for having firmware
there, and if there is one, it proceedes to update firmware on H8S/2116 (when
both external power and main battery are attached). Once update is performed,
first 64 KB of `ec` area is erased. Visit
first 64 KiB of `ec` area is erased. Visit
[thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn
more about how to extract EC firmware from vendor updates.
8 changes: 4 additions & 4 deletions Documentation/mainboard/lenovo/t440p.md
View file
Expand Up @@ -8,15 +8,15 @@ Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).

## Flashing instructions

T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash
T440p has two flash chips, an 8 MiB W25Q64FV and a 4 MiB W25Q32FV. To flash
coreboot, you just need to remove the big door according to the T440
[Hardware Maintenance Manual] and flash the 4MB chip.
[Hardware Maintenance Manual] and flash the 4 MiB chip.

![T440p flash chip](t440p_flash_chip.jpg)

To access the 8MB chip, you need to remove the base cover.
To access the 8 MiB chip, you need to remove the base cover.

![T440p 8MB flash chip](t440p_all_flash_chips.jpg)
![T440p 8 MiB flash chip](t440p_all_flash_chips.jpg)

The flash layout of the OEM firmware is as follows:

Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/msi/ms7707/ms7707.md
View file
Expand Up @@ -2,7 +2,7 @@

* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555)
* SandyBridge Intel P67 (BD82x6x)
* Winbond 25Q32BV (4MB)
* Winbond 25Q32BV (4 MiB)
* Fintek F71808A SuperIO
* Intel 82579V Gigabit
* NEC uPD720200 USB 3.0 Host Controller
Expand Down
2 changes: 1 addition & 1 deletion Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
View file
Expand Up @@ -18,7 +18,7 @@ Controller etc.
## De-blobbing

- [Intel FSP2.0] can not be removed as long as there is no free replacement
- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space)
- Intel ME can be cleaned using me_cleaner (~4.5 MiB more free space)
- Intel Ethernet Controller Firmware can be removed when it's extended functionality is not
needed. For more details refer to the respective datasheet (e.g 333016-008 for I210).
- Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC]
Expand Down
71 changes: 71 additions & 0 deletions Documentation/mainboard/system76/oryp5.md
View file
@@ -0,0 +1,71 @@
# System76 Oryx Pro 5 (oryp5)

## Specs

- CPU
- Intel Core i7-8750H
- Intel Core i7-9750H
- EC
- ITE8587E running https://github.com/system76/ec
- Graphics
- Intel UHD Graphics 630
- NVIDIA GeForce RTX 2080/2070/2060
- eDP 16.1" or 17.3" 1920x1080 @ 144 Hz LCD
- HDMI, Mini DisplayPort 1.3, and DisplayPort 1.3 over USB-C
- Memory
- Channel 0: 8-GB/16-GB/32-GB DDR4 SO-DIMM
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
- Networking
- Gigabit Ethernet
- Intel Dual Band Wireless-AC 9560 Wireless LAN (802.11ac) + Bluetooth
- Power
- 180W (19.5V, 9.23A) AC adapter
- 62Wh 4-cell battery
- Sound
- Realtek ALC1220 codec
- TAS5825MRHBR smart AMP
- Internal speakers and microphone
- Combined headphone and microphone 3.5mm jack
- Combined microphone and S/PDIF 3.5mm jack
- HDMI, Mini DisplayPort, USB-C DP audio
- Storage
- M.2 PCIe/SATA SSD1
- M.2 PCIe/SATA SSD2
- 2.5" SATA HDD/SSD
- RTS5250 SD card reader
- USB
- 2x USB 3.1 Gen2 Type-C
- 2x USB 3.1 Gen1 Type-A

## Building coreboot

```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.system76_oryp5
make
```

## Flashing coreboot

```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25Q127C/GD25Q128C |
+---------------------+---------------------+
| Size | 16 MiB |
+---------------------+---------------------+
| Package | SOIC-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```

External flashing via ISP requires removing the board from the chassis.
The IC is located under the touchpad.
8 changes: 4 additions & 4 deletions Documentation/mainboard/up/squared/index.md
View file
Expand Up @@ -76,15 +76,15 @@ firmware_vendor.rom

```bash
[upsquared]$ mkdir extracted && cd extracted
[extracted]$ ifdtool -x ../firmware_vendor.rom
[extracted]$ ifdtool -x ../firmware_vendor.rom
File ../firmware_vendor.rom is 16777216 bytes
Peculiar firmware descriptor, assuming Ibex Peak compatibility.
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
Flash Region 1 (BIOS): 00001000 - 00efefff
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
Flash Region 1 (BIOS): 00001000 - 00efefff
Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
Flash Region 5 (Reserved): 00eff000 - 00ffefff
Flash Region 5 (Reserved): 00eff000 - 00ffefff
Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
Expand Down
4 changes: 2 additions & 2 deletions Documentation/security/vboot/index.md
View file
Expand Up @@ -188,12 +188,12 @@ In addition to adding the coreboot files into the read-only region,
enabling vboot causes the build script to add the read/write files into
coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.

**RO_REGION_ONLY**
**RO_REGION_ONLY**

The files added to this list will only be placed in the read-only region and
not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.

**VBOOT_ENABLE_CBFS_FALLBACK**
**VBOOT_ENABLE_CBFS_FALLBACK**

Normally coreboot will use the active read/write coreboot file system for all
of it's file access when vboot is active and is not in recovery mode.
Expand Down
47 changes: 37 additions & 10 deletions Documentation/util.md
View file
Expand Up @@ -2,13 +2,16 @@

## List of utils

_Scripts and programs found in the `./util` directory_
_Scripts and programs found in the coreboot `./util` directory_
* __abuild__ - coreboot autobuild script builds coreboot images for all
available targets. `bash`
* __acpi__ - Walk through all ACPI tables with their addresses. `bash`
* __amdfwtool__ - Create AMD Firmware combination `C`
* __amdtools__ - A set of tools to compare extended) K8 memory
settings. `Perl`
* __apcb__ - AMD PSP Control Block tools
* _apcb_edit.py_ - This tool allows patching an existing APCB
binary with specific SPDs and GPIO selection pins. `Python3`
* __archive__ - Concatenate files and create an archive `C`
* __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
platforms `Go`
Expand All @@ -20,7 +23,8 @@ status repository `Bash` `Go`
* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
file `Python`
* __cbfstool__
* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file `C`
* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file
`C`
* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
* _rmodtool_ - Creates rmodules `C`
* _ifwitool_ - For manipulating IFWI `C`
Expand All @@ -37,18 +41,18 @@ _coreboot.org-status_ and _docs.coreboot.org_
* __ectool__ - Dumps the RAM of a laptop's Embedded/Environmental
Controller (EC). `C`
* __exynos__ - Computes and fills Exynos ROM checksum (for BL1 or BL2).
`Python2`
`Python3`
* __find_usbdebug__ - Help find USB debug ports
* __futility__ - Firmware utility for signing ChromeOS images `Make`
* __fuzz-tests__ - Create test cases that crash the jpeg code. `C`
* __genbuild_h__ - Generate build system definitions `Shell`
* __genprof__ - Format function tracing logs `Bash` `C`
* __gitconfig__ - Initialize git repository submodules install git
hooks `Bash`
* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information
`C`
* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware
Descriptor information `C`
* __intelmetool__ - Dump interesting things about Management Engine
even if hidden `C`
* __intelp2m__ - Intel Pad to Macro (intelp2m) converter 'Go'
* __inteltool__ - Provides information about the Intel CPU/chipset
hardware configuration (register contents, MSRs, etc). `C`
* __intelvbttool__ - Parse VBT from VGA BIOS `C`
Expand All @@ -65,12 +69,14 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
embedded controller and insert them to the firmware image. `C`
* __kconfig__ - Build system `Make`
* __lint__ - Source linter and linting rules `Shell`
* __mainboard__ - mainboard specific scripts
* _google_ - Directory for google mainboard specific scripts
* __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C`
* __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
partial deblobbing of Intel ME/TXE firmware images `Python`
* __mma__ - Memory Margin Analysis automation tests `Bash`
* __msrtool__ - Dumps chipset-specific MSR registers. `C`
* __mtkheader__ - Generate MediaTek bootload header. `Python2`
* __mtkheader__ - Generate MediaTek bootload header. `Python3`
* __nvidia__ - nvidia blob parsers
* __nvramtool__ - Reads and writes coreboot parameters and displaying
information from the coreboot table in CMOS/NVRAM. `C`
Expand All @@ -80,6 +86,8 @@ information from the coreboot table in CMOS/NVRAM. `C`
ThinkPads. PMH7 is used for switching on and off the power of some
devices on the board such as dGPU. `C`
* __post__ - Userspace utility that can be used to test POST cards. `C`
* __qemu__ - Makefile & comprehensive default config for QEMU Q35
emulation
* __qualcomm__ - CMM script to debug Qualcomm coreboot environments.
`CMM`
* __release__ - Generate coreboot release `Bash`
Expand All @@ -88,7 +96,7 @@ devices on the board such as dGPU. `C`
can be passed to SPIKE, the RISC-V reference emulator.`Bash`
* _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for
SiFive's bootrom. `Python3`
* __rockchip__ - Generate Rockchip idblock bootloader. `Python2`
* __rockchip__ - Generate Rockchip idblock bootloader. `Python3`
* __sconfig__ - coreboot device tree compiler `Lex` `Yacc`
* __scripts__
* _config_ - Manipulate options in a .config file from the
Expand Down Expand Up @@ -117,11 +125,19 @@ file `Perl`
* __spdtool__ - Dumps SPD ROMs from a given blob to separate files
using known patterns and reserved bits. Useful for analysing firmware
that holds SPDs on boards that have soldered down DRAM. `python`
* __spd_tools__ - Tools for generating SPD files for DDR4 memory used
in platforms with memory down configuration.
* _gen_spd.go_ - Generates de-duplicated SPD files using a
global memory part list provided by the mainboard in JSON format. `Go`
* _gen_part_id.go_ - Allocates DRAM strap IDs for different
DDR4 memory parts used by the board. `Go`
* __spkmodem_recv__ - Decode spkmodem signals `C`
* __superiotool__ - A user-space utility to detect Super I/O of a
mainboard and provide detailed information about the register contents
of the Super I/O. `C`
* __smcbiosinfo__ - Generates SMC biosinfo for BMC BIOS updates `C`
* __supermicro__ - Tools for supermicro platforms
* _smcbiosinfo_ - Generates SMC biosinfo for BMC BIOS updates
`C`
* __testing__ - coreboot test targets `Make`
* __uio_usbdebug__ - Debug coreboot's usbdebug driver inside a running
operating system (only Linux at this time). `C`
Expand All @@ -135,6 +151,17 @@ the documentation `Bash`
* __xcompile__ - Cross compile setup `Bash`


## In depth documentation
## In depth documentation

* [ifdtool](ifdtool/index.md)

## Generated documentation

**Please do not edit the markdown file in the documentation directory
*directly.**

This file was generated by running util_readme.sh. Please make sure it
is rerun when new tools are added or when documentation is updated.

To update, edit the markdown files in the util directory, then
re-generate this file by running `util/util_readme/util_readme.sh`
20 changes: 10 additions & 10 deletions LICENSES/Apache-2.0.txt
View file
Expand Up @@ -7,17 +7,17 @@ AND DISTRIBUTION

1. Definitions.



"License" shall mean the terms and conditions for use, reproduction, and distribution
as defined by Sections 1 through 9 of this document.



"Licensor" shall mean the copyright owner or entity authorized by the copyright
owner that is granting the License.



"Legal Entity" shall mean the union of the acting entity and all other entities
that control, are controlled by, or are under common control with that entity.
Expand All @@ -26,31 +26,31 @@ or indirect, to cause the direction or management of such entity, whether
by contract or otherwise, or (ii) ownership of fifty percent (50%) or more
of the outstanding shares, or (iii) beneficial ownership of such entity.



"You" (or "Your") shall mean an individual or Legal Entity exercising permissions
granted by this License.



"Source" form shall mean the preferred form for making modifications, including
but not limited to software source code, documentation source, and configuration
files.



"Object" form shall mean any form resulting from mechanical transformation
or translation of a Source form, including but not limited to compiled object
code, generated documentation, and conversions to other media types.



"Work" shall mean the work of authorship, whether in Source or Object form,
made available under the License, as indicated by a copyright notice that
is included in or attached to the work (an example is provided in the Appendix
below).



"Derivative Works" shall mean any work, whether in Source or Object form,
that is based on (or derived from) the Work and for which the editorial revisions,
Expand All @@ -59,7 +59,7 @@ original work of authorship. For the purposes of this License, Derivative
Works shall not include works that remain separable from, or merely link (or
bind by name) to the interfaces of, the Work and Derivative Works thereof.



"Contribution" shall mean any work of authorship, including the original version
of the Work and any modifications or additions to that Work or Derivative
Expand All @@ -74,7 +74,7 @@ for the purpose of discussing and improving the Work, but excluding communicatio
that is conspicuously marked or otherwise designated in writing by the copyright
owner as "Not a Contribution."



"Contributor" shall mean Licensor and any individual or Legal Entity on behalf
of whom a Contribution has been received by Licensor and subsequently incorporated
Expand Down
2 changes: 1 addition & 1 deletion LICENSES/GPL-2.0-only.txt
View file
Expand Up @@ -2,7 +2,7 @@ GNU GENERAL PUBLIC LICENSE

Version 2, June 1991

Copyright (C) 1989, 1991 Free Software Foundation, Inc.
Copyright (C) 1989, 1991 Free Software Foundation, Inc.

51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA

Expand Down
2 changes: 1 addition & 1 deletion LICENSES/GPL-2.0-or-later.txt
View file
Expand Up @@ -2,7 +2,7 @@ GNU GENERAL PUBLIC LICENSE

Version 2, June 1991

Copyright (C) 1989, 1991 Free Software Foundation, Inc.
Copyright (C) 1989, 1991 Free Software Foundation, Inc.

51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA

Expand Down
3 changes: 3 additions & 0 deletions MAINTAINERS
View file
Expand Up @@ -563,20 +563,23 @@ AMD Cezanne
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
S: Maintained
F: src/soc/amd/cezanne/

AMD common SoC code
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
S: Maintained
F: src/soc/amd/common/

AMD Picasso
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
S: Maintained
F: src/soc/amd/picasso/
F: src/vendorcode/amd/fsp/picasso/
Expand Down
9 changes: 5 additions & 4 deletions Makefile.inc
View file
Expand Up @@ -259,14 +259,14 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
# Redundant offset remarks are not useful in any way and are masking useful
# ones that might indicate an issue so it is better to hide them.
REDUNDANT_OFFSET_REMARK = 2158
# Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code.
# See cb:38803 & cb:38802
# Ignore _HID & _ADR coexisting in Intel Lynxpoint ASL code.
# See cb:38802
# "Multiple types (Device object requires either a _HID or _ADR, but not both)"
MULTIPLE_TYPES_WARNING = 3073

IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)

ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y)
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING)
endif

Expand Down Expand Up @@ -426,7 +426,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11
CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla
CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else
CFLAGS_common += -Wdangling-else
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
ifeq ($(CONFIG_COMPILER_GCC),y)
Expand All @@ -435,6 +435,7 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned
CFLAGS_common += -fconserve-stack
CFLAGS_common += -Wnull-dereference -Wreturn-type
CFLAGS_common += -Wlogical-op -Wduplicated-cond
# cf. commit f69a99db (coreboot: x86: enable gc-sections)
CFLAGS_common += -Wno-unused-but-set-variable
endif
Expand Down
2 changes: 2 additions & 0 deletions configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100
View file
Expand Up @@ -3,6 +3,7 @@
# the future, then this config can be split into several smaller chunks.
# Exercises, among other things:
# + Code coverage
# + ASAN
# + UBSAN
# + Debug options
# + SMMSTORE
Expand All @@ -11,6 +12,7 @@
# + EM100 support
# + SMM module loader V2
CONFIG_COVERAGE=y
CONFIG_ASAN=y
CONFIG_UBSAN=y
CONFIG_VENDOR_ASROCK=y
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
Expand Down
1 change: 0 additions & 1 deletion configs/config.facebook_fbg1701.mboot_vboot
View file
@@ -1,5 +1,4 @@
CONFIG_VENDOR_FACEBOOK=y
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000
CONFIG_ONBOARD_SAMSUNG_MEM=y
CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
Expand Down
13 changes: 13 additions & 0 deletions configs/config.gigabyte_ga-g41m-es2l
View file
@@ -0,0 +1,13 @@
CONFIG_VENDOR_GIGABYTE=y
CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
CONFIG_MAINBOARD_VERSION="1.1"
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_PAYLOAD_CONFIGFILE=".config_seabios"
CONFIG_USE_OPTION_TABLE=y
CONFIG_USE_BLOBS=y
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y

# It is better to take this unique value from old CMOS.
# Default MAC-address is 00:e0:4c:00:c0:b0
# CONFIG_REALTEK_8168_MACADDRESS="6c:f0:49:xx:xx:xx"
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.3"
CONFIG_LOCALVERSION="v4.13.0.4"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_NO_GFX_INIT=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.3"
CONFIG_LOCALVERSION="v4.13.0.4"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.3"
CONFIG_LOCALVERSION="v4.13.0.4"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.3"
CONFIG_LOCALVERSION="v4.13.0.4"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.3"
CONFIG_LOCALVERSION="v4.13.0.4"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.3"
CONFIG_LOCALVERSION="v4.13.0.4"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU6=y
Expand Down
6 changes: 6 additions & 0 deletions configs/config.system76_oryp5
View file
@@ -0,0 +1,6 @@
CONFIG_VENDOR_SYSTEM76=y
CONFIG_BOARD_SYSTEM76_ORYP5=y
CONFIG_PAYLOAD_TIANOCORE=y
CONFIG_POST_IO=n
CONFIG_RUN_FSP_GOP=y
CONFIG_SMMSTORE=y
13 changes: 9 additions & 4 deletions payloads/Makefile.inc
View file
Expand Up @@ -10,7 +10,7 @@ img/coreinfo-type := payload
img/coreinfo-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)

cbfs-files-$(CONFIG_NVRAMCUI_SECONDARY_PAYLOAD) += img/nvramcui
img/nvramcui-file := payloads/nvramcui/nvramcui.elf
img/nvramcui-file := payloads/nvramcui/build/nvramcui.elf
img/nvramcui-type := payload
img/nvramcui-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)

Expand All @@ -30,10 +30,14 @@ payloads/external/GRUB2 \
payloads/external/LinuxBoot \
payloads/external/Yabits \

payloads/coreinfo/build/coreinfo.elf coreinfo:
force-payload:

payloads/coreinfo/build/coreinfo.elf coreinfo: export CCACHE := $(CCACHE)
payloads/coreinfo/build/coreinfo.elf coreinfo: force-payload
$(MAKE) -C payloads/coreinfo defaultbuild

payloads/nvramcui/nvramcui.elf nvramcui:
payloads/nvramcui/build/nvramcui.elf nvramcui: export CCACHE := $(CCACHE)
payloads/nvramcui/build/nvramcui.elf nvramcui: force-payload
$(MAKE) -C payloads/nvramcui

clean-payloads:
Expand All @@ -45,4 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )

.PHONY: clean-payloads distclean-payloads print-repo-info-payloads nvramcui coreinfo
.PHONY: force-payload coreinfo nvramcui
.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
4 changes: 2 additions & 2 deletions payloads/coreinfo/.gitignore
View file
@@ -1,2 +1,2 @@
lpbuild/
lp.config*
libpayload/
.lp.config*
123 changes: 35 additions & 88 deletions payloads/coreinfo/Makefile
View file
@@ -1,76 +1,53 @@
## SPDX-License-Identifier: GPL-2.0-only

unexport $(COREBOOT_EXPORTS)

src := $(CURDIR)
obj := build

srctree := $(src)
srck := $(src)/../../util/kconfig
coreinfo_obj := $(src)/build
objk := $(src)/build/util/kconfig

LIBPAYLOAD_DEFCONFIG ?= $(src)/../libpayload/configs/defconfig-tinycurses

PAYLOAD_DEPS := $(obj)/config.h

OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \
nvram_module.o bootlog_module.o ramdump_module.o \
multiboot_module.o cbfs_module.o timestamps_module.o coreinfo.o
OBJS = $(patsubst %,$(obj)/%,$(OBJECTS))
TARGET = $(obj)/coreinfo.elf

ARCH := x86_32

all: real-all

include ../libpayload/Makefile.payload

ifeq ($(filter %clean,$(MAKECMDGOALS)),)
export KERNELVERSION := 0.1.0
export KCONFIG_AUTOHEADER := $(coreinfo_obj)/config.h
export KCONFIG_AUTOCONFIG := $(coreinfo_obj)/auto.conf
export KCONFIG_DEPENDENCIES := $(coreinfo_obj)/auto.conf.cmd
export KCONFIG_SPLITCONFIG := $(coreinfo_obj)/config
export KCONFIG_TRISTATE := $(coreinfo_obj)/tristate.conf
export KCONFIG_CONFIG := $(CURDIR)/.config
export KCONFIG_NEGATIVES := 1
export Kconfig := Kconfig

export V := $(V)
export KERNELVERSION := 0.1.0
export KCONFIG_AUTOHEADER := $(obj)/config.h
export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
export KCONFIG_SPLITCONFIG := $(obj)/config
export KCONFIG_TRISTATE := $(obj)/tristate.conf
export KCONFIG_CONFIG := $(CURDIR)/.config
export KCONFIG_NEGATIVES := 1
export Kconfig := Kconfig

CONFIG_SHELL := sh
KBUILD_DEFCONFIG := configs/defconfig
UNAME_RELEASE := $(shell uname -r)
HAVE_DOTCONFIG := $(wildcard .config)
MAKEFLAGS += -rR --no-print-directory

# Make is silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)
.SILENT:
endif

HOSTCC ?= gcc
HOSTCXX ?= g++
HOSTCFLAGS := -I$(srck) -I$(objk)
HOSTCXXFLAGS := -I$(srck) -I$(objk)

LIBPAYLOAD_PATH := $(realpath ../libpayload)
LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload
HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a)
LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses
OBJCOPY ?= objcopy

INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_OBJ)/include/kconfig.h -I$(src)/../../src/commonlib/include
OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \
nvram_module.o bootlog_module.o ramdump_module.o \
multiboot_module.o cbfs_module.o timestamps_module.o coreinfo.o
OBJS = $(patsubst %,$(coreinfo_obj)/%,$(OBJECTS))
TARGET = $(coreinfo_obj)/coreinfo.elf

all: real-all

# in addition to the dependency below, create the file if it doesn't exist
# to silence warnings about a file that would be generated anyway.
$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile)))
.xcompile: ../../util/xcompile/xcompile
$< $(XGCCPATH) > $@.tmp
\mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@

CONFIG_COMPILER_GCC := y
ARCH-y := x86_32

include .xcompile

CC := $(CC_$(ARCH-y))
AS := $(AS_$(ARCH-y))
OBJCOPY := $(OBJCOPY_$(ARCH-y))

LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc
LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas

CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror
CFLAGS += -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES)
CFLAGS += -I$(obj) -I../../src/commonlib/include

ifneq ($(strip $(HAVE_DOTCONFIG)),)
include $(src)/.config
Expand All @@ -80,21 +57,6 @@ ifeq ($(CONFIG_LTO),y)
CFLAGS += -flto
endif

$(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload
printf " LPCC $(subst $(CURDIR)/,,$(@)) (LINK)\n"
$(LPCC) $(CFLAGS) -o $@ $(OBJS)
$(OBJCOPY) --only-keep-debug $@ $(TARGET).debug
$(OBJCOPY) --strip-debug $@
$(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@

$(coreinfo_obj)/%.S.o: $(src)/%.S libpayload
printf " LPAS $(subst $(CURDIR)/,,$(@))\n"
$(LPAS) -o $@ $<

$(coreinfo_obj)/%.o: $(src)/%.c libpayload
printf " LPCC $(subst $(CURDIR)/,,$(@))\n"
$(LPCC) $(CFLAGS) -c -o $@ $<

else
real-all: config
endif
Expand All @@ -103,34 +65,19 @@ defaultbuild:
$(MAKE) olddefconfig
$(MAKE) all

ifneq ($(strip $(HAVE_LIBPAYLOAD)),)
libpayload:
printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n"
else
LPOPTS=obj="$(CURDIR)/lpbuild" DOTCONFIG="$(CURDIR)/lp.config"
libpayload:
printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n"
$(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) distclean coreinfo_obj=$(coreinfo_obj)/libptmp
$(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG)
$(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) install DESTDIR=$(coreinfo_obj)
endif

$(coreinfo_obj)/config.h:
$(obj)/config.h:
$(MAKE) oldconfig

$(shell mkdir -p $(coreinfo_obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))
$(shell mkdir -p $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))

include $(srck)/Makefile

.PHONY: $(PHONY) prepare
.PHONY: $(PHONY) prepare all real-all defaultbuild

else

clean:
rm -rf build lpbuild .xcompile

distclean: clean
rm -f .config* lp.config*
rm -f .config*

.PHONY: clean distclean
.PHONY: distclean
endif
2 changes: 1 addition & 1 deletion payloads/coreinfo/README
View file
Expand Up @@ -22,5 +22,5 @@ Then you can build coreinfo now:
$ cd coreinfo

$ make menuconfig

$ make
2 changes: 1 addition & 1 deletion payloads/external/FILO/Makefile
View file
Expand Up @@ -44,7 +44,7 @@ libpayload: checkout
$(MAKE) && $(MAKE) DESTDIR=../external/FILO/filo/build install

clean:
test -d filo && $(MAKE) -C filo clean || exit 0
test -d filo && $(MAKE) -C filo clean LIBCONFIG_PATH=../../../libpayload || exit 0

distclean:
rm -rf filo
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/U-Boot/Kconfig
View file
@@ -1,6 +1,6 @@
if PAYLOAD_UBOOT

config PAYLOAD_SPECIFIC_OPTIONS # dummy
config PAYLOAD_SPECIFIC_OPTIONS
def_bool y
select PAYLOAD_IS_FLAT_BINARY

Expand Down
6 changes: 3 additions & 3 deletions payloads/external/tint/Makefile
View file
@@ -1,5 +1,5 @@
project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.04+nmu1.tar.gz
archive_name=tint_0.04+nmu1.tar.gz
project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.05.tar.xz
archive_name=tint_0.05.tar.xz

unexport KCONFIG_AUTOHEADER
unexport KCONFIG_AUTOCONFIG
Expand All @@ -26,7 +26,7 @@ download:
test -d tint || { wget $(project_url); \
tar -xvf $(archive_name); \
rm $(archive_name); \
mv tint-0.04+nmu1 tint; }
mv tint-0.05 tint; }

clean:
test -d tint && $(MAKE) -C tint clean || exit 0
Expand Down
90 changes: 44 additions & 46 deletions payloads/external/tint/libpayload_tint.patch
View file
@@ -1,6 +1,6 @@
diff -rupN tint-0.04+nmu1/config.h tint/config.h
--- tint-0.04+nmu1/config.h 2001-12-08 00:03:24.000000000 +0100
+++ tint/config.h 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/config.h tint/config.h
--- tint-0.05/config.h 2001-12-08 00:03:24.000000000 +0100
+++ tint/config.h 2021-02-09 08:00:00.000000000 +0200
@@ -29,7 +29,15 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
Expand All @@ -17,9 +17,9 @@ diff -rupN tint-0.04+nmu1/config.h tint/config.h
+#endif

#endif /* #ifndef CONFIG_H */
diff -rupN tint-0.04+nmu1/engine.c tint/engine.c
--- tint-0.04+nmu1/engine.c 2005-07-17 13:26:22.000000000 +0200
+++ tint/engine.c 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/engine.c tint/engine.c
--- tint-0.05/engine.c 2005-07-17 13:26:22.000000000 +0200
+++ tint/engine.c 2021-02-09 08:00:00.000000000 +0200
@@ -27,10 +27,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
Expand All @@ -35,21 +35,21 @@ diff -rupN tint-0.04+nmu1/engine.c tint/engine.c
#include "utils.h"
#include "io.h"
#include "engine.h"
diff -rupN tint-0.04+nmu1/engine.h tint/engine.h
--- tint-0.04+nmu1/engine.h 2001-12-07 16:48:08.000000000 +0100
+++ tint/engine.h 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/engine.h tint/engine.h
--- tint-0.05/engine.h 2001-12-07 16:48:08.000000000 +0100
+++ tint/engine.h 2021-02-09 08:00:00.000000000 +0200
@@ -29,7 +29,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

-#include "typedefs.h" /* bool */
+#include "curses.h" /* bool */

/*
* Macros
diff -rupN tint-0.04+nmu1/io.c tint/io.c
--- tint-0.04+nmu1/io.c 2010-06-23 15:05:12.000000000 +0100
+++ tint/io.c 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/io.c tint/io.c
--- tint-0.05/io.c 2010-06-23 15:05:12.000000000 +0100
+++ tint/io.c 2021-02-09 08:00:00.000000000 +0200
@@ -27,9 +27,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
Expand Down Expand Up @@ -102,25 +102,21 @@ diff -rupN tint-0.04+nmu1/io.c tint/io.c
return ch;
}

diff -rupN tint-0.04+nmu1/io.h tint/io.h
--- tint-0.04+nmu1/io.h 2010-06-23 14:55:03.000000000 +0100
+++ tint/io.h 2018-02-23 12:00:00.000000000 +0200
@@ -29,9 +29,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff -rupN tint-0.05/io.h tint/io.h
--- tint-0.05/io.h 2010-06-23 14:55:03.000000000 +0100
+++ tint/io.h 2021-02-09 08:00:00.000000000 +0200
@@ -30,7 +30,6 @@
*/
-
+

#include <curses.h>
-#include <wchar.h>
-
+

/*
* Colors
*/
diff -rupN tint-0.04+nmu1/Makefile tint/Makefile
--- tint-0.04+nmu1/Makefile 2010-06-23 15:06:11.000000000 +0200
+++ tint/Makefile 2018-02-23 12:00:00.000000000 +0200
@@ -1,0 +1,106 @@
diff -rupN tint-0.05/Makefile tint/Makefile
--- tint-0.05/Makefile 2010-06-23 15:06:11.000000000 +0200
+++ tint/Makefile 2021-02-09 08:00:00.000000000 +0200
@@ -0,0 +1,106 @@
+
+# -*- sh -*-
+
Expand Down Expand Up @@ -227,9 +223,9 @@ diff -rupN tint-0.04+nmu1/Makefile tint/Makefile
+
+
+.PHONY: all clean do-it-all depend with-depends without-depends debian postinst
diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
--- tint-0.04+nmu1/tint.c 2010-08-08 19:42:50.000000000 +0200
+++ tint/tint.c 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/tint.c tint/tint.c
--- tint-0.05/tint.c 2010-08-08 19:42:50.000000000 +0200
+++ tint/tint.c 2021-02-09 08:00:00.000000000 +0200
@@ -1,4 +1,3 @@
-
/*
Expand All @@ -253,13 +249,15 @@ diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
#include "utils.h"
#include "io.h"
#include "config.h"
@@ -306,4 +306,4 @@
@@ -304,7 +304,7 @@ static void showstatus (engine_t *engine
/***************************************************************************/

/* Header for scorefile */
-#define SCORE_HEADER "Tint 0.02b (c) Abraham vd Merwe - Scores"
+#define SCORE_HEADER "Tint 0.04+nmu1 (c) Abraham vd Merwe - Scores"
-
+
+#define SCORE_HEADER "Tint 0.05 (c) Abraham vd Merwe - Scores"

/* Header for score title */
static const char scoretitle[] = "\n\t TINT HIGH SCORES\n\n\tRank Score Name\n\n";
@@ -322,6 +322,7 @@ typedef struct
time_t timestamp;
} score_t;
Expand Down Expand Up @@ -376,7 +374,7 @@ diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
rand_init (); /* must be called before engine_init () */
engine_init (&engine,score_function); /* must be called before using engine.curshape */
finished = shownext = FALSE;
@@ -632,13 +651,15 @@ int main (int argc,char *argv[])
@@ -632,12 +651,14 @@ int main (int argc,char *argv[])
/* pause */
case 'p':
out_setcolor (COLOR_WHITE,COLOR_BLACK);
Expand All @@ -393,8 +391,8 @@ diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
break;
/* unknown keypress */
default:
out_beep ();
@@ -673,11 +694,31 @@ int main (int argc,char *argv[])
@@ -672,12 +693,32 @@ int main (int argc,char *argv[])
while (!finished);
/* Restore console settings and exit */
io_close ();
+#if 0
Expand Down Expand Up @@ -426,9 +424,9 @@ diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
+#endif
}

diff -rupN tint-0.04+nmu1/utils.c tint/utils.c
--- tint-0.04+nmu1/utils.c 2001-12-07 16:49:19.000000000 +0100
+++ tint/utils.c 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/utils.c tint/utils.c
--- tint-0.05/utils.c 2001-12-07 16:49:19.000000000 +0100
+++ tint/utils.c 2021-02-09 08:00:00.000000000 +0200
@@ -27,11 +27,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
Expand Down Expand Up @@ -458,15 +456,15 @@ diff -rupN tint-0.04+nmu1/utils.c tint/utils.c
}

+#endif
diff -rupN tint-0.04+nmu1/utils.h tint/utils.h
--- tint-0.04+nmu1/utils.h 2001-12-07 16:49:35.000000000 +0100
+++ tint/utils.h 2018-02-23 12:00:00.000000000 +0200
diff -rupN tint-0.05/utils.h tint/utils.h
--- tint-0.05/utils.h 2001-12-07 16:49:35.000000000 +0100
+++ tint/utils.h 2021-02-09 08:00:00.000000000 +0200
@@ -29,7 +29,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

-#include "typedefs.h"
+#include <curses.h>

/*
* Initialize random number generator
157 changes: 157 additions & 0 deletions payloads/libpayload/Makefile.payload
View file
@@ -0,0 +1,157 @@
# SPDX-License-Identifier: BSD-3-Clause

#
# This file is meant to be included by in-tree payloads
# to provide default targets for incremental builds.
#
# Variables with file names and directory overrides have
# to be defined in advance for proper dependency tracking.
# Then, include this file. e.g
#
# obj := output
# OBJS := $(obj)/payload.o
# TARGET := $(obj)/payload.elf
# include ../path/to/libpayload/Makefile.payload
#

# Find relative path to libpayload (where this Makefile resides).
LIBPAYLOAD_SRC := $(dir $(lastword $(MAKEFILE_LIST)))
LIBPAYLOAD_SRC := $(patsubst %/,%,$(LIBPAYLOAD_SRC))

# Build dir and config for libpayload. Need absolute
# paths to pass to libpayload's sub-make.
LIBPAYLOAD_OBJ ?= $(CURDIR)/libpayload
LIBPAYLOAD := $(LIBPAYLOAD_OBJ)/libpayload.a
LIBPAYLOAD_CONFIG_H := $(LIBPAYLOAD_OBJ)/libpayload-config.h
LIBPAYLOAD_DOTCONFIG ?= $(CURDIR)/.lp.config
LIBPAYLOAD_DEFCONFIG ?= $(CURDIR)/$(LIBPAYLOAD_SRC)/configs/defconfig

# Some default dependencies for all targets:
DEFAULT_DEPS := Makefile $(lastword $(MAKEFILE_LIST))
DEFAULT_DEPS += $(PAYLOAD_DEPS)

obj ?= build

ARCH ?=
OBJS ?=
CCACHE ?=

CFLAGS = $(GCC_CFLAGS_$(ARCH))
CFLAGS += -Os -ffreestanding
CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror

STRIP ?= debug

$(TARGET):

# Make is silent per default, but `make V=1` will show all calls.
Q:=@
ifneq ($(V),1)
ifneq ($(Q),)
.SILENT:
MAKEFLAGS += -s
endif
endif
export V

ifeq ($(filter %clean,$(MAKECMDGOALS)),)

xcompile := $(obj)/xcompile
xcompile_script := $(LIBPAYLOAD_SRC)/../../util/xcompile/xcompile

# In addition to the dependency below, create the file if it doesn't exist
# to silence warnings about a file that would be generated anyway.
$(if $(wildcard $(xcompile)),,$(shell \
mkdir -p $(dir $(xcompile)) && \
$(xcompile_script) $(XGCCPATH) > $(xcompile) || rm -f $(xcompile)))

$(xcompile): $(xcompile_script)
$< $(XGCCPATH) > $@

include $(xcompile)

ifneq ($(XCOMPILE_COMPLETE),1)
$(shell rm -f $(XCOMPILE_COMPLETE))
$(error $(xcompile) deleted because it's invalid. \
Restarting the build should fix that, or explain the problem.)
endif

# `lpgcc` in in-tree mode:
LPGCC = CC="$(CCACHE) $(GCC_CC_$(ARCH))"
LPGCC += _OBJ="$(LIBPAYLOAD_OBJ)"
LPGCC += $(LIBPAYLOAD_SRC)/bin/lpgcc

LPAS = AS="$(AS_$(ARCH))"
LPAS += $(LIBPAYLOAD_SRC)/bin/lpas

OBJCOPY = $(OBJCOPY_$(ARCH))

$(obj)/%.bin: $(OBJS) $(LIBPAYLOAD) $(DEFAULT_DEPS)
@printf " LPGCC $(subst $(obj)/,,$@)\n"
$(LPGCC) $(CFLAGS) -o $@ $(OBJS)

$(obj)/%.map: $(obj)/%.bin
@printf " SYMS $(subst $(obj)/,,$@)\n"
$(NM_$(ARCH)) -n $< > $@

$(obj)/%.debug: $(obj)/%.bin
@printf " DEBUG $(subst $(obj)/,,$@)\n"
$(OBJCOPY) --only-keep-debug $< $@

.PRECIOUS: $(obj)/%.debug

$(obj)/%.elf: $(obj)/%.bin $(obj)/%.debug
@printf " STRIP $(subst $(obj)/,,$@)\n"
$(OBJCOPY) --strip-$(STRIP) $< $@
$(OBJCOPY) --add-gnu-debuglink=$(obj)/$*.debug $@

$(obj)/%.o: %.c $(LIBPAYLOAD_CONFIG_H) $(DEFAULT_DEPS)
@printf " LPGCC $(subst $(obj)/,,$@)\n"
$(LPGCC) -MMD $(CFLAGS) -c $< -o $@

$(obj)/%.S.o: %.S $(LIBPAYLOAD_CONFIG_H) $(DEFAULT_DEPS)
@printf " LPAS $(subst $(obj)/,,$@)\n"
$(LPAS) $< -o $@

-include $(OBJS:.o=.d)

.PRECIOUS: $(OBJS)

LIBPAYLOAD_OPTS := obj="$(LIBPAYLOAD_OBJ)"
LIBPAYLOAD_OPTS += DOTCONFIG="$(LIBPAYLOAD_DOTCONFIG)"
LIBPAYLOAD_OPTS += $(if $(CCACHE),CONFIG_LP_CCACHE=y)

defconfig: lp-defconfig
lp-defconfig: $(LIBPAYLOAD_DOTCONFIG)
$(LIBPAYLOAD_DOTCONFIG): $(LIBPAYLOAD_DEFCONFIG) | $(PAYLOAD_DEPS)
$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) \
KBUILD_DEFCONFIG=$(LIBPAYLOAD_DEFCONFIG) defconfig

$(LIBPAYLOAD_CONFIG_H): $(LIBPAYLOAD_DOTCONFIG)
$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) $(LIBPAYLOAD_CONFIG_H)

oldconfig: lp-oldconfig
lp-oldconfig:
[ ! -f $(LIBPAYLOAD_DOTCONFIG) ] || \
$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) oldconfig

$(LIBPAYLOAD): lp-defconfig | $(LIBPAYLOAD_CONFIG_H)
$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS)

$(shell mkdir -p $(sort $(dir $(OBJS))))

.PHONY: oldconfig lp-oldconfig defconfig lp-defconfig

else # %clean,$(MAKECMDGOALS)

default-payload-clean:
rm -rf $(obj) $(LIBPAYLOAD_OBJ)
clean: default-payload-clean

default-payload-distclean: clean
rm -f $(LIBPAYLOAD_DOTCONFIG) $(LIBPAYLOAD_DOTCONFIG).old
distclean: default-payload-distclean

.PHONY: default-payload-clean clean default-payload-distclean distclean

endif
2 changes: 1 addition & 1 deletion payloads/libpayload/arch/arm/Kconfig
View file
Expand Up @@ -28,7 +28,7 @@

if ARCH_ARM

config ARCH_SPECIFIC_OPTIONS # dummy
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN

Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/arch/arm64/Kconfig
View file
Expand Up @@ -28,7 +28,7 @@

if ARCH_ARM64

config ARCH_SPECIFIC_OPTIONS # dummy
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN

Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/arch/arm64/mmu.c
View file
Expand Up @@ -389,7 +389,7 @@ struct mmu_new_range_prop {

/*
* Func: mmu_is_range_free
* Desc: We need to ensure that the new range being allocated doesnt overlap
* Desc: We need to ensure that the new range being allocated doesn't overlap
* with any used memory range. Basically:
* 1. Memory ranges used by the payload (usedmem_ranges)
* 2. Any area that falls below _end symbol in linker script (Kernel needs to be
Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/arch/x86/Kconfig
View file
Expand Up @@ -28,7 +28,7 @@

if ARCH_X86

config ARCH_SPECIFIC_OPTIONS # dummy
config ARCH_SPECIFIC_OPTIONS
def_bool y
select LITTLE_ENDIAN
select IO_ADDRESS_SPACE
Expand Down
25 changes: 19 additions & 6 deletions payloads/libpayload/include/arm/arch/io.h
View file
Expand Up @@ -80,43 +80,56 @@ static inline void writel(uint32_t _v, volatile void *_a)
dmb();
}

static inline uint8_t read8(const void *addr)
static inline uint8_t read8(volatile const void *addr)
{
dmb();
return *(volatile uint8_t *)addr;
}

static inline uint16_t read16(const void *addr)
static inline uint16_t read16(volatile const void *addr)
{
dmb();
return *(volatile uint16_t *)addr;
}

static inline uint32_t read32(const void *addr)
static inline uint32_t read32(volatile const void *addr)
{
dmb();
return *(volatile uint32_t *)addr;
}

static inline void write8(void *addr, uint8_t val)
static inline uint64_t read64(volatile const void *addr)
{
dmb();
return *(volatile uint64_t *)addr;
}

static inline void write8(volatile void *addr, uint8_t val)
{
dmb();
*(volatile uint8_t *)addr = val;
dmb();
}

static inline void write16(void *addr, uint16_t val)
static inline void write16(volatile void *addr, uint16_t val)
{
dmb();
*(volatile uint16_t *)addr = val;
dmb();
}

static inline void write32(void *addr, uint32_t val)
static inline void write32(volatile void *addr, uint32_t val)
{
dmb();
*(volatile uint32_t *)addr = val;
dmb();
}

static inline void write64(volatile void *addr, uint64_t val)
{
dmb();
*(volatile uint64_t *)addr = val;
dmb();
}

#endif
25 changes: 19 additions & 6 deletions payloads/libpayload/include/arm64/arch/io.h
View file
Expand Up @@ -81,43 +81,56 @@ static inline void writel(uint32_t _v, volatile void *_a)
dmb();
}

static inline uint8_t read8(const void *addr)
static inline uint8_t read8(volatile const void *addr)
{
dmb();
return *(volatile uint8_t *)addr;
}

static inline uint16_t read16(const void *addr)
static inline uint16_t read16(volatile const void *addr)
{
dmb();
return *(volatile uint16_t *)addr;
}

static inline uint32_t read32(const void *addr)
static inline uint32_t read32(volatile const void *addr)
{
dmb();
return *(volatile uint32_t *)addr;
}

static inline void write8(void *addr, uint8_t val)
static inline uint64_t read64(volatile const void *addr)
{
dmb();
return *(volatile uint64_t *)addr;
}

static inline void write8(volatile void *addr, uint8_t val)
{
dmb();
*(volatile uint8_t *)addr = val;
dmb();
}

static inline void write16(void *addr, uint16_t val)
static inline void write16(volatile void *addr, uint16_t val)
{
dmb();
*(volatile uint16_t *)addr = val;
dmb();
}

static inline void write32(void *addr, uint32_t val)
static inline void write32(volatile void *addr, uint32_t val)
{
dmb();
*(volatile uint32_t *)addr = val;
dmb();
}

static inline void write64(volatile void *addr, uint64_t val)
{
dmb();
*(volatile uint64_t *)addr = val;
dmb();
}

#endif
2 changes: 1 addition & 1 deletion payloads/nvramcui/.gitignore
View file
@@ -1,2 +1,2 @@
build
libpayload
.lp.config*
37 changes: 8 additions & 29 deletions payloads/nvramcui/Makefile
View file
@@ -1,34 +1,13 @@
LIBPAYLOAD_DIR=$(CURDIR)/libpayload
XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile
# build libpayload and put .config file in $(CURDIR) instead of ../libpayload
# to avoid pollute the libpayload source directory and possible conflicts
LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config"
CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib
unexport $(COREBOOT_EXPORTS)

all: nvramcui.elf
ARCH = x86_32
OBJS = $(obj)/nvramcui.o
TARGET = $(obj)/nvramcui.elf

$(LIBPAYLOAD_DIR):
$(MAKE) -C ../libpayload $(LPOPTS) defconfig
$(MAKE) -C ../libpayload $(LPOPTS)
$(MAKE) -C ../libpayload $(LPOPTS) install
all: real-all

ifneq ($(strip $(wildcard libpayload)),)
include $(XCOMPILE)
LPGCC = CC="$(GCC_CC_x86_32)" "$(LIBPAYLOAD_DIR)/bin/lpgcc"
%.elf: %.c Makefile
$(LPGCC) $(CFLAGS) -o $*.elf $*.c
else
# If libpayload is not found, first build libpayload,
# then do the make, this time it'll find libpayload
# and generate the nvramcui.elf target
%.elf: $(LIBPAYLOAD_DIR)
$(MAKE) all
endif
include ../libpayload/Makefile.payload

clean:
rm -rf build libpayload nvramcui.elf
real-all: $(TARGET)

distclean: clean
rm -rf .config .config.old

.PHONY: all clean distclean
.PHONY: all real-all
2 changes: 2 additions & 0 deletions src/Kconfig
View file
Expand Up @@ -523,8 +523,10 @@ comment "CPU"
source "src/cpu/Kconfig"
comment "Northbridge"
source "src/northbridge/*/*/Kconfig"
source "src/northbridge/*/*/Kconfig.common"
comment "Southbridge"
source "src/southbridge/*/*/Kconfig"
source "src/southbridge/*/*/Kconfig.common"
comment "Super I/O"
source "src/superio/*/*/Kconfig"
comment "Embedded Controllers"
Expand Down
3 changes: 3 additions & 0 deletions src/acpi/Kconfig
View file
Expand Up @@ -30,6 +30,9 @@ config ACPI_SOC_NVS
Set to indicate <soc/nvs.h> exists for the platform with a definition
for global_nvs.

config ACPI_HAS_DEVICE_NVS
bool

config ACPI_NO_PCAT_8259
bool
help
Expand Down
24 changes: 24 additions & 0 deletions src/acpi/acpi.c
View file
Expand Up @@ -23,6 +23,7 @@
#include <commonlib/helpers.h>
#include <cpu/cpu.h>
#include <cbfs.h>
#include <types.h>
#include <version.h>
#include <commonlib/sort.h>

Expand Down Expand Up @@ -1331,6 +1332,14 @@ unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t
return lpi_desc->header.length;
}

/* BERT helpers */
bool __weak acpi_is_boot_error_src_present(void)
{
return false;
}

__weak void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length) {}

unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
{
return 0;
Expand All @@ -1352,6 +1361,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_tpm2_t *tpm2;
acpi_madt_t *madt;
acpi_lpit_t *lpit;
acpi_bert_t *bert;
struct device *dev;
unsigned long fw;
size_t slic_size, dsdt_size;
Expand Down Expand Up @@ -1573,6 +1583,20 @@ unsigned long write_acpi_tables(unsigned long start)

current = acpi_align_current(current);

if (acpi_is_boot_error_src_present()) {
void *region;
size_t size;
printk(BIOS_DEBUG, "ACPI: * BERT\n");
bert = (acpi_bert_t *) current;
acpi_soc_fill_bert(bert, &region, &size);
acpi_write_bert(bert, (uintptr_t)region, size);
if (bert->header.length >= sizeof(acpi_bert_t)) {
current += bert->header.length;
acpi_add_table(rsdp, bert);
}
current = acpi_align_current(current);
}

printk(BIOS_DEBUG, "current = %lx\n", current);

for (dev = all_devices; dev; dev = dev->next) {
Expand Down
13 changes: 1 addition & 12 deletions src/acpi/acpigen.c
View file
Expand Up @@ -21,6 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_type.h>
#include <device/soundwire.h>
#include <types.h>

static char *gencurrent;

Expand Down Expand Up @@ -151,18 +152,6 @@ void acpigen_write_integer(uint64_t data)
acpigen_write_qword(data);
}

void acpigen_write_name_zero(const char *name)
{
acpigen_write_name(name);
acpigen_write_one();
}

void acpigen_write_name_one(const char *name)
{
acpigen_write_name(name);
acpigen_write_zero();
}

void acpigen_write_name_byte(const char *name, uint8_t val)
{
acpigen_write_name(name);
Expand Down
26 changes: 26 additions & 0 deletions src/acpi/acpigen_extern.asl
View file
@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/*
* Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we provide it runtime via NVBx and NVSx variables from acpigen.
*/

#if CONFIG(ACPI_SOC_NVS)
External (NVB0, IntObj)
External (NVS0, IntObj)
OperationRegion (GNVS, SystemMemory, NVB0, NVS0)
#endif

#if CONFIG(ACPI_HAS_DEVICE_NVS)
External (NVB1, IntObj)
External (NVS1, IntObj)
OperationRegion (DNVS, SystemMemory, NVB1, NVS1)
#endif

#if CONFIG(CHROMEOS)
External (NVB2, IntObj)
External (NVS2, IntObj)
OperationRegion (CNVS, SystemMemory, NVB2, NVS2)
#endif
45 changes: 45 additions & 0 deletions src/acpi/dsdt_top.asl
View file
@@ -0,0 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpigen_extern.asl>

#if CONFIG(CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif

/* Operating system enumeration. */
Name (OSYS, 0)

/* Zero => PIC mode, One => APIC Mode */
Name (PICM, Zero)

/* Power state (AC = 1) */
Name (PWRS, One)

/*
* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/

Method (_PIC, 1)
{
/* Remember the OS' IRQ routing choice. */
PICM = Arg0
}

#if CONFIG(MMCONF_SUPPORT)
Scope(\_SB) {
/* Base address of PCIe config space */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)

/* Length of PCIe config space, 1MB each bus */
Name(PCLN, CONFIG_MMCONF_LENGTH)

/* PCIe Configuration Space */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
}
#endif
76 changes: 56 additions & 20 deletions src/acpi/gnvs.c
View file
Expand Up @@ -12,36 +12,21 @@

static struct global_nvs *gnvs;

void *acpi_get_gnvs(void)
{
if (gnvs)
return gnvs;

gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs)
return gnvs;

printk(BIOS_ERR, "Unable to locate Global NVS\n");
return NULL;
}

__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { }
__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }

void acpi_create_gnvs(void)
{
size_t gnvs_size;

if (cbmem_find(CBMEM_ID_ACPI_GNVS))
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs)
return;

/* Match with OpRegion declared in global_nvs.asl. */
gnvs_size = sizeof(struct global_nvs);
if (gnvs_size < 0x100)
gnvs_size = 0x100;
if (gnvs_size > 0x1000)
if (CONFIG(ACPI_HAS_DEVICE_NVS))
gnvs_size = 0x2000;
else if (CONFIG(MAINBOARD_HAS_CHROMEOS))
else if (CONFIG(CHROMEOS))
gnvs_size = 0x1000;

gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
Expand All @@ -57,6 +42,29 @@ void acpi_create_gnvs(void)
gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
}

void *acpi_get_gnvs(void)
{
if (gnvs)
return gnvs;

gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs)
return gnvs;

printk(BIOS_ERR, "Unable to locate Global NVS\n");
return NULL;
}

void *acpi_get_device_nvs(void)
{
return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
}

/* Implemented under platform. */
__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { }
__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }

/* Called from write_acpi_tables() only on normal boot path. */
void acpi_fill_gnvs(void)
{
if (!gnvs)
Expand All @@ -66,6 +74,34 @@ void acpi_fill_gnvs(void)
mainboard_fill_gnvs(gnvs);

acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
acpigen_write_name_dword("NVB0", (uintptr_t)gnvs);
acpigen_write_name_dword("NVS0", 0x100);
acpigen_pop_len();

if (CONFIG(CHROMEOS)) {
acpigen_write_scope("\\");
acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
acpigen_write_name_dword("NVS2", 0xf00);
acpigen_pop_len();
}

if (CONFIG(ACPI_HAS_DEVICE_NVS)) {
acpigen_write_scope("\\");
acpigen_write_name_dword("NVB1", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET);
acpigen_write_name_dword("NVS1", 0x1000);
acpigen_pop_len();
}
}

int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs_)
{
if (!gnvs)
return -1;

/* Set unknown wake source */
gnvs->pm1i = -1;
gnvs->gpei = -1;

*gnvs_ = gnvs;
return 0;
}
110 changes: 0 additions & 110 deletions src/arch/arm/armv7/thread.c
View file

This file was deleted.

1 change: 0 additions & 1 deletion src/arch/arm/fit_payload.c
View file
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <console/console.h>
#include <bootmem.h>
#include <program_loading.h>
#include <fit.h>
Expand Down
2 changes: 1 addition & 1 deletion src/arch/arm/include/armv7/arch/mmio.h
View file
Expand Up @@ -7,7 +7,7 @@
#ifndef __ARCH_MMIO_H__
#define __ARCH_MMIO_H__

#include <arch/cache.h> /* for dmb() */
#include <arch/cache.h>
#include <endian.h>
#include <stdint.h>

Expand Down
1 change: 0 additions & 1 deletion src/arch/riscv/romstage.c
View file
Expand Up @@ -9,7 +9,6 @@

#include <arch/stages.h>
#include <arch/smp/smp.h>
#include <rules.h>
#include <mcall.h>

void stage_entry(int hart_id, void *fdt)
Expand Down
10 changes: 8 additions & 2 deletions src/arch/x86/Kconfig
View file
Expand Up @@ -186,10 +186,16 @@ config HPET_ADDRESS
hex
default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

# 64KiB default bootblock size
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x10000
default 0x40000 if !FIXED_BOOTBLOCK_SIZE
help
This is only the default maximum of bootblock size for linking
purposes. Platforms may provide different limit and need to
specify this when FIXED_BOOTBLOCK_SIZE is selected.

config FIXED_BOOTBLOCK_SIZE
bool

# Default address romstage is to be linked at
config ROMSTAGE_ADDR
Expand Down
2 changes: 0 additions & 2 deletions src/arch/x86/Makefile.inc
View file
Expand Up @@ -85,8 +85,6 @@ bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c

$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h

bootblock-y += bootblock_crt0.S

ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
$(eval $(call early_x86_stage,bootblock,elf32-i386))
else
Expand Down
46 changes: 46 additions & 0 deletions src/arch/x86/acpi_bert_storage.c
View file
Expand Up @@ -106,6 +106,7 @@ static void revise_error_sizes(acpi_generic_error_status_t *status, size_t size)
entries = bert_entry_count(status);
entry = acpi_hest_generic_data_nth(status, entries);
status->data_length += size;
status->raw_data_length += size;
if (entry)
entry->data_length += size;
}
Expand Down Expand Up @@ -174,6 +175,7 @@ static acpi_hest_generic_data_v300_t *new_generic_error_entry(
entry->validation_bits |= ACPI_GENERROR_VALID_TIMESTAMP;

status->data_length += sizeof(*entry);
status->raw_data_length += sizeof(*entry);
bert_bump_entry_count(status);

return entry;
Expand All @@ -186,12 +188,52 @@ static size_t sizeof_error_section(guid_t *guid)
return sizeof(cper_proc_generic_error_section_t);
else if (!guidcmp(guid, &CPER_SEC_PROC_IA32X64_GUID))
return sizeof(cper_ia32x64_proc_error_section_t);
else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID))
return sizeof(cper_fw_err_rec_section_t);
/* else if ... sizeof(structures not yet defined) */

printk(BIOS_ERR, "Error: Requested size of unrecognized CPER GUID\n");
return 0;
}

void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size)
{
void *cl_data = bert_allocate_storage(cl_size);
if (!cl_data) {
printk(BIOS_ERR, "Error: Crashlog entry (size %zu) would exceed available region\n",
cl_size);
return NULL;
}

revise_error_sizes(status, cl_size);

return cl_data;
}

/* Helper to append an ACPI Generic Error Data Entry per crashlog data */
acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status)
{
acpi_hest_generic_data_v300_t *entry;
cper_fw_err_rec_section_t *fw_err;

entry = bert_append_error_datasection(status, &CPER_SEC_FW_ERR_REC_REF_GUID);
if (!entry)
return NULL;

status->block_status |= GENERIC_ERR_STS_UNCORRECTABLE_VALID;
status->error_severity = ACPI_GENERROR_SEV_FATAL;
entry->error_severity = ACPI_GENERROR_SEV_FATAL;

fw_err = section_of_acpientry(fw_err, entry);

fw_err->record_type = CRASHLOG_RECORD_TYPE;
fw_err->revision = CRASHLOG_FW_ERR_REV;
fw_err->record_id = 0;
guidcpy(&fw_err->record_guid, &FW_ERR_RECORD_ID_CRASHLOG_GUID);

return entry;
}

/* Append a new ACPI Generic Error Data Entry plus CPER Error Section to an
* existing ACPI Generic Error Status Block. The caller is responsible for
* the setting the status and entry severity, as well as populating all fields
Expand Down Expand Up @@ -486,10 +528,14 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid)
if (!status)
return NULL;

status->raw_data_length = sizeof(*status);

if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID))
r = bert_append_genproc(status);
else if (!guidcmp(guid, &CPER_SEC_PROC_GENERIC_GUID))
r = bert_append_ia32x64(status);
else if (!guidcmp(guid, &CPER_SEC_FW_ERR_REC_REF_GUID))
r = bert_append_fw_err(status);
/* else if other types not implemented */
else
r = NULL;
Expand Down
47 changes: 45 additions & 2 deletions src/arch/x86/bootblock.ld
View file
Expand Up @@ -12,8 +12,40 @@ ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff;
#endif

SECTIONS {
/* Trigger an error if I have an unusable start address */
_bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");

#if CONFIG(FIXED_BOOTBLOCK_SIZE)
. = _ebootblock - CONFIG_C_ENV_BOOTBLOCK_SIZE;
#else
. = BOOTBLOCK_TOP - PROGRAM_SZ;
. = ALIGN(16);
#endif

_bootblock = .;

INCLUDE "bootblock/lib/program.ld"

/*
* Allocation reserves extra space here. Alignment requirements
* may cause the total size of a section to change when the start
* address gets applied.
*/
PROGRAM_SZ = SIZEOF(.text) + 512;

. = MIN(_ID_SECTION, _FIT_POINTER) - EARLYASM_SZ;
. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16);
BOOTBLOCK_TOP = .;
.init (.) : {
*(.init._start);
*(.init);
*(.init.*);
}

/*
* Allocation reserves extra space here. Alignment requirements
* may cause the total size of a section to change when the start
* address gets applied.
*/
EARLYASM_SZ = SIZEOF(.init) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16);

. = _ID_SECTION;
.id (.): {
Expand All @@ -37,4 +69,15 @@ SECTIONS {
. = 15;
BYTE(0x00);
}
_ebootblock = .;
}

/*
* Tests _bogus1 and _bogus2 are here to detect case of symbol addresses truncated
* to 32 bits and intermediate files reaching size of close to 4 GiB.
*/
_bogus1 = ASSERT(_bootblock & 0x80000000, "_bootblock too low, invalid ld script");
_bogus2 = ASSERT(_start16bit & 0x80000000, "_start16bit too low, invalid ld script");
_bogus3 = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");
_bogus4 = ASSERT(_ebootblock - _bootblock <= CONFIG_C_ENV_BOOTBLOCK_SIZE,
"_bootblock too low, increase C_ENV_BOOTBLOCK_SIZE");
2 changes: 2 additions & 0 deletions src/arch/x86/c_start.S
View file
Expand Up @@ -8,13 +8,15 @@
.section .bss, "aw", @nobits
.global _stack
.global _estack
.global _stack_size

/* Stack alignment is not enforced with rmodule loader, reserve one
* extra CPU such that alignment can be enforced on entry. */
.align CONFIG_STACK_SIZE
_stack:
.space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE
_estack:
.set _stack_size, _estack - _stack
#if CONFIG(COOP_MULTITASKING)
.global thread_stacks
thread_stacks:
Expand Down
19 changes: 5 additions & 14 deletions src/arch/x86/car.ld
View file
Expand Up @@ -11,9 +11,7 @@
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
_pagetables = . ;
. += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
_epagetables = . ;
REGION(pagetables, ., 4K * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4K)
#endif
#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
/* Vboot work buffer only needs to be available when verified boot
Expand All @@ -28,9 +26,7 @@
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
_car_stack = .;
. += CONFIG_DCACHE_BSP_STACK_SIZE;
_ecar_stack = .;
REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 4)
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that
* multiple stages (romstage and verstage) have a consistent
Expand All @@ -42,9 +38,7 @@
* totalling 32 bytes that need to be 32-byte aligned. The reason the
* pdpt are not colocated with the rest of the page tables is to reduce
* fragmentation of the CAR space that persists across stages. */
_pdpt = .;
. += 32;
_epdpt = .;
REGION(pdpt, ., 32, 32)
#endif

TIMESTAMP(., 0x200)
Expand All @@ -56,10 +50,8 @@
FMAP_CACHE(., FMAP_SIZE)
#endif

_car_ehci_dbg_info = .;
/* Reserve sizeof(struct ehci_dbg_info). */
. += 80;
_ecar_ehci_dbg_info = .;
REGION(car_ehci_dbg_info, ., 80, 1)

/* _bss and _ebss provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
Expand All @@ -75,6 +67,7 @@
*(.sbss.*)
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_ebss = .;
RECORD_SIZE(bss)

#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
_shadow_size = (_ebss - _car_region_start) >> 3;
Expand All @@ -94,8 +87,6 @@
.car.mrc_var . (NOLOAD) : {
. += CONFIG_DCACHE_RAM_MRC_VAR_SIZE;
}

. = _car_region_end;
.car.fspt_reserved . (NOLOAD) : {
. += CONFIG_FSP_T_RESERVED_SIZE;
}
Expand Down
5 changes: 2 additions & 3 deletions src/arch/x86/cpu.c
View file
Expand Up @@ -9,7 +9,6 @@
#include <cpu/x86/mp.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
#include <smp/spinlock.h>
Expand Down Expand Up @@ -124,7 +123,7 @@ static const char *cpu_vendor_name(int vendor)
{
const char *name;
name = "<invalid CPU vendor>";
if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
if ((vendor < ARRAY_SIZE(x86_vendor_name)) &&
(x86_vendor_name[vendor] != 0))
name = x86_vendor_name[vendor];
return name;
Expand Down Expand Up @@ -334,7 +333,7 @@ void arch_bootstate_coreboot_exit(void)
* function will always getting called from coreboot context
* (ESP stack pointer will always refer to coreboot).
*
* But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this
* But with MP_SERVICES_PPI implementation in coreboot this
* assumption might not be true, where FSP context (stack pointer refers
* to FSP) will request to get cpu_index().
*
Expand Down
1 change: 0 additions & 1 deletion src/arch/x86/ebda.c
View file
Expand Up @@ -4,7 +4,6 @@
#include <acpi/acpi.h>
#include <arch/ebda.h>
#include <commonlib/endian.h>
#include <console/console.h>

static void *get_ebda_start(void)
{
Expand Down