136 changes: 136 additions & 0 deletions payloads/external/iPXE/general.h
View file
@@ -0,0 +1,136 @@
/*
* Network protocols
*
*/

#define NET_PROTO_IPV4 /* IPv4 protocol */
#define NET_PROTO_IPV6 /* IPv6 protocol */
#undef NET_PROTO_FCOE /* Fibre Channel over Ethernet protocol */
#define NET_PROTO_STP /* Spanning Tree protocol */

/*
* PXE support
*
*/
#define PXE_STACK /* PXE stack in iPXE - you want this! */
#define PXE_MENU /* PXE menu booting */

/*
* Download protocols
*
*/

#define DOWNLOAD_PROTO_TFTP /* Trivial File Transfer Protocol */
#define DOWNLOAD_PROTO_HTTP /* Hypertext Transfer Protocol */
#define DOWNLOAD_PROTO_HTTPS /* Secure Hypertext Transfer Protocol */
#define DOWNLOAD_PROTO_FTP /* File Transfer Protocol */
#define DOWNLOAD_PROTO_SLAM /* Scalable Local Area Multicast */
#define DOWNLOAD_PROTO_NFS /* Network File System Protocol */

/*
* SAN boot protocols
*
*/

#define SANBOOT_PROTO_ISCSI /* iSCSI protocol */
#define SANBOOT_PROTO_AOE /* AoE protocol */
#undef SANBOOT_PROTO_IB_SRP /* Infiniband SCSI RDMA protocol */
#undef SANBOOT_PROTO_FCP /* Fibre Channel protocol */
#define SANBOOT_PROTO_HTTP /* HTTP SAN protocol */

/*
* HTTP extensions
*
*/
#define HTTP_AUTH_BASIC /* Basic authentication */
#define HTTP_AUTH_DIGEST /* Digest authentication */
#define HTTP_ENC_PEERDIST /* PeerDist content encoding */

/*
* 802.11 cryptosystems and handshaking protocols
*
*/
#define CRYPTO_80211_WEP /* WEP encryption (deprecated and insecure!) */
#define CRYPTO_80211_WPA /* WPA Personal, authenticating with passphrase */
#define CRYPTO_80211_WPA2 /* Add support for stronger WPA cryptography */

/*
* Name resolution modules
*
*/

#define DNS_RESOLVER /* DNS resolver */
/*
* Image types
*
* Etherboot supports various image formats. Select whichever ones
* you want to use.
*
*/
#define IMAGE_NBI /* NBI image support */
#define IMAGE_ELF /* ELF image support */
#define IMAGE_MULTIBOOT /* MultiBoot image support */
#define IMAGE_PXE /* PXE image support */
#define IMAGE_SCRIPT /* iPXE script image support */
#define IMAGE_BZIMAGE /* Linux bzImage image support */
#define IMAGE_COMBOOT /* SYSLINUX COMBOOT image support */
#undef IMAGE_EFI /* EFI image support */
#define IMAGE_SDI /* SDI image support */
#define IMAGE_PNM /* PNM image support */
#define IMAGE_PNG /* PNG image support */

/*
* Command-line commands to include
*
*/
#define AUTOBOOT_CMD /* Automatic booting */
#define NVO_CMD /* Non-volatile option storage commands */
#define CONFIG_CMD /* Option configuration console */
#define IFMGMT_CMD /* Interface management commands */
#define IWMGMT_CMD /* Wireless interface management commands */
#define IBMGMT_CMD /* Infiniband management commands */
#define FCMGMT_CMD /* Fibre Channel management commands */
#define ROUTE_CMD /* Routing table management commands */
#define IMAGE_CMD /* Image management commands */
#define DHCP_CMD /* DHCP management commands */
#define SANBOOT_CMD /* SAN boot commands */
#define MENU_CMD /* Menu commands */
#define LOGIN_CMD /* Login command */
#define SYNC_CMD /* Sync command */
#define NSLOOKUP_CMD /* DNS resolving command */
#define TIME_CMD /* Time commands */
#define DIGEST_CMD /* Image crypto digest commands */
#define LOTEST_CMD /* Loopback testing commands */
#define VLAN_CMD /* VLAN commands */
#define PXE_CMD /* PXE commands */
#define REBOOT_CMD /* Reboot command */
#define POWEROFF_CMD /* Power off command */
#define IMAGE_TRUST_CMD /* Image trust management commands */
#define PCI_CMD /* PCI commands */
#define PARAM_CMD /* Form parameter commands */
#define NEIGHBOUR_CMD /* Neighbour management commands */
#define PING_CMD /* Ping command */
#define CONSOLE_CMD /* Console command */
#define IPSTAT_CMD /* IP statistics commands */
#define PROFSTAT_CMD /* Profiling commands */


/*
* ROM-specific options
*
*/
#undef NONPNP_HOOK_INT19 /* Hook INT19 on non-PnP BIOSes */
#define AUTOBOOT_ROM_FILTER /* Autoboot only devices matching our ROM */

/*
* Virtual network devices
*
*/
#define VNIC_IPOIB /* Infiniband IPoIB virtual NICs */
//#define VNIC_XSIGO /* Infiniband Xsigo virtual NICs */

/*
* Error message tables to include
*
*/
#define ERRMSG_80211 /* All 802.11 error descriptions (~3.3kb) */
17 changes: 17 additions & 0 deletions payloads/external/iPXE/menu.ipxe
View file
@@ -0,0 +1,17 @@
#!ipxe
:MENU
menu
item --gap -- ---------------- iPXE boot menu ----------------
item shell ipxe shell
item boot autoboot
choose --default boot --timeout 3000 target && goto ${target}

:boot
autoboot net0
goto MENU

:shell
shell ||
goto MENU

autoboot net0
6 changes: 5 additions & 1 deletion src/cpu/Kconfig
View file
Expand Up @@ -159,6 +159,10 @@ config CPU_MICROCODE_CBFS_NONE
Make sure you have a way of flashing the ROM externally before
selecting this option.

config CPU_UCODE_RAW_BINARY
bool "Add raw microcode binary to CBFS"
help

endchoice

config CPU_MICROCODE_MULTIPLE_FILES
Expand All @@ -178,7 +182,7 @@ config CPU_MICROCODE_HEADER_FILES

config CPU_UCODE_BINARIES
string "Microcode binary path and filename"
depends on CPU_MICROCODE_CBFS_GENERATE
depends on CPU_MICROCODE_CBFS_GENERATE || CPU_UCODE_RAW_BINARY
default ""
help
Some platforms have microcode in the blobs directory, and these can
Expand Down
6 changes: 6 additions & 0 deletions src/cpu/Makefile.inc
View file
Expand Up @@ -21,6 +21,12 @@ ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin
endif

ifeq ($(CONFIG_CPU_UCODE_RAW_BINARY), y)
cbfs-files-y += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file = $(CONFIG_CPU_UCODE_BINARIES)
cpu_microcode_blob.bin-type = microcode
endif

ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
cbfs-files-y += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/microcode/Makefile.inc
View file
@@ -1,2 +1,2 @@
ramstage-y += microcode.c
romstage-y += microcode.c
romstage-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode.c
ramstage-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode.c
1 change: 1 addition & 0 deletions src/cpu/amd/pi/00730F01/Kconfig
View file
Expand Up @@ -16,6 +16,7 @@
config CPU_AMD_PI_00730F01
bool
select X86_AMD_FIXED_MTRRS
select SUPPORT_CPU_UCODE_IN_CBFS

if CPU_AMD_PI_00730F01

Expand Down
4 changes: 4 additions & 0 deletions src/cpu/amd/pi/00730F01/Makefile.inc
View file
Expand Up @@ -14,10 +14,14 @@
#

romstage-y += fixme.c
romstage-y += update_microcode.c
romstage-y += microcode_fam16h.c

ramstage-y += fixme.c
ramstage-y += chip_name.c
ramstage-y += model_16_init.c
ramstage-y += update_microcode.c
ramstage-y += microcode_fam16h.c

subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
Expand Down
163 changes: 163 additions & 0 deletions src/cpu/amd/pi/00730F01/microcode_fam16h.c
View file
@@ -0,0 +1,163 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Raptor Engineering
* Copyright (C) 2018 PC Engines GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#include <arch/io.h>
#include <smp/spinlock.h>

#define UCODE_DEBUG(fmt, args...) \
do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while (0)

#define F16H_MPB_MAX_SIZE 3458
#define F16H_MPB_DATA_OFFSET 32

/*
* STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
* Microcode Patch Block
* Microcode Header
* Microcode "Blob"
* ...
* ...
* (end of file)
*
*
* MICROCODE HEADER (offset 0 bytes from start of file)
* Total size = 32 bytes
* [0:3] Date code (32 bits)
* [4:7] Patch level (32 bits)
* [8:9] Microcode patch data ID (16 bits)
* [10:15] Reserved (48 bits)
* [16:19] Chipset 1 device ID (32 bits)
* [20:23] Chipset 2 device ID (32 bits)
* [24:25] Processor Revisions ID (16 bits)
* [26] Chipset 1 revision ID (8 bits)
* [27] Chipset 2 revision ID (8 bits)
* [28:31] Reserved (32 bits)
*
* MICROCODE BLOB (offset += 32)
* Total size = m bytes
*
*/

struct microcode {
uint32_t date_code;
uint32_t patch_id;

uint16_t mc_patch_data_id;
uint8_t reserved1[6];

uint32_t chipset1_dev_id;
uint32_t chipset2_dev_id;

uint16_t processor_rev_id;

uint8_t chipset1_rev_id;
uint8_t chipset2_rev_id;

uint8_t reserved2[4];

uint8_t m_patch_data[F16H_MPB_MAX_SIZE-F16H_MPB_DATA_OFFSET];

};

static void apply_microcode_patch(const struct microcode *m)
{
uint32_t new_patch_id;
msr_t msr;

/* apply patch */
msr.hi = 0;
msr.lo = (uint32_t)m;

wrmsr(0xc0010020, msr);

UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);

/* patch authentication */
msr = rdmsr(0x8b);
new_patch_id = msr.lo;

UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id ,
(new_patch_id == m->patch_id) ? "success" : "fail");
}

static void amd_update_microcode(const void *ucode, size_t ucode_len,
uint32_t equivalent_processor_rev_id)
{
const struct microcode *m;
const uint8_t *c = ucode;

m = (struct microcode *)c;

if (m->processor_rev_id == equivalent_processor_rev_id) {
apply_microcode_patch(m);
}
}

static const char *microcode_cbfs_file[] = {
"cpu_microcode_blob.bin",
};

void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
{
const void *ucode;
size_t ucode_len;

uint32_t i;

for (i = 0; i < ARRAY_SIZE(microcode_cbfs_file); i++)
{
if (equivalent_processor_rev_id == 0) {
UCODE_DEBUG("rev id not found. Skipping microcode patch!\n");
return;
}

#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_lock(romstage_microcode_cbfs_lock());
#endif
#endif

ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i],
CBFS_TYPE_MICROCODE, &ucode_len);
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
return;
}

if(ucode_len > F16H_MPB_MAX_SIZE) {
UCODE_DEBUG("microcode file invalid. Skipping updates.\n");
}

amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);

#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
}
}
56 changes: 56 additions & 0 deletions src/cpu/amd/pi/00730F01/update_microcode.c
View file
@@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <cpu/amd/microcode.h>

struct id_mapping {
uint32_t orig_id;
uint16_t new_id;
};

static u16 get_equivalent_processor_rev_id(u32 orig_id) {
static const struct id_mapping id_mapping_table[] = {
/* Family 16h */

/* TODO This equivalent processor revisions ID needs verification */
{ 0x730f01, 0x7301 },

/* Array terminator */
{ 0xffffff, 0x0000 },
};

u32 new_id;
int i;

new_id = 0;

for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
if (id_mapping_table[i].orig_id == orig_id) {
new_id = id_mapping_table[i].new_id;
break;
}
}

return new_id;

}

void update_microcode(u32 cpu_deviceid)
{
u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
}
3 changes: 2 additions & 1 deletion src/mainboard/pcengines/apu2/mainboard.c
View file
Expand Up @@ -468,7 +468,8 @@ const char *smbios_mainboard_serial_number(void)
int ret;

ret = read_serial_from_flash(serial, sizeof(serial)-1);
if (ret || (serial[0] == 0) || (serial[0] == 0xff)) {

if (ret || ((serial[0] & 0xff) == 0x00) || ((serial[0] & 0xff) == 0xff)) {
ret = read_serial_from_nic(serial, sizeof(serial)-1);
if (ret) {
serial[0] = '0';
Expand Down
3 changes: 3 additions & 0 deletions src/mainboard/pcengines/apu2/romstage.c
View file
Expand Up @@ -29,6 +29,7 @@
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <cpu/amd/microcode.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <Fch/Fch.h>
#include "gpio_ftns.h"
Expand Down Expand Up @@ -136,6 +137,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);

update_microcode(val);

post_code(0x37);
AGESAWRAPPER(amdinitreset);

Expand Down
2 changes: 1 addition & 1 deletion util/cbfstool/lz4/lib/lz4frame.c
View file
Expand Up @@ -1091,7 +1091,7 @@ size_t LZ4F_decompress(LZ4F_decompressionContext_t decompressionContext,
dctxPtr->tmpInTarget = minFHSize; /* minimum to attempt decode */
dctxPtr->dStage = dstage_storeHeader;
}

/* Falls through. */
case dstage_storeHeader:
{
size_t sizeToCopy = dctxPtr->tmpInTarget - dctxPtr->tmpInSize;
Expand Down