7 changes: 3 additions & 4 deletions src/commonlib/include/commonlib/cbmem_id.h
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -79,6 +76,7 @@
#define CBMEM_ID_ROM1 0x524f4d31
#define CBMEM_ID_ROM2 0x524f4d32
#define CBMEM_ID_ROM3 0x524f4d33
#define CBMEM_ID_FMAP 0x464d4150

#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
Expand Down Expand Up @@ -137,5 +135,6 @@
{ CBMEM_ID_ROM0, "VGA ROM #0 "}, \
{ CBMEM_ID_ROM1, "VGA ROM #1 "}, \
{ CBMEM_ID_ROM2, "VGA ROM #2 "}, \
{ CBMEM_ID_ROM3, "VGA ROM #3 "},
{ CBMEM_ID_ROM3, "VGA ROM #3 "}, \
{ CBMEM_ID_FMAP, "FMAP "},
#endif /* _CBMEM_ID_H_ */
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/compiler.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/compression.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
1 change: 1 addition & 0 deletions src/commonlib/include/commonlib/coreboot_tables.h
View file
Expand Up @@ -89,6 +89,7 @@ enum {
LB_TAG_VBOOT_WORKBUF = 0x0034,
LB_TAG_MMC_INFO = 0x0035,
LB_TAG_TCPA_LOG = 0x0036,
LB_TAG_FMAP = 0x0037,
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,
LB_TAG_OPTION_ENUM = 0x00ca,
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/endian.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/fsp.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/iobuf.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/loglevel.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Nicholas Sielicki <sielicki@nicky.io>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/mem_pool.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/region.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/rmodule-defs.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
9 changes: 3 additions & 6 deletions src/commonlib/include/commonlib/sd_mmc_ctrlr.h
View file
@@ -1,10 +1,5 @@
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* Copyright 2017 Intel Corporation
*
* Controller independent definitions
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -15,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Controller independent definitions
*/
#ifndef __COMMONLIB_SD_MMC_CTRLR_H__
#define __COMMONLIB_SD_MMC_CTRLR_H__
Expand Down
9 changes: 3 additions & 6 deletions src/commonlib/include/commonlib/sdhci.h
View file
@@ -1,10 +1,5 @@
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* Copyright 2017 Intel Corporation
*
* SD host controller specific definitions
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -15,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* SD host controller specific definitions
*/
#ifndef __COMMONLIB_SDHCI_H__
#define __COMMONLIB_SDHCI_H__
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/sort.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
6 changes: 1 addition & 5 deletions src/commonlib/include/commonlib/storage.h
View file
@@ -1,9 +1,5 @@
/*
* Copyright 2008,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/tcpa_log_serialized.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Facebook Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/include/commonlib/timestamp_serialized.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/iobuf.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/mem_pool.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/region.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/sort.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/storage/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Intel Corp.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/commonlib/storage/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Intel Corporation.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
7 changes: 3 additions & 4 deletions src/commonlib/storage/bouncebuf.c
View file
@@ -1,8 +1,5 @@
/*
* Generic bounce buffer implementation
*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
* Copyright 2013 Google Inc. All rights reserved.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -13,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Generic bounce buffer implementation
*/

#include <arch/cache.h>
Expand Down
7 changes: 3 additions & 4 deletions src/commonlib/storage/bouncebuf.h
View file
@@ -1,8 +1,5 @@
/*
* Generic bounce buffer implementation
*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
* Copyright 2013 Google Inc. All rights reserved.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -13,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Generic bounce buffer implementation
*/

#ifndef __COMMONLIB_STORAGE_BOUNCEBUF_H__
Expand Down
12 changes: 4 additions & 8 deletions src/commonlib/storage/mmc.c
View file
@@ -1,12 +1,5 @@
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
*
* MultiMediaCard (MMC) and eMMC specific support code
* This code is controller independent
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -17,6 +10,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* MultiMediaCard (MMC) and eMMC specific support code
* This code is controller independent
*/

#include <commonlib/storage.h>
Expand Down
6 changes: 1 addition & 5 deletions src/commonlib/storage/mmc.h
View file
@@ -1,9 +1,5 @@
/*
* Copyright 2008,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
11 changes: 3 additions & 8 deletions src/commonlib/storage/pci_sdhci.c
View file
@@ -1,6 +1,5 @@
/*
* Copyright 2013 Google Inc.
* Copyright 2017 Intel Corporation
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -13,10 +12,6 @@
* GNU General Public License for more details.
*/

#if ENV_RAMSTAGE
#define __SIMPLE_DEVICE__ 1
#endif

#include <arch/early_variables.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
Expand Down Expand Up @@ -55,11 +50,11 @@ struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr)
return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr);
}

struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev)
struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev)
{
uint32_t addr;

addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0);
if (addr == ((uint32_t)~0)) {
sdhc_error("Error: PCI SDHCI not found\n");
return NULL;
Expand Down
12 changes: 4 additions & 8 deletions src/commonlib/storage/sd.c
View file
@@ -1,12 +1,5 @@
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
*
* Secure Digital (SD) card specific support code
* This code is controller independent
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -17,6 +10,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Secure Digital (SD) card specific support code
* This code is controller independent
*/

#include <commonlib/sd_mmc_ctrlr.h>
Expand Down
14 changes: 5 additions & 9 deletions src/commonlib/storage/sd_mmc.c
View file
@@ -1,13 +1,5 @@
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) common initialization
* code which brings the card into the standby state. This code is controller
* independent.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -18,6 +10,10 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) common initialization
* code which brings the card into the standby state. This code is controller
* independent.
*/

#include <commonlib/storage.h>
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/sd_mmc.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright 2017 Intel Corporation
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
9 changes: 3 additions & 6 deletions src/commonlib/storage/sdhci.c
View file
@@ -1,10 +1,5 @@
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* Copyright 2017 Intel Corporation
*
* Secure Digital (SD) Host Controller interface specific code
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -15,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Secure Digital (SD) Host Controller interface specific code
*/

#include "bouncebuf.h"
Expand Down
5 changes: 1 addition & 4 deletions src/commonlib/storage/sdhci.h
View file
@@ -1,8 +1,5 @@
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* Copyright 2017 Intel Corporation
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
9 changes: 3 additions & 6 deletions src/commonlib/storage/sdhci_adma.c
View file
@@ -1,10 +1,5 @@
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* Copyright 2017 Intel Corporation
*
* Secure Digital (SD) Host Controller interface DMA support code
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -15,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Secure Digital (SD) Host Controller interface DMA support code
*/

#include <commonlib/sdhci.h>
Expand Down
9 changes: 3 additions & 6 deletions src/commonlib/storage/sdhci_display.c
View file
@@ -1,10 +1,5 @@
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* Copyright 2017 Intel Corporation
*
* Secure Digital (SD) Host Controller interface specific code
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -15,6 +10,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Secure Digital (SD) Host Controller interface specific code
*/

#include <commonlib/sd_mmc_ctrlr.h>
Expand Down
16 changes: 6 additions & 10 deletions src/commonlib/storage/storage.c
View file
@@ -1,14 +1,5 @@
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) common code which
* transitions the card from the standby state to the transfer state. The
* common code supports read operations, erase and write operations are in
* a separate modules. This code is controller independent.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -19,6 +10,11 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) common code which
* transitions the card from the standby state to the transfer state. The
* common code supports read operations, erase and write operations are in
* a separate modules. This code is controller independent.
*/

#include <commonlib/storage.h>
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/storage.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright 2017 Intel Corporation
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
12 changes: 4 additions & 8 deletions src/commonlib/storage/storage_erase.c
View file
@@ -1,12 +1,5 @@
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) erase support code.
* This code is controller independent.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -17,6 +10,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) erase support code.
* This code is controller independent.
*/

#include "sd_mmc.h"
Expand Down
12 changes: 4 additions & 8 deletions src/commonlib/storage/storage_write.c
View file
@@ -1,12 +1,5 @@
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Copyright 2013 Google Inc. All rights reserved.
* Copyright 2017 Intel Corporation
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) write support code.
* This code is controller independent.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -17,6 +10,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* MultiMediaCard (MMC), eMMC and Secure Digital (SD) write support code.
* This code is controller independent.
*/

#include <stdlib.h>
Expand Down
2 changes: 0 additions & 2 deletions src/console/console.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/console/die.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/console/hw-debug_sink.adb
View file
@@ -1,8 +1,6 @@
--
-- This file is part of the coreboot project.
--
-- Copyright (C) 2015 secunet Security Networks AG
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/console/hw-debug_sink.ads
View file
@@ -1,8 +1,6 @@
--
-- This file is part of the coreboot project.
--
-- Copyright (C) 2015 secunet Security Networks AG
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; version 2 of the License.
Expand Down
8 changes: 1 addition & 7 deletions src/console/init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand All @@ -24,11 +22,7 @@
#include <version.h>

/* Mutable console log level only allowed when RAM comes online. */
#if defined(__PRE_RAM__)
#define CONSOLE_LEVEL_CONST 1
#else
#define CONSOLE_LEVEL_CONST 0
#endif
#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION

static int console_inited CAR_GLOBAL;
static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
Expand Down
2 changes: 0 additions & 2 deletions src/console/post.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
4 changes: 0 additions & 4 deletions src/console/printk.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
* Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/console/vsprintf.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/console/vtxprintf.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 1991, 1992 Linus Torvalds
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family12/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family12/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family12/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family12/model_12_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/agesa/family12/romstage.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family14/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family14/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family14/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family14/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family14/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family14/model_14_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/agesa/family14/romstage.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/model_15_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family15tn/udelay.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family16kb/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family16kb/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family16kb/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family16kb/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family16kb/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/agesa/family16kb/model_16_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/car/cache_as_ram.inc
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
* Copyright (C) 2008 Carl-Daniel Hailfinger
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
6 changes: 0 additions & 6 deletions src/cpu/amd/car/disable_cache_as_ram.c
View file
@@ -1,12 +1,6 @@
/*
* This file is part of the coreboot project.
*
* original idea yhlu 6.2005 (assembler code)
*
* Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
* Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
10 changes: 2 additions & 8 deletions src/cpu/amd/car/post_cache_as_ram.c
View file
@@ -1,12 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
* Raptor Engineering
* Copyright (C) 2012 Google LLC
* 2005.6 by yhlu
* 2006.3 yhlu add copy data from CAR to ram
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -107,11 +101,11 @@ asmlinkage void *post_cache_as_ram(void)
void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);

print_car_debug("Copying data from cache to RAM...");
memcpy_(migrated_car, _car_relocatable_data_start, car_size);
memcpy_(migrated_car, _car_global_start, car_size);
print_car_debug(" Done\n");

print_car_debug("Verifying data integrity in RAM...");
if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0)
if (memcmp_(migrated_car, _car_global_start, car_size) == 0)
print_car_debug(" Done\n");
else
print_car_debug(" FAILED\n");
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/family_10h-family_15h/defaults.h
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/family_10h-family_15h/fidvid.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/family_10h-family_15h/init_cpus.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/family_10h-family_15h/init_cpus.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/family_10h-family_15h/monotonic_timer.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
5 changes: 0 additions & 5 deletions src/cpu/amd/family_10h-family_15h/processor_name.c
View file
@@ -1,11 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2008 Peter Stuge
* Copyright (C) 2010 Marc Jones <marcj303@gmail.com>
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
5 changes: 1 addition & 4 deletions src/cpu/amd/family_10h-family_15h/ram_calc.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -68,7 +65,7 @@ uint64_t get_cc6_memory_size()
if (is_fam15h()) {
enable_cc6 = 0;

#ifdef __SIMPLE_DEVICE__
#if ENV_PCI_SIMPLE_DEVICE
if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
enable_cc6 = 1;
#else
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/family_10h-family_15h/ram_calc.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/family_10h-family_15h/tsc_freq.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/family_10h-family_15h/update_microcode.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/microcode/microcode.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/model_15_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00630F01/udelay.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License or (at your option)
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00660F01/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00660F01/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00660F01/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00660F01/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00660F01/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00660F01/model_15_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00730F01/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/pi/00730F01/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand All @@ -14,8 +12,6 @@
#

romstage-y += fixme.c
romstage-y += update_microcode.c
romstage-y += microcode_fam16h.c

ramstage-y += fixme.c
ramstage-y += chip_name.c
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00730F01/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00730F01/chip_name.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00730F01/fixme.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
31 changes: 1 addition & 30 deletions src/cpu/amd/pi/00730F01/microcode_fam16h.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Raptor Engineering
* Copyright (C) 2019 PC Engines GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -20,8 +16,6 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#include <arch/io.h>
#include <smp/spinlock.h>

/*
* Values and header structure from:
Expand Down Expand Up @@ -126,44 +120,21 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
"Skipping microcode patch!\n");
return;
}
#ifdef __PRE_RAM__
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_lock(romstage_microcode_cbfs_lock());
#endif
#endif
ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
CBFS_TYPE_MICROCODE,
&ucode_len);
if (!ucode) {
printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. "
"Skipping updates.\n");
#ifdef __PRE_RAM__
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
return;
}

if (ucode_len > F16H_MPB_MAX_SIZE ||
ucode_len < F16H_MPB_DATA_OFFSET) {
printk(BIOS_DEBUG, "microcode file invalid. Skipping "
"updates.\n");
#ifdef __PRE_RAM__
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
return;
}

amd_update_microcode(ucode, ucode_len,
equivalent_processor_rev_id);

#ifdef __PRE_RAM__
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif

amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
}
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/00730F01/model_16_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/pi/00730F01/update_microcode.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2019 PC Engines GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/pi/amd_late_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -17,7 +15,6 @@
#include <bootstate.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>

#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/pi/romstage.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/quadcore/amd_sibling.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/amd/quadcore/quadcore.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
* Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
8 changes: 2 additions & 6 deletions src/cpu/amd/quadcore/quadcore_id.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
* Raptor Engineering
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -46,7 +42,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
uint32_t family;
uint32_t model;

#ifdef __SIMPLE_DEVICE__
#if ENV_PCI_SIMPLE_DEVICE
f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
#else
f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
Expand Down Expand Up @@ -113,7 +109,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54)
uint32_t f5x84;
uint8_t core_count;

#ifdef __SIMPLE_DEVICE__
#if ENV_PCI_SIMPLE_DEVICE
f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
#else
f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/smm/smm_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 coresystems GmbH
* Copyright (C) 2010 Rudolf Marek
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/amd/socket_G34/socket_G34.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 2 additions & 0 deletions src/cpu/intel/Makefile.inc
View file
Expand Up @@ -16,3 +16,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775

subdirs-y += common
4 changes: 0 additions & 4 deletions src/cpu/intel/car/core2/cache_as_ram.S
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/intel/car/non-evict/cache_as_ram.S
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/car/non-evict/exit_car.S
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
5 changes: 0 additions & 5 deletions src/cpu/intel/car/p3/cache_as_ram.S
View file
@@ -1,11 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
5 changes: 0 additions & 5 deletions src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file
@@ -1,11 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/car/p4-netburst/exit_car.S
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
6 changes: 6 additions & 0 deletions src/cpu/intel/common/Kconfig
View file
Expand Up @@ -19,4 +19,10 @@ config SET_IA32_FC_LOCK_BIT
However, leaving the lock bit unset will break Windows' detection of
VMX support and built-in virtualization features like Hyper-V.

config CPU_INTEL_COMMON_TIMEBASE
bool

config CPU_INTEL_COMMON_HYPERTHREADING
bool

endif
14 changes: 10 additions & 4 deletions src/cpu/intel/common/Makefile.inc
View file
@@ -1,5 +1,11 @@
ramstage-y += common_init.c
romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c

ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
bootblock-y += fsb.c
verstage-y += fsb.c
romstage-y += fsb.c
postcar-y += fsb.c
ramstage-y += fsb.c
smm-y += fsb.c
endif
2 changes: 0 additions & 2 deletions src/cpu/intel/common/acpi/cpu.asl
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
7 changes: 7 additions & 0 deletions src/cpu/intel/common/common.h
View file
Expand Up @@ -15,6 +15,8 @@
#ifndef _CPU_INTEL_COMMON_H
#define _CPU_INTEL_COMMON_H

#include <stdint.h>

void set_vmx_and_lock(void);
void set_feature_ctrl_vmx(void);
void set_feature_ctrl_lock(void);
Expand All @@ -27,4 +29,9 @@ void set_feature_ctrl_lock(void);
struct cppc_config;
void cpu_init_cppc_config(struct cppc_config *config, u32 version);

/*
* Returns true if it's not thread 0 on a hyperthreading enabled core.
*/
bool intel_ht_sibling(void);

#endif
3 changes: 0 additions & 3 deletions src/cpu/intel/common/common_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
85 changes: 71 additions & 14 deletions src/cpu/intel/common/fsb.c
View file
Expand Up @@ -11,72 +11,129 @@
* GNU General Public License for more details.
*/

#include <arch/early_variables.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/fsb.h>
#include <console/console.h>
#include <commonlib/helpers.h>
#include <delay.h>

static int get_fsb(void)
static u32 g_timer_fsb CAR_GLOBAL;
static u32 g_timer_tsc CAR_GLOBAL;

/* This is not an architectural MSR. */
#define MSR_PLATFORM_INFO 0xce

static int get_fsb_tsc(int *fsb, int *ratio)
{
struct cpuinfo_x86 c;
static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
msr_t msr;
int ret = -2;

get_fms(&c, cpuid_eax(1));
switch (c.x86) {
case 0x6:
switch (c.x86_model) {
case 0xe: /* Core Solo/Duo */
case 0x1c: /* Atom */
ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
*fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
*ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f;
break;
case 0xf: /* Core 2 or Xeon */
case 0x17: /* Enhanced Core */
ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
*fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
*ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f;
break;
case 0x25: /* Nehalem BCLK fixed at 133MHz */
ret = 133;
*fsb = 133;
*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz */
case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
case 0x3c: /* Haswell BCLK fixed at 100MHz */
case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
case 0x4d: /* Rangeley BCLK fixed at 100MHz */
ret = 100;
*fsb = 100;
*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
break;
default:
return -2;
}
break;
case 0xf: /* Netburst */
msr = rdmsr(MSR_EBC_FREQUENCY_ID);
*ratio = msr.lo >> 24;
switch (c.x86_model) {
case 0x2:
ret = f2x_fsb[(msr.lo >> 16) & 7];
*fsb = f2x_fsb[(msr.lo >> 16) & 7];
break;
case 0x3:
case 0x4:
case 0x6:
ret = core2_fsb[(msr.lo >> 16) & 7];
*fsb = core2_fsb[(msr.lo >> 16) & 7];
break;
default:
return -2;
}
break;
default:
return -2;
}
return ret;
if (*fsb > 0)
return 0;
return -1;
}

int get_ia32_fsb(void)
static void resolve_timebase(void)
{
int ret;
int ret, fsb, ratio;

ret = get_fsb_tsc(&fsb, &ratio);
if (ret == 0) {
u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100);
car_set_var(g_timer_fsb, fsb);
car_set_var(g_timer_tsc, tsc);
return;
}

ret = get_fsb();
if (ret == -1)
printk(BIOS_ERR, "FSB not found\n");
if (ret == -2)
printk(BIOS_ERR, "CPU not supported\n");
return ret;

/* Set some semi-ridiculous defaults. */
car_set_var(g_timer_fsb, 500);
car_set_var(g_timer_tsc, 5000);
return;
}

u32 get_timer_fsb(void)
{
u32 fsb;

fsb = car_get_var(g_timer_fsb);
if (fsb > 0)
return fsb;

resolve_timebase();
return car_get_var(g_timer_fsb);
}

unsigned long tsc_freq_mhz(void)
{
u32 tsc;

tsc = car_get_var(g_timer_tsc);
if (tsc > 0)
return tsc;

resolve_timebase();
return car_get_var(g_timer_tsc);
}

/**
Expand All @@ -87,7 +144,7 @@ int get_ia32_fsb(void)
*/
int get_ia32_fsb_x3(void)
{
const int fsb = get_ia32_fsb();
const int fsb = get_timer_fsb();

if (fsb > 0)
return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100);
Expand Down
45 changes: 45 additions & 0 deletions src/cpu/intel/common/hyperthreading.c
View file
@@ -0,0 +1,45 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <cpu/x86/lapic.h>
#include <cpu/intel/common/common.h>
#include <arch/cpu.h>

/*
* Return true if running thread does not have the smallest lapic ID
* within a CPU core.
*/
bool intel_ht_sibling(void)
{
struct cpuid_result result;
unsigned int core_ids, apic_ids, threads;

/* Is Hyper-Threading supported */
if (!(cpuid_edx(1) & CPUID_FEAURE_HTT))
return false;

apic_ids = 1;
if (cpuid_eax(0) >= 1)
apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
if (apic_ids == 0)
apic_ids = 1;

core_ids = 1;
if (cpuid_eax(0) >= 4) {
result = cpuid_ext(4, 0);
core_ids += (result.eax >> 26) & 0x3f;
}

threads = (apic_ids / core_ids);
return !!(lapicid() & (threads - 1));
}
8 changes: 4 additions & 4 deletions src/cpu/intel/fsp_model_406dx/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand All @@ -28,13 +26,15 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select MMX
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select MICROCODE_BLOB_NOT_IN_BLOB_REPO
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
select TSC_MONOTONIC_TIMER
select TSC_CONSTANT_RATE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_SMM

# Microcode header files are delivered in FSP package
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/fsp_model_406dx/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyrignt (C) 2014 Sage Electronic Engineering, LLC.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand All @@ -15,7 +13,6 @@

ramstage-y += model_406dx_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common

subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/intel/fsp_model_406dx/acpi.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/fsp_model_406dx/bootblock.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/fsp_model_406dx/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/fsp_model_406dx/model_406dx.h
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/haswell/Kconfig
View file
Expand Up @@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select PARALLEL_MP
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_FIXED_XIP_ROM_SIZE

config SMM_TSEG_SIZE
Expand Down
9 changes: 0 additions & 9 deletions src/cpu/intel/haswell/Makefile.inc
View file
@@ -1,35 +1,26 @@
ramstage-y += haswell_init.c
ramstage-y += tsc_freq.c
romstage-y += romstage.c
romstage-y += tsc_freq.c
romstage-y += ../car/romstage.c

postcar-y += tsc_freq.c

ramstage-y += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c

smm-y += finalize.c
smm-y += tsc_freq.c

bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../car/bootblock.c
bootblock-y += ../../x86/early_reset.S
bootblock-y += bootblock.c
bootblock-y += tsc_freq.c

postcar-y += ../car/non-evict/exit_car.S

verstage-y += tsc_freq.c

subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../turbo
subdirs-y += ../common

cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*)
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*)
3 changes: 0 additions & 3 deletions src/cpu/intel/haswell/acpi.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/haswell/bootblock.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -20,7 +18,6 @@
#include <arch/io.h>
#include <halt.h>

#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"

#include <southbridge/intel/lynxpoint/pch.h>
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/haswell/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/haswell/finalize.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
14 changes: 1 addition & 13 deletions src/cpu/intel/haswell/haswell.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down Expand Up @@ -132,9 +130,6 @@
# error "CONFIG_IED_REGION_SIZE is not a power of 2"
#endif

#if !defined(__ROMCC__) // FIXME romcc should handle below constructs

#if defined(__PRE_RAM__)
struct pei_data;
struct rcba_config_instruction;
struct romstage_params {
Expand All @@ -144,24 +139,17 @@ struct romstage_params {
void (*copy_spd)(struct pei_data *);
};
void romstage_common(const struct romstage_params *params);
#endif

#ifdef __SMM__
/* Lock MSRs */
void intel_cpu_haswell_finalize_smm(void);
#else

/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
/* Determine if HyperThreading is disabled. The variable is not valid until
* setup_ap_init() has been called. */
#endif

/* CPU identification */
int haswell_family_model(void);
int haswell_stepping(void);
int haswell_is_ult(void);

#endif

#endif
3 changes: 0 additions & 3 deletions src/cpu/intel/haswell/haswell_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/haswell/romstage.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/haswell/smmrelocate.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
24 changes: 0 additions & 24 deletions src/cpu/intel/hyperthreading/intel_sibling.c
View file
Expand Up @@ -25,30 +25,6 @@
static int first_time = 1;
static int disable_siblings = !CONFIG(LOGICAL_CPUS);

/* Return true if running thread does not have the smallest lapic ID
* within a CPU core.
*/
int intel_ht_sibling(void)
{
unsigned int core_ids, apic_ids, threads;

apic_ids = 1;
if (cpuid_eax(0) >= 1)
apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
if (apic_ids < 1)
apic_ids = 1;

core_ids = 1;
if (cpuid_eax(0) >= 4) {
struct cpuid_result result;
result = cpuid_ext(4, 0);
core_ids += (result.eax >> 26) & 0x3f;
}

threads = (apic_ids / core_ids);
return !!(lapicid() & (threads-1));
}

void intel_sibling_init(struct device *cpu)
{
unsigned int i, siblings;
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/microcode/Makefile.inc
View file
@@ -1,5 +1,6 @@
bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S
romstage-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S

bootblock-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
29 changes: 3 additions & 26 deletions src/cpu/intel/microcode/microcode.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2000 Ronald G. Minnich
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -20,18 +17,16 @@
#include <stddef.h>
#if !defined(__ROMCC__)
#include <cbfs.h>
#include <console/console.h>
#else
#include <arch/cbfs.h>
#endif
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>

#if !defined(__PRE_RAM__)
#include <smp/spinlock.h>

DECLARE_SPIN_LOCK(microcode_lock)
#endif

struct microcode {
u32 hdrver; /* Header Version */
Expand Down Expand Up @@ -89,9 +84,7 @@ void intel_microcode_load_unlocked(const void *microcode_patch)

/* No use loading the same revision. */
if (current_rev == m->rev) {
#if !defined(__ROMCC__)
printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n");
#endif
return;
}

Expand All @@ -109,18 +102,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch)

current_rev = read_microcode_rev();
if (current_rev == m->rev) {
#if !defined(__ROMCC__)
printk(BIOS_INFO, "microcode: updated to revision "
"0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
m->date & 0xffff, (m->date >> 24) & 0xff,
(m->date >> 16) & 0xff);
#endif
return;
}

#if !defined(__ROMCC__)
printk(BIOS_INFO, "microcode: Update failed\n");
#endif
}

uint32_t get_current_microcode_rev(void)
Expand Down Expand Up @@ -185,31 +174,23 @@ const void *intel_microcode_find(void)
msr = rdmsr(IA32_PLATFORM_ID);
pf = 1 << ((msr.hi >> 18) & 7);
}
#if !defined(__ROMCC__)
/* If this code is compiled with ROMCC we're probably in
* the bootblock and don't have console output yet.
*/

printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n",
sig, pf, rev);
#endif

while (microcode_len >= sizeof(*ucode_updates)) {
/* Newer microcode updates include a size field, whereas older
* containers set it at 0 and are exactly 2048 bytes long */
if (ucode_updates->total_size) {
update_size = ucode_updates->total_size;
} else {
#if !defined(__ROMCC__)
printk(BIOS_SPEW, "Microcode size field is 0\n");
#endif
update_size = 2048;
}

/* Checkpoint 1: The microcode update falls within CBFS */
if (update_size > microcode_len) {
#if !defined(__ROMCC__)
printk(BIOS_WARNING, "Microcode header corrupted!\n");
#endif
break;
}

Expand All @@ -228,15 +209,11 @@ void intel_update_microcode_from_cbfs(void)
{
const void *patch = intel_microcode_find();

#if !defined(__ROMCC__) && !defined(__PRE_RAM__)
spin_lock(&microcode_lock);
#endif

intel_microcode_load_unlocked(patch);

#if !defined(__ROMCC__) && !defined(__PRE_RAM__)
spin_unlock(&microcode_lock);
#endif
}

#if ENV_RAMSTAGE
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/microcode/microcode_asm.S
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/intel/model_1067x/Kconfig
View file
Expand Up @@ -6,7 +6,10 @@ config CPU_INTEL_MODEL_1067X
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
1 change: 0 additions & 1 deletion src/cpu/intel/model_1067x/Makefile.inc
View file
@@ -1,7 +1,6 @@
ramstage-y += model_1067x_init.c
ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
subdirs-y += ../smm/gen1

cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*)
2 changes: 0 additions & 2 deletions src/cpu/intel/model_1067x/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_1067x/model_1067x_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_1067x/mp_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/intel/model_106cx/Kconfig
View file
Expand Up @@ -6,13 +6,16 @@ config CPU_INTEL_MODEL_106CX
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select SERIALIZED_SMM_INITIALIZATION
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE

if CPU_INTEL_MODEL_106CX

Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_106cx/Makefile.inc
View file
@@ -1,6 +1,5 @@
ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
subdirs-y += ../common
subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c

Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_106cx/model_106cx_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/model_2065x/Kconfig
View file
Expand Up @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP

Expand Down
6 changes: 0 additions & 6 deletions src/cpu/intel/model_2065x/Makefile.inc
View file
Expand Up @@ -8,12 +8,6 @@ subdirs-y += ../../intel/turbo
subdirs-y += ../../intel/microcode
subdirs-y += ../../x86/smm
subdirs-y += ../smm/gen1
subdirs-y += ../common

ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
smm-y += tsc_freq.c

ramstage-y += acpi.c

Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_2065x/acpi.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
54 changes: 0 additions & 54 deletions src/cpu/intel/model_2065x/bootblock.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -59,60 +57,8 @@ static void enable_rom_caching(void)
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}

static void set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
u32 soft_reset;
u8 nominal_ratio;

/* Minimum CPU revision for configurable TDP support */
if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
return;

/* Check for Flex Ratio support */
flex_ratio = rdmsr(MSR_FLEX_RATIO);
if (!(flex_ratio.lo & FLEX_RATIO_EN))
return;

/* Check for >0 configurable TDPs */
msr = rdmsr(MSR_PLATFORM_INFO);
if (((msr.hi >> 1) & 3) == 0)
return;

/* Use nominal TDP ratio for flex ratio */
msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
nominal_ratio = msr.lo & 0xff;

/* See if flex ratio is already set to nominal TDP ratio */
if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
return;

/* Set flex ratio to nominal TDP ratio */
flex_ratio.lo &= ~0xff00;
flex_ratio.lo |= nominal_ratio << 8;
flex_ratio.lo |= FLEX_RATIO_LOCK;
wrmsr(MSR_FLEX_RATIO, flex_ratio);

/* Set flex ratio in soft reset data register bits 11:6.
* RCBA region is enabled in southbridge bootblock */
soft_reset = RCBA32(SOFT_RESET_DATA);
soft_reset &= ~(0x3f << 6);
soft_reset |= (nominal_ratio & 0x3f) << 6;
RCBA32(SOFT_RESET_DATA) = soft_reset;

/* Set soft reset control to use register value */
RCBA32_OR(SOFT_RESET_CTRL, 1);

/* Issue warm reset, will be "CPU only" due to soft reset data */
outb(0x0, 0xcf9);
outb(0x6, 0xcf9);
halt();
}

static void bootblock_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
enable_rom_caching();
intel_update_microcode_from_cbfs();
}
2 changes: 0 additions & 2 deletions src/cpu/intel/model_2065x/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_2065x/finalize.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_2065x/model_2065x.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_2065x/model_2065x_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/model_206ax/Kconfig
View file
Expand Up @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select PARALLEL_MP
select NO_FIXED_XIP_ROM_SIZE

Expand Down
6 changes: 0 additions & 6 deletions src/cpu/intel/model_206ax/Makefile.inc
View file
@@ -1,7 +1,6 @@
ramstage-y += model_206ax_init.c
subdirs-y += ../../x86/name
subdirs-y += ../smm/gen1
subdirs-y += ../common

subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
Expand All @@ -17,11 +16,6 @@ ramstage-y += common.c
romstage-y += common.c
smm-y += common.c

ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
smm-y += tsc_freq.c

smm-y += finalize.c

cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_206ax/acpi.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_206ax/bootblock.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_206ax/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_206ax/common.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_206ax/finalize.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_206ax/model_206ax.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_206ax/model_206ax_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_65x/Makefile.inc
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_65x/model_65x_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_67x/Makefile.inc
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_67x/model_67x_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_68x/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/model_68x/Makefile.inc
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_68x/model_68x_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_6bx/model_6bx_init.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/intel/model_6ex/Kconfig
View file
Expand Up @@ -6,8 +6,11 @@ config CPU_INTEL_MODEL_6EX
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
2 changes: 0 additions & 2 deletions src/cpu/intel/model_6ex/model_6ex_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/intel/model_6fx/Kconfig
View file
Expand Up @@ -6,8 +6,11 @@ config CPU_INTEL_MODEL_6FX
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
2 changes: 0 additions & 2 deletions src/cpu/intel/model_6fx/model_6fx_init.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 2 additions & 0 deletions src/cpu/intel/model_f2x/Kconfig
View file
Expand Up @@ -7,3 +7,5 @@ config CPU_INTEL_MODEL_F2X
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS
select SMM_ASEG
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_HYPERTHREADING
2 changes: 2 additions & 0 deletions src/cpu/intel/model_f2x/Makefile.inc
View file
@@ -1,3 +1,5 @@
subdirs-y += ../common

ramstage-y += model_f2x_init.c

cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*)
1 change: 1 addition & 0 deletions src/cpu/intel/model_f2x/model_f2x_init.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/common/common.h>
#include <cpu/x86/cache.h>

static void model_f2x_init(struct device *cpu)
Expand Down
2 changes: 2 additions & 0 deletions src/cpu/intel/model_f3x/Kconfig
View file
Expand Up @@ -6,3 +6,5 @@ config CPU_INTEL_MODEL_F3X
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_HYPERTHREADING
1 change: 1 addition & 0 deletions src/cpu/intel/model_f3x/model_f3x_init.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/common/common.h>
#include <cpu/x86/cache.h>

static void model_f3x_init(struct device *cpu)
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/slot_1/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/slot_1/Makefile.inc
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/slot_1/l2_cache.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000 Denis Dowling <dpd@alphalink.com.au>
* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/slot_1/slot_1.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
4 changes: 1 addition & 3 deletions src/cpu/intel/smm/gen1/smmrelocate.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -123,7 +121,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)

/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
if (cpu_has_alternative_smrr())
params->smrr_base.lo &= ~rmask;
params->smrr_base.lo &= rmask;

smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
}
Expand Down
3 changes: 3 additions & 0 deletions src/cpu/intel/socket_mPGA604/Kconfig
View file
Expand Up @@ -9,9 +9,12 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX
select SSE
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM
select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE

# mPGA604 are usually Intel Netburst CPUs which should have SSE2
# but the ramtest.c code on the Dell S1850 seems to choke on
Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/speedstep/acpi.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 coresystems GmbH
* 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/speedstep/speedstep.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/turbo/turbo.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/qemu-power8/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Gerd Hoffmann <kraxel@redhat.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 1 addition & 3 deletions src/cpu/qemu-x86/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Gerd Hoffmann <kraxel@redhat.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand All @@ -21,6 +19,6 @@ config CPU_QEMU_X86
select ARCH_RAMSTAGE_X86_32
select SMP
select UDELAY_TSC
select NO_MONOTONIC_TIMER
select TSC_MONOTONIC_TIMER
select C_ENVIRONMENT_BOOTBLOCK
select SMM_ASEG
3 changes: 0 additions & 3 deletions src/cpu/qemu-x86/bootblock.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Stefan Reinauer
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/qemu-x86/cache_as_ram_bootblock.S
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/bootblock.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/bootblock_media.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/clock.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright (C) 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/dmtimer.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/dmtimer.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/gpio.c
View file
@@ -1,5 +1,5 @@
/*
* Copyright 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/gpio.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/header.c
View file
@@ -1,5 +1,5 @@
/*
* Copyright (C) 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/header.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright (C) 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/header.ld
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/memlayout.ld
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/monotonic_timer.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/ti/am335x/nand.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 1 addition & 2 deletions src/cpu/ti/am335x/pinmux.c
View file
@@ -1,6 +1,5 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
3 changes: 1 addition & 2 deletions src/cpu/ti/am335x/pinmux.h
View file
@@ -1,6 +1,5 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
4 changes: 3 additions & 1 deletion src/cpu/ti/am335x/uart.c
View file
@@ -1,5 +1,5 @@
/*
* Copyright 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand Down Expand Up @@ -189,6 +189,8 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = get_uart_baudrate();
serial.regwidth = 2;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);

lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/uart.h
View file
@@ -1,5 +1,5 @@
/*
* Copyright 2013 Google Inc.
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down
10 changes: 0 additions & 10 deletions src/cpu/via/car/cache_as_ram.inc
View file
@@ -1,16 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Eswar Nallusamy, LANL
* Copyright (C) 2005 Tyan
* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
* Copyright (C) 2007,2008 Carl-Daniel Hailfinger
* Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down