diff --git a/spd/lp5/set-0/spd-5.hex b/spd/lp5/set-0/spd-5.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A 95 08 00 00 00 00 02 01 00 00
+00 00 0C 00 00 00 00 00 AF 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 CE 00 D3 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-0/spd-6.hex b/spd/lp5/set-0/spd-6.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 22 B5 08 00 00 00 00 0A 01 00 00
+00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -7,3 +7,7 @@ H9JCNNNCP3MLYR-N6E,spd-2.hex
 K3LKBKB0BM-MGCP,spd-3.hex
 H9JCNNNBK3MLYR-N6E,spd-1.hex
 MT62F2G32D8DR-031 WT:B,spd-4.hex
+K3LKLKL0EM-MGCN,spd-5.hex
+H58G56AK6BX069,spd-3.hex
+MT62F1G32D4DS-031 WT:B,spd-2.hex
+K3LKCKC0BM-MGCP,spd-6.hex
diff --git a/spd/lp5/set-1/spd-5.hex b/spd/lp5/set-1/spd-5.hex
@@ -0,0 +1,32 @@
+23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
+00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-1/spd-6.hex b/spd/lp5/set-1/spd-6.hex
@@ -0,0 +1,32 @@
+23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
+00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/Kconfig b/src/Kconfig
@@ -70,25 +70,37 @@ config COMPILER_GCC
 	  For details see http://gcc.gnu.org.
 
 config COMPILER_LLVM_CLANG
-	bool "LLVM/clang (TESTING ONLY - Not currently working)"
+	bool "LLVM/clang"
+	depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG
 	help
 	  Use LLVM/clang to build coreboot.  To use this, you must build the
 	  coreboot version of the clang compiler.  Run the command
 	    make clang
-	  Note that this option is not currently working correctly and should
-	  really only be selected if you're trying to work on getting clang
-	  operational.
+	  Note that Clang is not currently working on all architectures.
 
 	  For details see http://clang.llvm.org.
 
 endchoice
 
+config ARCH_SUPPORTS_CLANG
+	bool
+	help
+	  Opt-in flag for architectures that generally work well with CLANG.
+	  By default the option would be hidden.
+
+config ALLOW_EXPERIMENTAL_CLANG
+	bool "Allow experimental LLVM/Clang"
+	depends on !ARCH_SUPPORTS_CLANG
+	help
+	  On some architectures CLANG does not work that well.
+	  Use this only to try to get CLANG working.
+
 config ANY_TOOLCHAIN
 	bool "Allow building with any toolchain"
 	default n
 	help
 	  Many toolchains break when building coreboot since it uses quite
-	  unusual linker features. Unless developers explicitely request it,
+	  unusual linker features. Unless developers explicitly request it,
 	  we'll have to assume that they use their distro compiler by mistake.
 	  Make sure that using patched compilers is a conscious decision.
 
@@ -635,7 +647,7 @@ config HEAP_SIZE
 
 config STACK_SIZE
 	hex
-	default 0x1000 if ARCH_X86
+	default 0x2000 if ARCH_X86
 	default 0x0
 
 config MAX_CPUS

diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c
@@ -13,7 +13,7 @@ void arch_prog_run(struct prog *prog)
 	cache_sync_instructions();
 
 	switch (prog_cbfs_type(prog)) {
-	case CBFS_TYPE_FIT:
+	case CBFS_TYPE_FIT_PAYLOAD:
 		/*
 		 * We only load Linux payloads from the ramstage, so provide a hint to
 		 * the linker that the below functions do not need to be included in

diff --git a/src/arch/arm/include/arch/boot/boot.h b/src/arch/arm/include/arch/boot/boot.h
diff --git a/src/arch/arm64/include/arch/boot/boot.h b/src/arch/arm64/include/arch/boot/boot.h
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
@@ -27,7 +27,7 @@ static void do_arch_prog_run(struct arch_prog_run_args *args)
 	struct prog *prog = args->prog;
 	void *fdt = HLS()->fdt;
 
-	if (prog_cbfs_type(prog) == CBFS_TYPE_FIT)
+	if (prog_cbfs_type(prog) == CBFS_TYPE_FIT_PAYLOAD)
 		fdt = prog_entry_arg(prog);
 
 	if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {

diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c
@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+/* OpenSBI wants to make its own definitions for some of our compiler.h macros. */
+#undef __packed
+#undef __noreturn
+
 #include <sbi/fw_dynamic.h>
 #include <arch/boot.h>
 /* DO NOT INCLUDE COREBOOT HEADERS HERE */

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
@@ -33,6 +33,7 @@ config ARCH_ALL_STAGES_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select ARCH_SUPPORTS_CLANG
 
 # stage selectors for x64
 

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -102,15 +102,11 @@ else
 $(eval $(call early_x86_stage,bootblock,elf64-x86-64))
 endif
 
-ifneq ($(CONFIG_UPDATE_IMAGE),y)
 ifeq ($(CONFIG_BOOTBLOCK_IN_CBFS),y)
-$(call add_intermediate, add_bootblock, $(objcbfs)/bootblock.bin)
-	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
-	$(CBFSTOOL) $< add -f $(objcbfs)/bootblock.bin  -n bootblock -t bootblock $(TXTIBB) -b -$(call file-size,$(objcbfs)/bootblock.bin) \
+add_bootblock = \
+	$(CBFSTOOL) $(1) add -f $(2) -n bootblock -t bootblock $(TXTIBB) \
+	-b -$(call file-size,$(2)) \
 	$(cbfs-autogen-attributes) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
-else # Make sure the bootblock gets build, if only for buildtesting
-$(call add_intermediate, gen_bootblock, $(objcbfs)/bootblock.bin)
-endif
 endif
 
 $(call src-to-obj,bootblock,$(dir)/walkcbfs.S): $(obj)/fmap_config.h
@@ -163,6 +159,7 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
 romstage-y += assembly_entry.S
+romstage-y += romstage.c
 romstage-y += boot.c
 romstage-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
 romstage-y += post.c

diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl
@@ -90,7 +90,7 @@ Method(DBGN, 1)
 */
 Method(DBGB, 1)
 {
-	ShiftRight(Arg0, 4, Local0)
+	Local0 = Arg0 >> 4
 	DBGN(Local0)
 	DBGN(Arg0)
 }
@@ -101,7 +101,7 @@ Method(DBGB, 1)
 */
 Method(DBGW, 1)
 {
-	ShiftRight(Arg0, 8, Local0)
+	Local0 = Arg0 >> 8
 	DBGB(Local0)
 	DBGB(Arg0)
 }
@@ -112,7 +112,7 @@ Method(DBGW, 1)
 */
 Method(DBGD, 1)
 {
-	ShiftRight(Arg0, 16, Local0)
+	Local0 = Arg0 >> 16
 	DBGW(Local0)
 	DBGW(Arg0)
 }
@@ -125,10 +125,10 @@ Method(DBGO, 1)
 {
 	/* DINI() */
 	if (ObjectType(Arg0) == 1) {
-		if (LGreater(Arg0, 0xffff)) {
+		if (Arg0 > 0xffff) {
 			DBGD(Arg0)
 		} else {
-			if (LGreater(Arg0, 0xff)) {
+			if (Arg0 > 0xff) {
 				DBGW(Arg0)
 			} else {
 				DBGB(Arg0)

diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl
@@ -43,7 +43,7 @@ Method(SCMP, 2)
 	While(LLess(Local4, Local7)) {
 		Store(Derefof(Local0[Local4]), Local2)
 		Store(Derefof(Local1[Local4]), Local3)
-		if (LGreater(Local2, Local3)) {
+		if (Local2 > Local3) {
 			Return(One)
 		} else {
 			if (LLess(Local2, Local3)) {
@@ -95,7 +95,7 @@ Method(I2BM, 1)
 	Store(0, Local0)
 	if (LNotEqual(ARG0, 0)) {
 		Store(1, Local1)
-		ShiftLeft(Local1, ARG0, Local0)
+		Local0 = Local1 << ARG0
 	}
 	Return(Local0)
 }
diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c
@@ -567,15 +567,16 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
 	return ctx;
 }
 
-/* The region must be in memory marked as reserved.  If not implemented,
- * skip generating the information in the region.
- */
-__weak void bert_reserved_region(void **start, size_t *size)
+static void bert_reserved_region(void **start, size_t *size)
 {
-	printk(BIOS_ERR, "%s not implemented.  BERT region generation disabled\n",
-			__func__);
-	*start = NULL;
-	*size = 0;
+	if (!CONFIG(ACPI_BERT)) {
+		*start = NULL;
+		*size = 0;
+	} else {
+		*start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE);
+		*size = CONFIG_ACPI_BERT_SIZE;
+	}
+	printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size);
 }
 
 static void bert_storage_setup(void *unused)

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -115,8 +115,8 @@ _rom_mtrr_base = _rom_mtrr_mask;
 
 . = 0xffffff00;
 .illegal_globals . : {
-	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+	*(.data)
+	*(.data.*)
 }
 
 _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");

diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h
@@ -44,9 +44,6 @@
 #define CRASHLOG_RECORD_TYPE	0x2
 #define CRASHLOG_FW_ERR_REV	0x2
 
-/* Get implementation-specific reserved area for generating BERT info */
-void bert_reserved_region(void **start, size_t *size);
-
 /* Get the region where BERT error structures have been constructed for
  * generating the ACPI table
  */

diff --git a/src/arch/x86/include/arch/boot/boot.h b/src/arch/x86/include/arch/boot/boot.h
@@ -1,11 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef ASM_I386_BOOT_H
-#define ASM_I386_BOOT_H
-
-#define ELF_CLASS	ELFCLASS32
-#define ELF_DATA	ELFDATA2LSB
-#define ELF_ARCH	EM_386
+#ifndef X86_BOOT_H
+#define X86_BOOT_H
 
 #include <types.h>
 /*
@@ -15,7 +11,6 @@
  *
  * @noreturn
  */
-void protected_mode_jump(uint32_t func_ptr,
-			 uint32_t argument);
+void protected_mode_jump(uint32_t func_ptr, uint32_t argument);
 
-#endif /* ASM_I386_BOOT_H */
+#endif /* X86_BOOT_H */
diff --git a/src/arch/x86/include/arch/null_breakpoint.h b/src/arch/x86/include/arch/null_breakpoint.h
@@ -7,10 +7,15 @@
 
 /* Places data and instructions breakpoints at address zero. */
 void null_breakpoint_init(void);
+void null_breakpoint_disable(void);
 #else
 static inline void null_breakpoint_init(void)
 {
-    /* Not implemented */
+	/* Not implemented */
+}
+static inline void null_breakpoint_disable(void)
+{
+	/* Not implemented */
 }
 #endif
 #endif /* _NULL_BREAKPOINT_H_ */
diff --git a/src/arch/x86/null_breakpoint.c b/src/arch/x86/null_breakpoint.c
@@ -17,9 +17,9 @@ static int handle_fetch_breakpoint(struct breakpoint_handle handle, struct eregs
 static int handle_deref_breakpoint(struct breakpoint_handle handle, struct eregs *regs)
 {
 #if ENV_X86_64
-	printk(BIOS_ERR, "Null dereference at rip: 0x%llx \n", regs->rip);
+	printk(BIOS_ERR, "Null dereference at rip: 0x%llx\n", regs->rip);
 #else
-	printk(BIOS_ERR, "Null dereference at eip: 0x%x \n", regs->eip);
+	printk(BIOS_ERR, "Null dereference at eip: 0x%x\n", regs->eip);
 #endif
 	return CONFIG(DEBUG_NULL_DEREF_HALT);
 }
@@ -57,11 +57,16 @@ void null_breakpoint_init(void)
 	create_instruction_breakpoint();
 }
 
-static void null_breakpoint_disable(void *unused)
+void null_breakpoint_disable(void)
 {
 	breakpoint_remove(null_fetch_bp);
 	breakpoint_remove(null_deref_bp);
 }
 
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable, NULL);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable, NULL);
+static void null_breakpoint_disable_hook(void *unused)
+{
+	null_breakpoint_disable();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL);
diff --git a/src/arch/x86/romstage.c b/src/arch/x86/romstage.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <timestamp.h>
+#include <romstage_common.h>
+
+asmlinkage void car_stage_entry(void)
+{
+	timestamp_add_now(TS_ROMSTAGE_START);
+
+	/* Assumes the hardware was set up during the bootblock */
+	console_init();
+
+	romstage_main();
+}
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
@@ -516,6 +516,8 @@ static int smbios_write_type3(unsigned long *current, int handle)
 	return len;
 }
 
+#define MAX_CPUS_ENABLED (CONFIG_MAX_CPUS > 0xff ? 0xff : CONFIG_MAX_CPUS)
+
 static int smbios_write_type4(unsigned long *current, int handle)
 {
 	unsigned int cpu_voltage;
@@ -570,7 +572,7 @@ static int smbios_write_type4(unsigned long *current, int handle)
 		t->thread_count = t->thread_count2;
 	}
 	/* Assume we enable all the cores always, capped only by MAX_CPUS */
-	t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS);
+	t->core_enabled = MIN(t->core_count, MAX_CPUS_ENABLED);
 	t->core_enabled2 = MIN(t->core_count2, CONFIG_MAX_CPUS);
 	t->l1_cache_handle = 0xffff;
 	t->l2_cache_handle = 0xffff;

diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
@@ -142,7 +142,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
 {
 	unsigned long high_table_pointer;
 
-#define MAX_SMBIOS_SIZE (4 * KiB)
+#define MAX_SMBIOS_SIZE (32 * KiB)
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS,
 		MAX_SMBIOS_SIZE);

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
@@ -13,9 +13,10 @@
  * success. Allocate a new group or errors every 100 values.
  */
 enum cb_err {
-	CB_SUCCESS = 0,		/**< Call completed successfully */
-	CB_ERR = -1,		/**< Generic error code */
-	CB_ERR_ARG = -2,	/**< Invalid argument */
+	CB_SUCCESS = 0,			/**< Call completed successfully */
+	CB_ERR = -1,			/**< Generic error code */
+	CB_ERR_ARG = -2,		/**< Invalid argument */
+	CB_ERR_NOT_IMPLEMENTED = -3,	/**< Function not implemented */
 
 	/* NVRAM/CMOS errors */
 	CB_CMOS_OTABLE_DISABLED = -100,		/**< Option table disabled */

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
@@ -23,13 +23,14 @@ enum cbfs_type {
 	CBFS_TYPE_LEGACY_STAGE	= 0x10,
 	CBFS_TYPE_STAGE		= 0x11,
 	CBFS_TYPE_SELF		= 0x20,
-	CBFS_TYPE_FIT		= 0x21,
+	CBFS_TYPE_FIT_PAYLOAD	= 0x21,
 	CBFS_TYPE_OPTIONROM	= 0x30,
 	CBFS_TYPE_BOOTSPLASH	= 0x40,
 	CBFS_TYPE_RAW		= 0x50,
 	CBFS_TYPE_VSA		= 0x51,
 	CBFS_TYPE_MBI		= 0x52,
 	CBFS_TYPE_MICROCODE	= 0x53,
+	CBFS_TYPE_INTEL_FIT	= 0x54,
 	CBFS_TYPE_FSP		= 0x60,
 	CBFS_TYPE_MRC		= 0x61,
 	CBFS_TYPE_MMA		= 0x62,

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -11,6 +11,7 @@
 #define CBMEM_ID_ACPI_UCSI	0x55435349
 #define CBMEM_ID_AFTER_CAR	0xc4787a93
 #define CBMEM_ID_AGESA_RUNTIME	0x41474553
+#define CBMEM_ID_AGESA_MTRR	0xf08b4b9d
 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
 #define CBMEM_ID_CAR_GLOBALS	0xcac4e6a3
 #define CBMEM_ID_CBTABLE	0x43425442
@@ -90,6 +91,7 @@
 	{ CBMEM_ID_ACPI_HEST,		"ACPI HEST  " }, \
 	{ CBMEM_ID_ACPI_UCSI,		"ACPI UCSI  " }, \
 	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
+	{ CBMEM_ID_AGESA_MTRR,		"AGESA MTRR " }, \
 	{ CBMEM_ID_AFTER_CAR,		"AFTER CAR  " }, \
 	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
 	{ CBMEM_ID_CAR_GLOBALS,		"CAR GLOBALS" }, \

diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h
@@ -5,34 +5,34 @@
 
 #ifndef __packed
 #if defined(__WIN32) || defined(__WIN64)
-#define __packed __attribute__((gcc_struct, packed))
+#define __packed __attribute__((__gcc_struct__, __packed__))
 #else
-#define __packed __attribute__((packed))
+#define __packed __attribute__((__packed__))
 #endif
 #endif
 
 #ifndef __aligned
-#define __aligned(x) __attribute__((aligned(x)))
+#define __aligned(x) __attribute__((__aligned__(x)))
 #endif
 
-#ifndef __always_unused
-#define __always_unused __attribute__((unused))
+#ifndef __unused
+#define __unused __attribute__((__unused__))
 #endif
 
 #ifndef __must_check
-#define __must_check __attribute__((warn_unused_result))
+#define __must_check __attribute__((__warn_unused_result__))
 #endif
 
 #ifndef __weak
-#define __weak __attribute__((weak))
+#define __weak __attribute__((__weak__))
 #endif
 
 #ifndef __noreturn
-#define __noreturn __attribute__((noreturn))
+#define __noreturn __attribute__((__noreturn__))
 #endif
 
 #ifndef __always_inline
-#define __always_inline inline __attribute__((always_inline))
+#define __always_inline inline __attribute__((__always_inline__))
 #endif
 
 #ifndef __fallthrough

diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
@@ -20,8 +20,7 @@
  * DOCUMENTATION:
  * Please document any and all post codes using Doxygen style comments. We
  * want to be able to generate a verbose enough documentation that is useful
- * during debugging. Failure to do so will result in your patch being rejected
- * without any explanation or effort on part of the maintainers.
+ * during debugging.
  *
  */
 

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -86,6 +86,7 @@ enum {
 	LB_TAG_ACPI_CNVS		= 0x0041,
 	LB_TAG_TYPE_C_INFO		= 0x0042,
 	LB_TAG_ACPI_RSDP                = 0x0043,
+	LB_TAG_PCIE			= 0x0044,
 	/* The following options are CMOS-related */
 	LB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	LB_TAG_OPTION			= 0x00c9,
@@ -144,6 +145,14 @@ struct lb_memory {
 	struct lb_memory_range map[0];
 };
 
+struct lb_pcie {
+	uint32_t tag;
+	uint32_t size;
+	lb_uint64_t ctrl_base;		/* Base address of PCIe controller */
+};
+_Static_assert(_Alignof(struct lb_pcie) == 4,
+	       "lb_uint64_t alignment doesn't work as expected for struct lb_pcie!");
+
 struct lb_hwrpb {
 	uint32_t tag;
 	uint32_t size;

diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
@@ -34,10 +34,6 @@
 	const __typeof__(((type *)0)->member) *__mptr = (ptr);	\
 	(type *)((char *)__mptr - offsetof(type, member)); })
 
-#ifndef __unused
-#define __unused __attribute__((unused))
-#endif
-
 #ifndef alloca
 #define alloca(x) __builtin_alloca(x)
 #endif

diff --git a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h
@@ -17,8 +17,9 @@
 enum {
 	MMC_STATUS_NEED_RESET = 0,
 	MMC_STATUS_CMD1_READY_OR_IN_PROGRESS,
-	MMC_STATUS_CMD1_READY,
+	MMC_STATUS_CMD1_READY,		/* Byte mode */
 	MMC_STATUS_CMD1_IN_PROGRESS,
+	MMC_STATUS_CMD1_READY_HCS,	/* Sector mode (High capacity support) */
 };
 
 struct mmc_command {

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -169,8 +169,8 @@ enum timestamp_id {
 	TS_CRHV_BOOT = 1200,
 	TS_CRHV_PLATFORM_INIT = 1201,
 	TS_CRHV_SERVICES_STARTED = 1202,
-	TS_CRHV_HW_PASSTRHOUGH_START = 1203,
-	TS_CRHV_HW_PASSTRHOUGH_END = 1204,
+	TS_CRHV_HW_PASSTHROUGH_START = 1203,
+	TS_CRHV_HW_PASSTHROUGH_END = 1204,
 	TS_CRHV_PSTORE_START = 1205,
 	TS_CRHV_PSTORE_END = 1206,
 	TS_CRHV_VMM_START = 1207,
@@ -348,10 +348,10 @@ static const struct timestamp_id_to_name {
 	TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
 	TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),
 	TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"),
-	TS_NAME_DEF(TS_CRHV_HW_PASSTRHOUGH_START, TS_CRHV_HW_PASSTRHOUGH_END,
-		    "hypervisor hardware passtrough setup start"),
-	TS_NAME_DEF(TS_CRHV_HW_PASSTRHOUGH_END, 0,
-		    "hypervisor hardware passtrhough setup complete"),
+	TS_NAME_DEF(TS_CRHV_HW_PASSTHROUGH_START, TS_CRHV_HW_PASSTHROUGH_END,
+		    "hypervisor hardware passthrough setup start"),
+	TS_NAME_DEF(TS_CRHV_HW_PASSTHROUGH_END, 0,
+		    "hypervisor hardware passthrough setup complete"),
 	TS_NAME_DEF(TS_CRHV_PSTORE_START, TS_CRHV_PSTORE_END, "hypervisor pstore init start"),
 	TS_NAME_DEF(TS_CRHV_PSTORE_END, 0, "hypervisor pstore init complete"),
 	TS_NAME_DEF(TS_CRHV_VMM_START, 0, "hypervisor OS VMM start"),

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
@@ -37,7 +37,7 @@ endif
 # updates are wrapped in a container, like AMD's microcode update container. If
 # there is only one microcode binary (i.e. one container), then we don't have
 # this issue, and this rule will continue to work.
-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
+$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) $(DOTCONFIG)
 	for bin in $(cpu_microcode_bins); do \
 		if [ ! -f "$$bin" ]; then \
 			echo "Microcode error: $$bin does not exist"; \
@@ -50,10 +50,10 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
 		fi; \
 		false; \
 	fi
-	$(if $^,,false) # fail if no file is given at all
+	$(if $(cpu_microcode_bins),,false) # fail if no file is given at all
 	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
 	@echo $(cpu_microcode_bins)
-	cat $^ > $@
+	cat $(cpu_microcode_bins) > $@
 
 cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
 cpu_microcode_blob.bin-type := microcode

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
@@ -13,6 +13,7 @@ config CPU_AMD_AGESA
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SSE2
+	select CACHE_MRC_SETTINGS
 
 if CPU_AMD_AGESA
 
@@ -44,14 +45,6 @@ config ENABLE_MRC_CACHE
 	  Try to restore memory training results
 	  from non-volatile memory.
 
-config S3_DATA_POS
-	hex
-	default 0xFFFF0000
-
-config S3_DATA_SIZE
-	int
-	default 8192
-
 endif # CPU_AMD_AGESA
 
 source "src/cpu/amd/agesa/family14/Kconfig"

diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
@@ -3,18 +3,3 @@
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
-
-ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
-
-$(obj)/coreboot_s3nv.rom: $(obj)/config.h
-	echo "    S3 NVRAM   $(CONFIG_S3_DATA_POS) (S3 storage area)"
-	# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
-	printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp
-	mv $@.tmp $@
-
-cbfs-files-y += s3nv
-s3nv-file := $(obj)/coreboot_s3nv.rom
-s3nv-position := $(CONFIG_S3_DATA_POS)
-s3nv-type := raw
-
-endif # CONFIG_HAVE_ACPI_RESUME == y
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
@@ -7,14 +7,14 @@
 #include <arch/symbols.h>
 #include <commonlib/helpers.h>
 #include <program_loading.h>
-#include <timestamp.h>
+#include <romstage_common.h>
 #include <security/vboot/vboot_common.h>
 
 /* If we do not have a constrained _car_stack region size, use the
    following as a guideline for acceptable stack usage. */
 #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
 
-static void romstage_main(void)
+void __noreturn romstage_main(void)
 {
 	int i;
 	const int num_guards = 64;
@@ -54,14 +54,5 @@ static void romstage_main(void)
 
 	prepare_and_run_postcar();
 	/* We do not return here. */
-}
-
-asmlinkage void car_stage_entry(void)
-{
-	timestamp_add_now(TS_ROMSTAGE_START);
-
-	/* Assumes the hardware was set up during the bootblock */
-	console_init();
-
-	romstage_main();
+	die("failed to load postcar\n");
 }
diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc
@@ -8,7 +8,7 @@ bootblock-y += fit.c
 
 cbfs-files-y += intel_fit
 intel_fit-file := fit_table.c:struct
-intel_fit-type := raw
+intel_fit-type := intel_fit
 intel_fit-align := 16
 
 $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
@@ -41,7 +41,7 @@ endif # FIT_ENTRY
 
 cbfs-files-y += intel_fit_ts
 intel_fit_ts-file := fit_table.c:struct
-intel_fit_ts-type := raw
+intel_fit_ts-type := intel_fit
 intel_fit_ts-align := 16
 
 endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK

diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
@@ -5,3 +5,13 @@ config MICROCODE_UPDATE_PRE_RAM
 	help
 	  Select this option if you want to update the microcode
 	  during the cache as RAM setup.
+
+config RELOAD_MICROCODE_PATCH
+	bool
+	default n
+	help
+	  Select this option if SoC recommends to re-load microcode
+	  patch as part of CPU multiprocessor initialization process.
+	  This feature is mostly required with Intel latest generation
+	  processors starting with Alder Lake (with modified MCHECK init
+	  flow).
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
@@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_F2X
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select SMM_ASEG
 	select CPU_INTEL_COMMON
+	select SSE2
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
@@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_F3X
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
+	select SSE2
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
@@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_F4X
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select SSE2
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
@@ -10,7 +10,6 @@ config CPU_QEMU_X86
 
 if CPU_QEMU_X86
 
-# coreboot i440fx does not support SMM
 choice
 	prompt "AP init"
 	default CPU_QEMU_X86_LAPIC_INIT
@@ -24,6 +23,7 @@ config CPU_QEMU_X86_PARALLEL_MP
 
 endchoice
 
+# coreboot i440fx does not support SMM
 choice
 	prompt "SMM support"
 	default CPU_QEMU_X86_ASEG_SMM
@@ -35,7 +35,6 @@ config CPU_QEMU_X86_NO_SMM
 
 config CPU_QEMU_X86_ASEG_SMM
 	bool "SMM in ASEG"
-	depends on CPU_QEMU_X86_LAPIC_INIT
 	select SMM_ASEG
 
 config CPU_QEMU_X86_TSEG_SMM

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -21,8 +21,20 @@ config PARALLEL_MP_AP_WORK
 config LEGACY_SMP_INIT
 	bool
 
+config DEFAULT_X2APIC
+	def_bool n
+	help
+	  Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC.
+
+config DEFAULT_X2APIC_RUNTIME
+	def_bool n
+	help
+	  Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_RUNTIME.
+
 choice LAPIC_ACCESS_MODE
 	prompt "APIC operation mode"
+	default X2APIC_ONLY if DEFAULT_X2APIC
+	default X2APIC_RUNTIME if DEFAULT_X2APIC_RUNTIME
 	default XAPIC_ONLY
 
 config XAPIC_ONLY
@@ -124,13 +136,6 @@ config SMM_LEGACY_ASEG
 
 if HAVE_SMI_HANDLER && !SMM_LEGACY_ASEG
 
-config SMM_MODULE_HEAP_SIZE
-	hex
-	default 0x4000
-	help
-	  This option determines the size of the heap within the SMM handler
-	  modules.
-
 config SMM_MODULE_STACK_SIZE
 	hex
 	default 0x800 if ARCH_RAMSTAGE_X86_64

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
@@ -673,9 +673,6 @@ struct mp_state {
 	int cpu_count;
 	uintptr_t perm_smbase;
 	size_t perm_smsize;
-	/* Size of the real CPU save state */
-	size_t smm_real_save_state_size;
-	/* Size of allocated CPU save state, MAX(real save state size, stub size) */
 	size_t smm_save_state_size;
 	uintptr_t reloc_start32_offset;
 	int do_smm;
@@ -756,13 +753,11 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params)
 		stub_params->apic_id_to_cpu[i] = cpu_get_apic_id(i);
 }
 
-static enum cb_err install_relocation_handler(int num_cpus, size_t real_save_state_size,
-				      size_t save_state_size)
+static enum cb_err install_relocation_handler(int num_cpus, size_t save_state_size)
 {
 	struct smm_loader_params smm_params = {
 		.num_cpus = num_cpus,
-		.real_cpu_save_state_size = real_save_state_size,
-		.per_cpu_save_state_size = save_state_size,
+		.cpu_save_state_size = save_state_size,
 		.num_concurrent_save_states = 1,
 		.handler = smm_do_relocation,
 	};
@@ -779,8 +774,7 @@ static enum cb_err install_relocation_handler(int num_cpus, size_t real_save_sta
 }
 
 static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase,
-				     size_t smsize, size_t real_save_state_size,
-				     size_t save_state_size)
+				     size_t smsize, size_t save_state_size)
 {
 	/*
 	 * All the CPUs will relocate to permanaent handler now. Set parameters
@@ -791,8 +785,7 @@ static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase,
 	 */
 	struct smm_loader_params smm_params = {
 		.num_cpus = num_cpus,
-		.real_cpu_save_state_size = real_save_state_size,
-		.per_cpu_save_state_size = save_state_size,
+		.cpu_save_state_size = save_state_size,
 		.num_concurrent_save_states = num_cpus,
 	};
 
@@ -809,8 +802,7 @@ static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase,
 /* Load SMM handlers as part of MP flight record. */
 static void load_smm_handlers(void)
 {
-	size_t real_save_state_size = mp_state.smm_real_save_state_size;
-	size_t smm_save_state_size = mp_state.smm_save_state_size;
+	const size_t save_state_size = mp_state.smm_save_state_size;
 
 	/* Do nothing if SMM is disabled.*/
 	if (!is_smm_enabled())
@@ -823,15 +815,13 @@ static void load_smm_handlers(void)
 	}
 
 	/* Install handlers. */
-	if (install_relocation_handler(mp_state.cpu_count, real_save_state_size,
-				       smm_save_state_size) != CB_SUCCESS) {
+	if (install_relocation_handler(mp_state.cpu_count, save_state_size) != CB_SUCCESS) {
 		printk(BIOS_ERR, "Unable to install SMM relocation handler.\n");
 		smm_disable();
 	}
 
 	if (install_permanent_handler(mp_state.cpu_count, mp_state.perm_smbase,
-				      mp_state.perm_smsize, real_save_state_size,
-				      smm_save_state_size) != CB_SUCCESS) {
+				      mp_state.perm_smsize, save_state_size) != CB_SUCCESS) {
 		printk(BIOS_ERR, "Unable to install SMM permanent handler.\n");
 		smm_disable();
 	}
@@ -1051,9 +1041,9 @@ enum cb_err mp_run_on_all_cpus_synchronously(void (*func)(void *), void *arg)
 	/* Run on BSP first. */
 	func(arg);
 
-	/* For up to 1 second for AP to finish previous work. */
+	/* For up to 1 second per AP (console can be slow) to finish previous work. */
 	return mp_run_on_aps_and_wait_for_complete(func, arg, MP_RUN_ON_ALL_CPUS,
-						1000 * USECS_PER_MSEC);
+						   1000 * USECS_PER_MSEC * global_num_aps);
 }
 
 enum cb_err mp_park_aps(void)
@@ -1090,26 +1080,11 @@ static struct mp_flight_record mp_steps[] = {
 	MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL),
 };
 
-static size_t smm_stub_size(void)
-{
-	extern unsigned char _binary_smmstub_start[];
-	struct rmodule smm_stub;
-
-	if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) {
-		printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__);
-		return 0;
-	}
-
-	return rmodule_memory_size(&smm_stub);
-}
-
 static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops)
 {
 	if (ops->get_smm_info != NULL)
 		ops->get_smm_info(&state->perm_smbase, &state->perm_smsize,
-				  &state->smm_real_save_state_size);
-
-	state->smm_save_state_size = MAX(state->smm_real_save_state_size, smm_stub_size());
+				  &state->smm_save_state_size);
 
 	/*
 	 * Make sure there is enough room for the SMM descriptor

diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
@@ -1,11 +1,5 @@
 ramstage-y	+= mtrr.c
 
-ramstage-y	+= mtrrlib.c
-postcar-y	+= mtrrlib.c
-romstage-y	+= mtrrlib.c
-bootblock-y	+= mtrrlib.c
-verstage_x86-y	+= mtrrlib.c
-
 romstage-y	+= earlymtrr.c
 bootblock-y	+= earlymtrr.c
 verstage_x86-y	+= earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
@@ -7,6 +7,66 @@
 #include <commonlib/bsd/helpers.h>
 #include <stdint.h>
 
+/* Get first available variable MTRR.
+ * Returns var# if available, else returns -1.
+ */
+int get_free_var_mtrr(void)
+{
+	msr_t maskm;
+	int vcnt;
+	int i;
+
+	vcnt = get_var_mtrr_count();
+
+	/* Identify the first var mtrr which is not valid. */
+	for (i = 0; i < vcnt; i++) {
+		maskm = rdmsr(MTRR_PHYS_MASK(i));
+		if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
+			return i;
+	}
+
+	/* No free var mtrr. */
+	return -1;
+}
+
+void set_var_mtrr(
+	unsigned int reg, unsigned int base, unsigned int size,
+	unsigned int type)
+{
+	/* Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
+	msr_t basem, maskm;
+
+	if (!IS_POWER_OF_2(size))
+		printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
+	if (size < 4 * KiB)
+		printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size);
+	if (base % size != 0)
+		printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base,
+		       size);
+
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRR_PHYS_BASE(reg), basem);
+	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
+	maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
+	wrmsr(MTRR_PHYS_MASK(reg), maskm);
+}
+
+void clear_all_var_mtrr(void)
+{
+	msr_t mtrr = {0, 0};
+	int vcnt;
+	int i;
+
+	vcnt = get_var_mtrr_count();
+
+	for (i = 0; i < vcnt; i++) {
+		wrmsr(MTRR_PHYS_MASK(i), mtrr);
+		wrmsr(MTRR_PHYS_BASE(i), mtrr);
+	}
+}
+
 void var_mtrr_context_init(struct var_mtrr_context *ctx)
 {
 	ctx->max_var_mtrrs = get_var_mtrr_count();

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
@@ -9,6 +9,7 @@
  */
 
 #include <stddef.h>
+#include <stdint.h>
 #include <string.h>
 #include <bootstate.h>
 #include <commonlib/helpers.h>
@@ -860,11 +861,6 @@ void x86_mtrr_check(void)
 
 static bool put_back_original_solution;
 
-void need_restore_mtrr(void)
-{
-	put_back_original_solution = true;
-}
-
 void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 {
 	const struct range_entry *r;
@@ -873,6 +869,28 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	struct memranges addr_space;
 	const int above4gb = 1; /* Cover above 4GiB by default. */
 	int address_bits;
+	static struct temp_range {
+		uintptr_t begin;
+		size_t size;
+		int type;
+	} temp_ranges[10];
+
+	if (size == 0)
+		return;
+
+	int i;
+	for (i = 0; i < ARRAY_SIZE(temp_ranges); i++) {
+		if (temp_ranges[i].size == 0) {
+			temp_ranges[i].begin = begin;
+			temp_ranges[i].size = size;
+			temp_ranges[i].type = type;
+			break;
+		}
+	}
+	if (i == ARRAY_SIZE(temp_ranges)) {
+		printk(BIOS_ERR, "Out of temporary ranges for MTRR use\n");
+		return;
+	}
 
 	/* Make a copy of the original address space and tweak it with the
 	 * provided range. */
@@ -891,7 +909,11 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 	}
 
 	/* Place new range into the address space. */
-	memranges_insert(&addr_space, begin, size, type);
+	for (i = 0; i < ARRAY_SIZE(temp_ranges); i++) {
+		if (temp_ranges[i].size != 0)
+			memranges_insert(&addr_space, temp_ranges[i].begin,
+					 temp_ranges[i].size, temp_ranges[i].type);
+	}
 
 	print_physical_address_space(&addr_space, "TEMPORARY");
 
@@ -908,7 +930,7 @@ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type)
 			(long long)begin, (long long)begin + size - 1,
 			(long long)size, type);
 	else
-		need_restore_mtrr();
+		put_back_original_solution = true;
 
 	memranges_teardown(&addr_space);
 }

diff --git a/src/cpu/x86/mtrr/mtrrlib.c b/src/cpu/x86/mtrr/mtrrlib.c
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
@@ -67,9 +67,9 @@ $(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/sm
 # C-based SMM handler.
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32))
+$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, 0,x86_32))
 else
-$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64))
+$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, 0,x86_64))
 endif
 
 $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod

diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
diff --git a/src/device/Kconfig b/src/device/Kconfig
@@ -421,6 +421,7 @@ config WANT_LINEAR_FRAMEBUFFER
 	bool
 	default y if CHROMEOS
 	default y if PAYLOAD_TIANOCORE
+	default y if COREDOOM_SECONDARY_PAYLOAD
 
 choice
 	prompt "Framebuffer mode"

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -932,3 +932,12 @@ const char *dev_path_name(enum device_path_type type)
 		type_name = type_names[type];
 	return type_name;
 }
+
+void log_resource(const char *type, const struct device *dev, const struct resource *res,
+			const char *srcfile, const int line)
+{
+	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%lx, base: 0x%llx, "
+			  "end: 0x%llx, size_kb: 0x%llx\n",
+			  srcfile, line, type, dev_path(dev), res->index, res->base,
+			  resource_end(res), res->size / KiB);
+}
diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c
@@ -6,6 +6,12 @@
 #include <device/i2c_bus.h>
 #include <commonlib/endian.h>
 
+bool i2c_dev_detect(struct device *dev, unsigned int addr)
+{
+	struct i2c_msg seg = { .flags = 0, .slave = addr, .buf = NULL, .len = 0 };
+	return dev->ops->ops_i2c_bus->transfer(dev, &seg, 0) == 0;
+}
+
 struct bus *i2c_link(const struct device *const dev)
 {
 	if (!dev || !dev->bus)
@@ -19,14 +25,15 @@ struct bus *i2c_link(const struct device *const dev)
 		    (parent->ops->ops_i2c_bus || parent->ops->ops_smbus_bus))
 			break;
 
-		if (parent && parent->bus)
+		if (parent && parent->bus && link != parent->bus)
 			link = parent->bus;
 		else
 			link = NULL;
 	}
 
 	if (!link)
-		printk(BIOS_ALERT, "%s Cannot find I2C or SMBus bus operations", dev_path(dev));
+		printk(BIOS_ALERT, "%s Cannot find I2C or SMBus bus operations\n",
+				dev_path(dev));
 
 	return link;
 }

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
@@ -423,7 +423,9 @@ static void configure_adjustable_base(const struct device *dev,
 	res->align = max_requested_bits;
 	res->gran = max_requested_bits;
 	res->limit = (res->flags & IORESOURCE_PCI64) ? UINT64_MAX : UINT32_MAX;
-	res->flags |= IORESOURCE_PCIE_RESIZABLE_BAR;
+	res->flags |= (res->flags & IORESOURCE_PCI64) ?
+		IORESOURCE_PCIE_RESIZABLE_BAR | IORESOURCE_ABOVE_4G :
+		IORESOURCE_PCIE_RESIZABLE_BAR;
 
 	printk(BIOS_INFO, "%s: Adjusting resource index %lu: base: %llx size: %llx "
 	       "align: %d gran: %d limit: %llx\n",

diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c
@@ -129,7 +129,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt)
 
 AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-	if (!ENV_ROMSTAGE)
+	if (!ENV_RAMINIT)
 		return AGESA_UNSUPPORTED;
 
 	return AmdMemoryReadSPD (Func, Data, ConfigPtr);
@@ -139,7 +139,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
 
-	if (!ENV_ROMSTAGE)
+	if (!ENV_RAMINIT)
 		return AGESA_UNSUPPORTED;
 
 	if (info->MemChannelId > 0)

diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c
@@ -1,62 +1,32 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <spi-generic.h>
-#include <spi_flash.h>
 #include <string.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <mrc_cache.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <AGESA.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
-typedef enum {
-	S3DataTypeNonVolatile = 0,	///< NonVolatile Data Type
-	S3DataTypeMTRR			///< MTRR storage
-} S3_DATA_TYPE;
-
-/* The size needs to be 4k aligned, which is the sector size of most flashes. */
-#define S3_DATA_MTRR_SIZE			0x1000
-#define S3_DATA_NONVOLATILE_SIZE	0x1000
-
-#if CONFIG(HAVE_ACPI_RESUME) && \
-	(S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
-#error "Please increase the value of S3_DATA_SIZE"
-#endif
-
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len)
-{
-	/* FIXME: Find file from CBFS. */
-	u32 s3_data = CONFIG_S3_DATA_POS;
-
-	switch (S3DataType) {
-	case S3DataTypeMTRR:
-		*pos = s3_data;
-		*len = S3_DATA_MTRR_SIZE;
-		break;
-	case S3DataTypeNonVolatile:
-		*pos = s3_data + S3_DATA_MTRR_SIZE;
-		*len = S3_DATA_NONVOLATILE_SIZE;
-		break;
-	default:
-		*pos = 0;
-		*len = 0;
-		break;
-	}
-}
+/* Training data versioning is not supported or tracked. */
+#define DEFAULT_MRC_VERSION 0
 
 AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock)
 {
-	uintptr_t pos, size;
-	get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
+	void *nv_storage = NULL;
+	size_t nv_storage_size = 0;
 
-	u32 len = *(u32*)pos;
+	nv_storage = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION,
+						 &nv_storage_size);
 
-	/* Test for uninitialized s3nv data in SPI. */
-	if (len == 0 || len == (u32)-1ULL)
-		return AGESA_FATAL;
+	if (nv_storage == NULL || nv_storage_size == 0) {
+		printk(BIOS_ERR, "%s: No valid MRC cache!\n", __func__);
+		return AGESA_CRITICAL;
+	}
+
+	dataBlock->NvStorage = nv_storage;
+	dataBlock->NvStorageSize = nv_storage_size;
 
-	dataBlock->NvStorageSize = len;
-	dataBlock->NvStorage = (void *) (pos + sizeof(u32));
 	return AGESA_SUCCESS;
 }
 
@@ -77,47 +47,13 @@ AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock)
 	return AGESA_SUCCESS;
 }
 
-#if ENV_RAMSTAGE
-
-static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
-{
-#if CONFIG(SPI_FLASH)
-	struct spi_flash flash;
-
-	spi_init();
-	if (spi_flash_probe(0, 0, &flash))
-		return -1;
-
-	spi_flash_volatile_group_begin(&flash);
-
-	spi_flash_erase(&flash, pos, size);
-	spi_flash_write(&flash, pos, sizeof(len), &len);
-	spi_flash_write(&flash, pos + sizeof(len), len, buf);
-
-	spi_flash_volatile_group_end(&flash);
-	return 0;
-#else
-	return -1;
-#endif
-}
-
-static u8 MTRRStorage[S3_DATA_MTRR_SIZE];
-
 AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock)
 {
-	u32 MTRRStorageSize = 0;
-	uintptr_t pos, size;
-
-	/* To be consumed in AmdInitResume. */
-	get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
-	if (size && dataBlock->NvStorageSize)
-		spi_SaveS3info(pos, size, dataBlock->NvStorage,
-			dataBlock->NvStorageSize);
-	else
-		printk(BIOS_EMERG,
-			"Error: Cannot store memory training results in SPI.\n"
-			"Error: S3 resume will not be possible.\n"
-		);
+	if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION,
+				 dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) {
+		printk(BIOS_ERR, "%s: Failed to stash MRC data\n", __func__);
+		return AGESA_CRITICAL;
+	}
 
 	/* To be consumed in AmdS3LateRestore. */
 	char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH);
@@ -127,24 +63,7 @@ AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock)
 	}
 
 	/* Collect MTRR setup. */
-	backup_mtrr(MTRRStorage, &MTRRStorageSize);
-
-	/* To be consumed in restore_mtrr, CPU enumeration in ramstage. */
-	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
-	if (size && MTRRStorageSize)
-		spi_SaveS3info(pos, size, MTRRStorage, MTRRStorageSize);
+	backup_mtrr();
 
 	return AGESA_SUCCESS;
 }
-
-#endif /* ENV_RAMSTAGE */
-
-const void *OemS3Saved_MTRR_Storage(void)
-{
-	uintptr_t pos, size;
-	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
-	if (!size)
-		return NULL;
-
-	return (void *)(pos + sizeof(UINT32));
-}
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
@@ -13,6 +13,7 @@
 #include <smp/node.h>
 #include <string.h>
 #include <timestamp.h>
+#include <romstage_common.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
@@ -31,16 +32,12 @@ static void fill_sysinfo(struct sysinfo *cb)
  */
 static void ap_romstage_main(void);
 
-static void romstage_main(void)
+void __noreturn romstage_main(void)
 {
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
 	int cbmem_initted = 0;
 
-	timestamp_add_now(TS_ROMSTAGE_START);
-
-	console_init();
-
 	printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n",
 	       initial_lapicid(), cpuid_eax(1));
 
@@ -79,6 +76,7 @@ static void romstage_main(void)
 
 	prepare_and_run_postcar();
 	/* We do not return. */
+	die("failed to load postcar\n");
 }
 
 static void ap_romstage_main(void)
@@ -96,11 +94,6 @@ static void ap_romstage_main(void)
 	halt();
 }
 
-asmlinkage void car_stage_entry(void)
-{
-	romstage_main();
-}
-
 void *cbmem_top_chipset(void)
 {
 	/* Top of CBMEM is at highest usable DRAM address below 4GiB. */

diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
@@ -1,121 +1,88 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
+#include <cbmem.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <string.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
-static void write_mtrr(u8 **p_nvram_pos, unsigned int idx)
+/* TODO: Do we want MTRR_DEF_TYPE_MSR too? */
+static const uint32_t msr_backup[] = {
+	MTRR_FIX_64K_00000,
+	MTRR_FIX_16K_80000,
+	MTRR_FIX_16K_A0000,
+	MTRR_FIX_4K_C0000,
+	MTRR_FIX_4K_C8000,
+	MTRR_FIX_4K_D0000,
+	MTRR_FIX_4K_D8000,
+	MTRR_FIX_4K_E0000,
+	MTRR_FIX_4K_E8000,
+	MTRR_FIX_4K_F0000,
+	MTRR_FIX_4K_F8000,
+	MTRR_PHYS_BASE(0),
+	MTRR_PHYS_MASK(0),
+	MTRR_PHYS_BASE(1),
+	MTRR_PHYS_MASK(1),
+	MTRR_PHYS_BASE(2),
+	MTRR_PHYS_MASK(2),
+	MTRR_PHYS_BASE(3),
+	MTRR_PHYS_MASK(3),
+	MTRR_PHYS_BASE(4),
+	MTRR_PHYS_MASK(4),
+	MTRR_PHYS_BASE(5),
+	MTRR_PHYS_MASK(5),
+	MTRR_PHYS_BASE(6),
+	MTRR_PHYS_MASK(6),
+	MTRR_PHYS_BASE(7),
+	MTRR_PHYS_MASK(7),
+	SYSCFG_MSR,
+	TOP_MEM,
+	TOP_MEM2,
+};
+
+void backup_mtrr(void)
 {
-	msr_t  msr_data;
-	msr_data = rdmsr(idx);
-
-	memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
-	*p_nvram_pos += sizeof(msr_data);
-}
-
-void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
-{
-	u8 *nvram_pos = mtrr_store;
-	msr_t  msr_data;
-	u32 i;
+	msr_t syscfg_msr;
+	msr_t *mtrr_save = (msr_t *)cbmem_add(CBMEM_ID_AGESA_MTRR,
+					      sizeof(msr_t) * ARRAY_SIZE(msr_backup));
+	if (!mtrr_save)
+		return;
 
 	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYSCFG_MSR);
-	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, msr_data);
-
-	/* Fixed MTRRs */
-	write_mtrr(&nvram_pos, MTRR_FIX_64K_00000);
-	write_mtrr(&nvram_pos, MTRR_FIX_16K_80000);
-	write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000);
+	syscfg_msr = rdmsr(SYSCFG_MSR);
+	syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, syscfg_msr);
 
-	for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++)
-		write_mtrr(&nvram_pos, i);
+	for (int i = 0; i < ARRAY_SIZE(msr_backup); i++)
+		*mtrr_save++ = rdmsr(msr_backup[i]);
 
 	/* Disable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYSCFG_MSR);
-	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, msr_data);
-
-	/* Variable MTRRs */
-	for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++)
-		write_mtrr(&nvram_pos, i);
-
-	/* SYSCFG_MSR */
-	write_mtrr(&nvram_pos, SYSCFG_MSR);
-	/* TOM */
-	write_mtrr(&nvram_pos, TOP_MEM);
-	/* TOM2 */
-	write_mtrr(&nvram_pos, TOP_MEM2);
-
-	*mtrr_store_size = nvram_pos - (u8*) mtrr_store;
+	syscfg_msr = rdmsr(SYSCFG_MSR);
+	syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, syscfg_msr);
 }
 
 void restore_mtrr(void)
 {
-	volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage();
-	u32 msr;
-	msr_t msr_data;
+	msr_t syscfg_msr;
+	msr_t *mtrr_save = (msr_t *)cbmem_find(CBMEM_ID_AGESA_MTRR);
 
-	if (!msrPtr)
+	if (!mtrr_save)
 		return;
 
-	disable_cache();
-
 	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYSCFG_MSR);
-	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, msr_data);
-
-	/* Now restore the Fixed MTRRs */
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(MTRR_FIX_64K_00000, msr_data);
-
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(MTRR_FIX_16K_80000, msr_data);
+	syscfg_msr = rdmsr(SYSCFG_MSR);
+	syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, syscfg_msr);
 
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(MTRR_FIX_16K_A0000, msr_data);
-
-	for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) {
-		msr_data.lo = *msrPtr;
-		msrPtr ++;
-		msr_data.hi = *msrPtr;
-		msrPtr ++;
-		wrmsr(msr, msr_data);
-	}
+	for (int i = 0; i < ARRAY_SIZE(msr_backup); i++)
+		wrmsr(msr_backup[i], *mtrr_save++);
 
 	/* Disable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYSCFG_MSR);
-	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, msr_data);
-
-	/* Restore the Variable MTRRs */
-	for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) {
-		msr_data.lo = *msrPtr;
-		msrPtr ++;
-		msr_data.hi = *msrPtr;
-		msrPtr ++;
-		wrmsr(msr, msr_data);
-	}
-
-	/* Restore SYSCFG MTRR */
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(SYSCFG_MSR, msr_data);
+	syscfg_msr = rdmsr(SYSCFG_MSR);
+	syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, syscfg_msr);
 }
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c
@@ -18,7 +18,7 @@
 #include "Dispatcher.h"
 #endif
 
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
 #include <PlatformMemoryConfiguration.h>
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
 #endif
@@ -262,7 +262,7 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func)
 	if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id)
 		timestamp_add_now(task.ts_entry_id);
 
-	if (ENV_ROMSTAGE)
+	if (ENV_RAMINIT)
 		final = romstage_dispatch(cb, func, StdHeader);
 
 	if (ENV_RAMSTAGE)

diff --git a/src/drivers/i2c/cs35l53/chip.h b/src/drivers/i2c/cs35l53/chip.h
@@ -48,6 +48,12 @@ struct drivers_i2c_cs35l53_config {
 
 	const char *sub; /* SUB ID to uniquely identify system */
 
+	/* Device Description */
+	const char *desc;
+
+	/* Identifier for chips */
+	uint32_t uid;
+
 	/* Interrupt configuration */
 	struct acpi_irq irq;
 

diff --git a/src/drivers/i2c/cs35l53/cs35l53.c b/src/drivers/i2c/cs35l53/cs35l53.c
@@ -33,8 +33,11 @@ static void cs35l53_fill_ssdt(const struct device *dev)
 	acpigen_write_scope(scope);
 	acpigen_write_device(acpi_device_name(dev));
 	acpigen_write_name_string("_HID", CS35L53_ACPI_HID);
-	acpigen_write_name_integer("_UID", 0);
-	acpigen_write_name_string("_DDN", dev->chip_ops->name);
+	acpigen_write_name_integer("_UID", config->uid);
+	if (config->desc == NULL)
+		acpigen_write_name_string("_DDN", dev->chip_ops->name);
+	else
+		acpigen_write_name_string("_DDN", config->desc);
 	acpigen_write_name_string("_SUB", config->sub);
 	acpigen_write_STA(acpi_device_status(dev));
 

diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c
@@ -358,6 +358,7 @@ static enum cb_err _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segm
 	struct dw_i2c_regs *regs;
 	size_t byte;
 	enum cb_err ret = CB_ERR;
+	bool seg_zero_len = segments->len == 0;
 
 	regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
 	if (!regs) {
@@ -374,6 +375,10 @@ static enum cb_err _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segm
 
 	dw_i2c_enable(regs);
 
+	if (seg_zero_len)
+		/* stop immediately */
+		write32(&regs->cmd_data, CMD_DATA_STOP);
+
 	/* Process each segment */
 	while (count--) {
 		if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) {
@@ -424,8 +429,8 @@ static enum cb_err _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segm
 
 	/* Check TX abort */
 	if (read32(&regs->raw_intr_stat) & INTR_STAT_TX_ABORT) {
-		printk(BIOS_ERR, "I2C TX abort detected (%08x)\n",
-		       read32(&regs->tx_abort_source));
+		printk(seg_zero_len ? BIOS_SPEW : BIOS_ERR, "I2C TX abort detected (%08x)\n",
+			read32(&regs->tx_abort_source));
 		/* clear INTR_STAT_TX_ABORT */
 		read32(&regs->clear_tx_abrt_intr);
 		goto out;
@@ -462,7 +467,7 @@ static enum cb_err dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg,
 	size_t start;
 	uint16_t addr;
 
-	if (count == 0 || !msg)
+	if (!msg)
 		return -1;
 
 	/* Break up the transfers at the differing slave address boundary. */

diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h
@@ -31,6 +31,17 @@ struct drivers_i2c_generic_config {
 	 */
 	int probed;
 
+	/*
+	 * This flag will add a device property which will indicate
+	 * that coreboot should attempt to detect the device on the i2c
+	 * bus before generating a device entry in the SSDT.
+	 *
+	 * This can be used to declare a device that may not exist on
+	 * the board, for example to support multiple touchpads and/or
+	 * touchscreens.
+	 */
+	int detect;
+
 	/* GPIO used to indicate if this device is present */
 	unsigned int device_present_gpio;
 	unsigned int device_present_gpio_invert;

diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c
@@ -3,6 +3,7 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpigen.h>
 #include <console/console.h>
+#include <device/i2c_bus.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
 #include <device/path.h>
@@ -65,6 +66,17 @@ void i2c_generic_fill_ssdt(const struct device *dev,
 		return;
 	}
 
+	if (config->detect) {
+		struct device *const busdev = i2c_busdev(dev);
+		if (!i2c_dev_detect(busdev, dev->path.i2c.device)) {
+			printk(BIOS_SPEW, "%s: %s at %s -- NOT FOUND, skipping\n",
+				path,
+				config->desc ? : dev->chip_ops->name,
+				dev_path(dev));
+			return;
+		}
+	}
+
 	/* Device */
 	acpigen_write_scope(scope);
 	acpigen_write_device(acpi_device_name(dev));

diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
@@ -34,7 +34,6 @@
 #define CR50_TIMEOUT_LONG_MS	2000	/* Long timeout while waiting for TPM */
 #define CR50_TIMEOUT_SHORT_MS	2	/* Short timeout during transactions */
 #define CR50_TIMEOUT_NOIRQ_MS	20	/* Timeout for TPM ready without IRQ */
-#define CR50_TIMEOUT_IRQ_MS	100	/* Timeout for TPM ready with IRQ */
 #define CR50_DID_VID		0x00281ae0L
 #define TI50_DID_VID		0x504a6666L
 
@@ -60,21 +59,6 @@ __weak int tis_plat_irq_status(void)
 	return 1;
 }
 
-/* Wait for interrupt to indicate the TPM is ready */
-static int cr50_i2c_wait_tpm_ready(void)
-{
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_IRQ_MS);
-
-	while (!tis_plat_irq_status())
-		if (stopwatch_expired(&sw)) {
-			printk(BIOS_ERR, "Cr50 i2c TPM IRQ timeout!\n");
-			return -1;
-		}
-	return 0;
-}
-
 /*
  * cr50_i2c_read() - read from TPM register
  *
@@ -103,7 +87,7 @@ static int cr50_i2c_read(uint8_t addr, uint8_t *buffer, size_t len)
 	}
 
 	/* Wait for TPM to be ready with response data */
-	if (cr50_i2c_wait_tpm_ready() < 0)
+	if (cr50_wait_tpm_ready() != CB_SUCCESS)
 		return -1;
 
 	/* Read response data from the TPM */
@@ -149,7 +133,7 @@ static int cr50_i2c_write(uint8_t addr, const uint8_t *buffer, size_t len)
 	}
 
 	/* Wait for TPM to be ready */
-	return cr50_i2c_wait_tpm_ready();
+	return cr50_wait_tpm_ready() == CB_SUCCESS ? 0 : -1;
 }
 
 /*

diff --git a/src/drivers/intel/fsp2_0/fsp_debug_event.c b/src/drivers/intel/fsp2_0/fsp_debug_event.c
@@ -12,7 +12,7 @@ static const uint8_t fsp_string_type_guid[16] = {
 
 static efi_return_status_t print_fsp_string_data(const efi_status_code_data_t *data)
 {
-	printk(BIOS_SPEW, "%s", ((efi_status_code_string_data *) data)->String.Ascii);
+	printk(get_log_level(), "%s", ((efi_status_code_string_data *) data)->String.Ascii);
 
 	return FSP_SUCCESS;
 }

diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -109,13 +109,13 @@ static void save_hob_list(int is_recovery)
 	*cbmem_loc = (uintptr_t)hob_list;
 }
 
-ROMSTAGE_CBMEM_INIT_HOOK(save_hob_list);
+CBMEM_CREATION_HOOK(save_hob_list);
 
 const void *fsp_get_hob_list(void)
 {
 	uint32_t *list_loc;
 
-	if (ENV_ROMSTAGE)
+	if (ENV_RAMINIT)
 		return fsp_hob_list_ptr;
 	list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME);
 	return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL;

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <security/vboot/antirollback.h>
+#include <arch/null_breakpoint.h>
 #include <arch/symbols.h>
 #include <assert.h>
 #include <cbfs.h>
@@ -11,17 +11,18 @@
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <memrange.h>
+#include <mode_switch.h>
 #include <mrc_cache.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
+#include <security/tpm/tspi.h>
+#include <security/vboot/antirollback.h>
+#include <security/vboot/vboot_common.h>
 #include <string.h>
 #include <symbols.h>
 #include <timestamp.h>
-#include <security/vboot/vboot_common.h>
-#include <security/tpm/tspi.h>
-#include <vb2_api.h>
 #include <types.h>
-#include <mode_switch.h>
+#include <vb2_api.h>
 
 static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
 
@@ -293,6 +294,8 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 	fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset);
 	fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
 
+	/* FSP disables the interrupt handler so remove debug exceptions temporarily  */
+	null_breakpoint_disable();
 	post_code(POST_FSP_MEMORY_INIT);
 	timestamp_add_now(TS_FSP_MEMORY_INIT_START);
 	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
@@ -301,6 +304,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
 						  (uintptr_t)fsp_get_hob_list_ptr());
 	else
 		status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
+	null_breakpoint_init();
 
 	post_code(POST_FSP_MEMORY_EXIT);
 	timestamp_add_now(TS_FSP_MEMORY_INIT_END);

diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <arch/null_breakpoint.h>
 #include <bootstate.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
@@ -75,10 +76,13 @@ static void fsp_notify(enum fsp_notify_phase phase)
 	timestamp_add_now(data->timestamp_before);
 	post_code(data->post_code_before);
 
+	/* FSP disables the interrupt handler so remove debug exceptions temporarily  */
+	null_breakpoint_disable();
 	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
 		ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params);
 	else
 		ret = fspnotify(&notify_params);
+	null_breakpoint_init();
 
 	timestamp_add_now(data->timestamp_after);
 	post_code(data->post_code_after);

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <arch/null_breakpoint.h>
 #include <bootsplash.h>
 #include <cbfs.h>
 #include <cbmem.h>
@@ -133,10 +134,13 @@ static void do_silicon_init(struct fsp_header *hdr)
 	timestamp_add_now(TS_FSP_SILICON_INIT_START);
 	post_code(POST_FSP_SILICON_INIT);
 
+	/* FSP disables the interrupt handler so remove debug exceptions temporarily  */
+	null_breakpoint_disable();
 	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
 		status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
 	else
 		status = silicon_init(upd);
+	null_breakpoint_init();
 
 	printk(BIOS_INFO, "FSPS returned %x\n", status);
 

diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
@@ -77,7 +77,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, void *fsp_file, size_
 		return CB_ERR;
 	}
 
-	if (ENV_ROMSTAGE)
+	if (ENV_RAMINIT)
 		soc_validate_fspm_header(hdr);
 
 	return CB_SUCCESS;
@@ -118,7 +118,7 @@ void fsp_handle_reset(uint32_t status)
 
 static inline bool fspm_env(void)
 {
-	if (ENV_ROMSTAGE)
+	if (ENV_RAMINIT)
 		return true;
 	return false;
 }

diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl
@@ -7,7 +7,7 @@
 	Method(BRID, 1, NotSerialized)
 	{
 		Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
-		If (LEqual (Local0, Ones))
+		If (Local0 == Ones)
 		{
 			Return (SizeOf(BRIG) - 1)
 		}
@@ -38,7 +38,7 @@
 			Notify (LCD0, 0x87)
 		} Else {
 			Store (BRID (XBQC ()), Local0)
-			If (LNotEqual (Local0, 2))
+			If (Local0 != 2)
 			{
 				Local0--
 			}
@@ -56,7 +56,7 @@
 			Notify (LCD0, 0x86)
 		} Else {
 			Store (BRID (XBQC ()), Local0)
-			If (LNotEqual (Local0, SizeOf(BRIG) - 1))
+			If (Local0 != SizeOf(BRIG) - 1)
 			{
 				Local0++
 			}

diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -42,25 +42,25 @@
 		 */
 		Method (XBCM, 1, Serialized)
 		{
-			If (LEqual(ASLS, Zero))
+			If (ASLS == 0)
 			{
 				Return (Ones)
 			}
-			If (LEqual(And(MBOX, 0x4), Zero))
+			If (And(MBOX, 0x4) == 0)
 			{
 				Return (Ones)
 			}
 
 			/* Always keep BCLP up to date, even if driver is not ready.
 			   It requires a full 8-bit brightness value. 255 = 100% */
 			Store (Arg0 * 255 / 100, Local1)
-			If (LGreater(Local1, 255)) {
+			If (Local1 > 255) {
 				Store (255, Local1)
 			}
 			/* also set valid bit */
 			Store (Or (Local1, 0x80000000), BCLP)
 
-			If (LEqual(ARDY, Zero))
+			If (ARDY == 0)
 			{
 				Return (Ones)
 			}
@@ -71,13 +71,13 @@
 			Store (0x1, ASLE)
 
 			Store (0x20, Local0)
-			While (LGreater(Local0, Zero))
+			While (Local0 > 0)
 			{
 				Sleep (1)
-				If (LEqual (And (ASLC, 0x2), 0)) {
+				If (And (ASLC, 0x2) == 0) {
 					/* Request has been processed, check status: */
 					And (ShiftRight (ASLC, 12), 0x3, Local1)
-					If (LEqual (Local1, 0)) {
+					If (Local1 == 0) {
 						Return (Zero)
 					} Else {
 						Return (Ones)
@@ -121,13 +121,13 @@
 
 			/* Local1: loop index (selectable values start at 2 in BRIG) */
 			Store (2, Local1)
-			While (LLess (Local1, SizeOf (BRIG) - 1)) {
+			While (Local1 < SizeOf (BRIG) - 1) {
 				/* Local[23]: adjacent values in BRIG */
 				Store (DeRefOf (BRIG[Local1]), Local2)
 				Store (DeRefOf (BRIG[Local1 + 1]), Local3)
 
-				If (LLess (Local0, Local3)) {
-					If (LLess (Local0, Local2) || LLess (Local0 - Local2, Local3 - Local0)) {
+				If (Local0 < Local3) {
+					If (Local0 < Local2 || Local0 - Local2 < Local3 - Local0) {
 						Return (Local2)
 					} Else {
 						Return (Local3)
@@ -144,7 +144,7 @@
 
 	Method (XBCM, 1, NotSerialized)
 	{
-		If (LEqual(^BOX3.XBCM (Arg0), Ones))
+		If (^BOX3.XBCM (Arg0) == Ones)
 		{
 			^LEGA.XBCM (Arg0)
 		}

diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
@@ -15,6 +15,7 @@
 #include <commonlib/endian.h>
 #include <console/console.h>
 #include <delay.h>
+#include <drivers/tpm/cr50.h>
 #include <endian.h>
 #include <security/tpm/tis.h>
 #include <string.h>
@@ -63,6 +64,9 @@ __weak int tis_plat_irq_status(void)
 {
 	static int warning_displayed;
 
+	if (!CONFIG(TPM_GOOGLE))
+		dead_code();
+
 	if (!warning_displayed) {
 		printk(BIOS_WARNING, "%s() not implemented, wasting 10ms to wait on"
 		       " Cr50!\n", __func__);
@@ -73,23 +77,6 @@ __weak int tis_plat_irq_status(void)
 	return 1;
 }
 
-/*
- * TPM may trigger a IRQ after finish processing previous transfer.
- * Waiting for this IRQ to sync TPM status.
- */
-static enum cb_err tpm_sync(void)
-{
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, 10);
-	while (!tis_plat_irq_status()) {
-		if (stopwatch_expired(&sw))
-			return CB_ERR;
-	}
-
-	return CB_SUCCESS;
-}
-
 /*
  * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte
  * header is sent to the TPM, the master waits til TPM is ready to continue.
@@ -113,7 +100,7 @@ static enum cb_err start_transaction(int read_write, size_t bytes, unsigned int
 
 		/* Wait for TPM to finish previous transaction if needed */
 		if (tpm_sync_needed) {
-			if (tpm_sync() != CB_SUCCESS)
+			if (cr50_wait_tpm_ready() != CB_SUCCESS)
 				printk(BIOS_ERR, "Timeout waiting for TPM IRQ!\n");
 
 			/*
@@ -431,8 +418,9 @@ int tpm2_init(struct spi_slave *spi_if)
 
 	memcpy(&spi_slave, spi_if, sizeof(*spi_if));
 
-	/* clear any pending IRQs */
-	tis_plat_irq_status();
+	/* Clear any pending IRQs. */
+	if (CONFIG(TPM_GOOGLE))
+		tis_plat_irq_status();
 
 	/*
 	 * 150 ms should be enough to synchronize with the TPM even under the

diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
@@ -229,6 +229,15 @@ static const struct spi_flash_part_id flash_table[] = {
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 4,
 	},
+	{
+		/* W25Q256JW */
+		.id[0]				= 0x6019,
+		.nr_sectors_shift		= 13,
+		.fast_read_dual_output_support	= 1,
+		.fast_read_dual_io_support	= 1,
+		.protection_granularity_shift	= 16,
+		.bp_bits			= 4,
+	},
 };
 
 static int do_spi_flash_cmd_read(const struct spi_slave *spi, const void *dout,

diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c
@@ -3,6 +3,7 @@
 #include <drivers/spi/tpm/tpm.h>
 #include <security/tpm/tis.h>
 #include <string.h>
+#include <timer.h>
 #include <types.h>
 
 #define CR50_DID_VID	0x00281ae0L
@@ -234,3 +235,18 @@ enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version)
 		*version = cr50_firmware_version;
 	return CB_SUCCESS;
 }
+
+enum cb_err cr50_wait_tpm_ready(void)
+{
+	struct stopwatch sw;
+
+	stopwatch_init_msecs_expire(&sw, CONFIG_GOOGLE_TPM_IRQ_TIMEOUT_MS);
+
+	while (!tis_plat_irq_status())
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "Cr50 TPM IRQ timeout!\n");
+			return CB_ERR;
+		}
+
+	return CB_SUCCESS;
+}
diff --git a/src/drivers/tpm/cr50.h b/src/drivers/tpm/cr50.h
@@ -21,4 +21,7 @@ enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version);
 /* Set the BOARD_CFG register depending on Cr50 Kconfigs */
 enum cb_err cr50_set_board_cfg(void);
 
+/* Wait for IRQ to indicate the TPM is ready */
+enum cb_err cr50_wait_tpm_ready(void);
+
 #endif /* __DRIVERS_TPM_CR50_H__ */
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
@@ -680,7 +680,7 @@ static void migrate_ehci_debug(int is_recovery)
 	struct ehci_debug_info *dbg_info_cbmem;
 	int rv;
 
-	if (ENV_ROMSTAGE) {
+	if (ENV_CREATES_CBMEM) {
 		/* Move state from CAR to CBMEM. */
 		struct ehci_debug_info *dbg_info = dbgp_ehci_info();
 		dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG,
@@ -706,9 +706,7 @@ static void migrate_ehci_debug(int is_recovery)
 		printk(BIOS_DEBUG, "usbdebug: " ENV_STRING " starting...\n");
 }
 
-ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug);
-POSTCAR_CBMEM_INIT_HOOK(migrate_ehci_debug);
-RAMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug);
+CBMEM_READY_HOOK(migrate_ehci_debug);
 
 int dbgp_ep_is_active(struct dbgp_pipe *pipe)
 {
@@ -728,7 +726,7 @@ struct dbgp_pipe *dbgp_console_input(void)
 void usbdebug_init(void)
 {
 	/* USB console init is done early in romstage, yet delayed to
-	 * CBMEM_INIT_HOOKs for postcar and ramstage as we recover state
+	 * CBMEM_READY_HOOKs for postcar and ramstage as we recover state
 	 * from CBMEM.
 	 */
 	if (CONFIG(USBDEBUG_IN_PRE_RAM)

diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c
@@ -8,8 +8,6 @@
 #include "usb_ch9.h"
 #include "ehci.h"
 
-#define dprintk printk
-
 #define USB_HUB_PORT_CONNECTION		0
 #define USB_HUB_PORT_ENABLED		1
 #define USB_HUB_PORT_RESET		4
@@ -144,13 +142,13 @@ static int probe_for_debug_descriptor(struct ehci_dbg_port *ehci_debug, struct d
 		if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType == USB_DT_DEBUG)
 			goto debug_dev_found;
 		else
-			dprintk(BIOS_INFO, "Invalid debug device descriptor.\n");
+			printk(BIOS_INFO, "Invalid debug device descriptor.\n");
 	}
 	if (devnum == 0) {
 		devnum = USB_DEBUG_DEVNUM;
 		goto debug_dev_retry;
 	} else {
-		dprintk(BIOS_INFO, "Could not find attached debug device.\n");
+		printk(BIOS_INFO, "Could not find attached debug device.\n");
 		return -1;
 	}
 debug_dev_found:
@@ -161,23 +159,23 @@ static int probe_for_debug_descriptor(struct ehci_dbg_port *ehci_debug, struct d
 			USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
 			USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
 		if (ret < 0) {
-			dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
+			printk(BIOS_INFO, "Could not move attached device to %d.\n",
 				USB_DEBUG_DEVNUM);
 			return -2;
 		}
 		devnum = USB_DEBUG_DEVNUM;
-		dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
+		printk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
 	}
 
 	/* Enable the debug interface */
 	ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
 		USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
 		USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n");
+		printk(BIOS_INFO, "Could not enable EHCI debug device.\n");
 		return -3;
 	}
-	dprintk(BIOS_INFO, "EHCI debug interface enabled.\n");
+	printk(BIOS_INFO, "EHCI debug interface enabled.\n");
 
 	pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint;
 	pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;
@@ -189,7 +187,7 @@ static int probe_for_debug_descriptor(struct ehci_dbg_port *ehci_debug, struct d
 small_write:
 	ret = dbgp_bulk_write_x(&pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
+		printk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
 		if (!configured) {
 			/* Send Set Configure request to device. This is required for FX2
 			   (CY7C68013) to transfer from USB state Addressed to Configured,
@@ -203,7 +201,7 @@ static int probe_for_debug_descriptor(struct ehci_dbg_port *ehci_debug, struct d
 		}
 		return -4;
 	}
-	dprintk(BIOS_INFO, "Test write done\n");
+	printk(BIOS_INFO, "Test write done\n");
 	return 0;
 }
 
@@ -251,27 +249,27 @@ static int probe_for_ftdi(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
 		USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
 		USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
+		printk(BIOS_INFO, "Could not move attached device to %d.\n",
 			USB_DEBUG_DEVNUM);
 			return -2;
 	}
 	devnum = USB_DEBUG_DEVNUM;
-	dprintk(BIOS_INFO, "EHCI debug device renamed to %d.\n", devnum);
+	printk(BIOS_INFO, "EHCI debug device renamed to %d.\n", devnum);
 
 	/* Send Set Configure request to device.  */
 	ret = dbgp_control_msg(ehci_debug, devnum,
 		USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
 		USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "FTDI set configuration failed.\n");
+		printk(BIOS_INFO, "FTDI set configuration failed.\n");
 		return -2;
 	}
 
 	ret = dbgp_control_msg(ehci_debug, devnum,
 		USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
 		FTDI_SIO_SET_BITMODE_REQUEST, 0, uart_if, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "FTDI SET_BITMODE failed.\n");
+		printk(BIOS_INFO, "FTDI SET_BITMODE failed.\n");
 		return -3;
 	}
 	ft232h_baud(&baud_value, &baud_index,
@@ -281,23 +279,23 @@ static int probe_for_ftdi(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
 		FTDI_SIO_SET_BAUDRATE_REQUEST,
 		baud_value, baud_index | uart_if, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "FTDI SET_BAUDRATE failed.\n");
+		printk(BIOS_INFO, "FTDI SET_BAUDRATE failed.\n");
 		return -3;
 	}
 	ret = dbgp_control_msg(ehci_debug, devnum,
 		USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
 		FTDI_SIO_SET_DATA_REQUEST,
 		0x0008, uart_if, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "FTDI SET_DATA failed.\n");
+		printk(BIOS_INFO, "FTDI SET_DATA failed.\n");
 		return -3;
 	}
 	ret = dbgp_control_msg(ehci_debug, devnum,
 		USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
 		FTDI_SIO_SET_FLOW_CTRL_REQUEST,
 		0x0000, uart_if, NULL, 0);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "FTDI SET_FLOW_CTRL failed.\n");
+		printk(BIOS_INFO, "FTDI SET_FLOW_CTRL failed.\n");
 		return -3;
 	}
 
@@ -309,10 +307,10 @@ static int probe_for_ftdi(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
 	/* Perform a small write. */
 	ret = dbgp_bulk_write_x(&pipe[DBGP_CONSOLE_EPOUT], "USB\r\n", 5);
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
+		printk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
 		return -4;
 	}
-	dprintk(BIOS_INFO, "Test write done\n");
+	printk(BIOS_INFO, "Test write done\n");
 	return 0;
 }
 
@@ -335,7 +333,7 @@ int dbgp_probe_gadget(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe)
 		ret = probe_for_debug_descriptor(ehci_debug, pipe);
 	}
 	if (ret < 0) {
-		dprintk(BIOS_INFO, "Could not enable debug dongle.\n");
+		printk(BIOS_INFO, "Could not enable debug dongle.\n");
 		return ret;
 	}
 

diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c
@@ -295,4 +295,4 @@ bool vpd_get_int(const char *const key, const enum vpd_region region, int *const
 	return true;
 }
 
-ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd)
+CBMEM_CREATION_HOOK(cbmem_add_cros_vpd);
diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c
@@ -119,6 +119,11 @@ static const unsigned short intel_pci_device_ids[] = {
 	PCI_DID_GrP_6SERIES_1_WIFI,
 	PCI_DID_GrP_6SERIES_2_WIFI,
 	PCI_DID_GrP_6SERIES_3_WIFI,
+	/* Typhoon Peak 2 */
+	PCI_DID_TyP2_6SERIES_1_WIFI,
+	PCI_DID_TyP2_6SERIES_2_WIFI,
+	PCI_DID_TyP2_6SERIES_3_WIFI,
+	PCI_DID_TyP2_6SERIES_4_WIFI,
 	0
 };
 

diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
@@ -1,88 +1,92 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <device/device.h>
 #include <arch/io.h>
 #include <delay.h>
-#include <stdint.h>
+#include <types.h>
 #include "ec.h"
 
+#define EC_POLL_DELAY_US	10
+#define EC_SEND_TIMEOUT_US	20000	// 20ms
+#define EC_RECV_TIMEOUT_US	320000	// 320ms
+
 static u16 ec_cmd_reg = EC_SC;
 static u16 ec_data_reg = EC_DATA;
 
+/*
+ * Poll the EC status/command register for a specified
+ * state until the given timeout elapses.
+ */
+static int wait_ec_sc(int timeout_us, u8 mask, u8 state)
+{
+	while (timeout_us > 0 && (inb(ec_cmd_reg) & mask) != state) {
+		udelay(EC_POLL_DELAY_US);
+		timeout_us -= EC_POLL_DELAY_US;
+	}
+
+	return timeout_us > 0 ? 0 : -1;
+}
+
+bool ec_ready_send(int timeout_us)
+{
+	return wait_ec_sc(timeout_us, EC_IBF, 0) == 0;
+}
+
+bool ec_ready_recv(int timeout_us)
+{
+	return wait_ec_sc(timeout_us, EC_OBF, EC_OBF) == 0;
+}
+
 int send_ec_command(u8 command)
 {
-	int timeout;
+	return send_ec_command_timeout(command, EC_SEND_TIMEOUT_US);
+}
 
-	timeout = 0x7ff;
-	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) {
-		udelay(10);
-		if ((timeout & 0xff) == 0)
-			printk(BIOS_SPEW, ".");
-	}
-	if (!timeout) {
+int send_ec_command_timeout(u8 command, int timeout_us)
+{
+	if (!ec_ready_send(timeout_us)) {
 		printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n",
 				command);
 		// return -1;
 	}
 
-	udelay(10);
-
 	outb(command, ec_cmd_reg);
+
 	return 0;
 }
 
 int send_ec_data(u8 data)
 {
-	int timeout;
+	return send_ec_data_timeout(data, EC_SEND_TIMEOUT_US);
+}
 
-	timeout = 0x7ff;
-	while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) { // wait for IBF = 0
-		udelay(10);
-		if ((timeout & 0xff) == 0)
-			printk(BIOS_SPEW, ".");
-	}
-	if (!timeout) {
+int send_ec_data_timeout(u8 data, int timeout_us)
+{
+	if (!ec_ready_send(timeout_us)) {
 		printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n",
 				data);
 		// return -1;
 	}
 
-	udelay(10);
-
 	outb(data, ec_data_reg);
 
 	return 0;
 }
 
-int send_ec_data_nowait(u8 data)
+u8 recv_ec_data(void)
 {
-	outb(data, ec_data_reg);
-
-	return 0;
+	return recv_ec_data_timeout(EC_RECV_TIMEOUT_US);
 }
 
-u8 recv_ec_data(void)
+u8 recv_ec_data_timeout(int timeout_us)
 {
-	int timeout;
 	u8 data;
 
-	timeout = 0x7fff;
-	while (--timeout) { // Wait for OBF = 1
-		if (inb(ec_cmd_reg) & EC_OBF) {
-			break;
-		}
-		udelay(10);
-		if ((timeout & 0xff) == 0)
-			printk(BIOS_SPEW, ".");
-	}
-	if (!timeout) {
-		printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n");
+	if (!ec_ready_recv(timeout_us)) {
+		printk(BIOS_DEBUG, "Timeout while receiving data from EC!\n");
 		// return -1;
 	}
 
-	udelay(10);
-
 	data = inb(ec_data_reg);
 	printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, data);
 
@@ -91,30 +95,31 @@ u8 recv_ec_data(void)
 
 void ec_clear_out_queue(void)
 {
-	int timeout = 0x7fff;
+	int timeout = EC_RECV_TIMEOUT_US;
 	printk(BIOS_SPEW, "Clearing EC output queue...\n");
-	while (--timeout && (inb(ec_cmd_reg) & EC_OBF)) {
+	while (timeout > 0 && inb(ec_cmd_reg) & EC_OBF) {
 		u8 data = inb(ec_data_reg);
 		printk(BIOS_SPEW, "Discarding a garbage byte: 0x%02x\n", data);
-		udelay(10);
+		udelay(EC_POLL_DELAY_US);
+		timeout -= EC_POLL_DELAY_US;
 	}
-	if (!timeout)
+	if (timeout <= 0)
 		printk(BIOS_ERR, "Timeout while clearing EC output queue!\n");
 	else
 		printk(BIOS_SPEW, "EC output queue has been cleared.\n");
 }
 
 u8 ec_read(u8 addr)
 {
-	send_ec_command(0x80);
+	send_ec_command(RD_EC);
 	send_ec_data(addr);
 
 	return recv_ec_data();
 }
 
 int ec_write(u8 addr, u8 data)
 {
-	send_ec_command(0x81);
+	send_ec_command(WR_EC);
 	send_ec_data(addr);
 	return send_ec_data(data);
 }
@@ -126,7 +131,7 @@ u8 ec_status(void)
 
 u8 ec_query(void)
 {
-	send_ec_command(0x84);
+	send_ec_command(QR_EC);
 	return recv_ec_data();
 }
 

diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h
@@ -3,15 +3,15 @@
 #ifndef _EC_ACPI_H
 #define _EC_ACPI_H
 
-#include <stdint.h>
+#include <types.h>
 
 #define EC_DATA	0x62
 #define EC_SC	0x66
 
 /* EC_SC input */
 #define   EC_SMI_EVT	(1 << 6) // 1: SMI event pending
 #define   EC_SCI_EVT	(1 << 5) // 1: SCI event pending
-#define   EC_BURST	(1 << 4) // controller is in burst mode
+#define   EC_BURST	(1 << 4) // 1: controller is in burst mode
 #define   EC_CMD	(1 << 3) // 1: byte in data register is command
 				 // 0: byte in data register is data
 #define   EC_IBF	(1 << 1) // 1: input buffer full (data ready for ec)
@@ -23,10 +23,14 @@
 #define   BD_EC		0x83 // Burst Disable Embedded Controller
 #define   QR_EC		0x84 // Query Embedded Controller
 
+bool ec_ready_send(int timeout_us);
+bool ec_ready_recv(int timeout_us);
 int send_ec_command(u8 command);
+int send_ec_command_timeout(u8 command, int timeout);
 int send_ec_data(u8 data);
-int send_ec_data_nowait(u8 data);
+int send_ec_data_timeout(u8 data, int timeout);
 u8 recv_ec_data(void);
+u8 recv_ec_data_timeout(int timeout);
 void ec_clear_out_queue(void);
 u8 ec_status(void);
 u8 ec_query(void);

diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
@@ -11,25 +11,25 @@ Mutex (BATM, 0)
 Method (BTSW, 1)
 {
 #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
-	If (LEqual (BTIX, Arg0)) {
+	If (BTIX == Arg0) {
 		Return (Zero)
 	}
-	If (LGreaterEqual (Arg0, BTCN)) {
+	If (Arg0 >= BTCN) {
 		Return (One)
 	}
 	Store (Arg0, \_SB.PCI0.LPCB.EC0.BTID)
 	Store (5, Local0)      // Timeout 5 msec
-	While (LNotEqual (BTIX, Arg0))
+	While (BTIX != Arg0)
 	{
 		Sleep (1)
 		Local0--
-		If (LEqual (Local0, Zero))
+		If (Local0 == 0)
 		{
 			Return (One)
 		}
 	}
 #else
-	If (LNotEqual (0, Arg0)) {
+	If (Arg0 != 0) {
 		Return (One)
 	}
 #endif
@@ -78,11 +78,11 @@ Method (BBIF, 2, Serialized)
 	Store (Local0, Arg1[1])
 
 	// Design Capacity of Warning
-	Divide (Local0 * DWRN, 100, , Local2)
+	Local2 = Local0 * DWRN / 100
 	Store (Local2, Arg1[5])
 
 	// Design Capacity of Low
-	Divide (Local0 * DLOW, 100, , Local2)
+	Local2 = Local0 * DLOW / 100
 	Store (Local2, Arg1[6])
 
 	// Get battery info from mainboard
@@ -118,11 +118,11 @@ Method (BBIX, 2, Serialized)
 	Store (Local0, Arg1[2])
 
 	// Design Capacity of Warning
-	Divide (Local0 * DWRN, 100, , Local2)
+	Local2 = Local0 * DWRN / 100
 	Store (Local2, Arg1[6])
 
 	// Design Capacity of Low
-	Divide (Local0 * DLOW, 100, , Local2)
+	Local2 = Local0 * DLOW / 100
 	Store (Local2, Arg1[7])
 
 	// Cycle Count
@@ -180,9 +180,9 @@ Method (BBST, 4, Serialized)
 	Store (Local1, Arg1[0])
 
 	// Notify if battery state has changed since last time
-	If (LNotEqual (Local1, DeRefOf (Arg2))) {
+	If (Local1 != DeRefOf (Arg2)) {
 		Store (Local1, Arg2)
-		If (LEqual(Arg0, 0)) {
+		If (Arg0 == 0) {
 			Notify (BAT0, 0x80)
 		}
 #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
@@ -210,7 +210,7 @@ Method (BBST, 4, Serialized)
 
 		// See if within ~6% of full
 		ShiftRight (Local2, 4, Local3)
-		If (LGreater (Local1, Local2 - Local3) && LLess (Local1, Local2 + Local3))
+		If (Local1 > Local2 - Local3 && Local1 < Local2 + Local3)
 		{
 			Store (Local2, Local1)
 		}

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
@@ -178,30 +178,30 @@ Device (EC0)
 		Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0)
 
 		/* Check for sensor not calibrated */
-		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
+		If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) {
 			Return (Zero)
 		}
 
 		/* Check for sensor not present */
-		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
+		If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) {
 			Return (Zero)
 		}
 
 		/* Check for sensor not powered */
-		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
+		If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) {
 			Return (Zero)
 		}
 
 		/* Check for sensor bad reading */
-		If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
+		If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) {
 			Return (Zero)
 		}
 
 		/* Adjust by offset to get Kelvin */
 		Local0 += \_SB.PCI0.LPCB.EC0.TOFS
 
 		/* Convert to 1/10 Kelvin */
-		Multiply (Local0, 10, Local0)
+		Local0 *= 10
 
 		Return (Local0)
 	}
@@ -423,7 +423,7 @@ Device (EC0)
 		Store (ToInteger (Arg0), ^PATI)
 
 		/* Temperature is passed in 1/10 Kelvin */
-		Divide (ToInteger (Arg1), 10, , Local1)
+		Local1 = ToInteger (Arg1) / 10
 
 		/* Adjust by EC temperature offset */
 		^PATT = Local1 - ^TOFS
@@ -450,7 +450,7 @@ Device (EC0)
 		Store (ToInteger (Arg0), ^PATI)
 
 		/* Temperature is passed in 1/10 Kelvin */
-		Divide (ToInteger (Arg1), 10, , Local1)
+		Local1 = ToInteger (Arg1) / 10
 
 		/* Adjust by EC temperature offset */
 		^PATT = Local1 - ^TOFS
@@ -494,7 +494,7 @@ Device (EC0)
 			Store (^PATI, Local0)
 
 			/* When sensor ID returns 0xFF then no more events */
-			While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT))
+			While (Local0 != EC_TEMP_SENSOR_NOT_PRESENT)
 			{
 #ifdef HAVE_THERM_EVENT_HANDLER
 				\_SB.DPTF.TEVT (Local0)
@@ -539,7 +539,7 @@ Device (EC0)
 		 * DDPN = 0 is reserved for backwards compatibility.
 		 * If DDPN == 0 use TBMD to load appropriate DPTF table.
 		 */
-		If (LEqual (^DDPN, 0)) {
+		If (^DDPN == 0) {
 			Return (^TBMD)
 		} Else {
 			Local0 = ^DDPN - 1

diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl
@@ -23,11 +23,11 @@ Scope (\_SB)
 			/* If query is unsupported, but this code is compiled
 			 * in, assume the backlight exists physically.
 			 */
-			If (LEqual (1, \_SB.PCI0.LPCB.EC0.DFUD)) {
+			If (\_SB.PCI0.LPCB.EC0.DFUD == 1) {
 				Return (0xf)
 			}
 			/* If EC reports that backlight exists, trust it */
-			If (LEqual (1, \_SB.PCI0.LPCB.EC0.KBLE)) {
+			If (\_SB.PCI0.LPCB.EC0.KBLE == 1) {
 				Return (0xf)
 			}
 			/* Otherwise: no device -> disable */

diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl
@@ -7,7 +7,7 @@ Device (TBMC)
 	Name (_DDN, "Tablet Motion Control")
 	Method (TBMC)
 	{
-		If (LEqual (^^RCTM, One)) {
+		If (^^RCTM == 1) {
 			Return (0x1)
 		} Else {
 			Return (0x0)

diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c
@@ -109,6 +109,12 @@ static void write_fan_fst(const struct device *ec)
 	acpigen_emit_namestring("TFST");
 	acpigen_write_integer(1);
 	acpigen_emit_byte(ZERO_OP); /* 3rd arg to Index */
+	acpigen_write_store();
+	acpigen_emit_namestring(acpi_device_path_join(ec, "FAN0"));
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring("TFST");
+	acpigen_write_integer(2);
+	acpigen_emit_byte(ZERO_OP);
 	acpigen_emit_byte(RETURN_OP);
 	acpigen_emit_namestring("TFST");
 	acpigen_pop_len(); /* Method _FST */

diff --git a/src/ec/google/chromeec/mux/conn/chip.h b/src/ec/google/chromeec/mux/conn/chip.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EC_GOOGLE_CHROMEEC_MUX_CONN_CHIP_H
+#define EC_GOOGLE_CHROMEEC_MUX_CONN_CHIP_H
+
+struct ec_google_chromeec_mux_conn_config {
+	/* When set to true, this signifies that the mux device
+	 * is used as a Type-C mode switch in addition to
+	 * a retimer switch. */
+	bool mode_switch;
+};
+
+#endif /* EC_GOOGLE_CHROMEEC_MUX_CONN_CHIP_H */
diff --git a/src/ec/google/chromeec/mux/conn/conn.c b/src/ec/google/chromeec/mux/conn/conn.c
@@ -2,6 +2,8 @@
 
 #include <acpi/acpigen.h>
 
+#include "chip.h"
+
 static const char *conn_acpi_name(const struct device *dev)
 {
 	static char name[5];
@@ -11,6 +13,7 @@ static const char *conn_acpi_name(const struct device *dev)
 
 static void conn_fill_ssdt(const struct device *dev)
 {
+	const struct ec_google_chromeec_mux_conn_config *config = dev->chip_info;
 	const char *name;
 	name = acpi_device_name(dev);
 	if (!name)
@@ -21,6 +24,12 @@ static void conn_fill_ssdt(const struct device *dev)
 
 	acpigen_write_name_integer("_ADR", dev->path.generic.id);
 
+	if (config && config->mode_switch) {
+		struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+		acpi_dp_add_integer(dsd, "mode-switch", 1);
+		acpi_dp_write(dsd);
+	}
+
 	acpigen_write_device_end();
 	acpigen_write_scope_end();
 }

diff --git a/src/ec/kontron/it8516e/acpi/pm_channels.asl b/src/ec/kontron/it8516e/acpi/pm_channels.asl
@@ -35,7 +35,7 @@ Device (PM1) {
 		If (And (Local0, EC_ERROR_MASK)) {
 			Return (0)
 		}
-		Multiply (Local0, 10, Local0)	/* Convert to 10th °C */
+		Local0 *= 10
 		Return (Local0 + 2732)	/* Return as 10th Kelvin */
 	}
 }

diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
@@ -64,9 +64,9 @@ Device(EC)
 	Method (_REG, 2, NotSerialized)
 	{
 		/* Wait for ERAM driver loaded */
-		if (LEqual(Arg1, One)) {
+		if (Arg1 == 1) {
 			/* Fill HKEY defaults on first boot */
-			if (LEqual(^HKEY.INIT, Zero)) {
+			if (^HKEY.INIT == 0) {
 				Store (BTEB, ^HKEY.WBDC)
 				Store (WWEB, ^HKEY.WWAN)
 				Store (One, ^HKEY.INIT)

diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl
@@ -5,7 +5,7 @@ Scope (\_SI)
 {
 	Method(_SST, 1, NotSerialized)
 	{
-		If (LEqual (Arg0, 0)) {
+		If (Arg0 == 0) {
 			/* Indicator off */
 
 			/* power TLED off */
@@ -14,7 +14,7 @@ Scope (\_SI)
 			\_SB.PCI0.LPCB.EC.TLED(0x07)
 		}
 
-		If (LEqual (Arg0, 1)) {
+		If (Arg0 == 1) {
 			/* working state */
 
 			/* power TLED on */
@@ -23,7 +23,7 @@ Scope (\_SI)
 			\_SB.PCI0.LPCB.EC.TLED(0x07)
 		}
 
-		If (LEqual (Arg0, 2)) {
+		If (Arg0 == 2) {
 			/* waking state */
 
 			/* power LED on */
@@ -32,7 +32,7 @@ Scope (\_SI)
 			\_SB.PCI0.LPCB.EC.TLED(0xc7)
 		}
 
-		If (LEqual (Arg0, 3)) {
+		If (Arg0 == 3) {
 			/* sleep state */
 
 			/* power TLED pulsing */

diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl
@@ -11,13 +11,13 @@ Scope(\_TZ)
 
 	Method(C2K, 1, NotSerialized)
 	{
-		Multiply(Arg0, 10, Local0)
+		Local0 = Arg0 * 10
 		Local0 += 2732
 		if (LLessEqual(Local0, 2732)) {
 			Return (3000)
 		}
 
-		if (LGreater(Local0, 4012)) {
+		if (Local0 > 4012) {
 			Return (3000)
 		}
 		Return (Local0)
@@ -47,7 +47,7 @@ External (\PPKG, MethodObj)
 		/* Get critical temperature in degree celsius */
 		Method (GCRT, 0, NotSerialized) {
 			Store (\TCRT, Local0)
-			if (LGreater (Local0, 0)) {
+			if (Local0 > 0) {
 				Return (Local0)
 			}
 			Return (127)
@@ -56,7 +56,7 @@ External (\PPKG, MethodObj)
 		/* Get passive temperature in degree celsius */
 		Method (GPSV, 0, NotSerialized) {
 			Store (\TPSV, Local0)
-			if (LGreater (Local0, 0)) {
+			if (Local0 > 0) {
 				Return (Local0)
 			}
 			Return (95)
@@ -73,7 +73,7 @@ External (\PPKG, MethodObj)
 		Method(_TMP) {
 #if defined(EC_LENOVO_H8_ME_WORKAROUND)
 			/* Avoid tripping alarm if ME isn't booted at all yet */
-			If (!MEB1 && LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128)) {
+			If (!MEB1 && \_SB.PCI0.LPCB.EC.TMP0 == 128) {
 				Return (C2K(40))
 			}
 			Store (1, MEB1)
@@ -160,7 +160,7 @@ External (\PPKG, MethodObj)
 		Method(_TMP) {
 #if defined(EC_LENOVO_H8_ME_WORKAROUND)
 			/* Avoid tripping alarm if ME isn't booted at all yet */
-			If (!MEB2 && LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128)) {
+			If (!MEB2 && \_SB.PCI0.LPCB.EC.TMP1 == 128) {
 				Return (C2K(40))
 			}
 			Store (1, MEB2)