diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h
diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c
diff --git a/src/cpu/allwinner/a10/dramc.h b/src/cpu/allwinner/a10/dramc.h
diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c
diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h
diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h
diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c
diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c
diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h
diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c
diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h
diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c
diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h
diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
@@ -30,6 +30,7 @@ config CPU_AMD_AGESA
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select POSTCAR_STAGE
+	select SMM_ASEG
 
 if CPU_AMD_AGESA
 

diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -19,7 +19,7 @@ ramstage-y += fixme.c
 ramstage-y += chip_name.c
 ramstage-y += model_15_init.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+smm-y += udelay.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../smm

diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
@@ -7,7 +7,6 @@ config CPU_AMD_MODEL_10XXX
 	select SSE2
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC
-	select HAVE_MONOTONIC_TIMER
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_MICROCODE_MULTIPLE_FILES
 	select ACPI_HUGE_LOWMEM_BACKUP

diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -91,6 +91,7 @@ b.-  prep_fid_change(...)
 
 #include <console/console.h>
 #include <cpu/amd/msr.h>
+#include <device/pci_ops.h>
 #include <inttypes.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
 

diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc
@@ -19,7 +19,7 @@ ramstage-y += fixme.c
 ramstage-y += chip_name.c
 ramstage-y += model_15_init.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+smm-y += udelay.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../smm

diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
@@ -29,6 +29,7 @@ config CPU_AMD_PI
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER
+	select SMM_ASEG
 
 if CPU_AMD_PI
 

diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c
@@ -40,8 +40,7 @@ void *asmlinkage romstage_main(unsigned long bist)
 
 	romstage_handoff_init(s3resume);
 
-	uintptr_t stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
-		ROMSTAGE_STACK_CBMEM);
+	char *stack_top = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
 	stack_top += HIGH_ROMSTAGE_STACK_SIZE;
 
 	printk(BIOS_DEBUG, "Move CAR stack.\n");

diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c
@@ -70,11 +70,6 @@ void smm_init(void)
 	/* CPU MSR are set in CPU init */
 }
 
-void smm_lock(void)
-{
-	/* We lock SMM in CPU init */
-}
-
 void smm_init_completion(void)
 {
 }
diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
@@ -2,4 +2,4 @@ ramstage-y += common_init.c
 romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
 postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c
+smm-y += fsb.c
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select LAPIC_MONOTONIC_TIMER
 	select CPU_INTEL_COMMON
+	select NO_SMM
 
 	# Microcode header files are delivered in FSP package
 	select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN

diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
@@ -10,13 +10,12 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
-	select HAVE_MONOTONIC_TIMER
 	select SMP
 	select MMX
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
-	select SMM_TSEG
+	select TSC_MONOTONIC_TIMER
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
@@ -7,22 +7,10 @@ romstage-y += ../car/romstage.c
 postcar-y += tsc_freq.c
 
 ramstage-y += acpi.c
-ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
-
-ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y)
-bootblock-y += monotonic_timer.c
-romstage-y += monotonic_timer.c
-postcar-y += monotonic_timer.c
-ramstage-y += monotonic_timer.c
-smm-y += monotonic_timer.c
-endif
+smm-y += finalize.c
+smm-y += tsc_freq.c
 
 bootblock-y += ../car/non-evict/cache_as_ram.S
 bootblock-y += ../car/bootblock.c

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
@@ -118,15 +118,9 @@
 /* Data is passed through bits 31:0 of the data register. */
 #define BIOS_MAILBOX_DATA			0x5da0
 
-/* Region of SMM space is reserved for multipurpose use. It falls below
- * the IED region and above the SMM handler. */
-#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
-#define RESERVED_SMM_OFFSET \
-	(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
-
 /* Sanity check config options. */
-#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
-# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
 #endif
 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
@@ -166,6 +160,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 		size_t *smm_save_state_size);
 void smm_initialize(void);
 void smm_relocate(void);
+void smm_lock(void);
 struct bus;
 void bsp_init_and_start_aps(struct bus *cpu_bus);
 /* Determine if HyperThreading is disabled. The variable is not valid until

diff --git a/src/cpu/intel/haswell/monotonic_timer.c b/src/cpu/intel/haswell/monotonic_timer.c
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
@@ -250,7 +250,7 @@ static void fill_in_relocation_params(struct device *dev,
 	params->ied_size = tseg_size - params->smram_size;
 
 	/* Adjust available SMM handler memory size. */
-	params->smram_size -= RESERVED_SMM_SIZE;
+	params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */
 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;

diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc
@@ -2,6 +2,6 @@ ramstage-y += model_1067x_init.c
 ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
-subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+subdirs-y += ../smm/gen1
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*)
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
@@ -1,7 +1,7 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
-subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+subdirs-y += ../smm/gen1
 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*)
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
@@ -13,15 +13,14 @@ config CPU_SPECIFIC_OPTIONS
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
-	select SMM_TSEG
+	select TSC_MONOTONIC_TIMER
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select PARALLEL_CPU_INIT
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
 	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 
 config BOOTBLOCK_CPU_INIT
 	string

diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
@@ -13,15 +13,11 @@ subdirs-y += ../common
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 postcar-y += tsc_freq.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
+smm-y += tsc_freq.c
 
 ramstage-y += acpi.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-
-romstage-y += stage_cache.c
-ramstage-y += stage_cache.c
-postcar-y += stage_cache.c
+smm-y += finalize.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
 

diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
@@ -80,16 +80,9 @@ void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 #endif
 
-/*
- * Region of SMM space is reserved for multipurpose use. It falls below
- * the IED region and above the SMM handler.
- */
-#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
-#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE)
-
 /* Sanity check config options. */
-#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE)
-# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE"
+#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)
+# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE"
 #endif
 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"

diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
@@ -15,12 +15,10 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
 	select TSC_MONOTONIC_TIMER
-	select SMM_TSEG
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select PARALLEL_MP
 	select NO_FIXED_XIP_ROM_SIZE
 

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
@@ -15,18 +15,14 @@ ramstage-y += acpi.c
 
 ramstage-y += common.c
 romstage-y += common.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
+smm-y += common.c
 
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 postcar-y += tsc_freq.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
+smm-y += tsc_freq.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+smm-y += finalize.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)

diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
@@ -81,17 +81,9 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
-/*
- * Region of SMM space is reserved for multipurpose use. It falls below
- * the IED region and above the SMM handler.
- */
-#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
-#define RESERVED_SMM_OFFSET \
-	(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
-
 /* Sanity check config options. */
-#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
-# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
 #endif
 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"

diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc
@@ -1,7 +1,7 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
-subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+subdirs-y += ../smm/gen1
 ramstage-y += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*)
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc
@@ -2,6 +2,6 @@ ramstage-y += model_6fx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
-subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+subdirs-y += ../smm/gen1
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*)
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
@@ -6,3 +6,4 @@ config CPU_INTEL_MODEL_F2X
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select SMM_ASEG
diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc
@@ -1,5 +1,5 @@
 ramstage-y += model_f3x_init.c
-subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+subdirs-y += ../smm/gen1
 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*)
diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc
@@ -1,5 +1,5 @@
 ramstage-y += model_f4x_init.c
-subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+subdirs-y += ../smm/gen1
 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*)
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
@@ -25,6 +25,8 @@ config SLOT_SPECIFIC_OPTIONS # dummy
 	select CPU_INTEL_MODEL_68X
 	select CPU_INTEL_MODEL_6BX
 	select CPU_INTEL_MODEL_6XX
+	select NO_SMM
+	select NO_MONOTONIC_TIMER
 
 config DCACHE_RAM_BASE
 	hex

diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
@@ -31,3 +31,4 @@ void southbridge_smm_clear_state(void);
 void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 			uintptr_t staggered_smbase);
 void smm_relocate(void);
+void smm_lock(void);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -57,7 +57,6 @@ struct smm_relocation_params {
 
 /* This gets filled in and used during relocation. */
 static struct smm_relocation_params smm_reloc_params;
-static void *default_smm_area = NULL;
 
 /* On model_6fx, model_1067x and model_106cx SMRR functions slightly
    differently. The MSR are at different location from the rest
@@ -122,7 +121,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	}
 
 	/* Adjust available SMM handler memory size. */
-	if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
+	if (CONFIG(TSEG_STAGE_CACHE)) {
 		ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
 		params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
 	}
@@ -168,11 +167,6 @@ static void setup_ied_area(struct smm_relocation_params *params)
 	memset(ied_base + (1 << 20), 0, (32 << 10));
 }
 
-void smm_init_completion(void)
-{
-	restore_default_smm_area(default_smm_area);
-}
-
 void smm_lock(void)
 {
 	/* LOCK the SMM memory window and enable normal SMM.

diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -9,6 +9,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select MMX
 	select SSE
 	select UDELAY_TSC
+	select TSC_MONOTONIC_TIMER
 	select SIPI_VECTOR_IN_ROM
 	select C_ENVIRONMENT_BOOTBLOCK
 

diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
@@ -50,21 +50,15 @@ static const char *const turbo_state_desc[] = {
 };
 
 /*
- * Determine the current state of Turbo and cache it for later.
- * Turbo is a package level config so it does not need to be
- * enabled on every core.
+ * Try to update the global Turbo state.
  */
-int get_turbo_state(void)
+static int update_turbo_state(void)
 {
 	struct cpuid_result cpuid_regs;
 	int turbo_en, turbo_cap;
 	msr_t msr;
 	int turbo_state = get_global_turbo_state();
 
-	/* Return cached state if available */
-	if (turbo_state != TURBO_UNKNOWN)
-		return turbo_state;
-
 	cpuid_regs = cpuid(CPUID_LEAF_PM);
 	turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
 
@@ -84,6 +78,22 @@ int get_turbo_state(void)
 
 	set_global_turbo_state(turbo_state);
 	printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]);
+
+	return turbo_state;
+}
+
+/*
+ * Determine the current state of Turbo and cache it for later. Turbo is package
+ * level config so it does not need to be enabled on every core.
+ */
+int get_turbo_state(void)
+{
+	int turbo_state = get_global_turbo_state();
+
+	/* Return cached state if available */
+	if (turbo_state == TURBO_UNKNOWN)
+		turbo_state = update_turbo_state();
+
 	return turbo_state;
 }
 
@@ -102,8 +112,7 @@ void enable_turbo(void)
 		wrmsr(IA32_MISC_ENABLE, msr);
 
 		/* Update cached turbo state */
-		set_global_turbo_state(TURBO_ENABLED);
-		printk(BIOS_INFO, "Turbo has been enabled\n");
+		update_turbo_state();
 	}
 }
 
@@ -114,12 +123,14 @@ void disable_turbo(void)
 {
 	msr_t msr;
 
-	/* Set Turbo Disable bit in Misc Enables */
-	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.hi |= H_MISC_DISABLE_TURBO;
-	wrmsr(IA32_MISC_ENABLE, msr);
+	/* Only possible if turbo is available and visible */
+	if (get_turbo_state() == TURBO_ENABLED) {
+		/* Set Turbo Disable bit in Misc Enables */
+		msr = rdmsr(IA32_MISC_ENABLE);
+		msr.hi |= H_MISC_DISABLE_TURBO;
+		wrmsr(IA32_MISC_ENABLE, msr);
 
-	/* Update cached turbo state */
-	set_global_turbo_state(TURBO_UNAVAILABLE);
-	printk(BIOS_INFO, "Turbo has been disabled\n");
+		/* Update cached turbo state */
+		update_turbo_state();
+	}
 }
diff --git a/src/cpu/qemu-power8/Kconfig b/src/cpu/qemu-power8/Kconfig
@@ -19,3 +19,4 @@ config CPU_QEMU_POWER8
 	select ARCH_VERSTAGE_PPC64
 	select ARCH_ROMSTAGE_PPC64
 	select ARCH_RAMSTAGE_PPC64
+	select NO_MONOTONIC_TIMER
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
@@ -21,4 +21,6 @@ config CPU_QEMU_X86
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select UDELAY_TSC
+	select NO_MONOTONIC_TIMER
 	select C_ENVIRONMENT_BOOTBLOCK
+	select SMM_ASEG
diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig
@@ -3,9 +3,7 @@ config CPU_TI_AM335X
 	select ARCH_VERSTAGE_ARMV7
 	select ARCH_ROMSTAGE_ARMV7
 	select ARCH_RAMSTAGE_ARMV7
-	select HAVE_MONOTONIC_TIMER
 	select HAVE_UART_SPECIAL
-	select GENERIC_UDELAY
 	select UART_OVERRIDE_REFCLK
 	select BOOT_DEVICE_NOT_SPI_FLASH
 	bool

diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig
@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select UDELAY_TSC
+	select NO_MONOTONIC_TIMER
 	select MMX
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -17,19 +17,13 @@ config PARALLEL_MP_AP_WORK
 	 Allow APs to do other work after initialization instead of going
 	 to sleep.
 
-config UDELAY_IO
-	bool
-	default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 && !GENERIC_UDELAY
-	default n
-
 config UDELAY_LAPIC
 	bool
 	default n
 
 config LAPIC_MONOTONIC_TIMER
 	def_bool n
 	depends on UDELAY_LAPIC
-	select HAVE_MONOTONIC_TIMER
 	help
 	  Expose monotonic time using the local APIC.
 
@@ -50,15 +44,9 @@ config TSC_CONSTANT_RATE
 config TSC_MONOTONIC_TIMER
 	def_bool n
 	depends on UDELAY_TSC
-	select HAVE_MONOTONIC_TIMER
 	help
 	  Expose monotonic time using the TSC.
 
-# This option is used in code but never selected.
-config UDELAY_TIMER2
-	bool
-	default n
-
 config TSC_SYNC_LFENCE
 	bool
 	default n
@@ -98,34 +86,50 @@ config LOGICAL_CPUS
 	bool
 	default y
 
-config SMM_TSEG
+config HAVE_SMI_HANDLER
+	bool
+	default n
+	depends on (SMM_ASEG || SMM_TSEG)
+
+config NO_SMM
 	bool
 	default n
 
+config SMM_ASEG
+	bool
+	default n
+	depends on !NO_SMM
+
+config SMM_TSEG
+	bool
+	default y
+	depends on !(NO_SMM || SMM_ASEG)
+
+if SMM_TSEG
+
 config SMM_MODULE_HEAP_SIZE
 	hex
 	default 0x4000
-	depends on SMM_TSEG
 	help
 	  This option determines the size of the heap within the SMM handler
 	  modules.
 
 config SMM_MODULE_STACK_SIZE
 	hex
 	default 0x400
-	depends on SMM_TSEG
 	help
 	  This option determines the size of the stack within the SMM handler
 	  modules.
 
 config SMM_STUB_STACK_SIZE
 	hex
 	default 0x400
-	depends on SMM_TSEG
 	help
 	  This option determines the size of the stack within the SMM handler
 	  modules.
 
+endif
+
 config SMM_LAPIC_REMAP_MITIGATION
 	bool
 	default y if NORTHBRIDGE_INTEL_I945

diff --git a/src/cpu/x86/Kconfig.debug b/src/cpu/x86/Kconfig.debug
@@ -14,4 +14,4 @@ config DISPLAY_MTRRS
 
 config DEBUG_SMM_RELOCATION
 	bool "Debug SMM relocation code"
-	depends on HAVE_SMI_HANDLER
+	depends on HAVE_SMI_HANDLER && SMM_ASEG
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
@@ -910,7 +910,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us)
 			return 0;
 	} while (expire_us <= 0 || !stopwatch_expired(&sw));
 
-	printk(BIOS_ERR, "AP call expired. %d/%d CPUs accepted.\n",
+	printk(BIOS_CRIT, "CIRTICAL ERROR: AP call expired. %d/%d CPUs accepted.\n",
 		cpus_accepted, global_num_aps);
 	return -1;
 }

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
@@ -51,6 +52,6 @@ void set_var_mtrr(
 	basem.hi = 0;
 	wrmsr(MTRR_PHYS_BASE(reg), basem);
 	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
 	wrmsr(MTRR_PHYS_MASK(reg), maskm);
 }
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
@@ -36,13 +36,20 @@ $(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
 	cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
 
+ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
+ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
+endif
+
 ifeq ($(CONFIG_SMM_TSEG),y)
 
+ramstage-y += stage_cache.c
+romstage-y += stage_cache.c
+postcar-y += stage_cache.c
+
 smmstub-y += smm_stub.S
 
 smm-y += smm_module_handler.c
 
-ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
 ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual
 
 # SMM Stub Module. The stub is used as a trampoline for relocation and normal
@@ -82,10 +89,6 @@ $(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld
 	$(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map
 	$(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@
 
-ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
-ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
-endif
-
 smm-y += smmhandler.S
 smm-y += smihandler.c
 

diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
@@ -47,7 +47,7 @@ static int smi_obtain_lock(void)
 	return (ret == SMI_UNLOCKED);
 }
 
-void smi_release_lock(void)
+static void smi_release_lock(void)
 {
 	asm volatile (
 		"movb %1, %%al\n"

diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
@@ -185,7 +185,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params,
 	void *stacks_top;
 	size_t size;
 	char *base;
-	int i;
+	size_t i;
 	struct smm_stub_params *stub_params;
 	struct rmodule smm_stub;
 

diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
@@ -32,10 +32,9 @@
 // ADDR32() macro
 #include <arch/registers.h>
 
-#if CONFIG(SMM_TSEG)
-#error "Don't use this file with TSEG."
-
-#endif /* CONFIG_SMM_TSEG */
+#if !CONFIG(SMM_ASEG)
+#error "Only use this file with ASEG."
+#endif /* CONFIG_SMM_ASEG */
 
 #define LAPIC_ID 0xfee00020
 

diff --git a/src/drivers/intel/fsp1_1/stage_cache.c → src/cpu/x86/smm/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c → src/cpu/x86/smm/stage_cache.c
@@ -1,8 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,12 +14,18 @@
  */
 
 #include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
 #include <stage_cache.h>
+#include <types.h>
 
-void stage_cache_external_region(void **base, size_t *size)
+int __weak smm_subregion(int sub, uintptr_t *base, size_t *size)
 {
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+	return -1;
+}
+
+void __weak stage_cache_external_region(void **base, size_t *size)
+{
+	if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
 		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
 		*base = NULL;
 		*size = 0;

diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
@@ -3,6 +3,4 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
 romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
 verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
 postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
-ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
 smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
-endif
diff --git a/src/device/Kconfig b/src/device/Kconfig
@@ -255,6 +255,7 @@ menu "Display"
 config FRAMEBUFFER_SET_VESA_MODE
 	prompt "Set framebuffer graphics resolution"
 	bool
+	default y if CHROMEOS
 	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
 	select HAVE_VBE_LINEAR_FRAMEBUFFER
 	help
@@ -407,6 +408,8 @@ endif # FRAMEBUFFER_SET_VESA_MODE
 
 choice
 	prompt "Framebuffer mode"
+	default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && CHROMEOS
+	default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && CHROMEOS
 	default VGA_TEXT_FRAMEBUFFER
 
 config VGA_TEXT_FRAMEBUFFER

diff --git a/src/device/device_const.c b/src/device/device_const.c
@@ -183,29 +183,79 @@ DEVTREE_CONST struct device *pcidev_path_behind(
 	return find_dev_path(parent, &path);
 }
 
-DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn)
+DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn)
+{
+	DEVTREE_CONST struct bus *parent = pci_root_bus();
+	DEVTREE_CONST struct device *dev = parent->children;
+
+	/* FIXME: Write the loop with topology links. */
+	while (dev) {
+		if (dev->path.type != DEVICE_PATH_PCI) {
+			dev = dev->next;
+			continue;
+		}
+		if (dev->bus->secondary == bus)
+			return pcidev_path_behind(dev->bus, devfn);
+		dev = dev->next;
+	}
+	return NULL;
+}
+
+DEVTREE_CONST struct bus *pci_root_bus(void)
 {
 	DEVTREE_CONST struct device *pci_domain;
+	MAYBE_STATIC DEVTREE_CONST struct bus *pci_root = NULL;
+
+	if (pci_root)
+		return pci_root;
 
+	pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
+	if (!pci_domain)
+		return NULL;
+
+	pci_root = pci_domain->link_list;
+	return pci_root;
+}
+
+DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn)
+{
 	/* Work around pcidev_path_behind() below failing
 	 * due tue complicated devicetree with topology
 	 * being manipulated on-the-fly.
 	 */
 	if (CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
 		return dev_find_slot(0, devfn);
 
-	pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
-	if (!pci_domain)
-		return NULL;
-
-	return pcidev_path_behind(pci_domain->link_list, devfn);
+	return pcidev_path_behind(pci_root_bus(), devfn);
 }
 
 DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn)
 {
 	return pcidev_path_on_root(PCI_DEVFN(dev, fn));
 }
 
+DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func)
+{
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(devfn);
+	if (dev)
+		return dev;
+
+	devtree_bug(func, devfn);
+
+	/* FIXME: This can return wrong device. */
+	return dev_find_slot(0, devfn);
+}
+
+void devtree_bug(const char *func, pci_devfn_t devfn)
+{
+	printk(BIOS_ERR, "BUG: %s requests hidden 00:%02x.%u\n", func, devfn >> 3, devfn & 7);
+}
+
+void __noreturn devtree_die(void)
+{
+	die("DEVTREE: dev or chip_info is NULL\n");
+}
+
 /**
  * Given an SMBus bus and a device number, find the device structure.
  *

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -145,7 +145,7 @@ u32 dev_path_encode(const struct device *dev)
 		ret |= dev->path.spi.cs;
 		break;
 	case DEVICE_PATH_USB:
-		ret |= dev->path.usb.port_type << 8 || dev->path.usb.port_id;
+		ret |= dev->path.usb.port_type << 8 | dev->path.usb.port_id;
 		break;
 	case DEVICE_PATH_NONE:
 	case DEVICE_PATH_MMIO:  /* don't care */
@@ -229,7 +229,7 @@ const char *dev_path(const struct device *dev)
 				 dev->path.usb.port_type, dev->path.usb.port_id);
 			break;
 		case DEVICE_PATH_MMIO:
-			snprintf(buffer, sizeof(buffer), "MMIO: %08x",
+			snprintf(buffer, sizeof(buffer), "MMIO: %08lx",
 				 dev->path.mmio.addr);
 			break;
 		default:
@@ -331,7 +331,7 @@ void compact_resources(struct device *dev)
  * @param index The index of the resource on the device.
  * @return The resource, if it already exists.
  */
-struct resource *probe_resource(struct device *dev, unsigned index)
+struct resource *probe_resource(const struct device *dev, unsigned index)
 {
 	struct resource *res;
 
@@ -401,7 +401,7 @@ struct resource *new_resource(struct device *dev, unsigned index)
  * @param index The index of the resource on the device.
  * return TODO.
  */
-struct resource *find_resource(struct device *dev, unsigned index)
+struct resource *find_resource(const struct device *dev, unsigned index)
 {
 	struct resource *resource;
 

diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
@@ -291,7 +291,6 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_d
 	prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
 
 	/* If present, assign unitid to a hypertransport chain. */
-	last_unitid = min_unitid -1;
 	max_unitid = next_unitid = min_unitid;
 	do {
 		u8 pos;