171 changes: 142 additions & 29 deletions src/include/spi-generic.h
View file
Expand Up @@ -2,9 +2,6 @@
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
Expand All @@ -14,50 +11,135 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/

#ifndef _SPI_GENERIC_H_
#define _SPI_GENERIC_H_

#include <stdint.h>
#include <stddef.h>

/* Controller-specific definitions: */

/* SPI opcodes */
#define SPI_OPCODE_WREN 0x06
#define SPI_OPCODE_FAST_READ 0x0b

#define SPI_READ_FLAG 0x01
#define SPI_WRITE_FLAG 0x02
struct spi_ctrlr;

/*-----------------------------------------------------------------------
* Representation of a SPI slave, i.e. what we're communicating with.
*
* Drivers are expected to extend this with controller-specific data.
*
* bus: ID of the bus that the slave is attached to.
* cs: ID of the chip select connected to the slave.
* rw: Read or Write flag
* ctrlr: Pointer to SPI controller structure.
*/
struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int rw;
int force_programmer_specific;
struct spi_flash * (*programmer_specific_probe) (struct spi_slave *spi);
const struct spi_ctrlr *ctrlr;
};

/* Representation of SPI operation status. */
enum spi_op_status {
SPI_OP_NOT_EXECUTED = 0,
SPI_OP_SUCCESS = 1,
SPI_OP_FAILURE = 2,
};

/*
* Representation of a SPI operation.
*
* dout: Pointer to data to send.
* bytesout: Count of data in bytes to send.
* din: Pointer to store received data.
* bytesin: Count of data in bytes to receive.
*/
struct spi_op {
const void *dout;
size_t bytesout;
void *din;
size_t bytesin;
enum spi_op_status status;
};

enum spi_clock_phase {
SPI_CLOCK_PHASE_FIRST,
SPI_CLOCK_PHASE_SECOND
};

enum spi_wire_mode {
SPI_4_WIRE_MODE,
SPI_3_WIRE_MODE
};

enum spi_polarity {
SPI_POLARITY_LOW,
SPI_POLARITY_HIGH
};

struct spi_cfg {
/* CLK phase - 0: Phase first, 1: Phase second */
enum spi_clock_phase clk_phase;
/* CLK polarity - 0: Low, 1: High */
enum spi_polarity clk_polarity;
/* CS polarity - 0: Low, 1: High */
enum spi_polarity cs_polarity;
/* Wire mode - 0: 4-wire, 1: 3-wire */
enum spi_wire_mode wire_mode;
/* Data bit length. */
unsigned int data_bit_length;
};

/*-----------------------------------------------------------------------
* Representation of a SPI contoller.
*
* claim_bus: Claim SPI bus and prepare for communication.
* release_bus: Release SPI bus.
* setup: Setup given SPI device bus.
* xfer: Perform one SPI transfer operation.
* xfer_vector: Vector of SPI transfer operations.
*/
struct spi_ctrlr {
int (*claim_bus)(const struct spi_slave *slave);
void (*release_bus)(const struct spi_slave *slave);
int (*setup)(const struct spi_slave *slave);
int (*xfer)(const struct spi_slave *slave, const void *dout,
size_t bytesout, void *din, size_t bytesin);
int (*xfer_vector)(const struct spi_slave *slave,
struct spi_op vectors[], size_t count);
};

/*-----------------------------------------------------------------------
* Structure defining mapping of SPI buses to controller.
*
* ctrlr: Pointer to controller structure managing the given SPI buses.
* bus_start: Start bus number managed by the controller.
* bus_end: End bus number manager by the controller.
*/
struct spi_ctrlr_buses {
const struct spi_ctrlr *ctrlr;
unsigned int bus_start;
unsigned int bus_end;
};

/* Mapping of SPI buses to controllers - should be defined by platform. */
extern const struct spi_ctrlr_buses spi_ctrlr_bus_map[];
extern const size_t spi_ctrlr_bus_map_count;

/*-----------------------------------------------------------------------
* Initialization, must be called once on start up.
*
*/
void spi_init(void);

/*
* Get configuration of SPI bus.
*
* slave: Pointer to slave structure.
* cfg: Pointer to SPI configuration that needs to be filled.
*
* Returns:
* 0 on success, -1 on error
*/
int spi_get_config(const struct spi_slave *slave, struct spi_cfg *cfg);

/*-----------------------------------------------------------------------
* Set up communications parameters for a SPI slave.
*
Expand All @@ -68,11 +150,12 @@ void spi_init(void);
*
* bus: Bus ID of the slave chip.
* cs: Chip select ID of the slave chip on the specified bus.
* slave: Pointer to slave structure that needs to be initialized.
*
* Returns: A spi_slave reference that can be used in subsequent SPI
* calls, or NULL if one or more of the parameters are not supported.
* Returns:
* 0 on success, -1 on error
*/
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs);
int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave);

/*-----------------------------------------------------------------------
* Claim the bus and prepare it for communication with a given slave.
Expand All @@ -88,7 +171,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs);
* Returns: 0 if the bus was claimed successfully, or a negative value
* if it wasn't.
*/
int spi_claim_bus(struct spi_slave *slave);
int spi_claim_bus(const struct spi_slave *slave);

/*-----------------------------------------------------------------------
* Release the SPI bus
Expand All @@ -99,7 +182,7 @@ int spi_claim_bus(struct spi_slave *slave);
*
* slave: The SPI slave
*/
void spi_release_bus(struct spi_slave *slave);
void spi_release_bus(const struct spi_slave *slave);

/*-----------------------------------------------------------------------
* SPI transfer
Expand All @@ -113,10 +196,21 @@ void spi_release_bus(struct spi_slave *slave);
*
* Returns: 0 on success, not 0 on failure
*/
int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout,
void *din, unsigned int bytesin);

int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout,
void *din, size_t bytesin);

/*-----------------------------------------------------------------------
* Vector of SPI transfer operations
*
* spi_xfer_vector() interface:
* slave: The SPI slave which will be sending/receiving the data.
* vectors: Array of SPI op structures.
* count: Number of SPI op vectors.
*
* Returns: 0 on success, not 0 on failure
*/
int spi_xfer_vector(const struct spi_slave *slave,
struct spi_op vectors[], size_t count);

unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len);

Expand All @@ -129,7 +223,7 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len);
*
* TODO: This function probably shouldn't be inlined.
*/
static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
static inline int spi_w8r8(const struct spi_slave *slave, unsigned char byte)
{
unsigned char dout[2];
unsigned char din[2];
Expand All @@ -142,4 +236,23 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
return ret < 0 ? ret : din[1];
}

/*
* Helper function to allow chipsets to combine two vectors if possible. It can
* only handle upto 2 vectors.
*
* This function is provided to support command-response kind of transactions
* expected by users like flash. Some special SPI flash controllers can handle
* such command-response operations in a single transaction. For these special
* controllers, separate command and response vectors can be combined into a
* single operation.
*
* Two vectors are combined if first vector has a non-NULL dout and NULL din and
* second vector has a non-NULL din and NULL dout. Otherwise, each vector is
* operated upon one at a time.
*
* Returns 0 on success and non-zero on failure.
*/
int spi_xfer_two_vectors(const struct spi_slave *slave,
struct spi_op vectors[], size_t count);

#endif /* _SPI_GENERIC_H_ */
87 changes: 67 additions & 20 deletions src/include/spi_flash.h
View file
Expand Up @@ -3,9 +3,6 @@
*
* Copyright (C) 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
Expand All @@ -14,37 +11,87 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPI_FLASH_H_
#define _SPI_FLASH_H_

#include <stdint.h>
#include <stddef.h>
#include <console/console.h>
#include <spi-generic.h>
#include <boot/coreboot_tables.h>

struct spi_flash {
struct spi_slave *spi;

const char *name;

u32 size;
/* SPI Flash opcodes */
#define SPI_OPCODE_WREN 0x06
#define SPI_OPCODE_FAST_READ 0x0b

u32 sector_size;

int (*read)(struct spi_flash *flash, u32 offset,
struct spi_flash {
struct spi_slave spi;
const char *name;
u32 size;
u32 sector_size;
u8 erase_cmd;
u8 status_cmd;
/*
* Internal functions are expected to be called ONLY by spi flash
* driver. External components should only use the public API calls
* spi_flash_{read,write,erase,status,volatile_group_begin,
* volatile_group_end}.
*/
int (*internal_read)(const struct spi_flash *flash, u32 offset,
size_t len, void *buf);
int (*write)(struct spi_flash *flash, u32 offset,
int (*internal_write)(const struct spi_flash *flash, u32 offset,
size_t len, const void *buf);
int (*erase)(struct spi_flash *flash, u32 offset,
int (*internal_erase)(const struct spi_flash *flash, u32 offset,
size_t len);
int (*internal_status)(const struct spi_flash *flash, u8 *reg);
int (*internal_read_sec)(const struct spi_flash *flash, u32 offset,
size_t len, void *buf);
};

/* SPI Flash Driver Public API */
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs);
/*
* Specialized probing performed by platform. This is a weak function which can
* be overriden by platform driver.
* spi = Pointer to spi_slave structure.
* force = Indicates if the platform driver can skip specialized probing.
*/
struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force);

/* All the following functions return 0 on success and non-zero on error. */
int spi_flash_read(const struct spi_flash *flash, u32 offset, size_t len,
void *buf);
int spi_flash_write(const struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
int spi_flash_erase(const struct spi_flash *flash, u32 offset, size_t len);
int spi_flash_status(const struct spi_flash *flash, u8 *reg);
int spi_flash_read_sec(const struct spi_flash * flash, u32 offset, size_t len,
void *buf);
/*
* Some SPI controllers require exclusive access to SPI flash when volatile
* operations like erase or write are being performed. In such cases,
* volatile_group_begin will gain exclusive access to SPI flash if not already
* acquired and volatile_group_end will end exclusive access if this was the
* last request in the group. spi_flash_{write,erase} operations call
* volatile_group_begin at the start of function and volatile_group_end after
* erase/write operation is performed. These functions can also be used by any
* components that wish to club multiple volatile operations into a single
* group.
*/
int spi_flash_volatile_group_begin(const struct spi_flash *flash);
int spi_flash_volatile_group_end(const struct spi_flash *flash);

/*
* These are callbacks for marking the start and end of volatile group as
* handled by the chipset. Not every chipset requires this special handling. So,
* these functions are expected to be implemented in Kconfig option for volatile
* group is enabled (SPI_FLASH_HAS_VOLATILE_GROUP).
*/
int chipset_volatile_group_begin(const struct spi_flash *flash);
int chipset_volatile_group_end(const struct spi_flash *flash);

/* Return spi_flash object reference for the boot device. This is only valid
* if CONFIG_BOOT_DEVICE_SPI_FLASH is enabled. */
const struct spi_flash *boot_device_spi_flash(void);

#endif /* _SPI_FLASH_H_ */
5 changes: 5 additions & 0 deletions src/mainboard/pcengines/Kconfig
View file
Expand Up @@ -10,6 +10,9 @@ config BOARD_PCENGINES_APU2
config BOARD_PCENGINES_APU3
bool "APU3"

config BOARD_PCENGINES_APU4
bool "APU4"

config BOARD_PCENGINES_APU5
bool "APU5"

Expand All @@ -19,6 +22,8 @@ source "src/mainboard/pcengines/apu2/Kconfig"

source "src/mainboard/pcengines/apu3/Kconfig"

source "src/mainboard/pcengines/apu4/Kconfig"

source "src/mainboard/pcengines/apu5/Kconfig"

config MAINBOARD_VENDOR
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/pcengines/apu2/Kconfig
View file
Expand Up @@ -38,6 +38,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select USE_OPTION_TABLE # order can be fixed now.
# select HAVE_CMOS_DEFAULT
select USE_CBMEM_FILE_OVERRIDE
select SPI_FLASH
select SPI_FLASH_WINBOND

config MAINBOARD_DIR
string
Expand Down
12 changes: 6 additions & 6 deletions src/mainboard/pcengines/apu2/devicetree.cb
View file
Expand Up @@ -37,19 +37,19 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 2.2 on end # LAN3
device pci 2.3 on end # LAN2
device pci 2.4 on end # LAN1
device pci 2.5 on end # mPCIe slot 1
device pci 2.5 on end # mPCIe slot 1
device pci 8.0 on end # Platform Security Processor
end #chip northbridge/amd/pi/00730F01

chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
device pci 10.0 on end # XHCI HC0 muxed with EHCI 2
device pci 11.0 on end # SATA
device pci 12.0 off end # USB EHCI0 usb[0:3] not connected
device pci 13.0 on end # USB EHCI1 usb[4:7]
device pci 14.0 on end # SM
# disabled device pci 14.2 on end # HDA 0x4383
# disabled device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d # SIO NCT5104D
chip superio/nuvoton/nct5104d # SIO NCT5104D
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
Expand Down Expand Up @@ -77,8 +77,8 @@ chip northbridge/amd/pi/00730F01/root_complex
device pnp 2e.107 on end
device pnp 2e.607 off end
device pnp 2e.e off end
end # SIO NCT5104D
end # LPC 0x439d
end # SIO NCT5104D
end # LPC 0x439d

device pci 14.7 on end # SD
device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI
Expand Down
133 changes: 106 additions & 27 deletions src/mainboard/pcengines/apu2/mainboard.c
View file
Expand Up @@ -50,6 +50,37 @@
#include <cpuRegisters.h>
#include <build.h>
#include "bios_knobs.h"
#include <spi-generic.h>
#include <spi_flash.h>
#include <cbfs_core.h>

static int find_knob_index(const char *s, const char *pattern)
{

int pattern_index = 0;
char *result = (char *) s;
char *lpattern = (char *) pattern;

while (*result && *pattern ) {
if ( *lpattern == 0) // the pattern matches return the pointer
return pattern_index;
if ( *result == 0) // We're at the end of the file content but don't have a patter match yet
return -1;
if (*result == *lpattern ) {
// The string matches, simply advance
result++;
pattern_index++;
lpattern++;
} else {
// The string doesn't match restart the pattern
result++;
pattern_index++;
lpattern = (char *) pattern;
}
}

return -1;
}

/**********************************************
* enable the dedicated function in mainboard.
Expand Down Expand Up @@ -170,13 +201,10 @@ static void mainboard_final(void *chip_info) {

printk(BIOS_INFO, "USB PORT ROUTING = EHCI PORTS ENABLED\n");
}
#if CONFIG_USE_CBMEM_FILE_OVERRIDE

#if CONFIG_FORCE_CONSOLE
bool console_enabled = TRUE;
#else //CONFIG_FORCE_CONSOLE


bool console_enabled = check_console( ); // Get console setting from bootorder file.
#endif //CONFIG_FORCE_CONSOLE

if ( !console_enabled ) {

Expand All @@ -186,35 +214,86 @@ static void mainboard_final(void *chip_info) {
if ( !ReadFchGpio(APU2_BIOS_CONSOLE_GPIO) ) {

printk(BIOS_INFO, "S1 PRESSED\n");
console_enabled = TRUE;
}
}

if ( !console_enabled ) {
const struct spi_flash *flash;
const char *file_name = "bootorder";
size_t boot_file_len = 0;
size_t offset;
struct cbfs_file *bootorder_cbfs_file = NULL;
char* bootorder_copy;
int knob_index;

//
// The console should be disabled
//
unsigned char data = 0;
char *boot_file = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, file_name, CBFS_TYPE_RAW, &boot_file_len);

//
// Indicated to SeaBIOS it should display console output itself
//
add_cbmem_file(
"etc/screen-and-debug",
1,
&data );
if (boot_file == NULL) {
printk(BIOS_EMERG, "file [%s] not found in CBFS\n", file_name);
return;
}

//
// Hide the sgabios to disable SeaBIOS console
//
hide_cbmem_file(
"vgaroms/sgabios.bin" );
if (boot_file_len < 4096) {
printk(BIOS_EMERG, "Missing bootorder data.\n");
return;
}

}
boot_file_len--; // cbfs_get_file_content returns size+1

#endif //CONFIG_USE_CBMEM_FILE_OVERRIDE
offset = cbfs_locate_file(CBFS_DEFAULT_MEDIA, bootorder_cbfs_file, file_name);

if(offset ==-1) {
printk(BIOS_WARNING,"Failed to retrieve bootorder file offset\n");
return;
}

bootorder_copy = (char *) malloc(boot_file_len);

if(bootorder_copy == NULL) {
printk(BIOS_WARNING,"Failed to allocate memory for bootorder\n");
return;
}

if(memcpy(bootorder_copy, boot_file, boot_file_len) == NULL) {
printk(BIOS_WARNING,"Copying bootorder failed\n");
free(bootorder_copy);
return;
}

knob_index = find_knob_index(bootorder_copy, "scon");

if(knob_index == -1){
printk(BIOS_WARNING,"scon knob not found in bootorder\n");
free(bootorder_copy);
return;
}

*(bootorder_copy + knob_index) = '1';

spi_init();

flash = spi_flash_probe(0, 0);

if (flash == NULL) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
}

if (spi_flash_erase(flash, (u32) offset, boot_file_len)) {
printk(BIOS_WARNING, "SPI erase failed\n");
free(bootorder_copy);
return;
}

if (spi_flash_write(flash, (u32) offset, boot_file_len, bootorder_copy)) {
printk(BIOS_WARNING, "SPI write failed\n");
free(bootorder_copy);
return;
} else {
printk(BIOS_INFO, "Bootorder write successed\n");
}

free(bootorder_copy);
}
}
}

struct chip_operations mainboard_ops = {
Expand Down
4 changes: 3 additions & 1 deletion src/mainboard/pcengines/apu3/Kconfig
View file
Expand Up @@ -38,7 +38,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select USE_OPTION_TABLE # order can be fixed now.
# select HAVE_CMOS_DEFAULT
select USE_CBMEM_FILE_OVERRIDE

select SPI_FLASH
select SPI_FLASH_WINBOND

config MAINBOARD_DIR
string
default pcengines/apu3
Expand Down
132 changes: 105 additions & 27 deletions src/mainboard/pcengines/apu3/mainboard.c
View file
Expand Up @@ -50,6 +50,37 @@
#include <cpuRegisters.h>
#include <build.h>
#include "bios_knobs.h"
#include <spi-generic.h>
#include <spi_flash.h>
#include <cbfs_core.h>

static int find_knob_index(const char *s, const char *pattern)
{

int pattern_index = 0;
char *result = (char *) s;
char *lpattern = (char *) pattern;

while (*result && *pattern ) {
if ( *lpattern == 0) // the pattern matches return the pointer
return pattern_index;
if ( *result == 0) // We're at the end of the file content but don't have a patter match yet
return -1;
if (*result == *lpattern ) {
// The string matches, simply advance
result++;
pattern_index++;
lpattern++;
} else {
// The string doesn't match restart the pattern
result++;
pattern_index++;
lpattern = (char *) pattern;
}
}

return -1;
}

/**********************************************
* enable the dedicated function in mainboard.
Expand Down Expand Up @@ -170,13 +201,8 @@ static void mainboard_final(void *chip_info) {

printk(BIOS_INFO, "USB PORT ROUTING = EHCI PORTS ENABLED\n");
}
#if CONFIG_USE_CBMEM_FILE_OVERRIDE

#if CONFIG_FORCE_CONSOLE
bool console_enabled = TRUE;
#else //CONFIG_FORCE_CONSOLE
bool console_enabled = check_console( ); // Get console setting from bootorder file.
#endif //CONFIG_FORCE_CONSOLE

if ( !console_enabled ) {

Expand All @@ -186,34 +212,86 @@ static void mainboard_final(void *chip_info) {
if ( !ReadFchGpio(APU2_BIOS_CONSOLE_GPIO) ) {

printk(BIOS_INFO, "S1 PRESSED\n");
console_enabled = TRUE;
}
}

if ( !console_enabled ) {
const struct spi_flash *flash;
const char *file_name = "bootorder";
size_t boot_file_len = 0;
size_t offset;
struct cbfs_file *bootorder_cbfs_file = NULL;
char* bootorder_copy;
int knob_index;

//
// The console should be disabled
//
unsigned char data = 0;
char *boot_file = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, file_name, CBFS_TYPE_RAW, &boot_file_len);

//
// Indicated to SeaBIOS it should display console output itself
//
add_cbmem_file(
"etc/screen-and-debug",
1,
&data );
if (boot_file == NULL) {
printk(BIOS_EMERG, "file [%s] not found in CBFS\n", file_name);
return;
}

//
// Hide the sgabios to disable SeaBIOS console
//
hide_cbmem_file(
"vgaroms/sgabios.bin" );
if (boot_file_len < 4096) {
printk(BIOS_EMERG, "Missing bootorder data.\n");
return;
}

}
boot_file_len--; // cbfs_get_file_content returns size+1

#endif //CONFIG_USE_CBMEM_FILE_OVERRIDE
offset = cbfs_locate_file(CBFS_DEFAULT_MEDIA, bootorder_cbfs_file, file_name);

if(offset ==-1) {
printk(BIOS_WARNING,"Failed to retrieve bootorder file offset\n");
return;
}

bootorder_copy = (char *) malloc(boot_file_len);

if(bootorder_copy == NULL) {
printk(BIOS_WARNING,"Failed to allocate memory for bootorder\n");
return;
}

if(memcpy(bootorder_copy, boot_file, boot_file_len) == NULL) {
printk(BIOS_WARNING,"Copying bootorder failed\n");
free(bootorder_copy);
return;
}

knob_index = find_knob_index(bootorder_copy, "scon");

if(knob_index == -1){
printk(BIOS_WARNING,"scon knob not found in bootorder\n");
free(bootorder_copy);
return;
}

*(bootorder_copy + knob_index) = '1';

spi_init();

flash = spi_flash_probe(0, 0);

if (flash == NULL) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
}

if (spi_flash_erase(flash, (u32) offset, boot_file_len)) {
printk(BIOS_WARNING, "SPI erase failed\n");
free(bootorder_copy);
return;
}

if (spi_flash_write(flash, (u32) offset, boot_file_len, bootorder_copy)) {
printk(BIOS_WARNING, "SPI write failed\n");
free(bootorder_copy);
return;
} else {
printk(BIOS_INFO, "Bootorder write successed\n");
}

free(bootorder_copy);
}
}

}

Expand Down
168 changes: 168 additions & 0 deletions src/mainboard/pcengines/apu4/BiosCallOuts.c
View file
@@ -0,0 +1,168 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/pi/BiosCallOuts.h>
#include "Ids.h"
//#include "OptionsIds.h"
#include "heapManager.h"
#include "FchPlatform.h"
#include "cbfs.h"
#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
#include "imc.h"
#endif
#include "hudson.h"
#include <stdlib.h>
#include <fchgpio.h>
#include "apu2.h"
#include <spd_cache.h> // for the apu2_ReadSpd_from_cbfs function
#include "bios_knobs.h"

static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);

const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
{AGESA_READ_SPD, apu2_ReadSpd_from_cbfs },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);

//{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_NoopUnsupported }


/*
* Hardware Monitor Fan Control
* Hardware limitation:
* HWM will fail to read the input temperature via I2C if other
* software switches the I2C address. AMD recommends using IMC
* to control fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = FALSE;
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */
}

/**
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
* such Azalia, SATA, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "\n%s in INIT RESET\n", __func__ );
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;


} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

/* Azalia Controller OEM Codec Table Pointer */
/* Azalia Controller Front Panel OEM Table Pointer */

// No audio support in this system
FchParams->Azalia.AzaliaEnable = AzDisable;

/* Fan Control */
oem_fan_control(FchParams);

/* XHCI configuration */
FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;

/* EHCI configuration */
FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams->Usb.Ehci1Enable = check_ehci0();
FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.

/* sata configuration */
FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
FchParams->Sata.SataDevSlpPort1 = 0;

FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
case SataRaid:
case SataAhci:
case SataAhci7804:
case SataLegacyIde:
FchParams->Sata.SataIdeMode = FALSE;
break;
case SataIde2Ahci:
case SataIde2Ahci7804:
default: /* SataNativeIde */
FchParams->Sata.SataIdeMode = TRUE;
break;
}
}
printk(BIOS_DEBUG, "Done\n");

return AGESA_SUCCESS;
}


AGESA_STATUS apu2_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
int index = 0;

if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
if (info->SocketId != 0)
return AGESA_UNSUPPORTED;
if (info->DimmId != 0)
return AGESA_UNSUPPORTED;

/* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/

if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0;
if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1;

printk(BIOS_INFO, "Reading SPD index %d\n", index);

if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0)
die("No SPD data\n");

Status = AGESA_SUCCESS;
#endif
return Status;
}
264 changes: 264 additions & 0 deletions src/mainboard/pcengines/apu4/HYNIX-2G-1333.spd.hex
View file
@@ -0,0 +1,264 @@
# PCEngines 2Gb 1333

# SPD contents for APU 2GB DDR3 NO ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 128
01

# 1 SPD Revision
# 0x13 = Revision 1.3
13

# 2 Key Byte / DRAM Device Type
# bits[7:0]: 0x0b = DDR3 SDRAM
0B

# 3 Key Byte / Module Type
# bits[3:0]: 3 = SO-DIMM
# bits[3:0]: 8 = 72b-SO-DIMM
# bits[7:4]: reserved
03

# 4 SDRAM CHIP Density and Banks
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
03

# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
# bits[5:3]: 4 = 16 Row Address Bits
# bits[5:3]: 3 = 15 Row Address Bits
# bits[5:3]: 2 = 14 Row Address Bits
# bits[7:6]: reserved
19

# 6 Module Nominal Voltage, VDD
# bit0 : 0 = 1.5 V operable
# bit1 : 0 = NOT 1.35 V operable
# bit2 : 0 = NOT 1.25 V operable
# bits[7:3]: reserved
00

# 7 Module Organization
# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
01

# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
# bits[4:3]: 0 = 0 bits (no bus width extension)
# bits[4:3]: 1 = 8 bits (for ECC)
# bits[7:5]: reserved
03

# 9 Fine Timebase (FTB) Dividend / Divisor
# bits[3:0]: 0x02 divisor
# bits[7:4]: 0x05 dividend
# 5 / 2 = 2.5ps
52

# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
# 1 / 8 = .125 ns
01 08

# 12 SDRAM Minimum Cycle Time (tCKmin)
# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
0C

# 13 Reserved
00

# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
# Cas Latencies of 11 - 5 are supported
7E 00

# 16 Minimum CAS Latency Time (tAAmin)
# 0x6C = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 17 Minimum Write Recovery Time (tWRmin)
# 0x78 = tWR of 15ns - All DDR3 speed grades
78

# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
# 0x6E = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
# 0x30 = 6.0ns
# 0x38 = 7.0ns
# 0x3C = 7.5ns
30

# 20 Minimum Row Precharge Delay Time (tRPmin)
# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69

# 21 Upper Nibbles for tRAS and tRC
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
11

# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
# 0x120 = 36ns - DDR3-1333 (see byte 21)
# 0x120 = 36ns - DDR3
20

# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
# 0x289 = 49.125ns - DDR3-1333
89

# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
# 0x820 = 260ns - for 4 Gigabit chips
00 05

# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
3C

# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
3C

# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
00 F0

# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
# bit7 : 1 = DLL Off mode supported
83

# 31 SDRAM Thermal and Refresh Options
# bit0 : 1 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
01

# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
00

# 33 SDRAM Device Type
# bits[1:0]: 0 = Signal Loading not specified
# bits[3:2]: reserved
# bits[6:4]: 0 = Die count not specified
# bit7 : 0 = Standard Monolithic DRAM Device
00

# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
00

# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
00

# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
00

# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
00

# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
00

# 39 40 (reserved)
00 00

# 41 tMAW, MAC
# 8K*tREFI / 200k
86

# 42 - 47 (reserved)
00 00 00 00 00 00

# 48 - 55 (reserved)
00 00 00 00 00 00 00 00

# 56 - 59 (reserved)
00 00 00 00

# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
00

# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
00

# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
# revision B4
61

# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
# bits[7:1]: reserved
00

# 64 - 71 (reserved)
00 00 00 00 00 00 00 00

# 72 - 79 (reserved)
00 00 00 00 00 00 00 00

# 80 - 87 (reserved)
00 00 00 00 00 00 00 00

# 88 - 95 (reserved)
00 00 00 00 00 00 00 00

# 96 - 103 (reserved)
00 00 00 00 00 00 00 00

# 104 - 111 (reserved)
00 00 00 00 00 00 00 00

# 112 - 116 (reserved)
00 00 00 00 00

# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
# 0x0001 = AMD
00 01

# 119 Module ID: Module Manufacturing Location - OEM specified
00

# 120 Module ID: Module Manufacture Year in BCD
# 0x15 = 2015
15

# 121 Module ID: Module Manufacture week
# 0x44 = 44th week
44

# 122 - 125: Module Serial Number
00 00 00 00

# 126 - 127: Cyclical Redundancy Code
b6 73

261 changes: 261 additions & 0 deletions src/mainboard/pcengines/apu4/HYNIX-4G-1333-ECC.spd.hex
View file
@@ -0,0 +1,261 @@
# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix

# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 128
01

# 1 SPD Revision -
# 0x13 = Revision 1.3
13
# 2 Key Byte / DRAM Device Type
# bits[7:0]: 0x0b = DDR3 SDRAM
0B

# 3 Key Byte / Module Type
# bits[3:0]: 3 = SO-DIMM
# bits[3:0]: 8 = 72b-SO-DIMM
# bits[7:4]: reserved
08

# 4 SDRAM CHIP Density and Banks
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
04

# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
# bits[5:3]: 4 = 16 Row Address Bits
# bits[5:3]: 3 = 15 Row Address Bits
# bits[5:3]: 2 = 14 Row Address Bits
# bits[7:6]: reserved
21

# 6 Module Nominal Voltage, VDD
# bit0 : 0 = 1.5 V operable
# bit1 : 0 = NOT 1.35 V operable
# bit2 : 0 = NOT 1.25 V operable
# bits[7:3]: reserved
00

# 7 Module Organization
# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
01

# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
# bits[4:3]: 0 = 0 bits (no bus width extension)
# bits[4:3]: 1 = 8 bits (for ECC)
# bits[7:5]: reserved
0B

# 9 Fine Timebase (FTB) Dividend / Divisor
# bits[3:0]: 0x02 divisor
# bits[7:4]: 0x05 dividend
# 5 / 2 = 2.5 ps
52

# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
# 1 / 8 = .125 ns
01 08

# 12 SDRAM Minimum Cycle Time (tCKmin)
# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
0C

# 13 Reserved
00

# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
# Cas Latencies of 11 - 5 are supported
7E 00

# 16 Minimum CAS Latency Time (tAAmin)
# 0x6C = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 17 Minimum Write Recovery Time (tWRmin)
# 0x78 = tWR of 15ns - All DDR3 speed grades
78

# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
# 0x6E = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
# 0x30 = 6ns
# 0x38 = 7.0ns
# 0x3C = 7.5ns
30

# 20 Minimum Row Precharge Delay Time (tRPmin)
# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69

# 21 Upper Nibbles for tRAS and tRC
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
11

# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
# 0x120 = 36ns - DDR3-1333 (see byte 21)
# 0x120 = 36ns - DDR3
20

# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
# 0x28C = 49.5ns - DDR3-1333
# 0x289 = 49.125ns - DDR3-1333
89

# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
# 0x820 = 260ns - for 4 Gigabit chips
20 08

# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
3C

# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
3C

# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
00 F0

# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
# bit7 : 1 = DLL Off mode supported
83

# 31 SDRAM Thermal and Refresh Options
# bit0 : 1 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
01

# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
00

# 33 SDRAM Device Type
# bits[1:0]: 0 = Signal Loading not specified
# bits[3:2]: reserved
# bits[6:4]: 0 = Die count not specified
# bit7 : 0 = Standard Monolithic DRAM Device
00

# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
00
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
00
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
00
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
00
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
00

# 39 40 (reserved)
00 00

# 41 tMAW, MAC
# 8K*tREFI / 200k
86

# 42 - 47 (reserved)
00 00 00 00 00 00

# 48 - 55 (reserved)
00 00 00 00 00 00 00 00

# 56 - 59 (reserved)
00 00 00 00

# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
00

# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
00

# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
# revision B4
61

# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
# bits[7:1]: reserved
00

# 64 - 71 (reserved)
00 00 00 00 00 00 00 00

# 72 - 79 (reserved)
00 00 00 00 00 00 00 00

# 80 - 87 (reserved)
00 00 00 00 00 00 00 00

# 88 - 95 (reserved)
00 00 00 00 00 00 00 00

# 96 - 103 (reserved)
00 00 00 00 00 00 00 00

# 104 - 111 (reserved)
00 00 00 00 00 00 00 00

# 112 - 116 (reserved)
00 00 00 00 00

# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
# 0x0001 = AMD
00 01

# 119 Module ID: Module Manufacturing Location - oem specified
00

# 120 Module ID: Module Manufacture Year in BCD
# 0x15 = 2015
# 121 Module ID: Module Manufacture week
# 0x44 = 44th week
15 44

# 122 - 125: Module Serial Number
00 00 00 00

# 126 - 127: Cyclical Redundancy Code
67 94




262 changes: 262 additions & 0 deletions src/mainboard/pcengines/apu4/HYNIX-4G-1333-NOECC.spd.hex
View file
@@ -0,0 +1,262 @@
# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix

# SPD contents for APU 4GB DDR3 NO ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 128
01

# 1 SPD Revision -
# 0x13 = Revision 1.3
13

# 2 Key Byte / DRAM Device Type
# bits[7:0]: 0x0b = DDR3 SDRAM
0B

# 3 Key Byte / Module Type
# bits[3:0]: 3 = SO-DIMM
# bits[3:0]: 8 = 72b-SO-DIMM
# bits[7:4]: reserved
03

# 4 SDRAM CHIP Density and Banks
# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
04

# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
# bits[5:3]: 4 = 16 Row Address Bits
# bits[5:3]: 3 = 15 Row Address Bits
# bits[5:3]: 2 = 14 Row Address Bits
# bits[7:6]: reserved
21

# 6 Module Nominal Voltage, VDD
# bit0 : 0 = 1.5 V operable
# bit1 : 0 = NOT 1.35 V operable
# bit2 : 0 = NOT 1.25 V operable
# bits[7:3]: reserved
00

# 7 Module Organization
# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
01

# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
# bits[4:3]: 0 = 0 bits (no bus width extension)
# bits[4:3]: 1 = 8 bits (for ECC)
# bits[7:5]: reserved
03

# 9 Fine Timebase (FTB) Dividend / Divisor
# bits[3:0]: 0x02 divisor
# bits[7:4]: 0x05 dividend
# 5 / 2 = 2.5 ps
52

# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
# 1 / 8 = .125 ns
01 08

# 12 SDRAM Minimum Cycle Time (tCKmin)
# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
# 0x0c = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
0C

# 13 Reserved
00

# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
# Cas Latencies of 11 - 5 are supported
7E 00

# 16 Minimum CAS Latency Time (tAAmin)
# 0x6C = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 17 Minimum Write Recovery Time (tWRmin)
# 0x78 = tWR of 15ns - All DDR3 speed grades
78

# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
# 0x6E = 13.5ns - DDR3-1333
# 0x69 = 13.125 ns - DDR3-1333
69

# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
# 0x30 = 6ns
# 0x38 = 7.0ns
# 0x3C = 7.5ns
30

# 20 Minimum Row Precharge Delay Time (tRPmin)
# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69

# 21 Upper Nibbles for tRAS and tRC
# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
11

# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
# 0x120 = 36ns - DDR3-1333 (see byte 21)
# 0x120 = 36ns - DDR3
20

# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
# 0x28C = 49.5ns - DDR3-1333
# 0x289 = 49.125ns - DDR3-1333
89

# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
# 0x820 = 260ns - for 4 Gigabit chips
20 08

# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
3C

# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
3C

# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
00 F0

# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
# bit7 : 1 = DLL Off mode supported
83

# 31 SDRAM Thermal and Refresh Options
# bit0 : 1 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
01

# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
00

# 33 SDRAM Device Type
# bits[1:0]: 0 = Signal Loading not specified
# bits[3:2]: reserved
# bits[6:4]: 0 = Die count not specified
# bit7 : 0 = Standard Monolithic DRAM Device
00

# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
00
# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
00
# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
00
# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
00
# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
00

# 39 40 (reserved)
00 00

# 41 tMAW, MAC
# 8K*tREFI / 200k
86

# 42 - 47 (reserved)
00 00 00 00 00 00

# 48 - 55 (reserved)
00 00 00 00 00 00 00 00

# 56 - 59 (reserved)
00 00 00 00

# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
00

# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
00

# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
# revision B4
61

# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
# bits[7:1]: reserved
00

# 64 - 71 (reserved)
00 00 00 00 00 00 00 00

# 72 - 79 (reserved)
00 00 00 00 00 00 00 00

# 80 - 87 (reserved)
00 00 00 00 00 00 00 00

# 88 - 95 (reserved)
00 00 00 00 00 00 00 00

# 96 - 103 (reserved)
00 00 00 00 00 00 00 00

# 104 - 111 (reserved)
00 00 00 00 00 00 00 00

# 112 - 116 (reserved)
00 00 00 00 00

# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
# 0x0001 = AMD
00 01

# 119 Module ID: Module Manufacturing Location - oem specified
00

# 120 Module ID: Module Manufacture Year in BCD
# 0x15 = 2015
# 121 Module ID: Module Manufacture week
# 0x44 = 44th week
15 44

# 122 - 125: Module Serial Number
00 00 00 00

# 126 - 127: Cyclical Redundancy Code
09 ff




139 changes: 139 additions & 0 deletions src/mainboard/pcengines/apu4/Kconfig
View file
@@ -0,0 +1,139 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2016 Eltan B.V.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#

if BOARD_PCENGINES_APU4

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_PI_00730F01
select NORTHBRIDGE_AMD_PI_00730F01
select SOUTHBRIDGE_AMD_PI_AVALON
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
# select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
# select GFXUMA # disable graphics
select SPD_CACHE
select HUDSON_DISABLE_IMC
# select HAVE_OPTION_TABLE # Removed the CMOS support as the boot
# select USE_OPTION_TABLE # order can be fixed now.
# select HAVE_CMOS_DEFAULT
select USE_CBMEM_FILE_OVERRIDE
select SPI_FLASH
select SPI_FLASH_WINBOND

config MAINBOARD_DIR
string
default pcengines/apu4

config MAINBOARD_PART_NUMBER
string
default "apu4"

config SVI2_SLOW_SPEED
bool "SVI2 slow speed"
default n
help
Used when there are problems switching the VRM speed. By default
speed is 20 Mhz

config SVI_WAIT_COMP_DIS
bool "Disable SVI2 controller waits for command completion"
default y
help
SVI2 controller will not wait for command completion from VRM

config HW_MEM_HOLE_SIZEK
hex
default 0x200000

config MAX_CPUS
int
default 4

config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

config IRQ_SLOT_COUNT
int
default 11

config RAMTOP
hex
default 0x1000000

config HEAP_SIZE
hex
default 0xc0000

config ACPI_SSDTX_NUM
int
default 0

config RAMBASE
hex
default 0x200000

#config ONBOARD_VGA_IS_PRIMARY
# bool
# default y

config HUDSON_LEGACY_FREE
bool
default y

config HUDSON_XHCI_ENABLE
bool
default y

config DRIVERS_PS2_KEYBOARD
bool
default n

config AGESA_HEAP_MEMTEST
bool
default y

config VGA_ROM_RUN
bool
default n

config DUMP_GPIO_CONFIGURATION
bool "Dump FCH GPIO configuration in board finalize"
default n

config DUMP_CLOCK_CONFIGURATION
bool "Dump FCH MISC configuration in board finalize"
default n

config DUMP_LINK_CONFIGURATION
bool "Dump PCIe LINK configuration in board finalize"
default n

config FORCE_CONSOLE
bool "always enable serial console"
default n
help
by default serial console is only enabled when pressing S1

endif # BOARD_PCENGINES_APU4
128 changes: 128 additions & 0 deletions src/mainboard/pcengines/apu4/Makefile.inc
View file
@@ -0,0 +1,128 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2016 Eltan B.V.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#

romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
romstage-y += bios_knobs.c

ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ramstage-y += bios_knobs.c

# WIV20150202 add ramtest
cbfs-files-y += img/memtest
img/memtest-file := payloads/eltan/memtest86+/memtest501.serial.com1.nospd.eltan-elf
img/memtest-position := 0xcd900
img/memtest-type := payload
# WIV20150202 add ramtest

cbfs-files-y += bootorder_map
bootorder_map-file := bootorder_map
bootorder_map-type := raw

cbfs-files-y += bootorder_def
bootorder_def-file := bootorder_def
bootorder_def-type := raw

# WIV20150126 add boot order
cbfs-files-y += bootorder
bootorder-file := src/mainboard/$(MAINBOARDDIR)/bootorder
bootorder-type := raw
bootorder-align := 0x1000

cbfs-files-y += etc/boot-menu-message
etc/boot-menu-message-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-message
etc/boot-menu-message-type := raw

cbfs-files-y += etc/boot-menu-key
etc/boot-menu-key-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-key
etc/boot-menu-key-type := raw

cbfs-files-y += etc/boot-menu-wait
etc/boot-menu-wait-file := src/mainboard/$(MAINBOARDDIR)/boot-menu-wait
etc/boot-menu-wait-type := raw
# WIV20150126 end add boot order

# add a SeaBIOS sercon-port file
cbfs-files-y += etc/sercon-port
etc/sercon-port-file := src/mainboard/$(MAINBOARDDIR)/sercon-port
etc/sercon-port-type := raw

# WIV20141001 START ADD SPD FROM FILE
## DIMM SPD for on-board memory
SPD_BIN = $(obj)/spd.bin

# Order of names in SPD_SOURCES is important!
SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-ECC
#SPD_SOURCES = HYNIX-2G-1333 HYNIX-4G-1333-NOECC

SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)

# Include spd rom data
$(SPD_BIN): $(SPD_DEPS) src/mainboard/$(MAINBOARDDIR)/Makefile.inc
echo " create SPD $@"
for f in $(SPD_DEPS); \
do for c in $$(cat $$f | grep -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@

cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
# WIV20141001 END ADD SPD FROM FILE

# iPXE

ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
IPXE_UART=COM$(call int-add,$(CONFIG_UART_FOR_CONSOLE) 1)
endif

ifeq ($(CONFIG_PXE_SERIAL_CONSOLE),y)
IPXE_SERIAL_CONSOLE = $(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO)
else
IPXE_SERIAL_CONSOLE = n
endif

ifeq ($(CONFIG_PXE_ROM),y)
PXE_ROM_FILE:=$(CONFIG_PXE_ROM_FILE)
endif
ifeq ($(CONFIG_BUILD_IPXE),y)
PXE_ROM_FILE:=payloads/external/iPXE/ipxe/ipxe.rom
endif

cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += genroms/pxe.rom
genroms/pxe.rom-file := $(PXE_ROM_FILE)
genroms/pxe.rom-type := raw

payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG)
$(MAKE) -C payloads/external/iPXE -f Makefile.inc all \
CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \
PXE_ROM_PCI_ID=$(subst $(comma),,$(CONFIG_PXE_ROM_ID)) \
CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \
CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \
CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \
IPXE_UART=$(IPXE_UART) \
CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \
CONFIG_PXE_CUSTOM_GENERAL_H=$(CONFIG_PXE_CUSTOM_GENERAL_H) \
CONFIG_PXE_CUSTOM_BOOTMENU_FILE=$(CONFIG_PXE_CUSTOM_BOOTMENU_FILE)

72 changes: 72 additions & 0 deletions src/mainboard/pcengines/apu4/OptionsIds.h
View file
@@ -0,0 +1,72 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/**
* @file
*
* IDS Option File
*
* This file is used to switch on/off IDS features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
*/
#ifndef _OPTION_IDS_H_
#define _OPTION_IDS_H_

/**
*
* This file generates the defaults tables for the Integrated Debug Support
* Module. The documented build options are imported from a user controlled
* file for processing. The build options for the Integrated Debug Support
* Module are listed below:
*
* IDSOPT_IDS_ENABLED
* IDSOPT_ERROR_TRAP_ENABLED
* IDSOPT_CONTROL_ENABLED
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/

//#define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_CONTROL_ENABLED TRUE

//#define IDSOPT_TRACING_ENABLED TRUE
//#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
//#define IDS_DEBUG_PRINT_MASK (FCH_TRACE_ALL) // We just want to see the FCH stuff now
//#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_TRACING_CONSOLE_REDIRECT_IO TRUE

//#define IDSOPT_PERF_ANALYSIS TRUE
//#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
126 changes: 126 additions & 0 deletions src/mainboard/pcengines/apu4/PlatformGnbPcie.c
View file
@@ -0,0 +1,126 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#include <northbridge/amd/pi/agesawrapper.h>

#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE

const PCIe_PORT_DESCRIPTOR PortList [] = {
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x01, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x02, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x03, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x04, 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
HotplugDisabled,
PcieGenMaxSupported,
PcieGenMaxSupported,
AspmDisabled, 0x05, 0)
}
};

const PCIe_DDI_DESCRIPTOR DdiList [] = {
/* DP0 to HDMI0/DP */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
},
/* DP1 to FCH */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
},
/* DP2 to HDMI1/DP */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
},
};

const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList
};

/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] **PeiServices
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
}
31 changes: 31 additions & 0 deletions src/mainboard/pcengines/apu4/PlatformGnbPcieComplex.h
View file
@@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H

#include <Porting.h>
#include <AGESA.h>

VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);

#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
84 changes: 84 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/gpe.asl
View file
@@ -0,0 +1,84 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
}

/* Temp warning (TWarn) event */
Method(_L09) {
/* DBGO("\\_GPE\\_L09\n") */
/* Notify (\_TZ.TZ00, 0x80) */
}

/* USB controller PME# */
Method(_L0B) {
/* DBGO("\\_GPE\\_L0B\n") */
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON AND !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
#endif //!CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Method(_L10) {
/* DBGO("\\_GPE\\_L10\n") */
}

/* ExtEvent1 SCI event */
Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */
}

/* GPIO0 or GEvent8 event */
Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

// /* Azalia SCI event */
// Method(_L1B) {
// /* DBGO("\\_GPE\\_L1B\n") */
// Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
// Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
// }
} /* End Scope GPE */
1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu4/acpi/ide.asl
View file
@@ -0,0 +1 @@
/* No IDE functionality */
41 changes: 41 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/mainboard.asl
View file
@@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */

Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */

Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */

/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */
Name(PMOD, One) /* Assume APIC */

/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) {
, 11,
USBS, 1,
}
475 changes: 475 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/pci_int.asl
View file

Large diffs are not rendered by default.

217 changes: 217 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/routing.asl
View file
@@ -0,0 +1,217 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "routing.asl"
}
*/

/* Routing is in System Bus scope */
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - F16 Host Controller */

/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 },


/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },

/* FCH devices */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },

#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 0, INTC, 0 },

#else // CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },

Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 1, INTB, 0 },

Package(){0x0016FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 1, INTB, 0 },
#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, INTC, 0 },
Package(){0x0010FFFF, 1, INTB, 0 },

/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },

})

Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - F15 Host Controller */

/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, 0, 44 },
Package(){0x0001FFFF, 1, 0, 45 },

/* Bus 0, Dev 2 - PCIe Bridges */
Package(){0x0002FFFF, 0, 0, 24 },
Package(){0x0002FFFF, 1, 0, 25 },
Package(){0x0002FFFF, 2, 0, 26 },
Package(){0x0002FFFF, 3, 0, 27 },


/* SB devices in APIC mode */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON || CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: EHCI */

Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 0, 0, 18 },

#else //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0012FFFF, 1, 0, 17 },

Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 17 },

Package(){0x0016FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 1, 0, 17 },
#endif //CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON OR CONFIG_SOUTHBRIDGE_AMD_PI_AVALON

/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, 0, 0x12},
Package(){0x0010FFFF, 1, 0, 0x11},

/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, 0, 19 },

})

Name(PS2, Package(){
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})

/* GFX */
Name(PS4, Package(){
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, 0, 24 },
Package(){0x0000FFFF, 1, 0, 25 },
Package(){0x0000FFFF, 2, 0, 26 },
Package(){0x0000FFFF, 3, 0, 27 },
})

/* GPP 0 */
Name(PS5, Package(){
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
Package(){0x0000FFFF, 0, 0, 28 },
Package(){0x0000FFFF, 1, 0, 29 },
Package(){0x0000FFFF, 2, 0, 30 },
Package(){0x0000FFFF, 3, 0, 31 },
})

/* GPP 1 */
Name(PS6, Package(){
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
Package(){0x0000FFFF, 0, 0, 32 },
Package(){0x0000FFFF, 1, 0, 33 },
Package(){0x0000FFFF, 2, 0, 34 },
Package(){0x0000FFFF, 3, 0, 35 },
})

/* GPP 2 */
Name(PS7, Package(){
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
Package(){0x0000FFFF, 0, 0, 36 },
Package(){0x0000FFFF, 1, 0, 37 },
Package(){0x0000FFFF, 2, 0, 38 },
Package(){0x0000FFFF, 3, 0, 39 },
})

/* GPP 3 */
Name(PS8, Package(){
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS8, Package(){
Package(){0x0000FFFF, 0, 0, 40 },
Package(){0x0000FFFF, 1, 0, 41 },
Package(){0x0000FFFF, 2, 0, 42 },
Package(){0x0000FFFF, 3, 0, 43 },
})
1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu4/acpi/sata.asl
View file
@@ -0,0 +1 @@
/* No SATA functionality */
27 changes: 27 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/si.asl
View file
@@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

Scope(\_SI) {
Method(_SST, 1) {
/* DBGO("\\_SI\\_SST\n") */
/* DBGO(" New Indicator state: ") */
/* DBGO(Arg0) */
/* DBGO("\n") */
}
} /* End Scope SI */
97 changes: 97 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/sleep.asl
View file
@@ -0,0 +1,97 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/* Wake status package */
Name(WKST,Package(){Zero, Zero})

/*
* \_PTS - Prepare to Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2, etc
*
*s Exit:
* -none-
*
* The _PTS control method is executed at the beginning of the sleep process
* for S1-S5. The sleeping value is passed to the _PTS control method. This
* control method may be executed a relatively long time before entering the
* sleep state and the OS may abort the operation without notification to
* the ACPI driver. This method cannot modify the configuration or power
* state of any device in the system.
*/

External(\_SB.APTS, MethodObj)
External(\_SB.AWAK, MethodObj)

Method(_PTS, 1) {
/* DBGO("\\_PTS\n") */
/* DBGO("From S0 to S") */
/* DBGO(Arg0) */
/* DBGO("\n") */

/* Clear wake status structure. */
Store(0, Index(WKST,0))
Store(0, Index(WKST,1))
Store(7, UPWS)
\_SB.APTS(Arg0)
} /* End Method(\_PTS) */

/*
* \_BFS OEM Back From Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* -none-
*/
Method(\_BFS, 1) {
/* DBGO("\\_BFS\n") */
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
}

/*
* \_WAK System Wake method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* Return package of 2 DWords
* Dword 1 - Status
* 0x00000000 wake succeeded
* 0x00000001 Wake was signaled but failed due to lack of power
* 0x00000002 Wake was signaled but failed due to thermal condition
* Dword 2 - Power Supply state
* if non-zero the effective S-state the power supply entered
*/
Method(\_WAK, 1) {
/* DBGO("\\_WAK\n") */
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
Store(1,USBS)

\_SB.AWAK(Arg0)

Return(WKST)
} /* End Method(\_WAK) */
31 changes: 31 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/superio.asl
View file
@@ -0,0 +1,31 @@
/* We don't have a real SIO but lets define the serial port here, this is where it belongs */

Device (COM1) {
Name (_HID, EISAID ("PNP0501"))
Name (_UID, 1)
Name (_ADR, 0)

Method (_STA, 0, NotSerialized) {
Return (0x0F)
}

Name (_CRS, ResourceTemplate ()
{
IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
IRQNoFlags () {4}
// IRQNoFlags () {}
})

Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
// IRQNoFlags () {4}
IRQNoFlags () {}
}
EndDependentFn ()
})
}



1 change: 1 addition & 0 deletions src/mainboard/pcengines/apu4/acpi/thermal.asl
View file
@@ -0,0 +1 @@
/* No thermal zone functionality */
41 changes: 41 additions & 0 deletions src/mainboard/pcengines/apu4/acpi/usb_oc.asl
View file
@@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/

/* simple name description */
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "usb.asl"
}
*/

/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
Name(UOM2, 0)
Name(UOM3, 7)
Name(UOM4, 2)
Name(UOM5, 2)
Name(UOM6, 6)
Name(UOM7, 2)
Name(UOM8, 6)
Name(UOM9, 6)