28 changes: 17 additions & 11 deletions src/mainboard/asrock/g41c-gs/romstage.c
View file
Expand Up @@ -22,6 +22,8 @@
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <lib.h>
#include <arch/stages.h>
Expand All @@ -30,7 +32,8 @@
#include <device/pnp_def.h>
#include <timestamp.h>

#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)

Expand All @@ -44,15 +47,19 @@ static void mb_lpc_setup(void)
setup_pch_gpios(&mainboard_gpio_map);

/* Set GPIOs on superio, enable UART */
nuvoton_pnp_enter_conf_state(SERIAL_DEV);
pnp_set_logical_device(SERIAL_DEV);

pnp_write_config(SERIAL_DEV, 0x1c, 0x80);
pnp_write_config(SERIAL_DEV, 0x27, 0x80);
pnp_write_config(SERIAL_DEV, 0x2a, 0x60);

nuvoton_pnp_exit_conf_state(SERIAL_DEV);

if (IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)) {
nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
pnp_set_logical_device(SERIAL_DEV_R2);

pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);

nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
} else { /* BOARD_ASROCK_G41C_GS */
winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
}
/* IRQ routing */
RCBA16(D31IR) = 0x0132;
RCBA16(D29IR) = 0x0237;
Expand Down Expand Up @@ -91,7 +98,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
mb_lpc_setup();
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

console_init();

Expand Down
0 src/mainboard/asrock/g41c-gs/devicetree.cb → ...g41c-gs/variants/g41c-gs-r2/devicetree.cb
View file
File renamed without changes.
138 changes: 138 additions & 0 deletions src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
View file
@@ -0,0 +1,138 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#

chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30
end
device pci 1.0 on end # PEG

device pci 2.0 on # Integrated graphics controller
subsystemid 0x1849 0x2e32
end
device pci 3.0 off end # ME
device pci 3.1 off end # ME
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b"

register "ide_enable_primary" = "0x1"
register "gpe0_en" = "0x440"

device pci 1b.0 on # Audio
subsystemid 0x1849 0x3662
end
device pci 1c.0 on end # PCIe 1
device pci 1c.1 on end # PCIe 2
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6
device pci 1d.0 on # USB
subsystemid 0x1849 0x27c8
end
device pci 1d.1 on # USB
subsystemid 0x1849 0x27c9
end
device pci 1d.2 on # USB
subsystemid 0x1849 0x27ca
end
device pci 1d.3 on # USB
subsystemid 0x1849 0x27cb
end
device pci 1d.7 on # USB
subsystemid 0x1849 0x27cc
end
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # ISA bridge
subsystemid 0x1849 0x27b8
chip superio/winbond/w83627dhg
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
irq 0x28 = 0x70
irq 0x2c = 0xd2
# parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2
device pnp 2e.5 on # Keyboard & MOUSE
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 0x0C
end
device pnp 2e.6 off end # SPI
device pnp 2e.7 off end # GPIO6
device pnp 2e.8 off end # WDT0#, PLED
device pnp 2e.9 off end # GPIO2
device pnp 2e.109 off end # GPIO3
device pnp 2e.209 on # GPIO4
irq 0xf4 = 0x73
end
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0xe4 = 0x10 # Power dram during s3
end
device pnp 2e.b on # HWM, front pannel LED
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.c off end # PECI, SST
end
end
device pci 1f.1 on # PATA/IDE
subsystemid 0x1849 0x27df
end
device pci 1f.2 on # SATA
subsystemid 0x1849 0x27c0
end
device pci 1f.3 on # SMbus
subsystemid 0x1849 0x27da
chip drivers/i2c/ck505 # W83115RG-965
# set SATA to fixed 100Mhz refclk
register "mask" = "{ 0x02 }"
register "regs" = "{ 0x02 }"
device i2c 69 on end
end
end
end
end
end
135 changes: 135 additions & 0 deletions src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
View file
@@ -0,0 +1,135 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#

chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30
end
device pci 1.0 on end # PEG

device pci 2.0 on # Integrated graphics controller
subsystemid 0x1849 0x2e32
end
device pci 3.0 off end # ME
device pci 3.1 off end # ME
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x0b"

register "ide_enable_primary" = "0x1"
register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
register "sata_ports_implemented" = "0x3"
register "gpe0_en" = "0x440"

device pci 1b.0 on # Audio
subsystemid 0x1849 0x3662
end
device pci 1c.0 on end # PCIe 1
device pci 1c.1 on end # PCIe 2
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1d.0 on # USB
subsystemid 0x1849 0x27c8
end
device pci 1d.1 on # USB
subsystemid 0x1849 0x27c9
end
device pci 1d.2 on # USB
subsystemid 0x1849 0x27ca
end
device pci 1d.3 on # USB
subsystemid 0x1849 0x27cb
end
device pci 1d.7 on # USB
subsystemid 0x1849 0x27cc
end
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA bridge
subsystemid 0x1849 0x27b8
chip superio/winbond/w83627dhg
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
irq 0x28 = 0x70
irq 0x2c = 0xd2
# parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off end # COM2
device pnp 2e.5 on # Keyboard & MOUSE
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 0x0C
end
device pnp 2e.6 off end # SPI
device pnp 2e.7 off end # GPIO6
device pnp 2e.8 off end # WDT0#, PLED
device pnp 2e.9 on end # GPIO2
device pnp 2e.109 on # GPIO3
irq 0xfe = 0x07
end
device pnp 2e.209 on # GPIO4
irq 0xf4 = 0x73
end
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0xe4 = 0x10 # Power dram during s3
end
device pnp 2e.b on # HWM, front pannel LED
io 0x60 = 0x290
irq 0x70 = 0
end
device pnp 2e.c off end # PECI, SST
end
end
device pci 1f.1 on # PATA/IDE
subsystemid 0x1849 0x27df
end
device pci 1f.2 on # SATA
subsystemid 0x1849 0x27c0
end
device pci 1f.3 on # SMbus
subsystemid 0x1849 0x27da
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end
2 changes: 1 addition & 1 deletion src/mainboard/asus/kcma-d8/acpi_tables.c
View file
Expand Up @@ -66,7 +66,7 @@ unsigned long acpi_fill_madt(unsigned long current)
return current;
}

unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
{
uint8_t *p;

Expand Down
8 changes: 4 additions & 4 deletions src/mainboard/asus/kcma-d8/romstage.c
View file
Expand Up @@ -247,7 +247,7 @@ static void execute_memory_test(void)
uint32_t x;
uint32_t y;
uint32_t z;
uint32_t* dataptr;
uint32_t *dataptr;
uint32_t readback;
uint32_t start = 0x300000;
printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n");
Expand Down Expand Up @@ -317,7 +317,7 @@ static void execute_memory_test(void)

static spinlock_t printk_spinlock CAR_GLOBAL;

spinlock_t* romstage_console_lock(void)
spinlock_t *romstage_console_lock(void)
{
return car_get_var_ptr(&printk_spinlock);
}
Expand All @@ -329,7 +329,7 @@ void initialize_romstage_console_lock(void)

static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL;

spinlock_t* romstage_nvram_cbfs_lock(void)
spinlock_t *romstage_nvram_cbfs_lock(void)
{
return car_get_var_ptr(&nvram_cbfs_spinlock);
}
Expand All @@ -341,7 +341,7 @@ void initialize_romstage_nvram_cbfs_lock(void)

static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL;

spinlock_t* romstage_microcode_cbfs_lock(void)
spinlock_t *romstage_microcode_cbfs_lock(void)
{
return car_get_var_ptr(&microcode_cbfs_spinlock);
}
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/kgpe-d16/acpi_tables.c
View file
Expand Up @@ -66,7 +66,7 @@ unsigned long acpi_fill_madt(unsigned long current)
return current;
}

unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
{
uint8_t *p;

Expand Down
8 changes: 4 additions & 4 deletions src/mainboard/asus/kgpe-d16/romstage.c
View file
Expand Up @@ -288,7 +288,7 @@ static void execute_memory_test(void)
uint32_t x;
uint32_t y;
uint32_t z;
uint32_t* dataptr;
uint32_t *dataptr;
uint32_t readback;
uint32_t start = 0x300000;
printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n");
Expand Down Expand Up @@ -358,7 +358,7 @@ static void execute_memory_test(void)

static spinlock_t printk_spinlock CAR_GLOBAL;

spinlock_t* romstage_console_lock(void)
spinlock_t *romstage_console_lock(void)
{
return car_get_var_ptr(&printk_spinlock);
}
Expand All @@ -370,7 +370,7 @@ void initialize_romstage_console_lock(void)

static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL;

spinlock_t* romstage_nvram_cbfs_lock(void)
spinlock_t *romstage_nvram_cbfs_lock(void)
{
return car_get_var_ptr(&nvram_cbfs_spinlock);
}
Expand All @@ -382,7 +382,7 @@ void initialize_romstage_nvram_cbfs_lock(void)

static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL;

spinlock_t* romstage_microcode_cbfs_lock(void)
spinlock_t *romstage_microcode_cbfs_lock(void)
{
return car_get_var_ptr(&microcode_cbfs_spinlock);
}
Expand Down
26 changes: 11 additions & 15 deletions src/mainboard/google/lars/Makefile.inc → src/mainboard/cavium/Kconfig
View file
@@ -1,8 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
## Copyright (C) 2015 Intel Corporation.
## Copyright (C) 2018 Facebook Inc
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
Expand All @@ -13,22 +12,19 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if VENDOR_CAVIUM

subdirs-y += spd
choice
prompt "Mainboard model"

bootblock-y += bootblock_mainboard.c
source "src/mainboard/cavium/*/Kconfig.name"

romstage-y += pei_data.c
endchoice

bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
source "src/mainboard/cavium/*/Kconfig"

ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
config MAINBOARD_VENDOR
string "Mainboard Vendor"
default "Cavium"

ramstage-y += mainboard.c
ramstage-y += pei_data.c
ramstage-y += ramstage.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
endif # VENDOR_CAVIUM
2 changes: 2 additions & 0 deletions src/mainboard/cavium/Kconfig.name
View file
@@ -0,0 +1,2 @@
config VENDOR_CAVIUM
bool "Cavium"
71 changes: 71 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/Kconfig
View file
@@ -0,0 +1,71 @@
##
## This file is part of the coreboot project.
##
## Copyright 2018 Facebook, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##

if BOARD_CAVIUM_CN8100_SFF_EVB

config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select COMMON_CBFS_SPI_WRAPPER
select RTC
select SOC_CAVIUM_CN81XX
select SPI_FLASH
select SPI_FLASH_STMICRO

config MAINBOARD_DIR
string
default "cavium/cn8100_sff_evb"

config MAINBOARD_VENDOR
string
default "Cavium"

config DRAM_SIZE_MB
int
default 8192

config BOOT_DEVICE_SPI_FLASH_BUS
int
default 0

config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0x87E028000000

config UART_FOR_CONSOLE
int
depends on DRIVERS_UART
default 0

config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"

config MAX_CPUS
default 4

##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
config DEVICETREE
string
default "devicetree.cb"

config MAINBOARD_PART_NUMBER
string
default "CN8100_SFF_EVB"

endif
2 changes: 2 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/Kconfig.name
View file
@@ -0,0 +1,2 @@
config BOARD_CAVIUM_CN8100_SFF_EVB
bool "CN8100 SFF EVB"
24 changes: 9 additions & 15 deletions src/mainboard/google/chell/Makefile.inc → ...nboard/cavium/cn8100_sff_evb/Makefile.inc
View file
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2015 Google Inc.
## Copyright 2017-present Facebook, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
Expand All @@ -13,21 +13,15 @@
## GNU General Public License for more details.
##

subdirs-y += spd
bootblock-y += bootblock.c
bootblock-y += memlayout.ld

bootblock-y += bootblock_mainboard.c

romstage-y += pei_data.c

bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += memlayout.ld
romstage-y += romstage.c
romstage-y += bdk_devicetree.c

ramstage-y += mainboard.c
ramstage-y += pei_data.c
ramstage-y += ramstage.c
ramstage-y += memlayout.ld
ramstage-y += bdk_devicetree.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
verstage-y += memlayout.ld
125 changes: 125 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c
View file
@@ -0,0 +1,125 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017-present Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/

// This file is automatically generated.
// DO NOT EDIT BY HAND.

#include <bdk-devicetree.h>

const struct bdk_devicetree_key_value devtree[] = {
{"DDR-TEST-BOOT", "1"},
{"DDR-CONFIG-DQX-CTL", "0x4"},
{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},
{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"},
{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"},
{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"},
{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"},
{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"},
{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"},
{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"},
{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"},
{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"},
{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"},
{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"},
{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"},
{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"},
{"DDR-CONFIG-CUSTOM-CK-CTL", "0x4"},
{"DDR-CONFIG-CUSTOM-CMD-CTL", "0x4"},
{"DDR-CONFIG-CUSTOM-CTL-CTL", "0x4"},
{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"},
{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"},
{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"},
{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"},
{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"},
{"PHY-ADDRESS.N0.BGX0.P0", "0xff000010"},
{"PHY-ADDRESS.N0.BGX0.P1", "0xff000011"},
{"PHY-ADDRESS.N0.BGX0.P2", "0xff000012"},
{"PHY-ADDRESS.N0.BGX0.P3", "0xff000013"},
{"PHY-ADDRESS.N0.BGX1.P0", "0xff002014"},
{"PHY-ADDRESS.N0.BGX1.P1", "0xff002014"},
{"PHY-ADDRESS.N0.BGX2.P0", "0xff000000"},
{"BGX-ENABLE.N0.BGX0.P0", "1"},
{"BGX-ENABLE.N0.BGX0.P1", "1"},
{"BGX-ENABLE.N0.BGX0.P2", "1"},
{"BGX-ENABLE.N0.BGX0.P3", "1"},
{"BGX-ENABLE.N0.BGX1.P0", "1"},
{"BGX-ENABLE.N0.BGX1.P1", "1"},
{"BGX-ENABLE.N0.BGX2.P0", "1"},
{"BDK-NUM-PACKET-BUFFERS", "0x1000"},
{"BDK-PACKET-BUFFER-SIZE", "0x400"},
{"BDK-SHOW-LINK-STATUS", "1"},
{"BDK-COREMASK", "0"},
{"MULTI-NODE", "0"},
{"QLM-AUTO-CONFIG", "0"},
{"QLM-DIP-AUTO-CONFIG", "1"},
{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"},
{"USB-PWR-GPIO.N0.PORT0", "12"},
{"USB-PWR-GPIO-POLARITY.N0.PORT0", "0"},
{"USB-REFCLK-SRC.N0.PORT0", "0"},
{"GPIO-PIN-SELECT-GPIO15", "0x24f"},
{"GPIO-PIN-SELECT-GPIO16", "0x24e"},
{"GPIO-PIN-SELECT-GPIO17", "0x24b"},
{"GPIO-PIN-SELECT-GPIO18", "0x247"},
{"GPIO-PIN-SELECT-GPIO19", "0x24d"},
{"GPIO-PIN-SELECT-GPIO20", "0x24c"},
{"GPIO-PIN-SELECT-GPIO37", "0x24a"},
{"GPIO-PIN-SELECT-GPIO38", "0x246"},
{"GPIO-PIN-SELECT-GPIO7", "0xe1"},
{"GPIO-PIN-SELECT-GPIO24", "0xeb"},
{"GPIO-PIN-SELECT-GPIO27", "0xed"},
{"GPIO-PIN-SELECT-GPIO28", "0xe3"},
{"GPIO-PIN-SELECT-GPIO29", "0xe0"},
{"GPIO-PIN-SELECT-GPIO30", "0xe2"},
{"GPIO-PIN-SELECT-GPIO40", "0x112"},
{"GPIO-PIN-SELECT-GPIO41", "0x113"},
{"GPIO-PIN-SELECT-GPIO42", "0x114"},
{"GPIO-PIN-SELECT-GPIO43", "0x115"},
{"GPIO-PIN-SELECT-GPIO44", "0x116"},
{"GPIO-PIN-SELECT-GPIO45", "0x117"},
{"GPIO-PIN-SELECT-GPIO46", "0x118"},
{"GPIO-PIN-SELECT-GPIO47", "0x119"},
{"GPIO-POLARITY-GPIO7", "1"},
{"GPIO-POLARITY-GPIO27", "1"},
{"GPIO-POLARITY-GPIO28", "1"},
{"GPIO-POLARITY-GPIO30", "1"},
{0, 0},
};
24 changes: 24 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/board.fmd
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@@ -0,0 +1,24 @@
FLASH@0x0 8M {
WP_RO@0x0 0x400000 {
RO_SECTION@0x0 0x200000 {
# bootblock includes trusted/non-trusted CLIB, CSIB,
# and BL1FWs packaged in
# src/soc/cavium/common/Makefile.inc.
BOOTBLOCK@0x10000 0x70000
FMAP@0x90000 0x1000
COREBOOT(CBFS)@0x100000 0x100000
}
}
RW_SECTION_A@0x400000 0xe8000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0xe5f00
RW_FWID_A@0xe7f00 0x100
}
RW_UNUSED@0x4e8000 0x8000
RW_ELOG@0x5d8000 0x1000
RW_SHARED@0x5e0000 0x10000 {
SHARED_DATA@0x0 0x10000
}
RW_NVRAM@0x5f0000 0x10000
CONSOLE@0x700000 0x100000
}
6 changes: 6 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/board_info.txt
View file
@@ -0,0 +1,6 @@
Vendor name: Cavium
Board name: CN81XX SFF EVB
Category: eval
ROM protocol: SPI
ROM socketed: n
Flashrom support: n
44 changes: 44 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/bootblock.c
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@@ -0,0 +1,44 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <bootblock_common.h>
#include <soc/soc.h>
#include <soc/spi.h>
#include <soc/uart.h>

void bootblock_mainboard_early_init(void)
{
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))
uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);
}
}

static void configure_spi_flash(void)
{
/* FIXME: Only tested on EM100 Pro */
spi_init_custom(0, // bus
25000000, // speed Hz
0, // idle low disabled
0, // zero idle cycles between transfers
0, // MSB first
0, // Chip select 0
1); // assert is high
}

void bootblock_mainboard_init(void)
{
configure_spi_flash();
}
496 changes: 496 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/cn81xx-linux.dtsi
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Large diffs are not rendered by default.

802 changes: 802 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/ddr4-common.dtsi
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Large diffs are not rendered by default.

210 changes: 210 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
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@@ -0,0 +1,210 @@
##
## This file is part of the coreboot project.
##
## Copyright 2017-present Facebook, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##

chip soc/cavium/cn81xx
device cpu_cluster 0 on end

device domain 0 on
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.0 on # PCI bridge
chip soc/cavium/common/pci
register "secure" = "0"
device pci 00.0 on end # MRML
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 00.1 on end # RESET
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 00.2 on end # DAP
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 00.3 on end # MDIO
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 00.4 on end # FUSE
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.2 on end # SGPIO
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.3 on end # SMI
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.4 on end # MMC
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 01.5 on end # KEY
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 01.6 on end # BOOT BUS
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.7 on end # PBUS
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 02.0 on end # XCV
end
device pci 04.0 on end

chip soc/cavium/common/pci
register "secure" = "0"
device pci 06.0 on end # L2C-TAD
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 07.0 on end # L2C-CBC
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 07.4 on end # L2C-MCI
end

chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.0 on end # UUA0
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.1 on end # UUA1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.2 on end # UUA2
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.3 on end # UUA3
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.4 on end # VRM
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 09.0 on end # I2C0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 09.1 on end # I2C1
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 0a.0 on end # PCC Bridge
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0b.0 on end # IOBN
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 0c.0 on end # OCLA0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 0c.1 on end # OCLA1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0d.0 on end
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0e.0 on end # PCIe0
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0e.1 on end # PCIe1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0e.2 on end # PCIe2
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 10.0 on end # bgx0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 10.1 on end # bgx1
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 11.0 on end # rgx0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 12.0 on end # MAC
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.0 on end # GSER0
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.1 on end # GSER1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.2 on end # GSER2
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.3 on end # GSER3
end
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 02.0 on end #SMMU
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 03.0 on end #GIC
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 04.0 on end #GTI
end

device pci 05.0 on end # NIC
device pci 06.0 on end # GPIO
device pci 07.0 on end # SPI
device pci 08.0 on end # MIO
device pci 09.0 on end # PCI bridge
device pci 0a.0 on end # PCI bridge
device pci 0b.0 on end # NFC
device pci 0c.0 on end # PCI bridge
device pci 0d.0 on end # PCM
device pci 0e.0 on end # VRM
device pci 0f.0 on end # PCI bridge

device pci 10.0 on end # USB0
device pci 11.0 on end # USB1
device pci 16.0 on end # SATA0
device pci 17.0 on end # SATA1
end
end
end
285 changes: 285 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/mainboard.c
View file
@@ -0,0 +1,285 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017-2018 Facebook, Inc.
* Copyright 2003-2017 Cavium Inc. (support@cavium.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
*/

#include <device/device.h>
#include <libbdk-hal/bdk-config.h>
#include <libbdk-hal/bdk-twsi.h>
#include <soc/twsi.h>
#include <soc/gpio.h>
#include <delay.h>
#include <soc/uart.h>
#include <console/console.h>
#include <soc/clock.h>
#include <soc/gpio.h>
#include <soc/timer.h>
#include <soc/cpu.h>
#include <soc/sdram.h>

static void mainboard_print_info(void)
{
printk(BIOS_INFO, "MB: trusted boot : %s\n",
gpio_strap_value(10) ? "yes" : "no");

const size_t boot_method = gpio_strap_value(0) |
(gpio_strap_value(1) << 1) |
(gpio_strap_value(2) << 2) |
(gpio_strap_value(3) << 3);

printk(BIOS_INFO, "MB: boot method : ");
switch (boot_method) {
case 0x2:
case 0x3:
printk(BIOS_INFO, "EMMC\n");
break;
case 0x5:
case 0x6:
printk(BIOS_INFO, "SPI\n");
break;
case 0x8:
printk(BIOS_INFO, "REMOTE\n");
break;
case 0xc:
case 0xd:
printk(BIOS_INFO, "PCIe\n");
break;
default:
printk(BIOS_INFO, "unknown\n");
}

printk(BIOS_INFO, "MB: REFclk : %llu MHz\n",
thunderx_get_ref_clock() / 1000000ULL);

printk(BIOS_INFO, "MB: IOclk : %llu MHz\n",
thunderx_get_io_clock() / 1000000ULL);

printk(BIOS_INFO, "MB: COREclk : %llu MHz\n",
thunderx_get_core_clock() / 1000000ULL);

printk(BIOS_INFO, "MB: #CPU cores : %zu\n",
cpu_get_num_available_cores());

printk(BIOS_INFO, "MB: RAM : %zu MiB\n",
sdram_size_mb());
}

extern const struct bdk_devicetree_key_value devtree[];

static void mainboard_init(struct device *dev)
{
size_t i;

/* Init UARTs */
for (i = 0; i < 4; i++) {
if (!uart_is_enabled(i))
uart_setup(i, 0);
}

/* Init timer */
soc_timer_init();

/* Init CPUs */
for (i = 1; i < CONFIG_MAX_CPUS; i++)
start_cpu(i, NULL);
}

static void mainboard_enable(struct device *dev)
{
dev->ops->init = &mainboard_init;

bdk_config_set_fdt(devtree);

/*
* Adapted from Cavium's devicetree TWSI-WRITE:
* Init board-specific I2C hardware:
*/
twsi_init(0, I2C_SPEED_STANDARD);

/* Initialize IO expander U6 to power-up defaults */
/* float all pins 0.0-0.7 */
bdk_twsix_write_ia(0,0,0x21,6,1,1,0xff);
/* float all pins 1.0-1.7 */
bdk_twsix_write_ia(0,0,0x21,7,1,1,0xff);
/* 0.x: all outputs low, but disabled */
bdk_twsix_write_ia(0,0,0x21,2,1,1,0x00);
/* 1.x: all outputs low, but disabled */
bdk_twsix_write_ia(0,0,0x21,3,1,1,0x00);
/* 0.x: no polarity inversion */
bdk_twsix_write_ia(0,0,0x21,4,1,1,0x00);
/* 1.x: no polarity inversion */
bdk_twsix_write_ia(0,0,0x21,5,1,1,0x00);
/* Initialize IO expander U89 to power-up defaults */
/* float all pins 0.0-0.7 */
bdk_twsix_write_ia(0,0,0x22,6,1,1,0xff);
/* float all pins 1.0-1.7 */
bdk_twsix_write_ia(0,0,0x22,7,1,1,0xff);
/* 0.x: all outputs low, but disabled */
bdk_twsix_write_ia(0,0,0x22,2,1,1,0x00);
/* 1.x: all outputs low, but disabled */
bdk_twsix_write_ia(0,0,0x22,3,1,1,0x00);
/* 0.x: no polarity inversion */
bdk_twsix_write_ia(0,0,0x22,4,1,1,0x00);
/* 1.x: no polarity inversion */
bdk_twsix_write_ia(0,0,0x22,5,1,1,0x00);
/* set outputs SLIC_RESET_L=0 and SPI_SEL=0 */
bdk_twsix_write_ia(0,0,0x21,6,1,1,0xee); /* 0.0 & 0.4 are outputs */

/* Select channel-0 in PCA9546A to enable SFI */
bdk_twsix_write_ia(0, 0, 0x70, 0, 1, 1, 0x7);
mdelay(10);
/* Configure I2C-GPIO expander I/O directions */
bdk_twsix_write_ia(0, 0, 0x22, 6, 1, 1, 0x07);
mdelay(10);
/* Configure I2C-GPIO expander I/O directions */
bdk_twsix_write_ia(0, 0, 0x22, 7, 1, 1, 0x38);
mdelay(10);
/* Turn on SFP+ Transmitters */
bdk_twsix_write_ia(0, 0, 0x22, 2, 1, 1, 0x0);
mdelay(10);
/* Set VSC7224 to I2C mode */
bdk_twsix_write_ia(0, 0, 0x22, 3, 1, 1, 0x0);
mdelay(10);
/* Assert VSC7224 reset*/
bdk_twsix_write_ia(0, 0, 0x22, 2, 1, 1, 0x80);
mdelay(50);
/* Deassert VSC7224 reset*/
bdk_twsix_write_ia(0, 0, 0x22, 2, 1, 1, 0x0);
mdelay(50);
/* Page select FSYNC0 (0x30) */
bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0030);
mdelay(10);
/* Set FSYNC0 for 10.3125Gbps See Table 3 */
bdk_twsix_write_ia(0, 0, 0x14, 0x80, 2, 1, 0x2841);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x81, 2, 1, 0x0008);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x82, 2, 1, 0x7a00);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x83, 2, 1, 0x000f);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x84, 2, 1, 0x9c18);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x85, 2, 1, 0x0);
mdelay(10);

/* All channels Rx settings set equally */
bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0050);
mdelay(10);
/* Shrink EQ_BUFF */
bdk_twsix_write_ia(0, 0, 0x14, 0x82, 2, 1, 0x0014);
mdelay(10);
/* Select min DFE Delay (DFE_DELAY) */
bdk_twsix_write_ia(0, 0, 0x14, 0x90, 2, 1, 0x5585);
mdelay(10);
/* Set DFE 1-3 limit (DXMAX) = 32dec, AP Max limit = 127 decimal */
bdk_twsix_write_ia(0, 0, 0x14, 0x92, 2, 1, 0x207f);
mdelay(10);
/* Set AP Min limit = 32 decimal */
bdk_twsix_write_ia(0, 0, 0x14, 0x93, 2, 1, 0x2000);
mdelay(10);
/* Set DFE Averaging to the slowest (DFE_AVG) */
bdk_twsix_write_ia(0, 0, 0x14, 0x94, 2, 1, 0x0031);
mdelay(10);
/* Set Inductor Bypass OD_IND_BYP = 0 & fastest Rise/Fall */
bdk_twsix_write_ia(0, 0, 0x14, 0x9c, 2, 1, 0x0000);
mdelay(10);
/* Setting DFE Boost = none. Must set for rev C
* (if DFE in adapt mode) */
bdk_twsix_write_ia(0, 0, 0x14, 0xaa, 2, 1, 0x0888);
mdelay(10);
/* Setting EQ Min/Max = 8/72 */
bdk_twsix_write_ia(0, 0, 0x14, 0xa8, 2, 1, 0x2408);
mdelay(10);
/* Setting EQVGA = 96, when in EQVGA manual mode */
bdk_twsix_write_ia(0, 0, 0x14, 0xa9, 2, 1, 0x0060);
mdelay(10);
/* Setting SW_BFOCM, bits 15:14 to 01 */
bdk_twsix_write_ia(0, 0, 0x14, 0x87, 2, 1, 0x4021);
mdelay(10);
/* Turn off adaptive input equalization and VGA adaptive algorithm
* control */
bdk_twsix_write_ia(0, 0, 0x14, 0x89, 2, 1, 0x7313);
mdelay(10);
/* Turn on adaptive input equalization and VGA adaptive algorithm
* control */
bdk_twsix_write_ia(0, 0, 0x14, 0x89, 2, 1, 0x7f13);
mdelay(10);

/* TAP settings for each channel 0-3 */
/* Ch-0 Tx */
bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0000);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x001f);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x9a, 2, 1, 0x000f);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x9b, 2, 1, 0x0004);
mdelay(10);

/* Ch-1 Rx */
bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0001);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x1400);
mdelay(10);
/* Transmitter Output polarity Inverted (Unfortunately,
* Rx polarity lines are wrongly inverted on board */
bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x4000);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x000f);
mdelay(10);

/* Ch-2 Tx */
bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0002);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x001f);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x9a, 2, 1, 0x000f);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x9b, 2, 1, 0x0004);
mdelay(10);

/* Ch-3 Rx */
bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0003);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x1400);
mdelay(10);
/* Transmitter Output polarity Inverted (Unfortunately,
* Rx polarity lines are wrongly inverted on board */
bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x4000);
mdelay(10);
bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x000f);
mdelay(10);

/**
* The following hardware magically starts working after toggling
* GPIO_10_PHY_RESET_L:
* * SATA PHY
* * GBE PHY
* * XFI PHY
* * MMC
*/
gpio_output(10, 0);
udelay(100);
gpio_output(10, 1);

mainboard_print_info();
}

struct chip_operations mainboard_ops = {
.name = CONFIG_MAINBOARD_PART_NUMBER,
.enable_dev = mainboard_enable,
};
1 change: 1 addition & 0 deletions src/mainboard/cavium/cn8100_sff_evb/memlayout.ld
View file
@@ -0,0 +1 @@
#include <soc/memlayout.ld>
41 changes: 27 additions & 14 deletions src/mainboard/google/chell/ec.c → ...ainboard/cavium/cn8100_sff_evb/romstage.c
View file
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
* Copyright 2017-present Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -12,23 +11,37 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/

#include <arch/acpi.h>
#include <arch/exception.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#include <soc/sdram.h>
#include <soc/timer.h>
#include <soc/mmu.h>
#include <stdlib.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include "ec.h"
#include <program_loading.h>
#include <libbdk-hal/bdk-config.h>
#include <string.h>

extern const struct bdk_devicetree_key_value devtree[];

void mainboard_ec_init(void)
void main(void)
{
const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
};
watchdog_poke(0);

console_init();
exception_init();

bdk_config_set_fdt(devtree);

sdram_init();
soc_mmu_init();

printk(BIOS_DEBUG, "mainboard: EC init\n");
watchdog_poke(0);

google_chromeec_events_init(&info, acpi_is_wakeup_s3());
cbmem_initialize_empty();
run_ramstage();
}
282 changes: 282 additions & 0 deletions src/mainboard/cavium/cn8100_sff_evb/sff8104-linux.dts
View file
@@ -0,0 +1,282 @@
/*
* Cavium Thunder DTS file - Thunder board description
*
* Copyright (C) 2016, Cavium Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/

/dts-v1/;

/include/ "cn81xx-linux.dtsi"

&mrml_bridge {
mdio-nexus@1,3 {
mdio0@87e005003800 {
rgmii00: rgmii00 {
reg = <0> ;
compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22";
};

qsgmii00: qsgmii00 {
qlm-mode = "0x000,qsgmii";
reg = <0x10> ;
compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22";
};
qsgmii01: qsgmii01 {
qlm-mode = "0x001,qsgmii";
reg = <0x11> ;
compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22";
};
qsgmii02: qsgmii02 {
qlm-mode = "0x002,qsgmii";
reg = <0x12> ;
compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22";
};
qsgmii03: qsgmii03 {
qlm-mode = "0x003,qsgmii";
reg = <0x13> ;
compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22";
};
};
mdio1@87e005003880 {
xfi00: xfi00 {
qlm-mode = "0x000,xfi";
reg = <0x0>;
compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45";
};
};
};

rgx0 {
rgmii00 {
reg = <0>;
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&rgmii00>;
};
};

bgx0 {
/* typename+qlm+typenumber eg :
qsgmii+bgx0+sgmmi0
*/
qsgmii00 {
reg = <0>;
qlm-mode = "0x000,qsgmii";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&qsgmii00>;
};
qsgmii01 {
reg = <1>;
qlm-mode = "0x001,qsgmii";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&qsgmii01>;
};
qsgmii02 {
reg = <2>;
qlm-mode = "0x002,qsgmii";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&qsgmii02>;
};
qsgmii03 {
reg = <3>;
qlm-mode = "0x003,qsgmii";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&qsgmii03>;
};

xfi00 {
reg = <0>;
qlm-mode = "0x000,xfi";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&xfi00>;
};
};

bgx1 {
xfi10 {
reg = <0>;
qlm-mode = "0x010,xfi";
local-mac-address = [00 00 00 00 00 00];
};

xfi11 {
reg = <1>;
qlm-mode = "0x011,xfi";
local-mac-address = [00 00 00 00 00 00];
};
};


};

&mmc_1_4 {
/* NOTE: the BDK is responsible for swapping the two slots.
* Unfortunately there does not appear to be any way to read the
* position of SW2-7 in software.
*/
mmc-slot@0 {
compatible = "mmc-slot";
reg = <0>;
vmmc-supply = <&mmc_supply_3v3>;
max-frequency = <26000000>;
/* 1.8v is not supported */
no-1-8-v;
/* Bus width is only 4 bits maximum */
bus-width = <4>;
/* No write-protect switch is present */
disable-wp;
/* There is no card detection available; polling must be used. */
broken-cd;
/* High-speed mode is supported */
cap-sd-highspeed;
/* speed up device probing */
no-sdio;
no-mmc;
};
mmc-slot@1 {
compatible = "mmc-slot";
reg = <1>;
vmmc-supply = <&mmc_supply_3v3>;
max-frequency = <26000000>;
mmc-ddr-3_3v;
/* 1.8v is not supported */
no-1-8-v;
/* Bus width is only 8 bits maximum */
bus-width = <8>;
/* No write-protect switch is present */
disable-wp;
/* There is no card detection available; polling must be used. */
broken-cd;
/* High-speed mode is supported */
cap-mmc-highspeed;
/* eMMC device is soldered onto the board */
non-removable;
/* speed up device probing */
no-sdio;
no-sd;
};
};

&i2c_9_0 {
/* another pca9535 at 0x20 is only visible via jtag */
gpio1: gpio-i2c@21 {
compatible = "nxp,pca9535";
gpio-controller;
reg = <0x21>;
gpio_base = <48>;
pins = <48 16>;
ngpios = <16>; // standard
n_gpios = <16>; // deprecated, driver required
#gpio-cells = <2>;
};

gpio2: gpio-i2c@22 {
compatible = "nxp,pca9535";
gpio-controller;
reg = <0x22>;
gpio_base = <64>;
pins = <64 16>;
ngpios = <16>; // standard
n_gpios = <16>; // deprecated, driver required
#gpio-cells = <2>;
};

mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;

i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};

i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};

i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
};
};

&i2c_9_1 {
rom@54 {
compatible = "atmel,24c256";
reg = <0x54>;
pagesize = <64>;
};

rtc@68 {
compatible = "isil,isl12057";
reg = <0x68>;
};
};

&spi_7_0 {
flash@0 {
compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <16000000>;
#address-cells = <1>;
#size-cells = <1>;
};
flash@1 {
compatible = "spinand,mt29f", "mt29f";
reg = <0x1>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-mode = "none";
};
};

&nfc {
nand@1 {
reg = <0x1>;
nand-ecc-mode = "none";
};
};
2 changes: 1 addition & 1 deletion src/mainboard/emulation/qemu-i440fx/romstage.c
View file
Expand Up @@ -28,7 +28,7 @@

#include "memory.c"

void * asmlinkage romstage_main(unsigned long bist)
void *asmlinkage romstage_main(unsigned long bist)
{
int cbmem_was_initted;

Expand Down
9 changes: 5 additions & 4 deletions src/mainboard/facebook/watson/board.fmd
View file
@@ -1,9 +1,10 @@
FLASH@0xff000000 0x1000000 {
SI_DESC@0x0 0x1000
IDPROM@0x1000 0x500
UNUSED_1@0x1500 0x1FB00
UNUSED_1@0x1000 0x1000
IDPROM@0x2000 0x400
UNUSED_2@0x2400 0x1ec00
SI_ME@0x21000 0x3de000
UNUSED_2@0x400000 0x200000
UNUSED_3@0x400000 0x200000
SI_BIOS@0x600000 0xA00000 {
FMAP@0x0 0x1000
RW_MISC@0x1000 0xe000 {
Expand All @@ -19,7 +20,7 @@ FLASH@0xff000000 0x1000000 {
# This only exists to satisfy tools that specifically
# look for RO_VPD.
RO_VPD@0x30000 0x1000
UNUSED_3@0x31000 0x1CF000
UNUSED_4@0x31000 0x1cf000
COREBOOT(CBFS)@0x200000 0x800000
}
}
1 change: 1 addition & 0 deletions src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
View file
Expand Up @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS
select USE_NATIVE_RAMINIT
select SUPERIO_ITE_IT8728F
select MAINBOARD_HAS_LIBGFXINIT
select INTEL_GMA_HAVE_VBT
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT

Expand Down
Binary file added src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt
View file
Binary file not shown.
71 changes: 0 additions & 71 deletions src/mainboard/google/chell/Kconfig
View file

This file was deleted.

2 changes: 0 additions & 2 deletions src/mainboard/google/chell/Kconfig.name
View file

This file was deleted.

57 changes: 0 additions & 57 deletions src/mainboard/google/chell/chromeos.c
View file

This file was deleted.

38 changes: 0 additions & 38 deletions src/mainboard/google/chell/chromeos.fmd
View file

This file was deleted.

125 changes: 0 additions & 125 deletions src/mainboard/google/chell/cmos.layout
View file

This file was deleted.

55 changes: 0 additions & 55 deletions src/mainboard/google/chell/dsdt.asl
View file

This file was deleted.

58 changes: 0 additions & 58 deletions src/mainboard/google/chell/ec.h
View file

This file was deleted.

78 changes: 0 additions & 78 deletions src/mainboard/google/chell/mainboard.c
View file

This file was deleted.

62 changes: 0 additions & 62 deletions src/mainboard/google/chell/romstage.c
View file

This file was deleted.

89 changes: 0 additions & 89 deletions src/mainboard/google/chell/smihandler.c
View file

This file was deleted.

16 changes: 0 additions & 16 deletions src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex
View file

This file was deleted.

123 changes: 0 additions & 123 deletions src/mainboard/google/chell/spd/spd.c
View file

This file was deleted.

3 changes: 3 additions & 0 deletions src/mainboard/google/cyan/acpi/dptf.asl
View file
Expand Up @@ -3,6 +3,7 @@
*
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -14,6 +15,8 @@
* GNU General Public License for more details.
*/

#define HAVE_THERM_EVENT_HANDLER

/* Include Variant DPTF */
#include <variant/acpi/dptf.asl>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/eve/devicetree.cb
View file
Expand Up @@ -38,7 +38,6 @@ chip soc/intel/skylake
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "IshEnable" = "0"
register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/fizz/devicetree.cb
View file
Expand Up @@ -73,7 +73,6 @@ chip soc/intel/skylake
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "2"
register "IshEnable" = "0"
register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
Expand Down
41 changes: 30 additions & 11 deletions src/mainboard/google/glados/Kconfig
View file
@@ -1,26 +1,27 @@
if BOARD_GOOGLE_GLADOS

config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
config BOARD_GOOGLE_BASEBOARD_GLADOS
def_bool n
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_NAU8825
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_LPC
select EC_GOOGLE_CHROMEEC_MEC
select EC_GOOGLE_CHROMEEC_PD
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_SMI_HANDLER
select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select SOC_INTEL_SKYLAKE
select SYSTEM_TYPE_LAPTOP

if BOARD_GOOGLE_BASEBOARD_GLADOS

config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_LID_SWITCH
Expand All @@ -35,12 +36,26 @@ config MAINBOARD_DIR

config MAINBOARD_PART_NUMBER
string
default "Glados"
default "Chell" if BOARD_GOOGLE_CHELL
default "Glados" if BOARD_GOOGLE_GLADOS
default "Lars" if BOARD_GOOGLE_LARS

config MAINBOARD_FAMILY
string
default "Google_Glados"

config VARIANT_DIR
string
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
default "lars" if BOARD_GOOGLE_LARS

config DEVICETREE
string
default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS

config MAX_CPUS
int
default 8
Expand All @@ -52,20 +67,24 @@ config TPM_PIRQ
config INCLUDE_NHLT_BLOBS
bool "Include blobs for audio."
select NHLT_DMIC_2CH
select NHLT_DMIC_4CH
select NHLT_NAU88L25
select NHLT_SSM4567

config EC_GOOGLE_CHROMEEC_BOARDNAME
string
default "glados"
default "chell" if BOARD_GOOGLE_CHELL
default "glados" if BOARD_GOOGLE_GLADOS
default ""

config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
string
default "glados_pd"
default "chell_pd" if BOARD_GOOGLE_CHELL
default "glados_pd" if BOARD_GOOGLE_GLADOS
default ""

config GBB_HWID
string
depends on CHROMEOS
default "GLADOS TEST 1988"
default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
default "LARS TEST 5001" if BOARD_GOOGLE_LARS
endif
19 changes: 18 additions & 1 deletion src/mainboard/google/glados/Kconfig.name
View file
@@ -1,2 +1,19 @@
comment "Glados"

config BOARD_GOOGLE_CHELL
bool "-> Chell (HP Chromebook 13 G1)"
select BOARD_GOOGLE_BASEBOARD_GLADOS
select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS

config BOARD_GOOGLE_GLADOS
bool "Glados"
bool "-> Glados Skylake Reference Board"
select BOARD_GOOGLE_BASEBOARD_GLADOS
select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS
select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS

config BOARD_GOOGLE_LARS
bool "-> Lars (Acer Chromebook 14 for Work (CP5-471))"
select BOARD_GOOGLE_BASEBOARD_GLADOS
select DRIVERS_GENERIC_MAX98357A
select EXCLUDE_NATIVE_SD_INTERFACE
select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS
7 changes: 5 additions & 2 deletions src/mainboard/google/glados/Makefile.inc
View file
Expand Up @@ -17,7 +17,7 @@ subdirs-y += spd

bootblock-y += bootblock_mainboard.c

romstage-y += pei_data.c
romstage-y += spd/spd.c

bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
Expand All @@ -27,7 +27,10 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c

ramstage-y += mainboard.c
ramstage-y += pei_data.c
ramstage-y += ramstage.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
75 changes: 3 additions & 72 deletions src/mainboard/google/glados/acpi/dptf.asl
View file
Expand Up @@ -14,77 +14,8 @@
* GNU General Public License for more details.
*/

#define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 90
#define DPTF_CPU_ACTIVE_AC0 90
#define DPTF_CPU_ACTIVE_AC1 80
#define DPTF_CPU_ACTIVE_AC2 70
#define DPTF_CPU_ACTIVE_AC3 60
#define DPTF_CPU_ACTIVE_AC4 50
/* Include Variant DPTF */
#include <variant/acpi/dptf.asl>

#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Ambient"
#define DPTF_TSR0_PASSIVE 55
#define DPTF_TSR0_CRITICAL 70

#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Charger"
#define DPTF_TSR1_PASSIVE 55
#define DPTF_TSR1_CRITICAL 70

#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 55
#define DPTF_TSR2_CRITICAL 70

#define DPTF_TSR3_SENSOR_ID 4
#define DPTF_TSR3_SENSOR_NAME "WiFi"
#define DPTF_TSR3_PASSIVE 55
#define DPTF_TSR3_CRITICAL 70

/* SKL-Y EC already has a custom charge profile based on temperature. */
#undef DPTF_ENABLE_CHARGER

/* SKL-Y is Fanless design. */
#undef DPTF_ENABLE_FAN_CONTROL

Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },

/* CPU Effect on Temp Sensor 0 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },

/* CPU Effect on Temp Sensor 1 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },

/* CPU Effect on Temp Sensor 2 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },

/* CPU Effect on Temp Sensor 3 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
})

Name (MPPC, Package ()
{
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
1600, /* PowerLimitMinimum */
6000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
200 /* StepSize */
},
Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */
8000, /* PowerLimitMinimum */
8000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
1000 /* StepSize */
}
})

/* Include DPTF */
/* Include SoC DPTF */
#include <soc/intel/skylake/acpi/dptf/dptf.asl>
9 changes: 2 additions & 7 deletions src/mainboard/google/glados/acpi/ec.asl
View file
Expand Up @@ -15,13 +15,8 @@

/* mainboard configuration */
#include "../ec.h"
#include "../gpio.h"

/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE

/* Enable EC backed Keyboard Backlight in ACPI */
#define EC_ENABLE_KEYBOARD_BACKLIGHT
#include <variant/ec.h>
#include <variant/gpio.h>

/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
Expand Down
5 changes: 3 additions & 2 deletions src/mainboard/google/glados/acpi/mainboard.asl
View file
Expand Up @@ -13,12 +13,13 @@
* GNU General Public License for more details.
*/

#include "../gpio.h"

Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}

/* Variant-specific ACPI, including USB port defs */
#include <variant/acpi/mainboard.asl>
2 changes: 0 additions & 2 deletions src/mainboard/google/glados/acpi/superio.asl
View file
Expand Up @@ -14,8 +14,6 @@
*/

/* mainboard configuration */
#include "../ec.h"

#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/glados/bootblock_mainboard.c
View file
Expand Up @@ -15,7 +15,7 @@

#include <bootblock_common.h>
#include <soc/gpio.h>
#include "gpio.h"
#include <variant/gpio.h>

static void early_config_gpio(void)
{
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/google/glados/chromeos.c
View file
Expand Up @@ -14,14 +14,13 @@
* GNU General Public License for more details.
*/

#include <bootmode.h>
#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>

#include "gpio.h"
#include <variant/gpio.h>

#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
Expand Down
28 changes: 23 additions & 5 deletions src/mainboard/google/glados/mainboard.c
View file
Expand Up @@ -16,13 +16,17 @@
*/

#include <arch/acpi.h>
#include <baseboard/variant.h>
#include <console/console.h>
#include <device/device.h>
#include <stdlib.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"

static const char *oem_id_maxim = "INTEL";
static const char *oem_table_id_maxim = "SCRDMAX";

static void mainboard_init(struct device *dev)
{
mainboard_ec_init();
Expand All @@ -34,6 +38,8 @@ static unsigned long mainboard_write_acpi_tables(
uintptr_t start_addr;
uintptr_t end_addr;
struct nhlt *nhlt;
const char *oem_id = NULL;
const char *oem_table_id = NULL;

start_addr = current;

Expand All @@ -47,18 +53,30 @@ static unsigned long mainboard_write_acpi_tables(
printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");

/* 4 Channel DMIC array. */
if (nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH))
if (nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");

/* ADI Smart Amps for left and right. */
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
if (IS_ENABLED(CONFIG_NHLT_SSM4567))
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add ssm4567.\n");

/* MAXIM Smart Amps for left and right. */
if (IS_ENABLED(CONFIG_NHLT_MAX98357)) {
if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add max98357.\n");

oem_id = oem_id_maxim;
oem_table_id = oem_table_id_maxim;
}

/* NAU88l25 Headset codec. */
if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Couldn't add headset codec.\n");

end_addr = nhlt_soc_serialize(nhlt, start_addr);
end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
oem_id, oem_table_id, 0);

if (end_addr != start_addr)
acpi_add_table(rsdp, (void *)start_addr);
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/glados/ramstage.c
View file
Expand Up @@ -15,7 +15,7 @@
*/

#include <soc/ramstage.h>
#include "gpio.h"
#include <variant/gpio.h>

void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
{
Expand Down
17 changes: 17 additions & 0 deletions src/mainboard/google/glados/romstage.c
View file
Expand Up @@ -17,13 +17,30 @@

#include <string.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
#include "spd/spd.h"
#include <variant/ec.h>
#include <variant/gpio.h>

void mainboard_romstage_entry(struct romstage_params *params)
{
#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
/* Turn on keyboard backlight to indicate we are booting */
if (params->power_state->prev_sleep_state != ACPI_S3)
google_chromeec_kbbacklight(25);
#endif
/* Get SPD index */
gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};
params->pei_data->mem_cfg_id =
gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
Expand Down
20 changes: 4 additions & 16 deletions src/mainboard/google/glados/smihandler.c
View file
Expand Up @@ -16,6 +16,7 @@

#include <arch/acpi.h>
#include <arch/io.h>
#include <baseboard/variant.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <elog.h>
Expand All @@ -26,7 +27,7 @@
#include <soc/pm.h>
#include <soc/smm.h>
#include "ec.h"
#include "gpio.h"
#include <variant/gpio.h>

int mainboard_io_trap_handler(int smif)
{
Expand Down Expand Up @@ -54,21 +55,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts)
chromeec_smi_process_events();
}

static void mainboard_gpio_smi_sleep(u8 slp_typ)
__weak void mainboard_gpio_smi_sleep(void)
{
int i;

/* Power down the rails on any sleep type. */
gpio_t active_high_signals[] = {
EN_PP3300_KEPLER,
EN_PP3300_DX_TOUCH,
EN_PP3300_DX_EMMC,
EN_PP1800_DX_EMMC,
EN_PP3300_DX_CAM,
};

for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
gpio_set(active_high_signals[i], 0);
}

void mainboard_smi_sleep(u8 slp_typ)
Expand All @@ -77,7 +65,7 @@ void mainboard_smi_sleep(u8 slp_typ)
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);

mainboard_gpio_smi_sleep(slp_typ);
mainboard_gpio_smi_sleep();
}

int mainboard_smi_apmc(u8 apmc)
Expand Down
0 ...ell/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex → ...dos/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex
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0 ...ell/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex → ...dos/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex
View file
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0 ...x_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex → ...x_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
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File renamed without changes.
0 ...ell/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex → ...dos/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
View file
File renamed without changes.
0 ...ell/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex → ...dos/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
View file
File renamed without changes.
0 ...x_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex → ...x_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
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File renamed without changes.
0 ...ell/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex → ...dos/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex
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0 ...ell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex → ...dos/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex
View file
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0 ..._dimm_MT52L256M32D1PF-107-1G-1866.spd.hex → ..._dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
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0 ..._dimm_MT52L512M32D2PF-107-2G-1866.spd.hex → ..._dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
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0 ...sung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex → ...sung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
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File renamed without changes.
0 .../spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex → .../spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
View file
File renamed without changes.
0 .../spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex → .../spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
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0 ...sung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex → ...sung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
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0 .../spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex → .../spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
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0 .../spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex → .../spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex
View file
File renamed without changes.
21 changes: 10 additions & 11 deletions src/mainboard/google/glados/spd/spd.c
View file
Expand Up @@ -22,8 +22,7 @@
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <string.h>

#include "../gpio.h"
#include <baseboard/variant.h>
#include "spd.h"

static void mainboard_print_spd_info(uint8_t spd[])
Expand Down Expand Up @@ -77,21 +76,20 @@ static void mainboard_print_spd_info(uint8_t spd[])
}
}

__weak int is_dual_channel(const int spd_index)
{
/* default to dual channel */
return 1;
}

/* Copy SPD data for on-board memory */
void mainboard_fill_spd_data(struct pei_data *pei_data)
{
char *spd_file;
size_t spd_file_len;
int spd_index;

gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};

spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
spd_index = pei_data->mem_cfg_id;
printk(BIOS_INFO, "SPD index %d\n", spd_index);

/* Load SPD data from CBFS */
Expand All @@ -113,7 +111,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
/* Assume same memory in both channels */
spd_index *= SPD_LEN;
memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
if (is_dual_channel(spd_index))
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);

/* Make sure a valid SPD was found */
if (pei_data->spd_data[0][0][0] == 0)
Expand Down
21 changes: 21 additions & 0 deletions src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h
View file
@@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#ifndef GLADOS_VARIANT_H
#define GLADOS_VARIANT_H

int is_dual_channel(const int spd_index);
void mainboard_gpio_smi_sleep(void);

#endif /* GLADOS_VARIANT_H */
4 changes: 3 additions & 1 deletion src/mainboard/google/chell/spd/Makefile.inc → ...google/glados/variants/chell/Makefile.inc
View file
Expand Up @@ -14,7 +14,9 @@
## GNU General Public License for more details.
##

romstage-y += spd.c
romstage-y += variant.c
ramstage-y += variant.c
smm-y += variant.c

SPD_BIN = $(obj)/spd.bin

Expand Down