diff --git a/Documentation/corebootBuildingGuide.tex b/Documentation/corebootBuildingGuide.tex
diff --git a/Documentation/gerrit_guidelines.md b/Documentation/gerrit_guidelines.md
@@ -41,7 +41,7 @@ project you're submitting the changes to. If you’re submitting code that
 you wrote that might be owned by your employer, make sure that your
 employer is aware and you are authorized to submit the code. For
 clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
 
 * Let non-trivial patches sit in a review state for at least 24 hours
 before submission. Remember that there are coreboot developers in timezones
@@ -205,7 +205,7 @@ would be a good reviewer, look in the MAINTAINERS file or git history of
 the files that you’ve changed, and add those people.
 
 * Familiarize yourself with the coreboot [commit message
-guidelines](http://www.coreboot.org/Git#Commit_messages), before pushing
+guidelines](https://www.coreboot.org/Git#Commit_messages), before pushing
 patches. This will help to keep annoying requests to fix your commit
 message to a minimum.
 

diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md
@@ -0,0 +1,124 @@
+libgfxinit - Native Graphics Initialization
+===========================================
+
+Introduction and Current State in coreboot
+------------------------------------------
+
+*libgfxinit* is a library of full-featured graphics initialization
+(aka. modesetting) drivers. It's implemented in SPARK (a subset of
+Ada with formal verification features). While not restricted to in
+any way, it currently only supports Intel's integrated gfx control-
+lers (GMA).
+
+Currently, it supports the Intel Core i3/i5/i7 processor line and
+will support HDMI and DP on the Atom successor Apollo Lake. At the
+time of writing, Sandy Bridge, Ivy Bridge, and Haswell are veri-
+fied to work within *coreboot*.
+
+GMA: Framebuffer Configuration
+------------------------------
+
+*coreboot* supports two different framebuffer setups. The default
+enables the legacy VGA plane in textmode. Due to legacy hardware
+constraints, only the first found display is enabled in this mode.
+(cf. `src/drivers/intel/gma/text_fb/gma.adb`).
+
+The second option sets up a high-resolution framebuffer with the
+native resolution of the display if only one is detected, or the
+smallest of all resolutions (per dimension) if multiple displays
+are detected. This option is selected by
+`CONFIG_FRAMEBUFFER_KEEP_VESA_MODE`.
+(cf. `src/drivers/intel/gma/hires_fb/gma.adb`).
+
+In any case, a smaller framebuffer is up-scaled to each display's
+native resolution while keeping aspect ratio.
+
+GMA: Hook-up in Chipset Initialization
+--------------------------------------
+
+Both configurations described above implement a procedure
+`GMA.gfxinit()`:
+
+    procedure gfxinit (lightup_ok : out int);
+
+This procedure is exported as the C function `gma_gfxinit()` as
+follows:
+
+    void gma_gfxinit(int *lightup_ok);
+
+* `lightup_ok`: returns whether the initialization succeeded `1` or
+                failed `0`. Currently, only the case that no display
+                could be found counts as failure. A failure at a la-
+                ter stage (e.g. failure to train a DP) is not propa-
+                gated.
+
+GMA: Per Board Configuration
+----------------------------
+
+There are a few Kconfig symbols to consider. To indicate that a
+board can initialize graphics through *libgfxinit*:
+
+    select MAINBOARD_HAS_LIBGFXINIT
+
+Internal ports share some hardware blocks (e.g. backlight, panel
+power sequencer). Therefore, each board has to select either eDP
+or LVDS as the internal port, if any:
+
+    select GFX_GMA_INTERNAL_IS_EDP	# the default, or
+    select GFX_GMA_INTERNAL_IS_LVDS
+
+Boards with a DVI-I connector share the DDC (I2C) pins for both
+analog and digital displays. In this case, *libgfxinit* needs to
+know through which interface the EDID can be queried:
+
+    select GFX_GMA_ANALOG_I2C_HDMI_B	# or
+    select GFX_GMA_ANALOG_I2C_HDMI_C	# or
+    select GFX_GMA_ANALOG_I2C_HDMI_D
+
+Beside Kconfig options, *libgfxinit* needs to know which ports are
+implemented on a board and should be probed for displays. Each
+board has to implement the package `GMA.Mainboard` with a list:
+
+    ports : HW.GFX.GMA.Display_Probing.Port_List;
+
+or a function returning such a list:
+
+    function ports return HW.GFX.GMA.Display_Probing.Port_List;
+
+You can select from the following Ports:
+
+    type Port_Type is
+      (Disabled,	-- optionally terminates the list
+       Internal,	-- either eDP or LVDS as selected in Kconfig
+       DP1,
+       DP2,
+       DP3,
+       HDMI1,		-- also DVI-D, or HDMI over DP++
+       HDMI2,
+       HDMI3,
+       Analog);		-- legacy VGA port, or analog part of DVI-I
+
+Each `DPx` and `HDMIx` pair share pins. If they are exposed as DP
+ports, they are usually DP++ (aka. dual-mode DP) ports that can
+also output HDMI signals through passive adapters. In this case,
+both DPx and HDMIx should be listed.
+
+A good example is the mainboard Kontron/KTQM77, it features two
+DP++ ports (DP2/HDMI2, DP3/HDMI3), one DVI-I port (HDMI1/Analog),
+eDP and LVDS. Due to the constraints mentioned above, only one of
+eDP and LVDS can be enabled. It defines `ports` as follows:
+
+    ports : constant Port_List :=
+      (DP2,
+       DP3,
+       HDMI1,
+       HDMI2,
+       HDMI3,
+       Analog,
+       Internal,
+       others => Disabled);
+
+The `GMA.gfxinit()` procedure probes for display EDIDs in the
+given order until all available pipes are taken. That's 1 pipe
+in VGA textmode, 2 pipes in high-resolution mode until Sandy
+Bridge, 3 pipes from Ivy Bridge on.
diff --git a/Documentation/index.html b/Documentation/index.html
diff --git a/Documentation/index.md b/Documentation/index.md
@@ -0,0 +1,23 @@
+Welcome to coreboot's documentation!
+====================================
+
+This is the developer documentation for [coreboot](https://coreboot.org).
+It is built from Markdown files in the
+[Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
+directory in the source code.
+
+Contents:
+
+* [Lesson 2: Submitting a patch to coreboot.org](Lesson2.md)
+* [Gerrit Etiquette and Guidelines](gerrit_guidelines.md)
+* [coreboot's build system](build_system.md)
+* [Kconfig in coreboot](core/Kconfig.md)
+* [Use of git submodules in coreboot](submodules.md)
+* [Timestamps](timestamp.md)
+* [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
+* [ABI data consumption](abi-data-consumption.md)
+* [GPIO toggling in ACPI AML](acpi/gpio.md)
+* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
+* [Sandy Bridge Raminit](Intel/NativeRaminit/Sandybridge.md)
+* [Mainboard-specific documentation](mainboard/index.md)
+* [SuperIO-specific documentation](superio/index.md)
diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md
@@ -0,0 +1,80 @@
+# HP Compaq 8200 Elite SFF
+
+This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop
+from [HP].
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Extended HWM reporting
+- Advanced LED control
+- Advanced power configuration in S3
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MX25L6406E |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but it powers the
+whole southbridge complex. You need to supply enough current through the programming adapter.
+
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
+
+**Position of SOIC-8 flash IC near 2nd DIMM holder**
+![][compaq_8200_flash1]
+
+[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg
+
+**Closeup view of SOIC-8 flash IC**
+![][compaq_8200_flash2]
+
+[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------+
+| Northbridge      | Sandy Bridge                         |
++------------------+--------------------------------------+
+| Southbridge      | bd82x6x                              |
++------------------+--------------------------------------+
+| CPU              | model_206ax                          |
++------------------+--------------------------------------+
+| SuperIO          | :doc:`../../superio/nuvoton/npcd378` |
++------------------+--------------------------------------+
+| EC               |                                      |
++------------------+--------------------------------------+
+| Coprocessor      | Intel ME                             |
++------------------+--------------------------------------+
+```
+
+[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
+[HP]: https://www.hp.com/
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/hp/compaq_8200_sff_flash1.jpg b/Documentation/mainboard/hp/compaq_8200_sff_flash1.jpg
diff --git a/Documentation/mainboard/hp/compaq_8200_sff_flash2.jpg b/Documentation/mainboard/hp/compaq_8200_sff_flash2.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -0,0 +1,11 @@
+# Mainboard-specific documentation
+
+This section contains documentation about coreboot on specific mainboards.
+
+## SiFive
+
+- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
+
+## HP
+
+- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -0,0 +1,104 @@
+# SiFive HiFive Unleashed
+
+This page describes how to run coreboot on the [HiFive Unleashed] development
+board from [SiFive], the first RISC-V board on the market with enough resources
+to run a multiuser operating system.
+
+For general setup instructions, please refer to the [Getting Started Guide].
+
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Trampoline in the MBR block to support boot mode 1
+- SiFive UART driver
+- CBMEM support
+- FU540 clock configuration
+- FU540 RAM init
+- Placing the ramstage in DRAM
+- Starting the U54 cores
+- FU540 PIN configuration and GPIO access macros
+- FU540 OTP driver and serial number read-out
+- Support for booting Linux on RISC-V
+
+
+## Configuration
+
+Run `make menuconfig` and select _SiFive_/_HiFive Unleashed_ in the _Mainboard_
+menu.
+
+
+### Boot modes
+
+A total of 16 boot modes can be configured using the switches labeled `MSEL0`
+through `MSEL3`. The most important ones are as follows:
+
+- **MSEL=1**: Jump directly into the SPI flash, bypassing ROM1
+- **MSEL=11**: Load FSBL from SD-card
+- **MSEL=15**: Default boot mode; Load FSBL/coreboot from a GPT partition on
+  SPI flash
+
+
+## Flashing coreboot
+
+The HiFive Unleashed has an 32 MiB SPI flash (**ISSI IS25WP256D**), that can be
+programmed from within Linux running on the board, via USB/JTAG, or directly
+with an SPI programmer.
+
+### Internal programming
+
+The SPI flash can be accessed as `/dev/mtd0` from Linux.
+
+### USB/JTAG
+
+To program the flash via USB/JTAG, connect the USB port to a computer. If the
+board is powered on, two new serial ports, for example `/dev/ttyUSB0` and
+`/dev/ttyUSB1` will appear. The first is JTAG, and the second is connected to
+the SoC's UART.
+
+- Download and build the [RISC-V fork of OpenOCD].
+- Download the [OpenOCD script] for Freedom Unleashed.
+- Start OpenOCD with `openocd -f openocd.cfg`
+- Connect to OpenOCD's command interface (via telnet) and enter the line
+  marked with `> `:
+```
+> flash write_image erase unlock build/coreboot.rom 0x20000000
+auto erase enabled
+auto unlock enabled
+wrote 33554432 bytes from file build/coreboot.rom in 1524.943848s (21.488 KiB/s)
+```
+  Note that programming the whole flash with OpenOCD isn't fast. In this
+  example it took just over 25 minutes. This process can be sped up
+  considerably by building/flashing a smaller image; OpenOCD does not check if
+  the image and the flash have the same size.
+
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] may work, but has not
+been tested. Please study the [schematics] before going this route.
+
+
+## Error codes
+
+The zeroth-stage bootloader (ZSBL) in ROM1 can print error codes on the serial
+console in certain situations.
+
+```
+// Error codes are formatted as follows:
+// [63:60]    [59:56]  [55:0]
+// bootstage  trap     errorcode
+// If trap == 1, then errorcode is actually the mcause register with the
+// interrupt bit shifted to bit 55.
+```
+(--- from the [SiFive forum](https://forums.sifive.com/t/loading-fsbl-from-sd/1156/4))
+
+
+[HiFive Unleashed]: https://www.crowdsupply.com/sifive/hifive-unleashed
+[SiFive]: https://www.sifive.com/
+[Getting Started Guide]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-getting-started-guide/
+[RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd
+[OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a68e90381cc/bsp/env/freedom-u500-unleashed/openocd.cfg
+[flashrom]: https://flashrom.org/Flashrom
+[schematics]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-schematics/
diff --git a/Documentation/submodules.txt → Documentation/submodules.md b/Documentation/submodules.txt → Documentation/submodules.md
diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md
@@ -0,0 +1,7 @@
+# SuperIO-specific documentation
+
+This section contains documentation about coreboot on specific SuperIOs.
+
+## Nuvoton
+
+- [NPCD378](nuvoton/npcd378.md)
diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md
@@ -0,0 +1,125 @@
+# NPCD378
+
+This page describes the [Nuvoton] SuperIO chip that can be found on various [HP]
+mainboards.
+
+As no datasheet is available most of the functions have been reverse engineered and
+might be inacurate or wrong.
+
+## LDNs
+
+```eval_rst
++-------+---------------------------+
+| LDN # | Function                  |
++=======+===========================+
+| 0     | FDC                       |
++-------+---------------------------+
+| 1     | Parallel Port             |
++-------+---------------------------+
+| 2     | Com1                      |
++-------+---------------------------+
+| 3     | Com2 / IR                 |
++-------+---------------------------+
+| 4     | LED and PWR button CTRL   |
++-------+---------------------------+
+| 5     | PS/2 AUX                  |
++-------+---------------------------+
+| 6     | PS/2 KB                   |
++-------+---------------------------+
+| 7     | WDT1                      |
++-------+---------------------------+
+| 8     | HWM                       |
++-------+---------------------------+
+| 0xf   | GPIO                      |
++-------+---------------------------+
+| 0x15  | I2C ?                     |
++-------+---------------------------+
+| 0x1e  | SUSPEND CTL ?             |
++-------+---------------------------+
+| 0x1c  | GPIO ?                    |
++-------+---------------------------+
+```
+
+### LDN0
+
+Follows [Nuvoton]'s default FDC register set. See [NCT6102D] for more details.
+
+### LDN1
+
+Follows [Nuvoton]'s default LPT register set. See [NCT6102D] for more details.
+
+### LDN2
+
+Follows [Nuvoton]'s default COM1 register set. See [NCT6102D] for more details.
+
+### LDN3
+
+Follows [Nuvoton]'s default COM2 register set. See [NCT6102D] for more details.
+
+### LDN4
+
+On most SuperIOs the use of LDN4 is forbidden. That's not the case on NPCD378.
+
+It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle
+and power button behaviour on normal / during S3 resume.
+
+### LDN5
+
+A custom PS/2 AUX port.
+
+### LDN6
+
+Follows [Nuvoton]'s default KBC register set. See [NCT6102D] for more details.
+
+### LDN7
+
+Looks like a WDT.
+
+### LDN8
+
+Custom HWM space. It exposes 256 byte of IO config space.
+See [HWM](#HWM) for more details.
+
+## HWM
+
+### Register
+
+The registers are accessible via IO space and are located at LDN8's IOBASE.
+
+```eval_rst
++---------------+-----------------------+
+| IOBASE offset | Register              |
++---------------+-----------------------+
+| 0x4           | Host Write CTRL       |
++---------------+-----------------------+
+| 0x10 - 0xfe   | HWM Page #            |
++---------------+-----------------------+
+| 0xff          | Page index select     |
++---------------+-----------------------+
+```
+
+### Host Write CTRL
+Bit 0 must be cleared prior to writing any of the HWM register and it must be
+set after writing to HWM register to signal the SuperIO that data has changed.
+Reading register is possible at any time and doesn't need special locking.
+
+### HWM Page
+The SuperIO exposes 16 different pages. Nearly all registers are unknown.
+
+**Page 1**
+
+```eval_rst
++---------------+-----------------------+
+| IOBASE offset | Register              |
++---------------+-----------------------+
+| 0x98          | PSU fan PWM           |
++---------------+-----------------------+
+```
+
+### Page index
+The 4 LSB of the page index register selects which HWM page is active.
+A write takes effect immediately.
+
+[NCT6102D]: https://www.nuvoton.com/resource-files/NCT6102D_NCT6106D_Datasheet_V1_0.pdf
+[Nuvoton]: http://www.nuvoton.com/hq/
+[HP]: https://www.hp.com/
diff --git a/Documentation/thinkpad/codenames.csv b/Documentation/thinkpad/codenames.csv
@@ -0,0 +1,29 @@
+t60,magi-5|magi-7|austin-3
+t400,malibu-3
+t400s,shinai
+t410,nozomi-1
+t410s,shinai-2
+t420,nozomi-3
+t420s,shinai-3
+t430,nozomi-4
+t430s,lsn-4
+t500,coronado-5
+t510,kendo-1
+t520,kendo-3
+t530,kendo-4
+w500,coronado-5
+w510,kendo-1 workstation
+w520,kendo-3 workstation
+w530,kendo-4 workstation
+w700,n-note
+x1_carbon_gen1,genesis-1
+x60,ks note
+x61,ks note-3
+x200,mocha-1
+x201,mocha-3
+x220,dasher-1
+x230,dasher-2
+x230s,rogue-1
+x240,rogue-2
+x300,kodachi
+x301,kodachi-2
diff --git a/Documentation/timestamp.md b/Documentation/timestamp.md
@@ -1,33 +1,31 @@
-Table of Contents
-=================
+# Timestamps
+
+## Table of Contents
+
 Introduction
-	Transition from cache to cbmem
+- Transition from cache to cbmem
 
 Data structures used
-	cache_state
-	table
-	entries
+- cache_state
+- table
+- entries
 
 Function APIs
-	timestamp_init
-	timestamp_add
-	timestamp_add_now
-	timestamp_sync
+- timestamp_init
+- timestamp_add
+- timestamp_add_now
+- timestamp_sync
 
 Use / Test Cases
-	Case 1: Timestamp Region Exists
-	Case 2: No timestamp region, fresh boot, cbmem_initialize called after
-	timestamp_init
-	Case 3: No timestamp region, fresh boot, cbmem_initialize called before
-	timestamp_init
-	Case 4: No timestamp region, resume, cbmem_initialize called after
-	timestamp_init
-	Case 5: No timestamp region, resume, cbmem_initialize called before
-	timestamp_init
+- Case 1: Timestamp Region Exists
+- Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init
+- Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init
+- Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init
+- Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init
 
 
-Introduction
-============
+## Introduction
+
 The aim of the timestamp library is to make it easier for different boards
 to  save timestamps in cbmem / stash (until cbmem is brought up) by
 providing a simple API to initialize, add and sync timestamps. In order
@@ -51,8 +49,8 @@ Behind the scenes, the timestamp library takes care of:
 3. Add a new cbmem timestamp area based on whether a reset of the cbmem
    timestamp region is required or not.
 
-Transition from cache to cbmem
-------------------------------
+### Transition from cache to cbmem
+
 To move timestamps from the cache to cbmem (and initialize the cbmem area in
 the first place), we use the CBMEM_INIT_HOOK infrastructure of coreboot.
 
@@ -62,25 +60,30 @@ copies all timestamps to cbmem and disables the cache.
 After such a transition, timestamp_init() must not be run again.
 
 
-Data structures used
-====================
+## Data structures used
+
 The main structure that maintains information about the timestamp cache is:
-struct __attribute__((__packed__)) timestamp_cache {
+
+```
+struct __packed timestamp_cache {
         uint16_t cache_state;
         struct timestamp_table table;
         struct timestamp_entry entries[MAX_TIMESTAMP_CACHE];
 };
+```
 
-cache_state
------------
-The state of the cache is maintained by cache_state attribute which can
+### cache_state
+
+The state of the cache is maintained by `cache_state` attribute which can
 be any one of the following:
 
+```
 enum {
         TIMESTAMP_CACHE_UNINITIALIZED = 0,
         TIMESTAMP_CACHE_INITIALIZED,
         TIMESTAMP_CACHE_NOT_NEEDED,
 };
+```
 
 By default, if the cache is stored in local stash (bss area), then
 it will be reset to uninitialized state. However, if the cache is
@@ -89,112 +92,109 @@ attributes. Thus, if the timestamp region is being used by any board, it is
 initialized to default values by the library.
 
 Once the cache is initialized, its state is set to
-CACHE_INITIALIZED. Henceforth, the calls to cache i.e. timestamp_add
+`CACHE_INITIALIZED`. Henceforth, the calls to cache i.e. `timestamp_add`
 know that the state reflected is valid and timestamps can be directly
 saved in the cache.
 
-Once the cbmem area is up (i.e. call to timestamp_sync_cache_to_cbmem),
+Once the cbmem area is up (i.e. call to `timestamp_sync_cache_to_cbmem`),
 we do not need to store the timestamps in local stash / timestamp area
-anymore. Thus, the cache state is set to CACHE_NOT_NEEDED, which allows
-timestamp_add to store all timestamps directly into the cbmem area.
+anymore. Thus, the cache state is set to `CACHE_NOT_NEEDED`, which allows
+`timestamp_add` to store all timestamps directly into the cbmem area.
+
 
+### table
 
-table
------
 This field is represented by a structure which provides overall
 information about the entries in the timestamp area:
 
+```
 struct timestamp_table {
         uint64_t        base_time;
         uint32_t        max_entries;
         uint32_t        num_entries;
         struct timestamp_entry entries[0]; /* Variable number of entries */
-} __attribute__((packed));
+} __packed;
+```
 
 It indicates the base time for all timestamp entries, maximum number
 of entries that can be stored, total number of entries that currently
 exist and an entry structure to hold variable number of entries.
 
 
-entries
--------
+### entries
+
 This field holds the details of each timestamp entry, upto a maximum
-of MAX_TIMESTAMP_CACHE which is defined as 16 entries. Each entry is
+of `MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is
 defined by:
 
+```
 struct timestamp_entry {
         uint32_t        entry_id;
         uint64_t        entry_stamp;
-} __attribute__((packed));
+} __packed;
+```
 
-entry_id holds the timestamp id corresponding to this entry and
-entry_stamp holds the actual timestamp.
+`entry_id` holds the timestamp id corresponding to this entry and
+`entry_stamp` holds the actual timestamp.
 
 
-For timestamps stored in the cbmem area, a timestamp_table is allocated
-with space for MAX_TIMESTAMPS equal to 30. Thus, the cbmem area holds
-base_time, max_entries (which is 30), current number of entries and the
-actual entries represented by timestamp_entry.
+For timestamps stored in the cbmem area, a `timestamp_table` is allocated
+with space for `MAX_TIMESTAMPS` equal to 30. Thus, the cbmem area holds
+`base_time`, `max_entries` (which is 30), current number of entries and the
+actual entries represented by `timestamp_entry`.
 
 
-Function APIs
-=============
+## Function APIs
+
+### timestamp_init
 
-timestamp_init
---------------
 This function initializes the timestamp cache and should be run as early
 as possible. On platforms with SRAM, this might mean in bootblock, on
 x86 with its CAR backed memory in romstage, this means romstage before
 memory init.
 
-timestamp_add
--------------
+### timestamp_add
+
 This function accepts from user a timestamp id and time to record in the
 timestamp table. It stores the entry in the appropriate table in cbmem
-or _timestamp region or local stash.
+or `_timestamp` region or local stash.
 
 
-timestamp_add_now
------------------
-This function calls timestamp_add with user-provided id and current time.
+### timestamp_add_now
 
+This function calls `timestamp_add` with user-provided id and current time.
 
-Use / Test Cases
-================
+
+## Use / Test Cases
 
 The following cases have been considered while designing the timestamp
 library. It is important to ensure that any changes made to this library satisfy
 each of the following use cases:
 
-Case 1: Timestamp Region Exists (Fresh Boot / Resume)
------------------------------------------------------
+### Case 1: Timestamp Region Exists (Fresh Boot / Resume)
 
-In this case, the library needs to call timestamp_init as early as possible to
+In this case, the library needs to call `timestamp_init` as early as possible to
 enable the timestamp cache. Once cbmem is available, the values will be
 transferred automatically.
 
 All regions are automatically reset on initialization.
 
-Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init
--------------------------------------------------------------------------------------
+### Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init
 
-timestamp_init will set up a local cache. cbmem must be initialized before that
+`timestamp_init` will set up a local cache. cbmem must be initialized before that
 cache vanishes - as happens when jumping to the next stage.
 
-Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init
---------------------------------------------------------------------------------------
+### Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init
 
-This case is not supported right now, just don't call timestamp_init after
-cbmem_initialize. (Patches to make this more robust are welcome.)
+This case is not supported right now, just don't call `timestamp_init` after
+`cbmem_initialize`. (Patches to make this more robust are welcome.)
 
-Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init
----------------------------------------------------------------------------------
+### Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init
 
 We always reset the cbmem region before using it, so pre-suspend timestamps
 will be gone.
 
-Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init
-----------------------------------------------------------------------------------
+### Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init
 
 We always reset the cbmem region before using it, so pre-suspend timestamps
 will be gone.
diff --git a/MAINTAINERS b/MAINTAINERS
@@ -35,7 +35,7 @@ trivial patch so apply some common sense.
 
 	PLEASE check your patch with the automated style checker
 	(util/lint/checkpatch.pl) to catch trival style violations.
-	See http://coreboot.org/Coding_Style for guidance here.
+	See https://www.coreboot.org/Coding_Style for guidance here.
 
 	PLEASE add the maintainers that are generated by
 	util/scripts/get_maintainer.pl as reviewers.  The results returned
@@ -54,7 +54,7 @@ trivial patch so apply some common sense.
 	of the OSDL certificate of contribution and should include a
 	Signed-off-by: line.  The current version of this "Developer's
 	Certificate of Origin" (DCO) is listed at
-	http://coreboot.org/Development_Guidelines#Sign-off_Procedure.
+	https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure.
 
 6.	Make sure you have the right to send any changes you make. If you
 	do changes at work you may find your employer owns the patch
@@ -150,22 +150,22 @@ F:	src/mainboard/lenovo/
 
 INTEL PINEVIEW CHIPSET
 M:	Damien Zammit <damien@zamaudio.com>
-S:	Maintained
+S:	Odd Fixes
 F:	src/northbridge/intel/pineview/
 
 INTEL D510MO MAINBOARD
 M:	Damien Zammit <damien@zamaudio.com>
-S:	Maintained
+S:	Odd Fixes
 F:	src/mainboard/intel/d510mo
 
 INTEL X4X CHIPSET
 M:	Damien Zammit <damien@zamaudio.com>
-S:	Maintained
+S:	Odd Fixes
 F:	src/northbridge/intel/x4x/
 
 GIGABYTE GA-G41M-ES2L MAINBOARD
 M:	Damien Zammit <damien@zamaudio.com>
-S:	Maintained
+S:	Odd Fixes
 F:	src/mainboard/gigabyte/ga-g41m-es2l
 
 GOOGLE PANTHER MAINBOARD
@@ -176,14 +176,12 @@ F:	src/mainboard/google/panther/
 INTEL MINNOWBOARD MAX MAINBOARD
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
-M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	src/mainboard/intel/minnowmax/
 
 INTEL FSP BAYTRAIL CHIP & CRBs
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
-M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	src/soc/intel/fsp_baytrail/
 F:	src/vendorcode/intel/fsp1_0/baytrail/
@@ -209,6 +207,17 @@ F:	src/vendorcode/intel/fsp1_0/ivybridge_i89xx
 F:	src/mainboard/intel/cougar_canyon2/
 F:	src/mainboard/intel/stargo2/
 
+INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
+M:	SweeHeng Wong <swee.heng.wong@intel.com>
+M:	Jeff Daly <jeffrey.daly@intel.com>
+M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
+M:	David Guckian <david.guckian@intel.com>
+M:	Shine Liu <shine.liu@intel.com>
+S:	Supported
+F:	src/mainboard/intel/harcuvar/
+F:	src/soc/intel/denverton_ns/
+F:	src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
+
 FSP 1.0 RANGELEY & CRB
 M:	David Guckian <david.guckian@intel.com>
 M:	Fei Wang <fei.z.wang@intel.com>
@@ -219,29 +228,22 @@ F:	src/southbridge/intel/fsp_rangeley/
 F:	src/vendorcode/intel/fsp1_0/rangeley/
 F:	src/mainboard/intel/mohonpeak/
 
-INTEL LITTLE PLAINS MAINBOARD
-M:	Marcin Wojciechowski <marcin.wojciechowski@intel.com>
-S:	Supported
-F:	src/mainboard/intel/littleplains/
-
 INTEL FSP 1.0
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
-M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	src/drivers/intel/fsp1_0/
 
 INTEL FSP 1.1
 M:	Lee Leahy <leroy.p.leahy@intel.com>
-M:	Andrey Petrov <andrey.petrov@intel.com>
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
 S:	Supported
 F:	src/drivers/intel/fsp1_1/
 
 INTEL FSP 2.0
-M:	Andrey Petrov <andrey.petrov@intel.com>
-S:	Supported
+M:	Andrey Petrov <andrey.petrov@gmail.com>
+S:	Maintained
 F:	src/drivers/intel/fsp2_0/
 
 INTEL STRAGO MAINBOARD
@@ -256,8 +258,8 @@ F:	/src/soc/intel/braswell
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell
 
 INTEL APOLLOLAKE_SOC
-M:	Andrey Petrov <andrey.petrov@intel.com>
-S:	Supported
+M:	Andrey Petrov <andrey.petrov@gmail.com>
+S:	Maintained
 F:	src/soc/intel/apollolake/
 
 ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
@@ -278,7 +280,7 @@ F:	src/mainboard/asus/kgpe-d16/
 
 PC ENGINES ALL MAINBOARDS
 M:	Piotr Król <piotr.krol@3mdeb.com>
-M:	Kamil Wcisło <kamil.wcislo@3mdeb.com>
+M:	Michał Żygowski <michal.zygowski@3mdeb.com>
 S:	Supported
 F:	src/mainboard/pcengines/
 
@@ -321,25 +323,37 @@ F:	src/acpi/
 F:	src/arch/x86/acpi/
 F:	util/acpi/
 
+LZ4 COMPRESSION
+M:	Julius Werner <jwerner@chromium.org>
+S:	Supported
+F:	src/commonlib/lz4*
+F:	payloads/libpayload/liblz4/
+F:	util/cbfstool/lz4/
+
 ARM ARCHITECTURE
+M:	Julius Werner <jwerner@chromium.org>
+S:	Supported
 F:	src/arch/arm/
-F:	src/arch/arm64
+F:	src/arch/arm64/
+F:	src/soc/mediatek/
+F:	src/soc/nvidia/
+F:	src/soc/rockchip/
+F:	util/nvidia/
+F:	util/rockchip/
+
+ORPHANED ARM SOCS
+S:	Orphaned
 F:	src/cpu/allwinner/
 F:	src/cpu/armltd/
-F:	src/cpu/samsung/
 F:	src/cpu/ti/
 F:	src/soc/broadcom/
 F:	src/soc/marvell/
-F:	src/soc/nvidia/
 F:	src/soc/qualcomm/
-F:	src/soc/rockchip/
 F:	src/soc/samsung/
 F:	util/arm_boot_tools/
 F:	util/broadcom/
 F:	util/exynos/
 F:	util/ipqheader/
-F:	util/nvidia/
-F:	util/rockchip/
 
 MIPS ARCHITECTURE
 F:	src/arch/mips/
@@ -415,8 +429,6 @@ F:	util/xcompile/
 F:	util/genbuild_h/
 
 BOARD STATUS
-M:	Martin Roth <gaumless@gmail.com>
-S:	Supported
 F:	util/board_status/
 
 BINARY OBJECTS
@@ -487,30 +499,34 @@ S:	Supported
 F:	util/docker/
 
 TOOLCHAIN
-M:	Martin Roth <gaumless@gmail.com>
-S:	Supported
 F:	util/crossgcc/
 
 GIT
-M:	Martin Roth <gaumless@gmail.com>
-S:	Supported
 F:	.git*
 F:	/util/gitconfig
 
+SUPERIOS & SUPERIOTOOL
+M:	Felix Held <felix-coreboot@felixheld.de>
+S:	Maintained
+F:	src/superio/
+F:	util/superiotool/
+
+MEMLAYOUT
+M:	Julius Werner <jwerner@chromium.org>
+S:	Supported
+F:	*/memlayout.h
+F:	*.ld
+
 MISSING: TIMERS / DELAYS
 
 MISSING: TIMESTAMPS
 
-MISSING: MEMLAYOUT
-
 MISSING: FMAP
 
 MISSING: GPIO
 
 MISSING: SMP
 
-MISSING: SUPERIOS
-
 MISSING: DMP / QEMU-X86
 
 MISSING: ELOG
@@ -519,7 +535,49 @@ MISSING: SPI
 
 THE REST
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
-T:	git http://review.coreboot.org/coreboot
+T:	git https://review.coreboot.org/coreboot
 S:	Buried alive in mainboards
 F:	*
 F:	*/
+
+# *** Infrastructure Owners***
+# This is intended to let people know who they should contact for issues with various infrastructure pieces.
+# Hardware
+#	Owners: Stefan, Patrick
+#	Backups:
+
+# Web Server
+#	Owners: Stefan, Patrick
+#	Backups:
+
+# Website
+#	Owners: Martin, Philipp
+#	Backups: Patrick, Stefan
+
+# Documentation Website
+#	Owners: Patrick, Philipp
+#	Backups:
+
+# Wiki
+#	Owners: Stefan, Patrick
+#	Backups:
+
+# Gerrit
+#	Owners: Stefan, Patrick
+#	Backups: Martin
+
+# Jenkins
+#	Owners: Patrick, Martin
+#	Backups:
+
+# Bug Tracker
+#	Owners: Lynxis,
+#	Backups: Martin,
+
+# Mailing List
+#	Owners: Stefan, Patrick
+#	Backups: Martin,
+
+# Software Freedom Conservancy
+#	Main contact: Martin
+#	“Official” contact: Stefan
diff --git a/Makefile b/Makefile
@@ -30,34 +30,38 @@
 ## SUCH DAMAGE.
 ##
 
-export top := $(CURDIR)
-export src := src
-export srck := $(top)/util/kconfig
+top := $(CURDIR)
+src := src
+srck := $(top)/util/kconfig
 obj ?= build
 override obj := $(subst $(top)/,,$(abspath $(obj)))
-export obj
-export objutil ?= $(obj)/util
-export objk := $(objutil)/kconfig
+objutil ?= $(obj)/util
+objk := $(objutil)/kconfig
 absobj := $(abspath $(obj))
 
+COREBOOT_EXPORTS := COREBOOT_EXPORTS
+COREBOOT_EXPORTS += top src srck obj objutil objk
 
-export KCONFIG_AUTOHEADER := $(obj)/config.h
-export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
-export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
-export KCONFIG_SPLITCONFIG := $(obj)/config
-export KCONFIG_TRISTATE := $(obj)/tristate.conf
-export KCONFIG_NEGATIVES := 1
-export KCONFIG_STRICT := 1
+DOTCONFIG ?= $(top)/.config
+KCONFIG_CONFIG = $(DOTCONFIG)
+KCONFIG_AUTOHEADER := $(obj)/config.h
+KCONFIG_AUTOCONFIG := $(obj)/auto.conf
+KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
+KCONFIG_SPLITCONFIG := $(obj)/config
+KCONFIG_TRISTATE := $(obj)/tristate.conf
+KCONFIG_NEGATIVES := 1
+KCONFIG_STRICT := 1
+
+COREBOOT_EXPORTS += KCONFIG_CONFIG KCONFIG_AUTOHEADER KCONFIG_AUTOCONFIG
+COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
+COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
 
 # directory containing the toplevel Makefile.inc
 TOPLEVEL := .
 
 CONFIG_SHELL := sh
 KBUILD_DEFCONFIG := configs/defconfig
 UNAME_RELEASE := $(shell uname -r)
-DOTCONFIG ?= $(top)/.config
-KCONFIG_CONFIG = $(DOTCONFIG)
-export KCONFIG_CONFIG
 HAVE_DOTCONFIG := $(wildcard $(DOTCONFIG))
 MAKEFLAGS += -rR --no-print-directory
 
@@ -82,6 +86,8 @@ PREPROCESS_ONLY := -E -P -x assembler-with-cpp -undef -I .
 DOXYGEN := doxygen
 DOXYGEN_OUTPUT_DIR := doxygen
 
+export $(COREBOOT_EXPORTS)
+
 all: real-all
 
 help_coreboot help::
@@ -92,9 +98,8 @@ help_coreboot help::
 	@echo  '  distclean             - Remove build artifacts and config files'
 	@echo  '  doxygen               - Build doxygen documentation for coreboot'
 	@echo  '  doxyplatform          - Build doxygen documentation for the current platform'
-	@echo  '  what-jenkins-does     - Run platform build tests (Use CPUS=# for more cores)'
+	@echo  '  filelist              - Show files used in current build'
 	@echo  '  printall              - print makefile info for debugging'
-	@echo  '  lint / lint-stable    - run coreboot lint tools (all / minimal)'
 	@echo  '  gitconfig             - set up git to submit patches to coreboot'
 	@echo  '  ctags / ctags-project - make ctags file for all of coreboot or current board'
 	@echo  '  cscope / cscope-project - make cscope.out file for coreboot or current board'
@@ -124,6 +129,8 @@ endif
 ifeq ($(NOCOMPILE),1)
 include $(TOPLEVEL)/Makefile.inc
 include $(TOPLEVEL)/payloads/Makefile.inc
+include $(TOPLEVEL)/util/testing/Makefile.inc
+-include $(TOPLEVEL)/site-local/Makefile.inc
 real-all:
 	@echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2
 	@echo "Please specify a config file or run 'make menuconfig' to" >&2
@@ -230,7 +237,7 @@ includemakefiles= \
 			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
 	$(foreach special,$(special-classes), \
 		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
-	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
+	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
 
 # For each path in $(subdirs) call includemakefiles
 # Repeat until subdirs is empty
@@ -302,13 +309,19 @@ define create_cc_template
 # $4 additional dependencies
 ifn$(EMPTY)def $(1)-objs_$(2)_template
 de$(EMPTY)fine $(1)-objs_$(2)_template
+ifn$(EMPTY)eq ($(filter ads adb,$(2)),)
 $$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $$(call create_ada_deps,$1,$$(call src-to-ali,$1,$$(1).$2)) $(KCONFIG_AUTOHEADER) $(4)
+	@printf "    GCC        $$$$(subst $$$$(obj)/,,$$$$(@))\n"
+	$(GCC_$(1)) \
+		$$$$(ADAFLAGS_$(1)) $$$$(addprefix -I,$$$$($(1)-ada-dirs)) \
+		$(3) -c -o $$$$@ $$$$<
+el$(EMPTY)se
+$$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4)
 	@printf "    CC         $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$(CC_$(1)) \
-		$$(if $$(filter-out ads adb,$(2)), \
-		   -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@), \
-		   $$$$(ADAFLAGS_$(1)) $$$$(addprefix -I,$$$$($(1)-ada-dirs))) \
+		-MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \
 		$(3) -c -o $$$$@ $$$$<
+end$(EMPTY)if
 en$(EMPTY)def
 end$(EMPTY)if
 endef
@@ -339,8 +352,8 @@ $$(obj)/$(1)/b__$(1).adb: $$$$(filter-out $$(obj)/$(1)/b__$(1).ali,$$$$($(1)-ali
 			-L$(1)_ada -o $$(notdir $$@) \
 			$$(subst $$(dir $$@),,$$^)
 $$(obj)/$(1)/b__$(1).o: $$(obj)/$(1)/b__$(1).adb
-	@printf "    CC         $$(subst $$(obj)/,,$$@)\n"
-	$(CC_$(1)) $$(ADAFLAGS_$(1)) -c -o $$@ $$<
+	@printf "    GCC        $$(subst $$(obj)/,,$$@)\n"
+	$(GCC_$(1)) $$(ADAFLAGS_$(1)) -c -o $$@ $$<
 $(1)-objs += $$(obj)/$(1)/b__$(1).o
 $($(1)-alis): %.ali: %.o ;
 endef
@@ -363,11 +376,19 @@ ifndef NOMKDIR
 $(shell mkdir -p $(KCONFIG_SPLITCONFIG) $(objk)/lxdialog $(additional-dirs) $(alldirs))
 endif
 
-$(obj)/project_filelist.txt: all
-	find $(obj) -name "*.d" -exec cat {} \; | \
-	  sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \
+$(obj)/project_filelist.txt:
+	if [ -z "$(wildcard $(obj)/coreboot.rom)" ]; then \
+		echo "*** Error: Project must be built before generating file list ***"; \
+		exit 1; \
+	fi
+	find $(obj) -path "$(obj)/util" -prune -o -name "*.d" -exec cat {} \; | \
+	  sed "s|$(top)/||" | sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \
 	  grep -v '\.o$$' > $(obj)/project_filelist.txt
 
+filelist: $(obj)/project_filelist.txt
+	printf "\nFiles used in build:\n"
+	cat $(obj)/project_filelist.txt
+
 #works with either exuberant ctags or ctags.emacs
 ctags-project: clean-ctags $(obj)/project_filelist.txt
 	cat $(obj)/project_filelist.txt | \
@@ -402,7 +423,7 @@ doxygen-clean:
 clean-for-update: doxygen-clean clean-for-update-target
 	rm -rf $(obj) .xcompile
 
-clean: clean-for-update clean-target
+clean: clean-for-update clean-target clean-utils
 	rm -f .ccwrap
 
 clean-cscope:
@@ -411,8 +432,19 @@ clean-cscope:
 clean-ctags:
 	rm -f tags
 
-distclean: clean clean-ctags clean-cscope distclean-payloads
+clean-utils:
+	$(foreach tool, $(TOOLLIST), \
+		$(MAKE) -C util/$(tool) clean MFLAGS= MAKEFLAGS= ;)
+
+distclean-utils:
+	$(foreach tool, $(TOOLLIST), \
+		$(MAKE) -C util/$(tool) distclean MFLAGS= MAKEFLAGS= ; \
+		rm -f /util/$(tool)/junit.xml;)
+
+distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
 	rm -f .config .config.old ..config.tmp* .kconfig.d .tmpconfig* .ccwrap .xcompile
+	rm -rf coreboot-builds coreboot-builds-chromeos
+	rm -f abuild*.xml junit.xml* util/lint/junit.xml
 
 .PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy doxygen_simple
 .PHONY: ctags-project cscope-project clean-ctags
diff --git a/Makefile.inc b/Makefile.inc
diff --git a/README b/README
@@ -24,7 +24,7 @@ Payloads
 After the basic initialization of the hardware has been performed, any
 desired "payload" can be started by coreboot.
 
-See http://www.coreboot.org/Payloads for a list of supported payloads.
+See https://www.coreboot.org/Payloads for a list of supported payloads.
 
 
 Supported Hardware
@@ -34,8 +34,8 @@ coreboot supports a wide range of chipsets, devices, and mainboards.
 
 For details please consult:
 
- * http://www.coreboot.org/Supported_Motherboards
- * http://www.coreboot.org/Supported_Chipsets_and_Devices
+ * https://www.coreboot.org/Supported_Motherboards
+ * https://www.coreboot.org/Supported_Chipsets_and_Devices
 
 
 Build Requirements
@@ -51,6 +51,8 @@ Build Requirements
    ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
    case).
  * iasl (for targets with ACPI support)
+ * pkg-config
+ * libssl-dev (openssl)
 
 Optional:
 
@@ -63,7 +65,7 @@ Optional:
 Building coreboot
 -----------------
 
-Please consult http://www.coreboot.org/Build_HOWTO for details.
+Please consult https://www.coreboot.org/Build_HOWTO for details.
 
 
 Testing coreboot Without Modifying Your Hardware
@@ -73,7 +75,7 @@ If you want to test coreboot without any risks before you really decide
 to use it on your hardware, you can use the QEMU system emulator to run
 coreboot virtually in QEMU.
 
-Please see http://www.coreboot.org/QEMU for details.
+Please see https://www.coreboot.org/QEMU for details.
 
 
 Website and Mailing List
@@ -82,11 +84,11 @@ Website and Mailing List
 Further details on the project, a FAQ, many HOWTOs, news, development
 guidelines and more can be found on the coreboot website:
 
-  http://www.coreboot.org
+  https://www.coreboot.org
 
 You can contact us directly on the coreboot mailing list:
 
-  http://www.coreboot.org/Mailinglist
+  https://www.coreboot.org/Mailinglist
 
 
 Copyright and License

diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial
@@ -2,5 +2,5 @@ CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_POST_IO is not set
 # CONFIG_POST_DEVICE is not set
 CONFIG_CONSOLE_POST=y
-CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+CONFIG_LINEAR_FRAMEBUFFER=y
 # CONFIG_CONSOLE_SERIAL is not set
diff --git a/configs/config.intel_galileo_gen1 b/configs/config.intel_galileo_gen1
@@ -0,0 +1,10 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_GALILEO_GEN2 is not set
+# CONFIG_FSP_DEBUG_ALL is not set
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_460800=y
diff --git a/configs/config.intel_galileo_gen2 b/configs/config.intel_galileo_gen2
@@ -0,0 +1,9 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y
diff --git a/configs/config.intel_galileo_gen2.debug b/configs/config.intel_galileo_gen2.debug
@@ -0,0 +1,14 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_DISPLAY_MTRRS=y
+CONFIG_DISPLAY_SMM_MEMORY_MAP=y
+CONFIG_DISPLAY_ESRAM_LAYOUT=y
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+CONFIG_VERIFY_HOBS=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_CONSOLE_SERIAL_921600=y
diff --git a/configs/config.intel_galileo_gen2.fsp1.1 b/configs/config.intel_galileo_gen2.fsp1.1
@@ -0,0 +1,9 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+CONFIG_FSP_VERSION_1_1=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y
diff --git a/configs/config.intel_galileo_gen2.fsp2.0 b/configs/config.intel_galileo_gen2.fsp2.0
@@ -0,0 +1,8 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y
diff --git a/configs/config.intel_galileo_gen2.sd b/configs/config.intel_galileo_gen2.sd
@@ -0,0 +1,18 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_COMMONLIB_STORAGE_MMC=y
+CONFIG_STORAGE_ERASE=y
+CONFIG_STORAGE_EARLY_ERASE=y
+CONFIG_STORAGE_WRITE=y
+CONFIG_STORAGE_EARLY_WRITE=y
+CONFIG_SD_MMC_DEBUG=y
+CONFIG_SD_MMC_TRACE=y
+CONFIG_SDHC_TRACE=y
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_CONSOLE_SERIAL_921600=y
diff --git a/configs/config.intel_galileo_gen2.vboot b/configs/config.intel_galileo_gen2.vboot
@@ -0,0 +1,9 @@
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_VBOOT_WITH_CRYPTO_SHIELD=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y
diff --git a/configs/config.intel_harcuvar b/configs/config.intel_harcuvar
@@ -0,0 +1,18 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_CBFS_SIZE=0x800000
+CONFIG_BOARD_INTEL_HARCUVAR=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+CONFIG_ENABLE_HSUART=y
+CONFIG_UART_PCI_ADDR=0x8000d000
+
+#Sample settings for Denverton-NS FSP.
+#CONFIG_ADD_FSP_BINARIES=y
+#CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
+#CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
+#CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
+#CONFIG_FSP_CAR=y
+
+#Sample settings for microcode definitions.
+#CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
+#CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -0,0 +1,16 @@
+CONFIG_VENDOR_PCENGINES=y
+CONFIG_BOARD_PCENGINES_APU1=y
+CONFIG_NO_GFX_INIT=y
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
+CONFIG_PXE=y
+CONFIG_BUILD_IPXE=y
+CONFIG_PXE_ROM_ID="10ec,8168"
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
+CONFIG_MEMTEST_MASTER=y
+CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -0,0 +1,18 @@
+CONFIG_VENDOR_PCENGINES=y
+CONFIG_BOARD_PCENGINES_APU2=y
+CONFIG_APU2_PINMUX_UART_C=y
+CONFIG_APU2_PINMUX_UART_D=y
+CONFIG_NO_GFX_INIT=y
+CONFIG_PXE=y
+CONFIG_BUILD_IPXE=y
+CONFIG_PXE_ROM_ID="8086,157b"
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
+CONFIG_MEMTEST_MASTER=y
+CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -0,0 +1,16 @@
+CONFIG_VENDOR_PCENGINES=y
+CONFIG_BOARD_PCENGINES_APU3=y
+CONFIG_NO_GFX_INIT=y
+CONFIG_PXE=y
+CONFIG_BUILD_IPXE=y
+CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
+CONFIG_MEMTEST_MASTER=y
+CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -0,0 +1,16 @@
+CONFIG_VENDOR_PCENGINES=y
+CONFIG_BOARD_PCENGINES_APU4=y
+CONFIG_NO_GFX_INIT=y
+CONFIG_PXE=y
+CONFIG_BUILD_IPXE=y
+CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
+CONFIG_MEMTEST_MASTER=y
+CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -0,0 +1,16 @@
+CONFIG_VENDOR_PCENGINES=y
+CONFIG_BOARD_PCENGINES_APU5=y
+CONFIG_NO_GFX_INIT=y
+CONFIG_PXE=y
+CONFIG_BUILD_IPXE=y
+CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
+CONFIG_MEMTEST_MASTER=y
+CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
diff --git a/configs/pcengines_apu1.config b/configs/pcengines_apu1.config
diff --git a/configs/pcengines_apu2.config b/configs/pcengines_apu2.config
diff --git a/configs/pcengines_apu3.config b/configs/pcengines_apu3.config
diff --git a/configs/pcengines_apu4.config b/configs/pcengines_apu4.config
diff --git a/configs/pcengines_apu5.config b/configs/pcengines_apu5.config
diff --git a/payloads/Kconfig b/payloads/Kconfig
@@ -1,8 +1,11 @@
 menu "Payload"
 
+config NO_DEFAULT_PAYLOAD
+	bool
+
 choice
 	prompt "Add a payload"
-	default PAYLOAD_NONE if !ARCH_X86
+	default PAYLOAD_NONE if NO_DEFAULT_PAYLOAD || !ARCH_X86
 	default PAYLOAD_SEABIOS if ARCH_X86
 
 config PAYLOAD_NONE
@@ -46,15 +49,27 @@ config PAYLOAD_FILE
 	help
 	  The path and filename of the ELF executable file to use as payload.
 
-# TODO: Defined if no payload? Breaks build?
+choice
+	prompt "Payload compression algorithm"
+	default COMPRESSED_PAYLOAD_LZMA
+	depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
+	help
+	  Choose the compression algorithm for the chosen payloads.
+	  You can choose between LZMA and LZ4.
+
 config COMPRESSED_PAYLOAD_LZMA
 	bool "Use LZMA compression for payloads"
-	default y
-	depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
 	help
 	  In order to reduce the size payloads take up in the ROM chip
 	  coreboot can compress them using the LZMA algorithm.
 
+config COMPRESSED_PAYLOAD_LZ4
+	bool "Use LZ4 compression for payloads"
+	help
+	  In order to reduce the size payloads take up in the ROM chip
+	  coreboot can compress them using the LZ4 algorithm.
+endchoice
+
 config PAYLOAD_OPTIONS
 	string
 	default ""
@@ -67,6 +82,13 @@ config PAYLOAD_IS_FLAT_BINARY
 	  Add the payload to cbfs as a flat binary type instead of as an
 	  elf payload
 
+config COMPRESS_SECONDARY_PAYLOAD
+	bool "Use LZMA compression for secondary payloads"
+	default y
+	help
+	  In order to reduce the size secondary payloads take up in the
+	  ROM chip they can be compressed using the LZMA algorithm.
+
 menu "Secondary Payloads"
 
 config COREINFO_SECONDARY_PAYLOAD
@@ -79,7 +101,7 @@ config COREINFO_SECONDARY_PAYLOAD
 
 config MEMTEST_SECONDARY_PAYLOAD
 	bool "Load Memtest86+ as a secondary payload"
-	default y
+	default n
 	depends on ARCH_X86
 	help
 	  Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
@@ -124,7 +146,7 @@ config TINT_SECONDARY_PAYLOAD
 
 config SORTBOOTORDER_SECONDARY_PAYLOAD
 	bool "Load sortbootorder as a secondary payload"
-	default y
+	default n
 	depends on ARCH_X86
 	help
 	  sortbootorder can be loaded as a secondary payload under SeaBIOS

diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
@@ -16,10 +16,12 @@
 cbfs-files-$(CONFIG_COREINFO_SECONDARY_PAYLOAD) += img/coreinfo
 img/coreinfo-file := payloads/coreinfo/build/coreinfo.elf
 img/coreinfo-type := payload
+img/coreinfo-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
 cbfs-files-$(CONFIG_NVRAMCUI_SECONDARY_PAYLOAD) += img/nvramcui
 img/nvramcui-file := payloads/nvramcui/nvramcui.elf
 img/nvramcui-type := payload
+img/nvramcui-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
 PAYLOADS_LIST=\
 payloads/coreinfo \
@@ -32,7 +34,9 @@ payloads/external/Memtest86Plus \
 payloads/external/iPXE \
 payloads/external/tint \
 payloads/external/sortbootorder \
-payloads/external/sgabios
+payloads/external/sgabios \
+payloads/external/tianocore \
+payloads/external/GRUB2 \
 
 payloads/coreinfo/build/coreinfo.elf coreinfo:
 	$(MAKE) -C payloads/coreinfo defaultbuild

diff --git a/payloads/bayou/lzma.c b/payloads/bayou/lzma.c
@@ -1,6 +1,6 @@
 /*
 
-Coreboot interface to memory-saving variant of LZMA decoder
+coreboot interface to memory-saving variant of LZMA decoder
 
 (C)opyright 2006 Carl-Daniel Hailfinger
 Released under the GNU GPL v2 or later

diff --git a/payloads/coreinfo/README b/payloads/coreinfo/README
@@ -11,8 +11,8 @@ a package called gcc-multilib if you are on a 64bit system.
 Build
 -----
 
-You need libpayload to build coreinfo. So, first, you need follow the README of 
-libpayload to build it but install libpayload into its own directory by doing 
+You need libpayload to build coreinfo. So, first, you need follow the README of
+libpayload to build it but install libpayload into its own directory by doing
 this:
 
  $ make DESTDIR=/path/to/libpayload/install install

diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c
@@ -33,7 +33,7 @@ struct cbmem_console {
 	u32 size;
 	u32 cursor;
 	u8 body[0];
-} __attribute__ ((__packed__));
+} __packed;
 
 #define CURSOR_MASK ((1 << 28) - 1)
 #define OVERFLOW (1 << 31)
@@ -170,7 +170,7 @@ static int bootlog_module_init(void)
 
 static int bootlog_module_redraw(WINDOW *win)
 {
-	print_module_title(win, "Coreboot Bootlog");
+	print_module_title(win, "coreboot Bootlog");
 
 	if (!g_buf) {
 		return -1;

diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c
@@ -28,7 +28,7 @@
 #define COMPONENT_BOOTBLOCK	0x01
 #define COMPONENT_CBFSHEADER	0x02
 #define COMPONENT_STAGE		0x10
-#define COMPONENT_PAYLOAD	0x20
+#define COMPONENT_SELF		0x20
 #define COMPONENT_OPTIONROM	0x30
 #define COMPONENT_RAW		0x50
 #define COMPONENT_MICROCODE	0x53
@@ -44,7 +44,7 @@ struct cbheader {
 	u32 offset;
 	u32 architecture;
 	u32 pad[1];
-} __attribute__ ((packed));
+} __packed;
 
 struct cbfile {
 	u64 magic;
@@ -53,7 +53,7 @@ struct cbfile {
 	u32 checksum;
 	u32 offset;
 	char filename[0];
-} __attribute__ ((packed));
+} __packed;
 
 static int filecount = 0, selected = 0, start_row = 0;
 static char **filenames;
@@ -187,8 +187,8 @@ static int cbfs_module_redraw(WINDOW * win)
 	case COMPONENT_STAGE:
 		mvwprintw(win, row++, 38, "stage");
 		break;
-	case COMPONENT_PAYLOAD:
-		mvwprintw(win, row++, 38, "payload");
+	case COMPONENT_SELF:
+		mvwprintw(win, row++, 38, "simple ELF");
 		break;
 	case COMPONENT_OPTIONROM:
 		mvwprintw(win, row++, 38, "optionrom");

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
@@ -42,10 +42,10 @@ int coreboot_module_redraw(WINDOW *win)
 	int row = 2;
 	int i;
 
-	print_module_title(win, "Coreboot Tables");
+	print_module_title(win, "coreboot Tables");
 
 	if (tables_good) {
-		mvwprintw(win, row++, 1, "No Coreboot tables were found");
+		mvwprintw(win, row++, 1, "No coreboot tables were found");
 		return 0;
 	}
 
@@ -249,7 +249,7 @@ static int coreboot_module_init(void)
 }
 
 struct coreinfo_module coreboot_module = {
-	.name = "Coreboot",
+	.name = "coreboot",
 	.init = coreboot_module_init,
 	.redraw = coreboot_module_redraw,
 };

diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c
@@ -291,9 +291,8 @@ int main(void)
 {
 	int i, j;
 
-#if IS_ENABLED(CONFIG_LP_USB)
-	usb_initialize();
-#endif
+	if (IS_ENABLED(CONFIG_LP_USB))
+		usb_initialize();
 
 	initscr();
 

diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c
@@ -210,8 +210,10 @@ static int timestamps_module_init(void)
 	g_max_cursor_line = MAX(g_lines_count - 1 - LINES_SHOWN, 0);
 
 	g_buf = malloc(chars_count);
-	if (!g_buf)
+	if (!g_buf) {
+		free(buffer);
 		return -3;
+	}
 
 	if (sanitize_buffer_for_display(buffer, buff_cur + 1, g_buf,
 				chars_count, SCREEN_X) < 0) {
@@ -228,7 +230,7 @@ static int timestamps_module_init(void)
 
 static int timestamps_module_redraw(WINDOW *win)
 {
-	print_module_title(win, "Coreboot Timestamps");
+	print_module_title(win, "coreboot Timestamps");
 
 	if (!g_buf)
 		return -1;

diff --git a/payloads/external/FILO/Kconfig.name b/payloads/external/FILO/Kconfig.name
@@ -5,4 +5,4 @@ config PAYLOAD_FILO
 	  with a FILO payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See http://coreboot.org/Payloads for more information.
+	  See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile
@@ -3,7 +3,7 @@ NAME-$(CONFIG_FILO_MASTER)=MASTER
 TAG-$(CONFIG_FILO_STABLE)=22baa6bde9339029edfafa421b3d4a7be159edad
 NAME-$(CONFIG_FILO_STABLE)=STABLE
 
-project_git_repo=https://review.coreboot.org/p/filo.git
+project_git_repo=https://review.coreboot.org/filo.git
 project_dir=filo
 
 unexport KCONFIG_AUTOHEADER

diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig
@@ -2,7 +2,12 @@ if PAYLOAD_GRUB2
 
 choice
 	prompt "GRUB2 version"
-	default GRUB2_MASTER
+	default GRUB2_STABLE
+
+config GRUB2_STABLE
+	bool "2.02"
+	help
+	  Stable GRUB2 version
 
 config GRUB2_MASTER
 	bool "HEAD"

diff --git a/payloads/external/GRUB2/Kconfig.name b/payloads/external/GRUB2/Kconfig.name
@@ -1,8 +1,9 @@
 config PAYLOAD_GRUB2
 	bool "GRUB2"
+	depends on ARCH_X86 || ARCH_ARM
 	help
 	  Select this option if you want to build a coreboot image
 	  with a GRUB2 payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See http://coreboot.org/Payloads for more information.
+	  See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile
@@ -1,26 +1,15 @@
 TAG-$(CONFIG_GRUB2_MASTER)=
 TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
+TAG-$(CONFIG_GRUB2_STABLE)=e54c99aaff5e5f6f5d3b06028506c57e66d8ef77
 NAME-$(CONFIG_GRUB2_MASTER)=HEAD
 NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
+NAME-$(CONFIG_GRUB2_STABLE)=2.02
 
-project_git_repo=git://git.sv.gnu.org/grub.git
+project_git_repo=https://git.savannah.gnu.org/git/grub.git/
 project_dir=grub2
 
-unexport KCONFIG_AUTOCONFIG
-unexport CFLAGS
-unexport CPPFLAGS
-unexport CCASFLAGS
-unexport CC
-unexport BUILD_CC
-unexport TARGET_CC
-unexport TARGET_CFLAGS
-unexport TARGET_CPPFLAGS
-unexport TARGET_STRIP
-unexport TARGET_OBJCOPY
-unexport HOST_CFLAGS
-unexport HOST_CPPFLAGS
-unexport HOST_CC
-
+unexport HOSTCC CC LD OBJCOPY STRIP
+MAKEOVERRIDES :=
 
 all: grub2
 
@@ -35,24 +24,26 @@ checkout:
 			git branch -f $(NAME-y) $(TAG-y) && \
 			git checkout $(NAME-y) || true
 
-config: checkout
+grub2/build/config.h: $(CONFIG_DEP) | checkout
 	echo "    CONFIG     GRUB2 $(NAME-y)"
 	rm -rf grub2/build
 	mkdir grub2/build
 	cd grub2 && ./autogen.sh
-	cd grub2/build && ../configure BUILD_CC="$(HOSTCC)" CC="$(HOSTCC)" \
-	TARGET_CC="$(CC)" \
-	TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" CFLAGS=-O2 TARGET_CFLAGS=-Os --with-platform=coreboot \
-	--enable-boot-time
+	cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \
+	TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \
+	CFLAGS=-O2 TARGET_CFLAGS=-Os \
+	--with-platform=coreboot --enable-boot-time --disable-werror
+
+config: grub2/build/config.h checkout
 
 grub2: config
 	echo "    MAKE       GRUB2 $(NAME-y)"
-	$(MAKE) -C grub2/build CC="$(HOSTCC)"
+	$(MAKE) -C grub2/build
 	$(MAKE) -C grub2/build default_payload.elf \
 		EXTRA_PAYLOAD_MODULES="$(CONFIG_GRUB2_EXTRA_MODULES)"
 
 clean:
-	test -d grub2 && $(MAKE) -C grub2 clean || exit 0
+	test -f grub2/build/Makefile && $(MAKE) -C grub2/build clean || exit 0
 
 distclean:
 	rm -rf grub2

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -27,6 +27,7 @@ PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h
 endif
 ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y)
 PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config
+$(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf
 #TODO: Figure out version
 endif
 
@@ -89,7 +90,10 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG)
 			CONFIG_HUDSON_UART=$(CONFIG_HUDSON_UART) \
 			CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \
 			CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \
-			CONFIG_SEABIOS_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)
+			CONFIG_SEABIOS_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL) \
+			CONFIG_DRIVERS_UART_8250MEM_32=$(CONFIG_DRIVERS_UART_8250MEM_32) \
+			CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \
+			CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS)
 
 payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios
 payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
@@ -158,6 +162,28 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
 		DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) \
 		OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE)
 
+# Tianocore
+
+payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
+	$(MAKE) -C payloads/external/tianocore all \
+		HOSTCC="$(HOSTCC)" \
+		CC="$(HOSTCC)" \
+		CONFIG_TIANOCORE_MASTER=$(CONFIG_TIANOCORE_MASTER) \
+		CONFIG_TIANOCORE_STABLE=$(CONFIG_TIANOCORE_STABLE) \
+		CONFIG_TIANOCORE_REVISION=$(CONFIG_TIANOCORE_REVISION) \
+		CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
+		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
+		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
+		GCC_CC_x86_32=$(GCC_CC_x86_32) \
+		GCC_CC_x86_64=$(GCC_CC_x86_64) \
+		GCC_CC_arm=$(GCC_CC_arm) \
+		GCC_CC_arm64=$(GCC_CC_arm64) \
+		OBJCOPY_x86_32=$(OBJCOPY_x86_32) \
+		OBJCOPY_x86_64=$(OBJCOPY_x86_64) \
+		OBJCOPY_arm=$(OBJCOPY_arm) \
+		OBJCOPY_arm64=$(OBJCOPY_arm64) \
+		MFLAGS= MAKEFLAGS=
+
 # FILO
 
 filo:
@@ -174,11 +200,13 @@ payloads/external/FILO/filo/build/version.h: filo
 
 # Grub
 
-grub2:
+grub2: $(obj)/config.h
 	$(MAKE) -C payloads/external/GRUB2 \
 			HOSTCC="$(HOSTCC)" \
-			CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \
+			CC="$(CC_x86_32)" LD="$(LD_x86_32)" \
 			OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
+			CONFIG_DEP="$(abspath $(obj)/config.h)" \
+			CONFIG_GRUB2_STABLE=$(CONFIG_GRUB2_STABLE) \
 			CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER) \
 			CONFIG_GRUB2_REVISION=$(CONFIG_GRUB2_REVISION) \
 			CONFIG_GRUB2_REVISION_ID=$(CONFIG_GRUB2_REVISION_ID) \
@@ -201,12 +229,14 @@ payloads/external/tint/tint/tint.elf tint:
 cbfs-files-$(CONFIG_TINT_SECONDARY_PAYLOAD) += img/tint
 img/tint-file := payloads/external/tint/tint/tint.elf
 img/tint-type := payload
+img/tint-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
 # Memtest86+
 
 cbfs-files-$(CONFIG_MEMTEST_SECONDARY_PAYLOAD) += img/memtest
 img/memtest-file := payloads/external/Memtest86Plus/memtest86plus/memtest
 img/memtest-type := payload
+img/memtest-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
 ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
 	MEMTEST_SERIAL_OPTIONS=SERIAL_CONSOLE_DEFAULT=1 \

diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile
@@ -15,7 +15,7 @@
 
 TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
 NAME-$(CONFIG_MEMTEST_MASTER)=Master
-TAG-$(CONFIG_MEMTEST_STABLE)=485c4fd363fe8570b3da9f0cc5dacf20e1c40cbc
+TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb
 NAME-$(CONFIG_MEMTEST_STABLE)=Stable
 
 project_name=Memtest86+
@@ -38,8 +38,8 @@ checkout: fetch
 	echo "    Checking out $(project_name) revision $(NAME-y) ($(TAG-y))"
 	cd $(project_dir); \
 		git checkout master; \
- 		git branch -D coreboot 2>/dev/null; \
- 		git checkout -b coreboot $(TAG-y)
+		git branch -D coreboot 2>/dev/null; \
+		git checkout -b coreboot $(TAG-y)
 
 build: checkout
 	echo "    MAKE       $(project_name) $(NAME-y)"

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.11.0.4"
+	bool "1.11.1"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER
@@ -54,10 +54,10 @@ config SEABIOS_THREAD_OPTIONROMS
 config SEABIOS_VGA_COREBOOT
 	prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
 	default y if !VENDOR_EMULATION
-	depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
+	depends on !(VGA_BIOS || VGA_ROM_RUN) && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
 	bool
 	help
-	  Coreboot can initialize the GPU of some mainboards.
+	  coreboot can initialize the GPU of some mainboards.
 
 	  After initializing the GPU, the information about it can be passed to the payload.
 	  Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
@@ -72,7 +72,7 @@ config PAYLOAD_CONFIGFILE
 
 config SEABIOS_BOOTORDER_FILE
 	string "SeaBIOS bootorder file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+	default ""
 	help
 	  Add a SeaBIOS bootorder file.  From the wiki:
 	  "The bootorder file may be used to configure the boot up order. The file
@@ -90,37 +90,58 @@ config SEABIOS_BOOTORDER_MAP_FILE
 	string "SeaBIOS bootorder_map file"
 	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_map"
 	help
-	  TBD
+	  Determine mapping of keystrokes to group of positions in bootorder
 
 config SEABIOS_BOOTORDER_DEF_FILE
 	string "SeaBIOS bootorder_def file"
 	default "$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder_def"
 	help
-	  TBD
+	  Determine default boot order and default values for runtime config
+	  options e.g. usben, pxen, etc.
 
 config SEABIOS_BOOTMENU_KEY_FILE
 	string "SeaBIOS boot-menu-key file"
 	default "$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-key"
 	help
-	  TBD
+	  Add SeaBIOS boot-menu-key file. From wiki:
+	  "Controls which key activates the boot menu. The value stored is the
+	  DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set,
+	  be sure to also customize the boot-menu-message field above. 
+
+	  See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
 
 config SEABIOS_BOOTMENU_WAIT_FILE
 	string "SeaBIOS boot-menu-wait file"
 	default "$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-wait"
 	help
-	  TBD
+	  Add SeaBIOS boot-menu-wait file. From wiki:
+	  "Amount of time (in milliseconds) to wait at the boot menu prompt
+	  before selecting the default boot."
+
+	  See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
 
 config SEABIOS_BOOTMENU_MESSAGE_FILE
 	string "SeaBIOS boot-menu-message file"
 	default "$(top)/src/mainboard/$(MAINBOARDDIR)/boot-menu-message"
 	help
-	  TBD
+	  Customize the text boot menu message. From wiki:
+
+	  "Customize the text boot menu message. Normally, when in text mode
+	  SeaBIOS will report the string "\nPress ESC for boot menu.\n\n". This
+	  field allows the string to be changed. (This is a string field, and
+	  is added as a file containing the raw string.)"
+
+	  See: https://www.seabios.org/Runtime_config#Other_Configuration_items
 
 config SEABIOS_SERCON_PORT_FILE
 	string "SeaBIOS sercon-port file"
 	default "$(top)/src/mainboard/$(MAINBOARDDIR)/sercon-port"
 	help
-	  TBD
+	  Enable serial port in SeaBIOS. From wiki:
+	  "Set this to the IO address of a serial port to enable SeaBIOS' VGA
+	  adapter emulation on the given serial port.
+
+	  See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
 
 config PAYLOAD_FILE
 	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"

diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name
@@ -6,4 +6,4 @@ config PAYLOAD_SEABIOS
 	  with a SeaBIOS payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See http://coreboot.org/Payloads for more information.
+	  See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=rel-1.11.0.4
+TAG-$(CONFIG_SEABIOS_STABLE)=0551a4be2ce599fb60e478b4c15e06ab6587822c
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://github.com/pcengines/seabios.git
@@ -42,10 +42,15 @@ config: checkout
 ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
 	echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config
 	echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config
-	echo "CONFIG_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)" >> seabios/.config
 else ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250MEM)$(CONFIG_HUDSON_UART),yyy)
 	echo "CONFIG_DEBUG_SERIAL_MMIO=y" >> seabios/.config
 	echo "CONFIG_DEBUG_SERIAL_MEM_ADDRESS=0xFEDC6000" >> seabios/.config
+else ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_ENABLE_HSUART),yy)
+	echo "CONFIG_DEBUG_SERIAL_MMIO=y" >> seabios/.config
+	echo "CONFIG_DEBUG_SERIAL_MEM_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS)" >> seabios/.config
+else ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250MEM_32),yy)
+	echo "CONFIG_DEBUG_SERIAL_MMIO=y" >> seabios/.config
+	echo "CONFIG_DEBUG_SERIAL_MEM_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS)" >> seabios/.config
 else
 	echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config
 endif
@@ -64,24 +69,11 @@ else
 	false
 endif
 endif
-#
-# Project specific configuration for optimized SeaBIOS
-#
-	echo "# CONFIG_BOOTSPLASH is not set" >> seabios/.config
-	echo "# CONFIG_MEGASAS is not set" >> seabios/.config
-	echo "# CONFIG_FLOPPY is not set" >> seabios/.config
-	echo "# CONFIG_PS2PORT is not set" >> seabios/.config
-	echo "# CONFIG_USB_UHCI is not set" >> seabios/.config
-	echo "# CONFIG_USB_OHCI is not set" >> seabios/.config
-	echo "# CONFIG_LPT is not set" >> seabios/.config
-#
-# Enable UDMA to speed up booting
-#
-	echo "CONFIG_ATA_DMA=y" >> seabios/.config
-	echo "CONFIG_ATA_PIO32=y" >> seabios/.config
-
-	# This shows how to force a previously set .config option *off*
-	#echo "# CONFIG_SMBIOS is not set" >> seabios/.config
+ifneq ($(CONFIG_SEABIOS_DEBUG_LEVEL),-1)
+	echo "CONFIG_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)" >> seabios/.config
+endif
+#	This shows how to force a previously set .config option *off*
+#	echo "# CONFIG_SMBIOS is not set" >> seabios/.config
 	$(MAKE) -C seabios olddefconfig OUT=out/
 
 build: config

diff --git a/payloads/external/U-Boot/Kconfig.name b/payloads/external/U-Boot/Kconfig.name
@@ -5,6 +5,6 @@ config PAYLOAD_UBOOT
 	  Select this option if you want to build a coreboot image
 	  with a U-Boot payload.
 
-	  See http://coreboot.org/Payloads and U-Boot's documentation
+	  See https://coreboot.org/Payloads and U-Boot's documentation
 	  at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
 	  for more information.
diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig
@@ -36,7 +36,7 @@ config PAYLOAD_FILE
 	default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf"
 
 config LP_DEFCONFIG_OVERRIDE
-	def_bool n
+	bool "Use default libpayload config"
 	help
 	  The Depthcharge makefile looks for a file config.<boardname> in the
 	  libpayload/configs directory.  Say Y here to use the file defconfig

diff --git a/payloads/external/depthcharge/Kconfig.name b/payloads/external/depthcharge/Kconfig.name
@@ -5,4 +5,4 @@ config PAYLOAD_DEPTHCHARGE
 	  Select this option if you want to build a coreboot image
 	  with a depthcharge payload.
 
-	  See http://coreboot.org/Payloads for more information.
+	  See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile
@@ -1,5 +1,5 @@
-# stabilize-9430.B - Wed Mar 29, 2017
-STABLE_COMMIT_ID=eb583fa82e697a97cb13a2906fcda6e2470c7623
+# Wed Apr 25, 2018
+STABLE_COMMIT_ID=902681db13c170fc2d028f7391a9e9a5f69082a3
 
 project_name=depthcharge
 project_dir=$(CURDIR)/depthcharge
@@ -15,11 +15,6 @@ TAG-$(DEPTHCHARGE_MASTER)=origin/master
 TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID)
 TAG-$(DEPTHCHARGE_REVISION)=$(DEPTHCHARGE_REVISION_ID)
 
-# todo: consider reverting this once stable moves past the commit below
-payload_target=depthcharge
-payload_target_old=$(payload_target)_unified
-payload_namechange=74a07395eb9976747055b4ac7a0ae7dcb603a6f4
-
 unexport KCONFIG_AUTOHEADER
 unexport KCONFIG_AUTOCONFIG
 unexport KCONFIG_DEPENDENCIES
@@ -31,57 +26,70 @@ unexport src srck obj objk
 BOARD:=$(notdir $(CONFIG_MAINBOARD_DIR))
 
 ifeq ($(OVERRIDE_DEFCONFIG),y)
-$(info Depthcharge: Using default defconfig for libpayload)
 libpayload_config=$(libpayload_dir)/configs/defconfig
+DEPTHCHARGE_LIBPAYLOAD_MSG="Depthcharge: Using default defconfig for libpayload"
 else
 libpayload_config=$(libpayload_dir)/configs/config.$(BOARD)
+DEPTHCHARGE_LIBPAYLOAD_MSG="Depthcharge: Using $(libpayload_dir)/configs/config.$(BOARD)"
 endif
 
 all: build
 
 $(project_dir):
-	echo "    Cloning $(project_name) from Git"
-	git clone $(project_git_repo)
+	@echo "    Cloning $(project_name) from Git"
+	@git clone $(project_git_repo) $(project_name)
 
 fetch: $(project_dir)
-	cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ] || \
+	@cd $(project_dir); \
+		git show $(TAG-y) >/dev/null 2>&1; \
+		if [ $$? -ne 0 ] || \
 		[ "$(TAG-y)" = "origin/master" ]; then \
 		echo "    Fetching new commits from the $(project_name) git repo"; \
 		git fetch; fi
 
-checkout: fetch
+# Check out the requested version of the tree
+# Don't write a file for master branch so the latest remote version is always used
+$(project_dir)/.version_$(TAG-y):
+	$(MAKE) fetch
 	echo "    Checking out $(project_name) revision $(TAG-y)"
-	cd $(project_dir) ; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+	rm -f $(project_dir)/.version_*
+	cd $(project_dir); \
+		git checkout master; \
+		git branch -D coreboot 2>/dev/null; \
+		git checkout -b coreboot $(TAG-y)
+ifneq ($(DEPTHCHARGE_MASTER),y)
+	touch $(project_dir)/.version_$(TAG-y)
+endif
 
 $(libpayload_install_dir): $(project_dir)
-	test -f $(libpayload_config)|| \
+	test -f $(libpayload_config) || \
 		(echo "Error: $(libpayload_config) is not present" && \
 		false)
+	echo $(DEPTHCHARGE_LIBPAYLOAD_MSG)
 	cp $(libpayload_config) $(libpayload_dir)/.config
 	$(MAKE) -C $(libpayload_dir) olddefconfig
 	$(MAKE) -C $(libpayload_dir)
 	$(MAKE) -C $(libpayload_dir) install DESTDIR=$(libpayload_install_dir)
-#	rm -f $(libpayload_dir)/.config
 
-config: $(libpayload_install_dir) checkout
+config: $(project_dir)/.version_$(TAG-y) $(libpayload_install_dir)
 	echo "    CONFIG     project_name $(TAG-y)"
 	export VERSION=$$(cd depthcharge && \
 		git describe --tags --long --dirty 2>/dev/null || \
 		echo "unknown") ; \
-	cd $(project_dir) && $(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
+	cd $(project_dir) && \
+		$(MAKE) BOARD=$(BOARD) \
+		LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
 		VB_SOURCE=$(VBOOT_SOURCE) defconfig
 
 build: config
 	echo "    MAKE       $(project_name) $(TAG-y)"
-	cd $(project_dir) && \
-		git merge-base --is-ancestor $(payload_namechange) $(TAG-y) >/dev/null 2>&1 && \
-			$(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
-				VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" $(payload_target) || \
-			$(MAKE) BOARD=$(BOARD) LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
-				VB_SOURCE=$(VBOOT_SOURCE) PATH="$(abspath ../../../build/util/cbfstool):$$PATH" $(payload_target_old)
+	$(MAKE) -C $(project_dir) depthcharge BOARD=$(BOARD) \
+		LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
+		VB_SOURCE=$(VBOOT_SOURCE) \
+		PATH="$(abspath ../../../build/util/cbfstool):$$PATH"
 
 clean:
-	test -d $(output_dir) && rm -rf $(output_dir) || exit 0
+	rm -rf $(output_dir)
 
 distclean:
 	rm -rf $(project_dir)

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
@@ -21,7 +21,7 @@ menu "PXE Options"
 
 choice
 	prompt "PXE ROM to use"
-	default BUILD_IPXE
+	default PXE_ROM
 
 config PXE_ROM
 	bool "Add an existing PXE ROM image"
@@ -72,10 +72,7 @@ config PXE_SERIAL_CONSOLE
 
 config PXE_ROM_ID
 	string "network card PCI IDs"
-	default "10ec,8168" if BOARD_PCENGINES_APU1
-	default "8086,157b" if BOARD_PCENGINES_APU2
- 	default "8086,1539" if BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
-	BOARD_PCENGINES_APU5
+	default "10ec,8168"
 	help
 	  The comma-separated PCI vendor and device ID that would associate
 	  your PXE ROM to your network card.
@@ -90,13 +87,13 @@ config PXE_ROM_ID
 
 config PXE_CUSTOM_GENERAL_H
 	string "iPXE custom general.h file"
-	default "../../../../apu2-documentation/ipxe/general.h"
+	default "general.h"
 	help
 	  This option allows user to customize feature set built-in into iPXE ROM.
 
 config PXE_CUSTOM_BOOTMENU_FILE
 	string "iPXE custom menu.ipxe file"
-	default "../../../../apu2-documentation/ipxe/menu.ipxe"
+	default "menu.ipxe"
 	help
 	  This option allows user to customize boot menu for iPXE ROM.
 

diff --git a/payloads/external/sortbootorder/Makefile b/payloads/external/sortbootorder/Makefile
@@ -1,4 +1,4 @@
-version=4.6.8
+version=4.6.9
 branch_name=v$(version)
 project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
 archive_name=$(branch_name).tar.gz

diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
@@ -1,9 +1,91 @@
 if PAYLOAD_TIANOCORE
 
 config PAYLOAD_FILE
-	string "Tianocore firmware volume"
-	default "COREBOOT.fd"
+	string "Tianocore binary"
+	default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd"
 	help
 	  The result of a corebootPkg build
 
+choice
+	prompt "Tianocore version"
+	default TIANOCORE_STABLE
+	help
+	  Select which version of Tianocore to build (default is to build stable)
+	  stable: a version of Tianocore that builds without any errors
+	  master: most recent version from upstream Tianocore repository
+	  revision: use specific commit or branch to build Tianocore (specified by user)
+
+config TIANOCORE_STABLE
+	bool "stable"
+	help
+	  Select this option to build the stable tianocore version
+	  i.e. a version of Tianocore that builds without any errors
+
+config TIANOCORE_MASTER
+	bool "master"
+	help
+	  Select this option to build the master tianocore version
+	  i.e. most recent version from upstream Tianocore repository
+
+config TIANOCORE_REVISION
+	bool "git revision"
+	help
+	  Select this option if you have a specific commit or branch
+	  that you want to use as the revision from which to
+	  build Tianocore.
+
+	  You will be able to specify the name of a branch or a commit id
+	  later.
+
+endchoice
+
+config TIANOCORE_REVISION_ID
+	string "Insert a commit's SHA-1 or a branch name"
+	depends on TIANOCORE_REVISION
+	default "origin/master"
+	help
+	   The commit's SHA-1 or branch name of the revision to use.
+
+choice
+	prompt "Target architecture"
+	default TIANOCORE_TARGET_X64
+	help
+	  The Tianocore coreboot Payload Package binary can be
+	  built for either only IA32 or both X64 and IA32 architectures.
+	  Select which architecture(s) to build for; default is to build
+	  for both X64 and IA32.
+
+config TIANOCORE_TARGET_IA32
+	bool "IA32"
+	help
+	  By selecting this option, the target architecture will be built
+	  for only IA32.
+
+config TIANOCORE_TARGET_X64
+	bool "X64"
+	help
+	  By selecting this option, the target architecture will be built
+	  for X64 and IA32.
+
+endchoice
+
+choice
+	prompt "Tianocore build"
+	default TIANOCORE_RELEASE
+	help
+	  Select whether to generate a debug or release build for
+	  Tianocore; default is to generate a release build.
+
+config TIANOCORE_DEBUG
+	bool "Generate Tianocore debug build"
+	help
+	  Generate a debug build.
+
+config TIANOCORE_RELEASE
+	bool "Generate Tianocore release build"
+	help
+	  Generate a release build.
+
+endchoice
+
 endif
diff --git a/payloads/external/tianocore/Kconfig.name b/payloads/external/tianocore/Kconfig.name
@@ -1,8 +1,8 @@
 config PAYLOAD_TIANOCORE
-	bool "Tiano Core"
+	bool "Tianocore coreboot payload package"
 	help
 	  Select this option if you want to build a coreboot image
-	  with a Tiano Core payload. If you don't know what this is
+	  with a Tianocore payload. If you don't know what this is
 	  about, just leave it enabled.
 
-	  See http://coreboot.org/Payloads for more information.
+	  See https://coreboot.org/Payloads for more information.
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
@@ -0,0 +1,107 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# force the shell to bash - the edksetup.sh script doesn't work with dash
+export SHELL := env bash
+
+STABLE_COMMIT_ID=315d9d08fd77db1024ccc5307823da8aaed85e2f
+TAG-$(CONFIG_TIANOCORE_MASTER)=origin/master
+TAG-$(CONFIG_TIANOCORE_STABLE)=$(STABLE_COMMIT_ID)
+TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID)
+
+project_name=Tianocore
+project_dir=$(CURDIR)/tianocore
+project_git_repo=https://github.com/tianocore/edk2
+
+export EDK_TOOLS_PATH=$(project_dir)/BaseTools
+
+ifeq ($(CONFIG_TIANOCORE_DEBUG),y)
+BUILD_TYPE=DEBUG
+else
+BUILD_TYPE=RELEASE
+endif
+
+ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
+	BUILD_STR=-a IA32 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -b $(BUILD_TYPE)
+else
+	BUILD_STR=-a IA32 -a X64 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -b $(BUILD_TYPE)
+endif
+
+all: build
+
+$(project_dir):
+	echo "    Cloning $(project_name) from Git"
+	git clone $(project_git_repo) $(project_dir)
+
+fetch: $(project_dir)
+	cd $(project_dir); \
+		git show $(TAG-y) >/dev/null 2>&1 ; \
+		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
+			echo "    Fetching new commits from the $(project_name) repo"; \
+			git fetch; \
+		fi
+
+$(project_dir)/.version_$(TAG-y): fetch
+	if  ! [[ -e $(project_dir)/.version_$(STABLE_COMMIT_ID) ]] || \
+		[ "$(TAG-y)" = "origin/master" ] ; then \
+		rm -f .version_*; \
+		echo "    Checking out $(project_name) revision $(TAG-y)"; \
+		cd  $(project_dir); \
+			git checkout master; \
+			git branch -D coreboot 2>/dev/null; \
+			git checkout -b coreboot $(TAG-y); \
+		for patch in $(CURDIR)/patches/*.patch; do \
+			echo "Applying $$patch"; \
+			cd $(project_dir); \
+			git am --keep-cr $$patch || \
+				( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \
+		done; \
+		if ! [ "$(TAG-y)" = "origin/master" ] ; then \
+			touch $(project_dir)/.version_$(STABLE_COMMIT_ID); \
+		fi; \
+	fi; \
+
+checktools:
+	echo "Checking uuid-dev..."
+	echo "#include <uuid/uuid.h>" > libtest.c
+	echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
+	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \
+		( echo " Not found."; echo "ERROR: please_install uuid-dev (uuid-devel)"; exit 1 )
+	rm -rf libtest.c libtest
+	echo "Checking nasm..."
+	type nasm > /dev/null 2>&1 && echo " found nasm." || \
+		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
+
+build: $(project_dir)/.version_$(TAG-y) checktools
+	unset CC; $(MAKE) -C $(project_dir)/BaseTools
+	echo " build $(project_name) $(TAG-y)"
+	cd $(project_dir); \
+		export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
+		export WORKSPACE=$(project_dir); \
+		. ./edksetup.sh BaseTools; \
+		grep -q "COREBOOT" $(project_dir)/Conf/tools_def.txt; \
+		if [ $$? -ne 0 ]; then \
+			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
+		fi; \
+		build $(BUILD_STR); \
+		mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd
+
+clean:
+	test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
+
+distclean:
+	rm -rf $(project_dir)
+
+.PHONY: all fetch checkout checktools config build clean distclean
diff --git a/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch b/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch
@@ -0,0 +1,65 @@
+From 4f9d41e69356ce7486b0c74a754ff494256723de Mon Sep 17 00:00:00 2001
+From: CoolStar <coolstarorganization@gmail.com>
+Date: Sun, 4 Dec 2016 11:23:38 -0800
+Subject: [PATCH] PCI: use Duet's PciNoEnumeration
+
+---
+ CorebootPayloadPkg/CorebootPayloadPkg.fdf        | 4 ++--
+ CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc    | 7 ++-----
+ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 ++-----
+ 3 files changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+index 303e626842..a39e3999ba 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
++++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+@@ -124,8 +124,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ #
+ # PCI Support
+ #
+-INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+-INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
++INF DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
++INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+
+ #
+ # ISA Support
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+index cdfcb75b59..e838aca61d 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
++++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+@@ -450,11 +450,8 @@
+   #
+   # PCI Support
+   #
+-  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+-  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+-    <LibraryClasses>
+-      PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+-  }
++  DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
++  DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+
+   #
+   # SCSI/ATA/IDE/DISK Support
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+index 6b16af63ba..c25d821fd4 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
++++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+@@ -451,11 +451,8 @@
+   #
+   # PCI Support
+   #
+-  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+-  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+-    <LibraryClasses>
+-      PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+-  }
++  DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
++  DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+
+   #
+   # SCSI/ATA/IDE/DISK Support
+-- 
+2.13.2.725.g09c95d1e9-goog
+
diff --git a/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch b/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch
diff --git a/payloads/external/tianocore/patches/03_Library_EndofDXE.patch b/payloads/external/tianocore/patches/03_Library_EndofDXE.patch
@@ -0,0 +1,86 @@
+From 760f1cafdd689beedc8418ab89e856b54296389c Mon Sep 17 00:00:00 2001
+From: CoolStar <coolstarorganization@gmail.com>
+Date: Sun, 4 Dec 2016 12:07:30 -0800
+Subject: [PATCH] CorebootBdsLib: Call End of DXE event to allow booting 3rd
+ party efi binaries.
+
+---
+ .../Library/CorebootBdsLib/BdsPlatform.c           | 42 ++++++++++++++++++++++
+ .../Library/CorebootBdsLib/PlatformBds.inf         |  1 +
+ 2 files changed, 43 insertions(+)
+
+diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
+index b6253a17f8..cf3e5320cb 100644
+--- a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
++++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
+@@ -1129,6 +1129,46 @@ Returns:
+   Status = BaseMemoryTest (MemoryTestLevel);
+ }
+
++VOID
++EFIAPI
++InternalBdsEmptyCallbackFuntion (
++  IN EFI_EVENT                Event,
++  IN VOID                     *Context
++  )
++{
++  return;
++}
++
++VOID
++InstallReadyToLock (
++  VOID
++  )
++{
++  EFI_STATUS                            Status;
++  EFI_EVENT                             EndOfDxeEvent;
++
++  DEBUG((DEBUG_INFO,"InstallReadyToLock  entering......\n"));
++  //
++  // Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter
++  // Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth
++  //
++  Status = gBS->CreateEventEx (
++                  EVT_NOTIFY_SIGNAL,
++                  TPL_CALLBACK,
++                  InternalBdsEmptyCallbackFuntion,
++                  NULL,
++                  &gEfiEndOfDxeEventGroupGuid,
++                  &EndOfDxeEvent
++                  );
++  ASSERT_EFI_ERROR (Status);
++  gBS->SignalEvent (EndOfDxeEvent);
++  gBS->CloseEvent (EndOfDxeEvent);
++  DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n"));
++
++  DEBUG((DEBUG_INFO,"InstallReadyToLock  end\n"));
++  return;
++}
++
+ VOID
+ EFIAPI
+ PlatformBdsPolicyBehavior (
+@@ -1164,6 +1204,8 @@ Returns:
+   EFI_INPUT_KEY                      Key;
+   EFI_BOOT_MODE                      BootMode;
+
++  InstallReadyToLock();
++
+   //
+   // Init the time out value
+   //
+diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
+index 578c74afae..992bd846bd 100644
+--- a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
++++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
+@@ -58,6 +58,7 @@
+   gEfiSmbiosTableGuid
+   gEfiAcpiTableGuid
+   gLdrMemoryDescriptorGuid
++  gEfiEndOfDxeEventGroupGuid
+
+ [Pcd]
+   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+-- 
+2.13.2.725.g09c95d1e9-goog
+
diff --git a/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch b/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch
@@ -0,0 +1,56 @@
+From 77c5dfcce842819215490fe63c481860fa7d752d Mon Sep 17 00:00:00 2001
+From: CoolStar <coolstarorganization@gmail.com>
+Date: Sun, 4 Dec 2016 11:50:00 -0800
+Subject: [PATCH] CorebootPayloadPkg: Add PS/2 keyboard drivers.
+
+---
+ CorebootPayloadPkg/CorebootPayloadPkg.fdf        | 3 +++
+ CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc    | 3 +++
+ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +++
+ 3 files changed, 9 insertions(+)
+
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+index 347e9c75ce..a347af0c9a 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
++++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+@@ -132,6 +132,9 @@ INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+ # ISA Support
+ #
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++INF  PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
++INF  IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
++INF  IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+
+ #
+ # Console Support
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+index 5ce823bb95..60ee064c59 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
++++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+@@ -492,6 +492,9 @@
+   # ISA Support
+   #
+   MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++  PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
++  IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
++  IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+
+   #
+   # Console Support
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+index fea297a77a..167329c897 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
++++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+@@ -493,6 +493,9 @@
+   # ISA Support
+   #
+   MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++  PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
++  IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
++  IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+
+   #
+   # Console Support
+-- 
+2.13.2.725.g09c95d1e9-goog
+
diff --git a/payloads/external/tianocore/patches/05_CorebootPayloadPkg_noserial.patch b/payloads/external/tianocore/patches/05_CorebootPayloadPkg_noserial.patch
@@ -0,0 +1,39 @@
+From 77f75370d6fbfefb04456f6e1c32c85d4bac8bf5 Mon Sep 17 00:00:00 2001
+From: Matt Devo <matt.devillier@gmail.com>
+Date: Thu, 23 Feb 2017 14:11:14 -0600
+Subject: [PATCH] CorebootPayloadPkg: don't use serial output
+
+---
+ CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc    | 2 +-
+ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+index 1d80fc4f5c..ce360c9e9e 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
++++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+@@ -261,7 +261,7 @@
+ #
+ ################################################################################
+ [PcdsFeatureFlag]
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
++  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+index 52b26eb3d0..a27b0873a1 100644
+--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
++++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+@@ -261,7 +261,7 @@
+ #
+ ################################################################################
+ [PcdsFeatureFlag]
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
++  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+-- 
+2.13.2.725.g09c95d1e9-goog
+
diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch
@@ -0,0 +1,26 @@
+From ef89b11ce6f93c96fbd1753a8006dd9c3da212e0 Mon Sep 17 00:00:00 2001
+From: ReddestDream <reddestdream@gmail.com>
+Date: Wed, 3 May 2017 00:13:28 -0400
+Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being
+ overwritten
+
+Exclude the bottom 4kb from being included in System Memory HoB
+
+diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
+index 262e6b9..d3c5723 100755
+--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c
++++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c
+@@ -261,8 +261,9 @@ CbPeiEntryPoint (
+     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+     ),
+-    (EFI_PHYSICAL_ADDRESS)(0),
+-    (UINT64)(0xA0000)
++    // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides
++    (EFI_PHYSICAL_ADDRESS)(0 + 0x1000),
++    (UINT64)(0xA0000 - 0x1000)
+     );
+
+
+--
+2.14.0
diff --git a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch b/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch
@@ -0,0 +1,31 @@
+From 07dec11fe965e73cfef7df38af70c945b6ff21a2 Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Wed, 24 Jan 2018 10:07:08 +0100
+Subject: [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine
+
+Fetch BytesPerScanLine from coreboot table to reflect how the actual
+framebuffer is set up instead of guessing it from the horizontal
+resolution.
+
+This fixes a garbled display when HorizontalResolution * (BitsPerPixel
+/ 8) and pFbInfo->BytesPerScanLine don't match.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c
+index 37d6def7f7..6790617033 100644
+--- a/CorebootPayloadPkg/FbGop/FbGop.c
++++ b/CorebootPayloadPkg/FbGop/FbGop.c
+@@ -822,7 +822,7 @@ FbGopCheckForVbe (
+   BitsPerPixel         = pFbInfo->BitsPerPixel;
+   HorizontalResolution = pFbInfo->HorizontalResolution;
+   VerticalResolution   = pFbInfo->VerticalResolution;
+-  BytesPerScanLine     = HorizontalResolution * (BitsPerPixel / 8);
++  BytesPerScanLine     = pFbInfo->BytesPerScanLine;
+
+   ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool (
+ 																						ModeNumber * sizeof (FB_VIDEO_MODE_DATA)
+-- 
+2.16.1
+