37 changes: 0 additions & 37 deletions src/drivers/intel/fsp1_1/romstage.c
View file
Expand Up @@ -33,8 +33,6 @@ static void raminit_common(struct romstage_params *params)

elog_boot_notify(s3wake);

/* Perform remaining SOC initialization */
soc_pre_ram_init(params);
post_code(0x33);

/* Check recovery and MRC cache */
Expand Down Expand Up @@ -136,12 +134,6 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
post_code(0x38);
}

/* Initialize the power state */
__weak struct chipset_power_state *fill_power_state(void)
{
return NULL;
}

/* Board initialization before and after RAM is enabled */
__weak void mainboard_pre_raminit(struct romstage_params *params)
{
Expand Down Expand Up @@ -264,39 +256,10 @@ __weak void mainboard_save_dimm_info(
MEMORY_BUS_WIDTH_128;
break;
}

/* Add any mainboard specific information */
mainboard_add_dimm_info(params, mem_info,
channel, dimm, index);
index++;
}
}
}
mem_info->dimm_cnt = index;
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}

/* Add any mainboard specific information */
__weak void mainboard_add_dimm_info(
struct romstage_params *params,
struct memory_info *mem_info,
int channel, int dimm, int index)
{
}

/* Save the memory configuration data */
__weak int mrc_cache_stash_data(int type, uint32_t version,
const void *data, size_t size)
{
return -1;
}

/* SOC initialization after RAM is enabled */
__weak void soc_after_ram_init(struct romstage_params *params)
{
}

/* SOC initialization before RAM is enabled */
__weak void soc_pre_ram_init(struct romstage_params *params)
{
}
11 changes: 0 additions & 11 deletions src/drivers/intel/fsp1_1/verstage.c
View file

This file was deleted.

6 changes: 6 additions & 0 deletions src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -74,6 +74,12 @@ config FSP_T_CBFS
depends on FSP_CAR
default "fspt.bin"

config FSP_T_LOCATION
hex
default 0xfffe0000
help
The location for FSP-T.

config FSP_S_CBFS
string "Name of FSP-S in CBFS"
default "fsps.bin"
Expand Down
1 change: 1 addition & 0 deletions src/drivers/intel/fsp2_0/Makefile.inc
View file
Expand Up @@ -48,6 +48,7 @@ $(FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))
$(FSP_T_CBFS)-type := fsp
ifeq ($(CONFIG_FSP_T_XIP),y)
$(FSP_T_CBFS)-options := --xip $(TXTIBB)
$(FSP_T_CBFS)-position = $(CONFIG_FSP_T_LOCATION)
endif

cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_M_CBFS)
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/intel/fsp2_0/notify.c
View file
Expand Up @@ -38,10 +38,10 @@ static void fsp_notify(enum fsp_notify_phase phase)

if (phase == AFTER_PCI_ENUM) {
timestamp_add_now(TS_FSP_AFTER_ENUMERATE);
post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE);
post_code(POST_FSP_NOTIFY_AFTER_ENUMERATE);
} else if (phase == READY_TO_BOOT) {
timestamp_add_now(TS_FSP_AFTER_FINALIZE);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
post_code(POST_FSP_NOTIFY_AFTER_FINALIZE);
} else if (phase == END_OF_FIRMWARE) {
timestamp_add_now(TS_FSP_AFTER_END_OF_FIRMWARE);
post_code(POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE);
Expand Down
11 changes: 4 additions & 7 deletions src/drivers/intel/gma/Kconfig
View file
Expand Up @@ -84,10 +84,9 @@ config GFX_GMA
def_bool y
depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
|| NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \
|| NORTHBRIDGE_INTEL_HASWELL \
|| SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \
|| SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \
|| SOC_INTEL_WHISKEYLAKE || SOC_INTEL_COMETLAKE
|| NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \
|| SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \
|| SOC_INTEL_CANNONLAKE_BASE
depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID
select RAMSTAGE_LIBHWBASE

Expand All @@ -113,9 +112,7 @@ config GFX_GMA_DYN_CPU
config GFX_GMA_GENERATION
string
default "Broxton" if SOC_INTEL_APOLLOLAKE
default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \
SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE || \
SOC_INTEL_COMETLAKE
default "Skylake" if SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_CANNONLAKE_BASE
default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE
default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X
Expand Down
13 changes: 11 additions & 2 deletions src/drivers/intel/usb4/retimer/chip.h
View file
Expand Up @@ -4,10 +4,19 @@
#define __DRIVERS_INTEL_USB4_RETIMER_H__

#include <acpi/acpi_device.h>
#include <acpi/acpi.h>
#include <acpi/acpi_pld.h>

#define DFP_NUM_MAX 2

struct drivers_intel_usb4_retimer_config {
/* GPIO used to control power of retimer device. */
struct acpi_gpio power_gpio;
/* Downstream facing port(DFP) */
struct {
/* GPIO used to control power of retimer device */
struct acpi_gpio power_gpio;
/* _PLD setting */
struct acpi_pld_group group;
} dfp[DFP_NUM_MAX];
};

#endif /* __DRIVERS_INTEL_USB4_RETIMER_H__ */
402 changes: 331 additions & 71 deletions src/drivers/intel/usb4/retimer/retimer.c
View file

Large diffs are not rendered by default.

27 changes: 26 additions & 1 deletion src/drivers/intel/usb4/retimer/retimer.h
View file
Expand Up @@ -3,7 +3,32 @@
#ifndef _DRIVERS_INTEL_USB4_RETIMER_H_
#define _DRIVERS_INTEL_USB4_RETIMER_H_

/* Flags representing mux state */
#define USB_PD_MUX_NONE 0 /* Open switch */
#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */

#define USB_RETIMER_FW_UPDATE_OP_SHIFT 4
#define USB_RETIMER_FW_UPDATE_ERROR 0xfe
/* Retimer firmware update operations */
#define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */
#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */
#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */
#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */
#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */
#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */
#define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */

struct usb4_retimer_dsm_uuid {
const char *uuid;
void (**callbacks)(uint8_t port, void *);
size_t count;
void *arg;
};

const char *ec_retimer_fw_update_path(void);
void ec_retimer_fw_update(void *arg);
void ec_retimer_fw_update(uint8_t data);

#endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */
2 changes: 1 addition & 1 deletion src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
View file
Expand Up @@ -25,7 +25,7 @@ static void lenovo_hybrid_graphics_enable(struct device *dev)
return;
}

mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);

if (mode == HYBRID_GRAPHICS_DISCRETE) {
printk(BIOS_DEBUG, "Hybrid graphics:"
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/lenovo/hybrid_graphics/romstage.c
View file
Expand Up @@ -39,7 +39,7 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
return;
}

mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);

if (mode == HYBRID_GRAPHICS_DISCRETE) {
printk(BIOS_DEBUG, "Hybrid graphics:"
Expand Down
33 changes: 22 additions & 11 deletions src/drivers/pc80/rtc/option.c
View file
Expand Up @@ -84,7 +84,7 @@ static struct cmos_entries *find_cmos_entry(struct cmos_option_table *ct, const
return NULL;
}

enum cb_err cmos_get_option(void *dest, const char *name)
static enum cb_err cmos_get_uint_option(unsigned int *dest, const char *name)
{
struct cmos_option_table *ct;
struct cmos_entries *ce;
Expand All @@ -99,6 +99,11 @@ enum cb_err cmos_get_option(void *dest, const char *name)
return CB_CMOS_OPTION_NOT_FOUND;
}

if (ce->config != 'e' && ce->config != 'h') {
printk(BIOS_ERR, "ERROR: CMOS option '%s' is not of integer type.\n", name);
return CB_ERR_ARG;
}

if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC))
return CB_CMOS_CHECKSUM_INVALID;

Expand All @@ -108,6 +113,12 @@ enum cb_err cmos_get_option(void *dest, const char *name)
return CB_SUCCESS;
}

unsigned int get_uint_option(const char *name, const unsigned int fallback)
{
unsigned int value = 0;
return cmos_get_uint_option(&value, name) == CB_SUCCESS ? value : fallback;
}

static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
void *vret)
{
Expand Down Expand Up @@ -149,11 +160,10 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
return CB_SUCCESS;
}

enum cb_err cmos_set_option(const char *name, void *value)
static enum cb_err cmos_set_uint_option(const char *name, unsigned int *value)
{
struct cmos_option_table *ct;
struct cmos_entries *ce;
unsigned long length;

ct = get_cmos_layout();
if (!ct)
Expand All @@ -165,21 +175,22 @@ enum cb_err cmos_set_option(const char *name, void *value)
return CB_CMOS_OPTION_NOT_FOUND;
}

length = ce->length;
if (ce->config == 's') {
length = MAX(strlen((const char *)value) * 8, ce->length - 8);
/* make sure the string is null terminated */
if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0})
!= CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;
if (ce->config != 'e' && ce->config != 'h') {
printk(BIOS_ERR, "ERROR: CMOS option '%s' is not of integer type.\n", name);
return CB_ERR_ARG;
}

if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS)
if (set_cmos_value(ce->bit, ce->length, value) != CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;

return CB_SUCCESS;
}

enum cb_err set_uint_option(const char *name, unsigned int value)
{
return cmos_set_uint_option(name, &value);
}

int cmos_lb_cks_valid(void)
{
return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC);
Expand Down
1 change: 1 addition & 0 deletions src/drivers/pc80/tpm/Makefile.inc
View file
@@ -1,3 +1,4 @@
bootblock-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c
verstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c
romstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c
ramstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/pc80/tpm/tis.c
View file
Expand Up @@ -877,7 +877,7 @@ static struct pnp_info pnp_dev_info[] = {

static void enable_dev(struct device *dev)
{
if (CONFIG(TPM1) || CONFIG(TPM2))
if (CONFIG(TPM))
pnp_enable_devices(dev, &lpc_tpm_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
Expand Down
232 changes: 161 additions & 71 deletions src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
View file
Expand Up @@ -31,6 +31,14 @@
#define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
#define DP_LANE_COUNT_MASK 0xf

/* Backlight configuration */
#define DP_BACKLIGHT_MODE_SET 0x721
#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3
#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2
#define DP_DISPLAY_CONTROL_REGISTER 0x720
#define DP_BACKLIGHT_ENABLE 0x1
#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722

/* link configuration */
#define DP_LINK_BW_SET 0x100
#define DP_LINK_BW_1_62 0x06
Expand Down Expand Up @@ -127,14 +135,22 @@ enum vstream_config {
enum i2c_over_aux {
I2C_OVER_AUX_WRITE_MOT_0 = 0x0,
I2C_OVER_AUX_READ_MOT_0 = 0x1,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x4,
I2C_OVER_AUX_WRITE_MOT_1 = 0x5,
I2C_OVER_AUX_READ_MOT_1 = 0x6,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x7,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2,
I2C_OVER_AUX_WRITE_MOT_1 = 0x4,
I2C_OVER_AUX_READ_MOT_1 = 0x5,
I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6,
NATIVE_AUX_WRITE = 0x8,
NATIVE_AUX_READ = 0x9,
};

enum aux_cmd_status {
NAT_I2C_FAIL = 1 << 6,
AUX_SHORT = 1 << 5,
AUX_DFER = 1 << 4,
AUX_RPLY_TOUT = 1 << 3,
SEND_INT = 1 << 0,
};

enum ml_tx_mode {
MAIN_LINK_OFF = 0x0,
NORMAL_MODE = 0x1,
Expand All @@ -150,9 +166,13 @@ enum ml_tx_mode {
REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb,
};

enum dpcd_request {
DPCD_READ = 0x0,
DPCD_WRITE = 0x1,
enum aux_request {
DPCD_READ,
DPCD_WRITE,
I2C_RAW_READ,
I2C_RAW_WRITE,
I2C_RAW_READ_AND_STOP,
I2C_RAW_WRITE_AND_STOP,
};

enum {
Expand All @@ -169,84 +189,140 @@ static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = {
0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
};

enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out)
static bool request_is_write(enum aux_request request)
{
int ret;
u8 edid[EDID_LENGTH * 2];
int edid_size = EDID_LENGTH;

/* Send I2C command to claim EDID I2c slave */
i2c_writeb(bus, chip, SN_I2C_CLAIM_ADDR_EN1, (EDID_I2C_ADDR << 1) | 0x1);

/* read EDID */
ret = i2c_read_bytes(bus, EDID_I2C_ADDR, 0x0, edid, EDID_LENGTH);
if (ret != 0) {
printk(BIOS_ERR, "ERROR: Failed to read EDID.\n");
return CB_ERR;
}

if (edid[EDID_EXTENSION_FLAG]) {
edid_size += EDID_LENGTH;
ret = i2c_read_bytes(bus, EDID_I2C_ADDR, EDID_LENGTH,
&edid[EDID_LENGTH], EDID_LENGTH);
if (ret != 0) {
printk(BIOS_ERR, "Failed to read EDID ext block.\n");
return CB_ERR;
}
switch (request) {
case I2C_RAW_WRITE_AND_STOP:
case I2C_RAW_WRITE:
case DPCD_WRITE:
return true;
default:
return false;
}
}

if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) {
printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n");
return CB_ERR;
static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this)
{
switch (request) {
case I2C_RAW_WRITE_AND_STOP:
if (!remaining_after_this)
return I2C_OVER_AUX_WRITE_MOT_0;
/* fallthrough */
case I2C_RAW_WRITE:
return I2C_OVER_AUX_WRITE_MOT_1;
case I2C_RAW_READ_AND_STOP:
if (!remaining_after_this)
return I2C_OVER_AUX_READ_MOT_0;
/* fallthrough */
case I2C_RAW_READ:
return I2C_OVER_AUX_READ_MOT_1;
case DPCD_WRITE:
return NATIVE_AUX_WRITE;
case DPCD_READ:
default:
return NATIVE_AUX_READ;
}

return CB_SUCCESS;
}

static void sn65dsi86_bridge_dpcd_request(uint8_t bus,
uint8_t chip,
unsigned int dpcd_reg,
unsigned int len,
enum dpcd_request request,
uint8_t *data)
static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
uint8_t chip,
unsigned int target_reg,
unsigned int total_size,
enum aux_request request,
uint8_t *data)
{
int i;
uint32_t length;
uint8_t buf;
uint8_t reg;

while (len) {
length = MIN(len, 16);
/* Clear old status flags just in case they're left over from a previous transfer. */
i2c_writeb(bus, chip, SN_AUX_CMD_STATUS_REG,
NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT);

while (total_size) {
length = MIN(total_size, 16);
total_size -= length;

enum i2c_over_aux cmd = get_aux_cmd(request, total_size);
if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) ||
i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) ||
i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) ||
i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (target_reg) & 0xFF) ||
i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length))
return CB_ERR;

i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (dpcd_reg >> 16) & 0xF);
i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (dpcd_reg >> 8) & 0xFF);
i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (dpcd_reg) & 0xFF);
i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length); /* size of 1 Byte data */
if (request == DPCD_WRITE) {
if (request_is_write(request)) {
reg = SN_AUX_WDATA_REG_0;
for (i = 0; i < length; i++)
i2c_writeb(bus, chip, reg++, *data++);

i2c_writeb(bus, chip,
SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_WRITE << 4));
} else {
i2c_writeb(bus, chip,
SN_AUX_CMD_REG, AUX_CMD_SEND | (NATIVE_AUX_READ << 4));
if (!wait_ms(100,
!i2c_readb(bus, chip, SN_AUX_CMD_REG,
&buf) && !(buf & AUX_CMD_SEND))) {
printk(BIOS_ERR, "ERROR: aux command send failed\n");
}
if (i2c_writeb(bus, chip, reg++, *data++))
return CB_ERR;
}

if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, AUX_CMD_SEND | (cmd << 4)))
return CB_ERR;
if (!wait_ms(100, !i2c_readb(bus, chip, SN_AUX_CMD_REG, &buf) &&
!(buf & AUX_CMD_SEND))) {
printk(BIOS_ERR, "ERROR: AUX_CMD_SEND not acknowledged\n");
return CB_ERR;
}
if (i2c_readb(bus, chip, SN_AUX_CMD_STATUS_REG, &buf))
return CB_ERR;
if (buf & (NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT)) {
printk(BIOS_ERR, "ERROR: AUX command failed, status = %#x\n", buf);
return CB_ERR;
}

if (!request_is_write(request)) {
reg = SN_AUX_RDATA_REG_0;
for (i = 0; i < length; i++) {
i2c_readb(bus, chip, reg++, &buf);
if (i2c_readb(bus, chip, reg++, &buf))
return CB_ERR;
*data++ = buf;
}
}
}

return CB_SUCCESS;
}

cb_err_t sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out)
{
cb_err_t err;
u8 edid[EDID_LENGTH * 2];
int edid_size = EDID_LENGTH;

uint8_t reg_addr = 0;
err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, 1,
I2C_RAW_WRITE, &reg_addr);
if (!err)
err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, EDID_LENGTH,
I2C_RAW_READ_AND_STOP, edid);
if (err) {
printk(BIOS_ERR, "ERROR: Failed to read EDID.\n");
return err;
}

if (edid[EDID_EXTENSION_FLAG]) {
edid_size += EDID_LENGTH;
reg_addr = EDID_LENGTH;
err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, 1,
I2C_RAW_WRITE, &reg_addr);
if (!err)
err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR,
EDID_LENGTH, I2C_RAW_READ_AND_STOP, &edid[EDID_LENGTH]);
if (err) {
printk(BIOS_ERR, "Failed to read EDID ext block.\n");
return err;
}
}

len -= length;
if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) {
printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n");
return CB_ERR;
}

return CB_SUCCESS;
}

static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate_valid[])
Expand All @@ -255,15 +331,15 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate
uint8_t dpcd_val;
int i, j;

sn65dsi86_bridge_dpcd_request(bus, chip,
DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val);
sn65dsi86_bridge_aux_request(bus, chip,
DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val);
if (dpcd_val >= DP_BRIDGE_14) {
/* eDP 1.4 devices must provide a custom table */
uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0};

sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES,
sizeof(sink_rates),
DPCD_READ, (void *)sink_rates);
sn65dsi86_bridge_aux_request(bus, chip, DP_SUPPORTED_LINK_RATES,
sizeof(sink_rates),
DPCD_READ, (void *)sink_rates);
for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
rate_per_200khz = le16_to_cpu(sink_rates[i]);

Expand All @@ -288,7 +364,7 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate
}

/* On older versions best we can do is use DP_MAX_LINK_RATE */
sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val);
sn65dsi86_bridge_aux_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val);

switch (dpcd_val) {
default:
Expand Down Expand Up @@ -410,8 +486,8 @@ static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip)
* at DisplayPort address 0x0010A prior to link training.
*/
buf = 0x1;
sn65dsi86_bridge_dpcd_request(bus, chip,
DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf);
sn65dsi86_bridge_aux_request(bus, chip,
DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf);

int i; /* Kernel driver suggests to retry this up to 10 times if it fails. */
for (i = 0; i < 10; i++) {
Expand All @@ -429,6 +505,20 @@ static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip)
printk(BIOS_ERR, "ERROR: Link training failed 10 times\n");
}

void sn65dsi86_backlight_enable(uint8_t bus, uint8_t chip)
{
uint8_t val = DP_BACKLIGHT_CONTROL_MODE_DPCD;
sn65dsi86_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1, DPCD_WRITE, &val);

val = 0xff;
sn65dsi86_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1,
DPCD_WRITE, &val);

val = DP_BACKLIGHT_ENABLE;
sn65dsi86_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1,
DPCD_WRITE, &val);
}

static void sn65dsi86_bridge_assr_config(uint8_t bus, uint8_t chip, int enable)
{
if (enable)
Expand All @@ -441,7 +531,7 @@ static int sn65dsi86_bridge_dp_lane_config(uint8_t bus, uint8_t chip)
{
uint8_t lane_count;

sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count);
sn65dsi86_bridge_aux_request(bus, chip, DP_MAX_LANE_COUNT, 1, DPCD_READ, &lane_count);
lane_count &= DP_LANE_COUNT_MASK;
i2c_write_field(bus, chip, SN_SSC_CONFIG_REG, MIN(lane_count, 3), 3, 4);

Expand Down
1 change: 1 addition & 0 deletions src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h
View file
Expand Up @@ -18,5 +18,6 @@ void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip,
struct edid *edid, uint32_t num_of_lines,
uint32_t dsi_bpp);
enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out);
void sn65dsi86_backlight_enable(uint8_t bus, uint8_t chip);

#endif
3 changes: 2 additions & 1 deletion src/drivers/tpm/Kconfig
View file
@@ -1,7 +1,8 @@
config TPM_INIT_RAMSTAGE
bool
default y if TPM1 || TPM2
depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT
depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT \
&& !TPM_MEASURED_BOOT_INIT_BOOTBLOCK
help
This driver automatically initializes the TPM if vboot is not used.
The TPM driver init is done during the ramstage chip init phase.
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/wifi/generic/generic.c
View file
Expand Up @@ -10,7 +10,7 @@

static void wifi_pci_dev_init(struct device *dev)
{
if (pci_dev_is_wake_source(dev))
if (pci_dev_is_wake_source(PCI_BDF(dev)))
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_WIFI, 0);
}

Expand Down
7 changes: 7 additions & 0 deletions src/ec/google/chromeec/acpi/cros_ec.asl
View file
Expand Up @@ -55,4 +55,11 @@ Device (CREC)
{
Return (0xB)
}

#if CONFIG(DRIVERS_ACPI_THERMAL_ZONE)
Method(TMP, 1)
{
Return(^^TSRD(Arg0))
}
#endif
}
15 changes: 3 additions & 12 deletions src/ec/google/chromeec/ec_acpi.c
View file
Expand Up @@ -242,24 +242,15 @@ const char *ec_retimer_fw_update_path(void)
return "\\_SB_.PCI0.LPCB.EC0_.RFWU";
}

void ec_retimer_fw_update(void *arg)
void ec_retimer_fw_update(uint8_t data)
{
const char *RFWU = ec_retimer_fw_update_path();

/*
* Get information to set retimer info from Arg3[0]
* Local0 = DeRefOf (Arg3[0])
*/
acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP);

/*
* Write the EC RAM for Retimer Upgrade
* RFWU = LOCAL0
* RFWU = data
*/
acpigen_write_store();
acpigen_emit_byte(LOCAL0_OP);
acpigen_write_byte(data);
acpigen_emit_namestring(RFWU);

/* Return (Zero) */
acpigen_write_return_integer(0);
}
31 changes: 14 additions & 17 deletions src/ec/google/chromeec/ec_lpc.c
View file
Expand Up @@ -7,6 +7,7 @@
#include <device/pnp.h>
#include <ec/google/common/mec.h>
#include <stdint.h>
#include <timer.h>

#include "chip.h"
#include "ec.h"
Expand Down Expand Up @@ -92,23 +93,19 @@ static inline u8 write_byte(u8 val, u16 port)

static int google_chromeec_status_check(u16 port, u8 mask, u8 cond)
{
u8 ec_status = read_byte(port);
u32 time_count = 0;

/*
* One second is more than plenty for any EC operation to complete
* (and the bus accessing/code execution) overhead will make the
* timeout even longer.
*/
#define MAX_EC_TIMEOUT_US 1000000

while ((ec_status & mask) != cond) {
udelay(1);
if (time_count++ == MAX_EC_TIMEOUT_US)
return -1;
ec_status = read_byte(port);
}
return 0;
struct stopwatch timeout_sw;
/* One second is more than plenty for any EC operation to complete */
const uint64_t ec_status_timeout_us = 1 * USECS_PER_SEC;
/* Wait 1 usec between read attempts */
const uint64_t ec_status_read_period_us = 1;

stopwatch_init_usecs_expire(&timeout_sw, ec_status_timeout_us);
do {
if ((read_byte(port) & mask) == cond)
return 0;
udelay(ec_status_read_period_us);
} while (!stopwatch_expired(&timeout_sw));
return -1;
}

static int google_chromeec_wait_ready(u16 port)
Expand Down
2 changes: 1 addition & 1 deletion src/ec/google/wilco/mailbox.c
View file
Expand Up @@ -181,7 +181,7 @@ static int wilco_ec_transfer(struct wilco_ec_message *msg)
skip_size = (msg->type == WILCO_EC_MSG_DEFAULT) ? 1 : 0;

if (msg->response_size > rs.data_size - skip_size) {
printk(BIOS_ERR, "%s: data too short (%lu bytes, expected %zu)",
printk(BIOS_ERR, "%s: data too short (%zu bytes, expected %zu)",
__func__, rs.data_size - skip_size, msg->response_size);
return -1;
}
Expand Down
10 changes: 5 additions & 5 deletions src/ec/kontron/it8516e/ec.c
View file
Expand Up @@ -133,13 +133,13 @@ static void it8516e_set_fan_from_options(const config_t *const config,
u8 fan_max = config->default_fan_max[fan_idx];

fanX_mode[3] = '1' + fan_idx;
fan_mode = get_int_option(fanX_mode, fan_mode);
fan_mode = get_uint_option(fanX_mode, fan_mode);
if (!fan_mode)
fan_mode = IT8516E_MODE_AUTO;
it8516e_set_fan_mode(fan_idx, fan_mode);

fanX_target[3] = '1' + fan_idx;
fan_target = get_int_option(fanX_target, fan_target);
fan_target = get_uint_option(fanX_target, fan_target);
switch (fan_mode) {
case IT8516E_MODE_AUTO:
printk(BIOS_DEBUG,
Expand Down Expand Up @@ -173,8 +173,8 @@ static void it8516e_set_fan_from_options(const config_t *const config,

fanX_min[3] = '1' + fan_idx;
fanX_max[3] = '1' + fan_idx;
fan_min = get_int_option(fanX_min, fan_min);
fan_max = get_int_option(fanX_max, fan_max);
fan_min = get_uint_option(fanX_min, fan_min);
fan_max = get_uint_option(fanX_max, fan_max);

if (!fan_max || fan_max > 100) /* Constrain fan_max to 100% */
fan_max = 100;
Expand Down Expand Up @@ -202,7 +202,7 @@ static void it8516e_pm2_init(struct device *dev)
ec_set_ports(find_resource(dev, PNP_IDX_IO1)->base,
find_resource(dev, PNP_IDX_IO0)->base);

u8 systemp_type = get_int_option("systemp_type", config->default_systemp);
u8 systemp_type = get_uint_option("systemp_type", config->default_systemp);
if (systemp_type >= IT8516E_SYSTEMP_LASTPLUSONE)
systemp_type = IT8516E_SYSTEMP_NONE;
it8516e_set_systemp_type(systemp_type);
Expand Down
2 changes: 1 addition & 1 deletion src/ec/lenovo/h8/bluetooth.c
View file
Expand Up @@ -48,5 +48,5 @@ bool h8_has_bdc(const struct device *dev)
*/
bool h8_bluetooth_nv_enable(void)
{
return get_int_option("bluetooth", true);
return get_uint_option("bluetooth", true);
}
24 changes: 12 additions & 12 deletions src/ec/lenovo/h8/h8.c
View file
Expand Up @@ -243,7 +243,7 @@ static void h8_enable(struct device *dev)
reg8 = conf->config1;
if (conf->has_keyboard_backlight) {
/* Default to both backlights */
reg8 = (reg8 & 0xf3) | ((get_int_option("backlight", 0) & 0x3) << 2);
reg8 = (reg8 & 0xf3) | ((get_uint_option("backlight", 0) & 0x3) << 2);
}
ec_write(H8_CONFIG1, reg8);
ec_write(H8_CONFIG2, conf->config2);
Expand All @@ -253,14 +253,14 @@ static void h8_enable(struct device *dev)
beepmask1 = conf->beepmask1;

if (conf->has_power_management_beeps) {
if (get_int_option("power_management_beeps", 1) == 0) {
if (get_uint_option("power_management_beeps", 1) == 0) {
beepmask0 = 0x00;
beepmask1 = 0x00;
}
}

if (conf->has_power_management_beeps) {
if (get_int_option("low_battery_beep", 1))
if (get_uint_option("low_battery_beep", 1))
beepmask0 |= 2;
else
beepmask0 &= ~2;
Expand Down Expand Up @@ -292,15 +292,15 @@ static void h8_enable(struct device *dev)

ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);

h8_usb_always_on_enable(get_int_option("usb_always_on", 0));
h8_usb_always_on_enable(get_uint_option("usb_always_on", 0));

h8_wlan_enable(get_int_option("wlan", 1));
h8_wlan_enable(get_uint_option("wlan", 1));

h8_trackpoint_enable(1);
h8_usb_power_enable(1);

int volume = get_int_option("volume", -1);
if (volume >= 0 && !acpi_is_wakeup_s3())
unsigned int volume = get_uint_option("volume", ~0);
if (volume <= 0xff && !acpi_is_wakeup_s3())
ec_write(H8_VOLUME_CONTROL, volume);

val = (CONFIG(H8_SUPPORT_BT_ON_WIFI) || h8_has_bdc(dev)) &&
Expand All @@ -311,16 +311,16 @@ static void h8_enable(struct device *dev)
h8_wwan_enable(val);

if (conf->has_uwb)
h8_uwb_enable(get_int_option("uwb", 1));
h8_uwb_enable(get_uint_option("uwb", 1));

h8_fn_ctrl_swap(get_int_option("fn_ctrl_swap", 0));
h8_fn_ctrl_swap(get_uint_option("fn_ctrl_swap", 0));

h8_sticky_fn(get_int_option("sticky_fn", 0));
h8_sticky_fn(get_uint_option("sticky_fn", 0));

if (CONFIG(H8_HAS_PRIMARY_FN_KEYS))
f1_to_f12_as_primary(get_int_option("f1_to_f12_as_primary", 1));
f1_to_f12_as_primary(get_uint_option("f1_to_f12_as_primary", 1));

h8_charge_priority(get_int_option("first_battery", PRIMARY_BATTERY));
h8_charge_priority(get_uint_option("first_battery", PRIMARY_BATTERY));

h8_set_audio_mute(0);
h8_mb_init();
Expand Down
2 changes: 1 addition & 1 deletion src/ec/lenovo/h8/wwan.c
View file
Expand Up @@ -46,5 +46,5 @@ bool h8_has_wwan(const struct device *dev)
*/
bool h8_wwan_nv_enable(void)
{
return get_int_option("wwan", true);
return get_uint_option("wwan", true);
}
4 changes: 2 additions & 2 deletions src/ec/lenovo/pmh7/pmh7.c
View file
Expand Up @@ -117,9 +117,9 @@ static void enable_dev(struct device *dev)
pmh7_backlight_enable(conf->backlight_enable);
pmh7_dock_event_enable(conf->dock_event_enable);

pmh7_touchpad_enable(get_int_option("touchpad", 1));
pmh7_touchpad_enable(get_uint_option("touchpad", 1));

pmh7_trackpoint_enable(get_int_option("trackpoint", 1));
pmh7_trackpoint_enable(get_uint_option("trackpoint", 1));

printk(BIOS_INFO, "PMH7: ID %02x Revision %02x\n",
pmh7_register_read(EC_LENOVO_PMH7_REG_ID),
Expand Down
232 changes: 230 additions & 2 deletions src/include/acpi/acpi.h
View file
Expand Up @@ -71,8 +71,8 @@ enum coreboot_acpi_ids {

enum acpi_tables {
/* Tables defined by ACPI and used by coreboot */
BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG,
RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, DRTM,
BERT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, MADT,
MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, DRTM,
/* Additional proprietary tables used by coreboot */
VFCT, NHLT, SPMI, CRAT
};
Expand Down Expand Up @@ -208,6 +208,71 @@ typedef struct acpi_mcfg_mmconfig {
u8 reserved[4];
} __packed acpi_mcfg_mmconfig_t;

/*
* HMAT (Heterogeneous Memory Attribute Table)
* ACPI spec 6.4 section 5.2.27
*/
typedef struct acpi_hmat {
acpi_header_t header;
u32 resv;
/* Followed by HMAT table structure[n] */
} __packed acpi_hmat_t;

/* HMAT: Memory Proximity Domain Attributes structure */
typedef struct acpi_hmat_mpda {
u16 type; /* Type (0) */
u16 resv;
u32 length; /* Length in bytes (40) */
u16 flags;
u16 resv1;
u32 proximity_domain_initiator;
u32 proximity_domain_memory;
u32 resv2;
u64 resv3;
u64 resv4;
} __packed acpi_hmat_mpda_t;

/* HMAT: System Locality Latency and Bandwidth Information structure */
typedef struct acpi_hmat_sllbi {
u16 type; /* Type (1) */
u16 resv;
u32 length; /* Length in bytes */
u8 flags;
u8 data_type;
/*
* Transfer size defined as a 5-biased power of 2 exponent,
* when the bandwidth/latency value is achieved.
*/
u8 min_transfer_size;
u8 resv1;
u32 num_initiator_domains;
u32 num_target_domains;
u32 resv2;
u64 entry_base_unit;
/* Followed by initiator proximity domain list */
/* Followed by target proximity domain list */
/* Followed by latency / bandwidth values */
} __packed acpi_hmat_sllbi_t;

/* HMAT: Memory Side Cache Information structure */
typedef struct acpi_hmat_msci {
u16 type; /* Type (2) */
u16 resv;
u32 length; /* Length in bytes */
u32 domain; /* Proximity domain for the memory */
u32 resv1;
u64 cache_size;
/* Describes level, associativity, write policy, cache line size */
u32 cache_attributes;
u16 resv2;
/*
* Number of SMBIOS handlers that contribute to the
* memory side cache physical devices
*/
u16 num_handlers;
/* Followed by SMBIOS handlers*/
} __packed acpi_hmat_msci_t;

/* SRAT (System Resource Affinity Table) */
typedef struct acpi_srat {
acpi_header_t header;
Expand All @@ -216,6 +281,10 @@ typedef struct acpi_srat {
/* Followed by static resource allocation structure[n] */
} __packed acpi_srat_t;

#define ACPI_SRAT_STRUCTURE_LAPIC 0
#define ACPI_SRAT_STRUCTURE_MEM 1
#define ACPI_SRAT_STRUCTURE_GIA 5

/* SRAT: Processor Local APIC/SAPIC Affinity Structure */
typedef struct acpi_srat_lapic {
u8 type; /* Type (0) */
Expand Down Expand Up @@ -245,6 +314,21 @@ typedef struct acpi_srat_mem {
u32 resv2[2];
} __packed acpi_srat_mem_t;

/* SRAT: Generic Initiator Affinity Structure (ACPI spec 6.4 section 5.2.16.6) */
typedef struct acpi_srat_gia {
u8 type; /* Type (5) */
u8 length; /* Length in bytes (32) */
u8 resv;
u8 dev_handle_type; /* Device handle type */
u32 proximity_domain; /*Proximity domain */
u8 dev_handle[16]; /* Device handle */
u32 flags;
u32 resv1;
} __packed acpi_srat_gia_t;

#define ACPI_SRAT_GIA_DEV_HANDLE_ACPI 0
#define ACPI_SRAT_GIA_DEV_HANDLE_PCI 1

/* SLIT (System Locality Distance Information Table) */
typedef struct acpi_slit {
acpi_header_t header;
Expand Down Expand Up @@ -1024,6 +1108,134 @@ struct acpi_spmi {
u8 reserved3;
} __packed;

/* EINJ APEI Standard Definitions */
/* EINJ Error Types
Refer to the ACPI spec, EINJ section, for more info on bit definitions
*/
#define ACPI_EINJ_CPU_CE (1 << 0)
#define ACPI_EINJ_CPU_UCE (1 << 1)
#define ACPI_EINJ_CPU_UCE_FATAL (1 << 2)
#define ACPI_EINJ_MEM_CE (1 << 3)
#define ACPI_EINJ_MEM_UCE (1 << 4)
#define ACPI_EINJ_MEM_UCE_FATAL (1 << 5)
#define ACPI_EINJ_PCIE_CE (1 << 6)
#define ACPI_EINJ_PCIE_UCE_NON_FATAL (1 << 7)
#define ACPI_EINJ_PCIE_UCE_FATAL (1 << 8)
#define ACPI_EINJ_PLATFORM_CE (1 << 9)
#define ACPI_EINJ_PLATFORM_UCE (1 << 10)
#define ACPI_EINJ_PLATFORM_UCE_FATAL (1 << 11)
#define ACPI_EINJ_VENDOR_DEFINED (1 << 31)
#define ACPI_EINJ_DEFAULT_CAP (ACPI_EINJ_MEM_CE | ACPI_EINJ_MEM_UCE | \
ACPI_EINJ_PCIE_CE | ACPI_EINJ_PCIE_UCE_FATAL)

/* EINJ actions */
#define ACTION_COUNT 9
#define BEGIN_INJECT_OP 0x00
#define GET_TRIGGER_ACTION_TABLE 0x01
#define SET_ERROR_TYPE 0x02
#define GET_ERROR_TYPE 0x03
#define END_INJECT_OP 0x04
#define EXECUTE_INJECT_OP 0x05
#define CHECK_BUSY_STATUS 0x06
#define GET_CMD_STATUS 0x07
#define SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define TRIGGER_ERROR 0xFF

/* EINJ Instructions */
#define READ_REGISTER 0x00
#define READ_REGISTER_VALUE 0x01
#define WRITE_REGISTER 0x02
#define WRITE_REGISTER_VALUE 0x03
#define NO_OP 0x04

/* EINJ (Error Injection Table) */
typedef struct acpi_gen_regaddr1 {
u8 space_id; /* Address space ID */
u8 bit_width; /* Register size in bits */
u8 bit_offset; /* Register bit offset */
u8 access_size; /* Access size since ACPI 2.0c */
u64 addr; /* Register address */
} __packed acpi_addr64_t;

/* Instruction entry */
typedef struct acpi_einj_action_table {
u8 action;
u8 instruction;
u16 flags;
acpi_addr64_t reg;
u64 value;
u64 mask;
} __packed acpi_einj_action_table_t;

typedef struct acpi_injection_header {
u32 einj_header_size;
u32 flags;
u32 entry_count;
} __packed acpi_injection_header_t;

typedef struct acpi_einj_trigger_table {
u32 header_size;
u32 revision;
u32 table_size;
u32 entry_count;
acpi_einj_action_table_t trigger_action[1];
} __packed acpi_einj_trigger_table_t;

typedef struct set_error_type {
u32 errtype;
u32 vendorerrortype;
u32 flags;
u32 apicid;
u64 memaddr;
u64 memrange;
u32 pciesbdf;
} __packed set_error_type_t;

#define EINJ_PARAM_NUM 6
typedef struct acpi_einj_smi {
u64 op_state;
u64 err_inject[EINJ_PARAM_NUM];
u64 trigger_action_table;
u64 err_inj_cap;
u64 op_status;
u64 cmd_sts;
u64 einj_addr;
u64 einj_addr_msk;
set_error_type_t setaddrtable;
u64 reserved[50];
} __packed acpi_einj_smi_t;

/* EINJ Flags */
#define EINJ_DEF_TRIGGER_PORT 0xb2
#define FLAG_PRESERVE 0x01
#define FLAG_IGNORE 0x00

/* EINJ Registers */
#define EINJ_REG_MEMORY(address) \
{ \
.space_id = ACPI_ADDRESS_SPACE_MEMORY, \
.bit_width = 64, \
.bit_offset = 0, \
.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
.addr = address}

#define EINJ_REG_IO() \
{ \
.space_id = ACPI_ADDRESS_SPACE_IO, \
.bit_width = 0x10, \
.bit_offset = 0, \
.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS, \
.addr = EINJ_DEF_TRIGGER_PORT} /* HW dependent code can override this also */

typedef struct acpi_einj {
acpi_header_t header;
acpi_injection_header_t inj_header;
acpi_einj_action_table_t action_table[ACTION_COUNT];
} __packed acpi_einj_t;


void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions);

unsigned long fw_cfg_acpi_tables(unsigned long start);

/* These are implemented by the target port or north/southbridge. */
Expand Down Expand Up @@ -1069,6 +1281,12 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic);
int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
u32 flags);
/*
* Given the Generic Initiator device's BDF, the proximity domain's ID
* and flag, create Generic Initiator Affinity structure in SRAT.
*/
int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain,
u16 seg, u8 bus, u8 dev, u8 func, u32 flags);
int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base,
u16 seg_nr, u8 start, u8 end);
unsigned long acpi_create_srat_lapics(unsigned long current);
Expand All @@ -1078,6 +1296,16 @@ void acpi_create_srat(acpi_srat_t *srat,
void acpi_create_slit(acpi_slit_t *slit,
unsigned long (*acpi_fill_slit)(unsigned long current));

/*
* Create a Memory Proximity Domain Attributes structure for HMAT,
* given proximity domain for the attached initiaor, and
* proximimity domain for the memory.
*/
int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory);
/* Create Heterogenous Memory Attribute Table */
void acpi_create_hmat(acpi_hmat_t *hmat,
unsigned long (*acpi_fill_hmat)(unsigned long current));

void acpi_create_vfct(const struct device *device,
acpi_vfct_t *vfct,
unsigned long (*acpi_fill_vfct)(const struct device *device,
Expand Down
3 changes: 0 additions & 3 deletions src/include/acpi/acpi_gnvs.h
View file
Expand Up @@ -17,9 +17,6 @@ static inline void *acpi_get_gnvs(void) { return NULL; }
static inline int acpi_reset_gnvs_for_wake(struct global_nvs **gnvs) { return -1; }
#endif

void gnvs_assign_chromeos(void *gnvs_section);
void gnvs_set_ecfw_rw(void);

/*
* These functions populate the gnvs structure in acpi table.
* Defined as weak in common acpi as gnvs structure definition is
Expand Down
5 changes: 5 additions & 0 deletions src/include/acpi/acpigen.h
View file
Expand Up @@ -338,6 +338,11 @@ inline void acpigen_write_device_end(void)
{
acpigen_pop_len();
}
void acpigen_write_thermal_zone(const char *name);
inline void acpigen_write_thermal_zone_end(void)
{
acpigen_pop_len();
}
void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries);
void acpigen_write_PPC(u8 nr);
void acpigen_write_PPC_NVS(void);
Expand Down
60 changes: 37 additions & 23 deletions src/include/console/post_codes.h
View file
Expand Up @@ -104,6 +104,21 @@
*/
#define POST_ENABLING_CACHE 0x60

/**
* \brief Pre call to RAM stage main()
*
* POSTed right before RAM stage main() is called from c_start.S
*/
#define POST_PRE_HARDWAREMAIN 0x6e

/**
* \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
*/
#define POST_ENTRY_HARDWAREMAIN 0x6f

/**
* \brief Before Device Probe
*
Expand Down Expand Up @@ -174,21 +189,6 @@
*/
#define POST_BS_WRITE_TABLES 0x79

/**
* \brief Pre call to RAM stage main()
*
* POSTed right before RAM stage main() is called from c_start.S
*/
#define POST_PRE_HARDWAREMAIN 0x79

/**
* \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
*/
#define POST_ENTRY_RAMSTAGE 0x80

/**
* \brief Load Payload
*
Expand All @@ -204,16 +204,16 @@
#define POST_BS_PAYLOAD_BOOT 0x7b

/**
* \brief Before calling FSP Notify before End of Firmware
* \brief Before calling FSP Notify (end of firmware)
*
* Going to call into FSP binary for Notify phase
* Going to call into FSP binary for Notify phase (end of firmware)
*/
#define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88

/**
* \brief Before calling FSP Notify after End of Firmware
* \brief After calling FSP Notify (end of firmware)
*
* Going to call into FSP binary for Notify phase
* Going to call into FSP binary for Notify phase (end of firmware)
*/
#define POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89

Expand Down Expand Up @@ -246,16 +246,16 @@
#define POST_FSP_SILICON_INIT 0x93

/**
* \brief Before calling FSP Notify before resource allocation
* \brief Before calling FSP Notify (after PCI enumeration)
*
* Going to call into FSP binary for Notify phase
* Going to call into FSP binary for Notify phase (after PCI enumeration)
*/
#define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94

/**
* \brief Before calling FSP Notify before finalize
* \brief Before calling FSP Notify (ready to boot)
*
* Going to call into FSP binary for Notify phase
* Going to call into FSP binary for Notify phase (ready to boot)
*/
#define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95

Expand Down Expand Up @@ -301,6 +301,20 @@
*/
#define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1

/**
* \brief After calling FSP Notify (after PCI enumeration)
*
* Going to call into FSP binary for Notify phase (after PCI enumeration)
*/
#define POST_FSP_NOTIFY_AFTER_ENUMERATE 0xa2

/**
* \brief After calling FSP Notify (ready to boot)
*
* Going to call into FSP binary for Notify phase (ready to boot)
*/
#define POST_FSP_NOTIFY_AFTER_FINALIZE 0xa3

/**
* \brief Invalid or corrupt ROM
*
Expand Down
6 changes: 3 additions & 3 deletions src/include/cpu/x86/lapic.h
View file
Expand Up @@ -12,7 +12,7 @@ static inline bool is_x2apic_mode(void)
{
msr_t msr;
msr = rdmsr(LAPIC_BASE_MSR);
return (msr.lo & LAPIC_BASE_MSR_X2APIC_MODE);
return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED);
}

static inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid)
Expand Down Expand Up @@ -79,8 +79,8 @@ static inline void disable_lapic(void)
static __always_inline unsigned int initial_lapicid(void)
{
uint32_t lapicid;
if (is_x2apic_mode())
lapicid = lapic_read(LAPIC_ID);
if (is_x2apic_mode() && cpuid_get_max_func() >= 0xb)
lapicid = cpuid_ext(0xb, 0).edx;
else
lapicid = cpuid_ebx(1) >> 24;
return lapicid;
Expand Down
2 changes: 2 additions & 0 deletions src/include/cpu/x86/lapic_def.h
View file
Expand Up @@ -5,6 +5,8 @@
#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
#define LAPIC_BASE_MSR_X2APIC_MODE (1 << 10)
#define LAPIC_BASE_MSR_ENABLE (1 << 11)
#define LAPIC_BASE_X2APIC_ENABLED \
(LAPIC_BASE_MSR_X2APIC_MODE | LAPIC_BASE_MSR_ENABLE)
#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000

#ifndef LOCAL_APIC_ADDR
Expand Down
26 changes: 26 additions & 0 deletions src/include/cpu/x86/msr.h
View file
Expand Up @@ -300,6 +300,32 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
return MCA_ERRTYPE_UNKNOWN;
}

/**
* Helper for reading a MSR
*
* @param[in] reg The MSR.
*/
static inline uint64_t msr_read(unsigned int reg)
{
msr_t msr = rdmsr(reg);
return (((uint64_t)msr.hi << 32) | msr.lo);
}

/**
* Helper for writing a MSR
*
* @param[in] reg The MSR.
* @param[in] value The value to be written to the MSR.
*/
static inline void msr_write(unsigned int reg, uint64_t value)
{
msr_t msr = {
.lo = (unsigned int)value,
.hi = (unsigned int)(value >> 32)
};
wrmsr(reg, msr);
}

/**
* Helper for (un)setting MSR bitmasks
*
Expand Down
12 changes: 1 addition & 11 deletions src/include/device/device.h
View file
Expand Up @@ -168,12 +168,6 @@ extern struct bus *free_links;

extern const char mainboard_name[];

#if CONFIG(GFXUMA)
/* IGD UMA memory */
extern uint64_t uma_memory_base;
extern uint64_t uma_memory_size;
#endif

/* Generic device interface functions */
struct device *alloc_dev(struct bus *parent, struct device_path *path);
void dev_initialize_chips(void);
Expand All @@ -197,11 +191,7 @@ void dev_set_enabled(struct device *dev, int enable);
void disable_children(struct bus *bus);
bool dev_is_active_bridge(struct device *dev);
void add_more_links(struct device *dev, unsigned int total_links);

static inline bool is_dev_enabled(const struct device *const dev)
{
return dev && dev->enabled;
}
bool is_dev_enabled(const struct device *const dev);

/* Option ROM helper functions */
void run_bios(struct device *dev, unsigned long addr);
Expand Down
120 changes: 66 additions & 54 deletions src/include/device/pci_ids.h
View file
Expand Up @@ -2851,17 +2851,21 @@
#define PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER 0xa24b
#define PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER 0xa24c
#define PCI_DEVICE_ID_INTEL_EMB_SUPER 0x1b81
#define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4
#define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5
#define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6
#define PCI_DEVICE_ID_INTEL_KBP_H_Q250 0xa2c7
#define PCI_DEVICE_ID_INTEL_KBP_H_B250 0xa2c8
#define PCI_DEVICE_ID_INTEL_UPT_H_H270 0xa2c4
#define PCI_DEVICE_ID_INTEL_UPT_H_Z270 0xa2c5
#define PCI_DEVICE_ID_INTEL_UPT_H_Q270 0xa2c6
#define PCI_DEVICE_ID_INTEL_UPT_H_Q250 0xa2c7
#define PCI_DEVICE_ID_INTEL_UPT_H_B250 0xa2c8
#define PCI_DEVICE_ID_INTEL_UPT_H_Z370 0xa2c9
#define PCI_DEVICE_ID_INTEL_UPT_H_H310C 0xa2ca
#define PCI_DEVICE_ID_INTEL_UPT_H_B365 0xa2cc
#define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22 0x9d4b
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22 0x9d4e
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22 0x9d50
#define PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU 0x9d51
#define PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM 0x9d58
#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56
#define PCI_DEVICE_ID_INTEL_UPT_LP_SUPER_SKU 0x9d51
#define PCI_DEVICE_ID_INTEL_UPT_LP_U_BASE 0x9d53
#define PCI_DEVICE_ID_INTEL_UPT_LP_U_PREMIUM 0x9d58
#define PCI_DEVICE_ID_INTEL_UPT_LP_Y_PREMIUM 0x9d56
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8
#define PCI_DEVICE_ID_INTEL_GLK_ESPI 0x3197
Expand Down Expand Up @@ -3132,30 +3136,30 @@
#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER 0xa269
#define PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER 0xa26a

#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 0xa290
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2 0xa291
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3 0xa292
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4 0xa293
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5 0xa294
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6 0xa295
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7 0xa296
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8 0xa297
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9 0xa298
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10 0xa299
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11 0xa29a
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12 0xa29b
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13 0xa29c
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14 0xa29d
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15 0xa29e
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16 0xa29f
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17 0xa2e7
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18 0xa2e8
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19 0xa2e9
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20 0xa2ea
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21 0xa2eb
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22 0xa2ec
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23 0xa2ed
#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24 0xa2ee
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP1 0xa290
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP2 0xa291
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP3 0xa292
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP4 0xa293
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP5 0xa294
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP6 0xa295
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP7 0xa296
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP8 0xa297
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP9 0xa298
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP10 0xa299
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP11 0xa29a
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP12 0xa29b
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP13 0xa29c
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP14 0xa29d
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP15 0xa29e
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP16 0xa29f
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP17 0xa2e7
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP18 0xa2e8
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP19 0xa2e9
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP20 0xa2ea
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP21 0xa2eb
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP22 0xa2ec
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP23 0xa2ed
#define PCI_DEVICE_ID_INTEL_UPT_H_PCIE_RP24 0xa2ee

#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1 0x9db8
#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2 0x9db9
Expand Down Expand Up @@ -3421,7 +3425,7 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_PMC 0xa121
#define PCI_DEVICE_ID_INTEL_LWB_PMC 0xa1a1
#define PCI_DEVICE_ID_INTEL_LWB_PMC_SUPER 0xa221
#define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa2a1
#define PCI_DEVICE_ID_INTEL_UPT_H_PMC 0xa2a1
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1
Expand All @@ -3445,10 +3449,10 @@
#define PCI_DEVICE_ID_INTEL_SPT_I2C3 0x9d63
#define PCI_DEVICE_ID_INTEL_SPT_I2C4 0x9d64
#define PCI_DEVICE_ID_INTEL_SPT_I2C5 0x9d65
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C0 0xa2e0
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C1 0xa2e1
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C2 0xa2e2
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C3 0xa2e3
#define PCI_DEVICE_ID_INTEL_UPT_H_I2C0 0xa2e0
#define PCI_DEVICE_ID_INTEL_UPT_H_I2C1 0xa2e1
#define PCI_DEVICE_ID_INTEL_UPT_H_I2C2 0xa2e2
#define PCI_DEVICE_ID_INTEL_UPT_H_I2C3 0xa2e3
#define PCI_DEVICE_ID_INTEL_APL_I2C0 0x5aac
#define PCI_DEVICE_ID_INTEL_APL_I2C1 0x5aae
#define PCI_DEVICE_ID_INTEL_APL_I2C2 0x5ab0
Expand Down Expand Up @@ -3545,9 +3549,9 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_UART0 0xa127
#define PCI_DEVICE_ID_INTEL_SPT_H_UART1 0xa128
#define PCI_DEVICE_ID_INTEL_SPT_H_UART2 0xa166
#define PCI_DEVICE_ID_INTEL_KBP_H_UART0 0xa2a7
#define PCI_DEVICE_ID_INTEL_KBP_H_UART1 0xa2a8
#define PCI_DEVICE_ID_INTEL_KBP_H_UART2 0xa2e6
#define PCI_DEVICE_ID_INTEL_UPT_H_UART0 0xa2a7
#define PCI_DEVICE_ID_INTEL_UPT_H_UART1 0xa2a8
#define PCI_DEVICE_ID_INTEL_UPT_H_UART2 0xa2e6
#define PCI_DEVICE_ID_INTEL_APL_UART0 0x5abc
#define PCI_DEVICE_ID_INTEL_APL_UART1 0x5abe
#define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0
Expand Down Expand Up @@ -3788,6 +3792,7 @@
#define PCI_DEVICE_ID_INTEL_EHL_GT1_1 0x4541
#define PCI_DEVICE_ID_INTEL_EHL_GT2_1 0x4540
#define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551
#define PCI_DEVICE_ID_INTEL_EHL_GT1_2_1 0x4555
#define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550
#define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571
#define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570
Expand All @@ -3808,6 +3813,9 @@
#define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618
#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619
#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0
#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1 0x46b0
#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_2 0x46a1
#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_3 0x46a3
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0

Expand Down Expand Up @@ -3869,18 +3877,21 @@
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12
#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532
#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
#define PCI_DEVICE_ID_INTEL_EHL_ID_2 0x4522
#define PCI_DEVICE_ID_INTEL_EHL_ID_3 0x4524
#define PCI_DEVICE_ID_INTEL_EHL_ID_4 0x4512
#define PCI_DEVICE_ID_INTEL_EHL_ID_5 0x4526
#define PCI_DEVICE_ID_INTEL_EHL_ID_6 0x4514
#define PCI_DEVICE_ID_INTEL_EHL_ID_7 0x4528
#define PCI_DEVICE_ID_INTEL_EHL_ID_8 0x452A
#define PCI_DEVICE_ID_INTEL_EHL_ID_9 0x4516
#define PCI_DEVICE_ID_INTEL_EHL_ID_10 0x452C
#define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x452E
#define PCI_DEVICE_ID_INTEL_EHL_ID_0 0x4510
#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4522
#define PCI_DEVICE_ID_INTEL_EHL_ID_1A 0x4538
#define PCI_DEVICE_ID_INTEL_EHL_ID_2 0x4524
#define PCI_DEVICE_ID_INTEL_EHL_ID_2_1 0x453A
#define PCI_DEVICE_ID_INTEL_EHL_ID_3 0x4512
#define PCI_DEVICE_ID_INTEL_EHL_ID_3A 0x451E
#define PCI_DEVICE_ID_INTEL_EHL_ID_4 0x4526
#define PCI_DEVICE_ID_INTEL_EHL_ID_5 0x4514
#define PCI_DEVICE_ID_INTEL_EHL_ID_6 0x4528
#define PCI_DEVICE_ID_INTEL_EHL_ID_7 0x452A
#define PCI_DEVICE_ID_INTEL_EHL_ID_8 0x4516
#define PCI_DEVICE_ID_INTEL_EHL_ID_9 0x452C
#define PCI_DEVICE_ID_INTEL_EHL_ID_10 0x452E
#define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x4532
#define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518
#define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A
#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22
Expand All @@ -3904,7 +3915,7 @@
#define PCI_DEVICE_ID_INTEL_ADL_S_ID_13 0x4673
#define PCI_DEVICE_ID_INTEL_ADL_S_ID_14 0x4623
#define PCI_DEVICE_ID_INTEL_ADL_S_ID_15 0x0060
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4602
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4629
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_2 0x460a
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_3 0x4641
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_4 0x4649
Expand All @@ -3913,6 +3924,7 @@
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661
#define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f
#define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22
#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22
Expand Down Expand Up @@ -3948,7 +3960,7 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f
#define PCI_DEVICE_ID_INTEL_LWB_XHCI 0xa1af
#define PCI_DEVICE_ID_INTEL_LWB_XHCI_SUPER 0xa22f
#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af
#define PCI_DEVICE_ID_INTEL_UPT_H_XHCI 0xa2af
#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded
#define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d
#define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed
Expand Down
2 changes: 1 addition & 1 deletion src/include/device/pci_ops.h
View file
Expand Up @@ -215,6 +215,6 @@ u16 pci_find_capability(const struct device *dev, u16 cap)
*
* Returns true if PCI device is wake source, false otherwise.
*/
bool pci_dev_is_wake_source(const struct device *dev);
bool pci_dev_is_wake_source(pci_devfn_t dev);

#endif /* PCI_OPS_H */
19 changes: 19 additions & 0 deletions src/include/fw_config.h
View file
Expand Up @@ -70,6 +70,16 @@ bool fw_config_is_provisioned(void);
*/
const struct fw_config *fw_config_get_found(uint64_t field_mask);

/**
* fw_config_probe_dev() - Check if any of the probe conditions are true for given device.
* @dev: Device for which probe conditions are checked
* @matching_probe: If any probe condition match, then the matching probe condition is returned
* to the caller.
* Return %true if device has no probing conditions or if a matching probe condition is
* encountered, %false otherwise.
*/
bool fw_config_probe_dev(const struct device *dev, const struct fw_config **matching_probe);

#else

static inline bool fw_config_probe(const struct fw_config *match)
Expand All @@ -78,6 +88,15 @@ static inline bool fw_config_probe(const struct fw_config *match)
return true;
}

static inline bool fw_config_probe_dev(const struct device *dev,
const struct fw_config **matching_probe)
{
/* Always return true when probing with disabled fw_config. */
if (matching_probe)
*matching_probe = NULL;
return true;
}

#endif /* CONFIG(FW_CONFIG) */

#endif /* __FW_CONFIG__ */
1 change: 0 additions & 1 deletion src/include/lib.h
View file
Expand Up @@ -29,7 +29,6 @@ int checkstack(void *top_of_stack, int core);
* https://packages.debian.org/jessie/amd64/vim-common/filelist
*/
void hexdump(const void *memory, size_t length);
void hexdump32(char LEVEL, const void *d, size_t len);

/*
* hexstrtobin - Turn a string of ASCII hex characters into binary
Expand Down
1 change: 0 additions & 1 deletion src/include/metadata_hash.h
View file
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _METADATA_HASH_H_
#define _METADATA_HASH_H_
Expand Down
26 changes: 12 additions & 14 deletions src/include/option.h
View file
Expand Up @@ -7,25 +7,23 @@

void sanitize_cmos(void);

enum cb_err cmos_set_option(const char *name, void *val);
enum cb_err cmos_get_option(void *dest, const char *name);
#if !CONFIG(USE_OPTION_TABLE)

static inline enum cb_err set_int_option(const char *name, int value)
static inline unsigned int get_uint_option(const char *name, const unsigned int fallback)
{
if (CONFIG(USE_OPTION_TABLE))
return cmos_set_option(name, &value);

return CB_CMOS_OTABLE_DISABLED;
return fallback;
}

static inline int get_int_option(const char *name, const int fallback)
static inline enum cb_err set_uint_option(const char *name, unsigned int value)
{
if (CONFIG(USE_OPTION_TABLE)) {
int value = 0;
if (cmos_get_option(&value, name) == CB_SUCCESS)
return value;
}
return fallback;
return CB_CMOS_OTABLE_DISABLED;
}

#else /* USE_OPTION_TABLE */

unsigned int get_uint_option(const char *name, const unsigned int fallback);
enum cb_err set_uint_option(const char *name, unsigned int value);

#endif /* USE_OPTION_TABLE? */

#endif /* _OPTION_H_ */
11 changes: 0 additions & 11 deletions src/lib/Kconfig
View file
Expand Up @@ -98,14 +98,3 @@ config NO_CBFS_MCACHE
the associated CAR/SRAM size. In that case every single CBFS file
lookup must re-read the same CBFS directory entries from flash to find
the respective file.

config CBFS_MCACHE_RW_PERCENTAGE
int
depends on VBOOT && !NO_CBFS_MCACHE
default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only
default 50
help
The amount of the CBFS_MCACHE area that's used for the RW CBFS, in
percent from 0 to 100. The remaining area will be used for the RO
CBFS. Default is an even 50/50 split. When VBOOT is disabled, this
will automatically be 0 (meaning the whole MCACHE is used for RO).
7 changes: 7 additions & 0 deletions src/lib/bootblock.c
View file
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
#include <arch/exception.h>
#include <bootblock_common.h>
#include <console/console.h>
Expand All @@ -8,6 +9,7 @@
#include <option.h>
#include <post.h>
#include <program_loading.h>
#include <security/tpm/tspi.h>
#include <symbols.h>
#include <timestamp.h>

Expand Down Expand Up @@ -56,6 +58,11 @@ void bootblock_main_with_timestamp(uint64_t base_timestamp,
bootblock_soc_init();
bootblock_mainboard_init();

if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK)) {
int s3resume = acpi_is_wakeup_s3();
tpm_setup(s3resume);
}

timestamp_add_now(TS_END_BOOTBLOCK);

run_romstage();
Expand Down
11 changes: 5 additions & 6 deletions src/lib/coreboot_table.c
View file
Expand Up @@ -467,12 +467,11 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
lb_mainboard(head);

/* Record the serial ports and consoles */
#if CONFIG(CONSOLE_SERIAL)
uart_fill_lb(head);
#endif
#if CONFIG(CONSOLE_USB)
lb_add_console(LB_TAG_CONSOLE_EHCI, head);
#endif
if (CONFIG(CONSOLE_SERIAL))
uart_fill_lb(head);

if (CONFIG(CONSOLE_USB))
lb_add_console(LB_TAG_CONSOLE_EHCI, head);

/* Record our various random string information */
lb_strings(head);
Expand Down
45 changes: 32 additions & 13 deletions src/lib/fw_config.c
View file
Expand Up @@ -50,6 +50,10 @@ uint64_t fw_config_get(void)

bool fw_config_probe(const struct fw_config *match)
{
/* If fw_config is not provisioned, then there is nothing to match. */
if (!fw_config_is_provisioned())
return false;

/* Compare to system value. */
if ((fw_config_get() & match->mask) == match->value) {
if (match->field_name && match->option_name)
Expand All @@ -70,6 +74,29 @@ bool fw_config_is_provisioned(void)
return fw_config_get() != UNDEFINED_FW_CONFIG;
}

bool fw_config_probe_dev(const struct device *dev, const struct fw_config **matching_probe)
{
const struct fw_config *probe;

if (matching_probe)
*matching_probe = NULL;

/* If the device does not have a probe list, then probing is not required. */
if (!dev->probe_list)
return true;

for (probe = dev->probe_list; probe && probe->mask != 0; probe++) {
if (!fw_config_probe(probe))
continue;

if (matching_probe)
*matching_probe = probe;
return true;
}

return false;
}

#if ENV_RAMSTAGE

/*
Expand Down Expand Up @@ -111,23 +138,15 @@ static void fw_config_init(void *unused)

for (dev = all_devices; dev; dev = dev->next) {
const struct fw_config *probe;
bool match = false;

if (!dev->probe_list)
continue;

for (probe = dev->probe_list; probe && probe->mask != 0; probe++) {
if (fw_config_probe(probe)) {
match = true;
cached_configs[probe_index(probe->mask)] = probe;
break;
}
}

if (!match) {
if (!fw_config_probe_dev(dev, &probe)) {
printk(BIOS_INFO, "%s disabled by fw_config\n", dev_path(dev));
dev->enabled = 0;
continue;
}

if (probe)
cached_configs[probe_index(probe->mask)] = probe;
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL);
Expand Down
2 changes: 1 addition & 1 deletion src/lib/hardwaremain.c
View file
Expand Up @@ -442,7 +442,7 @@ void main(void)
cbmem_initialize();

timestamp_add_now(TS_START_RAMSTAGE);
post_code(POST_ENTRY_RAMSTAGE);
post_code(POST_ENTRY_HARDWAREMAIN);

/* Handoff sleep type from romstage. */
acpi_is_wakeup_s3();
Expand Down
18 changes: 0 additions & 18 deletions src/lib/hexdump.c
View file
Expand Up @@ -48,21 +48,3 @@ void hexdump(const void *memory, size_t length)
}
}
}

void hexdump32(char LEVEL, const void *d, size_t len)
{
size_t count = 0;

while (len > 0) {
if (count % 8 == 0) {
printk(LEVEL, "\n");
printk(LEVEL, "%p:", d);
}
printk(LEVEL, " 0x%08lx", *(unsigned long *)d);
count++;
len--;
d += 4;
}

printk(LEVEL, "\n\n");
}
1 change: 0 additions & 1 deletion src/lib/metadata_hash.c
View file
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <assert.h>
#include <metadata_hash.h>
Expand Down
5 changes: 3 additions & 2 deletions src/mainboard/amd/bilby/devicetree.cb
View file
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only

chip soc/amd/picasso
register "acp_pin_cfg" = "I2S_PINS_MAX_HDA"
# ACP Configuration
register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA"

# Set FADT Configuration
register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
Expand Down Expand Up @@ -119,7 +120,7 @@ chip soc/amd/picasso
.io_mode = ESPI_IO_MODE_SINGLE,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.dedicated_alert_pin = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 0,
.vw_ch_en = 0,
.oob_ch_en = 0,
Expand Down
7 changes: 0 additions & 7 deletions src/mainboard/amd/inagua/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -33,11 +32,5 @@
//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE

//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
9 changes: 6 additions & 3 deletions src/mainboard/amd/majolica/devicetree.cb
View file
Expand Up @@ -2,18 +2,21 @@

chip soc/amd/cezanne
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN | ESPI_DECODE_IO_0x80_EN
| ESPI_DECODE_IO_0X2E_0X2F_EN,
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN,
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
.crc_check_enable = 1,
.dedicated_alert_pin = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 1,
.flash_ch_en = 0,
}"

register "s0ix_enable" = "true"

register "pspp_policy" = "DXIO_PSPP_BALANCED"

device domain 0 on
device ref gpp_gfx_bridge_0 on end # MXM
device ref gpp_bridge_0 on end # NVMe
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/majolica/mainboard.c
View file
Expand Up @@ -52,7 +52,7 @@ static const struct fch_irq_routing {
{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
{ PIRQ_SATA, PIRQ_NC, PIRQ_NC },
{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
{ PIRQ_GPIO, PIRQ_NC, PIRQ_NC },
{ PIRQ_GPIO, 7, 7 },
{ PIRQ_I2C2, PIRQ_NC, PIRQ_NC },
{ PIRQ_I2C3, PIRQ_NC, PIRQ_NC },
{ PIRQ_UART0, 4, 4 },
Expand Down
5 changes: 3 additions & 2 deletions src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
View file
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only

chip soc/amd/picasso
register "acp_pin_cfg" = "I2S_PINS_MAX_HDA"
# ACP Configuration
register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA"

# Set FADT Configuration
register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
Expand Down Expand Up @@ -119,7 +120,7 @@ chip soc/amd/picasso
.io_mode = ESPI_IO_MODE_SINGLE,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.dedicated_alert_pin = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 0,
.vw_ch_en = 0,
.oob_ch_en = 0,
Expand Down
5 changes: 3 additions & 2 deletions src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
View file
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only

chip soc/amd/picasso
register "acp_pin_cfg" = "I2S_PINS_MAX_HDA"
# ACP Configuration
register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA"

# Set FADT Configuration
register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
Expand Down Expand Up @@ -119,7 +120,7 @@ chip soc/amd/picasso
.io_mode = ESPI_IO_MODE_SINGLE,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.dedicated_alert_pin = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 0,
.vw_ch_en = 0,
.oob_ch_en = 0,
Expand Down
8 changes: 0 additions & 8 deletions src/mainboard/amd/olivehill/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -35,12 +34,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
8 changes: 0 additions & 8 deletions src/mainboard/amd/parmer/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -35,12 +34,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
7 changes: 0 additions & 7 deletions src/mainboard/amd/persimmon/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -33,11 +32,5 @@
//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE

//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
7 changes: 0 additions & 7 deletions src/mainboard/amd/south_station/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -33,11 +32,5 @@
//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE

//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
8 changes: 0 additions & 8 deletions src/mainboard/amd/thatcher/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -35,12 +34,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
7 changes: 0 additions & 7 deletions src/mainboard/amd/union_station/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -33,11 +32,5 @@
//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_ASSERT_ENABLED TRUE

//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
2 changes: 1 addition & 1 deletion src/mainboard/aopen/dxplplusu/acpi_tables.c
View file
Expand Up @@ -44,7 +44,7 @@ unsigned long acpi_fill_madt(unsigned long current)

/* P64H2 Bus A IOAPIC */
if (bdev)
dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0));
dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/apple/macbook21/Kconfig
View file
Expand Up @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select USE_OPTION_TABLE
select I945_LVDS

config MAINBOARD_DIR
Expand Down
6 changes: 3 additions & 3 deletions src/mainboard/apple/macbookair4_2/devicetree.cb
View file
Expand Up @@ -13,17 +13,17 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_down_delay" = "500"
register "gpu_panel_power_up_delay" = "2000"
register "gpu_pch_backlight" = "0x13121312"
device cpu_cluster 0x0 on
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0 on end
device lapic 0xacac off end
end
end

device domain 0x0 on
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
Expand Down
10 changes: 0 additions & 10 deletions src/mainboard/asrock/b75pro3-m/acpi_tables.c
View file

This file was deleted.

6 changes: 3 additions & 3 deletions src/mainboard/asrock/b75pro3-m/devicetree.cb
View file
Expand Up @@ -13,16 +13,16 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_down_delay" = "0"
register "gpu_panel_power_up_delay" = "0"
register "gpu_pch_backlight" = "0x00000000"
device cpu_cluster 0x0 on
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0 on end
device lapic 0xacac off end
end
end
device domain 0x0 on
device domain 0 on
device pci 00.0 on
subsystemid 0x1849 0x0150
end
Expand Down
10 changes: 0 additions & 10 deletions src/mainboard/asrock/b85m_pro4/acpi_tables.c
View file

This file was deleted.

8 changes: 0 additions & 8 deletions src/mainboard/asrock/e350m1/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -34,12 +33,5 @@
//#define IDSOPT_TRACING_ENABLED TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
1 change: 0 additions & 1 deletion src/mainboard/asrock/h110m/devicetree.cb
View file
Expand Up @@ -19,7 +19,6 @@ chip soc/intel/skylake

# FSP Configuration
register "PrimaryDisplay" = "Display_PEG"
register "SaGv" = "SaGv_Enabled"

# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
Expand Down
8 changes: 0 additions & 8 deletions src/mainboard/asrock/h81m-hds/Kconfig
View file
Expand Up @@ -32,12 +32,4 @@ config MAINBOARD_PART_NUMBER
string
default "H81M-HDS"

#
# Since this is a desktop board, the assumption is made that most users
# would want CMOS configuration enabled by default.
#
config USE_OPTION_TABLE
bool
default y

endif
8 changes: 0 additions & 8 deletions src/mainboard/asrock/imb-a180/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -35,12 +34,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
8 changes: 0 additions & 8 deletions src/mainboard/asus/a88xm-e/OptionsIds.h
View file
Expand Up @@ -22,7 +22,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
**/

Expand All @@ -32,12 +31,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
4 changes: 2 additions & 2 deletions src/mainboard/asus/am1i-a/BiosCallOuts.c
View file
Expand Up @@ -87,7 +87,7 @@ void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_
FchParams_reset->Mode = 6;

/* Read SATA speed setting from CMOS */
FchParams_reset->SataSetMaxGen2 = get_int_option("sata_speed", 0);
FchParams_reset->SataSetMaxGen2 = get_uint_option("sata_speed", 0);
printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2);
}

Expand All @@ -102,7 +102,7 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */

/* Read SATA controller mode from CMOS */
FchParams_env->Sata.SataClass = get_int_option("sata_mode", 0);
FchParams_env->Sata.SataClass = get_uint_option("sata_mode", 0);

switch ((SATA_CLASS)FchParams_env->Sata.SataClass) {
case SataLegacyIde:
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/am1i-a/Kconfig
View file
Expand Up @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
select FORCE_AM1_SOCKET_SUPPORT
select GFXUMA
select HAVE_OPTION_TABLE
select USE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
select HAVE_ACPI_RESUME
Expand Down
8 changes: 0 additions & 8 deletions src/mainboard/asus/am1i-a/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -35,12 +34,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
8 changes: 0 additions & 8 deletions src/mainboard/asus/f2a85-m/OptionsIds.h
View file
Expand Up @@ -24,7 +24,6 @@
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
Expand All @@ -35,12 +34,5 @@
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80

#endif
2 changes: 2 additions & 0 deletions src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb
View file
Expand Up @@ -92,6 +92,8 @@ chip northbridge/amd/agesa/family15tn/root_complex
end
device pnp 2e.b on # Hardware Monitor, Front Panel LED
io 0x60 = 0x0290
io 0x62 = 0
io 0x70 = 0
irq 0xe2 = 0x7f
irq 0xe4 = 0xf1
end
Expand Down
55 changes: 55 additions & 0 deletions src/mainboard/asus/h61-series/Kconfig
View file
@@ -0,0 +1,55 @@
## SPDX-License-Identifier: GPL-2.0-only

config BOARD_ASUS_H61_SERIES
bool
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select USE_NATIVE_RAMINIT

if BOARD_ASUS_H61_SERIES

config MAINBOARD_DIR
string
default "asus/h61-series"

config VARIANT_DIR
string
default "h61m-cs" if BOARD_ASUS_H61M_CS
default "p8h61-m_lx" if BOARD_ASUS_P8H61_M_LX
default "p8h61-m_lx3_r2_0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "p8h61-m_pro" if BOARD_ASUS_P8H61_M_PRO

config MAINBOARD_PART_NUMBER
string
default "H61M-CS" if BOARD_ASUS_H61M_CS
default "P8H61-M LX" if BOARD_ASUS_P8H61_M_LX
default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO

config OVERRIDE_DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"

config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default"

config CMOS_LAYOUT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"

#
# These ME partitions need to be whitelisted for correct system
# operation. Example issues from removing them include: no serial output
# and kernel warnings about loading audio codecs.
#
config ME_CLEANER_ARGS
string
depends on USE_ME_CLEANER
default "-S --whitelist EFFS,FCRS" if BOARD_ASUS_P8H61_M_LX

endif
40 changes: 40 additions & 0 deletions src/mainboard/asus/h61-series/Kconfig.name
View file
@@ -0,0 +1,40 @@
config BOARD_ASUS_H61M_CS
bool "H61M-CS"
select BOARD_ASUS_H61_SERIES
select BOARD_ROMSIZE_KB_8192
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select NO_UART_ON_SUPERIO
select SUPERIO_NUVOTON_NCT6779D

config BOARD_ASUS_P8H61_M_LX
bool "P8H61-M LX"
select BOARD_ASUS_H61_SERIES
select BOARD_ROMSIZE_KB_4096
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select SUPERIO_NUVOTON_COMMON_COM_A
select SUPERIO_NUVOTON_NCT6776

config BOARD_ASUS_P8H61_M_LX3_R2_0
bool "P8H61-M LX3 R2.0"
select BOARD_ASUS_H61_SERIES
select BOARD_ROMSIZE_KB_8192
select NO_UART_ON_SUPERIO
select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select SUPERIO_NUVOTON_NCT6779D

config BOARD_ASUS_P8H61_M_PRO
bool "P8H61-M PRO"
select BOARD_ASUS_H61_SERIES
select BOARD_ROMSIZE_KB_4096
select DRIVERS_ASMEDIA_ASPM_BLACKLIST
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select MAINBOARD_HAS_LPC_TPM
select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select SUPERIO_NUVOTON_NCT6776
8 changes: 8 additions & 0 deletions src/mainboard/asus/h61-series/Makefile.inc
View file
@@ -0,0 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only

bootblock-y += variants/$(VARIANT_DIR)/early_init.c
romstage-y += variants/$(VARIANT_DIR)/early_init.c
bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
0 src/mainboard/asus/h61m-cs/acpi/ec.asl → src/mainboard/asus/h61-series/acpi/ec.asl
View file
File renamed without changes.
0 ...d/asus/p8h61-m_lx3_r2_0/acpi/platform.asl → ...inboard/asus/h61-series/acpi/platform.asl
View file
File renamed without changes.
6 changes: 6 additions & 0 deletions ...ainboard/asus/p8h61-m_lx/acpi/superio.asl → ...ainboard/asus/h61-series/acpi/superio.asl
View file
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#if CONFIG(BOARD_ASUS_P8H61_M_LX)

#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define NCT6776_SHOW_PP
Expand All @@ -10,3 +12,7 @@
#undef NCT6776_SHOW_GPIO

#include <superio/nuvoton/nct6776/acpi/superio.asl>

#else /* !BOARD_ASUS_P8H61_M_LX */
#include <drivers/pc80/pc/ps2_controller.asl>
#endif
5 changes: 5 additions & 0 deletions src/mainboard/asus/h61-series/board_info.txt
View file
@@ -0,0 +1,5 @@
Category: desktop
ROM package: DIP-8
ROM protocol: SPI
ROM socketed: y
Flashrom support: y
50 changes: 50 additions & 0 deletions src/mainboard/asus/h61-series/devicetree.cb
View file
@@ -0,0 +1,50 @@
## SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
device domain 0 on
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PEG
device pci 02.0 on end # iGPU

chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

device pci 16.0 on end # MEI #1
device pci 16.1 off end # MEI #2
device pci 16.2 off end # ME IDE-R
device pci 16.3 off end # ME KT
device pci 19.0 off end # Intel GbE
device pci 1a.0 on end # EHCI #2
device pci 1b.0 on end # HD Audio

device pci 1c.0 off end # RP #1
device pci 1c.1 off end # RP #2
device pci 1c.2 off end # RP #3
device pci 1c.3 off end # RP #4
device pci 1c.4 off end # RP #5
device pci 1c.5 off end # RP #6
device pci 1c.6 off end # RP #7
device pci 1c.7 off end # RP #8

device pci 1d.0 on end # EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on end # LPC bridge
device pci 1f.2 on end # SATA (AHCI)
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA (Legacy)
device pci 1f.6 off end # Thermal
end
end
end
10 changes: 8 additions & 2 deletions src/mainboard/asus/p8z77-m_pro/dsdt.asl → src/mainboard/asus/h61-series/dsdt.asl
View file
@@ -1,20 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>

#if CONFIG(BOARD_ASUS_P8H61_M_LX)
#define BOARD_DSDT_REVISION 0x20171231 /* OEM revision */
#else
#define BOARD_DSDT_REVISION 0x20141018
#endif

DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018 /* OEM revision */
BOARD_DSDT_REVISION
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>

#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>

Expand Down
0 src/mainboard/asus/p8h61-m_lx/acpi/ec.asl → src/mainboard/asus/h61-series/hda_verb.c
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File renamed without changes.
0 src/mainboard/asus/h61m-cs/mainboard.c → src/mainboard/asus/h61-series/mainboard.c
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0 src/mainboard/asus/h61m-cs/board_info.txt → ...61-series/variants/h61m-cs/board_info.txt
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0 src/mainboard/asus/h61m-cs/cmos.default → .../h61-series/variants/h61m-cs/cmos.default
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0 src/mainboard/asus/h61m-cs/cmos.layout → ...s/h61-series/variants/h61m-cs/cmos.layout
View file
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0 src/mainboard/asus/h61m-cs/data.vbt → ...asus/h61-series/variants/h61m-cs/data.vbt
View file
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0 src/mainboard/asus/h61m-cs/early_init.c → .../h61-series/variants/h61m-cs/early_init.c
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File renamed without changes.
0 src/mainboard/asus/h61m-cs/gma-mainboard.ads → ...series/variants/h61m-cs/gma-mainboard.ads
View file
File renamed without changes.
0 src/mainboard/asus/h61m-cs/gpio.c → ...d/asus/h61-series/variants/h61m-cs/gpio.c
View file
File renamed without changes.
0 src/mainboard/asus/h61m-cs/hda_verb.c → ...us/h61-series/variants/h61m-cs/hda_verb.c
View file
File renamed without changes.
33 changes: 3 additions & 30 deletions src/mainboard/asus/h61m-cs/devicetree.cb → ...1-series/variants/h61m-cs/overridetree.cb
View file
@@ -1,32 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/sandybridge
device cpu_cluster 0x0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
device domain 0x0 on
device domain 0 on
subsystemid 0x1043 0x844d inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
chip southbridge/intel/bd82x6x
register "gen1_dec" = "0x000c0291"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on # High Definition Audio Audio controller
subsystemid 0x1043 0x8445
end
Expand All @@ -40,8 +18,7 @@ chip northbridge/intel/sandybridge
end
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge

device pci 1f.0 on # LPC bridge PCI-LPC bridge
chip superio/nuvoton/nct6779d
device pnp 2e.1 off end # Parallel
Expand Down Expand Up @@ -78,10 +55,6 @@ chip northbridge/intel/sandybridge
device pnp 2e.16 off end # Deep Sleep
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
end
end
0 src/mainboard/asus/p8h61-m_lx/board_info.txt → ...series/variants/p8h61-m_lx/board_info.txt
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx/cmos.default → ...1-series/variants/p8h61-m_lx/cmos.default
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx/cmos.layout → ...61-series/variants/p8h61-m_lx/cmos.layout
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx/data.vbt → ...s/h61-series/variants/p8h61-m_lx/data.vbt
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx/early_init.c → ...1-series/variants/p8h61-m_lx/early_init.c
View file
File renamed without changes.
0 ...inboard/asus/p8h61-m_lx/gma-mainboard.ads → ...ies/variants/p8h61-m_lx/gma-mainboard.ads
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx/gpio.c → ...sus/h61-series/variants/p8h61-m_lx/gpio.c
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx/hda_verb.c → ...h61-series/variants/p8h61-m_lx/hda_verb.c
View file
File renamed without changes.
32 changes: 1 addition & 31 deletions src/mainboard/asus/p8h61-m_lx/devicetree.cb → ...eries/variants/p8h61-m_lx/overridetree.cb
View file
@@ -1,36 +1,11 @@
## SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end

device domain 0 on
subsystemid 0x1043 0x844d inherit

device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe bridge for discrete graphics
device pci 02.0 on end # VGA controller

chip southbridge/intel/bd82x6x
register "c2_latency" = "101"
register "gen1_dec" = "0x00000295" # Super I/O HWM
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

device pci 16.0 on end # Management Engine interface 1
device pci 16.1 off end # Management Engine interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on # HD audio controller
subsystemid 0x1043 0x8445
end
Expand All @@ -48,8 +23,7 @@ chip northbridge/intel/sandybridge
device pci 1c.5 off end # Unused PCIe port
device pci 1c.6 off end # Unused PCIe port
device pci 1c.7 off end # Unused PCIe port
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge

device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
Expand Down Expand Up @@ -106,10 +80,6 @@ chip northbridge/intel/sandybridge
device pnp 2e.17 off end # GPIOA
end
end
device pci 1f.2 on end # SATA controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA controller 2
device pci 1f.6 off end # Thermal
end
end
end
0 ...oard/asus/p8h61-m_lx3_r2_0/board_info.txt → .../variants/p8h61-m_lx3_r2_0/board_info.txt
View file
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0 src/mainboard/asus/p8h61-m_lx3_r2_0/data.vbt → ...series/variants/p8h61-m_lx3_r2_0/data.vbt
View file
File renamed without changes.
0 ...nboard/asus/p8h61-m_lx3_r2_0/early_init.c → ...es/variants/p8h61-m_lx3_r2_0/early_init.c
View file
File renamed without changes.
0 ...d/asus/p8h61-m_lx3_r2_0/gma-mainboard.ads → ...riants/p8h61-m_lx3_r2_0/gma-mainboard.ads
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_lx3_r2_0/gpio.c → ...1-series/variants/p8h61-m_lx3_r2_0/gpio.c
View file
File renamed without changes.
0 ...ainboard/asus/p8h61-m_lx3_r2_0/hda_verb.c → ...ries/variants/p8h61-m_lx3_r2_0/hda_verb.c
View file
File renamed without changes.
35 changes: 3 additions & 32 deletions ...board/asus/p8h61-m_lx3_r2_0/devicetree.cb → ...variants/p8h61-m_lx3_r2_0/overridetree.cb
View file
@@ -1,45 +1,20 @@
## SPDX-License-Identifier: GPL-2.0-only
## SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
device domain 0 on
subsystemid 0x1043 0x844d inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PEG
device pci 02.0 on end # iGPU

chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291"
register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

device pci 16.0 on end # MEI #1
device pci 16.1 off end # MEI #2
device pci 16.2 off end # ME IDE-R
device pci 16.3 off end # ME KT
device pci 19.0 off end # Intel GbE
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # HD Audio

device pci 1c.0 on end # RP #1
device pci 1c.1 off end # RP #2
device pci 1c.2 off end # RP #3
device pci 1c.3 on end # RP #4: PCIEX1_1
device pci 1c.4 on end # RP #5: PCIEX1_2
device pci 1c.5 on end # RP #6: RTL8111 GbE NIC
device pci 1c.6 off end # RP #7
device pci 1c.7 off end # RP #8

device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6779d
device pnp 2e.1 off end # Parallel
Expand Down Expand Up @@ -76,10 +51,6 @@ chip northbridge/intel/sandybridge
device pnp 2e.16 off end # Deep Sleep
end
end
device pci 1f.2 on end # SATA (AHCI)
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA (Legacy)
device pci 1f.6 off end # Thermal
end
end
end
0 ...mainboard/asus/p8h61-m_pro/board_info.txt → ...eries/variants/p8h61-m_pro/board_info.txt
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_pro/cmos.default → ...-series/variants/p8h61-m_pro/cmos.default
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_pro/cmos.layout → ...1-series/variants/p8h61-m_pro/cmos.layout
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File renamed without changes.
0 src/mainboard/asus/p8h61-m_pro/data.vbt → .../h61-series/variants/p8h61-m_pro/data.vbt
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_pro/early_init.c → ...-series/variants/p8h61-m_pro/early_init.c
View file
File renamed without changes.
2 changes: 1 addition & 1 deletion ...nboard/asus/p8h61-m_pro/gma-mainboard.ads → ...es/variants/p8h61-m_pro/gma-mainboard.ads
View file
@@ -1,4 +1,4 @@
-- SPDX-License-Identifier: GPL-2.0-only
-- SPDX-License-Identifier: GPL-2.0-or-later

with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
Expand Down
0 src/mainboard/asus/p8h61-m_pro/gpio.c → ...us/h61-series/variants/p8h61-m_pro/gpio.c
View file
File renamed without changes.
0 src/mainboard/asus/p8h61-m_pro/hda_verb.c → ...61-series/variants/p8h61-m_pro/hda_verb.c
View file
File renamed without changes.
38 changes: 4 additions & 34 deletions src/mainboard/asus/p8h61-m_pro/devicetree.cb → ...ries/variants/p8h61-m_pro/overridetree.cb
View file
@@ -1,35 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-only
## SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/sandybridge
device cpu_cluster 0x0 on
chip cpu/intel/model_206ax
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
device domain 0x0 on
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1)
device pci 02.0 on end # Internal graphics VGA controller

chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
device domain 0 on
chip southbridge/intel/bd82x6x
register "gen1_dec" = "0x000c0291" # HWM
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"

device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1)
device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2)
device pci 1c.2 on # Realtek RTL8111E Ethernet Controller
Expand All @@ -44,8 +19,7 @@ chip northbridge/intel/sandybridge
device pci 1c.5 on end # ASMedia ASM1062 SATA Controller
device pci 1c.6 off end # Unused PCIe Port
device pci 1c.7 off end # Unused PCIe Port
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge

device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
Expand Down Expand Up @@ -102,10 +76,6 @@ chip northbridge/intel/sandybridge
device pnp 4e.0 on end # TPM
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
end
end
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Expand Up @@ -28,10 +28,6 @@ config MAINBOARD_PART_NUMBER
string
default "Maximus IV GENE-Z"

config VGA_BIOS_ID
string
default "8086,0112"

config USBDEBUG_HCD_INDEX
int
default 1
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/maximus_iv_gene-z/devicetree.cb
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Expand Up @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge
register "acpi_c1" = "1"
register "acpi_c2" = "3"
register "acpi_c3" = "5"
device lapic 0x0 on end
device lapic 0 on end
device lapic 0xacac off end
end
end
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