diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
@@ -104,7 +104,7 @@ void paging_disable_pae(void)
  * Use PAE to map a page and then memset it with the pattern specified.
  * In order to use PAE pagetables for virtual addressing are set up and reloaded
  * on a 2MiB boundary. After the function is done, virtual addressing mode is
- * disabled again. The PAT are set to all cachable, but MTRRs still apply.
+ * disabled again. The PAT are set to all cacheable, but MTRRs still apply.
  *
  * Requires a scratch memory for pagetables and a virtual address for
  * non identity mapped memory.
@@ -124,7 +124,7 @@ void paging_disable_pae(void)
  *                  Content at physical address isn't preserved.
  * @param length    The length of the memory segment to memset
  * @param dest      Physical memory address to memset
- * @param pat       The pattern to write to the pyhsical memory
+ * @param pat       The pattern to write to the physical memory
  * @return 0 on success, 1 on error
  */
 int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,

diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/cpu_info.S.inc>
 #include <cpu/x86/cr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
@@ -19,6 +20,10 @@ gdtaddr:
 .word 0 /* unused */
 idt_ptr:
 .long 0
+per_cpu_segment_descriptors:
+.long 0
+per_cpu_segment_selector:
+.long 0
 stack_top:
 .long 0
 stack_size:
@@ -57,7 +62,7 @@ _start:
 	movw	%cs, %ax
 	movw	%ax, %ds
 
-	/* The gdtaddr needs to be releative to the data segment in order
+	/* The gdtaddr needs to be relative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
 	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
@@ -98,10 +103,20 @@ _start:
 	movl	stack_top, %edx
 	subl	%eax, %edx
 	mov	%edx, %esp
-	andl	$0xfffffff0, %esp /* ensure stack alignment */
 
-	/* Save CPU number. */
-	mov	%ecx, %esi
+	push_cpu_info index=%ecx
+	push_per_cpu_segment_data
+
+	/*
+	 * Update the AP's per_cpu_segment_descriptor to point to the
+	 * per_cpu_segment_data that was allocated on the stack.
+	 */
+	set_segment_descriptor_base per_cpu_segment_descriptors, %esp, %ecx
+
+	mov	%ecx, %eax
+	shl	$3, %eax /* The index is << 3 in the segment selector */
+	add	per_cpu_segment_selector, %eax
+	mov	%eax, %gs
 
 	/*
 	 * The following code only needs to run on Intel platforms and thus the caller
@@ -215,19 +230,15 @@ load_msr:
 	mov	%eax, %cr4
 #endif
 
+	andl	$0xfffffff0, %esp /* ensure stack alignment */
+
 #if ENV_X86_64
 	/* entry64.inc preserves ebx. */
 #include <cpu/x86/64bit/entry64.inc>
 
-	mov	%rsi, %rdi	/* cpu_num */
-
 	movabs	c_handler, %eax
 	call	*%rax
 #else
-	/* c_handler(cpu_num), preserve proper stack alignment */
-	sub	$12, %esp
-	push	%esi	/* cpu_num */
-
 	mov	c_handler, %eax
 	call	*%eax
 #endif

diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
@@ -95,7 +95,7 @@ smm_trampoline32:
 	movw	%ax, %ss
 	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs /* Will be used for cpu_info */
+	movw	%ax, %gs /* Used by cpu_info in ramstage */
 
 	/* The CPU number is calculated by reading the initial APIC id. Since
 	 * the OS can manipulate the APIC id use the non-changing cpuid result

diff --git a/src/device/Kconfig b/src/device/Kconfig
@@ -166,7 +166,7 @@ config ALWAYS_RUN_OPROM
 	def_bool n
 	depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM
 	help
-	  Always uncondtionally run the option regardless of other
+	  Always unconditionally run the option regardless of other
 	  policies.
 
 config ON_DEVICE_ROM_LOAD

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
@@ -289,7 +289,7 @@ void azalia_audio_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the azalia_audio get's a bar above 4G.
+	// NOTE this will break as soon as the azalia_audio gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);

diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
@@ -205,7 +205,7 @@ int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
 
 	/* Verify CRC of blocks that have them, do not step over 'used' length */
 	for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) {
-		/* this block is not checksumed */
+		/* this block is not checksummed */
 		if (spd_blocks[i].crc_start == 0)
 			continue;
 		/* we shouldn't have this block */

diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h
@@ -54,7 +54,7 @@
  * EAX & 0xff  === AL
  * EAX & 0xffff == AX
  *
- * etc.  The result is that alot of the calculations can then be
+ * etc.  The result is that a lot of the calculations can then be
  * done using the native instruction set fully.
  */
 

diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE
@@ -1,7 +1,7 @@
                          License information
                          -------------------
 
-The x86emu library is under a BSD style license, comaptible
+The x86emu library is under a BSD style license, compatible
 with the XFree86 and X licenses used by XFree86. The
 original x86emu libraries were under the GNU General Public
 License. Due to license incompatibilities between the GPL

diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c
@@ -2458,7 +2458,7 @@ void x86emu_cpuid(void)
     switch (feature) {
     case 0:
         /* Regardless if we have real data from the hardware, the emulator
-         * will only support upto feature 1, which we set in register EAX.
+         * will only support up to feature 1, which we set in register EAX.
          * Registers EBX:EDX:ECX contain a string identifying the CPU.
          */
         M.x86.R_EAX = 1;

diff --git a/src/device/pci_early.c b/src/device/pci_early.c
@@ -104,7 +104,7 @@ void pci_early_bridge_init(void)
 }
 
 /* FIXME: A lot of issues using the following, please avoid.
- * Assumes 256 PCI busses, scans them all even when PCI bridges are still
+ * Assumes 256 PCI buses, scans them all even when PCI bridges are still
  * disabled. Probes all functions even if 0 is not present.
  */
 pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)

diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c
@@ -238,7 +238,7 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask)
 	resource->limit = (1 << (bit + 1)) - 1;
 
 	/* The block of ones in the mask is expected to be continuous.
-	   If there is any zero inbetween the block of ones, it is ignored
+	   If there is any zero in between the block of ones, it is ignored
 	   in the calculation of the resource size and limit. */
 	if (mask != (resource->limit ^ (resource->size - 1)))
 		printk(BIOS_WARNING,

diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c
@@ -637,7 +637,7 @@ static void allocate_domain_resources(const struct device *domain)
  * order to accomplish best fit for the resources, a list of ranges is maintained by each
  * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since
  * they are allocated space from the same window, the resource allocator at the domain level
- * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the
+ * ensures that the biggest requirement is selected independent of the prefetch type. Once the
  * resource allocation for all immediate downstream devices is complete at the domain level,
  * resource allocator walks down the subtree for each downstream bridge to continue the
  * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and

diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
@@ -5,7 +5,7 @@
  *
  * $Workfile:: cache_as_ram.S
  *
- * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier
+ * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler
  *
  ******************************************************************************
  */

diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c
@@ -6,7 +6,7 @@
  *
  * TPM starts in IDLE Mode
  *
- *   IDLE  --> READY --> Command Receiption
+ *   IDLE  --> READY --> Command Reception
  *    ^	                        |
  *    |	                        v
       -- Cmd Complete <-- Command Execution

diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
@@ -2,6 +2,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <arch/mmio.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>

diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h
@@ -81,7 +81,7 @@ struct drivers_generic_gpio_keys_config {
 	struct acpi_gpio gpio;
 	/* Is this a polled GPIO button? - Optional */
 	bool is_polled;
-	/* Poll inverval - Mandatory only if GPIO is polled. */
+	/* Poll interval - Mandatory only if GPIO is polled. */
 	uint32_t poll_interval;
 	/* Details about the key - Mandatory */
 	struct key_info key;

diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h
@@ -6,7 +6,6 @@
 typedef struct drivers_generic_ioapic_config {
 	u32 version;
 	u8 apicid;
-	u8 enable_virtual_wire;
 	u8 have_isa_interrupts;
 	void *base;
 } ioapic_config_t;

diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c
@@ -13,7 +13,7 @@ static void ioapic_init(struct device *dev)
 	if (!dev->enabled || !config)
 		return;
 
-	setup_ioapic_helper(config->base, config->apicid, config->enable_virtual_wire);
+	setup_ioapic(config->base, config->apicid);
 }
 
 static void ioapic_read_resources(struct device *dev)

diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h
@@ -90,7 +90,7 @@ struct lm96000_temp_zone {
 	enum {
 		/* turn fan off below `low_temp - hysteresis` */
 		LM96000_LOW_TEMP_OFF = 0,
-		/* keep PWM at mininum duty cycle */
+		/* keep PWM at minimum duty cycle */
 		LM96000_LOW_TEMP_MIN = 1,
 	} min_off;
 	u8 hysteresis;

diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h
@@ -37,7 +37,7 @@ enum nct7802y_fan_mode {
 
 enum nct7802y_fan_smartmode {
 	SMART_FAN_DUTY = 0,	/* Target values given in duty cycle %. */
-	SMART_FAN_RPM,		/* Target valuse given in RPM. */
+	SMART_FAN_RPM,		/* Target values given in RPM. */
 };
 
 enum nct7802y_fan_speed {

diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
@@ -3,7 +3,7 @@
 /* Based on Linux Kernel TPM driver */
 
 /*
- * cr50 is a TPM 2.0 capable device that requries special
+ * cr50 is a TPM 2.0 capable device that requires special
  * handling for the I2C interface.
  *
  * - Use an interrupt for transaction status instead of hardcoded delays

diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
@@ -35,7 +35,7 @@
 
 /* max. number of iterations after I2C NAK for 'long' commands
  * we need this especially for sending TPM_READY, since the cleanup after the
- * transtion to the ready state may take some time, but it is unpredictable
+ * transition to the ready state may take some time, but it is unpredictable
  * how long it will take.
  */
 #define MAX_COUNT_LONG 50

diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c
@@ -91,7 +91,7 @@ static const TiLp55231Program solid_000000_program = {
  *
  * When solid patterns are deployed with instanteneous color intensity
  * changes, all three LEDs can be controlled by one engine in sequential
- * accesses. But the controllers still neeed to be synchronized.
+ * accesses. But the controllers still need to be synchronized.
  *
  * The maximum timer duration of lp55231 is .48 seconds. To achieve longer
  * blinking intervals the loops delays are deployed. Only the first controller

diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h
@@ -21,15 +21,15 @@
 #include <stdint.h>
 #include "drivers/i2c/ww_ring/ww_ring.h"
 
-/* There are threee independent engines/cores in the controller. */
+/* There are three independent engines/cores in the controller. */
 #define LP55231_NUM_OF_ENGINES 3
 
 /* Number of lp55321 controllers on the ring */
 #define WW_RING_NUM_LED_CONTROLLERS 1
 
 /*
  * Structure to describe an lp55231 program: pointer to the text of the
- * program, its size and load address (load addr + size sould not exceed
+ * program, its size and load address (load addr + size should not exceed
  * LP55231_MAX_PROG_SIZE), and start addresses for all of the three
  * engines.
  */

diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
@@ -5,16 +5,21 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <intelblocks/pmc_ipc.h>
+#include <soc/pci_devs.h>
 #include "chip.h"
 #include "dptf.h"
 
 /* Generic DPTF participants have a PTYP field to distinguish them */
 enum dptf_generic_participant_type {
 	DPTF_GENERIC_PARTICIPANT_TYPE_TSR	= 0x3,
+	DPTF_GENERIC_PARTICIPANT_TYPE_TPCH	= 0x5,
 	DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER	= 0xB,
 };
 
 #define DEFAULT_CHARGER_STR		"Battery Charger"
+#define DEFAULT_TPCH_STR		"Intel PCH FIVR Participant"
+
+#define PMC_IPC_COMMAND_FIVR_SIZE	0x8
 
 /*
  * Helper method to determine if a device is "used" (called out anywhere as a source or a target
@@ -195,45 +200,170 @@ static void write_generic_devices(const struct drivers_intel_dptf_config *config
 	}
 }
 
-/* \_SB.DPTF.TPCH.RFC methods */
-static void write_tpch_rfc_methods(const char *tpch_rfc_method_name,
+static const char *get_pmc_ipcs_method(void)
+{
+	const char *method = acpi_device_path_join(
+				pcidev_path_on_root(PCH_DEVFN_PMC), "IPCS");
+	if (!method) {
+		printk(BIOS_ERR, "%s: Unable to find PMC device IPCS method\n", __func__);
+		return NULL;
+	}
+	return method;
+}
+
+static void write_tpch_write_method(const char *tpch_write_method_name,
 				unsigned int ipc_subcmd_ctrl_value)
 {
-	acpigen_write_method_serialized(tpch_rfc_method_name, 1);
-	acpigen_emit_namestring("IPCS");
+	/* Get IPCS method from the PMC device */
+	const char *ipcs = get_pmc_ipcs_method();
+	acpigen_write_method_serialized(tpch_write_method_name, 1);
+	acpigen_emit_namestring(ipcs);
 	acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR);
 	acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_WRITE);
-	acpigen_write_integer(0x8);
+	acpigen_write_integer(PMC_IPC_COMMAND_FIVR_SIZE);
 	acpigen_write_integer(ipc_subcmd_ctrl_value);
 	acpigen_emit_byte(ARG0_OP);
-	acpigen_write_dword(0);
-	acpigen_write_dword(0);
+	acpigen_write_zero();
+	acpigen_write_zero();
 	/* The reason for returning a value here is a W/A for the ESIF shell */
 	acpigen_emit_byte(RETURN_OP);
-	acpigen_write_package(0);
+	acpigen_write_package(1);
+	acpigen_write_zero();
 	acpigen_write_package_end();
 	acpigen_write_method_end();
 }
 
+static void write_ppkg_package(const uint8_t i)
+{
+	acpigen_write_store();
+	acpigen_emit_byte(DEREF_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_byte(ARG0_OP);
+	acpigen_write_integer(i);
+	acpigen_emit_byte(ZERO_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring("PPKG");
+	acpigen_write_integer(i);
+	acpigen_emit_byte(ZERO_OP);
+}
+
+/*
+ * Truncate Package received from IPC
+ * Arguments:
+ *  Arg0: Package returned from the IPCS read call from the Pmc
+ * Return Value:
+ *  Return Package with just the Status and ReadBuf0
+ *  Status returns 0 for success and 2 for device error
+ */
+static void write_pkgc_method(void)
+{
+	acpigen_write_method_serialized("PKGC", 1);
+	acpigen_write_name("PPKG");
+	acpigen_write_package(2);
+	acpigen_write_zero();
+	acpigen_write_zero();
+	acpigen_write_package_end();
+
+	write_ppkg_package(0);
+	write_ppkg_package(1);
+
+	acpigen_write_return_namestr("PPKG");
+	acpigen_write_method_end();
+}
+
+static void write_tpch_read_method(const char *tpch_read_method_name,
+				unsigned int ipc_subcmd_ctrl_value)
+{
+	/* Get IPCS method from the PMC device */
+	const char *ipcs = get_pmc_ipcs_method();
+	acpigen_write_method_serialized(tpch_read_method_name, 0);
+	acpigen_write_store();
+	acpigen_emit_namestring(ipcs);
+	acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR);
+	acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_READ);
+	acpigen_write_integer(PMC_IPC_COMMAND_FIVR_SIZE);
+	acpigen_write_integer(ipc_subcmd_ctrl_value);
+	acpigen_write_zero();
+	acpigen_write_zero();
+	acpigen_write_zero();
+	acpigen_emit_byte(LOCAL0_OP);
+
+	acpigen_write_store();
+	acpigen_emit_namestring("PKGC");
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_emit_byte(LOCAL1_OP);
+
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_byte(LOCAL1_OP);
+	acpigen_write_method_end();
+}
+
 static void write_create_tpch(const struct dptf_platform_info *platform_info)
 {
 	acpigen_write_device("TPCH");
 	acpigen_write_name("_HID");
 	dptf_write_hid(platform_info->use_eisa_hids, platform_info->tpch_device_hid);
-	acpigen_write_name_integer("_UID", 0);
+	acpigen_write_name_string("_STR", DEFAULT_TPCH_STR);
+	acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_TPCH);
 	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 }
 
 static void write_tpch_methods(const struct dptf_platform_info *platform_info)
 {
 	write_create_tpch(platform_info);
 
-	/* Create RFC0 method */
-	write_tpch_rfc_methods(platform_info->tpch_rfc0_method,
-			PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC);
-	/* Create RFC1 method */
-	write_tpch_rfc_methods(platform_info->tpch_rfc1_method,
-			PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC);
+	const struct {
+		enum { READ, WRITE } type;
+		const char *method_name;
+		unsigned int subcommand;
+	} tpch_methods[] = {
+		{	.type = WRITE,
+			.method_name =
+				platform_info->tpch_method_names.set_fivr_low_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC
+		},
+		{	.type = WRITE,
+			.method_name =
+				platform_info->tpch_method_names.set_fivr_high_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_low_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_high_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_ssc_method,
+			.subcommand = PMC_IPC_SUBCMD_EMI_CTRL0_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+			platform_info->tpch_method_names.get_fivr_switching_fault_status,
+			.subcommand = PMC_IPC_SUBCMD_FFFC_FAULT_STATUS
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_switching_freq_mhz,
+			.subcommand = PMC_IPC_SUBCMD_FFFC_RFI_STATUS
+		},
+	};
+
+	write_pkgc_method();
+	for (size_t i = 0; i < ARRAY_SIZE(tpch_methods); i++) {
+		if (tpch_methods[i].type == READ) {
+			write_tpch_read_method(tpch_methods[i].method_name,
+						tpch_methods[i].subcommand);
+		} else if (tpch_methods[i].type == WRITE) {
+			write_tpch_write_method(tpch_methods[i].method_name,
+						tpch_methods[i].subcommand);
+		}
+	}
 
 	acpigen_write_device_end(); /* TPCH Device */
 }

diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h
@@ -15,8 +15,15 @@ struct dptf_platform_info {
 	const char *generic_hid;
 	const char *fan_hid;
 	const char *tpch_device_hid;
-	const char *tpch_rfc0_method;
-	const char *tpch_rfc1_method;
+	struct {
+		const char *set_fivr_low_clock_method;
+		const char *set_fivr_high_clock_method;
+		const char *get_fivr_low_clock_method;
+		const char *get_fivr_high_clock_method;
+		const char *get_fivr_ssc_method;
+		const char *get_fivr_switching_fault_status;
+		const char *get_fivr_switching_freq_mhz;
+	} tpch_method_names;
 };
 
 const struct dptf_platform_info *get_dptf_platform_info(void);

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -78,7 +78,7 @@ endif
 
 ifeq ($(CONFIG_FSP_FULL_FD),y)
 $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG)
-	python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd"
+	python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd"
 
 $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd
 	true

diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -9,6 +9,7 @@
 #include <fsp/ppi/mp_service_ppi.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
+#include <types.h>
 
 #define BSP_CPU_SLOT 0
 
@@ -72,7 +73,8 @@ efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
 	if (procedure == NULL)
 		return FSP_INVALID_PARAMETER;
 
-	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial)) {
+	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial) !=
+				CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}
@@ -94,7 +96,7 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
 
 	/* Run on APs */
 	if (mp_run_on_aps((void *)procedure, argument,
-			MP_RUN_ON_ALL_CPUS, timeout_usec)) {
+			MP_RUN_ON_ALL_CPUS, timeout_usec) != CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}
@@ -118,7 +120,7 @@ efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure,
 		return FSP_INVALID_PARAMETER;
 
 	if (mp_run_on_aps((void *)procedure, argument,
-			processor_number, timeout_usec)) {
+			processor_number, timeout_usec) != CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}

diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c
@@ -525,7 +525,7 @@ void print_fru_areas(struct fru_info_str *fru_info_str)
 	if (prod_info.product_name != NULL)
 		printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name);
 	if (prod_info.product_partnumber != NULL)
-		printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber);
+		printk(BIOS_DEBUG, "product part number: %s\n", prod_info.product_partnumber);
 	if (prod_info.product_version != NULL)
 		printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version);
 	if (prod_info.serial_number != NULL)

diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c
@@ -26,7 +26,7 @@ static void set_coreboot_ver(const uint16_t kcs_port)
 	int ret;
 	size_t i;
 
-	/* Only 8 charactars are visible in UI. Cut of on first dash */
+	/* Only 8 characters are visible in UI. Cut of on first dash */
 	for (i = 0; i < 15; i++) {
 		if (coreboot_ver[i] == '-')
 			break;

diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig
@@ -33,7 +33,7 @@ config RT8168_SET_LED_MODE
 	select REALTEK_8168_RESET
 	help
 	  This is to set a customized LED mode to distinguish 10/100/1000
-	  link and speed status with limited LEDs avaiable on a board.
+	  link and speed status with limited LEDs available on a board.
 	  Please refer to RTL811x datasheet section 7.2 Customizable LED
 	  Configuration for details. With this flag enabled, the
 	  customized_leds variable will be read from devicetree setting.

diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c
@@ -127,7 +127,7 @@ static void atl1e_init(struct device *dev)
 
 	/* Check if the base is invalid */
 	if (!mem_base) {
-		printk(BIOS_ERR, "atl1e: Error cant find MEM resource\n");
+		printk(BIOS_ERR, "atl1e: Error can't find MEM resource\n");
 		return;
 	}
 	/* Enable but do not set bus master */

diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c
@@ -280,7 +280,7 @@ static void r8168_init(struct device *dev)
 
 	/* Check if the base is invalid */
 	if (!io_base) {
-		printk(BIOS_ERR, "r8168: Error cant find IO resource\n");
+		printk(BIOS_ERR, "r8168: Error can't find IO resource\n");
 		return;
 	}
 	/* Enable but do not set bus master */

diff --git a/src/drivers/ocp/dmi/smbios.c b/src/drivers/ocp/dmi/smbios.c
@@ -11,6 +11,7 @@
 #include <soc/soc_util.h>
 #include <soc/util.h>
 #include <smbios.h>
+#include <types.h>
 
 #include "ocp_dmi.h"
 
@@ -244,7 +245,8 @@ void ocp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t)
 	if (CONFIG_MAX_SOCKET == 2 && CONFIG(PARALLEL_MP_AP_WORK)) {
 		/* Read the last CPU MSR */
 		if (mp_run_on_aps(read_remote_ppin, (void *)&xeon_sp_ppin[1],
-				get_platform_thread_count() - 1, 100 * USECS_PER_MSEC)) {
+				get_platform_thread_count() - 1, 100 * USECS_PER_MSEC) !=
+						CB_SUCCESS) {
 			printk(BIOS_ERR, "Failed to read remote PPIN.\n");
 			t->count = smbios_add_oem_string(t->eos, TBF);
 		} else {

diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
@@ -22,6 +22,7 @@
 #include <security/tpm/tis.h>
 #include <device/pnp.h>
 #include <drivers/tpm/tpm_ppi.h>
+#include <timer.h>
 #include "chip.h"
 
 #define PREFIX "lpc_tpm: "
@@ -84,7 +85,7 @@
 #define TPM_DRIVER_ERR		(~0)
 
  /* 1 second is plenty for anything TPM does.*/
-#define MAX_DELAY_US	(1000 * 1000)
+#define MAX_DELAY_US	USECS_PER_SEC
 
 /*
  * Structures defined below allow creating descriptions of TPM vendor/device
@@ -172,7 +173,7 @@ static inline u8 tpm_read_data(int locality)
 
 static inline void tpm_write_data(u8 data, int locality)
 {
-	TPM_DEBUG_IO_WRITE(TIS_REG_STS, data);
+	TPM_DEBUG_IO_WRITE(TIS_REG_DATA_FIFO, data);
 	write8(TIS_REG(locality, TIS_REG_DATA_FIFO), data);
 }
 
@@ -238,7 +239,7 @@ static inline u32 tpm_read_int_polarity(int locality)
 /*
  * tis_wait_sts()
  *
- * Wait for at least a second for a status to change its state to match the
+ * Wait for at most a second for a status to change its state to match the
  * expected state. Normally the transition happens within microseconds.
  *
  * @locality - locality
@@ -249,14 +250,15 @@ static inline u32 tpm_read_int_polarity(int locality)
  */
 static int tis_wait_sts(int locality, u8 mask, u8 expected)
 {
-	u32 time_us = MAX_DELAY_US;
-	while (time_us > 0) {
+	struct stopwatch sw;
+
+	stopwatch_init_usecs_expire(&sw, MAX_DELAY_US);
+	do {
 		u8 value = tpm_read_status(locality);
 		if ((value & mask) == expected)
 			return 0;
-		udelay(1); /* 1 us */
-		time_us--;
-	}
+		udelay(1);
+	} while (!stopwatch_expired(&sw));
 	return TPM_TIMEOUT_ERR;
 }
 
@@ -291,7 +293,7 @@ static inline int tis_expect_data(int locality)
 /*
  * tis_wait_access()
  *
- * Wait for at least a second for a access to change its state to match the
+ * Wait for at most a second for a access to change its state to match the
  * expected state. Normally the transition happens within microseconds.
  *
  * @locality - locality
@@ -302,14 +304,15 @@ static inline int tis_expect_data(int locality)
  */
 static int tis_wait_access(int locality, u8 mask, u8 expected)
 {
-	u32 time_us = MAX_DELAY_US;
-	while (time_us > 0) {
+	struct stopwatch sw;
+
+	stopwatch_init_usecs_expire(&sw, MAX_DELAY_US);
+	do {
 		u8 value = tpm_read_access(locality);
 		if ((value & mask) == expected)
 			return 0;
-		udelay(1); /* 1 us */
-		time_us--;
-	}
+		udelay(1);
+	} while (!stopwatch_expired(&sw));
 	return TPM_TIMEOUT_ERR;
 }
 
@@ -440,7 +443,6 @@ static u32 tis_senddata(const u8 *const data, u32 len)
 {
 	u32 offset = 0;
 	u16 burst = 0;
-	u32 max_cycles = 0;
 	u8 locality = 0;
 
 	if (tis_wait_ready(locality)) {
@@ -452,20 +454,20 @@ static u32 tis_senddata(const u8 *const data, u32 len)
 
 	while (1) {
 		unsigned int count;
+		struct stopwatch sw;
 
 		/* Wait till the device is ready to accept more data. */
+		stopwatch_init_usecs_expire(&sw, MAX_DELAY_US);
 		while (!burst) {
-			if (max_cycles++ == MAX_DELAY_US) {
-				printf("%s:%d failed to feed %d bytes of %d\n",
+			if (stopwatch_expired(&sw)) {
+				printf("%s:%d failed to feed %u bytes of %u\n",
 				       __FILE__, __LINE__, len - offset, len);
 				return TPM_DRIVER_ERR;
 			}
 			udelay(1);
 			burst = tpm_read_burst_count(locality);
 		}
 
-		max_cycles = 0;
-
 		/*
 		 * Calculate number of bytes the TPM is ready to accept in one
 		 * shot.
@@ -570,7 +572,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len)
 
 				if ((expected_count < offset) ||
 				    (expected_count > *len)) {
-					printf("%s:%d bad response size %d\n",
+					printf("%s:%d bad response size %u\n",
 					       __FILE__, __LINE__,
 					       expected_count);
 					return TPM_DRIVER_ERR;
@@ -600,7 +602,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len)
 
 	/* * Make sure we indeed read all there was. */
 	if (tis_has_valid_data(locality)) {
-		printf("%s:%d wrong receive status: %x %d bytes left\n",
+		printf("%s:%d wrong receive status: %x %u bytes left\n",
 		       __FILE__, __LINE__, tpm_read_status(locality),
 	               tpm_read_burst_count(locality));
 		return TPM_DRIVER_ERR;
@@ -647,7 +649,7 @@ int tis_open(void)
 
 	/* did we get a lock? */
 	if (tis_wait_received_access(locality)) {
-		printf("%s:%d - failed to lock locality %d\n",
+		printf("%s:%d - failed to lock locality %u\n",
 		       __FILE__, __LINE__, locality);
 		return TPM_DRIVER_ERR;
 	}
@@ -674,7 +676,7 @@ int tis_close(void)
 	if (tis_has_access(locality)) {
 		tis_drop_access(locality);
 		if (tis_wait_dropped_access(locality)) {
-			printf("%s:%d - failed to release locality %d\n",
+			printf("%s:%d - failed to release locality %u\n",
 			       __FILE__, __LINE__, locality);
 			return TPM_DRIVER_ERR;
 		}

diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c
@@ -683,7 +683,7 @@ int spi_sdcard_single_write(const struct spi_sdcard *card,
 	spi_sdcard_sendbyte(card, 0xff & (c >> 8));
 	spi_sdcard_sendbyte(card, 0xff & (c >> 0));
 
-	/* recevie and verify data response token */
+	/* receive and verify data response token */
 	c = spi_sdcard_recvbyte(card);
 	if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) {
 		spi_sdcard_disable_cs(card);
@@ -742,7 +742,7 @@ int spi_sdcard_multiple_write(const struct spi_sdcard *card,
 		spi_sdcard_sendbyte(card, 0xff & (c >> 8));
 		spi_sdcard_sendbyte(card, 0xff & (c >> 0));
 
-		/* recevie and verify data response token */
+		/* receive and verify data response token */
 		c = spi_sdcard_recvbyte(card);
 		if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED)
 			break;

diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
@@ -3,7 +3,7 @@
  *
  * It assumes that the required SPI interface has been initialized before the
  * driver is started. A 'sruct spi_slave' pointer passed at initialization is
- * used to direct traffic to the correct SPI interface. This dirver does not
+ * used to direct traffic to the correct SPI interface. This driver does not
  * provide a way to instantiate multiple TPM devices. Also, to keep things
  * simple, the driver unconditionally uses of TPM locality zero.
  *
@@ -159,7 +159,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
 
 	/*
 	 * The first byte of the frame header encodes the transaction type
-	 * (read or write) and transfer size (set to lentgh - 1), limited to
+	 * (read or write) and transfer size (set to length - 1), limited to
 	 * 64 bytes.
 	 */
 	header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1);
@@ -188,7 +188,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
 	 * the last clock of the byte) is set to 1.
 	 *
 	 * Due to some SPI controllers' shortcomings (Rockchip comes to
-	 * mind...) we trasmit the 4 byte header without checking the byte
+	 * mind...) we transmit the 4 byte header without checking the byte
 	 * transmitted by the TPM during the transaction's last byte.
 	 *
 	 * We know that cr50 is guaranteed to set the flow control bit to 0

diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl
@@ -118,7 +118,7 @@ Device (EC0)
 		SWTO, 1,        // SW Throttling (1=Active)             ; AEh.6
 		TTHR, 1,        // HW (THRM#) Throttling (1=Active)     ; AEh.7
 		TTHM, 1,        // TS_THERMAL(1:Throttling for thermal) ; AFh.0
-		THTL, 1,        // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1
+		THTL, 1,        // THROTTLING(1:Ctrl H/W throttling act); AFh.1
 		, 2,            // Reserved                             ; AFh.2-3
 		NPST, 4,        // Number of P-State level              ; AFh.4-7
 		CTMP, 8,        // Current CPU Temperature              ; B0h

diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
@@ -20,7 +20,7 @@ endif
 
 bootblock-y += ec.c
 bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
-ramstage-y += ec.c crosec_proto.c vstore.c
+ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
 ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
@@ -1477,7 +1477,9 @@ int google_ec_running_ro(void)
 	return (google_chromeec_get_current_image() == EC_IMAGE_RO);
 }
 
-int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode)
+/* Returns data role and type of device connected */
+static int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc,
+				    bool *active_cable, uint8_t *dp_mode)
 {
 	struct ec_params_usb_pd_control pd_control = {
 		.port = port,
@@ -1501,11 +1503,39 @@ int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *
 
 	*ufp = (resp.cc_state == PD_CC_DFP_ATTACHED);
 	*dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC);
+	*active_cable = !!(resp.control_flags & USB_PD_CTRL_ACTIVE_CABLE);
 	*dp_mode = resp.dp_mode;
 
 	return 0;
 }
 
+int google_chromeec_typec_control_enter_dp_mode(int port)
+{
+	if (!google_chromeec_check_feature(EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY))
+		return 0;
+
+	struct ec_params_typec_control typec_control = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_ENTER_MODE,
+		.mode_to_enter = TYPEC_MODE_DP,
+	};
+
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_TYPEC_CONTROL,
+		.cmd_version = 0,
+		.cmd_data_in = &typec_control,
+		.cmd_size_in = sizeof(typec_control),
+		.cmd_data_out = NULL,
+		.cmd_size_out = 0,
+		.cmd_dev_index = 0,
+	};
+
+	if (google_chromeec_command(&cmd) < 0)
+		return -1;
+
+	return 0;
+}
+
 /**
  * Check for the current mux state in EC. Flags representing the mux state found
  * in ec_commands.h
@@ -1536,13 +1566,50 @@ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags)
 	return 0;
 }
 
+/*
+ * Obtain any USB-C mux data needed for the specified port
+ * in: physical port number of the type-c port
+ * out: struct usbc_mux_info mux_info stores USB-C mux data
+ * Return: 0 on success, -1 on error
+*/
+int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info)
+{
+	uint8_t mux_flags;
+	uint8_t dp_pin_mode;
+	bool ufp, dbg_acc, active_cable;
+
+	if (google_chromeec_usb_get_pd_mux_info(port, &mux_flags) < 0) {
+		printk(BIOS_ERR, "Port C%d: get_pd_mux_info failed\n", port);
+		return -1;
+	}
+
+	if (google_chromeec_usb_pd_get_info(port, &ufp, &dbg_acc,
+					    &active_cable, &dp_pin_mode) < 0) {
+		printk(BIOS_ERR, "Port C%d: pd_control failed\n", port);
+		return -1;
+	}
+
+	mux_info->usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED);
+	mux_info->dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED);
+	mux_info->polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED);
+	mux_info->hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ);
+	mux_info->hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL);
+	mux_info->ufp = !!ufp;
+	mux_info->dbg_acc = !!dbg_acc;
+	mux_info->cable = !!active_cable;
+	mux_info->dp_pin_mode = dp_pin_mode;
+
+	return 0;
+}
+
 /**
  * Check if EC/TCPM is in an alternate mode or not.
  *
  * @param svid SVID of the alternate mode to check
- * @return     0: Not in the mode. -1: Error. 1: Yes.
+ * @return	0: Not in the mode. -1: Error.
+ *		>=1: bitmask of the ports that are in the mode.
  */
-int google_chromeec_pd_get_amode(uint16_t svid)
+static int google_chromeec_pd_get_amode(uint16_t svid)
 {
 	struct ec_response_usb_pd_ports resp;
 	struct chromeec_command cmd = {
@@ -1555,6 +1622,7 @@ int google_chromeec_pd_get_amode(uint16_t svid)
 		.cmd_dev_index = 0,
 	};
 	int i;
+	int ret = 0;
 
 	if (google_chromeec_command(&cmd) < 0)
 		return -1;
@@ -1580,41 +1648,71 @@ int google_chromeec_pd_get_amode(uint16_t svid)
 			if (google_chromeec_command(&cmd) < 0)
 				return -1;
 			if (resp2.svid == svid)
-				return 1;
+				ret |= BIT(i);
 			svid_idx++;
 		} while (resp2.svid);
 	}
 
-	return 0;
+	return ret;
 }
 
 #define USB_SID_DISPLAYPORT 0xff01
 
 /**
  * Wait for DisplayPort to be ready
  *
- * @param timeout Wait aborts after <timeout> ms.
- * @return 1: Success or 0: Timeout.
+ * @param timeout_ms Wait aborts after <timeout_ms> ms.
+ * @return	-1: Error. 0: Timeout.
+ *		>=1: Bitmask of the ports that DP device is connected
  */
-int google_chromeec_wait_for_displayport(long timeout)
+int google_chromeec_wait_for_displayport(long timeout_ms)
 {
 	struct stopwatch sw;
+	int ret = 0;
 
 	printk(BIOS_INFO, "Waiting for DisplayPort\n");
-	stopwatch_init_msecs_expire(&sw, timeout);
-	while (google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT) != 1) {
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+	while (1) {
+		ret = google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT);
+		if (ret > 0)
+			break;
+
+		if (ret < 0) {
+			printk(BIOS_ERR, "Can't get alternate mode!\n");
+			return ret;
+		}
+
 		if (stopwatch_expired(&sw)) {
 			printk(BIOS_WARNING,
 			       "DisplayPort not ready after %ldms. Abort.\n",
-			       timeout);
+			       timeout_ms);
 			return 0;
 		}
 		mdelay(200);
 	}
 	printk(BIOS_INFO, "DisplayPort ready after %lu ms\n",
 	       stopwatch_duration_msecs(&sw));
 
-	return 1;
+	return ret;
+}
+
+int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms)
+{
+	uint8_t mux_flags;
+	struct stopwatch sw;
+
+	stopwatch_init_msecs_expire(&sw, timeout_ms);
+	do {
+		google_chromeec_usb_get_pd_mux_info(port, &mux_flags);
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_WARNING, "HPD not ready after %ldms. Abort.\n", timeout_ms);
+			return -1;
+		}
+		mdelay(100);
+	} while (!(mux_flags & USB_PD_MUX_HPD_LVL) || !(mux_flags & USB_PD_MUX_DP_ENABLED));
+	printk(BIOS_INFO, "HPD ready after %lu ms\n", stopwatch_duration_msecs(&sw));
+
+	return 0;
 }
 
 int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd)

diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
@@ -9,6 +9,7 @@
 #include <types.h>
 #include <device/device.h>
 #include "ec_commands.h"
+#include <device/usbc_mux.h>
 
 /* Fill in base and size of the IO port resources used. */
 void google_chromeec_ioport_range(uint16_t *base, size_t *size);
@@ -26,17 +27,32 @@ bool google_chromeec_is_uhepi_supported(void);
 int google_ec_running_ro(void);
 enum ec_image google_chromeec_get_current_image(void);
 void google_chromeec_init(void);
-int google_chromeec_pd_get_amode(uint16_t svid);
 /* Check for the current mux state in EC
  * in: int port physical port number of the type-c port
  * out: uint8_t flags representing the status of the mux such as
  *	usb capability, dp capability, cable type, etc
  */
 int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags);
-/* Returns data role and type of device connected */
-int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc,
-					uint8_t *dp_mode);
-int google_chromeec_wait_for_displayport(long timeout);
+/* Poll (up to `timeout_ms` ms) for DisplayPort to be ready
+ * Return:	-1: Error. 0: Timeout.
+ *              >=1: Bitmask of the ports that DP device is connected
+ */
+int google_chromeec_wait_for_displayport(long timeout_ms);
+/* Poll (up to `timeout_ms` ms) for a Hot-Plug Detect (HPD)
+ * event on the specified port.
+ * Return: 0 on HPD ready, -1 on timeout */
+int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms);
+/* Send command to EC to request to enter DisplayPort ALT mode on the
+ * specified port.
+ * Return: 0 on success, -1 on error */
+int google_chromeec_typec_control_enter_dp_mode(int port);
+/*
+ * Obtain any USB-C mux data needed for the specified port
+ * in: int port physical port number of the type-c port
+ * out: struct usbc_mux_info mux_info stores USB-C mux data
+ * Return: 0 on success, -1 on error
+ */
+int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info);
 
 /* Device events */
 uint64_t google_chromeec_get_device_enabled_events(void);
@@ -161,7 +177,7 @@ int crosec_command_proto(struct chromeec_command *cec_command,
 			 crosec_io_t crosec_io, void *context);
 
 /**
- * Performs light verification of the EC<->AP communcation channel.
+ * Performs light verification of the EC<->AP communication channel.
  *
  * @return		0 on success, -1 on error
  */
@@ -330,7 +346,7 @@ struct usb_pd_port_caps {
  * Get role-based capabilities for a USB-PD port
  *
  * @param port			Which port to get information about
- * @param *power_role_cap	The power-role capabillity of the port
+ * @param *power_role_cap	The power-role capability of the port
  * @param *try_power_role_cap	The Try-power-role capability of the port
  * @param *data_role_cap	The data role capability of the port
  * @param *port_location	Location of the port on the device

diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
@@ -2856,7 +2856,7 @@ struct ec_params_motion_sense {
 		 */
 		struct __ec_todo_unpacked {
 			/* Data to set or EC_MOTION_SENSE_NO_VALUE to read.
-			 * kb_wake_angle: angle to wakup AP.
+			 * kb_wake_angle: angle to wake up AP.
 			 */
 			int16_t data;
 		} kb_wake_angle;

diff --git a/src/ec/google/chromeec/usbc_mux.c b/src/ec/google/chromeec/usbc_mux.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/google/chromeec/ec.h>
+
+static const struct usbc_ops google_chromeec_usbc_ops = {
+	.mux_ops = {
+		.get_mux_info = google_chromeec_get_usbc_mux_info,
+	},
+	.dp_ops = {
+		.wait_for_connection = google_chromeec_wait_for_displayport,
+		.enter_dp_mode = google_chromeec_typec_control_enter_dp_mode,
+		.wait_for_hpd = google_chromeec_wait_for_dp_hpd,
+	},
+};
+
+const struct usbc_ops *usbc_get_ops(void)
+{
+	return &google_chromeec_usbc_ops;
+}
diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h
@@ -10,7 +10,7 @@ enum {
 	KB_POWER_SMI = 0x04,
 	/* Read but do not clear power state information */
 	KB_POWER_STATUS = 0x05,
-	/* Inform the EC aboout the reason host is turning off */
+	/* Inform the EC about the reason host is turning off */
 	KB_POWER_OFF = 0x08,
 	/* Control wireless radios */
 	KB_RADIO_CONTROL = 0x2b,

diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
@@ -75,7 +75,7 @@ Device (EC0)
 		KBID, 1,        // 0=EN KBD, 1=JP KBD                   ; 80h.1
 		    , 6,        // Reserved                             ; 80h.2-7
 		NPST, 8,        // Number of P-State level              ; 81h
-		MPST, 8,        // Maxumum P-State                      ; 82h
+		MPST, 8,        // Maximum P-State                      ; 82h
 		KWAK, 1,        // Keyboard WAKE(0=Disable,1=Enable)    ; 83h.0
 		TWAK, 1,        // TouchPad WAKE(0=Disable,1=Enable)    ; 83h.1
 		    , 1,        // Reserved                             ; 83h.2

diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl
@@ -23,7 +23,7 @@ Device (BATX)
 		0,            //  0: Power Unit
 		0xFFFFFFFF,   //  1: Design Capacity
 		0xFFFFFFFF,   //  2: Last Full Charge Capacity
-		1,            //  3: Battery Technology(Rechargable)
+		1,            //  3: Battery Technology(Rechargeable)
 		10800,        //  4: Design Voltage 10.8V
 		0,            //  5: Design capacity of warning
 		0,            //  6: Design capacity of low

diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl
@@ -444,7 +444,7 @@ Device (EC0)
 		MBTH, 4,        //   bit 3-0: battery 0 highest level
 		SBTH, 4,        //   bit 7-4: battery 1 highest level
 		                //   note: if highest level is 0 or 0xF, it means not defined
-		                //         (in this case, use default hightest level, it is 6)
+		                //         (in this case, use default highest level, it is 6)
 
 		Offset(0xEF),   // [EC Function Specification Major Version]
 		Offset(0xF0),   // [Build ID]~ offset:0F7h

diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
@@ -128,6 +128,18 @@ typedef struct acpi_gen_regaddr {
 #define ACPI_ACCESS_SIZE_DWORD_ACCESS	3
 #define ACPI_ACCESS_SIZE_QWORD_ACCESS	4
 
+/* Macros for common resource types */
+#define ACPI_REG_MSR(address, offset, width) \
+	(acpi_addr_t){ \
+		.space_id    = ACPI_ADDRESS_SPACE_FIXED, \
+		.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
+		.addrl       = address, \
+		.bit_offset  = offset, \
+		.bit_width   = width, \
+	}
+
+#define ACPI_REG_UNSUPPORTED	(acpi_addr_t){0}
+
 /* Common ACPI HIDs */
 #define ACPI_HID_FDC "PNP0700"
 #define ACPI_HID_KEYBOARD "PNP0303"
@@ -1249,7 +1261,6 @@ unsigned long fw_cfg_acpi_tables(unsigned long start);
 /* These are implemented by the target port or north/southbridge. */
 unsigned long write_acpi_tables(unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);
-unsigned long acpi_fill_mcfg(unsigned long current);
 unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current);
 void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
 void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length);
@@ -1311,7 +1322,7 @@ void acpi_create_slit(acpi_slit_t *slit,
  * proximimity domain for the memory.
  */
 int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory);
-/* Create Heterogenous Memory Attribute Table */
+/* Create Heterogeneous Memory Attribute Table */
 void acpi_create_hmat(acpi_hmat_t *hmat,
 		      unsigned long (*acpi_fill_hmat)(unsigned long current));
 

diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
@@ -265,24 +265,37 @@ enum cppc_fields {
 	CPPC_MAX_FIELDS_VER_3,
 };
 
+typedef struct cppc_entry {
+	enum { CPPC_TYPE_REG, CPPC_TYPE_DWORD } type;
+	union {
+		acpi_addr_t reg;
+		uint32_t dword;
+	};
+} cppc_entry_t;
+
+#define CPPC_DWORD(_dword) \
+	(cppc_entry_t){ \
+		.type  = CPPC_TYPE_DWORD, \
+		.dword = _dword, \
+	}
+
+#define CPPC_REG(_reg) \
+	(cppc_entry_t){ \
+		.type = CPPC_TYPE_REG, \
+		.reg  = _reg, \
+	}
+
+#define CPPC_REG_MSR(address, offset, width) CPPC_REG(ACPI_REG_MSR(address, offset, width))
+#define CPPC_UNSUPPORTED CPPC_REG(ACPI_REG_UNSUPPORTED)
+
 struct cppc_config {
 	u32 version; /* must be 1, 2, or 3 */
 	/*
 	 * The generic acpi_addr_t structure is being used, though
 	 * anything besides PPC or FFIXED generally requires checking
 	 * if the OS has advertised support for it (via _OSC).
-	 *
-	 * NOTE: some fields permit DWORDs to be used.  If you
-	 * provide a System Memory register with all zeros (which
-	 * represents unsupported) then this will be used as-is.
-	 * Otherwise, a System Memory register with a 32-bit
-	 * width will be converted into a DWORD field (the value
-	 * of which will be the value of 'addrl'.  Any other use
-	 * of System Memory register is currently undefined.
-	 * (i.e., if you have an actual need for System Memory
-	 * then you'll need to adjust this kludge).
 	 */
-	acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3];
+	cppc_entry_t entries[CPPC_MAX_FIELDS_VER_3];
 };
 
 void acpigen_write_return_integer(uint64_t arg);
@@ -357,8 +370,8 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
 void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries);
 typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord;
 void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
-void acpigen_write_CST_package_entry(acpi_cstate_t *cstate);
-void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries);
+void acpigen_write_CST_package_entry(const acpi_cstate_t *cstate);
+void acpigen_write_CST_package(const acpi_cstate_t *entry, int nentries);
 typedef enum { CSD_HW_ALL = 0xfe } CSD_coord;
 void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype,
 				u32 index);
@@ -499,7 +512,7 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou
 void acpigen_write_indexfield(const char *idx, const char *data,
 			      struct fieldlist *l, size_t count, uint8_t flags);
 
-int get_cst_entries(acpi_cstate_t **);
+int get_cst_entries(const acpi_cstate_t **);
 
 /*
  * Get element from package into specified destination op:

diff --git a/src/include/bootmode.h b/src/include/bootmode.h
@@ -11,7 +11,6 @@ int get_recovery_mode_retrain_switch(void);
 int clear_recovery_mode_switch(void);
 int get_wipeout_mode_switch(void);
 int get_lid_switch(void);
-int get_ec_is_trusted(void);
 
 /* Return 1 if display initialization is required. 0 if not. */
 int display_init_required(void);

diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
@@ -56,7 +56,5 @@ static __always_inline void disable_cache(void)
 	wbinvd();
 }
 
-void x86_enable_cache(void);
-
 #endif /* !__ASSEMBLER__ */
 #endif /* CPU_X86_CACHE */
diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h
@@ -5,6 +5,8 @@
 
 /* These symbols are defined in c_start.S. */
 extern char gdt[];
+extern char per_cpu_segment_descriptors[];
+extern uint32_t per_cpu_segment_selector;
 extern char gdt_end[];
 extern char idtarg[];
 

diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
@@ -18,21 +18,10 @@ static __always_inline void xapic_write(unsigned int reg, uint32_t v)
 	write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v);
 }
 
-static inline void xapic_write_atomic(unsigned long reg, uint32_t v)
-{
-	volatile uint32_t *ptr;
-
-	ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg);
-
-	asm volatile ("xchgl %0, %1\n"
-		      : "+r" (v), "+m" (*(ptr))
-		      : : "memory", "cc");
-}
-
 static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid)
 {
-	xapic_write_atomic(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
-	xapic_write_atomic(LAPIC_ICR, icrlow);
+	xapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
+	xapic_write(LAPIC_ICR, icrlow);
 }
 
 static __always_inline int xapic_busy(void)
@@ -114,7 +103,7 @@ static __always_inline void lapic_update32(unsigned int reg, uint32_t mask, uint
 		value = xapic_read(reg);
 		value &= mask;
 		value |= or;
-		xapic_write_atomic(reg, value);
+		xapic_write(reg, value);
 	}
 }
 

diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
@@ -5,8 +5,7 @@
 
 #include <arch/smp/atomic.h>
 #include <cpu/x86/smm.h>
-#include <stddef.h>
-#include <stdint.h>
+#include <types.h>
 
 #define CACHELINE_SIZE 64
 
@@ -86,10 +85,9 @@ struct mp_ops {
 };
 
 /*
- * mp_init_with_smm() returns < 0 on failure and 0 on success. The mp_ops
- * argument is used to drive the multiprocess initialization. Unless otherwise
- * stated each callback is called on the BSP only. The sequence of operations
- * is the following:
+ * The mp_ops argument is used to drive the multiprocess initialization. Unless
+ * otherwise stated each callback is called on the BSP only. The sequence of
+ * operations is the following:
  * 1. pre_mp_init()
  * 2. get_cpu_count()
  * 3. get_smm_info()
@@ -103,7 +101,7 @@ struct mp_ops {
  * 10. mp_initialize_cpu() for each cpu
  * 11. post_mp_init()
  */
-int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops);
+enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops);
 
 enum {
 	/* Function runs on all cores (both BSP and APs) */
@@ -119,26 +117,25 @@ enum {
  * Input parameter expire_us <= 0 to specify an infinite timeout.
  * logical_cpu_num = MP_RUN_ON_ALL_CPUS to execute function over all cores (BSP
  * + APs) else specified AP number using logical_cpu_num.
- *
- * All functions return < 0 on error, 0 on success.
  */
-int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num,
+enum cb_err mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num,
 		long expire_us);
 
 /*
  * Runs func on all APs excluding BSP, with a provision to run calls in parallel
  * or serially per AP.
  */
-int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_parallel);
+enum cb_err mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us,
+			      bool run_parallel);
 
 /* Like mp_run_on_aps() but also runs func on BSP. */
-int mp_run_on_all_cpus(void (*func)(void *), void *arg);
+enum cb_err mp_run_on_all_cpus(void (*func)(void *), void *arg);
 
 /*
  * Park all APs to prepare for OS boot. This is handled automatically
  * by the coreboot infrastructure.
  */
-int mp_park_aps(void);
+enum cb_err mp_park_aps(void);
 
 /*
  * SMM helpers to use with initializing CPUs.

diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h
@@ -26,7 +26,7 @@ struct smm_save_state_ops {
 
 /* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */
 int get_apmc_node(u8 cmd);
-/* Return -1 on failure, 0 on succes.
+/* Return -1 on failure, 0 on success.
    Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */
 int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
 int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length);

diff --git a/src/include/device/device.h b/src/include/device/device.h
@@ -228,6 +228,17 @@ void set_cpu_topology(struct device *cpu, unsigned int node,
 void mp_init_cpus(DEVTREE_CONST struct bus *cpu_bus);
 static inline void mp_cpu_bus_init(struct device *dev)
 {
+	/*
+	 * When no LAPIC device is specified in the devietree inside the CPU cluster device,
+	 * neither a LAPIC device nor the link/bus between the CPU cluster and the LAPIC device
+	 * will be present in the static device tree and the link_list struct element of the
+	 * CPU cluster device will be NULL. In this case add one link, so that the
+	 * alloc_find_dev calls in init_bsp and allocate_cpu_devices will be able to add a
+	 * LAPIC device for the BSP and the APs on this link/bus.
+	 */
+	if (!dev->link_list)
+		add_more_links(dev, 1);
+
 	mp_init_cpus(dev->link_list);
 }
 

diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h
@@ -35,7 +35,7 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data,
 
 /*
  * software_i2c is supposed to be a debug feature. It's usually not compiled in,
- * but when it is it can be dynamically enabled at runtime for certain busses.
+ * but when it is it can be dynamically enabled at runtime for certain buses.
  * Need this ugly stub to arbitrate since I2C device drivers hardcode
  * 'i2c_transfer()' as their entry point.
  */

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
@@ -293,23 +293,6 @@
 #define PCI_DEVICE_ID_ATI_RADEON_RC	0x5146
 #define PCI_DEVICE_ID_ATI_RADEON_RD	0x5147
 
-#define PCI_DEVICE_ID_AMD_10H_NB_HT		0x1200
-#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT	0x1600
-#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT	0x1400
-#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT	0x141A
-#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT	0x1570
-#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT	0x15B0
-#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT	0x1536
-#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT	0x1566
-#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB	0x15d0
-#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB	0x1630
-#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU	0x1419
-#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU	0x1423
-#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU	0x1577
-#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU	0x1567
-#define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU	0x15D1
-#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU	0x1631
-
 #define PCI_DEVICE_ID_ATI_SB600_LPC		0x438D
 #define PCI_DEVICE_ID_ATI_SB600_SATA		0x4380
 #define PCI_DEVICE_ID_ATI_SB600_IDE		0x438C
@@ -363,31 +346,6 @@
 #define PCI_DEVICE_ID_ATI_SB800_USB_22_2	0x4396
 #define PCI_DEVICE_ID_ATI_SB800_GEC		0x1699
 
-#define PCI_DEVICE_ID_AMD_SB900_LPC		0x780E
-#define PCI_DEVICE_ID_AMD_SB900_SATA		0x7800
-#define PCI_DEVICE_ID_AMD_SB900_SATA_AHCI	0x7801
-#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID	0x7802
-#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID5	0x7803
-#define PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI	0x7804
-#define PCI_DEVICE_ID_AMD_SB900_IDE		0x780C
-#define PCI_DEVICE_ID_AMD_SB900_HDA		0x780D
-#define PCI_DEVICE_ID_AMD_SB900_PCI		0x780F
-#define PCI_DEVICE_ID_AMD_SB900_PCIEA		0x43A0
-#define PCI_DEVICE_ID_AMD_SB900_PCIEB		0x43A1
-#define PCI_DEVICE_ID_AMD_SB900_PCIEC		0x43A2
-#define PCI_DEVICE_ID_AMD_SB900_PCIED		0x43A3
-#define PCI_DEVICE_ID_AMD_SB900_SM		0x780B
-#define PCI_DEVICE_ID_AMD_SB900_USB_16_0	0x7812
-#define PCI_DEVICE_ID_AMD_SB900_USB_16_1	0x7812
-#define PCI_DEVICE_ID_AMD_SB900_USB_18_0	0x7807
-#define PCI_DEVICE_ID_AMD_SB900_USB_18_2	0x7808
-#define PCI_DEVICE_ID_AMD_SB900_USB_19_0	0x7807
-#define PCI_DEVICE_ID_AMD_SB900_USB_19_2	0x7808
-#define PCI_DEVICE_ID_AMD_SB900_USB_20_5	0x7809
-#define PCI_DEVICE_ID_AMD_SB900_GEC		0x7806
-#define PCI_DEVICE_ID_AMD_HUDSON_SD		0x7806
-#define PCI_DEVICE_ID_AMD_YANGTZE_SD		0x7813
-
 #define PCI_DEVICE_ID_ATI_RS690_HT		0x7910
 #define PCI_DEVICE_ID_ATI_RS740_HT		0x7911
 #define PCI_DEVICE_ID_ATI_RS690_PCIE		0x7912
@@ -402,17 +360,6 @@
 #define PCI_DEVICE_ID_ATI_RS690MT_INT_GFX	0x791f
 #define PCI_DEVICE_ID_ATI_RS740_INT_GFX		0x796e
 
-#define PCI_DEVICE_ID_AMD_RS780_HT		0x9600
-#define PCI_DEVICE_ID_AMD_RS780_PCIE		0x9602
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV2	0x9603
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV3	0x960B
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV4	0x9604
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV5	0x9605
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV6	0x9606
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV7	0x9607
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV9	0x9608
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV10	0x9609
-#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV8	0x960A
 #define PCI_DEVICE_ID_ATI_RS780_INT_GFX		0x9610
 #define PCI_DEVICE_ID_ATI_RS780C_INT_GFX	0x9611
 #define PCI_DEVICE_ID_ATI_RS780M_INT_GFX	0x9612
@@ -424,85 +371,6 @@
 #define PCI_DEVICE_ID_ATI_RS785MC_INT_GFX	0x9713
 #define PCI_DEVICE_ID_ATI_RS785D_INT_GFX	0x9714
 
-#define PCI_DEVICE_ID_AMD_RD890TV_HT		0x5956
-#define PCI_DEVICE_ID_AMD_RX780_HT		0x5957
-#define PCI_DEVICE_ID_AMD_RD780_HT		0x5958
-#define PCI_DEVICE_ID_AMD_SR5690_HT		0x5A10
-#define PCI_DEVICE_ID_AMD_RD890_HT		0x5A11
-#define PCI_DEVICE_ID_AMD_SR5670_HT		0x5A12
-#define PCI_DEVICE_ID_AMD_SR5650_HT		0x5A13
-#define PCI_DEVICE_ID_AMD_990FX_HT		0x5A14
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE		0x5A12
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2	0x5A16
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3	0x5A17
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4	0x5A18
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5	0x5A19
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6	0x5A1A
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7	0x5A1B
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9	0x5A1C
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10	0x5A1D
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11	0x5A1F
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12	0x5A20
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13	0x5A1E
-#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8	0x5A21
-#define PCI_DEVICE_ID_AMD_SR5650_IOMMU		0x5A23
-
-#define PCI_DEVICE_ID_AMD_CZ_HDA	0x157A
-#define PCI_DEVICE_ID_AMD_CZ_LPC	0x790E
-#define PCI_DEVICE_ID_AMD_CZ_SATA	0x7900
-#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI	0x7901
-#define PCI_DEVICE_ID_AMD_CZ_USB_0	0x7907
-#define PCI_DEVICE_ID_AMD_CZ_USB_1	0x7908
-#define PCI_DEVICE_ID_AMD_CZ_USB3_0	0x7914
-#define PCI_DEVICE_ID_AMD_CZ_SMBUS	0x790B
-
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP		0x15D3
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1		0x1633
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2		0x1634
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA		0x15DB
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB		0x15DC
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC	0x1635
-#define PCI_DEVICE_ID_AMD_FAM17H_ACP				0x15E2
-#define PCI_DEVICE_ID_AMD_FAM17H_HDA1				0x15E3
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0			0x15E0
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1			0x15E1
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0			0x15E5
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI			0x1639
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0			0x15E8
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1			0x15E9
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2			0x15EA
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3			0x15EB
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4			0x15EC
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5			0x15ED
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6			0x15EE
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF7			0x15EF
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0			0x1448
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1			0x1449
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2			0x144A
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3			0x144B
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4			0x144C
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5			0x144D
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6			0x144E
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7			0x144F
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0			0x166A
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1			0x166B
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2			0x166C
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3			0x166D
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4			0x166E
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5			0x166F
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6			0x1670
-#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7			0x1671
-#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0			0x7901
-#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1			0x7904
-#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0		0x7916
-#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1		0x7917
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD			0x7906
-#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS				0x790B
-#define PCI_DEVICE_ID_AMD_FAM17H_LPC				0x790E
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE			0x1458
-#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE			0x1641
-#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97			0x1644
-
 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU			0x15D8
 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU			0x1636
 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU			0x164C
@@ -624,6 +492,140 @@
 #define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
 
 #define PCI_VENDOR_ID_AMD		0x1022
+
+#define PCI_DEVICE_ID_AMD_10H_NB_HT		0x1200
+#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT	0x1600
+#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT	0x1400
+#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT	0x141A
+#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT	0x1570
+#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT	0x15B0
+#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT	0x1536
+#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT	0x1566
+#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB	0x15d0
+#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB	0x1630
+#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU	0x1419
+#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU	0x1423
+#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU	0x1577
+#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU	0x1567
+#define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU	0x15D1
+#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU	0x1631
+
+#define PCI_DEVICE_ID_AMD_SB900_LPC		0x780E
+#define PCI_DEVICE_ID_AMD_SB900_SATA		0x7800
+#define PCI_DEVICE_ID_AMD_SB900_SATA_AHCI	0x7801
+#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID	0x7802
+#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID5	0x7803
+#define PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI	0x7804
+#define PCI_DEVICE_ID_AMD_SB900_IDE		0x780C
+#define PCI_DEVICE_ID_AMD_SB900_HDA		0x780D
+#define PCI_DEVICE_ID_AMD_SB900_PCI		0x780F
+#define PCI_DEVICE_ID_AMD_SB900_PCIEA		0x43A0
+#define PCI_DEVICE_ID_AMD_SB900_PCIEB		0x43A1
+#define PCI_DEVICE_ID_AMD_SB900_PCIEC		0x43A2
+#define PCI_DEVICE_ID_AMD_SB900_PCIED		0x43A3
+#define PCI_DEVICE_ID_AMD_SB900_SM		0x780B
+#define PCI_DEVICE_ID_AMD_SB900_USB_16_0	0x7812
+#define PCI_DEVICE_ID_AMD_SB900_USB_16_1	0x7812
+#define PCI_DEVICE_ID_AMD_SB900_USB_18_0	0x7807
+#define PCI_DEVICE_ID_AMD_SB900_USB_18_2	0x7808
+#define PCI_DEVICE_ID_AMD_SB900_USB_19_0	0x7807
+#define PCI_DEVICE_ID_AMD_SB900_USB_19_2	0x7808
+#define PCI_DEVICE_ID_AMD_SB900_USB_20_5	0x7809
+#define PCI_DEVICE_ID_AMD_SB900_GEC		0x7806
+#define PCI_DEVICE_ID_AMD_HUDSON_SD		0x7806
+#define PCI_DEVICE_ID_AMD_YANGTZE_SD		0x7813
+
+#define PCI_DEVICE_ID_AMD_RS780_HT		0x9600
+#define PCI_DEVICE_ID_AMD_RS780_PCIE		0x9602
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV2	0x9603
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV3	0x960B
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV4	0x9604
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV5	0x9605
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV6	0x9606
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV7	0x9607
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV9	0x9608
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV10	0x9609
+#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV8	0x960A
+
+#define PCI_DEVICE_ID_AMD_RD890TV_HT		0x5956
+#define PCI_DEVICE_ID_AMD_RX780_HT		0x5957
+#define PCI_DEVICE_ID_AMD_RD780_HT		0x5958
+#define PCI_DEVICE_ID_AMD_SR5690_HT		0x5A10
+#define PCI_DEVICE_ID_AMD_RD890_HT		0x5A11
+#define PCI_DEVICE_ID_AMD_SR5670_HT		0x5A12
+#define PCI_DEVICE_ID_AMD_SR5650_HT		0x5A13
+#define PCI_DEVICE_ID_AMD_990FX_HT		0x5A14
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE		0x5A12
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2	0x5A16
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3	0x5A17
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4	0x5A18
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5	0x5A19
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6	0x5A1A
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7	0x5A1B
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9	0x5A1C
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10	0x5A1D
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11	0x5A1F
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12	0x5A20
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13	0x5A1E
+#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8	0x5A21
+#define PCI_DEVICE_ID_AMD_SR5650_IOMMU		0x5A23
+
+#define PCI_DEVICE_ID_AMD_CZ_HDA	0x157A
+#define PCI_DEVICE_ID_AMD_CZ_LPC	0x790E
+#define PCI_DEVICE_ID_AMD_CZ_SATA	0x7900
+#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI	0x7901
+#define PCI_DEVICE_ID_AMD_CZ_USB_0	0x7907
+#define PCI_DEVICE_ID_AMD_CZ_USB_1	0x7908
+#define PCI_DEVICE_ID_AMD_CZ_USB3_0	0x7914
+#define PCI_DEVICE_ID_AMD_CZ_SMBUS	0x790B
+
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP		0x15D3
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1		0x1633
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2		0x1634
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA		0x15DB
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB		0x15DC
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC	0x1635
+#define PCI_DEVICE_ID_AMD_FAM17H_ACP				0x15E2
+#define PCI_DEVICE_ID_AMD_FAM17H_HDA1				0x15E3
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0			0x15E0
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1			0x15E1
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0			0x15E5
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI			0x1639
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0			0x15E8
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1			0x15E9
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2			0x15EA
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3			0x15EB
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4			0x15EC
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5			0x15ED
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6			0x15EE
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF7			0x15EF
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0			0x1448
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1			0x1449
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2			0x144A
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3			0x144B
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4			0x144C
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5			0x144D
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6			0x144E
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7			0x144F
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0			0x166A
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1			0x166B
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2			0x166C
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3			0x166D
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4			0x166E
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5			0x166F
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6			0x1670
+#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7			0x1671
+#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0			0x7901
+#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1			0x7904
+#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0		0x7916
+#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1		0x7917
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD			0x7906
+#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS				0x790B
+#define PCI_DEVICE_ID_AMD_FAM17H_LPC				0x790E
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE			0x1458
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE			0x1641
+#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97			0x1644
+
 #define PCI_DEVICE_ID_AMD_LANCE		0x2000
 #define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
 #define PCI_DEVICE_ID_AMD_LX		0x1054
@@ -632,7 +634,7 @@
 #define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
 #define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
 #define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
-#define PCI_DEVIDE_ID_AMD_FE_GATE_700D	0x700D
+#define PCI_DEVICE_ID_AMD_FE_GATE_700D	0x700D
 #define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
 #define PCI_DEVICE_ID_AMD_FE_GATE_700F	0x700F
 #define PCI_DEVICE_ID_AMD_COBRA_7400	0x7400

diff --git a/src/include/device/usbc_mux.h b/src/include/device/usbc_mux.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* struct to hold all USB-C mux related variables */
+struct usbc_mux_info {
+	bool dp; /* DP connected */
+	bool usb; /* USB connected */
+	bool cable; /* 0 = Passive cable, 1 = Active cable */
+	bool polarity; /* Polarity of connected device. 0 = Normal, 1 = Flipped */
+	bool hpd_lvl; /* HPD Level assert */
+	bool hpd_irq; /* HPD IRQ assert */
+	bool ufp; /* 0 = DFP, 1 = UFP */
+	bool dbg_acc; /* Debug Accessory. 0 = Disable, 1 = Enable */
+	uint8_t dp_pin_mode; /* DP pin assignments
+				0h: Reserved.
+				1h: Pin Assignment A.
+				2h: Pin Assignment B.
+				3h: Pin Assignment C.
+				4h: Pin Assignment D.
+				5h: Pin Assignment E.
+				6h: Pin Assignment F.
+				7-Fh: Reserved. */
+};
+struct usbc_mux_ops {
+	/*
+	 * Get mux information on a given port.
+	 *
+	 * Return value:
+	 * -1 = error
+	 *  0 = success
+	 */
+	 int (*get_mux_info)(int port, struct usbc_mux_info *info);
+};
+
+struct usbc_dp_ops {
+	/*
+	 * Wait up to `timeout_ms` for DP connection to be ready on any available port.
+	 *
+	 * Return value:
+	 * -1 = error
+	 *  0 = no DP connection
+	 * <bit mask> = mask for ports that are ready in DP mode.
+	 */
+	int (*wait_for_connection)(long timeout_ms);
+
+	/*
+	 * Enter DP mode on a given `port`.
+	 *
+	 * Return value:
+	 * -1 = error
+	 *  0 = success
+	 */
+	int (*enter_dp_mode)(int port);
+
+	/*
+	 * Wait up to `timeout_ms` for HPD on a given port.
+	 *
+	 * Return value:
+	 * -1 = timeout
+	 *  0 = success
+	 */
+	int (*wait_for_hpd)(int port, long timeout_ms);
+};
+
+struct usbc_ops {
+	struct usbc_mux_ops mux_ops;
+	struct usbc_dp_ops dp_ops;
+};
+
+const struct usbc_ops *usbc_get_ops(void);
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
@@ -9,7 +9,7 @@
 
 #define DIMM_INFO_SERIAL_SIZE		4
 #define DIMM_INFO_PART_NUMBER_SIZE	33
-#define DIMM_INFO_TOTAL			8	/* Maximum num of dimm is 8 */
+#define DIMM_INFO_TOTAL			16
 
 /**
  * If this table is filled and put in CBMEM,

diff --git a/src/include/smbios.h b/src/include/smbios.h
@@ -247,6 +247,7 @@ typedef enum {
 	SMBIOS_PHYS_MEMORY_ARRAY = 16,
 	SMBIOS_MEMORY_DEVICE = 17,
 	SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19,
+	SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS = 20,
 	SMBIOS_SYSTEM_BOOT_INFORMATION = 32,
 	SMBIOS_IPMI_DEVICE_INFORMATION = 38,
 	SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41,
@@ -307,6 +308,18 @@ struct smbios_type0 {
 	u8 eos[2];
 } __packed;
 
+typedef enum {
+	SMBIOS_WAKEUP_TYPE_RESERVED = 0x00,
+	SMBIOS_WAKEUP_TYPE_OTHER = 0x01,
+	SMBIOS_WAKEUP_TYPE_UNKNOWN = 0x02,
+	SMBIOS_WAKEUP_TYPE_APM_TIMER = 0x03,
+	SMBIOS_WAKEUP_TYPE_MODEM_RING = 0x04,
+	SMBIOS_WAKEUP_TYPE_LAN_REMOTE = 0x05,
+	SMBIOS_WAKEUP_TYPE_POWER_SWITCH = 0x06,
+	SMBIOS_WAKEUP_TYPE_PCI_PME = 0x07,
+	SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED = 0x08,
+} smbios_wakeup_type;
+
 struct smbios_type1 {
 	struct smbios_header header;
 	u8 manufacturer;
@@ -880,6 +893,20 @@ struct smbios_type19 {
 	u8 eos[2];
 } __packed;
 
+struct smbios_type20 {
+	struct smbios_header header;
+	u32 addr_start;
+	u32 addr_end;
+	u16 memory_device_handle;
+	u16 memory_array_mapped_address_handle;
+	u8 partition_row_pos;
+	u8 interleave_pos;
+	u8 interleave_depth;
+	u64 ext_addr_start;
+	u64 ext_addr_end;
+	u8 eos[2];
+} __packed;
+
 struct smbios_type32 {
 	struct smbios_header header;
 	u8 reserved[6];
@@ -947,6 +974,7 @@ void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm,
 void smbios_fill_dimm_locator(const struct dimm_info *dimm,
 	struct smbios_type17 *t);
 
+smbios_wakeup_type smbios_system_wakeup_type(void);
 smbios_board_type smbios_mainboard_board_type(void);
 smbios_enclosure_type smbios_mainboard_enclosure_type(void);
 

diff --git a/src/include/thread.h b/src/include/thread.h
@@ -73,11 +73,6 @@ void thread_coop_disable(void);
 void thread_mutex_lock(struct thread_mutex *mutex);
 void thread_mutex_unlock(struct thread_mutex *mutex);
 
-static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci)
-{
-	ci->thread = NULL;
-}
-
 /* Architecture specific thread functions. */
 asmlinkage void switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack);
 /* Set up the stack frame for a new thread so that a switch_to_thread() call
@@ -96,8 +91,6 @@ static inline int thread_yield_microseconds(unsigned int microsecs)
 }
 static inline void thread_coop_enable(void) {}
 static inline void thread_coop_disable(void) {}
-struct cpu_info;
-static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { }
 
 static inline void thread_mutex_lock(struct thread_mutex *mutex) {}
 

diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
@@ -309,8 +309,15 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg,
 		loc = allocator(arg, size, &mdata);
 	} else if (compression == CBFS_COMPRESS_NONE) {
 		void *mapping = rdev_mmap_full(&rdev);
-		if (!mapping || cbfs_file_hash_mismatch(mapping, size, file_hash))
+
+		if (!mapping)
+			return NULL;
+
+		if (cbfs_file_hash_mismatch(mapping, size, file_hash)) {
+			rdev_munmap(&rdev, mapping);
 			return NULL;
+		}
+
 		return mapping;
 	} else if (!CBFS_CACHE_AVAILABLE) {
 		ERROR("Cannot map compressed file %s on x86\n", mdata.h.filename);

diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c
@@ -758,7 +758,7 @@ struct device_tree_node *dt_find_compat(struct device_tree_node *parent,
 }
 
 /*
- * Find the next compatible child of a given parent. All children upto the
+ * Find the next compatible child of a given parent. All children up to the
  * child passed in by caller are ignored. If child is NULL, it considers all the
  * children to find the first child which is compatible.
  *

diff --git a/src/lib/edid.c b/src/lib/edid.c
@@ -433,7 +433,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
 
 			/*
 			 * Slightly weird to return a global, but I've never
-			 * seen any EDID block wth two range descriptors, so
+			 * seen any EDID block with two range descriptors, so
 			 * it's harmless.
 			 */
 			return 1;
@@ -481,7 +481,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
 	  We have no samples between those values, so put a
 	  threshold at 95000 kHz. If we get anything over
 	  95000 kHz with single channel, we can make this
-	  more sofisticated but it's currently not needed.
+	  more sophisticated but it's currently not needed.
 	 */
 	out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000);
 	extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4));
@@ -1094,7 +1094,7 @@ int set_display_mode(struct edid *edid, enum edid_modes mode)
 }
 
 /*
- * Given a raw edid bloc, decode it into a form
+ * Given a raw edid block, decode it into a form
  * that other parts of coreboot can use -- mainly
  * graphics bringup functions. The raw block is
  * required to be 128 bytes long, per the standard,

diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c
@@ -126,7 +126,7 @@ struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp,
 	wave->channel_mask = speaker_mask;
 	memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format));
 
-	/* Calculate the dervied fields. */
+	/* Calculate the derived fields. */
 	wave->block_align = wave->num_channels * wave->bits_per_sample / 8;
 	wave->bytes_per_second = wave->block_align * wave->samples_per_second;
 

diff --git a/src/lib/region_file.c b/src/lib/region_file.c
@@ -9,7 +9,7 @@
  * A region file provides generic support for appending new data
  * within a storage region. The book keeping is tracked in metadata
  * blocks where an offset pointer points to the last byte of a newly
- * allocated byte sequence. Thus, by taking 2 block offets one can
+ * allocated byte sequence. Thus, by taking 2 block offsets one can
  * determine start and size of the latest update. The data does not
  * have to be the same consistent size, but the data size has be small
  * enough to fit a metadata block and one data write within the region.

diff --git a/src/lib/thread.c b/src/lib/thread.c
@@ -4,23 +4,14 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <stdlib.h>
-#include <arch/cpu.h>
 #include <bootstate.h>
 #include <commonlib/bsd/compiler.h>
 #include <console/console.h>
+#include <smp/node.h>
 #include <thread.h>
 #include <timer.h>
 
-/* Can't use the IS_POWER_OF_2 in _Static_assert */
-_Static_assert((CONFIG_STACK_SIZE & (CONFIG_STACK_SIZE - 1)) == 0,
-	       "`cpu_info()` requires the stack size to be a power of 2");
-
-/*
- * struct cpu_info lives at the top of each thread's stack. `cpu_info()` locates this struct by
- * taking the current stack pointer and masking off CONFIG_STACK_SIZE. This requires the stack
- * to be STACK_SIZE aligned.
- */
-static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(CONFIG_STACK_SIZE);
+static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(sizeof(uint64_t));
 static bool initialized;
 
 static void idle_thread_init(void);
@@ -36,28 +27,25 @@ static struct thread all_threads[TOTAL_NUM_THREADS];
 static struct thread *runnable_threads;
 static struct thread *free_threads;
 
-static inline struct cpu_info *thread_cpu_info(const struct thread *t)
-{
-	return (void *)(t->stack_orig);
-}
+static struct thread *active_thread;
 
 static inline int thread_can_yield(const struct thread *t)
 {
 	return (t != NULL && t->can_yield > 0);
 }
 
-/* Assumes current CPU info can switch. */
-static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci)
+static inline void set_current_thread(struct thread *t)
 {
-	return ci->thread;
+	assert(boot_cpu());
+	active_thread = t;
 }
 
 static inline struct thread *current_thread(void)
 {
-	if (!initialized)
+	if (!initialized || !boot_cpu())
 		return NULL;
 
-	return cpu_info_to_thread(cpu_info());
+	return active_thread;
 }
 
 static inline int thread_list_empty(struct thread **list)
@@ -94,22 +82,16 @@ static inline struct thread *pop_runnable(void)
 static inline struct thread *get_free_thread(void)
 {
 	struct thread *t;
-	struct cpu_info *ci;
-	struct cpu_info *new_ci;
 
 	if (thread_list_empty(&free_threads))
 		return NULL;
 
 	t = pop_thread(&free_threads);
 
-	ci = cpu_info();
-
-	/* Initialize the cpu_info structure on the new stack. */
-	new_ci = thread_cpu_info(t);
-	*new_ci = *ci;
-	new_ci->thread = t;
-
 	/* Reset the current stack value to the original. */
+	if (!t->stack_orig)
+		die("%s: Invalid stack value\n", __func__);
+
 	t->stack_current = t->stack_orig;
 
 	return t;
@@ -148,6 +130,8 @@ static void schedule(struct thread *t)
 	if (t->handle)
 		t->handle->state = THREAD_STARTED;
 
+	set_current_thread(t);
+
 	switch_to_thread(t->stack_current, &current->stack_current);
 }
 
@@ -262,24 +246,19 @@ static void threads_initialize(void)
 	int i;
 	struct thread *t;
 	u8 *stack_top;
-	struct cpu_info *ci;
 
 	if (initialized)
 		return;
 
-	/* `cpu_info()` requires the stacks to be STACK_SIZE aligned */
-	assert(IS_ALIGNED((uintptr_t)thread_stacks, CONFIG_STACK_SIZE));
-
-	/* Initialize the BSP thread first. The cpu_info structure is assumed
-	 * to be just under the top of the stack. */
 	t = &all_threads[0];
-	ci = cpu_info();
-	ci->thread = t;
-	t->stack_orig = (uintptr_t)ci;
+
+	set_current_thread(t);
+
+	t->stack_orig = (uintptr_t)NULL; /* We never free the main thread */
 	t->id = 0;
 	t->can_yield = 1;
 
-	stack_top = &thread_stacks[CONFIG_STACK_SIZE] - sizeof(struct cpu_info);
+	stack_top = &thread_stacks[CONFIG_STACK_SIZE];
 	for (i = 1; i < TOTAL_NUM_THREADS; i++) {
 		t = &all_threads[i];
 		t->stack_orig = (uintptr_t)stack_top;

diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl
@@ -13,7 +13,7 @@ DefinitionBlock(
 {
 	#include <acpi/dsdt_top.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
-	#include <soc/intel/skylake/acpi/globalnvs.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
 	Device (\_SB.PCI0)

diff --git a/src/mainboard/acer/g43t-am3/cstates.c b/src/mainboard/acer/g43t-am3/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb
@@ -127,7 +127,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_OFF"
 	register "gpp_clk_config[1]" = "GPP_CLK_OFF"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
@@ -36,11 +36,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-#config VGA_BIOS_FILE
-#        string "VGA BIOS path and filename"
-#        depends on VGA_BIOS
-#        default "rom/video/OntarioGenericVBios.bin"
-
 config VGA_BIOS_ID
 	string "VGA device PCI IDs"
 	depends on VGA_BIOS

diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
@@ -118,7 +118,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
@@ -118,7 +118,7 @@ chip soc/amd/picasso
 		.flash_ch_en = 0,
 	}"
 
-	# genral purpose PCIe clock output configuration
+	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
 	register "gpp_clk_config[2]" = "GPP_CLK_REQ"

diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
@@ -37,11 +37,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-#config VGA_BIOS_FILE
-#	string "VGA BIOS path and filename"
-#	depends on VGA_BIOS
-#	default "rom/video/OntarioGenericVbios.bin"
-
 config VGA_BIOS_ID
 	string
 	default "1002,9802"

diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
@@ -36,10 +36,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS_FILE
-	string
-	default "site-local/vgabios.bin"
-
 config VGA_BIOS_ID
 	string
 	default "1002,9806"

diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c
diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
@@ -35,10 +35,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS_FILE
-	string
-	default "site-local/vgabios.bin"
-
 config VGA_BIOS_ID
 	string
 	default "1002,9802"

diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c
diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-static acpi_cstate_t cst_entries[] = {
+static const acpi_cstate_t cst_entries[] = {
 	{
 		.ctype = 1,
 		.latency = 1,
@@ -31,7 +31,7 @@ static acpi_cstate_t cst_entries[] = {
 	},
 };
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	*entries = cst_entries;
 	return ARRAY_SIZE(cst_entries);

diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig
@@ -22,10 +22,6 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "MacBookAir4,2"
 
-config VGA_BIOS_FILE
-	string
-	default "pci8086,0116.rom"
-
 config VGA_BIOS_ID
 	string
 	default "8086,0116"

diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb
@@ -129,7 +129,7 @@ chip northbridge/intel/sandybridge
 						irq 0xe9 = 0x02
 						irq 0xf0 = 0x20
 					end
-					device pnp 2e.b off	end		# HWM, front pannel LED
+					device pnp 2e.b off	end		# HWM, front panel LED
 					device pnp 2e.d on end		# VID
 					device pnp 2e.e off end		# CIR WAKE-UP
 					device pnp 2e.f on end		# GPIO Push-Pull or Open-drain

diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c
diff --git a/src/mainboard/asrock/g41c-gs/cstates.c b/src/mainboard/asrock/g41c-gs/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
@@ -105,7 +105,7 @@ chip northbridge/intel/x4x		# Northbridge
 						irq 0xe9 = 0x02
 						irq 0xf0 = 0x20
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						io 0x62 = 0x200
 						irq 0x70 = 0

diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
@@ -99,7 +99,7 @@ chip northbridge/intel/x4x		# Northbridge
 					device pnp 2e.a on		# ACPI
 						irq 0xe4 = 0x10 # Power dram during s3
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						irq 0x70 = 0
 					end

diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
@@ -100,7 +100,7 @@ chip northbridge/intel/x4x		# Northbridge
 					device pnp 2e.a on		# ACPI
 						irq 0xe4 = 0x10 # Power dram during s3
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						irq 0x70 = 0
 					end

diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig
@@ -17,10 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select RT8168_SET_LED_MODE
 	select MAINBOARD_HAS_LPC_TPM
 
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
 config MAINBOARD_DIR
 	default "asrock/h110m"
 

diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl
@@ -14,7 +14,7 @@ DefinitionBlock(
 	#include <soc/intel/common/block/acpi/acpi/platform.asl>
 
 	// global NVS and variables
-	#include <soc/intel/skylake/acpi/globalnvs.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
 
 	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>

diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
@@ -95,10 +95,6 @@ config VGA_BIOS_ID
 	string
 	default "1002,9901"
 
-config VGA_BIOS_FILE
-	string
-	default "pci1002,9901.rom"
-
 endif
 
 config DEVICETREE

diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c
diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig
@@ -6,7 +6,6 @@ config BASE_ASUS_P2B_D
 	def_bool n
 	select SDRAMPWR_4DIMM
 	select HAVE_MP_TABLE
-	select IOAPIC
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y

diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/asus/p5qc/cstates.c b/src/mainboard/asus/p5qc/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c
@@ -3,7 +3,7 @@
 #include <acpi/acpigen.h>
 
 /* TODO: Could work... */
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb
@@ -34,7 +34,7 @@ chip northbridge/intel/x4x		# Northbridge
 						irq 0x70 = 0
 						irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
 					end
-					device pnp 2e.b on		# HWM, front pannel LED
+					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290
 						irq 0x70 = 0
 					end

diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -106,9 +106,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 			{ 1, 0, 0x0080 }, /* USB3 front internal header */
 			{ 1, 0, 0x0080 }, /* USB3 front internal header */
 			{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
-			{ 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+			{ 1, 1, 0x0080 }, /* USB3 ETH bottom connector */
 			{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
-			{ 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+			{ 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */
 			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
 			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
 			{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */

diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c
diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c
diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c
diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl
@@ -11,7 +11,7 @@ DefinitionBlock(
 )
 {
 	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/skylake/acpi/globalnvs.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 
 	Device (\_SB.PCI0) {

diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c
diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld
@@ -18,7 +18,7 @@
  * with -bios option which neatly puts coreboot into flash and so payloads
  * can find CBFS and we don't risk overwriting CBFS.
  *
- * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash
+ * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash
  * and -bios was unusable as $pc pointed to 0 which was zero-filled as a
  * workaround we suggested using -kernel but this still had all the issues
  * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends

diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h
@@ -2,7 +2,7 @@
 
 /*
  * These are the qemu firmware config interface defines and structs.
- * Copied over from qemu soure tree,
+ * Copied over from qemu source tree,
  * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly.
  */
 #ifndef FW_CFG_IF_H

diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -13,6 +13,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smbios.h>
+#include <types.h>
 #include "memory.h"
 
 #include "fw_cfg.h"
@@ -250,8 +251,8 @@ void mp_init_cpus(struct bus *cpu_bus)
 {
 	const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm;
 
-	if (mp_init_with_smm(cpu_bus, ops))
-		printk(BIOS_ERR, "MP initialization failure.\n");
+	/* TODO: Handle mp_init_with_smm failure? */
+	mp_init_with_smm(cpu_bus, ops);
 }
 
 static void cpu_bus_init(struct device *dev)

diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c
@@ -12,11 +12,3 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt)
 	fadt->acpi_enable = 0;
 	fadt->acpi_disable = 0;
 }
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
-					     CONFIG_MMCONF_BUS_NUMBER - 1);
-	return current;
-}
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void)
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
+	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
 	 * 4GiB.

diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c
@@ -181,7 +181,7 @@ static const struct edp_data b101uan08_table[] = {
 	{6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} },
 	{6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} },
 	{6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} },
-	/* Additional Settng for eDP */
+	/* Additional Setting for eDP */
 	{3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} },
 	{3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} },
 	/* DPRX CAD Register Setting */

diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex
@@ -39,7 +39,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 05
 
 #	5 SDRAM Addressing

diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
@@ -39,7 +39,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 05
 
 #	5 SDRAM Addressing

diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
@@ -38,7 +38,7 @@
 #	4 SDRAM CHIP Density and Banks
 #		bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
-#		bits[7]: reserverd
+#		bits[7]: reserved
 04
 
 #	5 SDRAM Addressing

diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig
@@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS
 config CBFS_SIZE
 	default 0x00900000
 
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
 config MAINBOARD_DIR
 	default "facebook/monolith"
 

diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl
@@ -13,7 +13,7 @@ DefinitionBlock(
 	#include <acpi/dsdt_top.asl>
 	#include <cpu/intel/common/acpi/cpu.asl>
 	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-	#include <soc/intel/skylake/acpi/globalnvs.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
 	Scope (\_SB) {

diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/foxconn/g41s-k/cstates.c b/src/mainboard/foxconn/g41s-k/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
@@ -32,8 +32,4 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
-config VGA_BIOS_FILE
-	string
-	default "getac-pci8086,27a2.rom"
-
 endif # BOARD_GETAC_P470
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
@@ -3,7 +3,7 @@
 #include <acpi/acpigen.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 
-static acpi_cstate_t cst_entries[] = {
+static const acpi_cstate_t cst_entries[] = {
 	{
 		/* ACPI C1 / CPU C1 */
 		1, 0x01, 1000,
@@ -21,7 +21,7 @@ static acpi_cstate_t cst_entries[] = {
 	},
 };
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	*entries = cst_entries;
 	return ARRAY_SIZE(cst_entries);

diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/gigabyte/ga-d510ud/cstates.c b/src/mainboard/gigabyte/ga-d510ud/cstates.c
@@ -2,7 +2,7 @@
 
 #include <acpi/acpigen.h>
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	return 0;
 }
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c
@@ -2,9 +2,9 @@
 
 #include <acpi/acpigen.h>
 
-static acpi_cstate_t cst_entries[] = {};
+static const acpi_cstate_t cst_entries[] = {};
 
-int get_cst_entries(acpi_cstate_t **entries)
+int get_cst_entries(const acpi_cstate_t **entries)
 {
 	*entries = cst_entries;
 	return ARRAY_SIZE(cst_entries);

diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c