15 changes: 8 additions & 7 deletions src/arch/x86/include/arch/pci_io_cfg.h
View file
Expand Up @@ -14,9 +14,10 @@
#ifndef _PCI_IO_CFG_H
#define _PCI_IO_CFG_H

#include <compiler.h>
#include <arch/io.h>

static inline __attribute__((always_inline))
static __always_inline
unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
{
if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) {
Expand All @@ -27,47 +28,47 @@ unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
}
}

static inline __attribute__((always_inline))
static __always_inline
uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned int where)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
return inb(0xCFC + (addr & 3));
}

static inline __attribute__((always_inline))
static __always_inline
uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned int where)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
return inw(0xCFC + (addr & 2));
}

static inline __attribute__((always_inline))
static __always_inline
uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned int where)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_io_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
}

static inline __attribute__((always_inline))
static __always_inline
void pci_io_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
}

static inline __attribute__((always_inline))
static __always_inline
void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
{
unsigned int addr = pci_io_encode_addr(dev, where);
Expand Down
13 changes: 7 additions & 6 deletions src/arch/x86/include/arch/pci_mmio_cfg.h
View file
Expand Up @@ -17,50 +17,51 @@
#define _PCI_MMIO_CFG_H

#include <arch/io.h>
#include <compiler.h>

#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS

static inline __attribute__((always_inline))
static __always_inline
u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where);
return read8(addr);
}

static inline __attribute__((always_inline))
static __always_inline
u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1));
return read16(addr);
}

static inline __attribute__((always_inline))
static __always_inline
u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3));
return read32(addr);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where);
write8(addr, value);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
{
void *addr;
addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1));
write16(addr, value);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
{
void *addr;
Expand Down
6 changes: 4 additions & 2 deletions src/arch/x86/include/arch/smp/atomic.h
View file
Expand Up @@ -14,6 +14,8 @@
#ifndef ARCH_SMP_ATOMIC_H
#define ARCH_SMP_ATOMIC_H

#include <compiler.h>

/*
* Make sure gcc doesn't try to be clever and move things around
* on us. We need to use _exactly_ the address the user gave us,
Expand Down Expand Up @@ -55,7 +57,7 @@ typedef struct { volatile int counter; } atomic_t;
* Atomically increments v by 1. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
static inline __attribute__((always_inline)) void atomic_inc(atomic_t *v)
static __always_inline void atomic_inc(atomic_t *v)
{
__asm__ __volatile__(
"lock ; incl %0"
Expand All @@ -70,7 +72,7 @@ static inline __attribute__((always_inline)) void atomic_inc(atomic_t *v)
* Atomically decrements v by 1. Note that the guaranteed
* useful range of an atomic_t is only 24 bits.
*/
static inline __attribute__((always_inline)) void atomic_dec(atomic_t *v)
static __always_inline void atomic_dec(atomic_t *v)
{
__asm__ __volatile__(
"lock ; decl %0"
Expand Down
8 changes: 5 additions & 3 deletions src/arch/x86/include/arch/smp/spinlock.h
View file
Expand Up @@ -14,6 +14,8 @@
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H

#include <compiler.h>

#if !defined(__PRE_RAM__) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
Expand Down Expand Up @@ -73,22 +75,22 @@ void initialize_romstage_microcode_cbfs_lock(void);
#define spin_unlock_string \
"movb $1,%0"

static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
static __always_inline void spin_lock(spinlock_t *lock)
{
__asm__ __volatile__(
spin_lock_string
: "=m" (lock->lock) : : "memory");
}

static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
static __always_inline void spin_unlock(spinlock_t *lock)
{
__asm__ __volatile__(
spin_unlock_string
: "=m" (lock->lock) : : "memory");
}

/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
static inline __attribute__((always_inline)) void cpu_relax(void)
static __always_inline void cpu_relax(void)
{
__asm__ __volatile__("rep;nop" : : : "memory");
}
Expand Down
3 changes: 2 additions & 1 deletion src/arch/x86/smbios.c
View file
Expand Up @@ -367,7 +367,8 @@ static int smbios_write_type0(unsigned long *current, int handle)

#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
/* SMBIOS offsets start at 1 rather than 0 */
acpi_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1);
chromeos_get_chromeos_acpi()->vbt10 =
(u32)t->eos + (version_offset - 1);
#endif
#endif /* CONFIG_CHROMEOS */

Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/lz4_wrapper.c
View file
Expand Up @@ -84,7 +84,7 @@ typedef uint32_t U32;
typedef int32_t S32;
typedef uint64_t U64;

#define FORCE_INLINE static inline __attribute__((always_inline))
#define FORCE_INLINE static __always_inline
#define likely(expr) __builtin_expect((expr) != 0, 1)
#define unlikely(expr) __builtin_expect((expr) != 0, 0)

Expand Down
3 changes: 1 addition & 2 deletions src/console/die.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <halt.h>

#ifndef __ROMCC__
#define NORETURN __attribute__((noreturn))

/*
* The method should be overwritten in mainboard directory to signal that a
Expand All @@ -33,7 +32,7 @@ __weak void die_notify(void)
}

/* Report a fatal error */
void NORETURN die(const char *msg)
void __noreturn die(const char *msg)
{
printk(BIOS_EMERG, "%s", msg);
die_notify();
Expand Down
5 changes: 3 additions & 2 deletions src/cpu/amd/car/disable_cache_as_ram.c
View file
Expand Up @@ -19,10 +19,11 @@
* WARNING: this file will be used by both any AP cores and core 0 / node 0
*/

#include <compiler.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>

static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
static __always_inline uint32_t amd_fam1x_cpu_family(void)
{
uint32_t family;

Expand All @@ -32,7 +33,7 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
return family;
}

static inline __attribute__((always_inline))
static __always_inline
void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
{
msr_t msr;
Expand Down
3 changes: 2 additions & 1 deletion src/cpu/amd/family_10h-family_15h/init_cpus.c
View file
Expand Up @@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/

#include <compiler.h>
#include "init_cpus.h"

#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
Expand Down Expand Up @@ -231,7 +232,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
#endif

static inline __attribute__((always_inline))
static __always_inline
void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
const char *str)
{
Expand Down
1 change: 1 addition & 0 deletions src/cpu/qemu-x86/Kconfig
View file
Expand Up @@ -20,3 +20,4 @@ config CPU_QEMU_X86
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select UDELAY_TSC
1 change: 1 addition & 0 deletions src/cpu/qemu-x86/Makefile.inc
View file
Expand Up @@ -16,3 +16,4 @@ ramstage-y += qemu.c
subdirs-y += ../x86/mtrr
subdirs-y += ../x86/lapic
subdirs-y += ../x86/smm
subdirs-y += ../x86/tsc
2 changes: 1 addition & 1 deletion src/cpu/x86/smm/smihandler.c
View file
Expand Up @@ -60,7 +60,7 @@ void smi_release_lock(void)
}

#define LAPIC_ID 0xfee00020
static inline __attribute__((always_inline)) unsigned long nodeid(void)
static __always_inline unsigned long nodeid(void)
{
return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
}
Expand Down
2 changes: 1 addition & 1 deletion src/device/dram/ddr2.c
View file
Expand Up @@ -124,7 +124,7 @@ u32 spd_decode_eeprom_size_ddr2(u8 byte1)
/**
* \brief Return index of MSB set
*
* Returns the index fof MSB set.
* Returns the index of MSB set.
*/
u8 spd_get_msbs(u8 c)
{
Expand Down
6 changes: 6 additions & 0 deletions src/device/dram/ddr3.c
View file
Expand Up @@ -559,6 +559,12 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
memset(mem_info, 0, sizeof(*mem_info));
}

if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) {
printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n",
__func__);
return CB_ERR;
}

dimm = &mem_info->dimm[mem_info->dimm_cnt];
if (info->size_mb) {
dimm->ddr_type = MEMORY_TYPE_DDR3;
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/generic/adau7002/adau7002.c
View file
Expand Up @@ -43,7 +43,7 @@ static void adau7002_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", ADAU7002_ACPI_HID);
acpigen_write_name_integer("_UID", 0);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/generic/max98357a/max98357a.c
View file
Expand Up @@ -43,7 +43,7 @@ static void max98357a_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", MAX98357A_ACPI_HID);
acpigen_write_name_integer("_UID", 0);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/da7219/da7219.c
View file
Expand Up @@ -51,7 +51,7 @@ static void da7219_fill_ssdt(struct device *dev)
acpigen_write_name_integer("_UID", 1);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
acpigen_write_name_integer("_S0W", 4);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/generic/generic.c
View file
Expand Up @@ -87,7 +87,7 @@ void i2c_generic_fill_ssdt(struct device *dev,
acpigen_write_name_string("_CID", config->cid);
acpigen_write_name_integer("_UID", config->uid);
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/max98373/max98373.c
View file
Expand Up @@ -51,7 +51,7 @@ static void max98373_fill_ssdt(struct device *dev)
acpigen_write_name_integer("_UID", config->uid);
if (config->desc)
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/max98927/max98927.c
View file
Expand Up @@ -49,7 +49,7 @@ static void max98927_fill_ssdt(struct device *dev)
acpigen_write_name_integer("_UID", config->uid);
if (config->desc)
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/nau8825/nau8825.c
View file
Expand Up @@ -55,7 +55,7 @@ static void nau8825_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", NAU8825_ACPI_HID);
acpigen_write_name_integer("_UID", 0);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/rt5663/rt5663.c
View file
Expand Up @@ -51,7 +51,7 @@ static void rt5663_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", RT5663_ACPI_HID);
acpigen_write_name_integer("_UID", config->uid);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/sx9310/sx9310.c
View file
Expand Up @@ -53,7 +53,7 @@ static void i2c_sx9310_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", I2C_SX9310_ACPI_ID);
acpigen_write_name_integer("_UID", config->uid);
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/tpm/chip.c
View file
Expand Up @@ -49,7 +49,7 @@ static void i2c_tpm_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", config->hid);
acpigen_write_name_integer("_UID", config->uid);
acpigen_write_name_string("_DDN", dev->chip_ops->name);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/intel/fsp1_0/fsp_util.c
View file
Expand Up @@ -15,6 +15,7 @@

#include <types.h>
#include <string.h>
#include <compiler.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
Expand Down Expand Up @@ -66,7 +67,7 @@ void FspNotify (u32 Phase)
* Call the FSP to do memory init. The FSP doesn't return to this function.
* The FSP returns to the romstage_main_continue().
*/
void __attribute__((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
{
FSP_FSP_INIT FspInitApi;
FSP_INIT_PARAMS FspInitParams;
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp1_1/fsp_relocate.c
View file
Expand Up @@ -40,7 +40,7 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src)
fih_offset = fsp1_1_relocate((uintptr_t)new_loc, new_loc, size);

if (fih_offset <= 0) {
printk(BIOS_ERR, "ERROR: FSP relocation faiulre.\n");
printk(BIOS_ERR, "ERROR: FSP relocation failure.\n");
return -1;
}

Expand Down
9 changes: 9 additions & 0 deletions src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -97,6 +97,15 @@ config FSP_M_XIP
help
Select this value when FSP-M is execute-in-place.

config FSP_USES_CB_STACK
bool
default n
help
Enable support for fsp to use same stack as coreboot.
This option allows fsp to continue using coreboot stack
without reinitializing stack pointer. This feature is
supported Icelake onwards.

config VERIFY_HOBS
bool "Verify the FSP hand-off-blocks"
default n
Expand Down
33 changes: 25 additions & 8 deletions src/drivers/intel/fsp2_0/memory_init.c
View file
Expand Up @@ -165,27 +165,44 @@ static enum cb_err check_region_overlap(const struct memranges *ranges,

return CB_SUCCESS;
}

static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
bool s3wake, uint32_t fsp_version,
const struct memranges *memmap)
static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd,
const struct memranges *memmap)
{
uintptr_t stack_begin;
uintptr_t stack_end;

/*
* FSPM_UPD passed here is populated with default values provided by
* the blob itself. We let FSPM use top of CAR region of the size it
* requests.
* FSP 2.1 version would use same stack as coreboot instead of
* setting up seprate stack frame. FSP 2.1 would not relocate stack
* top and does not reinitialize stack pointer.
*/
if (IS_ENABLED(CONFIG_FSP_USES_CB_STACK)) {
arch_upd->StackBase = (void *)_car_stack_end;
arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE;
return CB_SUCCESS;
}

/*
* FSPM_UPD passed here is populated with default values
* provided by the blob itself. We let FSPM use top of CAR
* region of the size it requests.
*/
stack_end = (uintptr_t)_car_region_end;
stack_begin = stack_end - arch_upd->StackSize;

if (check_region_overlap(memmap, "FSPM stack", stack_begin,
stack_end) != CB_SUCCESS)
return CB_ERR;

arch_upd->StackBase = (void *)stack_begin;
return CB_SUCCESS;
}

static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
bool s3wake, uint32_t fsp_version,
const struct memranges *memmap)
{
if (setup_fsp_stack_frame(arch_upd, memmap))
return CB_ERR;

fsp_fill_mrc_cache(arch_upd, fsp_version);

Expand Down
100 changes: 45 additions & 55 deletions src/drivers/intel/gma/acpi/configure_brightness_levels.asl
View file
Expand Up @@ -55,7 +55,7 @@
* * Driver not loaded or not ready
* * Driver reported an error during ASLE IRQ
*/
Method (XBCM, 1, NotSerialized)
Method (XBCM, 1, Serialized)
{
If (LEqual(ASLS, Zero))
{
Expand Down Expand Up @@ -89,45 +89,20 @@
While (LGreater(Local0, Zero))
{
Sleep (1)
If (LEqual(And(ShiftRight(ASLC, 12), 0x3), Zero))
{
Return (Zero)
If (LEqual (And (ASLC, 0x2), 0)) {
/* Request has been processed, check status: */
And (ShiftRight (ASLC, 12), 0x3, Local1)
If (LEqual (Local1, 0)) {
Return (Zero)
} Else {
Return (Ones)
}
}
Decrement (Local0)
}

Return (Ones)
}

/*
* Get current back-light brightness through mailbox 3
*
* @Return The current brightness or Ones on error
* Errors: * ASLS is zero
* * Mailbox 3 support not advertised
* * Driver not loaded or not ready
* * CBLV is not marked valid
*/
Method (XBQC, 0, NotSerialized)
{
If (LEqual(ASLS, Zero))
{
Return (Ones)
}
If (LEqual(And(MBOX, 0x4), Zero))
{
Return (Ones)
}
If (LEqual(ARDY, Zero))
{
Return (Ones)
}
If (LEqual(And (CBLV, 0x80000000), Zero))
{
Return (Ones)
}
Return (And (CBLV, 0xff))
}
}

/*
Expand All @@ -137,29 +112,45 @@
{
Name (_ADR, 0)

/* Divide round closest */
Method (DRCL, 2)
{
Return (Divide (Add (Arg0, Divide (Arg1, 2)), Arg1))
}

Method (XBCM, 1, NotSerialized)
{
Store (Divide (Multiply (Arg0, BCLM), 100), BCLV)
Store (DRCL (Multiply (Arg0, BCLM), 100), BCLV)
}

/* Find value closest to BCLV in BRIG (which must be ordered) */
Method (XBQC, 0, NotSerialized)
{
/* Find value close to BCLV in BRIG (which must be ordered) */
Store (BCLV, Local0) // Current value
Store (BCLM, Local1) // For calculations
Store (2, Local2) // Loop index
While (LLess (Local2, Subtract (SizeOf (BRIG), 1))) {
Store (DeRefOf (Index (BRIG, Local2)), Local3)
/* Use same calculation as XBCM, to get exact matches */
Store (Divide (Multiply (Local3, Local1), 100), Local3)

If (LLessEqual (Local0, Local3)) {
Return (DeRefOf (Index (BRIG, Local2)))
/* Local0: current percentage */
Store (DRCL (Multiply (BCLV, 100), BCLM), Local0)

/* Local1: loop index (selectable values start at 2 in BRIG) */
Store (2, Local1)
While (LLess (Local1, Subtract (SizeOf (BRIG), 1))) {
/* Local[23]: adjacent values in BRIG */
Store (DeRefOf (Index (BRIG, Local1)), Local2)
Store (DeRefOf (Index (BRIG, Add (Local1, 1))), Local3)

If (LLess (Local0, Local3)) {
If (LOr (LLess (Local0, Local2),
LLess (Subtract (Local0, Local2),
Subtract (Local3, Local0)))) {
Return (Local2)
} Else {
Return (Local3)
}
}
Add (Local2, 1, Local2)

Increment (Local1)
}

/* Didn't find greater/equal value: use the last */
Return (DeRefOf (Index (BRIG, Local2)))
Return (Local3)
}
}

Expand All @@ -173,11 +164,10 @@

Method (XBQC, 0, NotSerialized)
{
Store (^BOX3.XBQC (), Local0)
If (LEqual(Local0, Ones))
{
Store (^LEGA.XBQC (), Local0)
}

Return (Local0)
/*
* Always query the hardware directly. Not all OS drivers
* keep CBLV up to date (one is Linux' i915). Some years
* after that is fixed we can probably use CBLV?
*/
Return (^LEGA.XBQC ())
}
2 changes: 1 addition & 1 deletion src/drivers/intel/mipi_camera/camera.c
View file
Expand Up @@ -43,7 +43,7 @@ static void camera_fill_ssdt(struct device *dev)
acpigen_write_name_string("_HID", config->acpi_hid);
acpigen_write_name_integer("_UID", config->acpi_uid);
acpigen_write_name_string("_DDN", config->chip_name);
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
16 changes: 3 additions & 13 deletions src/drivers/lenovo/hybrid_graphics/romstage.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <southbridge/intel/common/gpio.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <console/console.h>
#include <delay.h>

#include "hybrid_graphics.h"
#include "chip.h"
Expand Down Expand Up @@ -87,18 +86,9 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
set_gpio(config->dgpu_power_gpio,
config->dgpu_power_off_lvl);
} else if (config->has_thinker1) {
const size_t power_en = !!(pmh7_register_read(0x50) & 0x08);
if (*enable_peg && !power_en) {
pmh7_register_clear_bit(0x50, 7); // DGPU_RST
pmh7_register_set_bit(0x50, 3); // DGPU_PWR
mdelay(10);
pmh7_register_set_bit(0x50, 7); // DGPU_RST
mdelay(50);
} else if (!*enable_peg && power_en) {
pmh7_register_clear_bit(0x50, 7); // DGPU_RST
udelay(100);
pmh7_register_clear_bit(0x50, 3); // DGPU_PWR
}
bool power_en = pmh7_dgpu_power_state();
if (*enable_peg != power_en)
pmh7_dgpu_power_enable(!power_en);
} else {
printk(BIOS_ERR, "Hybrid graphics:"
" FIXME: dGPU power handling not implemented\n");
Expand Down
1 change: 1 addition & 0 deletions src/drivers/spi/acpi/acpi.c
View file
Expand Up @@ -114,6 +114,7 @@ static void spi_acpi_fill_ssdt_generator(struct device *dev)
acpigen_write_name_integer("_UID", config->uid);
if (config->desc)
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(acpi_device_status(dev));

/* Resources */
acpigen_write_name("_CRS");
Expand Down
22 changes: 22 additions & 0 deletions src/drivers/spi/spi_flash.c
View file
Expand Up @@ -438,6 +438,28 @@ int spi_flash_read_sec(const struct spi_flash *flash, u32 offset, size_t len,
return flash->ops->read_sec(flash, offset, len, buf);
}

int spi_flash_is_write_protected(const struct spi_flash *flash,
const struct region *region)
{
struct region flash_region = { 0 };

if (!flash || !region)
return -1;

flash_region.size = flash->size;

if (!region_is_subregion(&flash_region, region))
return -1;

if (!flash->ops->get_write_protection) {
printk(BIOS_WARNING, "SPI: Write-protection gathering not "
"implemented for this vendor.\n");
return 0;
}

return flash->ops->get_write_protection(flash, region);
}

static uint32_t volatile_group_count CAR_GLOBAL;

int spi_flash_volatile_group_begin(const struct spi_flash *flash)
Expand Down
18 changes: 9 additions & 9 deletions src/drivers/spi/tpm/tpm.c
View file
Expand Up @@ -79,8 +79,8 @@ __weak int tis_plat_irq_status(void)
}

/*
* TPM may trigger a irq after finish processing previous transfer.
* Waiting for this irq to sync tpm status.
* TPM may trigger a IRQ after finish processing previous transfer.
* Waiting for this IRQ to sync TPM status.
*
* Returns 1 on success, 0 on failure (timeout).
*/
Expand All @@ -91,7 +91,7 @@ static int tpm_sync(void)
stopwatch_init_msecs_expire(&sw, 10);
while (!tis_plat_irq_status()) {
if (stopwatch_expired(&sw)) {
printk(BIOS_ERR, "Timeout wait for tpm irq!\n");
printk(BIOS_ERR, "Timeout wait for TPM IRQ!\n");
return 0;
}
}
Expand Down Expand Up @@ -119,7 +119,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned addr)
*/
int wakeup_needed = 1;

/* Wait for tpm to finish previous transaction if needed */
/* Wait for TPM to finish previous transaction if needed */
if (car_get_var(tpm_sync_needed)) {
tpm_sync();
/*
Expand Down Expand Up @@ -430,7 +430,7 @@ int tpm2_init(struct spi_slave *spi_if)

memcpy(spi_slave, spi_if, sizeof(*spi_if));

/* clear any pending irqs */
/* clear any pending IRQs */
tis_plat_irq_status();

/*
Expand All @@ -442,12 +442,12 @@ int tpm2_init(struct spi_slave *spi_if)
for (retries = 15; retries > 0; retries--) {
int i;

/* In case of falure to read div_vid is set to zero. */
/* In case of failure to read div_vid is set to zero. */
tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid));

for (i = 0; i < ARRAY_SIZE(supported_did_vids); i++)
if (did_vid == supported_did_vids[i])
break; /* Tpm is up and ready. */
break; /* TPM is up and ready. */

if (i < ARRAY_SIZE(supported_did_vids))
break;
Expand Down Expand Up @@ -643,7 +643,7 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
write_tpm_sts(TPM_STS_COMMAND_READY);

/*
* Tpm commands and responses written to and read from the FIFO
* TPM commands and responses written to and read from the FIFO
* register (0x24) are datagrams of variable size, prepended by a 6
* byte header.
*
Expand Down Expand Up @@ -687,7 +687,7 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
* TODO(vbendeb): at least drain the FIFO here or somehow let
* the TPM know that the response can be dropped.
*/
printk(BIOS_ERR, " tpm response too long (%zd bytes)",
printk(BIOS_ERR, " TPM response too long (%zd bytes)",
payload_size);
return 0;
}
Expand Down
154 changes: 154 additions & 0 deletions src/drivers/spi/winbond.c
View file
Expand Up @@ -9,6 +9,7 @@
#include <spi_flash.h>
#include <spi-generic.h>
#include <string.h>
#include <assert.h>

#include "spi_flash_internal.h"

Expand All @@ -17,6 +18,8 @@
#define CMD_W25_WRDI 0x04 /* Write Disable */
#define CMD_W25_RDSR 0x05 /* Read Status Register */
#define CMD_W25_WRSR 0x01 /* Write Status Register */
#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */
#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */
#define CMD_W25_READ 0x03 /* Read Data Bytes */
#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_W25_PP 0x02 /* Page Program */
Expand All @@ -37,9 +40,46 @@ struct winbond_spi_flash_params {
uint8_t pages_per_sector_shift : 4;
uint8_t sectors_per_block_shift : 4;
uint8_t nr_blocks_shift;
uint8_t bp_bits : 3;
uint8_t protection_granularity_shift : 5;
char name[10];
};

union status_reg1_bp3 {
uint8_t u;
struct {
uint8_t busy : 1;
uint8_t wel : 1;
uint8_t bp : 3;
uint8_t tb : 1;
uint8_t sec : 1;
uint8_t srp0 : 1;
};
};

union status_reg1_bp4 {
uint8_t u;
struct {
uint8_t busy : 1;
uint8_t wel : 1;
uint8_t bp : 4;
uint8_t tb : 1;
uint8_t srp0 : 1;
};
};

union status_reg2 {
uint8_t u;
struct {
uint8_t srp1 : 1;
uint8_t qe : 1;
uint8_t res : 1;
uint8_t lb : 3;
uint8_t cmp : 1;
uint8_t sus : 1;
};
};

static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
{
.id = 0x3015,
Expand Down Expand Up @@ -80,6 +120,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 5,
.name = "W25Q16",
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x4016,
Expand All @@ -88,6 +130,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 6,
.name = "W25Q32",
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x6016,
Expand All @@ -96,6 +140,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 6,
.name = "W25Q32DW",
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x4017,
Expand All @@ -104,6 +150,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 7,
.name = "W25Q64",
.protection_granularity_shift = 17,
.bp_bits = 3,
},
{
.id = 0x6017,
Expand All @@ -112,6 +160,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 7,
.name = "W25Q64DW",
.protection_granularity_shift = 17,
.bp_bits = 3,
},
{
.id = 0x4018,
Expand All @@ -120,6 +170,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 8,
.name = "W25Q128",
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x6018,
Expand All @@ -128,6 +180,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 8,
.name = "W25Q128FW",
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x4019,
Expand All @@ -136,6 +190,8 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.sectors_per_block_shift = 4,
.nr_blocks_shift = 9,
.name = "W25Q256",
.protection_granularity_shift = 16,
.bp_bits = 4,
},
};

Expand Down Expand Up @@ -225,6 +281,102 @@ static int winbond_sec_read(const struct spi_flash *flash, u32 offset,
return ret;
}

/*
* Convert BPx, TB and CMP to a region.
* SEC (if available) must be zero.
*/
static void winbond_bpbits_to_region(const size_t granularity,
const u8 bp,
bool tb,
const bool cmp,
const size_t flash_size,
struct region *out)
{
size_t protected_size =
min(bp ? granularity << (bp - 1) : 0, flash_size);

if (cmp) {
protected_size = flash_size - protected_size;
tb = !tb;
}

out->offset = tb ? flash_size - protected_size : 0;
out->size = protected_size;
}

/*
* Available on all devices.
* Read block protect bits from Status/Status2 Reg.
* Converts block protection bits to a region.
*
* Returns:
* -1 on error
* 1 if region is covered by write protection
* 0 if a part of region isn't covered by write protection
*/
static int winbond_get_write_protection(const struct spi_flash *flash,
const struct region *region)
{
const struct winbond_spi_flash_params *params;
struct region wp_region;
union status_reg2 reg2;
u8 bp, tb;
int ret;

params = (const struct winbond_spi_flash_params *)flash->driver_private;
const size_t granularity = (1 << params->protection_granularity_shift);

if (params->bp_bits == 3) {
union status_reg1_bp3 reg1_bp3;

ret = spi_flash_cmd(&flash->spi, flash->status_cmd, &reg1_bp3.u,
sizeof(reg1_bp3.u));
if (ret)
return ret;

if (reg1_bp3.sec) {
// FIXME: not supported
return -1;
}

bp = reg1_bp3.bp;
tb = reg1_bp3.tb;
} else if (params->bp_bits == 4) {
union status_reg1_bp4 reg1_bp4;

ret = spi_flash_cmd(&flash->spi, flash->status_cmd, &reg1_bp4.u,
sizeof(reg1_bp4.u));
if (ret)
return ret;

bp = reg1_bp4.bp;
tb = reg1_bp4.tb;
} else {
// FIXME: not supported
return -1;
}

ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, &reg2.u,
sizeof(reg2.u));
if (ret)
return ret;

winbond_bpbits_to_region(granularity, bp, tb, reg2.cmp, flash->size,
&wp_region);

if (!reg2.srp1 || !wp_region.size) {
printk(BIOS_DEBUG, "WINBOND: flash isn't protected\n");

return 0;
}

printk(BIOS_DEBUG, "WINBOND: flash protected range 0x%08zx-0x%08zx\n",
wp_region.offset, wp_region.size);

return region_is_subregion(&wp_region, region);
}


static const struct spi_flash_ops spi_flash_ops = {
.write = winbond_write,
.erase = spi_flash_cmd_erase,
Expand All @@ -235,6 +387,7 @@ static const struct spi_flash_ops spi_flash_ops = {
.read = spi_flash_cmd_read_fast,
#endif
.read_sec = winbond_sec_read,
.get_write_protection = winbond_get_write_protection,
};

int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode,
Expand Down Expand Up @@ -269,6 +422,7 @@ int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode,
flash->status_cmd = CMD_W25_RDSR;

flash->ops = &spi_flash_ops;
flash->driver_private = params;

return 0;
}
15 changes: 11 additions & 4 deletions src/drivers/uart/sifive.c
View file
Expand Up @@ -46,11 +46,10 @@ struct sifive_uart_registers {
#define IP_TXWM BIT(0)
#define IP_RXWM BIT(1)

void uart_init(int idx)
static void sifive_uart_init(struct sifive_uart_registers *regs, int div)
{
struct sifive_uart_registers *regs = uart_platform_baseptr(idx);

/* TODO: Configure the divisor */
/* Configure the divisor */
write32(&regs->div, div);

/* Enable transmission, one stop bit, transmit watermark at 1 */
write32(&regs->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1));
Expand All @@ -59,6 +58,14 @@ void uart_init(int idx)
write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
}

void uart_init(int idx)
{
unsigned int div;
div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
sifive_uart_init(uart_platform_baseptr(idx), div);
}

static bool uart_can_tx(struct sifive_uart_registers *regs)
{
return !(read32(&regs->txdata) & TXDATA_FULL);
Expand Down
24 changes: 12 additions & 12 deletions ...ard/intel/coffeelake_rvp/spd/Makefile.inc → src/drivers/vpd/Kconfig
View file
@@ -1,8 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
## Copyright (C) 2018 Intel Corporation.
## Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
Expand All @@ -14,15 +13,16 @@
## GNU General Public License for more details.
##

romstage-y += spd_util.c
config VPD
bool "Support for Vital Product Data tables"
default n
help
Enable support for flash based vital product data.

SPD_BIN = $(obj)/spd.bin
if VPD

SPD_SOURCES = empty # 0b000
SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB
SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB
SPD_SOURCES += empty # 0b011
SPD_SOURCES += empty # 0b100
SPD_SOURCES += empty # 0b101
SPD_SOURCES += empty # 0b110
SPD_SOURCES += empty # 0b111
config VPD_DEBUG
bool "Enable VPD debug output"
default n

endif
2 changes: 2 additions & 0 deletions src/drivers/vpd/Makefile.inc
View file
@@ -0,0 +1,2 @@
romstage-$(CONFIG_VPD) += lib_vpd.c
ramstage-$(CONFIG_VPD) += vpd.c lib_vpd.c
113 changes: 113 additions & 0 deletions src/drivers/vpd/lib_vpd.c
View file
@@ -0,0 +1,113 @@
/*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
*/
#include <assert.h>
#include "lib_vpd.h"

/* Given an encoded string, this functions decodes the length field which varies
* from 1 byte to many bytes.
*
* The in points the actual byte going to be decoded. The *length returns
* the decoded length field. The number of consumed bytes will be stroed in
* decoded_len.
*
* Returns VPD_FAIL if more bit is 1, but actually reaches the end of string.
*/
int decodeLen(const int32_t max_len,
const uint8_t *in,
int32_t *length,
int32_t *decoded_len)
{
uint8_t more;
int i = 0;

assert(length);
assert(decoded_len);

*length = 0;
do {
if (i >= max_len)
return VPD_FAIL;

more = in[i] & 0x80;
*length <<= 7;
*length |= in[i] & 0x7f;
++i;
} while (more);

*decoded_len = i;

return VPD_OK;
}

/* Given the encoded string, this function invokes callback with extracted
* (key, value). The *consumed will be plused the number of bytes consumed in
* this function.
*
* The input_buf points to the first byte of the input buffer.
*
* The *consumed starts from 0, which is actually the next byte to be decoded.
* It can be non-zero to be used in multiple calls.
*
* If one entry is successfully decoded, sends it to callback and returns the
* result.
*/
int decodeVpdString(const int32_t max_len,
const uint8_t *input_buf,
int32_t *consumed,
VpdDecodeCallback callback,
void *callback_arg)
{
int type;
int32_t key_len, value_len;
int32_t decoded_len;
const uint8_t *key, *value;

/* type */
if (*consumed >= max_len)
return VPD_FAIL;

type = input_buf[*consumed];
switch (type) {
case VPD_TYPE_INFO:
case VPD_TYPE_STRING:
(*consumed)++;
/* key */
if (VPD_OK != decodeLen(max_len - *consumed,
&input_buf[*consumed], &key_len,
&decoded_len) ||
*consumed + decoded_len >= max_len) {
return VPD_FAIL;
}

*consumed += decoded_len;
key = &input_buf[*consumed];
*consumed += key_len;

/* value */
if (VPD_OK != decodeLen(max_len - *consumed,
&input_buf[*consumed],
&value_len, &decoded_len) ||
*consumed + decoded_len > max_len) {
return VPD_FAIL;
}
*consumed += decoded_len;
value = &input_buf[*consumed];
*consumed += value_len;

if (type == VPD_TYPE_STRING)
return callback(key, key_len, value, value_len,
callback_arg);

return VPD_OK;

default:
return VPD_FAIL;
break;
}

return VPD_OK;
}
32 changes: 16 additions & 16 deletions src/vendorcode/google/chromeos/lib_vpd.h → src/drivers/vpd/lib_vpd.h
View file
Expand Up @@ -11,25 +11,25 @@
#include <inttypes.h>

enum {
VPD_OK = 0,
VPD_FAIL,
VPD_OK = 0,
VPD_FAIL,
};

enum {
VPD_TYPE_TERMINATOR = 0,
VPD_TYPE_STRING,
VPD_TYPE_INFO = 0xfe,
VPD_TYPE_IMPLICIT_TERMINATOR = 0xff,
VPD_TYPE_TERMINATOR = 0,
VPD_TYPE_STRING,
VPD_TYPE_INFO = 0xfe,
VPD_TYPE_IMPLICIT_TERMINATOR = 0xff,
};

enum {
VPD_AS_LONG_AS = -1,
VPD_AS_LONG_AS = -1,
};

enum { /* export_type */
VPD_EXPORT_KEY_VALUE = 1,
VPD_EXPORT_VALUE,
VPD_EXPORT_AS_PARAMETER,
VPD_EXPORT_KEY_VALUE = 1,
VPD_EXPORT_VALUE,
VPD_EXPORT_AS_PARAMETER,
};

/* Callback for decodeVpdString to invoke. */
Expand All @@ -39,15 +39,15 @@ typedef int VpdDecodeCallback(const uint8_t *key, int32_t key_len,

/* Container data types */
struct StringPair {
uint8_t *key;
uint8_t *value;
int pad_len;
int filter_out; /* TRUE means not exported. */
struct StringPair *next;
uint8_t *key;
uint8_t *value;
int pad_len;
int filter_out; /* TRUE means not exported. */
struct StringPair *next;
};

struct PairContainer {
struct StringPair *first;
struct StringPair *first;
};


Expand Down
23 changes: 15 additions & 8 deletions src/vendorcode/google/chromeos/cros_vpd.c → src/drivers/vpd/vpd.c
View file
Expand Up @@ -5,14 +5,13 @@
*/

#include <console/console.h>

#include <cbmem.h>
#include <fmap.h>
#include <stdlib.h>
#include <string.h>
#include <timestamp.h>

#include "cros_vpd.h"
#include "vpd.h"
#include "lib_vpd.h"
#include "vpd_tables.h"

Expand Down Expand Up @@ -178,7 +177,7 @@ static int vpd_gets_callback(const uint8_t *key, int32_t key_len,
return VPD_FAIL;
}

const void *cros_vpd_find(const char *key, int *size)
const void *vpd_find(const char *key, int *size, enum vpd_region region)
{
struct vpd_gets_arg arg = {0};
int consumed = 0;
Expand All @@ -191,10 +190,18 @@ const void *cros_vpd_find(const char *key, int *size)
arg.key = (const uint8_t *)key;
arg.key_len = strlen(key);

while (VPD_OK == decodeVpdString(vpd->ro_size, vpd->blob, &consumed,
vpd_gets_callback, &arg)) {
if (region == VPD_ANY || region == VPD_RO)
while (VPD_OK == decodeVpdString(vpd->ro_size, vpd->blob,
&consumed, vpd_gets_callback, &arg)) {
/* Iterate until found or no more entries. */
}
}

if (!arg.matched && region != VPD_RO)
while (VPD_OK == decodeVpdString(vpd->rw_size,
vpd->blob + vpd->ro_size, &consumed,
vpd_gets_callback, &arg)) {
/* Iterate until found or no more entries. */
}

if (!arg.matched)
return NULL;
Expand All @@ -203,12 +210,12 @@ const void *cros_vpd_find(const char *key, int *size)
return arg.value;
}

char *cros_vpd_gets(const char *key, char *buffer, int size)
char *vpd_gets(const char *key, char *buffer, int size, enum vpd_region region)
{
const void *string_address;
int string_size;

string_address = cros_vpd_find(key, &string_size);
string_address = vpd_find(key, &string_size, region);

if (!string_address)
return NULL;
Expand Down
18 changes: 10 additions & 8 deletions src/vendorcode/google/chromeos/cros_vpd.h → src/drivers/vpd/vpd.h
View file
Expand Up @@ -4,12 +4,14 @@
* found in the LICENSE file.
*/

#ifndef __CROS_VPD_H__
#define __CROS_VPD_H__

#define CROS_VPD_REGION_NAME "region"
#define CROS_VPD_WIFI_SAR_NAME "wifi_sar"
#ifndef __VPD_H__
#define __VPD_H__

enum vpd_region {
VPD_ANY = 0,
VPD_RO = 1,
VPD_RW = 2
};
/*
* Reads VPD string value by key.
*
Expand All @@ -19,7 +21,7 @@
*
* Returns NULL if key is not found, otherwise buffer.
*/
char *cros_vpd_gets(const char *key, char *buffer, int size);
char *vpd_gets(const char *key, char *buffer, int size, enum vpd_region region);

/*
* Find VPD value by key.
Expand All @@ -35,6 +37,6 @@ char *cros_vpd_gets(const char *key, char *buffer, int size);
* Returns NULL if key is not found.
*/

const void *cros_vpd_find(const char *key, int *size);
const void *vpd_find(const char *key, int *size, enum vpd_region region);

#endif /* __CROS_VPD_H__ */
#endif /* __VPD_H__ */
0 src/vendorcode/google/chromeos/vpd_tables.h → src/drivers/vpd/vpd_tables.h
View file
File renamed without changes.
56 changes: 28 additions & 28 deletions src/ec/google/chromeec/acpi/superio.asl
View file
Expand Up @@ -131,43 +131,43 @@ Device (SIO) {
})
}
#endif
}

#ifdef SIO_EC_ENABLE_PS2K
Device (PS2K) // Keyboard
{
Name (_UID, 0)
Name (_ADR, 0)
Name (_HID, "GOOG000A")
Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } )
Device (PS2K) // Keyboard
{
Name (_UID, 0)
Name (_ADR, 0)
Name (_HID, "GOOG000A")
Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } )

Method (_STA, 0, NotSerialized) {
Return (0x0F)
}
Method (_STA, 0, NotSerialized) {
Return (0x0F)
}

Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
#ifdef SIO_EC_PS2K_IRQ
SIO_EC_PS2K_IRQ
SIO_EC_PS2K_IRQ
#else
IRQ (Edge, ActiveHigh, Exclusive) {1}
IRQ (Edge, ActiveHigh, Exclusive) {1}
#endif
})
})

Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0) {
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0) {
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
#ifdef SIO_EC_PS2K_IRQ
SIO_EC_PS2K_IRQ
SIO_EC_PS2K_IRQ
#else
IRQ (Edge, ActiveHigh, Exclusive) {1}
#endif
}
EndDependentFn ()
})
}
IRQ (Edge, ActiveHigh, Exclusive) {1}
#endif
}
EndDependentFn ()
})
}
#endif
27 changes: 25 additions & 2 deletions src/ec/lenovo/pmh7/pmh7.c
View file
Expand Up @@ -19,6 +19,7 @@
#include <device/pnp.h>
#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <delay.h>

#include "pmh7.h"
#include "chip.h"
Expand Down Expand Up @@ -64,6 +65,26 @@ void pmh7_ultrabay_power_enable(int onoff)
pmh7_register_set_bit(0x62, 0);
}

void pmh7_dgpu_power_enable(int onoff)
{
if (onoff) {
pmh7_register_clear_bit(0x50, 7); // DGPU_RST
pmh7_register_set_bit(0x50, 3); // DGPU_PWR
mdelay(10);
pmh7_register_set_bit(0x50, 7); // DGPU_RST
mdelay(50);
} else {
pmh7_register_clear_bit(0x50, 7); // DGPU_RST
udelay(100);
pmh7_register_clear_bit(0x50, 3); // DGPU_PWR
}
}

bool pmh7_dgpu_power_state(void)
{
return (pmh7_register_read(0x50) & 0x08) == 8;
}

void pmh7_register_set_bit(int reg, int bit)
{
char val;
Expand All @@ -82,13 +103,15 @@ void pmh7_register_clear_bit(int reg, int bit)

char pmh7_register_read(int reg)
{
outb(reg, EC_LENOVO_PMH7_ADDR);
outb(reg & 0xff, EC_LENOVO_PMH7_ADDR_L);
outb((reg & 0xff00) >> 8, EC_LENOVO_PMH7_ADDR_H);
return inb(EC_LENOVO_PMH7_DATA);
}

void pmh7_register_write(int reg, int val)
{
outb(reg, EC_LENOVO_PMH7_ADDR);
outb(reg & 0xff, EC_LENOVO_PMH7_ADDR_L);
outb((reg & 0xff00) >> 8, EC_LENOVO_PMH7_ADDR_H);
outb(val, EC_LENOVO_PMH7_DATA);
}

Expand Down
5 changes: 4 additions & 1 deletion src/ec/lenovo/pmh7/pmh7.h
View file
Expand Up @@ -19,7 +19,8 @@
#define EC_LENOVO_PMH7_INDEX 0x77

#define EC_LENOVO_PMH7_BASE 0x15e0
#define EC_LENOVO_PMH7_ADDR (EC_LENOVO_PMH7_BASE + 0x0c)
#define EC_LENOVO_PMH7_ADDR_L (EC_LENOVO_PMH7_BASE + 0x0c)
#define EC_LENOVO_PMH7_ADDR_H (EC_LENOVO_PMH7_BASE + 0x0d)
#define EC_LENOVO_PMH7_DATA (EC_LENOVO_PMH7_BASE + 0x0e)

#define EC_LENOVO_PMH7_REG_ID 0xc2
Expand All @@ -35,5 +36,7 @@ void pmh7_dock_event_enable(int onoff);
void pmh7_touchpad_enable(int onoff);
void pmh7_ultrabay_power_enable(int onoff);
void pmh7_trackpoint_enable(int onoff);
void pmh7_dgpu_power_enable(int onoff);
bool pmh7_dgpu_power_state(void);

#endif /* EC_LENOVO_PMH7_H */
2 changes: 2 additions & 0 deletions src/include/compiler.h
View file
Expand Up @@ -26,5 +26,7 @@
#define __always_unused __attribute__((unused))
#define __must_check __attribute__((warn_unused_result))
#define __weak __attribute__((weak))
#define __noreturn __attribute__((noreturn))
#define __always_inline inline __attribute__((always_inline))

#endif
3 changes: 2 additions & 1 deletion src/include/console/console.h
View file
Expand Up @@ -19,6 +19,7 @@
#include <stdint.h>
#include <rules.h>
#include <arch/cpu.h>
#include <compiler.h>
#include <console/post_codes.h>
#include <commonlib/loglevel.h>

Expand All @@ -40,7 +41,7 @@ void post_log_clear(void);
#endif
/* this function is weak and can be overridden by a mainboard function. */
void mainboard_post(u8 value);
void __attribute__((noreturn)) die(const char *msg);
void __noreturn die(const char *msg);

/*
* This function is weak and can be overridden to provide additional
Expand Down
508 changes: 508 additions & 0 deletions src/include/cper.h
View file

Large diffs are not rendered by default.

166 changes: 166 additions & 0 deletions src/include/cpu/amd/amdfam15.h
View file
Expand Up @@ -16,13 +16,179 @@
#ifndef CPU_AMD_FAM15_H
#define CPU_AMD_FAM15_H

#include <types.h>
#include <cpu/x86/msr.h>

#define MCG_CAP 0x00000179
# define MCA_BANKS_MASK 0xff
#define MC0_CTL 0x00000400
#define MC0_STATUS 0x00000401
# define MCA_STATUS_HI_VAL BIT(63 - 32)
# define MCA_STATUS_HI_OVERFLOW BIT(62 - 32)
# define MCA_STATUS_HI_UC BIT(61 - 32)
# define MCA_STATUS_HI_EN BIT(60 - 32)
# define MCA_STATUS_HI_MISCV BIT(59 - 32)
# define MCA_STATUS_HI_ADDRV BIT(58 - 32)
# define MCA_STATUS_HI_PCC BIT(57 - 32)
# define MCA_STATUS_HI_COREID_VAL BIT(56 - 32)
# define MCA_STATUS_HI_CECC BIT(46 - 32)
# define MCA_STATUS_HI_UECC BIT(45 - 32)
# define MCA_STATUS_HI_DEFERRED BIT(44 - 32)
# define MCA_STATUS_HI_POISON BIT(43 - 32)
# define MCA_STATUS_HI_SUBLINK BIT(41 - 32)
# define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)
# define MCA_STATUS_LO_ERRCODE_EXT_SH 16
# define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
# define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define MC0_ADDR 0x00000402
#define MC0_MISC 0x00000403
#define MC0_CTL_MASK 0xC0010044

/* Helpers for interpreting MC[i]_STATUS */

static inline int mca_valid(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_VAL);
}

static inline int mca_over(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
}

static inline int mca_uc(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_UC);
}

static inline int mca_en(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_EN);
}

static inline int mca_miscv(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_MISCV);
}

static inline int mca_addrv(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_ADDRV);
}

static inline int mca_pcc(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_PCC);
}

static inline int mca_idv(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
}

static inline int mca_cecc(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_CECC);
}

static inline int mca_uecc(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_UECC);
}

static inline int mca_defd(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
}

static inline int mca_poison(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_POISON);
}

static inline int mca_sublink(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
}

static inline uint16_t mca_err_code(msr_t reg)
{
return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;
}

static inline uint16_t mca_err_extcode(msr_t reg)
{
return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;
}

/* Machine Check errors may be categorized by type, as determined by the
* Error Code field of MC[i]_STATUS. The definitions below can typically
* be found by searching the BKDG for a table called "Error Code Types".
*/
/* TLB Errors 0000 0000 0001 TTLL */
#define MCA_ERRCODE_TLB_DETECT 0xfff0
#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */
#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)
#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */
#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)

/* Memory Errors 0000 0001 RRRR TTLL */
#define MCA_ERRCODE_MEM_DETECT 0xff00
#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */
#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)
#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */
#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)
#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */
#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)

/* Bus Errors 0000 1PPT RRRR IILL */
#define MCA_ERRCODE_BUS_DETECT 0xf800
#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */
#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)
#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */
#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)
#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */
#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)
#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */
#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)
#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */
#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)

/* Int. Unclassified Errors 0000 01UU 0000 0000 */
#define MCA_ERRCODE_INT_DETECT 0xfc00
#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */
#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)

#define MCA_BANK_LS 0 /* Load-store, including DC */
#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */
#define MCA_BANK_CU 2 /* Combined Unit, including L2 */
/* bank 3 reserved */
#define MCA_BANK_NB 4 /* Northbridge, including IO link */
#define MCA_BANK_EX 5 /* Execution Unit */
#define MCA_BANK_FP 6 /* Floating Point */

enum mca_err_code_types {
MCA_ERRTYPE_UNKNOWN,
MCA_ERRTYPE_TLB,
MCA_ERRTYPE_MEM,
MCA_ERRTYPE_BUS,
MCA_ERRTYPE_INT
};

static inline enum mca_err_code_types mca_err_type(msr_t reg)
{
uint16_t error = mca_err_code(reg);
if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */
return MCA_ERRTYPE_BUS;
if (error & MCA_ERRCODE_INT_DETECT)
return MCA_ERRTYPE_INT;
if (error & MCA_ERRCODE_MEM_DETECT)
return MCA_ERRTYPE_MEM;
if (error & MCA_ERRCODE_TLB_DETECT)
return MCA_ERRTYPE_TLB;
return MCA_ERRTYPE_UNKNOWN;
}

#define MSR_SMM_BASE 0xC0010111
#define MSR_TSEG_BASE 0xC0010112
#define MSR_SMM_MASK 0xC0010113
Expand Down
6 changes: 3 additions & 3 deletions src/include/cpu/amd/mtrr.h
View file
Expand Up @@ -38,13 +38,14 @@

#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)

#include <compiler.h>
#include <cpu/x86/msr.h>

void amd_setup_mtrrs(void);
struct device;
void add_uma_resource_below_tolm(struct device *nb, int idx);

static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
static __always_inline msr_t rdmsr_amd(unsigned int index)
{
msr_t result;
__asm__ __volatile__ (
Expand All @@ -55,8 +56,7 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
return result;
}

static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index,
msr_t msr)
static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
Expand Down
9 changes: 5 additions & 4 deletions src/include/cpu/x86/cache.h
View file
Expand Up @@ -16,6 +16,7 @@
#ifndef CPU_X86_CACHE
#define CPU_X86_CACHE

#include <compiler.h>
#include <cpu/x86/cr.h>

#define CR0_CacheDisable (CR0_CD)
Expand Down Expand Up @@ -55,25 +56,25 @@ static inline void clflush(void *addr)
asm volatile ("clflush (%0)"::"r" (addr));
}

/* The following functions require the always_inline due to AMD
/* The following functions require the __always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* RAM, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
* declared as inline are not being inlined. This patch forces
* these functions to always be inlined by adding the qualifier
* __attribute__((always_inline)) to their declaration.
* __always_inline to their declaration.
*/
static inline __attribute__((always_inline)) void enable_cache(void)
static __always_inline void enable_cache(void)
{
unsigned long cr0;
cr0 = read_cr0();
cr0 &= ~(CR0_CD | CR0_NW);
write_cr0(cr0);
}

static inline __attribute__((always_inline)) void disable_cache(void)
static __always_inline void disable_cache(void)
{
/* Disable and write back the cache */
unsigned long cr0;
Expand Down
15 changes: 8 additions & 7 deletions src/include/cpu/x86/cr.h
View file
Expand Up @@ -18,6 +18,7 @@

#if !defined(__ASSEMBLER__)

#include <compiler.h>
#include <stdint.h>
#include <arch/cpu.h>

Expand All @@ -37,7 +38,7 @@
#define CRx_IN "r"
#define CRx_RET "=r"
#endif
static alwaysinline CRx_TYPE read_cr0(void)
static __always_inline CRx_TYPE read_cr0(void)
{
CRx_TYPE value;
__asm__ __volatile__ (
Expand All @@ -49,7 +50,7 @@ static alwaysinline CRx_TYPE read_cr0(void)
return value;
}

static alwaysinline void write_cr0(CRx_TYPE data)
static __always_inline void write_cr0(CRx_TYPE data)
{
__asm__ __volatile__ (
"mov %0, %%cr0"
Expand All @@ -59,7 +60,7 @@ static alwaysinline void write_cr0(CRx_TYPE data)
);
}

static alwaysinline CRx_TYPE read_cr2(void)
static __always_inline CRx_TYPE read_cr2(void)
{
CRx_TYPE value;
__asm__ __volatile__ (
Expand All @@ -71,7 +72,7 @@ static alwaysinline CRx_TYPE read_cr2(void)
return value;
}

static alwaysinline CRx_TYPE read_cr3(void)
static __always_inline CRx_TYPE read_cr3(void)
{
CRx_TYPE value;
__asm__ __volatile__ (
Expand All @@ -83,7 +84,7 @@ static alwaysinline CRx_TYPE read_cr3(void)
return value;
}

static alwaysinline void write_cr3(CRx_TYPE data)
static __always_inline void write_cr3(CRx_TYPE data)
{
__asm__ __volatile__ (
"mov %0, %%cr3"
Expand All @@ -92,7 +93,7 @@ static alwaysinline void write_cr3(CRx_TYPE data)
: COMPILER_BARRIER
);
}
static alwaysinline CRx_TYPE read_cr4(void)
static __always_inline CRx_TYPE read_cr4(void)
{
CRx_TYPE value;
__asm__ __volatile__ (
Expand All @@ -104,7 +105,7 @@ static alwaysinline CRx_TYPE read_cr4(void)
return value;
}

static alwaysinline void write_cr4(CRx_TYPE data)
static __always_inline void write_cr4(CRx_TYPE data)
{
__asm__ __volatile__ (
"mov %0, %%cr4"
Expand Down
13 changes: 6 additions & 7 deletions src/include/cpu/x86/lapic.h
View file
@@ -1,24 +1,23 @@
#ifndef CPU_X86_LAPIC_H
#define CPU_X86_LAPIC_H

#include <compiler.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/msr.h>
#include <halt.h>
#include <smp/node.h>

static inline __attribute__((always_inline)) unsigned long lapic_read(
unsigned long reg)
static __always_inline unsigned long lapic_read(unsigned long reg)
{
return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
}

static inline __attribute__((always_inline)) void lapic_write(unsigned long reg,
unsigned long v)
static __always_inline void lapic_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
}

static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
static __always_inline void lapic_wait_icr_idle(void)
{
do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
}
Expand All @@ -42,7 +41,7 @@ static inline void disable_lapic(void)
wrmsr(LAPIC_BASE_MSR, msr);
}

static inline __attribute__((always_inline)) unsigned long lapicid(void)
static __always_inline unsigned long lapicid(void)
{
return lapic_read(LAPIC_ID) >> 24;
}
Expand All @@ -51,7 +50,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
/* If we need to go back to sipi wait, we use the long non-inlined version of
* this function in lapic_cpu_init.c
*/
static inline __attribute__((always_inline)) void stop_this_cpu(void)
static __always_inline void stop_this_cpu(void)
{
/* Called by an AP when it is ready to halt and wait for a new task */
halt();
Expand Down
16 changes: 8 additions & 8 deletions src/include/cpu/x86/msr.h
View file
@@ -1,6 +1,8 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H

#include <compiler.h>

/* Intel SDM: Table 2-1
* IA-32 architectural MSR: Extended Feature Enable Register
*/
Expand Down Expand Up @@ -50,29 +52,28 @@ msr_t soc_msr_read(unsigned int index);
void soc_msr_write(unsigned int index, msr_t msr);

/* Handle MSR references in the other source code */
static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
static __always_inline msr_t rdmsr(unsigned int index)
{
return soc_msr_read(index);
}

static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
msr_t msr)
static __always_inline void wrmsr(unsigned int index, msr_t msr)
{
soc_msr_write(index, msr);
}
#else /* CONFIG_SOC_SETS_MSRS */

/* The following functions require the always_inline due to AMD
/* The following functions require the __always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* RAM, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
* declared as inline are not being inlined. This patch forces
* these functions to always be inlined by adding the qualifier
* __attribute__((always_inline)) to their declaration.
* __always_inline to their declaration.
*/
static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
static __always_inline msr_t rdmsr(unsigned int index)
{
msr_t result;
__asm__ __volatile__ (
Expand All @@ -83,8 +84,7 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
return result;
}

static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
msr_t msr)
static __always_inline void wrmsr(unsigned int index, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
Expand Down
1 change: 1 addition & 0 deletions src/include/device/device.h
View file
Expand Up @@ -133,6 +133,7 @@ struct device {
unsigned int initialized : 1; /* 1 if we have initialized the device */
unsigned int on_mainboard : 1;
unsigned int disable_pcie_aspm : 1;
unsigned int hidden : 1; /* set if we should hide from UI */
struct pci_irq_info pci_irq_info[4];
u8 command;

Expand Down
13 changes: 7 additions & 6 deletions src/include/device/pci_ops.h
View file
@@ -1,6 +1,7 @@
#ifndef PCI_OPS_H
#define PCI_OPS_H

#include <compiler.h>
#include <stdint.h>
#include <device/device.h>
#include <arch/pci_ops.h>
Expand All @@ -19,28 +20,28 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val);
* Use device_t here as the functions are to be used with either
* __SIMPLE_DEVICE__ defined or undefined.
*/
static inline __attribute__((always_inline))
static __always_inline
void pci_or_config8(device_t dev, unsigned int where, u8 ormask)
{
u8 value = pci_read_config8(dev, where);
pci_write_config8(dev, where, value | ormask);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_or_config16(device_t dev, unsigned int where, u16 ormask)
{
u16 value = pci_read_config16(dev, where);
pci_write_config16(dev, where, value | ormask);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_or_config32(device_t dev, unsigned int where, u32 ormask)
{
u32 value = pci_read_config32(dev, where);
pci_write_config32(dev, where, value | ormask);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
{
u8 reg8;
Expand All @@ -51,7 +52,7 @@ void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
pci_write_config8(dev, reg, reg8);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
{
u16 reg16;
Expand All @@ -62,7 +63,7 @@ void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
pci_write_config16(dev, reg, reg16);
}

static inline __attribute__((always_inline))
static __always_inline
void pci_update_config32(device_t dev, int reg, u32 mask, u32 or)
{
u32 reg32;
Expand Down
3 changes: 2 additions & 1 deletion src/include/halt.h
View file
Expand Up @@ -20,10 +20,11 @@
#ifdef __ROMCC__
#include <lib/halt.c>
#else
#include <compiler.h>
/**
* halt the system reliably
*/
void __attribute__((noreturn)) halt(void);
void __noreturn halt(void);
#endif /* __ROMCC__ */

/* Power off the system. */
Expand Down
8 changes: 5 additions & 3 deletions src/include/reset.h
View file
@@ -1,14 +1,16 @@
#ifndef RESET_H
#define RESET_H

#include <compiler.h>

/* Generic reset functions. Call from code that wants to trigger a reset. */

/* Super-hard reset specific to some Intel SoCs. */
__attribute__((noreturn)) void global_reset(void);
__noreturn void global_reset(void);
/* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */
__attribute__((noreturn)) void hard_reset(void);
__noreturn void hard_reset(void);
/* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */
__attribute__((noreturn)) void soft_reset(void);
__noreturn void soft_reset(void);

/* Reset implementations. Implement these in SoC or mainboard code. Implement
at least hard_reset() if possible, others fall back to it if necessary. */
Expand Down
26 changes: 26 additions & 0 deletions src/include/spi_flash.h
View file
Expand Up @@ -42,6 +42,16 @@ struct spi_flash_ops {
int (*status)(const struct spi_flash *flash, u8 *reg);
int (*read_sec)(const struct spi_flash *flash, u32 offset, size_t len,
void *buf);
/*
* Returns 1 if the whole region is software write protected.
* Hardware write protection mechanism aren't accounted.
* If the write protection could be changed, due to unlocked status
* register for example, 0 should be returned.
* Returns -1 on error.
*/
int (*get_write_protection)(const struct spi_flash *flash,
const struct region *region);

};

struct spi_flash {
Expand All @@ -53,6 +63,7 @@ struct spi_flash {
u8 erase_cmd;
u8 status_cmd;
const struct spi_flash_ops *ops;
const void *driver_private;
};

void lb_spi_flash(struct lb_header *header);
Expand Down Expand Up @@ -98,6 +109,21 @@ int spi_flash_status(const struct spi_flash *flash, u8 *reg);
int spi_flash_read_sec(const struct spi_flash * flash, u32 offset, size_t len,
void *buf);

/*
* Return the vendor dependent SPI flash write protection state.
* @param flash : A SPI flash device
* @param region: A subregion of the device's region
*
* Returns:
* -1 on error
* 0 if the device doesn't support block protection
* 0 if the device doesn't enable block protection
* 0 if given range isn't covered by block protection
* 1 if given range is covered by block protection
*/
int spi_flash_is_write_protected(const struct spi_flash *flash,
const struct region *region);

/*
* Some SPI controllers require exclusive access to SPI flash when volatile
* operations like erase or write are being performed. In such cases,
Expand Down
42 changes: 42 additions & 0 deletions src/include/uuid.h
View file
@@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010, Intel Corp. Huang Ying <ying.huang@intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#ifndef _UUID_H_
#define _UUID_H_

#include <string.h>

typedef struct {
uint8_t b[16];
} __packed guid_t;

#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
((guid_t) \
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
(b) & 0xff, ((b) >> 8) & 0xff, \
(c) & 0xff, ((c) >> 8) & 0xff, \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } })

static inline int guidcmp(const guid_t *guid1, const guid_t *guid2)
{
return memcmp(guid1, guid2, sizeof(guid_t));
}

static inline guid_t *guidcpy(guid_t *dest, const guid_t *src)
{
return (guid_t *)memcpy(dest, src, sizeof(guid_t));
}

#endif /* _UUID_H_ */
15 changes: 13 additions & 2 deletions src/lib/gpio.c
View file
Expand Up @@ -20,6 +20,14 @@
#include <delay.h>
#include <gpio.h>

static void _check_num(const char *name, int num)
{
if ((num > 31) || (num < 1)) {
printk(BIOS_EMERG, "%s: %d ", name, num);
die("is an invalid number of GPIOs");
}
}

static uint32_t _gpio_base2_value(const gpio_t gpio[], int num_gpio)
{
uint32_t result = 0;
Expand All @@ -38,6 +46,7 @@ uint32_t gpio_base2_value(const gpio_t gpio[], int num_gpio)
{
int i;

_check_num(__func__, num_gpio);
for (i = 0; i < num_gpio; i++)
gpio_input(gpio[i]);

Expand All @@ -48,6 +57,7 @@ uint32_t gpio_pulldown_base2_value(const gpio_t gpio[], int num_gpio)
{
int i;

_check_num(__func__, num_gpio);
for (i = 0; i < num_gpio; i++)
gpio_input_pulldown(gpio[i]);

Expand All @@ -58,6 +68,7 @@ uint32_t gpio_pullup_base2_value(const gpio_t gpio[], int num_gpio)
{
int i;

_check_num(__func__, num_gpio);
for (i = 0; i < num_gpio; i++)
gpio_input_pullup(gpio[i]);

Expand All @@ -82,8 +93,8 @@ uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first)
int index;
int temp;
char value[32];
if ((num_gpio > 32) && (num_gpio < 1))
die("gpio_base3_value: Invalid number of GPIOs");

_check_num(__func__, num_gpio);

/* Enable internal pull up */
for (index = 0; index < num_gpio; ++index)
Expand Down
2 changes: 1 addition & 1 deletion src/lib/reset.c
View file
Expand Up @@ -19,7 +19,7 @@
#include <halt.h>
#include <reset.h>

__attribute__((noreturn)) static void __hard_reset(void) {
__noreturn static void __hard_reset(void) {
if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))
do_hard_reset();
else
Expand Down
13 changes: 5 additions & 8 deletions src/lib/ubsan.c
View file
Expand Up @@ -43,8 +43,7 @@ typedef uintptr_t ubsan_value_handle_t;
*/
#pragma GCC diagnostic ignored "-Wmissing-prototypes"

__attribute__((noreturn))
static void ubsan_abort(const struct ubsan_source_location *location,
static void __noreturn ubsan_abort(const struct ubsan_source_location *location,
const char *violation) {
static const struct ubsan_source_location unknown_location = {
"<unknown file>",
Expand All @@ -61,8 +60,8 @@ static void ubsan_abort(const struct ubsan_source_location *location,
}

#define ABORT_VARIANT(name, params, call) \
__attribute__((noreturn)) void __ubsan_handle_##name##_abort params; \
__attribute__((noreturn)) void __ubsan_handle_##name##_abort params { \
__noreturn void __ubsan_handle_##name##_abort params; \
__noreturn void __ubsan_handle_##name##_abort params { \
__ubsan_handle_##name call; \
__builtin_unreachable(); \
}
Expand Down Expand Up @@ -212,16 +211,14 @@ struct ubsan_unreachable_data {
struct ubsan_source_location location;
};

__attribute__((noreturn))
void __ubsan_handle_builtin_unreachable(void *data_raw)
void __noreturn __ubsan_handle_builtin_unreachable(void *data_raw)
{
struct ubsan_unreachable_data *data =
(struct ubsan_unreachable_data *)data_raw;
ubsan_abort(&data->location, "reached unreachable");
}

__attribute__((noreturn))
void __ubsan_handle_missing_return(void *data_raw)
void __noreturn __ubsan_handle_missing_return(void *data_raw)
{
const struct ubsan_unreachable_data *data =
(struct ubsan_unreachable_data *)data_raw;
Expand Down
4 changes: 4 additions & 0 deletions src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
View file
Expand Up @@ -62,6 +62,8 @@ chip northbridge/intel/x4x # Northbridge
device pci 1c.1 on end # PCIe 2
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6
device pci 1d.0 on # USB
subsystemid 0x1849 0x27c8
end
Expand All @@ -78,6 +80,8 @@ chip northbridge/intel/x4x # Northbridge
subsystemid 0x1849 0x27cc
end
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # ISA bridge
subsystemid 0x1849 0x27b8
chip superio/nuvoton/nct6776
Expand Down
4 changes: 4 additions & 0 deletions src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
View file
Expand Up @@ -57,6 +57,8 @@ chip northbridge/intel/x4x # Northbridge
device pci 1c.1 on end # PCIe 2
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6
device pci 1d.0 on # USB
subsystemid 0x1849 0x27c8
end
Expand All @@ -73,6 +75,8 @@ chip northbridge/intel/x4x # Northbridge
subsystemid 0x1849 0x27cc
end
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # ISA bridge
subsystemid 0x1849 0x27b8
chip superio/winbond/w83627dhg
Expand Down
5 changes: 5 additions & 0 deletions src/mainboard/emulation/qemu-q35/Kconfig
View file
Expand Up @@ -36,4 +36,9 @@ config DCACHE_RAM_SIZE
hex
default 0x10000

# Do not show IFD/blob options since QEMU doesn't care
config HAVE_INTEL_FIRMWARE
bool
default n

endif # BOARD_EMULATION_QEMU_X86_Q35
2 changes: 1 addition & 1 deletion src/mainboard/foxconn/d41s/board_info.txt
View file
@@ -1,4 +1,4 @@
Category: desktop
Category: mini
Board URL: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481
ROM package: DIP-8
ROM protocol: SPI
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/auron/chromeos.fmd
View file
Expand Up @@ -22,7 +22,8 @@ FLASH@0xff800000 0x800000 {
}
RW_VPD@0x1f8000 0x2000
RW_UNUSED@0x1fa000 0x6000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/beltino/chromeos.fmd
View file
Expand Up @@ -22,7 +22,8 @@ FLASH@0xff800000 0x800000 {
}
RW_VPD@0x1f8000 0x2000
RW_UNUSED@0x1fa000 0x6000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/butterfly/chromeos.fmd
View file
Expand Up @@ -23,7 +23,8 @@ FLASH@0xff800000 0x800000 {
RW_ENVIRONMENT@0x1f8000 0x4000
RW_VPD@0x1fc000 0x2000
RW_UNUSED@0x1fe000 0x2000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
57 changes: 29 additions & 28 deletions src/mainboard/google/cheza/chromeos.fmd
View file
Expand Up @@ -13,40 +13,41 @@
## GNU General Public License for more details.
##

FLASH@0x0 0x800000 {
WP_RO@0x0 0x300000 {
RO_SECTION@0x0 0x2E0000 {
BOOTBLOCK@0 128K
COREBOOT(CBFS)@0x20000 0x1E0000
FMAP@0x200000 0x1000
GBB@0x201000 0xDEF00
RO_FRID@0x2DFF00 0x100
FLASH@0x0 8M {
WP_RO 4M {
RO_SECTION 0x184000 {
BOOTBLOCK 96K
COREBOOT(CBFS)
#TODO: Move FMAP to 2M or 3M once FSG can be smaller
FMAP@0x180000 0x1000
GBB 0x2f00
RO_FRID 0x100
}
RO_VPD@0x2E0000 0x2000
RO_VPD 16K
RO_DDR_TRAINING 8K
RO_FSG
}

RW_NVRAM@0x300000 0x8000
RW_ELOG@0x308000 0x8000
RW_VPD@0x310000 0x8000
RW_CDT@0x318000 0x8000

RW_SECTION_A@0x320000 0x268000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x1E1F00
RW_FWID_A@0x1E3F00 0x100
RW_DDR_TRAINING_A@0x1E4000 0x4000
RW_XBL_BUFFER_A@0x1E8000 0x4000
RW_VPD 32K
RW_NVRAM 16K
RW_DDR_TRAINING 8K
RW_ELOG 4K
RW_SHARED 4K {
SHARED_DATA
}

RW_SHARED@0x588000 0x10000 {
SHARED_DATA@0x0 0x10000
RW_SECTION_A 1280K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}

RW_SECTION_B@0x598000 0x268000 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x1E1F00
RW_FWID_B@0x1E3F00 0x100
RW_DDR_TRAINING_B@0x1E4000 0x4000
RW_XBL_BUFFER_B@0x1E8000 0x4000

RW_SECTION_B 1280K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
}

RW_LEGACY(CBFS)
}
3 changes: 2 additions & 1 deletion src/mainboard/google/cyan/chromeos.fmd
View file
Expand Up @@ -22,7 +22,8 @@ FLASH@0xff800000 0x800000 {
}
RW_VPD@0x1f8000 0x2000
RW_UNUSED@0x1fa000 0x6000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/eve/chromeos.fmd
View file
Expand Up @@ -27,7 +27,8 @@ FLASH@0xff000000 0x1000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x800000 0x200000
SMMSTORE@0x800000 0x40000
RW_LEGACY(CBFS)@0x840000 0x1c0000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/fizz/chromeos.fmd
View file
Expand Up @@ -27,7 +27,8 @@ FLASH@0xff000000 0x1000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x800000 0x200000
SMMSTORE@0x800000 0x40000
RW_LEGACY(CBFS)@0x840000 0x1c0000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/glados/chromeos.fmd
View file
Expand Up @@ -22,7 +22,8 @@ FLASH@0xff000000 0x1000000 {
}
RW_VPD@0x7f8000 0x2000
RW_NVRAM@0x7fa000 0x6000
RW_LEGACY(CBFS)@0x800000 0x200000
SMMSTORE@0x800000 0x40000
RW_LEGACY(CBFS)@0x840000 0x1c0000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/jecht/chromeos.fmd
View file
Expand Up @@ -22,7 +22,8 @@ FLASH@0xff800000 0x800000 {
}
RW_VPD@0x1f8000 0x2000
RW_UNUSED@0x1fa000 0x6000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/google/kahlee/Kconfig
View file
Expand Up @@ -20,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE
select ALWAYS_RUN_OPROM
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_LPC
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd
View file
Expand Up @@ -24,7 +24,8 @@ FLASH@0xFF000000 0x1000000 {
RW_VPD@0x465000 0x2000
RW_NVRAM@0x467000 0x5000
RW_UNUSED@0x46C000 0x14000
RW_LEGACY@0x480000 0x780000
SMMSTORE@0x480000 0x20000
RW_LEGACY@0x4a0000 0x760000

WP_RO@0xC00000 0x400000 {
RO_VPD@0x0 0x4000
Expand Down
12 changes: 10 additions & 2 deletions src/mainboard/google/kahlee/variants/baseboard/gpio.c
View file
Expand Up @@ -40,6 +40,10 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_15 - EC_IN_RW_OD */
PAD_GPI(GPIO_15, PULL_UP),

/* GPIO_12 - EN_PP3300_TRACKPAD */
/* Init low to reset the chip */
PAD_GPO(GPIO_12, LOW),

/* GPIO_22 - EC_SCI_ODL, SCI */
PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),

Expand All @@ -58,6 +62,10 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_74 - LPC_CLK0_EC_R */
PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN),

/* GPIO_76 - EN_PP3300_TOUCHSCREEN */
/* Init low to reset the chip */
PAD_GPO(GPIO_76, LOW),

/* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),

Expand Down Expand Up @@ -213,8 +221,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
PAD_GPO(GPIO_133, HIGH),

/* GPIO_135 - Unused (TP128) */
PAD_GPI(GPIO_135, PULL_UP),
/* GPIO_135 - BCLK Buffer Enable */
PAD_GPO(GPIO_135, HIGH),

/* GPIO_137 - Unused (TP27) */
PAD_GPI(GPIO_137, PULL_UP),
Expand Down
18 changes: 14 additions & 4 deletions src/mainboard/google/kahlee/variants/liara/devicetree.cb
View file
Expand Up @@ -24,23 +24,23 @@ chip soc/amd/stoneyridge
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 95,
.rise_time_ns = 85,
.fall_time_ns = 3,
}"

# Enable I2C1 for H1 at 400kHz
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 84,
.rise_time_ns = 45,
.fall_time_ns = 4,
}"

# Enable I2C2 for trackpad, pen at 400kHz
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 117,
.fall_time_ns = 113,
.rise_time_ns = 48,
.fall_time_ns = 37,
}"

# Enable I2C3 for touchscreen at 400kHz
Expand Down Expand Up @@ -132,8 +132,18 @@ chip soc/amd/stoneyridge
register "desc" = ""ELAN Touchpad""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)"
register "wake" = "7"
register "probed" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)"
register "generic.wake" = "7"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end
device mmio 0xfedc5000 on
chip drivers/i2c/generic
Expand Down
4 changes: 4 additions & 0 deletions src/mainboard/google/kukui/bootblock.c
View file
Expand Up @@ -21,6 +21,7 @@
#include "gpio.h"

#define BOOTBLOCK_EN_L (GPIO(KPROW0))
#define AP_IN_SLEEP_L (GPIO(SRCLKENA0))

void bootblock_mainboard_init(void)
{
Expand All @@ -29,6 +30,9 @@ void bootblock_mainboard_init(void)
/* Turn on real eMMC. */
gpio_output(BOOTBLOCK_EN_L, 1);

/* Declare we are in S0 */
gpio_output(AP_IN_SLEEP_L, 1);

mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz);
mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz);
}
3 changes: 2 additions & 1 deletion src/mainboard/google/kukui/chromeos.fmd
View file
Expand Up @@ -25,5 +25,6 @@ FLASH@0x0 0x800000 {
RW_FWID_B@0x77f00 0x100
}
RW_VPD@0x2f8000 0x8000
RW_LEGACY(CBFS)@0x300000 0x100000
SMMSTORE@0x300000 0x20000
RW_LEGACY(CBFS)@0x320000 0xe0000
}
16 changes: 16 additions & 0 deletions src/mainboard/google/kukui/mainboard.c
View file
Expand Up @@ -14,10 +14,26 @@
*/

#include <device/device.h>
#include <soc/gpio.h>
#include <soc/mmu_operations.h>

static void configure_emmc(void)
{
const gpio_t emmc_pin[] = {
GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1),
GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3),
GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5),
GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7),
GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB),
};

for (size_t i = 0; i < ARRAY_SIZE(emmc_pin); i++)
gpio_set_pull(emmc_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP);
}

static void mainboard_init(struct device *dev)
{
configure_emmc();
}

static void mainboard_enable(struct device *dev)
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/link/chromeos.fmd
View file
Expand Up @@ -22,7 +22,8 @@ FLASH@0xff800000 0x800000 {
}
RW_VPD@0x1f8000 0x2000
RW_UNUSED@0x1fa000 0x6000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
4 changes: 3 additions & 1 deletion src/mainboard/google/octopus/Kconfig
View file
Expand Up @@ -17,6 +17,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
select SOC_ESPI
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select GOOGLE_SMBIOS_MAINBOARD_VERSION

if BOARD_GOOGLE_BASEBOARD_OCTOPUS

Expand Down Expand Up @@ -110,6 +111,7 @@ config TPM_TIS_ACPI_INTERRUPT

config DRAM_PART_NUM_IN_CBI
bool
default y if BOARD_GOOGLE_PHASER

config DRAM_PART_NUM_ALWAYS_IN_CBI
bool
Expand All @@ -120,7 +122,7 @@ config DRAM_PART_IN_CBI_BOARD_ID_MIN
depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI
default 255 if BOARD_GOOGLE_YORP
default 255 if BOARD_GOOGLE_BIP
default 9 if BOARD_GOOGLE_PHASER
default 2 if BOARD_GOOGLE_PHASER
default 9 if BOARD_GOOGLE_FLEEX
default 9 if BOARD_GOOGLE_BOBBA
default 9 if BOARD_GOOGLE_MEEP
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/octopus/chromeos.fmd
View file
Expand Up @@ -36,7 +36,8 @@ FLASH 16M {
FW_MAIN_B(CBFS)@0x10000 0x46ffc0
RW_FWID_B@0x47ffc0 0x40
}
RW_LEGACY(CBFS)@0xd30000 0x200000
SMMSTORE@0xd30000 0x40000
RW_LEGACY(CBFS)@0xd70000 0x1c0000
BIOS_UNUSABLE@0xf30000 0x4f000
DEVICE_EXTENSION@0xf7f000 0x80000
# Currently, it is required that the BIOS region be a multiple of 8KiB.
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/google/octopus/variants/baseboard/gpio.c
View file
Expand Up @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */
Expand Down Expand Up @@ -297,7 +297,7 @@ const struct pad_config *__weak variant_override_gpio_table(size_t *num)
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
/* GSPI0_INT */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD), /* H1_PCH_INT_ODL */
/* GSPI0_CLK */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
Expand Down
3 changes: 3 additions & 0 deletions src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
View file
Expand Up @@ -67,6 +67,9 @@
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE

/* Enable Tablet switch */
#define EC_ENABLE_TBMC_DEVICE

/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE

Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/google/octopus/variants/bip/gpio.c
View file
Expand Up @@ -89,7 +89,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/
Expand Down Expand Up @@ -290,7 +290,7 @@ const struct pad_config *variant_base_gpio_table(size_t *num)
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
/* GSPI0_INT */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD), /* H1_PCH_INT_ODL */
/* GSPI0_CLK */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/octopus/variants/bobba/gpio.c
View file
Expand Up @@ -55,7 +55,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/octopus/variants/fleex/gpio.c
View file
Expand Up @@ -92,7 +92,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/octopus/variants/meep/gpio.c
View file
Expand Up @@ -44,7 +44,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/octopus/variants/phaser/gpio.c
View file
Expand Up @@ -72,7 +72,7 @@ static const struct pad_config early_gpio_table[] = {
/* PCH_WP_OD */
PAD_CFG_GPI(GPIO_190, NONE, DEEP),
/* H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
DISPUPD),
/* H1_SLAVE_SPI_CLK_R */
PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1),
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/google/octopus/variants/phaser/include/variant/ec.h
View file
Expand Up @@ -18,7 +18,4 @@

#include <baseboard/ec.h>

/* Enable Tablet switch */
#define EC_ENABLE_TBMC_DEVICE

#endif
3 changes: 0 additions & 3 deletions src/mainboard/google/octopus/variants/yorp/include/variant/ec.h
View file
Expand Up @@ -18,7 +18,4 @@

#include <baseboard/ec.h>

/* Enable Tablet switch */
#define EC_ENABLE_TBMC_DEVICE

#endif
3 changes: 2 additions & 1 deletion src/mainboard/google/parrot/chromeos.fmd
View file
Expand Up @@ -23,7 +23,8 @@ FLASH@0xff800000 0x800000 {
RW_ENVIRONMENT@0x1f8000 0x4000
RW_VPD@0x1fc000 0x2000
RW_UNUSED@0x1fe000 0x2000
RW_LEGACY(CBFS)@0x200000 0x200000
SMMSTORE@0x200000 0x40000
RW_LEGACY(CBFS)@0x240000 0x1c0000
WP_RO@0x400000 0x200000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/google/poppy/Kconfig
View file
Expand Up @@ -196,6 +196,7 @@ config VARIANT_SPECIFIC_OPTIONS_RAMMUS
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_I2C_MAX98927
select DRIVERS_I2C_DA7219
select DRIVERS_SPI_ACPI
select MAINBOARD_HAS_SPI_TPM_CR50

config VARIANT_SPECIFIC_OPTIONS_SORAKA
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/poppy/chromeos.fmd
View file
Expand Up @@ -27,7 +27,8 @@ FLASH@0xff000000 0x1000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x800000 0x200000
SMMSTORE@0x800000 0x40000
RW_LEGACY(CBFS)@0x840000 0x1c0000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
Expand Down
3 changes: 3 additions & 0 deletions src/mainboard/google/poppy/romstage.c
View file
Expand Up @@ -173,4 +173,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd);
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
mem_cfg->MemorySpdDataLen = spd_info[p.type].len;

mem_cfg->SaOcSupport = p.enable_sa_oc_support;
mem_cfg->SaVoltageOffset = p.sa_voltage_offset_val;
}
16 changes: 8 additions & 8 deletions ...ffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex → ...py/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
View file
@@ -1,11 +1,11 @@
23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08
00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00
23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE
0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand All @@ -18,10 +18,10 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31
34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE
00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00
01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36
4E 43 4D 52 2D 56 4B 43 20 20 20 20 20 00 80 AD
FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand Down
18 changes: 9 additions & 9 deletions ...eelake_rvp/spd/samsung_lpddr4_8GB.spd.hex → ...spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
View file
@@ -1,26 +1,26 @@
23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00
48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00
00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 60 8D
0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47
31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C
45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand Down
16 changes: 16 additions & 0 deletions src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex
View file
@@ -0,0 +1,16 @@
91 20 F1 03 05 19 05 03 03 11 01 08 08 00 00 15
78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
00 10 C2 08 00 00 00 A8 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 2C 00 00 00 00 00 00 00 5A 5C
4D 54 35 32 4C 32 35 36 4D 33 32 44 31 50 46 2D
30 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
16 changes: 16 additions & 0 deletions src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex
View file
@@ -0,0 +1,16 @@
91 20 F1 03 05 19 05 0B 03 11 01 08 08 00 00 15
78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
00 21 C2 08 00 00 00 A8 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 2C 00 00 00 00 00 00 00 12 81
4D 54 35 32 4C 35 31 32 4D 33 32 44 32 50 46 2D
30 39 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
21 changes: 19 additions & 2 deletions src/mainboard/google/poppy/variants/atlas/devicetree.cb
View file
Expand Up @@ -27,6 +27,9 @@ chip soc/intel/skylake
# Enable S0ix
register "s0ix_enable" = "1"

# Disable Command TriState
register "CmdTriStateDis" = "1"

# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
Expand Down Expand Up @@ -147,14 +150,28 @@ chip soc/intel/skylake
.dc_loadline = 441,
}"

# PCIe Root port 1 with SRCCLKREQ1#
# PCIe Root port 1 with SRCCLKREQ1# (WLAN)
register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"

# PCIe Root port 5 (NVMe)
# PcieRpEnable: Enable root port
# PcieRpClkReqSupport: Enable CLKREQ#
# PcieRpClkReqNumber: Uses SRCCLKREQ4#
# PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4
# PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
# PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "4"
register "PcieRpClkSrcNumber[4]" = "4"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"

# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
Expand Down Expand Up @@ -329,7 +346,7 @@ chip soc/intel/skylake
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.4 on end # PCI Express Port 5 (NVMe)
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/google/poppy/variants/atlas/gpio.c
View file
Expand Up @@ -78,8 +78,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_B7),
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, RSMRST),
/* B9 : SRCCLKREQ4# ==> NC */
PAD_CFG_NC(GPP_B9),
/* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* B10 : SRCCLKREQ5# ==> NC */
PAD_CFG_NC(GPP_B10),
/* B11 : EXT_PWR_GATE# ==> NC */
Expand Down
6 changes: 6 additions & 0 deletions src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
View file
Expand Up @@ -54,6 +54,12 @@ struct memory_params {
const void *rcomp_target;
size_t rcomp_target_size;
bool use_sec_spd;

/* Enable SA overclocking mailbox commands */
bool enable_sa_oc_support;

/* The voltage offset applied to the SA in mV. 1000(mV) = Maximum */
uint16_t sa_voltage_offset_val;
};

void variant_memory_params(struct memory_params *p);
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/google/poppy/variants/nami/Makefile.inc
View file
Expand Up @@ -6,15 +6,15 @@ SPD_SOURCES += micron_dimm_MT40A256M16GE-083E # 0b0001
SPD_SOURCES += samsung_dimm_K4A8G165WB-BCRC # 0b0010
SPD_SOURCES += hynix_dimm_H5AN4G6NBJR-UHC # 0b0011
SPD_SOURCES += hynix_dimm_H5ANAG6NAMR-UHC # 0b0100
SPD_SOURCES += empty_ddr4 # 0b0101
SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b0101
SPD_SOURCES += hynix_dimm_H5AN8G6NAFR-UHC # 0b0110
SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111
SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000
SPD_SOURCES += empty_ddr4 # 0b1001
SPD_SOURCES += empty_ddr4 # 0b1010
SPD_SOURCES += empty_ddr4 # 0b1011
SPD_SOURCES += empty_ddr4 # 0b1100
SPD_SOURCES += empty_ddr4 # 0b1101
SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101
SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b1110
SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b1111

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2 changes: 2 additions & 0 deletions src/mainboard/google/poppy/variants/nautilus/Makefile.inc
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Expand Up @@ -7,9 +7,11 @@ bootblock-y += gpio.c

romstage-y += memory.c
romstage-y += gpio.c
romstage-y += sku.c

ramstage-y += gpio.c
ramstage-y += nhlt.c
ramstage-y += mainboard.c
ramstage-y += sku.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c