diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 3e4a2e530f6..b12744905dd 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 3e4a2e530f6f6dab7e9dc4af3feff9bdb2073b18 +Subproject commit b12744905dd20c77154db99a379543f61a3e3e7f diff --git a/3rdparty/blobs b/3rdparty/blobs index a59fb6e3892..353f2469be5 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit a59fb6e3892f0629d43769a07ee7f1048a0ae1f8 +Subproject commit 353f2469be53919b6b359148469485a9040e5a8b diff --git a/3rdparty/fsp b/3rdparty/fsp index eb25f19ef7f..e7138bf1150 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit eb25f19ef7fbe88fb207c6896a37a2035bba9bc5 +Subproject commit e7138bf11508b8b82350bd17fb611b67c0c64e6b diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 0e4288f81f8..49bb67f32a2 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 +Subproject commit 49bb67f32a2e3e631ba1a9a73da1c52e1cac7fd9 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 3318bf26803..bc0588e482b 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 3318bf26803c77d41b18bef6d7ae4e051b97f9f2 +Subproject commit bc0588e482b1320d5739900b00a45033f5b587f4 diff --git a/CHANGELOG.md b/CHANGELOG.md index 743e13bf0f5..22a24c3bc55 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -13,6 +13,10 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder) ## [Unreleased] +## [v4.13.0.3] - 2021-01-27 +### Changed +- rebased with official coreboot repository commit 5e6e5c1 + ## [v4.13.0.2] - 2020-12-28 ### Changed - rebased with official coreboot repository commit 8edb48b @@ -480,7 +484,8 @@ redundant code which was similar for APU2/3/5 boards. - turn off D4 and D5 leds on boot - enable power on after power failure -[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...develop +[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.3...develop +[v4.13.0.3]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...v4.13.0.3 [v4.13.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.13.0.2 [v4.13.0.1]: https://github.com/pcengines/coreboot/compare/v4.12.0.6...v4.13.0.1 [v4.12.0.6]: https://github.com/pcengines/coreboot/compare/v4.12.0.5...v4.12.0.6 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index d22d31de1ac..0e14115db8b 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -65,3 +65,33 @@ The reference implementation is * Test how well CAR works with x86_64 and paging * Improve mode switches * Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +According to Intel x86_64 mode hasn't been validated in CAR environments. +Until now it could be verified on various Intel platforms and no issues have +been found. + +## Known bugs on KVM enabled qemu + +The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues +when using KVM mode on some machines. The workaround is to *not* place +page-tables in ROM, as done in +[CB:49228](https://review.coreboot.org/c/coreboot/+/49228). + +Here's a list of known issues: + +* After entering long mode, the FPU doesn't work anymore, including accessing + MMX registers. It works fine before entering long mode. It works fine when + switching back to protected mode. Other registers, like SSE registers, are + working fine. +* Reading from virtual memory, when the page tables are stored in ROM, causes + the MMU to abort the "page table walking" mechanism when the lower address + bits of the virtual address to be translated have a specific pattern. + Instead of loading the correct physical page, the one containing the + page tables in ROM will be loaded and used, which breaks code and data as + the page table doesn't contain the expected data. This in turn leads to + undefined behaviour whenever the 'wrong' address is being read. +* Disabling paging in compability mode crashes the CPU. +* Returning from long mode to compability mode crashes the CPU. +* Entering long mode crashes on AMD host platforms. diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 508beaf40ae..40d747da9de 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -4,7 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard and plugin devices, significantly reducing integration complexity and they allow to easily reuse existing code accross platforms. +* [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) * [SMMSTORE](smmstore.md) * [SoundWire](soundwire.md) * [SMMSTOREv2](smmstorev2.md) +* [USB4 Retimer](retimer.md) diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 13aeed5bd2a..d4e8ca7df40 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -129,3 +129,13 @@ If no pullup or pulldown is declared with these, they may end up "floating", i.e., not at logical high or logical low. This can cause problems such as unwanted power consumption or not reading the pin correctly, if it was intended to be strapped. + +## Pad-related known issues and workarounds + +### LPC_CLKRUNB blocks S0ix states when board uses eSPI + +When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode. +Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up +enable/disable etc are ignored. Leaving this pin in native mode will keep the +LPC Controller awake and prevent S0ix entry. This issues is know at least on +Apollolake and Geminilake. diff --git a/Documentation/index.md b/Documentation/index.md index fd1ecb1639f..82ff12d5e68 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -187,5 +187,6 @@ Contents: * [SuperIO](superio/index.md) * [Vendorcode](vendorcode/index.md) * [Utilities](util.md) +* [coreboot infrastructure](infrastructure/index.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) diff --git a/Documentation/infrastructure/builders.md b/Documentation/infrastructure/builders.md new file mode 100644 index 00000000000..15c3ab92f74 --- /dev/null +++ b/Documentation/infrastructure/builders.md @@ -0,0 +1,392 @@ +# Jenkins builder setup and configuration + +## How to set up a new jenkins builder + +### Contact a jenkins admin + +Let a jenkins admin know that you’re interested in setting up a jenkins +build system. + +For a permanent build system, this should generally be a dedicated +machine that is not generally being used for other purposes. The +coreboot builds are very intensive. + +It's also best to be aware that although we don't know of any security +issues, the jenkins-node image is run with the privileged flag which +gives the container root access to the build machine. See +[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-running-a-privileged-container-in-docker-is-a-bad-idea/) +about why this is discouraged. + +It's recommended that you give an admin root access on your machine so +that they can reset it in case of a failure. This is not a requirement, +as the system can just be disabled until someone is available to fix any +issues. + +Currently active Jenkins admins: +* Patrick Georgi: + * Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de) + * IRC: pgeorgi + + +### Build Machine requirements + +For a builder, we need a fast system with lots of threads and plenty of +RAM. The builder builds and stores the git repos and output in tmpfs +along with the ccache save area, so if there isn't enough memory, the +builds will slow down because of smaller ccache areas and can run into +"out of storage space" errors. + +#### Current Build Machines + +To give an idea of what a suitable build machine might be, currently the +coreboot project has 3 active jenkins build machines. + +* Congenialbuilder - 128 threads, 256GiB RAM + * Fastest Passing coreboot gerrit build: 4 min, 30 sec + * Slowest Passing coreboot gerrit build: 9 min, 56 sec + + +* Gleeful builder - 64 thread, 64GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 6 sec + * Slowest Passing coreboot gerrit build, 34 min + + +* Ultron (9elements) - 48 threads, 128GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 32 sec + * Slowest Passing coreboot gerrit build: 44 min + + +### Jenkins Builds + +There are a number of builds handled by the coreboot jenkins builders, +for a number of different projects - coreboot, flashrom, memtest86+, +em100, etc. Many of these have builders for their current master branch +as well as gerrit and coverity builds. + +You can see all the builds here: +[https://qa.coreboot.org/](https://qa.coreboot.org/) + +Most of the time on the builders is taken up by the coreboot master and +gerrit builds. + +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) + + +* [coreboot master build](https://qa.coreboot.org/job/coreboot/) + ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) + + +### Stress test the machine + +Test the machine to make sure that building won't stress the hardware +too much. Install stress-ng, then run the stress test for at least an +hour. + +On a system with 32 cores, it was tested with this command: + +``` +$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m +``` + +You can watch the temperature with the sensors package or with ‘acpi -t’ +if your machine supports that. + +You can check for thermal throttling by running this command and seeing +if the values go down on any of the cores after it's been running for a +while. + +``` +$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done +``` + +If the machine throttles or resets, you probably need to upgrade the +cooling system. + + +## jenkins-server docker installation + + +### Manual Installation + +If you’ve met all the above requirements, and an admin has agreed to set +up the builder in jenkins, you’re ready to go on to the next steps. + + +### Set up your network so jenkins can talk to the container + +Expose a local port through any firewalls you might have on your router. +This would generally be in the port forwarding section, and you'd just +forward a port (typically 49151) from the internet directly to the +builder’s IP address. + +You might also want to set up a port to forward to port 22 on your +machine and set up openssh so you or the jenkins admins can manage +the machine remotely (if you allow them). + + +### Install and set up docker + +Install docker by following the +[directions](https://docs.docker.com/engine/install/) on the docker +site. These instructions keep changing, so just check the latest +information. + + +#### Set up environment variables + +To make configuration and the later commands easier, these should go in +your shell's .rc file. Note that you only need to set them if you're +using something other than the default. + +``` +# Set the port used on your machine to connect to jenkins. +export COREBOOT_JENKINS_PORT=49151 + +# Set the revision of the container from docker hub +export DOCKER_COMMIT=65718760fa + +# Set the location of where the jenkins cache directory will be. +export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache" + +# Set the name of the container +export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins" +``` + +Make sure any variables needed are set in your environment before +continuing to the next step. + + +### Using the Makefile for docker installation + +From the coreboot directory, run + +``` +make -C util/docker help +``` + +This will show you the available targets and variables needed: + +``` +Commands for working with docker images: + coreboot-sdk - Build coreboot-sdk container + upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com + coreboot-jenkins-node - Build coreboot-jenkins-node container + upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com + doc.coreboot.org - Build doc.coreboot.org container + clean-coreboot-containers - Remove all docker coreboot containers + clean-coreboot-images - Remove all docker coreboot images + docker-clean - Remove docker coreboot containers & images + +Commands for using docker images + docker-build-coreboot - Build coreboot under coreboot-sdk + + docker-abuild - Run abuild under coreboot-sdk + + docker-what-jenkins-does - Run 'what-jenkins-does' target + docker-shell - Bash prompt in coreboot-jenkins-node + + docker-jenkins-server - Run coreboot-jenkins-node image (for server) + docker-jenkins-attach - Open shell in running jenkins server + docker-build-docs - Build the documentation + docker-livehtml-docs - Run sphinx-autobuild + +Variables: + COREBOOT_JENKINS_PORT=49151 + COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache + COREBOOT_JENKINS_CONTAINER=coreboot_jenkins + COREBOOT_IMAGE_TAG=f2741aa632f + DOCKER_COMMIT=65718760fa +``` + +### Set up the system for the jenkins builder + +As a regular user - *Not root*, run: + +``` +sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR} +sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR} +wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar +mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR} +``` + +### Install the coreboot jenkins builder + +``` +make -C util/docker docker-jenkins-server +``` + +Your installation is complete on your side. + +### Tell the Admins that the machine is set up +Let the admins know that the builder is set up so they can set up the +machine profile on qa.coreboot.org. + +They need to know: +* Your external IP address or domain name. If you don’t have a static +IP, make sure you have a dynamic dns hostname configured. +* The port on your machine and firewall that’s exposed for jenkins: +`$COREBOOT_JENKINS_PORT` +* The core count of the machine. +* How much memory is available on the machine. This helps determine +the amount of memory used for ccache. + + +### First build +On the first build after a machine is reset, it will frequently take +20-25 minutes to do the entire what-jenkins-does build while the ccache +is getting filled up and the entire coreboot repo gets downloaded. As +the ccache gets populated, the build time will drop. + + +## Additional Information + + +### How to log in to the docker instance for debugging +``` + $ make -C util/docker docker-jenkins-attach + $ su coreboot + $ cd ~/slave-root/workspace + $ bash +``` + + +WARNING: This should not be used to make changes to the build system, +but just to debug issues. Changes to the build system are highly +discouraged as it leads to situations where patches can pass the build +testing on one builder and fail on another builder. Any changes that are +made in the image will be lost on the next update, so if you +accidentally change something, you can remove the containers and images +and update to get a fresh installation. + + +### How to download containers/images for a fresh installation and remove old containers + +To delete the old containers & images: + +``` +$ docker stop $COREBOOT_JENKINS_CONTAINER +$ docker rm $COREBOOT_JENKINS_CONTAINER +$ docker images # lists all existing images +$ docker rmi XXXX # Use the image ID found in the above command. +``` + +To get and run the new coreboot-jenkins image, change the value in the +`DOCKER_COMMIT` variable to the new image value. + +``` +$ make -C util/docker docker-jenkins-server +``` + +#### Getting ready to push the docker images + +Set up an account on hub.docker.com + +Get an admin to add the account to the coreboot team on hub.docker.com + +[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners) + +Make sure your credentials are configured on your host machine by +running + +``` +$ docker login +``` + +This will prompt you for your docker username, password, and your email +address, and write out to ~/.docker/config.json. Without this file, you +won’t be able to push the images. + +#### Updating the Dockerfiles: + +The coreboot-sdk Dockerfile will need to be updated when any additional +dependencies are added. Both the coreboot-sdk and the +coreboot-jenkins-node Dockerfiles will need to be updated to the new +version number and git commit id anytime the toolchain is updated. Both +files are stored in the coreboot repo under coreboot/util/docker. + +Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/) +page before updating the files. + +#### Rebuilding the coreboot-sdk docker image to update the toolchain: + +``` +$ make -C util/docker coreboot-sdk +``` + +This takes a relatively long time. + +#### Test the coreboot-sdk docker image: + +There are two methods of running the docker image - interactively as a +shell, or doing the build directly. Running interactively as a shell is +useful for early testing, because it allows you to update the image +(without any changes getting saved) and re-test builds. This saves the +time of having to rebuild the image for every issue you find. + +#### Running the docker image interactively: + +Run: + +``` +$ make -C util/docker docker-jenkins-server +$ make -C util/docker docker-jenkins-attach +``` + +#### Running the build directly: + +From the coreboot directory: + +``` +$ make -C util/docker docker-build-coreboot +``` + +You’ll also want to test building the other projects and payloads: +ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo, +nvramcui, tint... + +#### Pushing the coreboot-sdk image to hub.docker.com for use: + +When you’re satisfied with the testing, push the coreboot-sdk image to +the hub.docker.com + +``` +$ make -C util/docker upload-coreboot-sdk +``` + +#### Building and pushing the coreboot-jenkins-node docker image: + +This docker image is pretty simple, so there’s not really any testing +that needs to be done. + +``` +$ make -C util/docker coreboot-jenkins-node +$ make -C util/docker upload-coreboot-jenkins-node +``` + +### Coverity Setup + +To run coverity jobs, the builder needs to have the tools available, and +to be marked as a coverity builder. + + +#### Set up the Coverity tools + +Download the Linux-64 coverity build tool and decompress it into your +cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable + +[https://scan.coverity.com/download](https://scan.coverity.com/download) + +Rename the directory from its original name +(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a +symlink: + +``` +ln -s cov-analysis-linux64-7.7.0.4 coverity +``` + + +Let the admins know that the ‘coverity’ label can be added to the +builder. diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md new file mode 100644 index 00000000000..42bcbf65c8c --- /dev/null +++ b/Documentation/infrastructure/index.md @@ -0,0 +1,6 @@ +# coreboot infrastructure + +This section contains documentation about coreboot infrastructure + +## Jenkins builders and builds +[Setting up Jenkins build machines](builders.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55e50e..b55876016aa 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -16,6 +16,7 @@ This section contains documentation about coreboot on specific mainboards. ## ASUS +- [A88XM-E](asus/a88xm-e.md) - [F2A85-M](asus/f2a85-m.md) - [P5Q](asus/p5q.md) - [P8H61-M LX](asus/p8h61-m_lx.md) @@ -176,6 +177,10 @@ The boards in this section are not real mainboards, but emulators. - [Lemur Pro](system76/lemp9.md) +## Texas Instruments + +- [Beaglebone Black](ti/beaglebone-black.md) + ## UP - [Squared](up/squared/index.md) diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 5f151663c4b..0f3e4c3179b 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -25,7 +25,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s. ## Installation instructions * Update the EC firmware, as there's no support for EC updates in coreboot. -* Do **NOT** accidently swap pins or power on the board while a SPI flasher +* Do **NOT** accidentally swap pins or power on the board while a SPI flasher is connected. It will permanently brick your device. * It's recommended to only flash the BIOS region. In that case you don't need to extract blobs from vendor firmware. diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 0bf118ff35e..84bae4014d7 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -22,8 +22,12 @@ ``` ## Installation instructions + +Flashing coreboot for the first time needs to be done using an external +programmer, because vendor firmware prevents rewriting the BIOS region. + * Update the EC firmware, as there's no support for EC updates in coreboot. -* Do **NOT** accidently swap pins or power on the board while a SPI flasher +* Do **NOT** accidentally swap pins or power on the board while a SPI flasher is connected. It will destroy your device. * It's recommended to only flash the BIOS region. In that case you don't need to extract blobs from vendor firmware. diff --git a/Documentation/mainboard/ti/beaglebone-black.md b/Documentation/mainboard/ti/beaglebone-black.md new file mode 100644 index 00000000000..db37e280994 --- /dev/null +++ b/Documentation/mainboard/ti/beaglebone-black.md @@ -0,0 +1,131 @@ +# Beaglebone Black +This page gives some details about the [BeagleBone Black] coreboot port and +describes how to build and run it. + +The port currently only supports booting coreboot from a micro SD card and has +some other limitations listed below. + +## Supported Boards +The Beaglebone port supports the following boards: + +- Beaglebone Black +- Beaglebone Black Wireless +- Beaglebone Pocket (untested, may need tweaking) +- Beaglebone Blue (untested, may need tweaking) +- Beaglebone Original (untested, may need tweaking) + +## Use Cases +This port was primarily developed as a learning exercise and there is +potentially little reason to use it compared to the defacto bootloader choice of +U-Boot. However, it does have some interesting practical use cases compared to +U-Boot: + +1. Choosing coreboot as a lightweight alternative to U-Boot. In this case, + coreboot is used to do the absolute minimum necessary to boot Linux, forgoing + some U-Boot features and functionality. Complex boot logic can then instead + be moved into Linux where it can be more flexibly and safely executed. This + is essentially the LinuxBoot philosophy. [U-Boot Falcon mode] has similar + goals to this as well. +2. Facilitating experimenting with coreboot on real hardware. The Beaglebone + Black is widely available at a low pricepoint (~$65) making it a great way to + experiment with coreboot on real ARMv7 hardware. It also works well as a + development platform as it has exposed pads for JTAG and, due to the way it + boots, is effectively impossible to brick. +3. The Beaglebone Black is often used as a external flasher and EHCI debug + gadget in the coreboot community, so many members have access to it and can + use it as a reference platform. + +## Quickstart +1. Run `make menuconfig` and select _TI_/_Beaglebone_ in the _Mainboard_ menu. +2. Add a payload as normal. +3. Run `make`. +4. Copy the resulting `build/MLO` file to the micro SD card at offset 128k - ie + `dd if=build/MLO of=/dev/sdcard seek=1 bs=128k`. + +**NOTE**: By default, the Beaglebone is configured to try to boot first from +eMMC before booting from SD card. To ensure that the Beaglebone boots from SD, +either erase the internal eMMC or hold the _S2_ button while powering on (note +that this has to be while powering on - ie when plugging in the USB or DC barrel +jack - the boot order doesn't change on reset) to prioritize SD in the boot +order. + +## Serial Console +By default, coreboot uses UART0 as the serial console. UART0 is available +through the J1 header on both the Beaglebone Black and Beaglebone Black +Wireless. The serial runs at 3.3V and 115200 8n1. + +The pin mapping is shown below for J1. + + ```eval_rst + +----------------------------+------------+ + | Pin number | Function | + +============================+============+ + | 1 (Closest to barrel jack) | GND | + +----------------------------+------------+ + | 4 | RX | + +----------------------------+------------+ + | 5 | TX | + +----------------------------+------------+ + ``` + +## Boot Process +The AM335x contains ROM code to allow booting in a number of different +configurations. More information about the boot ROM code can be found in the +AM335x technical reference manual (_SPRUH73Q_) in the _Initialization_ section. + +This coreboot port is currently configured to boot in "SD Raw Mode" where the +boot binary, with header ("Table of Contents" in TI's nomenclature), is placed +at the offset of 0x20000 (128KB) on the SD card. The boot ROM loads the coreboot +bootblock stage into SRAM and executes it. + +The bootblock and subsequent romstage and ramstage coreboot stages expect that +the coreboot image, containing the CBFS, is located at 0x20000 on the SD card. +All stages directly read from the SD card in order to load the next stage in +sequence. + +## Clock Initialization and PMIC +To simplify the port, the TPS65217C Power Management IC (PMIC) on the Beaglebone +Black is not configured by coreboot. By default, the PMIC reset values for +VDD_MPU (1.1V) and VDD_CORE (1.8V) are within the Operating Performance Point +(OPP) for the MPU PLL configuration set by the boot ROM of 500 MHz. + +When using Linux as a payload, the kernel will appropriately scale the core +voltages for the desired MPU clock frequency as defined in the device tree. + +One significant difference because of this to the U-Boot port is that the DCDC1 +rail that powers the DDR3 RAM will be 1.5V by default. The Micron DDR3 supports +both 1.35V and 1.5V and U-Boot makes use of this by setting it to 1.35V to +conserve power. Fortunately, Linux is again able to configure this rail but it +involves adding an entry to the device tree: + + &dcdc1_reg { + regulator-name = "vdd_ddr3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + +If this port was to be extended to work with boards or SoCs with different +requirements for the MPU clock frequency or different Operating Performance +Points, then the port may need to be extended to set the core voltages and MPU +PLL within coreboot, prior to loading a payload. Extending coreboot so that it +can configure the PMIC would also be necessary if there was a requirement for +coreboot to run at a different MPU frequency than the 500 MHz set by the boot +ROM. + +# Todo +- Allow coreboot to run from the Beaglebone Black's internal eMMC. This would + require updating the `mmc.c` driver to support running from both SD and eMMC. +- Support the boot ROMs *FAT mode* so that the coreboot binary can be placed on + a FAT partition. +- Increase the MMC read speed, it currently takes ~15s to read ~20MB which is a + bit slow. To do this, it should be possible to update the MMC driver to: + - Increase the supported blocksize (currently is always set to 1) + - Support 4-bit data width (currently only supports 1-bit data width) +- Convert the while loops in the MMC driver to timeout so that coreboot does not + hang on a bad SD card or when the SD card is removed during boot. + + +[Beaglebone Black]: https://beagleboard.org/black [U-Boot Falcon mode]: +https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon \ No newline at end of file diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md index 5f8e279841b..214733140bf 100644 --- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md +++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md @@ -20,11 +20,6 @@ Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel :doc:`../../../mainboard/intel/icelake_rvp` ``` -3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google - ```eval_rst - :doc:`../../../mainboard/google/dragonegg` - ``` - ### Summary: * SoC is Ice Lake. * Reference platform is icelake_rvp. diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index 5c7239af6b9..71e427ebef0 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -11,4 +11,4 @@ This section contains documentation about coreboot on specific Intel SOCs. - [Microcode Updates](microcode.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) -- [CSE FW Update](cse_fw_update/cse_fw_update_model.md) +- [CSE FW Update](cse_fw_update/cse_fw_update.md) diff --git a/MAINTAINERS b/MAINTAINERS index 49fbc38c627..7a82159919a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,8 @@ F: src/drivers/aspeed/common/ F: src/drivers/aspeed/ast2050/ ACPI +M: Lance Zhao +S: Supported F: src/acpi/ F: src/arch/x86/acpi/ F: util/acpi/ diff --git a/Makefile b/Makefile index 1b7cb9b8d65..ec0f95b5955 100644 --- a/Makefile +++ b/Makefile @@ -8,6 +8,7 @@ src := src srck := $(top)/util/kconfig obj ?= build override obj := $(subst $(top)/,,$(abspath $(obj))) +xcompile ?= $(obj)/xcompile objutil ?= $(obj)/util objk := $(objutil)/kconfig absobj := $(abspath $(obj)) @@ -119,7 +120,7 @@ UNIT_TEST:=1 NOCOMPILE:= endif -.xcompile: util/xcompile/xcompile +$(xcompile): util/xcompile/xcompile rm -f $@ $< $(XGCCPATH) > $@.tmp \mv -f $@.tmp $@ 2> /dev/null @@ -146,15 +147,17 @@ ifneq ($(UNIT_TEST),1) include $(DOTCONFIG) endif -# in addition to the dependency below, create the file if it doesn't exist -# to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) +# The toolchain requires xcompile to determine the ARCH_SUPPORTED, so we can't +# wait for make to generate the file. +$(if $(wildcard $(xcompile)),, $(shell \ + mkdir -p $(dir $(xcompile)) && \ + util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile))) --include .xcompile +include $(xcompile) ifneq ($(XCOMPILE_COMPLETE),1) -$(shell rm -f .xcompile) -$(error .xcompile deleted because it's invalid. \ +$(shell rm -f $(xcompile)) +$(error $(xcompile) deleted because it's invalid. \ Restarting the build should fix that, or explain the problem) endif diff --git a/Makefile.inc b/Makefile.inc index 1141f5c529b..a98c37675d2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -77,14 +77,15 @@ PHONY+= clean-abuild coreboot check-style build-dirs build_complete ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi +subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) -subdirs-y += src/superio +subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*) subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu +subdirs-y += util/ifdtool subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security @@ -483,7 +484,13 @@ ADAFLAGS_common += -gnatwa.eeD.HHTU.U.W.Y # Disable style checks for now ADAFLAGS_common += -gnatyN -LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static + +# Workaround for RISC-V linker bug, merge back into above line when fixed. +# https://sourceware.org/bugzilla/show_bug.cgi?id=27180 +ifneq ($(CONFIG_ARCH_RISCV),y) +LDFLAGS_common += --emit-relocs +endif ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror @@ -520,7 +527,8 @@ build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \ - util/genbuild_h/genbuild_h.sh .xcompile >$(build_h)t 2>/dev/null; \ + util/genbuild_h/genbuild_h.sh $(xcompile) \ + >$(build_h)t 2>/dev/null; \ cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t $(build_h): $$(shell $$(build_h_check)) @@ -575,10 +583,6 @@ endif BINCFG:=$(objutil)/bincfg/bincfg IFDTOOL:=$(objutil)/ifdtool/ifdtool -$(IFDTOOL): - @printf " Compile IFDTOOL\n" - +$(MAKE) -C $(top)/util/ifdtool - cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool @@ -982,6 +986,15 @@ else FMAP_SPD_CACHE_ENTRY := endif +ifeq ($(CONFIG_VPD),y) +FMAP_VPD_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000) +FMAP_VPD_SIZE := $(CONFIG_VPD_FMAP_SIZE) +FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(FMAP_VPD_BASE) $(FMAP_VPD_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_VPD_BASE) $(FMAP_VPD_SIZE)) +else +FMAP_VPD_ENTRY := +endif + # # X86 FMAP region # @@ -1059,6 +1072,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ + -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp @@ -1136,6 +1150,10 @@ else RAMSTAGE= endif +add_intermediate = \ + $(1): $(obj)/coreboot.pre $(2) | $(INTERMEDIATE) \ + $(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1)) + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -1242,7 +1260,7 @@ cbfs-get-segments-cmd = $(CBFSTOOL) $(obj)/coreboot.pre print -v | sed -n \ ramstage-symbol-addr-cmd = $(OBJDUMP_ramstage) -t $(objcbfs)/ramstage.elf | \ sed -n '/ $(1)$$/s/^\([0-9a-fA-F]*\) .*/0x\1/p' -check-ramstage-overlaps: $(obj)/coreboot.pre +$(call add_intermediate, check-ramstage-overlaps) programs=$$($(foreach file,$(check-ramstage-overlap-files), \ $(call cbfs-get-segments-cmd,$(file)) ; )) ; \ regions=$$($(foreach region,$(check-ramstage-overlap-regions), \ @@ -1268,6 +1286,4 @@ check-ramstage-overlaps: $(obj)/coreboot.pre pstart= ; pend= ; \ done -INTERMEDIATE+=check-ramstage-overlaps -PHONY+=check-ramstage-overlaps endif diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1 index cabf4c64c60..bbcd1e55aa0 100644 --- a/configs/config.pcengines_apu1 +++ b/configs/config.pcengines_apu1 @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="v4.13.0.2" +CONFIG_LOCALVERSION="v4.13.0.3" CONFIG_VENDOR_PCENGINES=y CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" CONFIG_NO_GFX_INIT=y diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 index 278969ca8ab..02611fb9e4f 100644 --- a/configs/config.pcengines_apu2 +++ b/configs/config.pcengines_apu2 @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="v4.13.0.2" +CONFIG_LOCALVERSION="v4.13.0.3" CONFIG_VENDOR_PCENGINES=y CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" CONFIG_BOARD_PCENGINES_APU2=y diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 index a383514bec1..3a083b7fb5e 100644 --- a/configs/config.pcengines_apu3 +++ b/configs/config.pcengines_apu3 @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="v4.13.0.2" +CONFIG_LOCALVERSION="v4.13.0.3" CONFIG_VENDOR_PCENGINES=y CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" CONFIG_BOARD_PCENGINES_APU3=y diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 index 7f4ecf5b086..4daae3bcd38 100644 --- a/configs/config.pcengines_apu4 +++ b/configs/config.pcengines_apu4 @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="v4.13.0.2" +CONFIG_LOCALVERSION="v4.13.0.3" CONFIG_VENDOR_PCENGINES=y CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" CONFIG_BOARD_PCENGINES_APU4=y diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 index ab24a7e51c1..7aa3cf97aea 100644 --- a/configs/config.pcengines_apu5 +++ b/configs/config.pcengines_apu5 @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="v4.13.0.2" +CONFIG_LOCALVERSION="v4.13.0.3" CONFIG_VENDOR_PCENGINES=y CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" CONFIG_BOARD_PCENGINES_APU5=y diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6 index f6831f82f4d..e343cf6d1f1 100644 --- a/configs/config.pcengines_apu6 +++ b/configs/config.pcengines_apu6 @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="v4.13.0.2" +CONFIG_LOCALVERSION="v4.13.0.3" CONFIG_VENDOR_PCENGINES=y CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" CONFIG_BOARD_PCENGINES_APU6=y diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index dae5c2fa232..42ae67e1289 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -145,26 +145,24 @@ endif ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) -INTERMEDIATE+=seabios_ps2_timeout -seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) +$(call add_intermediate, seabios_ps2_timeout, $(CBFSTOOL)) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/ps2-keyboard-spinup 2>/dev/null) $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif -endif ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) -INTERMEDIATE+=seabios_sercon -seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) +$(call add_intermediate, seabios_sercon, $(CBFSTOOL)) @printf " SeaBIOS Add sercon-port file\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/sercon-port 2>/dev/null) $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) -INTERMEDIATE+=seabios_thread_optionroms -seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) +$(call add_intermediate, seabios_thread_optionroms, $(CBFSTOOL)) @printf " SeaBIOS Thread optionroms\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/threads 2>/dev/null) $(CBFSTOOL) $< add-int -i 2 -n etc/threads endif @@ -194,6 +192,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ + CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 7d5f038ebd6..87b6e15582a 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -100,4 +100,12 @@ config TIANOCORE_BOOTSPLASH_FILE If an absolute path is not given, the path will assumed to be relative to the coreboot root directory. +config TIANOCORE_BOOT_TIMEOUT + int + default 2 + help + The length of time in seconds for which the boot splash/menu prompt will be displayed. + For boards with an internal display, the default value of 2s is generally sufficient. + For boards without an internal display, a value of 5s is generally sufficient. + endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index bc2164d2785..45c7e077801 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -34,12 +34,16 @@ ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) TIMER=-DUSE_HPET_TIMER endif +TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) + ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) - BUILD_STR=-q -a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) +ARCH=-a IA32 -p $(bootloader)/$(bootloader)Ia32.dsc else - BUILD_STR=-q -a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor) +ARCH=-a IA32 -a X64 -p $(bootloader)/$(bootloader)Ia32X64.dsc endif +BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor) + all: clean build $(project_dir): diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f5b81a9f000..7a502b5853b 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -375,10 +375,6 @@ config PC_KEYBOARD default y if ARCH_X86 # uses IO default n -config PC_KEYBOARD_AT_TRANSLATED - bool "AT Translation keyboard device" - default n - config PC_KEYBOARD_LAYOUT_US bool "English (US) keyboard layout" depends on PC_KEYBOARD diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index b5687c3859b..0b08c70af7d 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -118,6 +118,11 @@ NOCOMPILE:=1 endif endif +xcompile ?= $(obj)/xcompile +$(xcompile): $(top)/../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc real-all: config @@ -126,13 +131,17 @@ else # in addition to the dependency below, create the file if it doesn't exist # to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell $(top)/../../util/xcompile/xcompile $(XGCCPATH) > .xcompile))) +$(if $(wildcard $(xcompile)),,$(shell \ + mkdir -p $(dir $(xcompile)) && \ + $(top)/../../util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile))) -.xcompile: $(top)/../../util/xcompile/xcompile - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null +include $(xcompile) --include .xcompile +ifneq ($(XCOMPILE_COMPLETE),1) +$(shell rm -f $(xcompile)) +$(error $(xcompile) deleted because it's invalid. \ + Restarting the build should fix that, or explain the problem) +endif CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) @@ -294,7 +303,7 @@ doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR) clean-for-update: doxygen-clean clean-for-update-target - rm -f $(allobjs) .xcompile + rm -f $(allobjs) $(xcompile) rm -f $(DEPENDENCIES) rmdir -p $(alldirs) 2>/dev/null >/dev/null || true diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 6188ddefa7b..fc679dd27e7 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -69,7 +69,10 @@ ifeq ($(CONFIG_LP_LTO),y) CFLAGS += -flto endif -$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) +$(obj)/libpayload.config: $(DOTCONFIG) + cp $< $@ + +$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) $(obj)/libpayload.config cmp $@ $< 2>/dev/null || cp $< $@ library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a @@ -121,7 +124,7 @@ install: real-target install -m 755 bin/lpas $(DESTDIR)/libpayload/bin install -m 644 bin/lp.functions $(DESTDIR)/libpayload/bin install -m 644 $(DOTCONFIG) $(DESTDIR)/libpayload/libpayload.config - install -m 755 .xcompile $(DESTDIR)/libpayload/libpayload.xcompile + install -m 755 $(xcompile) $(DESTDIR)/libpayload/libpayload.xcompile clean-for-update-target: rm -f $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a diff --git a/payloads/libpayload/bin/lp.functions b/payloads/libpayload/bin/lp.functions index 3911c42a5b6..fd26956243d 100644 --- a/payloads/libpayload/bin/lp.functions +++ b/payloads/libpayload/bin/lp.functions @@ -35,6 +35,10 @@ warn() { echo "Warning: $1" } +# For in-tree builds, allow to override the libpayload build dir. + +_OBJ=${_OBJ:-$BASE/../build} + # If the user didn't specify LIBPAYLOAD_PREFIX, then preload it # with the default prefix value @@ -48,8 +52,8 @@ fi if [ -f $BASE/../lib/libpayload.a ]; then _LIBDIR=$BASE/../lib -elif [ -f $BASE/../build/libpayload.a ]; then - _LIBDIR=$BASE/../build +elif [ -f $_OBJ/libpayload.config ]; then + _LIBDIR=$_OBJ else _LIBDIR=$LIBPAYLOAD_PREFIX/lib fi diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index aa09c1d1164..c0fe56adf59 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -57,11 +57,17 @@ BASE=`dirname $0` # This will set the _LIBDIR and _INCDIR variables used below . $BASE/lp.functions +if [ $_LIBDIR != $_OBJ ]; then + _DOTCONFIG=$BASE/../libpayload.config + _XCOMPILE=$BASE/../libpayload.xcompile +else + _DOTCONFIG=$_OBJ/libpayload.config + _XCOMPILE=$_OBJ/xcompile +fi + # include libpayload config -if [ -f $BASE/../libpayload.config ]; then - . $BASE/../libpayload.config -elif [ -f $BASE/../.config ]; then - . $BASE/../.config +if [ -f $_DOTCONFIG ]; then + . $_DOTCONFIG else echo "Can't find config" exit 1 @@ -137,14 +143,19 @@ while [ $# -gt 0 ]; do shift done -_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" -if [ "$CONFIG_LP_PDCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses" -fi +if [ $_LIBDIR = $_OBJ ]; then + _CFLAGS="$_CFLAGS -I$_OBJ" -if [ "$CONFIG_LP_TINYCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses" + if [ "$CONFIG_LP_PDCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses -I$BASE/../curses/pdcurses-backend" + _CFLAGS="$_CFLAGS -I$BASE/../curses/form -I$BASE/../curses/menu" + fi + + if [ "$CONFIG_LP_TINYCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses" + fi fi # Check for the -fno-stack-protector silliness @@ -155,7 +166,7 @@ trygccoption -fno-stack-protector _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" +_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then @@ -167,15 +178,15 @@ else _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` if [ -f $_ARCHLIBDIR/head.o ]; then HEAD_O=$_ARCHLIBDIR/head.o - elif [ -f $BASE/../build/head.o ]; then - HEAD_O=$BASE/../build/head.o + elif [ -f $_OBJ/head.o ]; then + HEAD_O=$_OBJ/head.o else echo "Could not find head.o" exit 1 fi - if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config && - grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then + if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] && + grep -q fix-cortex-a53-843419 $_XCOMPILE; then _LDFLAGS="$_LDFLAGS -Wl,--fix-cortex-a53-843419" fi diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 84bad553715..a89b9d9717e 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -28,6 +28,7 @@ #include #include +#include #include #include "i8042.h" @@ -111,6 +112,19 @@ static u8 fifo_pop(struct fifo *fifo) return ret; } +/** Peek on the head of fifo queue. + * Returns the oldest object on the queue if any. + * In case the queue is empty 0 is returned. + * @fifo: Fifo to use + */ +static u8 fifo_peek(struct fifo *fifo) +{ + if (fifo_is_empty(fifo)) + return 0; + + return fifo->buf[fifo->rx]; +} + /** Destroys a fifo queue. * @fifo: Fifo to use */ @@ -318,6 +332,24 @@ void i8042_write_data(u8 data) return; } +/** + * Send command & data to keyboard controller. + * + * @param cmd: The command to be sent. + * @param data: The data to be sent. + * Returns 0 on success, -1 on failure. + */ +static int i8042_cmd_with_data(const u8 cmd, const u8 data) +{ + const int ret = i8042_cmd(cmd); + if (ret != 0) + return ret; + + i8042_write_data(data); + + return ret; +} + /** * Probe for keyboard controller data and queue it. */ @@ -371,6 +403,14 @@ u8 i8042_read_data_ps2(void) return fifo_pop(ps2_fifo); } +/** + * Returns available keyboard data without advancing the queue. + */ +u8 i8042_peek_data_ps2(void) +{ + return fifo_peek(ps2_fifo); +} + /** * Returns available mouse data, if any. */ @@ -408,3 +448,36 @@ int i8042_wait_read_aux(void) return (retries <= 0) ? -1 : i8042_read_data_aux(); } + +/** + * Get the keyboard scancode translation state. + * + * Returns: -1 on timeout, 1 if the controller translates + * scancode set #2 to #1, and 0 if not. + */ +int i8042_get_kbd_translation(void) +{ + const int cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE); + if (cfg < 0) + return cfg; + + return !!(cfg & I8042_CMD_BYTE_XLATE); +} + +/** + * Sets the keyboard scancode translation state. + * + * Returns: -1 on timeout, 0 otherwise. + */ +int i8042_set_kbd_translation(const bool xlate) +{ + int cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE); + if (cfg < 0) + return cfg; + + if (xlate) + cfg |= I8042_CMD_BYTE_XLATE; + else + cfg &= ~I8042_CMD_BYTE_XLATE; + return i8042_cmd_with_data(I8042_CMD_WR_CMD_BYTE, cfg); +} diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index 6d15d1e0c5b..bcb42fd13dd 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -56,9 +56,6 @@ #define I8042_MODE_SCROLL_LOCK_ON (1 << 0) #define I8042_MODE_SCROLL_LOCK_OFF (0 << 0) #define I8042_KBCMD_SET_SCANCODE 0xf0 -#define I8042_SCANCODE_SET_1 (1) -#define I8042_SCANCODE_SET_2 (2) -#define I8042_SCANCODE_SET_3 (3) #define I8042_KBCMD_SET_TYPEMATIC 0xf3 #define I8042_KBCMD_EN 0xf4 #define I8042_KBCMD_DEFAULT_DIS 0xf5 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 2dec3a38f2c..91a51bb0ee7 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -28,6 +28,7 @@ */ #include +#include #include #include @@ -35,6 +36,12 @@ #include "i8042.h" +#ifdef DEBUG +#define debug(x...) printf(x) +#else +#define debug(x...) do {} while (0) +#endif + #define POWER_BUTTON 0x90 #define MEDIA_KEY_PREFIX 0xE0 @@ -171,16 +178,253 @@ static struct layout_maps keyboard_layouts[] = { #endif }; +static void keyboard_drain_input(void) +{ + while (i8042_data_ready_ps2()) + (void)i8042_read_data_ps2(); +} + static bool keyboard_cmd(unsigned char cmd) { + const uint64_t timeout_us = cmd == I8042_KBCMD_RESET ? 1*1000*1000 : 200*1000; + const uint64_t start_time = timer_us(0); + i8042_write_data(cmd); - return i8042_wait_read_ps2() == 0xfa; + do { + if (!i8042_data_ready_ps2()) { + udelay(50); + continue; + } + + const uint8_t data = i8042_read_data_ps2(); + switch (data) { + case 0xfa: + return true; + case 0xfe: + return false; + default: + /* Warn only if we already disabled keyboard input. */ + if (cmd != I8042_KBCMD_DEFAULT_DIS) + debug("WARNING: Keyboard sent spurious 0x%02x.\n", data); + break; + } + } while (timer_us(start_time) < timeout_us); + + debug("ERROR: Keyboard command timed out.\n"); + return false; +} + +static bool set_scancode_set(const unsigned char set) +{ + bool ret; + + if (set < 1 || set > 3) + return false; + + ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); + if (!ret) { + debug("ERROR: Keyboard set scancode failed!\n"); + return ret; + } + + ret = keyboard_cmd(set); + if (!ret) { + debug("ERROR: Keyboard scancode set#%u failed!\n", set); + return ret; + } + + return ret; +} + +static enum keyboard_state { + STATE_INIT = 0, + STATE_SIMPLIFIED_INIT, + STATE_DISABLE_SCAN, + STATE_DRAIN_INPUT, + STATE_DISABLE_TRANSLATION, + STATE_START_SELF_TEST, + STATE_SELF_TEST, + STATE_CONFIGURE, + STATE_CONFIGURE_SET1, + STATE_ENABLE_TRANSLATION, + STATE_ENABLE_SCAN, + STATE_RUNNING, + STATE_IGNORE, +} keyboard_state; + +#define STATE_NAMES_ENTRY(name) [STATE_##name] = #name +static const char *const state_names[] = { + STATE_NAMES_ENTRY(INIT), + STATE_NAMES_ENTRY(SIMPLIFIED_INIT), + STATE_NAMES_ENTRY(DISABLE_SCAN), + STATE_NAMES_ENTRY(DRAIN_INPUT), + STATE_NAMES_ENTRY(DISABLE_TRANSLATION), + STATE_NAMES_ENTRY(START_SELF_TEST), + STATE_NAMES_ENTRY(SELF_TEST), + STATE_NAMES_ENTRY(CONFIGURE), + STATE_NAMES_ENTRY(CONFIGURE_SET1), + STATE_NAMES_ENTRY(ENABLE_TRANSLATION), + STATE_NAMES_ENTRY(ENABLE_SCAN), + STATE_NAMES_ENTRY(RUNNING), + STATE_NAMES_ENTRY(IGNORE), +}; + +__attribute__((unused)) +static const char *state_name(enum keyboard_state state) +{ + if (state >= ARRAY_SIZE(state_names) || !state_names[state]) + return ""; + return state_names[state]; +} + +static uint64_t keyboard_time; +static uint64_t state_time; + +static void keyboard_poll(void) +{ + enum keyboard_state next_state = keyboard_state; + unsigned int i; + + switch (keyboard_state) { + + case STATE_INIT: + /* Wait until keyboard_init() has been called. */ + break; + + case STATE_SIMPLIFIED_INIT: + /* On the first try, start opportunistically, do + the first steps at once and skip the self-test. */ + (void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS); + keyboard_drain_input(); + (void)i8042_set_kbd_translation(false); + next_state = STATE_CONFIGURE; + break; + + case STATE_DISABLE_SCAN: + (void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS); + next_state = STATE_DRAIN_INPUT; + break; + + case STATE_DRAIN_INPUT: + /* Limit number of bytes drained per poll. */ + for (i = 0; i < 50 && i8042_data_ready_ps2(); ++i) + (void)i8042_read_data_ps2(); + if (i == 0) + next_state = STATE_DISABLE_TRANSLATION; + break; + + case STATE_DISABLE_TRANSLATION: + /* Be opportunistic and assume it's disabled on failure. */ + (void)i8042_set_kbd_translation(false); + next_state = STATE_START_SELF_TEST; + break; + + case STATE_START_SELF_TEST: + if (!keyboard_cmd(I8042_KBCMD_RESET)) + debug("ERROR: Keyboard self-test couldn't be started.\n"); + /* We ignore errors and always move to the self-test state + which will simply try again if necessary. */ + next_state = STATE_SELF_TEST; + break; + + case STATE_SELF_TEST: + if (!i8042_data_ready_ps2()) { + if (timer_us(state_time) > 5*1000*1000) { + debug("WARNING: Keyboard self-test timed out.\n"); + next_state = STATE_DISABLE_SCAN; + } + break; + } + + const uint8_t self_test_result = i8042_read_data_ps2(); + switch (self_test_result) { + case 0xaa: + debug("INFO: Keyboard self-test succeeded.\n"); + next_state = STATE_CONFIGURE; + break; + case 0xfc: + case 0xfd: + /* Failure. Try again. */ + debug("WARNING: Keyboard self-test failed.\n"); + next_state = STATE_START_SELF_TEST; + break; + default: + debug("WARNING: Keyboard self-test received spurious 0x%02x\n", + self_test_result); + break; + } + break; + + case STATE_CONFIGURE: + if (set_scancode_set(2)) + next_state = STATE_ENABLE_TRANSLATION; + else + next_state = STATE_CONFIGURE_SET1; + break; + + case STATE_CONFIGURE_SET1: + if (!set_scancode_set(1)) { + debug("ERROR: Keyboard failed to set any scancode set.\n"); + next_state = STATE_DISABLE_SCAN; + break; + } + + next_state = STATE_ENABLE_SCAN; + break; + + case STATE_ENABLE_TRANSLATION: + if (i8042_set_kbd_translation(true) != 0) { + debug("ERROR: Keyboard controller set translation failed!\n"); + next_state = STATE_DISABLE_SCAN; + break; + } + + next_state = STATE_ENABLE_SCAN; + break; + + case STATE_ENABLE_SCAN: + if (!keyboard_cmd(I8042_KBCMD_EN)) { + debug("ERROR: Keyboard enable scanning failed!\n"); + next_state = STATE_DISABLE_SCAN; + break; + } + + next_state = STATE_RUNNING; + break; + + case STATE_RUNNING: + /* TODO: Use echo command to detect detach. */ + break; + + case STATE_IGNORE: + /* TODO: Try again after timeout if it ever seems useful. */ + break; + + } + + switch (next_state) { + case STATE_INIT: + case STATE_RUNNING: + case STATE_IGNORE: + break; + default: + if (timer_us(keyboard_time) > 30*1000*1000) + next_state = STATE_IGNORE; + break; + } + + if (keyboard_state != next_state) { + debug("INFO: Keyboard advancing state to '%s'.\n", state_name(next_state)); + keyboard_state = next_state; + state_time = timer_us(0); + } } bool keyboard_havechar(void) { - return i8042_data_ready_ps2(); + keyboard_poll(); + return keyboard_state == STATE_RUNNING && i8042_data_ready_ps2(); } unsigned char keyboard_get_scancode(void) @@ -313,83 +557,22 @@ static struct console_input_driver cons = { .input_type = CONSOLE_INPUT_TYPE_EC, }; -/* Enable keyboard translated */ -static bool enable_translated(void) -{ - if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) { - int cmd = i8042_read_data_ps2(); - cmd |= I8042_CMD_BYTE_XLATE; - if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) { - i8042_write_data(cmd); - } else { - printf("ERROR: i8042_cmd WR_CMD failed!\n"); - return false; - } - } else { - printf("ERROR: i8042_cmd RD_CMD failed!\n"); - return false; - } - return true; -} - -/* Set scancode set 1 */ -static bool set_scancode_set(void) -{ - bool ret; - ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret) { - printf("ERROR: Keyboard set scancode failed!\n"); - return ret; - } - - ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret) { - printf("ERROR: Keyboard scancode set#1 failed!\n"); - return ret; - } - - /* - * Set default parameters. - * Fix for broken QEMU PS/2 make scancodes. - */ - ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT); - if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); - return ret; - } - - /* Enable scanning */ - ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret) { - printf("ERROR: Keyboard enable scanning failed!\n"); - return ret; - } - - return ret; -} - void keyboard_init(void) { + if (keyboard_state != STATE_INIT) + return; + map = &keyboard_layouts[0]; /* Initialized keyboard controller. */ if (!i8042_probe() || !i8042_has_ps2()) return; - /* Empty keyboard buffer */ - while (keyboard_havechar()) - keyboard_getchar(); - /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - if (CONFIG(LP_PC_KEYBOARD_AT_TRANSLATED)) { - if (!enable_translated()) - return; - } else { - if (!set_scancode_set()) - return; - } + keyboard_state = STATE_SIMPLIFIED_INIT; + keyboard_time = state_time = timer_us(0); console_add_input_driver(&cons); } @@ -404,20 +587,18 @@ void keyboard_disconnect(void) if (!i8042_has_ps2()) return; - /* Empty keyboard buffer */ - while (keyboard_havechar()) - keyboard_getchar(); - /* Disable scanning */ keyboard_cmd(I8042_KBCMD_DEFAULT_DIS); + keyboard_drain_input(); /* Send keyboard disconnect command */ i8042_cmd(I8042_CMD_DIS_KB); /* Hand off with empty buffer */ - while (keyboard_havechar()) - keyboard_getchar(); + keyboard_drain_input(); /* Release keyboard controller driver */ i8042_close(); + + keyboard_state = STATE_INIT; } diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index f206fea2f97..a33d8bb3827 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -233,11 +233,15 @@ u8 i8042_data_ready_ps2(void); u8 i8042_data_ready_aux(void); u8 i8042_read_data_ps2(void); +u8 i8042_peek_data_ps2(void); u8 i8042_read_data_aux(void); int i8042_wait_read_ps2(void); int i8042_wait_read_aux(void); +int i8042_get_kbd_translation(void); +int i8042_set_kbd_translation(bool xlate); + /** @} */ /** diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile index eb70af90b79..637e45dee1d 100644 --- a/payloads/libpayload/sample/Makefile +++ b/payloads/libpayload/sample/Makefile @@ -28,7 +28,7 @@ # Sample libpayload Makefile. include ../.config -include ../.xcompile +include ../build/xcompile ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index ee3de1cde09..db3e522d605 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -37,7 +37,7 @@ static int max(int x, int y) return y; } -void render_form(FORM *form) +static void render_form(FORM *form) { int y, x, line; WINDOW *w = form_win(form); diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 07008db7a92..2727889f9e6 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -24,8 +24,11 @@ config ACPI_INTEL_HARDWARE_SLEEP_VALUES Provide common definitions for Intel hardware PM1_CNT register sleep values. -config ACPI_NO_SMI_GNVS +config ACPI_SOC_NVS bool + help + Set to indicate exists for the platform with a definition + for global_nvs. config ACPI_NO_PCAT_8259 bool @@ -37,3 +40,9 @@ config HAVE_ACPI_TABLES help This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. + +config ACPI_LPIT + bool + depends on HAVE_ACPI_TABLES + help + Selected by platforms that support and fill Intel Low Power Idle Table. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 2f06be1a2cc..86f29e46814 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c -ramstage-y += acpi_pm.c ramstage-y += acpigen.c ramstage-y += acpigen_dptf.c ramstage-y += acpigen_dsm.c @@ -11,12 +10,13 @@ ramstage-y += acpigen_ps2_keybd.c ramstage-y += acpigen_usb.c ramstage-y += device.c ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c -ramstage-y += gnvs.c +ramstage-$(CONFIG_ACPI_SOC_NVS) += gnvs.c ramstage-y += pld.c ramstage-y += sata.c ramstage-y += soundwire.c -postcar-y += acpi_pm.c +all-y += acpi_pm.c +smm-y += acpi_pm.c ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2bc75503b33..6e900a9b2a0 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -878,6 +878,35 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, header->checksum = acpi_checksum((void *)ivrs, header->length); } +void acpi_create_crat(struct acpi_crat_header *crat, + unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, + unsigned long current)) +{ + acpi_header_t *header = &(crat->header); + unsigned long current = (unsigned long)crat + sizeof(struct acpi_crat_header); + + memset((void *)crat, 0, sizeof(struct acpi_crat_header)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "CRAT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->length = sizeof(struct acpi_crat_header); + header->revision = get_acpi_table_revision(CRAT); + + current = acpi_fill_crat(crat, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)crat; + header->checksum = acpi_checksum((void *)crat, header->length); +} + unsigned long acpi_write_hpet(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -1264,6 +1293,44 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) acpi_checksum((void *) fadt, header->length); } +void acpi_create_lpit(acpi_lpit_t *lpit) +{ + acpi_header_t *header = &(lpit->header); + unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t); + + memset((void *)lpit, 0, sizeof(acpi_lpit_t)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "LPIT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->revision = get_acpi_table_revision(LPIT); + header->oem_revision = 42; + header->length = sizeof(acpi_lpit_t); + + current = acpi_fill_lpit(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)lpit; + header->checksum = acpi_checksum((void *)lpit, header->length); +} + +unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid) +{ + memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t)); + lpi_desc->header.length = sizeof(acpi_lpi_desc_ncst_t); + lpi_desc->header.type = ACPI_LPI_DESC_TYPE_NATIVE_CSTATE; + lpi_desc->header.uid = uid; + + return lpi_desc->header.length; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -1284,6 +1351,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_tcpa_t *tcpa; acpi_tpm2_t *tpm2; acpi_madt_t *madt; + acpi_lpit_t *lpit; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -1404,6 +1472,10 @@ unsigned long write_acpi_tables(unsigned long start) current += sizeof(acpi_header_t); acpigen_set_current((char *) current); + + if (CONFIG(ACPI_SOC_NVS)) + acpi_fill_gnvs(); + for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_inject_dsdt) dev->ops->acpi_inject_dsdt(dev); @@ -1478,6 +1550,18 @@ unsigned long write_acpi_tables(unsigned long start) } } + if (CONFIG(ACPI_LPIT)) { + printk(BIOS_DEBUG, "ACPI: * LPIT\n"); + + lpit = (acpi_lpit_t *)current; + acpi_create_lpit(lpit); + if (lpit->header.length >= sizeof(acpi_lpit_t)) { + current += lpit->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, lpit); + } + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; @@ -1486,6 +1570,7 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); } + current = acpi_align_current(current); printk(BIOS_DEBUG, "current = %lx\n", current); @@ -1636,6 +1721,10 @@ int get_acpi_table_revision(enum acpi_tables table) return 5; case BERT: return 1; + case CRAT: + return 1; + case LPIT: /* ACPI 5.1 up to 6.3: 0 */ + return 0; default: return -1; } diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c index 540b6d2bee0..bee5616e57d 100644 --- a/src/acpi/acpi_pm.c +++ b/src/acpi/acpi_pm.c @@ -1,32 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include -#include #include -/* This is filled with acpi_handoff_wakeup_s3() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_handoff_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - void __weak mainboard_suspend_resume(void) { } @@ -48,3 +27,43 @@ uint8_t acpi_get_preferred_pm_profile(void) return PM_UNSPECIFIED; } } + +struct chipset_power_state *acpi_get_pm_state(void) +{ + static struct chipset_power_state *acpi_pm_state; + if (acpi_pm_state) + return acpi_pm_state; + + acpi_pm_state = cbmem_find(CBMEM_ID_POWER_STATE); + return acpi_pm_state; +} + +int acpi_pm_state_for_elog(const struct chipset_power_state **ps) +{ + *ps = acpi_get_pm_state(); + if (!*ps) { + printk(BIOS_ERR, "No CBMEM_ID_POWER_STATE entry, no event recorded in ELOG.\n"); + return -1; + } + return 0; +} + +int acpi_pm_state_for_rtc(const struct chipset_power_state **ps) +{ + *ps = acpi_get_pm_state(); + if (!*ps) { + printk(BIOS_ERR, "No CBMEM_ID_POWER_STATE entry, RTC init aborted.\n"); + return -1; + } + return 0; +} + +int acpi_pm_state_for_wake(const struct chipset_power_state **ps) +{ + *ps = acpi_get_pm_state(); + if (!*ps) { + printk(BIOS_ERR, "No CBMEM_ID_POWER_STATE entry, wake source unknown.\n"); + return -1; + } + return 0; +} diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c index 4bcf8927450..060d56d44b0 100644 --- a/src/acpi/chromeos-gnvs.c +++ b/src/acpi/chromeos-gnvs.c @@ -2,11 +2,13 @@ #include #include +#include #include -void gnvs_assign_chromeos(void) +void gnvs_assign_chromeos(void *gnvs_section) { - chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(); + chromeos_acpi_t *gnvs_chromeos = gnvs_section; + chromeos_init_chromeos_acpi(gnvs_chromeos); /* EC can override to ECFW_RW. */ @@ -15,3 +17,22 @@ void gnvs_assign_chromeos(void) if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; } + +void gnvs_set_ecfw_rw(void) +{ + chromeos_acpi_t *gnvs_chromeos = chromeos_get_chromeos_acpi(); + if (!gnvs_chromeos) + return; + + gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; +} + +void smbios_type0_bios_version(uintptr_t address) +{ + chromeos_acpi_t *gnvs_chromeos = chromeos_get_chromeos_acpi(); + if (!gnvs_chromeos) + return; + + /* Location of smbios_type0.bios_version() string filled with spaces. */ + gnvs_chromeos->vbt10 = address; +} diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index fbc84b36fd4..a895a83e83d 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -4,10 +4,13 @@ #include #include #include +#include +#include #include #include +#include -static void *gnvs; +static struct global_nvs *gnvs; void *acpi_get_gnvs(void) { @@ -22,48 +25,47 @@ void *acpi_get_gnvs(void) return NULL; } -static void gnvs_assign_cbmc(void) -{ - uint32_t *gnvs_cbmc = gnvs_cbmc_ptr(); - if (gnvs_cbmc) - *gnvs_cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); -} +__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { } +__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { } -void *gnvs_get_or_create(void) +void acpi_create_gnvs(void) { size_t gnvs_size; - if (gnvs) - return gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) - return gnvs; + if (cbmem_find(CBMEM_ID_ACPI_GNVS)) + return; - gnvs_size = gnvs_size_of_array(); + /* Match with OpRegion declared in global_nvs.asl. */ + gnvs_size = sizeof(struct global_nvs); + if (gnvs_size < 0x100) + gnvs_size = 0x100; + if (gnvs_size > 0x1000) + gnvs_size = 0x2000; + else if (CONFIG(MAINBOARD_HAS_CHROMEOS)) + gnvs_size = 0x1000; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size); if (!gnvs) - return gnvs; + return; memset(gnvs, 0, gnvs_size); if (CONFIG(CONSOLE_CBMEM)) - gnvs_assign_cbmc(); + gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); if (CONFIG(CHROMEOS)) - gnvs_assign_chromeos(); - - return gnvs; + gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET); } -void acpi_inject_nvsa(void) +void acpi_fill_gnvs(void) { - uintptr_t gnvs_address = (uintptr_t)acpi_get_gnvs(); - if (!gnvs_address) + if (!gnvs) return; + soc_fill_gnvs(gnvs); + mainboard_fill_gnvs(gnvs); + acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", gnvs_address); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); acpigen_pop_len(); } diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index f70b5299726..c767b06ed07 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -14,6 +14,8 @@ config ARCH_RAMSTAGE_ARMV8_64 bool select ARCH_RAMSTAGE_ARM64 +if ARCH_ARM64 + config ARCH_ARMV8_EXTENSION int default 0 @@ -25,3 +27,5 @@ config ARCH_ARMV8_EXTENSION All ARMv8 implementations are downwards-compatible, so this does not need to be changed unless specific features (e.g. new instructions) are used by the SoC's coreboot code. + +endif # ARCH_ARM64 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 00917f0b693..cfefec605f2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -45,25 +45,6 @@ pci$(stripped_vgabios_dgpu_id).rom-type := optionrom # common support for early assembly includes ############################################################################### -# Chipset specific assembly stubs in the romstage program flow. Certain -# boards have more than one assembly stub so collect those and put them -# into a single generated file. -crt0s = $(cpu_incs-y) - -$(objgenerated)/assembly.inc: build-dirs $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ - - -define early_x86_assembly_entry_rule -# $1 stage name -# Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated assembly.inc is a proper -# dependency. -$(1)-y += assembly_entry.S -$(call src-to-obj,$(1),$(dir)/assembly_entry.S): $(objgenerated)/assembly.inc -endef - define early_x86_stage # $1 stage name # $2 oformat @@ -122,6 +103,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage-y += assembly_entry.S verstage-y += boot.c verstage-y += post.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S @@ -143,8 +125,6 @@ verstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c verstage-libs ?= -$(eval $(call early_x86_assembly_entry_rule,verstage)) - ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y) $(eval $(call early_x86_stage,verstage,elf32-i386)) else @@ -159,6 +139,7 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) +romstage-y += assembly_entry.S romstage-y += boot.c romstage-y += post.c romstage-y += gdt_init.S @@ -176,8 +157,6 @@ romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= -$(eval $(call early_x86_assembly_entry_rule,romstage)) - ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call early_x86_stage,romstage,elf32-i386)) else @@ -315,6 +294,4 @@ smm-y += memmove.c smm-y += memset.c smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),) -smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c -endif +smm-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 43a68f95f44..ec1fafcd3cf 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include @@ -18,9 +17,6 @@ extern unsigned int __wakeup_size; void __noreturn acpi_resume(void *wake_vec) { - /* Restore GNVS pointer in SMM if found. */ - apm_control(APM_CNT_GNVS_UPDATE); - /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index ad9c2efaa1b..479259fcbe2 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -19,14 +19,19 @@ SECTIONS { .id (.): { KEEP(*(.id)); } - _ID_SECTION = 0xffffff80 - SIZEOF(.id); - . = 0xffffffc0; + /* Flashrom and FILO have two alternatives for the location of .id section. */ + _ID_SECTION_END = SIZEOF(.fit_pointer) && SIZEOF(.id) > 0x28 ? 0xffffff80 : _X86_RESET_VECTOR; + _ID_SECTION = _ID_SECTION_END - SIZEOF(.id); + + . = _FIT_POINTER; .fit_pointer (.): { KEEP(*(.fit_pointer)); } + _FIT_POINTER = SIZEOF(.fit_pointer) ? 0xffffffc0 : _X86_RESET_VECTOR; . = 0xfffffff0; + _X86_RESET_VECTOR = .; .reset . : { *(.reset); . = 15; diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 82ae97f9c6a..387920e38af 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,7 +10,7 @@ #include -.section .text._start +.section .init._start, "ax", @progbits /* * Include the old code for reset vector and protected mode entry. That code has diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 9f8c2ad0455..68144c9d436 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -7,6 +7,7 @@ . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_region_start = . ; + . += CONFIG_FSP_M_RC_HEAP_SIZE; #if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ @@ -80,13 +81,25 @@ REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) #endif _car_unallocated_start = .; - _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) + - CONFIG_FSP_T_RESERVED_SIZE; } + +. = _car_region_start; +.car.fspm_rc_heap . (NOLOAD) : { +. += CONFIG_FSP_M_RC_HEAP_SIZE; +} + . = _car_region_end; .car.mrc_var . (NOLOAD) : { . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE; } +. = _car_region_end; +.car.fspt_reserved . (NOLOAD) : { + . += CONFIG_FSP_T_RESERVED_SIZE; +} + #if ENV_BOOTBLOCK _car_mtrr_end = .; _car_mtrr_start = _car_region_start; diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index 1558ac62c8d..f33a1517d82 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ .code32 -.section ".text._gdt_", "ax", @progbits + +.section .init, "ax", @progbits + +.section .init._gdt_, "ax", @progbits .globl gdt_init gdt_init: @@ -17,7 +20,7 @@ gdtptr: #ifdef __x86_64__ .code64 -.section ".text._gdt64_", "ax", @progbits +.section .init._gdt64_, "ax", @progbits .globl gdt_init64 gdt_init64: /* Workaround a bug in the assembler. diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index dcacc70445a..1df8c44366c 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -23,8 +23,12 @@ void main(void) /* * CBMEM needs to be recovered because timestamps rely on * the cbmem infrastructure being around. Explicitly recover it. + * + * On some platforms CBMEM needs to be initialized earlier. + * Use cbmem_online() to avoid init CBMEM twice. */ - cbmem_initialize(); + if (!cbmem_online()) + cbmem_initialize(); timestamp_add_now(TS_START_POSTCAR); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index aaf989da192..87714c0abed 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -16,9 +16,6 @@ #include #include #include -#if CONFIG(CHROMEOS) -#include -#endif #include #include @@ -330,8 +327,22 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, t->minimum_voltage = dimm->vdd_voltage; t->maximum_voltage = dimm->vdd_voltage; + /* Fill in type detail */ + switch (dimm->mod_type) { + case SPD_RDIMM: + case SPD_MINI_RDIMM: + t->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; + break; + case SPD_UDIMM: + case SPD_MINI_UDIMM: + t->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; + break; + default: + t->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + } /* Synchronous = 1 */ - t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS; + t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS; /* no handle for error information */ t->memory_error_information_handle = 0xFFFE; t->attributes = dimm->rank_per_dimm; @@ -411,11 +422,12 @@ static int smbios_write_type0(unsigned long *current, int handle) t->vendor = smbios_add_string(t->eos, "coreboot"); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); -#if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES) - u32 version_offset = (u32)smbios_string_table_len(t->eos); - /* SMBIOS offsets start at 1 rather than 0 */ - chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1); -#endif + if (CONFIG(CHROMEOS)) { + uintptr_t version_address = (uintptr_t)t->eos; + /* SMBIOS offsets start at 1 rather than 0 */ + version_address += (u32)smbios_string_table_len(t->eos) - 1; + smbios_type0_bios_version(version_address); + } t->bios_version = smbios_add_string(t->eos, get_bios_version()); uint32_t rom_size = CONFIG_ROM_SIZE; rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB); diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index b8d4fb985ab..393bcf54edb 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -21,7 +21,7 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) .code32 -.section .text +.section .init .global walkcbfs_asm /* diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 4bcda64a141..bcda7ada0fb 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -57,6 +57,7 @@ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 +#define CBMEM_ID_TPM_PPI 0x54505049 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 /* deprecated */ #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */ #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index c740975bc7e..be40c3818f1 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -81,6 +81,7 @@ enum { LB_TAG_FMAP = 0x0037, LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, LB_TAG_SMMSTOREV2 = 0x0039, + LB_TAG_TPM_PPI_HANDOFF = 0x003a, LB_TAG_BOARD_CONFIG = 0x0040, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, @@ -521,4 +522,27 @@ struct lb_smmstorev2 { uint8_t unused[3]; /* Set to zero */ }; +enum lb_tmp_ppi_tpm_version { + LB_TPM_VERSION_UNSPEC = 0, + LB_TPM_VERSION_TPM_VERSION_1_2, + LB_TPM_VERSION_TPM_VERSION_2, +}; + +/* + * Handoff buffer for TPM Physical Presence Interface. + * * ppi_address Pointer to PPI buffer shared with ACPI + * The layout of the buffer matches the QEMU virtual memory device + * that is generated by QEMU. + * See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h' + * for details. + * * tpm_version TPM version: 1 for TPM1.2, 2 for TPM2.0 + * * ppi_version BCD encoded version of TPM PPI interface + */ +struct lb_tpm_physical_presence { + uint32_t tag; + uint32_t size; + uint32_t ppi_address; /* Address of ACPI PPI communication buffer */ + uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ + uint8_t ppi_version; /* BCD encoded */ +} __packed; #endif diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 1ccfa5d15ba..b144fc1ca17 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -14,7 +14,6 @@ config CPU_AMD_AGESA select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 - select ACPI_NO_SMI_GNVS if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index dff896f016d..d3a94a8c216 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -13,7 +13,6 @@ config CPU_AMD_PI select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 - select ACPI_NO_SMI_GNVS if CPU_AMD_PI diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c8c9a..2c672071541 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,7 @@ #include #include +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cde1ca3d154..0451bb4dd5e 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -7,6 +7,7 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e +.section .init .global bootblock_pre_c_entry #include diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e344778f7..887bb22477d 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,7 @@ #include #include +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e365384141..103d9e97f99 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -8,6 +8,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 98666843e94..3b18e0b6aab 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -6,16 +6,14 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) -INTERMEDIATE+=add_mcu_fit -add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_mcu_fit, $(IFITTOOL)) @printf " UPDATE-FIT Microcode\n" $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT # Second FIT in TOP_SWAP bootblock ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) -INTERMEDIATE+=add_ts_mcu_fit -add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_ts_mcu_fit, $(IFITTOOL)) @printf " UPDATE-FIT Top Swap: Microcode\n" ifneq ($(FIT_ENTRY),) $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b93b911aeb2..bfb501133cf 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,4 +1,6 @@ ramstage-y += haswell_init.c + +romstage-y += romstage.c romstage-y += ../car/romstage.c ramstage-y += acpi.c @@ -23,3 +25,7 @@ subdirs-y += ../turbo cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) + +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin +endif diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 6dd8559d225..0f11e5f8d9a 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,24 @@ #include +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10, +}; + +static int cstate_set_lp[3] = { + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT, +}; + +static int cstate_set_trad[3] = { + C_STATE_C1, + C_STATE_C3, + C_STATE_C6_LONG_LAT, +}; + static int get_cores_per_package(void) { struct cpuinfo_x86 c; @@ -30,41 +48,6 @@ static int get_cores_per_package(void) return cores; } -static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -117,20 +100,29 @@ static void generate_T_state_entries(int core, int cores_per_package) ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } +static bool is_s0ix_enabled(void) +{ + if (!haswell_is_ult()) + return false; + + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (!lapic || !lapic->chip_info) + return false; + + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + return conf->s0ix_enable; +} + static void generate_C_state_entries(void) { + acpi_cstate_t map[3]; + int *set; + int i; + struct cpu_info *info; struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; /* Find CPU map of supported C-states */ info = cpu_info(); @@ -140,25 +132,20 @@ static void generate_C_state_entries(void) if (!cpu || !cpu->cstates) return; - acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); + if (is_s0ix_enabled()) + set = cstate_set_s0ix; + else if (haswell_is_ult()) + set = cstate_set_lp; + else + set = cstate_set_trad; - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); + for (i = 0; i < ARRAY_SIZE(map); i++) { + map[i] = cpu->cstates[set[i]]; + map[i].ctype = i + 1; + } + + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -209,7 +196,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * HASWELL_BCLK; + clock_max = ratio_max * CPU_BCLK; /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -273,7 +260,7 @@ static void generate_P_state_entries(int core, int cores_per_package) /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * HASWELL_BCLK; + clock = ratio * CPU_BCLK; acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index c9e3f2abadd..7066637f248 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "haswell.h" @@ -50,6 +51,10 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Set soft reset control to use register value */ RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Delay before reset to avoid potential TPM lockout */ + if (CONFIG(TPM1) || CONFIG(TPM2)) + mdelay(30); + /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 7d414613882..776e23903be 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,16 +3,38 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC -struct cpu_intel_haswell_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ +#include +#include + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; +struct cpu_intel_haswell_config { int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; + + /* Enable S0iX support */ + bool s0ix_enable; }; diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 9349a3d654a..133a12945da 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -3,40 +3,62 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H +#include #include -/* Haswell CPU types */ -#define HASWELL_FAMILY_MOBILE 0x306c0 -#define HASWELL_FAMILY_ULT 0x40650 +/* CPU types without stepping */ +#define HASWELL_FAMILY_TRAD 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 +#define CRYSTALWELL_FAMILY 0x306c0 +#define BROADWELL_FAMILY_ULT 0x306d0 -/* Haswell CPU steppings */ -#define HASWELL_STEPPING_MOBILE_A0 1 -#define HASWELL_STEPPING_MOBILE_B0 2 -#define HASWELL_STEPPING_MOBILE_C0 3 -#define HASWELL_STEPPING_MOBILE_D0 4 -#define HASWELL_STEPPING_ULT_B0 0 -#define HASWELL_STEPPING_ULT_C0 1 +/* Haswell CPUIDs */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 -/* Haswell bus clock is fixed at 100MHz */ -#define HASWELL_BCLK 100 +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT_C0 0x40651 + +/* Crystalwell CPUIDs */ +#define CPUID_CRYSTALWELL_B0 0x40660 +#define CPUID_CRYSTALWELL_C0 0x40661 + +/* Broadwell CPUIDs */ +#define CPUID_BROADWELL_C0 0x40671 + +#define CPUID_BROADWELL_ULT_C0 0x306d2 +#define CPUID_BROADWELL_ULT_D0 0x306d3 +#define CPUID_BROADWELL_ULT_E0 0x306d4 + +/* Haswell and Broadwell bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define TIMED_MWAIT_SUPPORTED (1 << (37 - 32)) +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) #define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_LT_LOCK_MEMORY 0x2e7 - -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 - #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b @@ -53,7 +75,7 @@ #define IRTL_33554432_NS (5 << 10) #define IRTL_RESPONSE_MASK (0x3ff) -/* long duration in low dword, short duration in high dword */ +/* Long duration in low dword, short duration in high dword */ #define MSR_PKG_POWER_LIMIT 0x610 #define PKG_POWER_LIMIT_MASK 0x7fff #define PKG_POWER_LIMIT_EN (1 << 15) @@ -76,18 +98,6 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) - -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 - -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 @@ -96,33 +106,26 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) +/* Intel suggested latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base) * 5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" @@ -137,6 +140,27 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif +/* + * List of supported C-states for Haswell and Broadwell. + * Only the ULT parts support C8, C9, and C10. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6_SHORT_LAT = 4, + C_STATE_C6_LONG_LAT = 5, + C_STATE_C7_SHORT_LAT = 6, + C_STATE_C7_LONG_LAT = 7, + C_STATE_C7S_SHORT_LAT = 8, + C_STATE_C7S_LONG_LAT = 9, + C_STATE_C8 = 10, + C_STATE_C9 = 11, + C_STATE_C10 = 12, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); @@ -144,9 +168,22 @@ void intel_cpu_haswell_finalize_smm(void); void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +void set_max_freq(void); + /* CPU identification */ -int haswell_family_model(void); -int haswell_stepping(void); -int haswell_is_ult(void); +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +static inline u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + +static inline int haswell_is_ult(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 32b6a9daf49..577061c9884 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,41 +20,6 @@ #include "haswell.h" #include "chip.h" -/* Intel suggested latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -186,27 +151,6 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -int haswell_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -int haswell_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int haswell_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) - ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); - - return ult; -} - /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ @@ -282,10 +226,39 @@ static u32 pcode_mailbox_read(u32 command) return MCHBAR32(BIOS_MAILBOX_DATA); } +static int pcode_mailbox_write(u32 command, u32 data) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return -1; + } + + MCHBAR32(BIOS_MAILBOX_DATA) = data; + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return -1; + } + + return 0; +} + static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr; + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n"); /* Configure VR_CURRENT_CONFIG. */ @@ -295,7 +268,7 @@ static void initialize_vr_config(void) msr.hi &= 0xc0000000; msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ if (haswell_is_ult()) msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ @@ -315,24 +288,41 @@ static void initialize_vr_config(void) msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ - if (haswell_is_ult()) { - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; - wrmsr(MSR_VR_MISC_CONFIG2, msr); - } + if (!haswell_is_ult()) + return; + + msr = rdmsr(MSR_VR_MISC_CONFIG2); + msr.lo &= ~0xffff; + /* Allow CPU to control minimum voltage completely (15:8) and + set the fast ramp voltage in 10mV steps. */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) + msr.lo |= 0x006a; /* 1.56V */ + else + msr.lo |= 0x006f; /* 1.60V */ + wrmsr(MSR_VR_MISC_CONFIG2, msr); + + /* Set C9/C10 VCC Min */ + pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); } static void configure_pch_power_sharing(void) @@ -403,8 +393,7 @@ void set_power_limits(u8 power_limit_1_time) u8 power_limit_1_val; if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - - 1; + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -468,7 +457,9 @@ void set_power_limits(u8 power_limit_1_time) static void configure_c_states(void) { - msr_t msr; + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + + const bool timed_mwait_capable = !!(msr.hi & TIMED_MWAIT_SUPPORTED); msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 30); // Package c-state Undemotion Enable @@ -478,14 +469,12 @@ static void configure_c_states(void) msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); - msr.lo &= ~0xffff; - msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address + if (timed_mwait_capable) + msr.lo |= (1 << 31); // Timed MWAIT Enable + /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination @@ -512,26 +501,24 @@ static void configure_c_states(void) msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - /* Haswell ULT only supoprts the 3-5 latency response registers.*/ - if (haswell_is_ult()) { - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); - } + /* Only Haswell ULT supports the 3-5 latency response registers */ + if (!haswell_is_ult()) + return; + + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } static void configure_thermal_target(void) @@ -584,7 +571,10 @@ static void set_max_ratio(void) perf_ctl.hi = 0; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; @@ -596,7 +586,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } static void configure_mca(void) @@ -616,7 +606,7 @@ static void configure_mca(void) } /* All CPUs including BSP will run the following function. */ -static void haswell_init(struct device *cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -643,9 +633,6 @@ static void haswell_init(struct device *cpu) /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -661,10 +648,11 @@ static void pre_mp_init(void) initialize_vr_config(); - if (haswell_is_ult()) { - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); - } + if (!haswell_is_ult()) + return; + + calibrate_24mhz_bclk(); + configure_pch_power_sharing(); } static int get_cpu_count(void) @@ -700,6 +688,9 @@ static void per_cpu_smm_trigger(void) static void post_mp_init(void) { + /* Set Max Ratio */ + set_max_ratio(); + /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ global_smi_enable(); @@ -726,17 +717,21 @@ void mp_init_cpus(struct bus *cpu_bus) } static struct device_operations cpu_dev_ops = { - .init = haswell_init, + .init = cpu_core_init, }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ - { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ - { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ - { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ - { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ - { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ - { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ + { X86_VENDOR_INTEL, CPUID_HASWELL_A0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0 }, + { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, + { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0 }, { 0, 0 }, }; diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/cpu/intel/haswell/romstage.c similarity index 91% rename from src/soc/intel/broadwell/cpu/romstage.c rename to src/cpu/intel/haswell/romstage.c index c9f70a85d1e..3b11e93cab3 100644 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -2,10 +2,8 @@ #include #include +#include #include -#include -#include -#include void set_max_freq(void) { diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 5173ae5a0ca..28705230a2a 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -44,7 +44,7 @@ */ .code32 -.section .text +.section .init .global update_bsp_microcode update_bsp_microcode: diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c1308948539..3e4de1fa31b 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -264,9 +264,6 @@ static void model_1067x_init(struct device *cpu) /* Test for TM2 only if EIST is available. */ const char tm2 = eist && (cpuid1.ecx & (1 << 8)); - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index b56d1069229..ff6cbec8dcf 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -33,7 +33,7 @@ static int get_cpu_count(void) static void get_microcode_info(const void **microcode, int *parallel) { *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 8c462f18741..278d8dea81f 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -63,9 +63,6 @@ static void model_106cx_init(struct device *cpu) { char processor_name[49]; - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 2d483ca7a5c..39d028bbbec 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -28,80 +28,9 @@ static int get_cores_per_package(void) return cores; } -static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - static void generate_C_state_entries(void) { - struct cpu_info *info; - struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_model_2065x_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; - - /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) - return; - cpu = find_cpu_driver(info->cpu); - if (!cpu || !cpu->cstates) - return; - - acpigen_write_method("_CST", 0); - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); + /* TODO */ } static acpi_tstate_t tss_table_fine[] = { @@ -195,15 +124,9 @@ static void generate_P_state_entries(int core, int cores_per_package) msr = rdmsr(MSR_PLATFORM_INFO); ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3; /* Calculate CPU TDP in mW */ diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index 21f75a3f561..4ee91f6821a 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -4,15 +4,5 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC struct cpu_intel_model_2065x_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ - int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 566f82ed89d..9c8b18039fc 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -43,13 +43,6 @@ #define PKG_POWER_LIMIT_TIME_SHIFT 17 #define PKG_POWER_LIMIT_TIME_MASK 0x7f -#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - /* P-state configuration */ #define PSS_MAX_ENTRIES 16 #define PSS_RATIO_STEP 1 @@ -61,7 +54,6 @@ void intel_model_2065x_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index db433536cf3..44552f59712 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -20,96 +20,6 @@ #include #include -/* - * List of supported C-states in this processor - * - * Latencies are typical worst-case package exit time in uS - * taken from the SandyBridge BIOS specification. - */ -static acpi_cstate_t cstate_map[] = { - { /* 0: C0 */ - }, { /* 1: C1 */ - .latency = 1, - .power = 1000, - .resource = { - .addrl = 0x00, /* MWAIT State 0 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } - }, - { /* 2: C1E */ - .latency = 1, - .power = 1000, - .resource = { - .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } - }, - { /* 3: C3 */ - .latency = 63, - .power = 500, - .resource = { - .addrl = 0x10, /* MWAIT State 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } - }, - { /* 4: C6 */ - .latency = 87, - .power = 350, - .resource = { - .addrl = 0x20, /* MWAIT State 2 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } - }, - { /* 5: C7 */ - .latency = 90, - .power = 200, - .resource = { - .addrl = 0x30, /* MWAIT State 3 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } - }, - { /* 6: C7S */ - .latency = 90, - .power = 200, - .resource = { - .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } - }, - { 0 } -}; - -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Minimum CPU revision */ - if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return 0; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - static void configure_thermal_target(void) { struct cpu_intel_model_2065x_config *conf; @@ -154,19 +64,12 @@ static void set_max_ratio(void) perf_ctl.hi = 0; - /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", + printk(BIOS_DEBUG, "model_x065x: frequency set to %d\n", ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); } @@ -185,9 +88,6 @@ static void model_2065x_init(struct device *cpu) { char processor_name[49]; - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Clear out pending MCEs */ configure_mca(); @@ -251,7 +151,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { microcode_patch = intel_microcode_find(); *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) @@ -307,5 +207,4 @@ static const struct cpu_device_id cpu_table[] = { static const struct cpu_driver driver __cpu_driver = { .ops = &cpu_dev_ops, .id_table = cpu_table, - .cstates = cstate_map, }; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index b24f411f00e..beb2fbc5792 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -31,8 +31,6 @@ static void generate_cstate_entries(acpi_cstate_t *cstates, ++cstate_count; if (c3 > 0) ++cstate_count; - if (!cstate_count) - return; acpigen_write_package(cstate_count + 1); acpigen_write_byte(cstate_count); @@ -78,20 +76,8 @@ static void generate_C_state_entries(void) return; acpigen_write_method("_CST", 0); - - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); - - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); + acpigen_emit_byte(RETURN_OP); + generate_cstate_entries(cpu->cstates, conf->acpi_c1, conf->acpi_c2, conf->acpi_c3); acpigen_pop_len(); } diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 4e40830f945..4fff04a7053 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -4,15 +4,9 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC struct cpu_intel_model_206ax_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ + int acpi_c1; /* ACPI C1 */ + int acpi_c2; /* ACPI C2 */ + int acpi_c3; /* ACPI C3 */ int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index b6e2d65e965..04e463934a8 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -6,6 +6,34 @@ #include #include +/* SandyBridge CPU stepping */ +#define SNB_STEP_B2 2 +#define SNB_STEP_C0 3 +#define SNB_STEP_D0 5 /* Also J0 */ +#define SNB_STEP_D1 6 +#define SNB_STEP_D2 7 /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 0 +#define IVB_STEP_B0 2 +#define IVB_STEP_C0 4 +#define IVB_STEP_K0 5 +#define IVB_STEP_D0 6 +#define IVB_STEP_E0 8 +#define IVB_STEP_E1 9 + +#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) +#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) +#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) +#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) +#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) + +#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) +#define IS_IVY_CPU_C(x) ((x & 0xf) == 4) +#define IS_IVY_CPU_K(x) ((x & 0xf) == 5) +#define IS_IVY_CPU_D(x) ((x & 0xf) == 6) +#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) + /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 2afbfeecec6..31099fd486e 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -425,9 +425,6 @@ static void model_206ax_report(void) static void model_206ax_init(struct device *cpu) { - /* Turn on caching if we haven't already */ - x86_enable_cache(); - /* Clear out pending MCEs */ configure_mca(); @@ -497,7 +494,7 @@ static void get_microcode_info(const void **microcode, int *parallel) { microcode_patch = intel_microcode_find(); *microcode = microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 36884a1b1ca..8dffceb4fdc 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -134,7 +134,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, if (smm_reloc_params.ied_size) setup_ied_area(&smm_reloc_params); - /* This may not be be correct for older CPU's supported by this code, + /* This may not be correct for older CPU's supported by this code, but given that em64t101_smm_state_save_area_t is larger than the save_state of these CPU's it works. */ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8db932ce580..537a0d1c5fa 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -17,7 +17,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy config DCACHE_RAM_SIZE hex - default 0x4000 # 16 kB + default 0x8000 # 32 kB config DCACHE_BSP_STACK_SIZE hex diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index fb560d6b7cc..3f27e8b2474 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += cache_as_ram_bootblock.S bootblock-y += bootblock.c +bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_64) += $(top)/src/arch/x86/walkcbfs.S romstage-y += ../intel/car/romstage.c diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 197e0fd8e89..07f848a0193 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -2,6 +2,15 @@ #include +#define CBFS_FILE_MAGIC 0 +#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) +#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) +#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) +#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) + +.section .init, "ax", @progbits +.code32 + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -22,12 +31,55 @@ cache_as_ram: post_code(0x21) +#if defined(__x86_64__) + /* + * Copy page tables to final location in DRAM. This prevents some strange + * bugs when running KVM enabled: + * Accessing MMX instructions in long mode causes an abort + * Some physical addresses aren't properly translated + * Emulation fault on every instruction fetched due to page tables in ROM + * Enabling or disabling paging causes a fault + * + * First, find page tables in CBFS: + */ + lea pagetables_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmpl $0, %eax + je .Lhlt + + /* Test if page tables are memory-mapped and skip relocation */ + cmpl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + je pages_done + + movl CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + addl %eax, %ebx + movl %ebx, %esi + + movl CBFS_FILE_LEN(%eax), %ecx + bswap %ecx + shr $2, %ecx + + movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %edi + +loop: + movl (%esi), %eax + movl %eax, (%edi) + addl $4, %esi + addl $4, %edi + decl %ecx + jnz loop +pages_done: +#endif + movl $_ecar_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ + /* entry64.inc preserves ebx. */ #include /* Restore the BIST result and timestamps. */ @@ -58,3 +110,6 @@ before_c_entry: post_code(POST_DEAD_CODE) hlt jmp .Lhlt + +pagetables_name: + .string "pagetables" diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 01c1d5fb832..c691c4882bd 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -344,9 +344,9 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params) sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) - sp->microcode_lock = 0; - else sp->microcode_lock = ~0; + else + sp->microcode_lock = 0; sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 879b8eff27a..aa301d0fe55 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -32,7 +32,7 @@ void set_var_mtrr( unsigned int reg, unsigned int base, unsigned int size, unsigned int type) { - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + /* Bit 32-35 of MTRRphysMask should be set to 1 */ /* FIXME: It only support 4G less range */ msr_t basem, maskm; diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 61d9e344663..f9b29576bdd 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -84,10 +84,9 @@ _start: mov idt_ptr, %ebx lidt (%ebx) - /* Obtain CPU number. */ - movl ap_count, %eax 1: - movl %eax, %ecx + /* Obtain CPU number. */ + movl ap_count, %ecx inc %ecx lock cmpxchg %ecx, ap_count jnz 1b @@ -103,12 +102,23 @@ _start: /* Save CPU number. */ mov %ecx, %esi + /* + * The following code only needs to run on Intel platforms and thus the caller + * doesn't provide a microcode_ptr if not on Intel. + * On Intel platforms which update microcode using FIT the version check will + * also skip the microcode update. + */ + /* Determine if one should check microcode versions. */ mov microcode_ptr, %edi test %edi, %edi jz microcode_done /* Bypass if no microde exists. */ /* Get the Microcode version. */ + xorl %eax, %eax + xorl %edx, %edx + movl $IA32_BIOS_SIGN_ID, %ecx + wrmsr mov $1, %eax cpuid mov $IA32_BIOS_SIGN_ID, %ecx @@ -117,6 +127,16 @@ _start: test %edx, %edx jnz microcode_done + /* + * Intel SDM and various BWGs specify to use a semaphore to update microcode + * on one thread per core on Hyper-Threading enabled CPUs. Due to this complex + * code would be necessary to determine the core #ID, initializing and picking + * the right semaphore out of CONFIG_MAX_CPUS / 2. + * Instead of the per core approachm, as recommended, use one global spinlock. + * Assuming that only pre-FIT platforms with Hyper-Threading enabled and at + * most 8 threads will ever run into this condition, the boot delay is negligible. + */ + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index eb386a69e50..1ed018d1be0 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -17,7 +17,7 @@ endif smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ -smm-c-deps:=$$(OPTION_TABLE_H) +smm-c-deps+=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $(smm-objs)) --no-whole-archive $(COMPILER_RT_smm) --end-group diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c index 4b637450b73..7e3ddb1613c 100644 --- a/src/cpu/x86/smm/smi_trigger.c +++ b/src/cpu/x86/smm/smi_trigger.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include -static void set_smm_gnvs_ptr(void); - int apm_control(u8 cmd) { if (!CONFIG(HAVE_SMI_HANDLER)) @@ -23,9 +20,6 @@ int apm_control(u8 cmd) case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n"); break; - case APM_CNT_GNVS_UPDATE: - set_smm_gnvs_ptr(); - return 0; case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "Finalizing SMM.\n"); break; @@ -45,32 +39,3 @@ int apm_control(u8 cmd) printk(BIOS_DEBUG, "APMC done.\n"); return 0; } - -static void set_smm_gnvs_ptr(void) -{ - uintptr_t gnvs_address; - - if (CONFIG(ACPI_NO_SMI_GNVS)) { - printk(BIOS_WARNING, "%s() is not implemented\n", __func__); - return; - } - - gnvs_address = (uintptr_t)acpi_get_gnvs(); - if (!gnvs_address) - return; - - /* - * Issue SMI to set the gnvs pointer in SMM. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" (gnvs_address), - "d" (APM_CNT) - ); -} diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3ba5684f353..8532d59b9db 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -134,8 +134,10 @@ asmlinkage void smm_handler_start(void *arg) /* Make sure to set the global runtime. It's OK to race as the value * will be the same across CPUs as well as multiple SMIs. */ - if (smm_runtime == NULL) + if (smm_runtime == NULL) { smm_runtime = runtime; + gnvs = (void *)(uintptr_t)smm_runtime->gnvs_ptr; + } if (cpu >= CONFIG_MAX_CPUS) { console_init(); diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index e3e9c28b7bc..715ea0afc76 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -332,7 +333,7 @@ static int smm_stub_place_staggered_entry_points(char *base, * * The save state and smm stack are treated as contiguous for the number of * concurrent areas requested. The save state always lives at the top of the - * the CPUS smbase (and the entry point is at offset 0x8000). This allows only a certain + * CPUS smbase (and the entry point is at offset 0x8000). This allows only a certain * number of CPUs with staggered entry points until the save state area comes * down far enough to overwrite/corrupt the entry code (stub code). Therefore, * an SMM map is created to avoid this corruption, see smm_create_map() above. @@ -447,6 +448,7 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size, stub_params->runtime.smm_size = smm_size; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; stub_params->runtime.num_cpus = params->num_concurrent_stacks; + stub_params->runtime.gnvs_ptr = (uintptr_t)acpi_get_gnvs(); printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", __func__, stub_params->stack_top - total_stack_size); diff --git a/src/device/Kconfig b/src/device/Kconfig index a472a6abbb7..bb4e913f358 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -46,6 +46,12 @@ config MAINBOARD_FORCE_NATIVE_VGA_INIT Selected by mainboards / chipsets whose graphics driver can't or shouldn't be disabled. +config VGA_ROM_RUN_DEFAULT + def_bool n + help + Selected by mainboards whose graphics initialization depends on VGA OpROM. + coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX. + config MAINBOARD_HAS_LIBGFXINIT def_bool n help @@ -54,8 +60,8 @@ config MAINBOARD_HAS_LIBGFXINIT choice prompt "Graphics initialization" - default NO_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS - default VGA_ROM_RUN if VGA_BIOS + default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS + default VGA_ROM_RUN if VGA_ROM_RUN_DEFAULT default MAINBOARD_DO_NATIVE_VGA_INIT default MAINBOARD_USE_LIBGFXINIT default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT @@ -690,6 +696,7 @@ config SUBSYSTEM_DEVICE_ID config VGA_BIOS bool "Add a VGA BIOS image" depends on ARCH_X86 + select VGA_ROM_RUN_DEFAULT help Select this option if you have a VGA BIOS image that you would like to add to your ROM. diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bb125afb8ff..808648d4b43 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -63,3 +63,5 @@ ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V3) += resource_allocator_v3.c ramstage-$(CONFIG_RESOURCE_ALLOCATOR_V4) += resource_allocator_v4.c ramstage-$(CONFIG_XHCI_UTILS) += xhci.c + +ramstage-y += gpio.c diff --git a/src/device/device_const.c b/src/device/device_const.c index 2dc583ca278..5288a743b6a 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -162,6 +162,9 @@ static int path_eq(const struct device_path *path1, case DEVICE_PATH_LPC: equal = (path1->lpc.addr == path2->lpc.addr); break; + case DEVICE_PATH_GPIO: + equal = (path1->gpio.id == path2->gpio.id); + break; default: printk(BIOS_ERR, "Unknown device type: %d\n", path1->type); break; diff --git a/src/device/device_util.c b/src/device/device_util.c index 452a87bf140..0bce26a99e5 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -130,6 +130,9 @@ u32 dev_path_encode(const struct device *dev) case DEVICE_PATH_USB: ret |= dev->path.usb.port_type << 8 | dev->path.usb.port_id; break; + case DEVICE_PATH_GPIO: + ret |= dev->path.gpio.id; + break; case DEVICE_PATH_NONE: case DEVICE_PATH_MMIO: /* don't care */ default: @@ -223,6 +226,9 @@ const char *dev_path(const struct device *dev) snprintf(buffer, sizeof(buffer), "LPC: %08lx", dev->path.lpc.addr); break; + case DEVICE_PATH_GPIO: + snprintf(buffer, sizeof(buffer), "GPIO: %d", dev->path.gpio.id); + break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); diff --git a/src/device/gpio.c b/src/device/gpio.c new file mode 100644 index 00000000000..5e714970243 --- /dev/null +++ b/src/device/gpio.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const struct gpio_operations *dev_get_gpio_ops(struct device *dev) +{ + if (!dev) { + printk(BIOS_ERR, "Could not get gpio operations, device is NULL."); + return NULL; + } else if (!dev->ops) { + printk(BIOS_ERR, "Could not get gpio operations, dev->ops is NULL."); + return NULL; + } else if (!dev->ops->ops_gpio) { + printk(BIOS_ERR, "Could not get gpio operations, ops_gpio is NULL."); + return NULL; + } + + return dev->ops->ops_gpio; +} diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 538660894f7..2f38ce582d2 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -64,7 +64,7 @@ static u8 *mem_ptr(u32 addr, int size) u8 *retaddr = 0; if (addr > M.mem_size - size) { - DB(printf("mem_ptr: address %#x out of range!\n", addr);) + DB(printf("%s: address %#x out of range!\n", __func__, addr);) HALT_SYS(); } if (addr < 0x200) { diff --git a/src/device/pci_device.c b/src/device/pci_device.c index a7eb91d42d1..5d38423cf30 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -967,7 +967,7 @@ static void set_pci_ops(struct device *dev) dev->ops = &default_cardbus_ops_bus; break; #endif -default: + default: bad: if (dev->enabled) { printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown " @@ -1263,7 +1263,7 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, post_code(0x25); /* - * Warn if any leftover static devices are are found. + * Warn if any leftover static devices are found. * There's probably a problem in devicetree.cb. */ diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 4224c651f36..94452433fce 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -207,7 +207,7 @@ pci_rom_acpi_fill_vfct(const struct device *device, acpi_vfct_t *vfct_struct, if (!rom) rom = pci_rom_probe(device); if (!rom) { - printk(BIOS_ERR, "pci_rom_acpi_fill_vfct failed\n"); + printk(BIOS_ERR, "%s failed\n", __func__); return current; } diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index afe6948a3a0..259d4497524 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -249,6 +249,8 @@ static void get_resources(struct device *dev, struct pnp_info *info) pnp_get_ioresource(dev, PNP_IDX_IO2, info->io2); if (info->flags & PNP_IO3) pnp_get_ioresource(dev, PNP_IDX_IO3, info->io3); + if (info->flags & PNP_IO4) + pnp_get_ioresource(dev, PNP_IDX_IO4, info->io4); if (info->flags & PNP_IRQ0) { resource = new_resource(dev, PNP_IDX_IRQ0); diff --git a/src/device/xhci.c b/src/device/xhci.c index d4caceffaa8..4523b56adcc 100644 --- a/src/device/xhci.c +++ b/src/device/xhci.c @@ -36,7 +36,7 @@ enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, } if (!(res->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "%s: BAR is is not assigned\n", __func__); + printk(BIOS_ERR, "%s: BAR is not assigned\n", __func__); return CB_ERR; } diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29b3c7..33940cb489d 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -10,16 +10,19 @@ ****************************************************************************** */ -#include "gcccar.inc" #include #include +.section .init + .code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end + .global bootblock_pre_c_entry _cache_as_ram_setup: +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 818355b5b9e..b394d3c4ce8 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -212,7 +212,7 @@ static int elog_is_buffer_clear(size_t offset) uint8_t *buffer = rdev_mmap(rdev, offset, size); int ret = 1; - elog_debug("elog_is_buffer_clear(offset=%zu size=%zu)\n", offset, size); + elog_debug("%s(offset=%zu size=%zu)\n", __func__, offset, size); if (buffer == NULL) return 0; @@ -235,7 +235,7 @@ static int elog_is_header_valid(void) { struct elog_header *header; - elog_debug("elog_is_header_valid()\n"); + elog_debug("%s()\n", __func__); header = rdev_mmap(mirror_dev_get(), 0, sizeof(*header)); @@ -348,7 +348,7 @@ static int elog_update_event_buffer_state(void) { size_t offset = elog_events_start(); - elog_debug("elog_update_event_buffer_state()\n"); + elog_debug("%s()\n", __func__); /* Go through each event and validate it */ while (1) { @@ -392,7 +392,7 @@ static int elog_update_event_buffer_state(void) static int elog_scan_flash(void) { - elog_debug("elog_scan_flash()\n"); + elog_debug("%s()\n", __func__); void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); @@ -558,7 +558,7 @@ static int elog_shrink_by_size(size_t requested_size) static int elog_prepare_empty(void) { - elog_debug("elog_prepare_empty()\n"); + elog_debug("%s()\n", __func__); return elog_shrink_by_size(elog_events_total_space()); } @@ -638,7 +638,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle) */ int elog_clear(void) { - elog_debug("elog_clear()\n"); + elog_debug("%s()\n", __func__); /* Make sure ELOG structures are initialized */ if (elog_init() < 0) @@ -786,7 +786,7 @@ int elog_init(void) } elog_state.elog_initialized = ELOG_BROKEN; - elog_debug("elog_init()\n"); + elog_debug("%s()\n", __func__); /* Set up the backing store */ if (elog_find_flash() < 0) @@ -860,7 +860,7 @@ int elog_add_event_raw(u8 event_type, void *data, u8 data_size) struct event_header *event; u8 event_size; - elog_debug("elog_add_event_raw(type=%X)\n", event_type); + elog_debug("%s(type=%X)\n", __func__, event_type); /* Make sure ELOG structures are initialized */ if (elog_init() < 0) diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index cdac9fe35a2..24386642ebf 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -44,6 +44,19 @@ static void bh720_init(struct device *dev) } board_bh720(dev); + + if (config && config->vih_tuning_value) { + /* Tune VIH */ + u32 bh720_pcr_data; + pci_write_config32(dev, BH720_PROTECT, + BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); + bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL); + bh720_pcr_data &= 0xFFFFFF00; + bh720_pcr_data |= config->vih_tuning_value; + pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data); + pci_write_config32(dev, BH720_PROTECT, + BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); + } } static struct device_operations bh720_ops = { diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h index dacad7cb846..f898378cb44 100644 --- a/src/drivers/generic/bayhub/chip.h +++ b/src/drivers/generic/bayhub/chip.h @@ -8,4 +8,7 @@ struct drivers_generic_bayhub_config { /* 1 to enable power-saving mode, 0 to disable */ int power_saving; + + /* CLK and DAT tuning values */ + uint8_t vih_tuning_value; }; diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c index 48e520bde23..cd581b93807 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.c +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -12,6 +12,8 @@ static void gl9763e_init(struct device *dev) { + uint32_t ver; + printk(BIOS_INFO, "GL9763E: init\n"); pci_dev_init(dev); @@ -25,6 +27,16 @@ static void gl9763e_init(struct device *dev) pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM); /* Enable SSC */ pci_or_config32(dev, PLL_CTL, PLL_CTL_SSC); + /* Check chip version */ + ver = pci_read_config32(dev, HW_VER_2); + if ((ver & HW_VER_MASK) == REVISION_03) { + /* Set clock source for RX path */ + pci_update_config32(dev, SD_CLKRX_DLY, ~CLK_SRC_MASK, AFTER_OUTPUT_BUFF); + } + /* Modify DS delay */ + pci_update_config32(dev, SD_CLKRX_DLY, ~HS400_RX_DELAY_MASK, HS400_RX_DELAY); + /* Disable Slow mode */ + pci_and_config32(dev, EMMC_CTL, ~SLOW_MODE); /* Set VHS to read-only */ pci_update_config32(dev, VHS, ~VHS_REV_MASK, VHS_REV_R); } diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h index fd9c6ba5c28..7f5dbf9c052 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.h +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -18,6 +18,19 @@ #define PLL_CTL 0x938 #define PLL_CTL_SSC BIT(19) +#define EMMC_CTL 0x960 +#define SLOW_MODE BIT(3) + #define PLL_CTL_2 0x93C #define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16) #define MAX_SSC_30000PPM (0xF5C3 << 16) + +#define HW_VER_2 0x8F8 +#define HW_VER_MASK 0xFFFF +#define REVISION_03 0x0011 + +#define SD_CLKRX_DLY 0x934 +#define CLK_SRC_MASK (0x3 << 24) +#define AFTER_OUTPUT_BUFF (0x0 << 24) +#define HS400_RX_DELAY_MASK (0xF << 28) +#define HS400_RX_DELAY (0x5 << 28) diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h index 7d00261787e..2e225729494 100644 --- a/src/drivers/i2c/sx9324/registers.h +++ b/src/drivers/i2c/sx9324/registers.h @@ -47,6 +47,7 @@ REGISTER(reg_gnrl_ctrl1); REGISTER(reg_irq_msk); REGISTER(reg_irq_cfg0); +REGISTER(reg_irq_cfg1); REGISTER(reg_irq_cfg2); REGISTER(reg_prox_ctrl0); diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8c0f8b69ee7..8e12d1f044c 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -49,7 +49,8 @@ __weak int tis_plat_irq_status(void) static int warning_displayed; if (!warning_displayed) { - printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!\n"); + printk(BIOS_WARNING, "WARNING: %s() not implemented, wasting 20ms to wait on" + " Cr50!\n", __func__); warning_displayed = 1; } mdelay(CR50_TIMEOUT_NOIRQ_MS); diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 217d8c6ed56..80de2df994e 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -24,7 +24,7 @@ int tis_open(void) int rc; if (chip.is_open) { - printk(BIOS_DEBUG, "tis_open() called twice.\n"); + printk(BIOS_DEBUG, "%s() called twice.\n", __func__); return -1; } @@ -68,11 +68,11 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, return -1; if (count == 0) { - printk(BIOS_DEBUG, "tpm_transmit: no data\n"); + printk(BIOS_DEBUG, "%s: no data\n", __func__); return -1; } if (count > sbufsiz) { - printk(BIOS_DEBUG, "tpm_transmit: invalid count value %x %zx\n", + printk(BIOS_DEBUG, "%s: invalid count value %x %zx\n", __func__, count, sbufsiz); return -1; } @@ -80,7 +80,7 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, ASSERT(chip.vendor.send); rc = chip.vendor.send(&chip, (uint8_t *) sbuf, count); if (rc < 0) { - printk(BIOS_DEBUG, "tpm_transmit: tpm_send error\n"); + printk(BIOS_DEBUG, "%s: tpm_send error\n", __func__); goto out; } @@ -95,7 +95,7 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, if (status == chip.vendor.req_canceled) { printk(BIOS_DEBUG, - "tpm_transmit: Operation Canceled\n"); + "%s: Operation Canceled\n", __func__); rc = -1; goto out; } @@ -105,7 +105,7 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, ASSERT(chip.vendor.cancel); chip.vendor.cancel(&chip); - printk(BIOS_DEBUG, "tpm_transmit: Operation Timed out\n"); + printk(BIOS_DEBUG, "%s: Operation Timed out\n", __func__); rc = -1; //ETIME; goto out; @@ -113,7 +113,7 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf, rc = chip.vendor.recv(&chip, (uint8_t *) rbuf, rbufsiz); if (rc < 0) - printk(BIOS_DEBUG, "tpm_transmit: tpm_recv: error %d\n", rc); + printk(BIOS_DEBUG, "%s: tpm_recv: error %d\n", __func__, rc); out: return rc; } diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 43217577056..ee23ea7c440 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -365,7 +365,7 @@ static int tpm_tis_i2c_recv(struct tpm_chip *chip, uint8_t *buf, size_t count) /* read first 10 bytes, including tag, paramsize, and result */ size = recv_data(chip, buf, TPM_HEADER_SIZE); if (size < TPM_HEADER_SIZE) { - printk(BIOS_DEBUG, "tpm_tis_i2c_recv: Unable to read header\n"); + printk(BIOS_DEBUG, "%s: Unable to read header\n", __func__); goto out; } @@ -379,15 +379,14 @@ static int tpm_tis_i2c_recv(struct tpm_chip *chip, uint8_t *buf, size_t count) size += recv_data(chip, &buf[TPM_HEADER_SIZE], expected - TPM_HEADER_SIZE); if (size < expected) { - printk(BIOS_DEBUG, "tpm_tis_i2c_recv: Unable to " - "read remainder of result\n"); + printk(BIOS_DEBUG, "%s: Unable to read remainder of result\n", __func__); size = -1; goto out; } wait_for_stat(chip, TPM_STS_VALID, &status); if (status & TPM_STS_DATA_AVAIL) { /* retry? */ - printk(BIOS_DEBUG, "tpm_tis_i2c_recv: Error left over data\n"); + printk(BIOS_DEBUG, "%s: Error left over data\n", __func__); size = -1; goto out; } diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index f1cfff771cc..e20d5277ed2 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -14,6 +14,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: /* diff --git a/src/drivers/intel/fsp1_1/temp_ram_exit.c b/src/drivers/intel/fsp1_1/temp_ram_exit.c index 08324eb8cf3..df7e67459bc 100644 --- a/src/drivers/intel/fsp1_1/temp_ram_exit.c +++ b/src/drivers/intel/fsp1_1/temp_ram_exit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include @@ -10,6 +11,10 @@ asmlinkage void chipset_teardown_car_main(void) FSP_TEMP_RAM_EXIT temp_ram_exit; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + /* CBMEM_ID_VBOOT_WORKBUF is used as vboot workbuffer. + * Init CBMEM before loading fsp, to have buffer available */ + cbmem_initialize(); + if (prog_locate(&fsp)) { die("Unable to locate fsp.bin\n"); } else { diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 96ae282522b..056c35cb790 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,6 +117,15 @@ config FSP_CAR help Use FSP APIs to initialize & Tear Down the Cache-As-Ram +config FSP_T_RESERVED_SIZE + hex + default 0x100 if FSP_CAR + default 0x0 + help + This is the size of the area reserved by FSP-T. This is not + defined in the FSP specification but in the SOC integration + guides. + config FSP_M_XIP bool default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 298198d0632..25e284679bf 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -73,7 +73,7 @@ $(FSP_S_CBFS)-compression := LZ4 endif ifeq ($(CONFIG_FSP_FULL_FD),y) -$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) +$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index b45b4d8a7c0..a134fed0653 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -18,7 +18,7 @@ void fsp_print_header_info(const struct fsp_header *hdr) revision.rev.bld_num); printk(BIOS_SPEW, "Type: %s/%s\n", (hdr->component_attribute & 1) ? "release" : "debug", - (hdr->component_attribute & 2) ? "test" : "official"); + (hdr->component_attribute & 2) ? "official" : "test"); printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", hdr->image_id, hdr->image_base, hdr->image_size); printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index bddd07f33c3..759bfa40f4d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -36,7 +36,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (!mrc_data) { - printk(BIOS_ERR, "Couldn't find memory training data HOB.\n"); + printk(BIOS_ERR, "ERROR: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); return; } @@ -48,7 +48,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) */ if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, mrc_data_size) < 0) - printk(BIOS_ERR, "Failed to stash MRC data\n"); + printk(BIOS_ERR, "ERROR: Failed to stash MRC data\n"); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -64,8 +64,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (CONFIG(HAVE_ACPI_RESUME)) { - printk(BIOS_ERR, - "Failed to recover CBMEM in S3 resume.\n"); + printk(BIOS_ERR, "ERROR: Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ full_reset(); diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 3f75ab93508..b001fd3e4d1 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -87,7 +87,7 @@ config GFX_GMA || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ - || SOC_INTEL_WHISKEYLAKE + || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_COMETLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE @@ -114,11 +114,21 @@ config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ - SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE || \ + SOC_INTEL_COMETLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X +config GFX_GMA_PCH + string + default "Ibex_Peak" if NORTHBRIDGE_INTEL_IRONLAKE + default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE + default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE + default "No_PCH" + config GFX_GMA_PANEL_1_PORT string default "eDP" if GFX_GMA_PANEL_1_ON_EDP diff --git a/src/soc/intel/common/block/acpi/acpi/gfx.asl b/src/drivers/intel/gma/acpi/gfx.asl similarity index 100% rename from src/soc/intel/common/block/acpi/acpi/gfx.asl rename to src/drivers/intel/gma/acpi/gfx.asl diff --git a/src/drivers/intel/gma/acpi/gma.asl b/src/drivers/intel/gma/acpi/gma.asl index c4ee2db8266..2282110fb94 100644 --- a/src/drivers/intel/gma/acpi/gma.asl +++ b/src/drivers/intel/gma/acpi/gma.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) - OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) Field (GFXC, DWordAcc, NoLock, Preserve) { @@ -20,6 +18,9 @@ Device (GFX0) { Offset (CONFIG_INTEL_GMA_BCLV_OFFSET), BCLV, CONFIG_INTEL_GMA_BCLV_WIDTH, + } + Field (GFRG, DWordAcc, NoLock, Preserve) + { Offset (CONFIG_INTEL_GMA_BCLM_OFFSET), BCLM, CONFIG_INTEL_GMA_BCLM_WIDTH } diff --git a/src/drivers/intel/gma/gma.h b/src/drivers/intel/gma/gma.h index d7a336c537f..a39198c006f 100644 --- a/src/drivers/intel/gma/gma.h +++ b/src/drivers/intel/gma/gma.h @@ -11,11 +11,31 @@ struct i915_gpu_controller_info { u32 did[5]; }; +/* Devicetree panel configuration */ +struct i915_gpu_panel_config { + unsigned int up_delay_ms; + unsigned int down_delay_ms; + unsigned int cycle_delay_ms; + unsigned int backlight_on_delay_ms; + unsigned int backlight_off_delay_ms; + unsigned int backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } backlight_polarity; +}; + #define GMA_STATIC_DISPLAYS(ssc) { \ .use_spread_spectrum_clock = (ssc), \ .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ } +/* Shortcut for one internal panel at port A */ +#define GMA_DEFAULT_PANEL(ssc) { \ + .use_spread_spectrum_clock = (ssc), \ + .ndid = 1, .did = { 0x0400 } \ +} + void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); #endif diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 137d7673fbf..f65c53290d1 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -549,7 +549,6 @@ #define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 -#define ESR 0x020b8 #define GM45_ERROR_PAGE_TABLE (1<<5) #define GM45_ERROR_MEM_PRIV (1<<4) #define I915_ERROR_PAGE_TABLE (1<<4) diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 558dae6abac..37e38aa338b 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -206,8 +206,8 @@ struct old_child_dev_config { } __packed; /* This one contains field offsets that are known to be common for all BDB - * versions. Notice that the meaning of the contents contents may still change, - * but at least the offsets are consistent. */ + * versions. Notice that the meaning of the contents may still change, but + * at least the offsets are consistent. */ struct common_child_dev_config { u16 handle; u16 device_type; diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 4e9f94d013b..e1ed6c82853 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -155,7 +155,7 @@ static enum cb_err locate_vbt_vbios(const u8 *vbios, struct region_device *rdev) return CB_ERR; } - printk(BIOS_DEBUG, "GMA: locate_vbt_vbios: %x %x %x %x %x\n", + printk(BIOS_DEBUG, "GMA: %s: %x %x %x %x %x\n", __func__, oprom->signature, pcir->vendor, pcir->classcode[0], pcir->classcode[1], pcir->classcode[2]); diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 7a693ff5315..f884ac6004d 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -8,6 +8,7 @@ #include #include #include "chip.h" +#include "retimer.h" /* Unique ID for the retimer _DSM. */ #define INTEL_USB4_RETIMER_DSM_UUID "61788900-C470-42BB-80F0-23A313864593" @@ -19,6 +20,8 @@ * 0: Query command implemented * 1: Query force power enable state * 2: Set force power state + * 3: Get Retimer FW Update EC Ram value + * 4: Set Retimer FW Update EC Ram value * Arg3: A package containing parameters for the function specified * by the UUID, revision ID and function index. */ @@ -28,15 +31,15 @@ static void usb4_retimer_cb_standard_query(void *arg) /* * ToInteger (Arg1, Local2) * If (Local2 == 1) { - * Return(Buffer() {0x07}) + * Return(Buffer() {0x1f}) * } * Return (Buffer() {0x01}) */ acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); - /* Revision 1 supports 2 Functions beyond the standard query */ + /* Revision 1 supports 4 Functions beyond the standard query */ acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); - acpigen_write_return_singleton_buffer(0x07); + acpigen_write_return_singleton_buffer(0x1f); acpigen_pop_len(); /* If */ /* Other revisions support no additional functions */ @@ -48,7 +51,7 @@ static void usb4_retimer_cb_get_power_state(void *arg) struct acpi_gpio *power_gpio = arg; /* - * // Read power gpio into Local0 + * Read power gpio into Local0 * Store (\_SB.PCI0.GTXS (power_gpio), Local0) * Return (Local0) */ @@ -61,7 +64,7 @@ static void usb4_retimer_cb_set_power_state(void *arg) struct acpi_gpio *power_gpio = arg; /* - * // Get argument for on/off from Arg3[0] + * Get information to set to retimer info from Arg3[0] * Local0 = DeRefOf (Arg3[0]) */ acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); @@ -90,10 +93,32 @@ static void usb4_retimer_cb_set_power_state(void *arg) acpigen_write_return_integer(0); } -static void (*usb4_retimer_callbacks[3])(void *) = { +static void usb4_retimer_cb_get_retimer_info(void *arg) +{ + const char *RFWU = ec_retimer_fw_update_path(); + + /* + * Read Mux Retimer info from EC RAM + * Return RFWU if RFWU is not NULL. Otherwise return -1 to + * inform kernel about error. + */ + if (!RFWU) + acpigen_write_return_byte(-1); + else + acpigen_write_return_namestr(RFWU); +} + +static void usb4_retimer_cb_set_retimer_info(void *arg) +{ + ec_retimer_fw_update(arg); +} + +static void (*usb4_retimer_callbacks[5])(void *) = { usb4_retimer_cb_standard_query, /* Function 0 */ usb4_retimer_cb_get_power_state, /* Function 1 */ usb4_retimer_cb_set_power_state, /* Function 2 */ + usb4_retimer_cb_get_retimer_info, /* Function 3 */ + usb4_retimer_cb_set_retimer_info, /* Function 4 */ }; static void usb4_retimer_fill_ssdt(const struct device *dev) @@ -134,3 +159,12 @@ struct chip_operations drivers_intel_usb4_retimer_ops = { CHIP_NAME("Intel USB4 Retimer") .enable_dev = usb4_retimer_enable }; + +__weak const char *ec_retimer_fw_update_path(void) +{ + return NULL; +} + +__weak void ec_retimer_fw_update(void *arg) +{ +} diff --git a/src/drivers/intel/usb4/retimer/retimer.h b/src/drivers/intel/usb4/retimer/retimer.h new file mode 100644 index 00000000000..4c4044a2fe3 --- /dev/null +++ b/src/drivers/intel/usb4/retimer/retimer.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _DRIVERS_INTEL_USB4_RETIMER_H_ +#define _DRIVERS_INTEL_USB4_RETIMER_H_ + +const char *ec_retimer_fw_update_path(void); +void ec_retimer_fw_update(void *arg); + +#endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */ diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 1137dcf8d54..012f67887c6 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -42,3 +42,14 @@ config IPMI_KCS_TIMEOUT_MS The time unit is millisecond for each IPMI KCS transfer. IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater is recommended. + +config DRIVERS_IPMI_SUPERMICRO_OEM + bool "Supermicro IPMI OEM BMC support" + depends on IPMI_KCS + default n + help + Tested on X11SSH only. Different BMCs might not support these OEM + commands. + The following features are implemented: + * Communicates the BIOS version to the BMC + * Communicates the BIOS date to the BMC diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 06a3433ae0f..e4bcf313ebc 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -2,6 +2,7 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_fru.c +ramstage-$(CONFIG_DRIVERS_IPMI_SUPERMICRO_OEM) += supermicro_oem.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs_ops_premem.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index f561bcd893c..fb5d4d921f2 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #ifndef _IMPI_CHIP_H_ #define _IPMI_CHIP_H_ +#include + struct drivers_ipmi_config { u8 bmc_i2c_address; u8 have_nv_storage; @@ -11,6 +15,16 @@ struct drivers_ipmi_config { u8 gpe_interrupt; u8 have_apic; u32 apic_interrupt; + /* Device to use for GPIO operations */ + DEVTREE_CONST struct device *gpio_dev; + /* + * Jumper GPIO for enabling / disabling BMC/IPMI + * If present, the jumper overrides the devicetree. + */ + u32 bmc_jumper_gpio; + /* "POST complete" GPIO and polarity */ + u32 post_complete_gpio; + bool post_complete_invert; /* * Wait for BMC to boot. * This can be used if the BMC takes a long time to boot after PoR: diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 640bfa1c176..9d1cac87159 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -9,8 +9,10 @@ */ #include +#include #include #include +#include #include #if CONFIG(HAVE_ACPI_TABLES) #include @@ -23,6 +25,7 @@ #include #include #include "ipmi_kcs.h" +#include "ipmi_supermicro_oem.h" #include "chip.h" /* 4 bit encoding */ @@ -32,6 +35,8 @@ static u8 ipmi_revision_minor = 0x0; static u8 bmc_revision_major = 0x0; static u8 bmc_revision_minor = 0x0; +static struct boot_state_callback bscb_post_complete; + static int ipmi_get_device_id(struct device *dev, struct ipmi_devid_rsp *rsp) { int ret; @@ -72,22 +77,62 @@ static int ipmi_get_bmc_self_test_result(struct device *dev, struct ipmi_selftes return 0; } +static void bmc_set_post_complete_gpio_callback(void *arg) +{ + struct drivers_ipmi_config *conf = arg; + const struct gpio_operations *gpio_ops; + + if (!conf || !conf->post_complete_gpio) + return; + + gpio_ops = dev_get_gpio_ops(conf->gpio_dev); + if (!gpio_ops) { + printk(BIOS_WARNING, "IPMI: specified gpio device is missing gpio ops!\n"); + return; + } + + /* Set POST Complete pin. The `invert` field controls the polarity. */ + gpio_ops->output(conf->post_complete_gpio, conf->post_complete_invert ^ 1); + + printk(BIOS_DEBUG, "BMC: POST complete gpio set\n"); +} + static void ipmi_kcs_init(struct device *dev) { struct ipmi_devid_rsp rsp; uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = dev->chip_info; + const struct gpio_operations *gpio_ops; struct ipmi_selftest_rsp selftestrsp = {0}; uint8_t retry_count; + if (!conf) { + printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n"); + return; + } + + if (conf->bmc_jumper_gpio) { + gpio_ops = dev_get_gpio_ops(conf->gpio_dev); + if (!gpio_ops) { + printk(BIOS_WARNING, "IPMI: gpio device is missing gpio ops!\n"); + } else { + /* Get jumper value and set device state accordingly */ + dev->enabled = gpio_ops->get(conf->bmc_jumper_gpio); + if (!dev->enabled) + printk(BIOS_INFO, "IPMI: Disabled by jumper\n"); + } + } + if (!dev->enabled) return; printk(BIOS_DEBUG, "IPMI: PNP KCS 0x%x\n", dev->path.pnp.port); - if (!conf) { - printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n"); - return; + /* Set up boot state callback for POST_COMPLETE# */ + if (conf->post_complete_gpio) { + bscb_post_complete.callback = bmc_set_post_complete_gpio_callback; + bscb_post_complete.arg = conf; + boot_state_sched_on_entry(&bscb_post_complete, BS_PAYLOAD_BOOT); } /* Get IPMI version for ACPI and SMBIOS */ @@ -167,6 +212,12 @@ static void ipmi_kcs_init(struct device *dev) /* Don't write tables if communication failed */ dev->enabled = 0; } + + if (!dev->enabled) + return; + + if (CONFIG(DRIVERS_IPMI_SUPERMICRO_OEM)) + supermicro_ipmi_oem(dev->path.pnp.port); } #if CONFIG(HAVE_ACPI_TABLES) diff --git a/src/drivers/ipmi/ipmi_supermicro_oem.h b/src/drivers/ipmi/ipmi_supermicro_oem.h new file mode 100644 index 00000000000..5babadb13f7 --- /dev/null +++ b/src/drivers/ipmi/ipmi_supermicro_oem.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IPMI_SUPERMICRO_OEM_H +#define __IPMI_SUPERMICRO_OEM_H + +#include + +void supermicro_ipmi_oem(const uint16_t kcs_port); + +#endif /* __IPMI_SUPERMICRO_OEM_H */ diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c new file mode 100644 index 00000000000..87b7fe243a7 --- /dev/null +++ b/src/drivers/ipmi/supermicro_oem.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include +#include +#include +#include +#include "ipmi_supermicro_oem.h" + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_LUN0_AC_SET_BIOS_VER 0x100 +#define IPMI_LUN0_AC_SET_BIOS_DATE 0x101 +#define IPMI_LUN0_SET_BIOS_STRING 0xac + +struct ipmi_oem_set_bios_str { + uint16_t ver; + char str[16]; // NULL terminated string +} __packed; + +static void set_coreboot_ver(const uint16_t kcs_port) +{ + const char *coreboot_ver = COREBOOT_VERSION; + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + size_t i; + + /* Only 8 charactars are visible in UI. Cut of on first dash */ + for (i = 0; i < 15; i++) { + if (coreboot_ver[i] == '-') + break; + bios_ver.str[i] = coreboot_ver[i]; + } + bios_ver.str[i] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_VER; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +static void set_coreboot_date(const uint16_t kcs_port) +{ + struct ipmi_oem_set_bios_str bios_ver; + struct ipmi_rsp rsp; + int ret; + + strncpy(bios_ver.str, COREBOOT_DMI_DATE, 15); + bios_ver.str[15] = 0; + bios_ver.ver = IPMI_LUN0_AC_SET_BIOS_DATE; + + ret = ipmi_kcs_message(kcs_port, IPMI_NETFN_OEM, 0, IPMI_LUN0_SET_BIOS_STRING, + (const unsigned char *) &bios_ver, sizeof(bios_ver), + (unsigned char *) &rsp, sizeof(rsp)); + if (ret < sizeof(rsp) || rsp.completion_code) { + printk(BIOS_ERR, "BMC_IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + } +} + +void supermicro_ipmi_oem(const uint16_t kcs_port) +{ + set_coreboot_ver(kcs_port); + set_coreboot_date(kcs_port); +} diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index f7728142182..0769a74d535 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -48,7 +48,7 @@ enum max77686_regnum { * @param vol_bitpos bit position to be set or clear within register * @param vol_bitmask bit mask value * @param reg_enaddr control register address, which enable the given - * given buck/ldo. + * buck/ldo. * @param reg_enbitpos bit position to be enabled * @param reg_enbiton value to be written to buck/ldo to make it ON * @param reg_enbitoff value to be written to buck/ldo to make it OFF diff --git a/src/drivers/ocp/dmi/Kconfig b/src/drivers/ocp/dmi/Kconfig index b30a40d4735..eaf5ad0c5d7 100644 --- a/src/drivers/ocp/dmi/Kconfig +++ b/src/drivers/ocp/dmi/Kconfig @@ -10,3 +10,4 @@ config OCP_DMI config FRU_DEVICE_ID int default 0 + depends on OCP_DMI diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index b90338c6190..6ea447ffe6e 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -143,7 +143,7 @@ static uint32_t smmstorev2_exec(uint8_t command, void *param) uint32_t smmstore_exec(uint8_t command, void *param) { - if (!param) + if (command != SMMSTORE_CMD_CLEAR && !param) return SMMSTORE_RET_FAILURE; if (CONFIG(SMMSTORE_V2)) diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 2554cf717ce..6465b40a0a7 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -31,7 +31,7 @@ static const char *tis_get_dev_name(struct tpm2_info *info) int tis_open(void) { if (tpm_is_open) { - printk(BIOS_ERR, "tis_open() called twice.\n"); + printk(BIOS_ERR, "%s() called twice.\n", __func__); return -1; } return 0; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index d65decda12e..1ad1eaac486 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -74,7 +74,8 @@ __weak int tis_plat_irq_status(void) static int warning_displayed; if (!warning_displayed) { - printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 10ms to wait on Cr50!\n"); + printk(BIOS_WARNING, "WARNING: %s() not implemented, wasting 10ms to wait on" + " Cr50!\n", __func__); warning_displayed = 1; } mdelay(10); diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 44a80884aa1..ca41cdbd761 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -10,8 +10,8 @@ #include #include "sn65dsi86bridge.h" -#define BRIDGE_GETHIGHERBYTE(x) (uint8_t)((x & 0xff00) >> 8) -#define BRIDGE_GETLOWERBYTE(x) (uint8_t)((x & 0x00ff)) +#define BRIDGE_GETHIGHERBYTE(x) ((uint8_t)((x & 0xff00) >> 8)) +#define BRIDGE_GETLOWERBYTE(x) ((uint8_t)(x & 0x00ff)) /* fudge factor required to account for 8b/10b encoding */ #define DP_CLK_FUDGE_NUM 10 diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 8508210fc63..baf760b4b04 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -5,3 +5,14 @@ config TPM_INIT help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. + +config TPM_PPI + bool "Generate ACPI code to implement TPM physical presence interface" + depends on TPM1 || TPM2 + depends on HAVE_ACPI_TABLES + depends on !CHROMEOS + default y if PAYLOAD_TIANOCORE + help + This driver automatically generates ACPI tables for the Physical + Presence Interface defined by the TCG. If not activated only a stub + will be generated without any functionality. diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 5fc46329121..af6e5a21c1c 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1,3 +1,7 @@ ramstage-$(CONFIG_TPM_INIT) += tpm.c +ifeq ($(CONFIG_TPM_PPI),y) +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi.c +else ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c +endif diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c new file mode 100644 index 00000000000..88dd6499544 --- /dev/null +++ b/src/drivers/tpm/ppi.c @@ -0,0 +1,726 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tpm_ppi.h" + +#define BCD(x, y) (((x) << 4) | ((y) << 0)) + +static void set_package_element_op(const char *package_name, unsigned int element, + uint8_t src_op) +{ + acpigen_write_store(); + acpigen_emit_byte(src_op); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +static void set_package_element_name(const char *package_name, unsigned int element, + const char *src) +{ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +/* PPI function is passed in src_op. Converted to Local2. Clobbers Local1 and Local2 */ +static void verify_supported_ppi(uint8_t src_op) +{ + /* + * Old OSes incorrectly pass a Buffer instead of a Package. + * See TCG Physical Presence Interface Specification Chapter 8.1.2 for details. + */ + + /* If (ObjectType(Arg3) == Package) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 4); + acpigen_get_package_op_element(src_op, 0, LOCAL2_OP); + acpigen_pop_len(); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + acpigen_write_to_integer(src_op, LOCAL2_OP); + acpigen_pop_len(); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + + /* + * Note: Must fake success for 1-4, 6-13, 15-16, 19-20 + * see "Trusted Execution Environment ACPI Profile" + * + * Even if not available, the TPM 1.2 PPI must be advertised as + * supported. Tests showed that Windows relies on it, even when + * a TPM2.0 is present! + * The functions aren't actually used when a TPM2.0 is present... + * Without this the Windows TPM 2.0 stack refuses to work. + */ + + /* + * Check if we have TPM1.2 but a TPM2 PPI function was called + * or if we have TPM2.0 but a TPM1.2 PPI function was called. + */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ZERO_OP : ONE_OP); + acpigen_emit_byte(LOCAL1_OP); + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + acpigen_write_return_integer(PPI2_RET_SUCCESS); /* As per TPM spec */ + acpigen_pop_len(); + acpigen_write_return_integer(PPI2_RET_NOT_SUPPORTED); + + acpigen_pop_len(); +} + +/* TPM PPI functions */ + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, 2); +} + + /* + * PPI 1.0: 2.1.1 Get Physical Presence Interface Version + * + * Arg2 (Integer): Function Index = 1 + * Arg3 (Package): Arguments = Empty Package + * + * Returns: Type: String + */ +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 1.3 */ + acpigen_write_return_string("1.3"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +/* + * Submit TPM Operation Request to Pre-OS Environment [Windows optional] + * PPI 1.0: 2.1.3 Submit TPM Operation Request to Pre-OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 2 + * Arg3 (Package): Arguments = Package: Type: Integer + * Operation Value of the Request + * + * Returns: Type: Integer + * 0: Success + * 1: Operation Value of the Request Not Supported + * 2: General Failure + */ +static void tpm_ppi_func2_cb(void *arg) +{ + /* Revision 1 */ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^USER"); + + acpigen_write_return_integer(PPI2_RET_SUCCESS); + acpigen_pop_len(); + + acpigen_write_return_integer(PPI2_RET_GENERAL_FAILURE); +} + +/* + * PPI 1.0: 2.1.4 Get Pending TPM Operation Requested By the OS + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 3 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer (optional)) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Pending TPM operation requested by OS + * Integer 3: + * Pending TPM operation argument requested by OS + */ +static void tpm_ppi_func3_cb(void *arg) +{ + acpigen_write_store(); + acpigen_write_integer(PPI3_RET_GENERAL_FAILURE); + acpigen_emit_byte(LOCAL0_OP); + + /* ^TPM3 [0] = PPI3_RET_GENERAL_FAILURE */ + set_package_element_op("^TPM3", 0, LOCAL0_OP); + + /* ^TPM2 [0] = PPI3_RET_GENERAL_FAILURE */ + set_package_element_op("^TPM2", 0, LOCAL0_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM2 [0] = PPI3_RET_SUCCESS */ + acpigen_write_store(); + acpigen_write_integer(PPI3_RET_SUCCESS); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM2", 0, LOCAL1_OP); + + /* ^TPM2 [1] = ^CMDR */ + set_package_element_name("^TPM2", 1, "^CMDR"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM2"); + acpigen_pop_len(); + + /* + * A return value of {0, 23, 1} indicates that operation 23 + * with argument 1 is pending. + */ + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + + /* ^TPM3 [0] = PPI3_RET_SUCCESS */ + acpigen_write_store(); + acpigen_write_integer(PPI3_RET_SUCCESS); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM3", 0, LOCAL1_OP); + + /* ^TPM3 [1] = ^CMDR */ + set_package_element_name("^TPM3", 1, "^CMDR"); + + /* ^TPM3 [2] = ^OARG */ + set_package_element_name("^TPM3", 2, "^OARG"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.0: 2.1.5 Get Platform-Specific Action to Transition to Pre-OS Environment + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 4 + * Arg3 (Package): Empty package + * + * Returns: Type: Integer + * 0: None + * 1: Shutdown + * 2: Reboot + * 3: Vendor specific + */ +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(PPI4_RET_REBOOT); +} + +/* + * PPI 1.0: 2.1.6 Return TPM Operation Response to OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Most recent TPM operation requested by OS + * Integer 3: + * Response to most recent TPM operation requested by OS + */ +static void tpm_ppi_func5_cb(void *arg) +{ + /* ^TPM3 [0] = PPI5_RET_GENERAL_FAILURE */ + acpigen_write_store(); + acpigen_write_integer(PPI5_RET_GENERAL_FAILURE); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM3", 0, LOCAL1_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM3 [0] = PPI5_RET_SUCCESS */ + acpigen_write_store(); + acpigen_write_integer(PPI5_RET_SUCCESS); + acpigen_emit_byte(LOCAL1_OP); + set_package_element_op("^TPM3", 0, LOCAL1_OP); + + /* ^TPM3 [1] = ^LCMD */ + set_package_element_name("^TPM3", 1, "^LCMD"); + + /* ^TPM3 [2] = ^RESU */ + set_package_element_name("^TPM3", 2, "^RESU"); + + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.2: 2.1.6 Submit preferred user language [Windows optional] + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + */ +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 aka + * "not implemented". + */ + acpigen_write_return_byte(PPI6_RET_NOT_IMPLEMENTED); +} + +/* + * PPI 1.2: 2.1.7 Submit TPM Operation Request to Pre-OS Environment 2 + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Success + * 1: Not implemented + * 2: General Failure + * 3: Blocked by current BIOS settings + */ +static void tpm_ppi_func7_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(ARG3_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + + /* Enforce use of Revision 1 that doesn't take an optional argument. */ + + /* Local0 = One */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Zero */ + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + + acpigen_write_return_byte(PPI7_RET_SUCCESS); + acpigen_pop_len(); + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Arg3 [1] */ + acpigen_get_package_op_element(ARG3_OP, 1, LOCAL3_OP); + acpigen_write_store(); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_namestring("^OARG"); + + acpigen_write_return_byte(PPI7_RET_SUCCESS); + acpigen_pop_len(); + + acpigen_write_return_byte(PPI7_RET_GENERAL_FAILURE); +} + +/* + * PPI 1.2: 2.1.8 Get User Confirmation Status for Operation + * + * Returns if a command is supported and allowed by firmware + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Not implemented + * 1: BIOS only + * 2: Blocked for OS by BIOS settings + * 3: Allowed and physical present user required + * 4: Allowed and physical present user not required + */ +static void tpm_ppi_func8_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL2_OP); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + acpigen_write_return_byte(0); /* Not implemented */ + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + if (CONFIG(TPM1)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm1_funcs[] = { + TPM_NOOP, + TPM_SET_NOPPICLEAR_TRUE, + TPM_SET_NOPPIMAINTAINANCE_TRUE, + TPM_SET_NOPPIPROVISION_TRUE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm1_funcs[i]); + acpigen_write_return_integer(PPI8_RET_ALLOWED); + acpigen_pop_len(); /* Pop : If */ + } + } else if (CONFIG(TPM2)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm2_funcs[i]); + acpigen_write_return_integer(PPI8_RET_ALLOWED); + acpigen_pop_len(); /* Pop : If */ + } + } + acpigen_write_return_integer(PPI8_RET_ALLOWED_WITH_PP); + + acpigen_pop_len(); + + acpigen_write_return_integer(PPI8_RET_NOT_IMPLEMENTED); +} + +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + struct cb_tpm_ppi_payload_handshake *ppib; + + static const struct fieldlist list[] = { + FIELDLIST_OFFSET(0x100),// FIXME: Add support for func + FIELDLIST_NAMESTR("PPIN", 8),// Not used + FIELDLIST_NAMESTR("PPIP", 32),// Not used + FIELDLIST_NAMESTR("RESU", 32),// Result of the last operation (TPM error code) + FIELDLIST_NAMESTR("CMDR", 32),// The command requested by OS. 0 for NOP + FIELDLIST_NAMESTR("OARG", 32),// The command optional argument requested by OS + FIELDLIST_NAMESTR("LCMD", 32),// The last command requested by OS. + FIELDLIST_NAMESTR("FRET", 32),// Not used + }; + static const u8 tpm1_funcs[] = { + TPM_NOOP, + TPM_ENABLE, + TPM_DISABLE, + TPM_ACTIVATE, + TPM_DEACTIVATE, + TPM_CLEAR, + TPM_ENABLE_ACTIVATE, + TPM_DEACTIVATE_DISABLE, + TPM_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE, + TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE, + TPM_CLEAR_ENABLE_ACTIVATE, + TPM_SET_NOPPIPROVISION_FALSE, + TPM_SET_NOPPIPROVISION_TRUE, + TPM_ENABLE_ACTIVE_CLEAR, + TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE, + }; + static const u8 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_ENABLE, + TPM2_DISABLE, + TPM2_CLEAR, + TPM2_CLEAR_ENABLE_ACTIVE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE, + TPM2_ENABLE_CLEAR, + TPM2_ENABLE_CLEAR2, + TPM2_SET_PCR_BANKS, + TPM2_CHANGE_EPS, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_LOG_ALL_DIGEST, + TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY, + TPM2_ENABLE_BLOCK_SID, + TPM2_DISABLE_BLOCK_SID, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE, + }; + + /* + * On hot reset/ACPI S3 the contents are preserved. + */ + ppib = (void *)cbmem_add(CBMEM_ID_TPM_PPI, sizeof(*ppib)); + if (!ppib) { + printk(BIOS_ERR, "PPI: Failed to add CBMEM\n"); + return; + } + printk(BIOS_DEBUG, "PPI: Pending OS request: 0x%x (0x%x)\n", ppib->pprq, ppib->pprm); + printk(BIOS_DEBUG, "PPI: OS response: CMD 0x%x = 0x%x\n", ppib->lppr, ppib->pprp); + + /* Clear unsupported fields */ + ppib->next_step = 0; + ppib->ppin = 1; // Not used by ACPI. Read by EDK-2, must be 1. + ppib->ppip = 0; + ppib->fret = 0; + ppib->next_step = 0; + + bool found = false; + /* Fill in defaults, the TPM command executor may overwrite this list */ + memset(ppib->func, 0, sizeof(ppib->func)); + if (CONFIG(TPM1)) { + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + ppib->func[tpm1_funcs[i]] = 1; + if (ppib->pprq == tpm1_funcs[i]) + found = true; + } + } else { + + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + ppib->func[tpm2_funcs[i]] = 1; + if (ppib->pprq == tpm2_funcs[i]) + found = true; + } + } + if (!found) { + // Set sane defaults + ppib->pprq = 0; + ppib->pprm = 0; + ppib->pprp = 0; + } + + /* Physical Presence OpRegion */ + struct opregion opreg = OPREGION("PPOP", SYSTEMMEMORY, (uintptr_t)ppib, + sizeof(*ppib)); + + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_name("TPM2"); + acpigen_write_package(2); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + acpigen_write_name("TPM3"); + acpigen_write_package(3); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + /* + * Returns One if the firmware implements this function. + * + * Arg0: Integer PPI function + */ + acpigen_write_method_serialized("FUNC", 1); + + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(VENDOR_SPECIFIC_OFFSET); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* If */ + + /* TPPF = CreateField("PPOP", Local0) */ + acpigen_emit_byte(CREATE_BYTE_OP); + acpigen_emit_namestring("PPOP"); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_namestring("TPPF"); + + /* Local0 = ToInteger("TPPF") */ + acpigen_emit_byte(TO_INTEGER_OP); + acpigen_emit_namestring("TPPF"); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_return_op(LOCAL0_OP); + acpigen_pop_len(); /* Method */ + + /* + * Returns One if the PPI spec supports this functions. + * That doesn't necessarily mean that the firmware implemtents it, or the + * TPM can execute the function. + * + * Arg0: Integer PPI function + * Arg1: Integer TPMversion (0: TPM2, 1: TPM1.2) + */ + acpigen_write_method("FSUP", 2); + + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(VENDOR_SPECIFIC_OFFSET); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm1_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm2_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_return_integer(0); + acpigen_pop_len(); /* Method */ + + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. + */ + DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], + ARRAY_SIZE(tpm_ppi_callbacks), NULL), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], + ARRAY_SIZE(tpm_mci_callbacks), NULL), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} + +void lb_tpm_ppi(struct lb_header *header) +{ + struct lb_tpm_physical_presence *tpm_ppi; + void *ppib; + + ppib = cbmem_find(CBMEM_ID_TPM_PPI); + if (!ppib) + return; + + tpm_ppi = (struct lb_tpm_physical_presence *)lb_new_record(header); + tpm_ppi->tag = LB_TAG_TPM_PPI_HANDOFF; + tpm_ppi->size = sizeof(*tpm_ppi); + tpm_ppi->ppi_address = (uintptr_t)ppib; + tpm_ppi->tpm_version = CONFIG(TPM1) ? LB_TPM_VERSION_TPM_VERSION_1_2 : + LB_TPM_VERSION_TPM_VERSION_2; + + tpm_ppi->ppi_version = BCD(1, 3); +} diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c index 11bd07e10ab..1e3a7fcb274 100644 --- a/src/drivers/tpm/ppi_stub.c +++ b/src/drivers/tpm/ppi_stub.c @@ -18,8 +18,8 @@ static void tpm_ppi_func0_cb(void *arg) static void tpm_ppi_func1_cb(void *arg) { if (CONFIG(TPM2)) - /* Interface version: 2.0 */ - acpigen_write_return_string("2.0"); + /* Interface version: 1.3 */ + acpigen_write_return_string("1.3"); else /* Interface version: 1.2 */ acpigen_write_return_string("1.2"); diff --git a/src/drivers/tpm/tpm_ppi.h b/src/drivers/tpm/tpm_ppi.h index 76623865753..4d468ba84dc 100644 --- a/src/drivers/tpm/tpm_ppi.h +++ b/src/drivers/tpm/tpm_ppi.h @@ -4,6 +4,7 @@ #define _TPM_PPI_H_ #include +#include #if CONFIG(HAVE_ACPI_TABLES) void tpm_ppi_acpi_fill_ssdt(const struct device *dev); @@ -13,7 +14,6 @@ static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev) } #endif - /* Return codes */ /* Function 2 */ #define PPI2_RET_SUCCESS 0 @@ -55,4 +55,92 @@ static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev) /* TCG Memory Clear Interface */ #define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 1 Physical Presence Interface Operation Summary for TPM 1.2 + */ +#define TPM_NOOP 0 +#define TPM_ENABLE 1 +#define TPM_DISABLE 2 +#define TPM_ACTIVATE 3 +#define TPM_DEACTIVATE 4 +#define TPM_CLEAR 5 +#define TPM_ENABLE_ACTIVATE 6 +#define TPM_DEACTIVATE_DISABLE 7 +#define TPM_SETOWNERINSTALL_TRUE 8 +#define TPM_SETOWNERINSTALL_FALSE 9 +#define TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE 10 +#define TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE 11 +#define TPM_CLEAR_ENABLE_ACTIVATE 14 +#define TPM_SET_NOPPIPROVISION_FALSE 15 +#define TPM_SET_NOPPIPROVISION_TRUE 16 +#define TPM_SET_NOPPICLEAR_FALSE 17 +#define TPM_SET_NOPPICLEAR_TRUE 18 +#define TPM_SET_NOPPIMAINTAINANCE_FALSE 19 +#define TPM_SET_NOPPIMAINTAINANCE_TRUE 20 +#define TPM_ENABLE_ACTIVE_CLEAR 21 +#define TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE 22 + +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 2 Physical Presence Interface Operation Summary for TPM 2.0 + */ +#define TPM2_NOOP 0 +#define TPM2_ENABLE 1 +#define TPM2_DISABLE 2 +#define TPM2_CLEAR 5 +#define TPM2_CLEAR_ENABLE_ACTIVE 14 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18 +#define TPM2_ENABLE_CLEAR 21 +#define TPM2_ENABLE_CLEAR2 22 +#define TPM2_SET_PCR_BANKS 23 +#define TPM2_CHANGE_EPS 24 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32 +#define TPM2_LOG_ALL_DIGEST 33 +#define TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY 34 +#define TPM2_ENABLE_BLOCK_SID 96 +#define TPM2_DISABLE_BLOCK_SID 97 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE 98 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE 99 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE 100 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE 101 + +#define VENDOR_SPECIFIC_OFFSET 0x80 + + /* + * The layout of the buffer matches the QEMU virtual memory device that is generated + * by QEMU. See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h' for details. + */ +struct cb_tpm_ppi_payload_handshake { + uint8_t func[256]; /* Firmware sets values for each supported operation. + * See defined values below. */ + uint8_t ppin; /* SMI interrupt to use. Set by firmware. + * Not supported. */ + uint32_t ppip; /* ACPI function index to pass to SMM code. + * Set by ACPI. Not supported. */ + uint32_t pprp; /* Result of last executed operation. + * Set by firmware. See function index 5 for values. */ + uint32_t pprq; /* Operation request number to execute. + * See 'Physical Presence Interface Operation Summary' + * tables in specs. Set by ACPI. */ + uint32_t pprm; /* Operation request optional parameter. + * Values depend on operation. Set by ACPI. */ + uint32_t lppr; /* Last executed operation request number. + * Copied from pprq field by firmware. */ + uint32_t fret; /* Result code from SMM function. Not supported. */ + uint8_t res1[0x040]; /* Reserved */ + uint8_t next_step; /* Operation to execute after reboot by firmware. + * Used by firmware. */ +} __packed; + +void lb_tpm_ppi(struct lb_header *header); + #endif /* _TPM_PPI_H_ */ diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index eda9130dd48..7d45eb6a850 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -5,3 +5,22 @@ config VPD default n help Enable support for flash based vital product data. + +config VPD_FMAP_NAME + string + depends on VPD + default "RO_VPD" + help + Name of the FMAP region created in the default FMAP to store VPD tables. + +config VPD_FMAP_SIZE + hex + depends on VPD + default 0x4000 + help + Size in bytes of the FMAP region created to store VPD tables. + +config SMBIOS_SERIAL_FROM_VPD + bool "Load device serial from VPD" + depends on VPD && GENERATE_SMBIOS_TABLES + default n diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index f54c4d0dd9c..615e48a18eb 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -5,3 +5,4 @@ verstage-$(CONFIG_VPD) += vpd_decode.c vpd.c romstage-$(CONFIG_VPD) += vpd_decode.c vpd.c postcar-$(CONFIG_VPD) += vpd_decode.c vpd.c ramstage-$(CONFIG_VPD) += vpd_decode.c vpd.c +ramstage-$(CONFIG_SMBIOS_SERIAL_FROM_VPD) += vpd_serial.c diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index c332a6e94c3..d3ff37019d6 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -3,10 +3,12 @@ #include #include #include +#include #include #include #include #include +#include #include "vpd.h" #include "vpd_decode.h" @@ -274,4 +276,25 @@ bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val) return false; } +/* + * Find value of integer type by vpd key. + * + * Expects to find a decimal string, trailing chars are ignored. + * Returns true if the key is found and the value is not too long and + * starts with a decimal digit. Leaves `val` untouched if unsuccessful. + */ +bool vpd_get_int(const char *const key, const enum vpd_region region, int *const val) +{ + char value[11]; + + if (!vpd_gets(key, value, sizeof(value), region)) + return false; + + if (!isdigit(*value)) + return false; + + *val = (int)atol(value); + return true; +} + ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 25e0aed4ee6..817867aba4b 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -50,4 +50,13 @@ const void *vpd_find(const char *key, int *size, enum vpd_region region); bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val); +/* + * Find value of integer type by vpd key. + * + * Expects to find a decimal string, trailing chars are ignored. + * Returns true if the key is found and the value is not too long and + * starts with a decimal digit. + */ +bool vpd_get_int(const char *key, enum vpd_region region, int *val); + #endif /* __VPD_H__ */ diff --git a/src/drivers/vpd/vpd_serial.c b/src/drivers/vpd/vpd_serial.c new file mode 100644 index 00000000000..528dcbb368c --- /dev/null +++ b/src/drivers/vpd/vpd_serial.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include + +#include "vpd.h" +#include "vpd_tables.h" + +#define VPD_KEY_SYSTEM_SERIAL "serial_number" +#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" +#define VPD_SERIAL_LEN 64 + +const char *smbios_system_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} + +const char *smbios_mainboard_serial_number(void) +{ + static char serial[VPD_SERIAL_LEN]; + if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) + return serial; + return ""; +} diff --git a/src/ec/acpi/ec.asl b/src/ec/acpi/ec.asl index 47c74bdd44e..dd3efac95f9 100644 --- a/src/ec/acpi/ec.asl +++ b/src/ec/acpi/ec.asl @@ -45,8 +45,8 @@ Field(ERDT, ByteAcc, NoLock, Preserve) { EC_DATA, 8 } */ Method (WAIT_EC_SC, 2) { - Store (0x7ff, Local0) /* Timeout */ - While (LAnd (LNotEqual (And (EC_SC, Arg0), Arg1), Decrement (Local0))) { + Local0 = 0x7ff /* Timeout */ + While (((EC_SC & Arg0) != Arg1) && Local0--) { Stall (10) } If (Local0) { @@ -66,8 +66,8 @@ Method (WAIT_EC_SC, 2) */ Method (SEND_EC_COMMAND, 1) { - Store (WAIT_EC_SC (EC_IBF, 0), Local0) - If (LNot (Local0)) { + Local0 = WAIT_EC_SC (EC_IBF, 0) + If (!Local0) { Store (Arg0, EC_SC) } Return (Local0) @@ -83,9 +83,9 @@ Method (SEND_EC_COMMAND, 1) */ Method (SEND_EC_DATA, 1) { - Store (WAIT_EC_SC (EC_IBF, 0), Local0) - If (LNot (Local0)) { - Store (Arg0, EC_DATA) + Local0 = WAIT_EC_SC (EC_IBF, 0) + If (!Local0) { + EC_DATA = Arg0 } Return (Local0) } @@ -100,8 +100,8 @@ Method (SEND_EC_DATA, 1) */ Method (RECV_EC_DATA) { - Store (WAIT_EC_SC (EC_OBF, EC_OBF), Local0) - If (LNot (Local0)) { + Local0 = WAIT_EC_SC (EC_OBF, EC_OBF) + If (!Local0) { Return (EC_DATA) } Else { Return (Local0) @@ -117,12 +117,12 @@ Method (RECV_EC_DATA) Method (EC_READ, 1) { Acquire (EC_MUTEX, 0xffff) - Store (SEND_EC_COMMAND (EC_READ_CMD), Local0) - If (LNot (Local0)) { - Store (SEND_EC_DATA (Arg0), Local0) + Local0 = SEND_EC_COMMAND (EC_READ_CMD) + If (!Local0) { + Local0 = SEND_EC_DATA (Arg0) } - If (LNot (Local0)) { - Store (RECV_EC_DATA (), Local0) + If (!Local0) { + Local0 = RECV_EC_DATA () } Release (EC_MUTEX) @@ -139,12 +139,12 @@ Method (EC_READ, 1) Method (EC_WRITE, 2) { Acquire (EC_MUTEX, 0xffff) - Store (SEND_EC_COMMAND (EC_WRITE_CMD), Local0) - If (LNot (Local0)) { - Store (SEND_EC_DATA (Arg0), Local0) + Local0 = SEND_EC_COMMAND (EC_WRITE_CMD) + If (!Local0) { + Local0 = SEND_EC_DATA (Arg0) } - If (LNot (Local0)) { - Store (SEND_EC_DATA (Arg1), Local0) + If (!Local0) { + Local0 = SEND_EC_DATA (Arg1) } Release (EC_MUTEX) diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 7cb71193c7c..a60de27ac5a 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -84,7 +84,7 @@ u8 recv_ec_data(void) udelay(10); data = inb(ec_data_reg); - printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data); + printk(BIOS_SPEW, "%s: 0x%02x\n", __func__, data); return data; } diff --git a/src/ec/compal/ene932/acpi/ac.asl b/src/ec/compal/ene932/acpi/ac.asl index b086bf5cd21..cc14b33addb 100644 --- a/src/ec/compal/ene932/acpi/ac.asl +++ b/src/ec/compal/ene932/acpi/ac.asl @@ -9,7 +9,7 @@ Device (AC) Method (_PSR) { - Store(ADPT, Local0) + Local0 = ADPT Return(Local0) } diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl index b3bf157e1b7..9c70b594bca 100644 --- a/src/ec/compal/ene932/acpi/battery.asl +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -38,13 +38,13 @@ Device (BATX) // Method to enable full battery workaround Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } // Method to disable full battery workaround Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } Method (_STA, 0, Serialized) @@ -59,22 +59,22 @@ Device (BATX) Method (_BIF, 0, Serialized) { // Update fields from EC - Store (BAM0, Index (PBIF, 0)) - Store (BDC0, Index (PBIF, 1)) - Store (BFC0, Index (PBIF, 2)) - Store (BDV0, Index (PBIF, 4)) - Divide(BFC0, 0x64, , Local1) - Multiply(Local1, 0x0A, Local1) - Store(Local1, Index(PBIF, 5)) - Divide(BFC0, 0x64, , Local1) - Multiply(Local1, 0x03, Local1) - Store (Local1, Index (PBIF, 6)) - - Store (ToString(Concatenate(BATD, 0x00)), Index (PBIF, 9)) // model - Store (ToHexString(BSN0), Index (PBIF, 10)) // serial - Store (ToString(BMFN), Index (PBIF, 12)) // vendor - - Store(BDN0, BTNM) // Save the battery number + PBIF [0] = BAM0 + PBIF [1] = BDC0 + PBIF [2] = BFC0 + PBIF [4] = BDV0 + Local1 = BFC0 / 100 + Local1 *= 10 + PBIF [5] = Local1 + Local1 = BFC0 / 100 + Local1 *= 3 + PBIF [6] = Local1 + + PBIF [9] = ToString (Concatenate (BATD, 0x00)) // model + PBIF [10] = ToHexString (BSN0) // serial + PBIF [12] = ToString (BMFN) // vendor + + BTNM = BDN0 // Save the battery number Return (PBIF) } @@ -90,47 +90,47 @@ Device (BATX) // // Get battery state from EC and save it for the charging workaround - Store (BST0, Local0) - Store (Local0, Index (PBST, 0)) + Local0 = BST0 + PBST [0] = Local0 // // 1: BATTERY PRESENT RATE/CURRENT // - Store (BAC0, Local1) - Subtract(0xFFFF, Local1, Local1) - Store (Local1, Index (PBST, 1)) + Local1 = BAC0 + Local1 = 0xFFFF - Local1 + PBST [1] = Local1 // // 2: BATTERY REMAINING CAPACITY // - Multiply(BFC0, GAU0, Local1) - Divide(Local1, 0x64, Local2, Local1) + Local1 = BFC0 * GAU0 + Local2 = Local1 % 100 + Local1 /= 100 - If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) { + If (BFWK && ADPT && !Local0) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. // https://bugzilla.kernel.org/show_bug.cgi?id=12632 - Store (GAU0, Local2) + Local2 = GAU0 // See if within ~3% of full - ShiftRight (Local2, 5, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + Local3 = Local2 >> 5 + If ((Local1 > (Local2 - Local3)) && (Local1 < (Local2 + Local3))) { - Store (Local2, Local1) + Local1 = Local2 } } - Store (Local1, Index (PBST, 2)) + PBST [2] = Local1 // // 3: BATTERY PRESENT VOLTAGE // - Store (BPV0, Index (PBST, 3)) + PBST [3] = BPV0 // Check the Battery Number - If(LNotEqual(BDN0, BTNM)) { + If(BDN0 != BTNM) { Notify(BATX, 0x81) } diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index c4fa3a38d37..f3fb9979fee 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -252,12 +252,12 @@ Device (EC0) Method (_REG, 2, NotSerialized) { // Initialize AC power state - Store (ADPT, \PWRS) + \PWRS = ADPT // Force a read of CPU temperature - Store (CTML, Local0) + Local0 = CTML /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } @@ -322,7 +322,7 @@ Device (EC0) // AC Power Connected Method (_Q37, 0, NotSerialized) { - Store (One, \PWRS) + \PWRS = 1 Notify (AC, 0x80) Notify (BATX, 0x80) // TODO ADD CPU power profile @@ -332,7 +332,7 @@ Device (EC0) // AC Power Removed Method (_Q38, 0, NotSerialized) { - Store (Zero, \PWRS) + \PWRS = 0 Notify (AC, 0x80) Notify (BATX, 0x80) // TODO ADD CPU power profile @@ -363,7 +363,7 @@ Device (EC0) { IF(WLEX) //if Wlan exist { - //TODO Store(WLAT, LANE) + //TODO LANE = WLAT } } diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b091c..7b1a66391c7 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -81,6 +81,7 @@ Device (EC0) Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power + RFWU, 8, // Retimer Firmware Update } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index ed7f97dc43c..0915833b911 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -863,6 +863,11 @@ int google_chromeec_cbi_get_board_version(uint32_t *version) return cbi_get_uint32(version, CBI_TAG_BOARD_VERSION); } +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc) +{ + return cbi_get_uint32(ssfc, CBI_TAG_SSFC); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { @@ -993,9 +998,24 @@ static uint16_t google_chromeec_get_uptime_info( bool google_chromeec_get_ap_watchdog_flag(void) { + int i; struct ec_response_uptime_info resp; - return (!google_chromeec_get_uptime_info(&resp) && - (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG)); + + if (google_chromeec_get_uptime_info(&resp)) + return false; + + if (resp.ec_reset_flags & EC_RESET_FLAG_AP_WATCHDOG) + return true; + + /* Find the last valid entry */ + for (i = ARRAY_SIZE(resp.recent_ap_reset) - 1; i >= 0; i--) { + if (resp.recent_ap_reset[i].reset_time_ms == 0) + continue; + return (resp.recent_ap_reset[i].reset_cause == + CHIPSET_RESET_AP_WATCHDOG); + } + + return false; } int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c3c456ff141..35ce3cce6e3 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -29,7 +29,7 @@ void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); /* Check for the current mux state in EC * in: int port physical port number of the type-c port - * out: uint8_t flags flags representing the status of the mux such as + * out: uint8_t flags representing the status of the mux such as * usb capability, dp capability, cable type, etc */ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); @@ -78,7 +78,7 @@ int google_chromeec_reboot(int dev_idx, enum ec_reboot_cmd type, uint8_t flags); /** * Get data from Cros Board Info * - * @param id/fw_config/buf [OUT] value from from CBI. + * @param id/fw_config/buf [OUT] value from CBI. * @return 0 on success or negative integer for errors. */ int google_chromeec_cbi_get_oem_id(uint32_t *id); @@ -89,6 +89,7 @@ int google_chromeec_cbi_get_oem_name(char *buf, size_t bufsize); /* version may be stored in CBI as a smaller integer width, but the EC code handles it correctly. */ int google_chromeec_cbi_get_board_version(uint32_t *version); +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc); #define CROS_SKU_UNKNOWN 0xFFFFFFFF #define CROS_SKU_UNPROVISIONED 0x7FFFFFFF diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index fff395411c2..bcecd8920b9 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "chip.h" @@ -235,3 +236,30 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev) fill_ssdt_typec_device(dev); fill_ssdt_ps2_keyboard(dev); } + +const char *ec_retimer_fw_update_path(void) +{ + return "\\_SB_.PCI0.LPCB.EC0_.RFWU"; +} + +void ec_retimer_fw_update(void *arg) +{ + const char *RFWU = ec_retimer_fw_update_path(); + + /* + * Get information to set retimer info from Arg3[0] + * Local0 = DeRefOf (Arg3[0]) + */ + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); + + /* + * Write the EC RAM for Retimer Upgrade + * RFWU = LOCAL0 + */ + acpigen_write_store(); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_namestring(RFWU); + + /* Return (Zero) */ + acpigen_write_return_integer(0); +} diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index fb83d60443f..3bd6b9359fd 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -29,7 +29,10 @@ extern "C" { #include "compile_time_macros.h" #else +/* If BUILD_ASSERT isn't already defined, make it a no-op */ +#ifndef BUILD_ASSERT #define BUILD_ASSERT(_cond) +#endif /* !BUILD_ASSERT */ #endif /* CHROMIUM_EC */ #ifdef __KERNEL__ @@ -50,6 +53,21 @@ extern "C" { #define BIT_ULL(nr) (1ULL << (nr)) #endif +/* + * When building Zephyr, this file ends up being included before Zephyr's + * include/sys/util.h so causes a warning there. We don't want to add an #ifdef + * in that file since it won't be accepted upstream. So work around it here. + */ +#ifndef CONFIG_ZEPHYR +#ifndef GENMASK +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#endif + +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) +#endif +#endif + #endif /* __KERNEL__ */ /* @@ -878,7 +896,7 @@ struct ec_host_response { * * Packets always start with a request or response header. They are followed * by data_len bytes of data. If the data_crc_present flag is set, the data - * bytes are followed by a CRC-8 of that data, using using x^8 + x^2 + x + 1 + * bytes are followed by a CRC-8 of that data, using x^8 + x^2 + x + 1 * polynomial. * * Host algorithm when sending a request q: @@ -1388,7 +1406,7 @@ enum ec_feature_code { */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, /* - * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option. + * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should * be sent to RO to be precise. */ @@ -1397,6 +1415,18 @@ enum ec_feature_code { EC_FEATURE_SCP = 39, /* The MCU is an Integrated Sensor Hub */ EC_FEATURE_ISH = 40, + /* New TCPMv2 TYPEC_ prefaced commands supported */ + EC_FEATURE_TYPEC_CMD = 41, + /* + * The EC will wait for direction from the AP to enter Type-C alternate + * modes or USB4. + */ + EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42, + /* + * The EC will wait for an acknowledge from the AP after setting the + * mux. + */ + EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2599,6 +2629,11 @@ enum motionsensor_orientation { MOTIONSENSE_ORIENTATION_UNKNOWN = 4, }; +struct ec_response_activity_data { + uint8_t activity; /* motionsensor_activity */ + uint8_t state; +} __ec_todo_packed; + struct ec_response_motion_sensor_data { /* Flags for each sensor. */ uint8_t flags; @@ -2606,17 +2641,16 @@ struct ec_response_motion_sensor_data { uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; /* for sensors using unsigned data */ - uint16_t udata[3]; + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { - uint8_t activity; /* motionsensor_activity */ - uint8_t state; - int16_t add_info[2]; + struct ec_response_activity_data activity_data; + int16_t add_info[2]; }; }; } __ec_todo_packed; @@ -2864,8 +2898,19 @@ struct ec_params_motion_sense { /* Ignored, used for alignment. */ uint8_t reserved; - /* Individual component values to spoof. */ - int16_t components[3]; + union { + /* Individual component values to spoof. */ + int16_t components[3]; + + /* Used when spoofing an activity */ + struct { + /* enum motionsensor_activity */ + uint8_t activity_num; + + /* spoof activity state */ + uint8_t activity_state; + }; + }; } spoof; /* Used for MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ @@ -3768,6 +3813,7 @@ struct ec_response_get_next_event_v1 { #define EC_MKBP_LID_OPEN 0 #define EC_MKBP_TABLET_MODE 1 #define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 @@ -4637,6 +4683,7 @@ enum ec_device_event { EC_DEVICE_EVENT_TRACKPAD, EC_DEVICE_EVENT_DSP, EC_DEVICE_EVENT_WIFI, + EC_DEVICE_EVENT_WLC, }; enum ec_device_event_param { @@ -5183,6 +5230,7 @@ enum ec_reboot_cmd { EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ @@ -5395,10 +5443,6 @@ enum pd_cc_states { /* Active Link Uni-Direction */ #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) -/* - * Underdevelopement : - * Please remove this tag if using _v2 outside platform/ec - */ struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; @@ -5408,8 +5452,7 @@ struct ec_response_usb_pd_control_v2 { uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ uint8_t reserved; /* Reserved for future use */ uint8_t control_flags; /* USB_PD_CTRL_*flags */ - /* TODO: b:158234949 Add definitions for cable speed */ - uint8_t cable_speed; /* USB_R30_SS/TBT_SS_* cable speed */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; @@ -5833,7 +5876,7 @@ struct ec_params_set_cbi { */ #define EC_CMD_GET_UPTIME_INFO 0x0121 -/* Reset causes */ +/* EC reset causes */ #define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ #define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ #define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ @@ -5862,6 +5905,72 @@ struct ec_params_set_cbi { #define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ #define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ +/* + * Reason codes used by the AP after a shutdown to figure out why it was reset + * by the EC. These are sent in EC commands. Therefore, to maintain protocol + * compatibility: + * - New entries must be inserted prior to the _COUNT field + * - If an existing entry is no longer in service, it must be replaced with a + * RESERVED entry instead. + * - The semantic meaning of an entry should not change. + * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. + */ +enum chipset_reset_reason { + CHIPSET_RESET_BEGIN = 0, + CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, + /* Custom reason defined by a board.c or baseboard.c file */ + CHIPSET_RESET_BOARD_CUSTOM, + /* Believe that the AP has hung */ + CHIPSET_RESET_HANG_REBOOT, + /* Reset by EC console command */ + CHIPSET_RESET_CONSOLE_CMD, + /* Reset by EC host command */ + CHIPSET_RESET_HOST_CMD, + /* Keyboard module reset key combination */ + CHIPSET_RESET_KB_SYSRESET, + /* Keyboard module warm reboot */ + CHIPSET_RESET_KB_WARM_REBOOT, + /* Debug module warm reboot */ + CHIPSET_RESET_DBG_WARM_REBOOT, + /* I cannot self-terminate. You must lower me into the steel. */ + CHIPSET_RESET_AP_REQ, + /* Reset as side-effect of startup sequence */ + CHIPSET_RESET_INIT, + /* EC detected an AP watchdog event. */ + CHIPSET_RESET_AP_WATCHDOG, + + CHIPSET_RESET_COUNT, +}; + +/* + * AP hard shutdowns are logged on the same path as resets. + */ +enum chipset_shutdown_reason { + CHIPSET_SHUTDOWN_BEGIN = BIT(15), + CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, + /* Forcing a shutdown as part of EC initialization */ + CHIPSET_SHUTDOWN_INIT, + /* Custom reason on a per-board basis. */ + CHIPSET_SHUTDOWN_BOARD_CUSTOM, + /* This is a reason to inhibit startup, not cause shut down. */ + CHIPSET_SHUTDOWN_BATTERY_INHIBIT, + /* A power_wait_signal is being asserted */ + CHIPSET_SHUTDOWN_WAIT, + /* Critical battery level. */ + CHIPSET_SHUTDOWN_BATTERY_CRIT, + /* Because you told me to. */ + CHIPSET_SHUTDOWN_CONSOLE_CMD, + /* Forcing a shutdown to effect entry to G3. */ + CHIPSET_SHUTDOWN_G3, + /* Force shutdown due to over-temperature. */ + CHIPSET_SHUTDOWN_THERMAL, + /* Force a chipset shutdown from the power button through EC */ + CHIPSET_SHUTDOWN_BUTTON, + + CHIPSET_SHUTDOWN_COUNT, +}; + + struct ec_response_uptime_info { /* * Number of milliseconds since the last EC boot. Sysjump resets @@ -5889,10 +5998,7 @@ struct ec_response_uptime_info { /* Empty log entries have both the cause and timestamp set to zero. */ struct ap_reset_log_entry { - /* - * See include/chipset.h: enum chipset_{reset,shutdown}_reason - * for details. - */ + /* See enum chipset_{reset,shutdown}_reason for details. */ uint16_t reset_cause; /* Reserved for protocol growth. */ @@ -6012,13 +6118,21 @@ struct ec_response_locate_chip { * * This command is used for validation purpose, where the AP needs to be * returned back to S0 state from G3 state without using the servo to trigger - * wake events.For this,there is no request or response struct. - * - * Order of command usage: - * ectool reboot_ap_on_g3 && shutdown -h now + * wake events. + * - With command version 0: + * AP reboots immediately from G3 + * command usage: ectool reboot_ap_on_g3 && shutdown -h now + * - With command version 1: + * AP reboots after the user specified delay + * command usage: ectool reboot_ap_on_g3 [] && shutdown -h now */ #define EC_CMD_REBOOT_AP_ON_G3 0x0127 +struct ec_params_reboot_ap_on_g3_v1 { + /* configurable delay in seconds in G3 state */ + uint32_t reboot_ap_at_g3_delay; +} __ec_align4; + /*****************************************************************************/ /* Get PD port capabilities * @@ -6366,6 +6480,14 @@ struct ec_response_typec_discovery { enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + TYPEC_CONTROL_COMMAND_ENTER_MODE, +}; + +/* Modes (USB or alternate) that a type-C port may enter. */ +enum typec_mode { + TYPEC_MODE_DP, + TYPEC_MODE_TBT, + TYPEC_MODE_USB4, }; struct ec_params_typec_control { @@ -6380,6 +6502,7 @@ struct ec_params_typec_control { */ union { uint32_t clear_events_mask; + uint8_t mode_to_enter; /* enum typec_mode */ uint8_t placeholder[128]; }; } __ec_align1; @@ -6393,9 +6516,6 @@ struct ec_params_typec_control { * EC_CMD_USB_PD_CONTROL command. * * This also combines in the EC_CMD_USB_PD_MUX_INFO flags. - * - * Version 0 of command is under development - * TODO(b/167700356): Remove this statement when version 0 is finalized */ #define EC_CMD_TYPEC_STATUS 0x0133 @@ -6469,33 +6589,183 @@ enum tcpc_cc_polarity { #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +/* + * Encode and decode for BCD revision response + * + * Note: the major revision set is written assuming that the value given is the + * Specification Revision from the PD header, which currently only maps to PD + * 1.0-3.0 with the major revision being one greater than the binary value. + */ +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) + +/* + * Decode helpers for Source and Sink Capability PDOs + * + * Note: The Power Delivery Specification should be considered the ultimate + * source of truth on the decoding of these PDOs + */ +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_AUGMENTED (3 << 30) +#define PDO_TYPE_MASK (3 << 30) + +/* + * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Fixed Supply + * <29> : Dual-Role Power + * <28> : SNK/SRC dependent + * <27> : Unconstrained Power + * <26> : USB Communications Capable + * <25> : Dual-Role Data + * <24:20> : SNK/SRC dependent + * <19:10> : Voltage in 50mV Units + * <9:0> : Maximum Current in 10mA units + */ +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Battery + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Maximum Allowable Power in 250mW units + */ +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) + +/* + * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 + * + * <31:30> : Variable Supply (non-Battery) + * <29:20> : Maximum Voltage in 50mV units + * <19:10> : Minimum Voltage in 50mV units + * <9:0> : Operational Current in 10mA units + */ +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) + +/* + * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 + * + * Note this type is reserved in PD 2.0, and only one type of APDO is + * supported as of the cited version. + * + * <31:30> : Augmented Power Data Object + * <29:28> : Programmable Power Supply + * <27> : PPS Power Limited + * <26:25> : Reserved + * <24:17> : Maximum Voltage in 100mV increments + * <16> : Reserved + * <15:8> : Minimum Voltage in 100mV increments + * <7> : Reserved + * <6:0> : Maximum Current in 50mA increments + */ +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) + struct ec_params_typec_status { uint8_t port; } __ec_align1; struct ec_response_typec_status { - uint8_t pd_enabled; /* PD communication enabled - bool */ - uint8_t dev_connected; /* Device connected - bool */ - uint8_t sop_connected; /* Device is SOP PD capable - bool */ - uint8_t reserved1; /* Reserved for future use */ + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ - uint8_t power_role; /* enum pd_power_role */ - uint8_t data_role; /* enum pd_data_role */ - uint8_t vconn_role; /* enum pd_vconn_role */ - uint8_t reserved2; /* Reserved for future use */ + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ - uint8_t polarity; /* enum tcpc_cc_polarity */ - uint8_t cc_state; /* enum pd_cc_states */ - uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ - uint8_t mux_state; /* USB_PD_MUX* - encoded USB mux state */ + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ - char tc_state[32]; /* TC state name */ + char tc_state[32]; /* TC state name */ - uint32_t events; /* PD_STATUS_EVENT bitmask */ + uint32_t events; /* PD_STATUS_EVENT bitmask */ - /* TODO(b/167700356): Add revisions and source cap PDOs */ + /* + * BCD PD revisions for partners + * + * The format has the PD major reversion in the upper nibble, and PD + * minor version in the next nibble. Following two nibbles are + * currently 0. + * ex. PD 3.2 would map to 0x3200 + * + * PD major/minor will be 0 if no PD device is connected. + */ + uint16_t sop_revision; + uint16_t sop_prime_revision; + + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ } __ec_align1; +/** + * Get the number of peripheral charge ports + */ +#define EC_CMD_PCHG_COUNT 0x0134 + +#define EC_PCHG_MAX_PORTS 8 + +struct ec_response_pchg_count { + uint8_t port_count; +} __ec_align1; + +/** + * Get the status of a peripheral charge port + */ +#define EC_CMD_PCHG 0x0135 + +struct ec_params_pchg { + uint8_t port; +} __ec_align1; + +struct ec_response_pchg { + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ + uint8_t battery_percentage; +} __ec_align2; + +enum pchg_state { + /* Charger is reset and not initialized. */ + PCHG_STATE_RESET = 0, + /* Charger is initialized or disabled. */ + PCHG_STATE_INITIALIZED, + /* Charger is enabled and ready to detect a device. */ + PCHG_STATE_ENABLED, + /* Device is detected in proximity. */ + PCHG_STATE_DETECTED, + /* Device is being charged. */ + PCHG_STATE_CHARGING, +}; + +#define EC_PCHG_STATE_TEXT { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + } + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -6841,6 +7111,28 @@ struct ec_response_battery_static_info { uint32_t cycle_count; } __ec_align4; +/** + * struct ec_response_battery_static_info_v1 - hostcmd v1 battery static info + * Equivalent to struct ec_response_battery_static_info, but with longer + * strings. + * @design_capacity: battery design capacity (in mAh) + * @design_voltage: battery design voltage (in mV) + * @cycle_count: battery cycle count + * @manufacturer_ext: battery manufacturer string + * @model_ext: battery model string + * @serial_ext: battery serial number string + * @type_ext: battery type string + */ +struct ec_response_battery_static_info_v1 { + uint16_t design_capacity; + uint16_t design_voltage; + uint32_t cycle_count; + char manufacturer_ext[12]; + char model_ext[12]; + char serial_ext[12]; + char type_ext[12]; +} __ec_align4; + /* * Get battery dynamic information, i.e. information that is likely to change * every time it is read. @@ -6896,6 +7188,13 @@ struct ec_params_charger_control { uint8_t allow_charging; } __ec_align_size1; +/* Get ACK from the USB-C SS muxes */ +#define EC_CMD_USB_PD_MUX_ACK 0x0603 + +struct ec_params_usb_pd_mux_ack { + uint8_t port; /* USB-C port number */ +} __ec_align1; + /*****************************************************************************/ /* * Reserve a range of host commands for board-specific, experimental, or diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index 705988af24b..6de72e817d0 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -96,7 +96,7 @@ Method (PATX, 0, Serialized) Printf ("Sensor trip mask: %o", Local0) - If (LNot (Acquire (^PATM, 1000))) { + If (!Acquire (^PATM, 1000)) { /* Handle bits that are set */ While (FindSetRightBit (Local1, Local2)) diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 7531dbf8a5d..d5526044068 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -50,7 +50,7 @@ Device (EC0) ^UCSI.INIT () // Initialize LID switch state - Store (R (P1LC), \LIDS) + \LIDS = R (P1LC) } /* diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl index 3fae71f5a5e..c381499c67f 100644 --- a/src/ec/google/wilco/acpi/lid.asl +++ b/src/ec/google/wilco/acpi/lid.asl @@ -8,7 +8,7 @@ Device (LID0) Method (_LID, 0, NotSerialized) { - Store (R (P1LC), \LIDS) + \LIDS = R (P1LC) Return (\LIDS) } } diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 43e5d3fb0ba..4d7d46d9e79 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS),y) KBC1126_EC_INSERT:=$(top)/util/kbc1126/kbc1126_ec_insert -INTERMEDIATE+=kbc1126_ec_insert ifeq ($(CONFIG_KBC1126_FIRMWARE),y) cbfs-files-y += ecfw1.bin @@ -17,7 +16,7 @@ ecfw2.bin-position := $(CONFIG_KBC1126_FW2_OFFSET) ecfw2.bin-type := raw endif -kbc1126_ec_insert: $(obj)/coreboot.pre +$(call add_intermediate, kbc1126_ec_insert) ifeq ($(CONFIG_KBC1126_FIRMWARE),y) printf " Building kbc1126_ec_insert.\n" $(MAKE) -C util/kbc1126 @@ -26,8 +25,6 @@ ifeq ($(CONFIG_KBC1126_FIRMWARE),y) $(CONFIG_KBC1126_FW1_OFFSET) $(CONFIG_KBC1126_FW2_OFFSET) endif -PHONY+=kbc1126_ec_insert - build_complete:: ifeq ($(CONFIG_KBC1126_FIRMWARE),) printf "\n** WARNING **\n" diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index 143dd044947..abdd8be919f 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -180,14 +180,14 @@ Device (EC) Method (_Q34) { TPSN (0x87) - XOr (^TPAD, One, ^TPAD) + ^TPAD ^= 1 } /* KEY_WLAN */ Method (_Q35) { TPSN (0x88) - XOr (^WIFI, One, ^WIFI) + ^WIFI ^= 1 } /* KEY_BLUETOOTH */ diff --git a/src/ec/system76/ec/acpi/ec_ram.asl b/src/ec/system76/ec/acpi/ec_ram.asl index d5f97edbd76..6ef54540b69 100644 --- a/src/ec/system76/ec/acpi/ec_ram.asl +++ b/src/ec/system76/ec/acpi/ec_ram.asl @@ -3,173 +3,52 @@ OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) Field (ERAM, ByteAcc, Lock, Preserve) { - NMSG, 8, - SLED, 4, - Offset (0x02), - MODE, 1, - FAN0, 1, - TME0, 1, - TME1, 1, - FAN1, 1, - , 2, Offset (0x03), - LSTE, 1, - LSW0, 1, - LWKE, 1, - WAKF, 1, - , 2, - PWKE, 1, - MWKE, 1, - AC0, 8, - PSV, 8, - CRT, 8, - TMP, 8, - AC1, 8, - BBST, 8, - Offset (0x0B), - Offset (0x0C), - Offset (0x0D), - Offset (0x0E), - SLPT, 8, - SWEJ, 1, - SWCH, 1, + LSTE, 1, // Lid is open + , 1, + LWKE, 1, // Lid wake + , 5, + Offset (0x07), + TMP1, 8, // CPU temperature Offset (0x10), - ADP, 1, - AFLT, 1, - BAT0, 1, - BAT1, 1, - , 3, - PWOF, 1, - WFNO, 8, - BPU0, 32, - BDC0, 32, - BFC0, 32, - BTC0, 32, - BDV0, 32, - BST0, 32, - BPR0, 32, - BRC0, 32, - BPV0, 32, - BTP0, 16, - BRS0, 16, - BCW0, 32, - BCL0, 32, - BCG0, 32, - BG20, 32, - BMO0, 64, - BIF0, 64, - BSN0, 32, - BTY0, 64, - Offset (0x67), + ADP, 1, // AC adapter connected + , 1, + BAT0, 1, // Battery connected + , 5, + WFNO, 8, // Wake cause (not implemented) + Offset (0x16), + BDC0, 32, // Battery design capacity + BFC0, 32, // Battery full capacity + Offset (0x22), + BDV0, 32, // Battery design voltage + BST0, 32, // Battery status + BPR0, 32, // Battery current + BRC0, 32, // Battery remaining capacity + BPV0, 32, // Battery voltage + Offset (0x3A), + BCW0, 32, + BCL0, 32, Offset (0x68), - ECOS, 8, - LNXD, 8, - ECPS, 8, - Offset (0x6C), - BTMP, 16, - EVTN, 8, - Offset (0x72), - PRCL, 8, - PRC0, 8, - PRC1, 8, - PRCM, 8, - PRIN, 8, - PSTE, 8, - PCAD, 8, - PEWL, 8, - PWRL, 8, - PECD, 8, - PEHI, 8, - PECI, 8, - PEPL, 8, - PEPM, 8, - PWFC, 8, - PECC, 8, - PDT0, 8, - PDT1, 8, - PDT2, 8, - PDT3, 8, - PRFC, 8, - PRS0, 8, - PRS1, 8, - PRS2, 8, - PRS3, 8, - PRS4, 8, - PRCS, 8, - PEC0, 8, - PEC1, 8, - PEC2, 8, - PEC3, 8, - CMDR, 8, - CVRT, 8, - GTVR, 8, - FANT, 8, - SKNT, 8, - AMBT, 8, - MCRT, 8, - DIM0, 8, - DIM1, 8, - PMAX, 8, - PPDT, 8, - PECH, 8, - PMDT, 8, - TSD0, 8, - TSD1, 8, - TSD2, 8, - TSD3, 8, - CPUP, 16, - MCHP, 16, - SYSP, 16, - CPAP, 16, - MCAP, 16, - SYAP, 16, - CFSP, 16, - CPUE, 16, - Offset (0xC6), - Offset (0xC7), - VGAT, 8, - OEM1, 8, - OEM2, 8, - OEM3, 16, - OEM4, 8, - Offset (0xCE), - DUT1, 8, - DUT2, 8, - RPM1, 16, - RPM2, 16, - RPM4, 16, - Offset (0xD7), - DTHL, 8, - DTBP, 8, - AIRP, 8, - WINF, 8, - RINF, 8, - Offset (0xDD), - INF2, 8, - MUTE, 1, - Offset (0xE0), - RPM3, 16, - ECKS, 8, - Offset (0xE4), - , 4, - XTUF, 1, - EP12, 1, - Offset (0xE5), - INF3, 8, - Offset (0xE7), - GFOF, 8, - Offset (0xE9), - KPCR, 1, - Offset (0xEA), - Offset (0xF0), - PL1T, 16, - PL2T, 16, - TAUT, 8, + ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver + Offset (0xC8), + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, // Extra SCI data + Offset (0xCD), + TMP2, 8, // GPU temperature + DUT1, 8, // Fan 1 duty + DUT2, 8, // Fan 2 duty + RPM1, 16, // Fan 1 RPM + RPM2, 16, // Fan 2 RPM + Offset (0xD9), + AIRP, 8, // Airplane mode LED + WINF, 8, // Enable ACPI brightness controls Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, - FBF3, 8 + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8, } diff --git a/src/ec/system76/ec/acpi/s76.asl b/src/ec/system76/ec/acpi/s76.asl index 7beb50b8139..a2bb310938b 100644 --- a/src/ec/system76/ec/acpi/s76.asl +++ b/src/ec/system76/ec/acpi/s76.asl @@ -111,4 +111,51 @@ Device (S76D) { } } #endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD) + + // Fan names + Method (NFAN, 0, Serialized) { + Return (Package() { + "CPU fan", + }) + } + + // Get fan duty cycle and RPM as a single value + Method (GFAN, 1, Serialized) { + Local0 = 0 + Local1 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.DUT1 + Local1 = ^^PCI0.LPCB.EC0.RPM1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.DUT2 + Local1 = ^^PCI0.LPCB.EC0.RPM2 + } + } + If (Local1 != 0) { + // 60 * (EC frequency / 120) / 2 + Local1 = 2156250 / Local1 + } + Return ((Local1 << 8) | Local0) + } + + // Temperature names + Method (NTMP, 0, Serialized) { + Return (Package() { + "CPU temp", + }) + } + + // Get temperature + Method (GTMP, 1, Serialized) { + Local0 = 0; + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.TMP1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.TMP2 + } + } + Return (Local0) + } } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 6e42e533b3b..1d4614161c6 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -49,6 +49,7 @@ #include #include #include +#include #include #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ @@ -71,9 +72,9 @@ enum coreboot_acpi_ids { enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, DRTM, + RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, DRTM, /* Additional proprietary tables used by coreboot */ - VFCT, NHLT, SPMI + VFCT, NHLT, SPMI, CRAT }; /* RSDP (Root System Description Pointer) */ @@ -257,6 +258,48 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __packed acpi_madt_t; +/* + * LPIT (Low Power Idle Table) + * Conforms to "Intel Low Power S0 Idle" specification, rev 002 from July 2017. + */ +typedef struct acpi_lpit { + acpi_header_t header; +} __packed acpi_lpit_t; + +/* LPIT: LPI descriptor flags */ +typedef struct acpi_lpi_flags { + uint32_t disabled : 1; + uint32_t counter_not_available : 1; + uint32_t reserved : 30; +} __packed acpi_lpi_desc_flags_t; + +/* LPIT: LPI descriptor types */ +enum acpi_lpi_desc_type { + ACPI_LPI_DESC_TYPE_NATIVE_CSTATE = 0x00, + /* type >= 1 reserved */ +}; + +/* LPIT: LPI descriptor header */ +typedef struct acpi_lpi_desc_hdr { + uint32_t type; + uint32_t length; + uint16_t uid; + uint16_t reserved; +} __packed acpi_lpi_desc_hdr_t; + +#define ACPI_LPIT_CTR_FREQ_TSC 0 + +/* LPIT: Native C-state instruction based LPI structure */ +typedef struct acpi_lpi_desc_ncst { + acpi_lpi_desc_hdr_t header; + acpi_lpi_desc_flags_t flags; + acpi_addr_t entry_trigger; /* Entry trigger C-state */ + uint32_t min_residency; /* Minimum residency or "break-even" in microseconds */ + uint32_t max_latency; /* Worst case exit latency in microseconds */ + acpi_addr_t residency_counter; + uint64_t counter_frequency; /* Frequency in cycles per second - 0 means TSC freq */ +} __packed acpi_lpi_desc_ncst_t; + /* VFCT image header */ typedef struct acpi_vfct_image_hdr { u32 PCIBus; @@ -307,6 +350,14 @@ typedef struct acpi_ivrs { struct acpi_ivrs_ivhd ivhd; } __packed acpi_ivrs_t; +/* CRAT (Component Resource Affinity Table Structure) */ +struct acpi_crat_header { + acpi_header_t header; + uint32_t total_entries; + uint16_t num_nodes; + uint8_t reserved[6]; +} __packed; + /* IVHD Type 11h IOMMU Attributes */ typedef struct ivhd11_iommu_attr { uint32_t reserved1 : 13; @@ -955,9 +1006,13 @@ void arch_fill_fadt(acpi_fadt_t *fadt); void soc_fill_fadt(acpi_fadt_t *fadt); void mainboard_fill_fadt(acpi_fadt_t *fadt); +void acpi_fill_gnvs(void); + void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); +unsigned long acpi_fill_lpit(unsigned long current); + /* These can be used by the target port. */ u8 acpi_checksum(u8 *table, u32 length); @@ -1008,6 +1063,10 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); +void acpi_create_crat(struct acpi_crat_header *crat, + unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, + unsigned long current)); + void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(const struct device *device, unsigned long start, acpi_rsdp_t *rsdp); @@ -1057,11 +1116,13 @@ void acpi_write_hest(acpi_hest_t *hest, unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +void acpi_create_lpit(acpi_lpit_t *lpit); +unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid); + /* For ACPI S3 support. */ void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); -int acpi_handoff_wakeup_s3(void); /* ACPI_Sn assignments are defined to always equal the sleep state numbers */ enum { @@ -1117,7 +1178,7 @@ static inline int acpi_is_wakeup_s3(void) if (ENV_ROMSTAGE_OR_BEFORE) return (acpi_get_sleep_type() == ACPI_S3); - return acpi_handoff_wakeup_s3(); + return romstage_handoff_is_resume(); } static inline uintptr_t acpi_align_current(uintptr_t current) diff --git a/src/include/acpi/acpi_crat.h b/src/include/acpi/acpi_crat.h new file mode 100644 index 00000000000..b6ae1d64b6f --- /dev/null +++ b/src/include/acpi/acpi_crat.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ACPI_CRAT_H__ +#define __ACPI_CRAT_H__ + +enum crat_entry_type { + CRAT_HSA_PROC_UNIT_TYPE, + CRAT_MEMORY_TYPE, + CRAT_CACHE_TYPE, + CRAT_TLB_TYPE, + CRAT_FPU_TYPE, + CRAT_IO_TYPE, + CRAT_MAX_TYPE, +}; + +#define CRAT_HSA_PR_FLAG_EN_SHFT 0 +#define CRAT_HSA_PR_FLAG_EN (0x1 << CRAT_HSA_PR_FLAG_EN_SHFT) +#define CRAT_HSA_PR_FLAG_HOT_PLUG_SHFT 1 +#define CRAT_HSA_PR_FLAG_HOT_PLUG (0x1 << CRAT_HSA_PR_FLAG_HOT_PLUG_SHFT) +#define CRAT_HSA_PR_FLAG_CPU_PRES_SHFT 2 +#define CRAT_HSA_PR_FLAG_CPU_PRES (0x1 << CRAT_HSA_PR_FLAG_CPU_PRES_SHFT) +#define CRAT_HSA_PR_FLAG_GPU_PRES_SHFT 3 +#define CRAT_HSA_PR_FLAG_GPU_PRES (0x1 << CRAT_HSA_PR_FLAG_GPU_PRES_SHFT) +#define CRAT_HSA_PR_FLAG_CRAT_HSAMMU_SHFT 4 +#define CRAT_HSA_PR_FLAG_CRAT_HSAMMU (0x1 << CRAT_HSA_PR_FLAG_CRAT_HSAMMU_SHFT) +#define CRAT_HSA_PR_FLAG_VAL_LIM_SHFT 5 +#define CRAT_HSA_PR_FLAG_VAL_LIM (0x7 << CRAT_HSA_PR_FLAG_VAL_LIM_SHFT) +#define CRAT_HSA_PR_FLAG_ATOM_OPS_SHFT 8 +#define CRAT_HSA_PR_FLAG_ATOM_OPS (0x3 << CRAT_HSA_PR_FLAG_ATOM_OPS_SHFT) +#define CRAT_HSA_PR_FLAG_SMT_CAPS_SHFT 10 +#define CRAT_HSA_PR_FLAG_SMT_CAPS (0x3 << CRAT_HSA_PR_FLAG_SMT_CAPS_SHFT) + +/* CRAT HSA Processing Unit Affinity Structure */ +struct crat_hsa_processing_unit { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proximity_node; + uint32_t processor_id_low; + uint16_t num_cpu_cores; + uint16_t num_simd_cores; + uint16_t max_waves_simd; + uint16_t io_count; + uint16_t hsa_capability; + uint16_t lds_size_in_kb; + uint8_t wave_front_size; + uint8_t num_shader_banks; + uint16_t uengine_identifier; + uint8_t num_arrays; + uint8_t num_cu_per_array; + uint8_t num_simd_per_cu; + uint8_t max_slots_scratch_cu; + uint8_t reserved1[4]; +} __packed; + +#define CRAT_L1_CACHE 1 +#define CRAT_L2_CACHE 2 +#define CRAT_L3_CACHE 3 + +#define CRAT_MEM_FLAG_EN_SHFT 0 +#define CRAT_MEM_FLAG_EN (0x1 << CRAT_MEM_FLAG_EN_SHFT) +#define CRAT_MEM_FLAG_HOT_PLUG_SHFT 1 +#define CRAT_MEM_FLAG_HOT_PLUG (0x1 << CRAT_MEM_FLAG_HOT_PLUG_SHFT) +#define CRAT_MEM_FLAG_NV_SHFT 2 +#define CRAT_MEM_FLAG_NV (0x1 << CRAT_MEM_FLAG_NV_SHFT) +#define CRAT_MEM_FLAG_ATOM_OPS_SHFT 3 +#define CRAT_MEM_FLAG_ATOM_OPS (0x3 << CRAT_MEM_FLAG_ATOM_OPS_SHFT) + +/* CRAT Memory Affinity Structure */ +struct crat_memory { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proximity_domain; + uint32_t base_address_low; + uint32_t base_address_high; + uint32_t length_low; + uint32_t length_high; + uint32_t width; + uint8_t reserved1[8]; +} __packed; + +#define CRAT_CACHE_FLAG_EN_SHFT 0 +#define CRAT_CACHE_FLAG_EN (0x1 << CRAT_CACHE_FLAG_EN_SHFT) +#define CRAT_CACHE_FLAG_DATA_CACHE_SHFT 1 +#define CRAT_CACHE_FLAG_DATA_CACHE (0x1 << CRAT_CACHE_FLAG_DATA_CACHE_SHFT) +#define CRAT_CACHE_FLAG_INSTR_CACHE_SHFT 2 +#define CRAT_CACHE_FLAG_INSTR_CACHE (0x1 << CRAT_CACHE_FLAG_INSTR_CACHE_SHFT) +#define CRAT_CACHE_FLAG_CPU_CACHE_SHFT 3 +#define CRAT_CACHE_FLAG_CPU_CACHE (0x1 << CRAT_CACHE_FLAG_CPU_CACHE_SHFT) +#define CRAT_CACHE_FLAG_SIMD_CACHE_SHFT 4 +#define CRAT_CACHE_FLAG_SIMD_CACHE (0x1 << CRAT_CACHE_FLAG_SIMD_CACHE_SHFT) +#define CRAT_CACHE_FLAG_GDS_SHFT 5 +#define CRAT_CACHE_FLAG_GDS (0x1 << CRAT_CACHE_FLAG_GDS_SHFT) +#define CRAT_CACHE_FLAG_ATOMIC_OPS_SHFT 6 +#define CRAT_CACHE_FLAG_ATOMIC_OPS (0x1 << CRAT_CACHE_FLAG_ATOMIC_OPS_SHFT) + +/* CRAT Cache Affinity Structure */ +struct crat_cache { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proc_id_low; + uint8_t sibling_map[32]; + uint32_t cache_size; + uint8_t cache_level; + uint8_t lines_per_tag; + uint16_t cache_line_size; + uint8_t associativity; + uint8_t cache_properties; + uint16_t cache_latency; + uint8_t reserved1[8]; +} __packed; + +enum tlb_type { + tlb_2m, + tlb_4k, + tlb_1g, + tlb_type_max, +}; + +#define CRAT_TLB_FLAG_EN_SHFT 0 +#define CRAT_TLB_FLAG_EN (0x1 << CRAT_TLB_FLAG_EN_SHFT) +#define CRAT_TLB_FLAG_DATA_TLB_SHFT 1 +#define CRAT_TLB_FLAG_DATA_TLB (0x1 << CRAT_TLB_FLAG_DATA_TLB_SHFT) +#define CRAT_TLB_FLAG_INSTR_TLB_SHFT 2 +#define CRAT_TLB_FLAG_INSTR_TLB (0x1 << CRAT_TLB_FLAG_INSTR_TLB_SHFT) +#define CRAT_TLB_FLAG_CPU_TLB_SHFT 3 +#define CRAT_TLB_FLAG_CPU_TLB (0x1 << CRAT_TLB_FLAG_CPU_TLB_SHFT) +#define CRAT_TLB_FLAG_SIMD_TLB_SHFT 4 +#define CRAT_TLB_FLAG_SIMD_TLB (0x1 << CRAT_TLB_FLAG_SIMD_TLB_SHFT) +#define CRAT_TLB_FLAG_4K_BASE_256_SHFT 5 +#define CRAT_TLB_FLAG_4K_BASE_256 (0x1 << CRAT_TLB_FLAG_4K_BASE_256_SHFT) +#define CRAT_TLB_FLAG_2MB_BASE_256_SHFT 7 +#define CRAT_TLB_FLAG_2MB_BASE_256 (0x1 << CRAT_TLB_FLAG_2MB_BASE_256_SHFT) +#define CRAT_TLB_FLAG_1GB_BASE_256_SHFT 9 +#define CRAT_TLB_FLAG_1GB_BASE_256 (0x1 << CRAT_TLB_FLAG_1GB_BASE_256_SHFT) + +/* CRAT TLB Affinity Structure */ +struct crat_tlb { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proc_id_low; + uint8_t sibling_map[32]; + uint32_t tlb_level; + uint8_t data_tlb_2mb_assoc; + uint8_t data_tlb_2mb_size; + uint8_t instr_tlb_2mb_assoc; + uint8_t instr_tlb_2mb_size; + uint8_t data_tlb_4k_assoc; + uint8_t data_tlb_4k_size; + uint8_t instr_tlb_4k_assoc; + uint8_t instr_tlb_4k_size; + uint8_t data_tlb_1g_assoc; + uint8_t data_tlb_1g_size; + uint8_t instr_tlb_1g_assoc; + uint8_t instr_tlb_1g_size; + uint8_t reserved1[4]; +} __packed; + +#define CRAT_FPU_FLAG_EN_SHFT 0 +#define CRAT_FPU_FLAG_EN (0x1 << CRAT_TLB_FLAG_EN_SHFT) + +/* CRAT FPU Affinity Structure */ +struct crat_fpu { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proc_id_low; + uint8_t sibling_map[32]; + uint32_t fpu_size; + uint8_t reserved1[16]; +} __packed; + +#define CRAT_IO_FLAG_EN_SHFT 0 +#define CRAT_IO_FLAG_EN (0x1 << CRAT_IO_FLAG_EN_SHFT) +#define CRAT_IO_FLAG_COHER_SHFT 1 +#define CRAT_IO_FLAG_COHER (0x1 << CRAT_IO_FLAG_COHER_SHFT) + +/* CRAT IO Affinity Structure */ +struct crat_io { + uint8_t type; + uint8_t length; + uint16_t reserved; + uint32_t flags; + uint32_t proximity_domain_from; + uint32_t proximity_domain_to; + uint8_t io_type; + uint8_t version_major; + uint16_t version_minor; + uint32_t minimum_latency; + uint32_t maximum_latency; + uint32_t minimum_bandwidth; + uint32_t maximum_bandwidth; + uint32_t recommended_transfer_size; + uint8_t reserved1[24]; +} __packed; + +#endif /* __ACPI_CRAT_H__ */ diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index 6173fa168be..936a922827a 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -5,32 +5,23 @@ #include +void acpi_create_gnvs(void); +#if CONFIG(ACPI_SOC_NVS) void *acpi_get_gnvs(void); -void *gnvs_get_or_create(void); -void acpi_inject_nvsa(void); - -void gnvs_assign_chromeos(void); - -/* Platform code must implement these. */ -size_t gnvs_size_of_array(void); -uint32_t *gnvs_cbmc_ptr(void); -void *gnvs_chromeos_ptr(void); +#else +static inline void *acpi_get_gnvs(void) { return NULL; } +#endif -/* - * Creates acpi gnvs and adds it to the DSDT table. - * GNVS creation is chipset specific and is done in soc specific acpi.c file. - */ -struct device; -void southbridge_inject_dsdt(const struct device *device); +void gnvs_assign_chromeos(void *gnvs_section); +void gnvs_set_ecfw_rw(void); /* - * This function populates the gnvs structure in acpi table. + * These functions populate the gnvs structure in acpi table. * Defined as weak in common acpi as gnvs structure definition is * chipset specific. */ struct global_nvs; - -void acpi_create_gnvs(struct global_nvs *gnvs); -void acpi_init_gnvs(struct global_nvs *gnvs); +void soc_fill_gnvs(struct global_nvs *gnvs); +void mainboard_fill_gnvs(struct global_nvs *gnvs); #endif diff --git a/src/include/acpi/acpi_pm.h b/src/include/acpi/acpi_pm.h new file mode 100644 index 00000000000..48342a3ac87 --- /dev/null +++ b/src/include/acpi/acpi_pm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ACPI_PM_H +#define ACPI_PM_H + +struct chipset_power_state; +struct chipset_power_state *acpi_get_pm_state(void); +int acpi_pm_state_for_elog(const struct chipset_power_state **ps); +int acpi_pm_state_for_rtc(const struct chipset_power_state **ps); +int acpi_pm_state_for_wake(const struct chipset_power_state **ps); + +#endif diff --git a/src/include/cpu/amd/cpuid.h b/src/include/cpu/amd/cpuid.h new file mode 100644 index 00000000000..b593562a099 --- /dev/null +++ b/src/include/cpu/amd/cpuid.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file applies to AMD64 products. + * The definitions come from the AMD64 Programmers Manual vol2 + * Revision 3.30 and/or the device's BKDG. + */ + +#ifndef CPU_AMD_CPUID_H +#define CPU_AMD_CPUID_H + +#define CPUID_L1_TLB_CACHE_IDS 0x80000005 +/* Fn0x80000005_EAX */ +#define L1_DAT_TLB_2M4M_ASSOC_SHFT 24 +#define L1_DAT_TLB_2M4M_ASSOC_MASK (0xff << L1_DAT_TLB_2M4M_ASSOC_SHFT) +#define L1_DAT_TLB_2M4M_SIZE_SHFT 16 +#define L1_DAT_TLB_2M4M_SIZE_MASK (0xff << L1_DAT_TLB_2M4M_SIZE_SHFT) +#define L1_INST_TLB_2M4M_ASSOC_SHFT 8 +#define L1_INST_TLB_2M4M_ASSOC_MASK (0xff << L1_INST_TLB_2M4M_ASSOC_SHFT) +#define L1_INST_TLB_2M4M_SIZE_SHFT 0 +#define L1_INST_TLB_2M4M_SIZE_MASK (0xff << L1_INST_TLB_2M4M_SIZE_SHFT) +/* Fn0x80000005_EBX */ +#define L1_DAT_TLB_4K_ASSOC_SHFT 24 +#define L1_DAT_TLB_4K_ASSOC_MASK (0xff << L1_DAT_TLB_4K_ASSOC_SHFT) +#define L1_DAT_TLB_4K_SIZE_SHFT 16 +#define L1_DAT_TLB_4K_SIZE_MASK (0xff << L1_DAT_TLB_4K_SIZE_SHFT) +#define L1_INST_TLB_4K_ASSOC_SHFT 8 +#define L1_INST_TLB_4K_ASSOC_MASK (0xff << L1_INST_TLB_4K_ASSOC_SHFT) +#define L1_INST_TLB_4K_SIZE_SHFT 0 +#define L1_INST_TLB_4K_SIZE_MASK (0xff << L1_INST_TLB_4K_SIZE_SHFT) +/* Fn0x80000005_ECX */ +#define L1_DC_SIZE_SHFT 24 +#define L1_DC_SIZE_MASK (0xff << L1_DC_SIZE_SHFT) +#define L1_DC_ASSOC_SHFT 16 +#define L1_DC_ASSOC_MASK (0xff << L1_DC_ASSOC_SHFT) +#define L1_DC_LINE_TAG_SHFT 8 +#define L1_DC_LINE_TAG_MASK (0xff << L1_DC_LINE_TAG_SHFT) +#define L1_DC_LINE_SIZE_SHFT 0 +#define L1_DC_LINE_SIZE_MASK (0xff << L1_DC_LINE_SIZE_SHFT) +/* Fn0x80000005_EDX */ +#define L1_IC_SIZE_SHFT 24 +#define L1_IC_SIZE_MASK (0xff << L1_IC_SIZE_SHFT) +#define L1_IC_ASSOC_SHFT 16 +#define L1_IC_ASSOC_MASK (0xff << L1_IC_ASSOC_SHFT) +#define L1_IC_LINE_TAG_SHFT 8 +#define L1_IC_LINE_TAG_MASK (0xff << L1_IC_LINE_TAG_SHFT) +#define L1_IC_LINE_SIZE_SHFT 0 +#define L1_IC_LINE_SIZE_MASK (0xff << L1_IC_LINE_SIZE_SHFT) + +#define CPUID_L2_L3_CACHE_L2_TLB_IDS 0x80000006 +/* Fn0x80000006_EAX */ +#define L2_DAT_TLB_2M4M_ASSOC_SHFT 28 +#define L2_DAT_TLB_2M4M_ASSOC_MASK (0xf << L2_DAT_TLB_2M4M_ASSOC_SHFT) +#define L2_DAT_TLB_2M4M_SIZE_SHFT 16 +#define L2_DAT_TLB_2M4M_SIZE_MASK (0xfff << L2_DAT_TLB_2M4M_SIZE_SHFT) +#define L2_INST_TLB_2M4M_ASSOC_SHFT 12 +#define L2_INST_TLB_2M4M_ASSOC_MASK (0xf << L2_INST_TLB_2M4M_ASSOC_SHFT) +#define L2_INST_TLB_2M4M_SIZE_SHFT 0 +#define L2_INST_TLB_2M4M_SIZE_MASK (0xfff << L2_INST_TLB_2M4M_SIZE_SHFT) +/*Fn0x80000006_EBX */ +#define L2_DAT_TLB_4K_ASSOC_SHFT 28 +#define L2_DAT_TLB_4K_ASSOC_MASK (0xf << L2_DAT_TLB_4K_ASSOC_SHFT) +#define L2_DAT_TLB_4K_SIZE_SHFT 16 +#define L2_DAT_TLB_4K_SIZE_MASK (0xfff << L2_DAT_TLB_4K_SIZE_SHFT) +#define L2_INST_TLB_4K_ASSOC_SHFT 12 +#define L2_INST_TLB_4K_ASSOC_MASK (0xf << L2_INST_TLB_4K_ASSOC_SHFT) +#define L2_INST_TLB_4K_SIZE_SHFT 0 +#define L2_INST_TLB_4K_SIZE_MASK (0xfff << L2_INST_TLB_4K_SIZE_SHFT) +/* Fn0x80000006_ECX */ +#define L2_DC_SIZE_SHFT 16 +#define L2_DC_SIZE_MASK (0xffff << L2_DC_SIZE_SHFT) +#define L2_DC_ASSOC_SHFT 12 +#define L2_DC_ASSOC_MASK (0xf << L2_DC_ASSOC_SHFT) +#define L2_DC_LINE_TAG_SHFT 8 +#define L2_DC_LINE_TAG_MASK (0xf << L2_DC_LINE_TAG_SHFT) +#define L2_DC_LINE_SIZE_SHFT 0 +#define L2_DC_LINE_SIZE_MASK (0xff << L2_DC_LINE_SIZE_SHFT) +/* Fn0x80000006_EDX */ +#define L3_DC_SIZE_SHFT 18 +#define L3_DC_SIZE_MASK (0x3fff << L3_DC_SIZE_SHFT) +#define L3_DC_ASSOC_SHFT 12 +#define L3_DC_ASSOC_MASK (0xf << L3_DC_ASSOC_SHFT) +#define L3_DC_LINE_TAG_SHFT 8 +#define L3_DC_LINE_TAG_MASK (0xf << L3_DC_LINE_TAG_SHFT) +#define L3_DC_LINE_SIZE_SHFT 0 +#define L3_DC_LINE_SIZE_MASK (0xff << L3_DC_LINE_SIZE_SHFT) + +#define CPUID_EXT_PM 0x80000007 +#define CPUID_MODEL 1 + +#define CPUID_TLB_L1L2_1G_IDS 0x80000019 +/* Fn0x80000019_EAX */ +#define L1_DAT_TLB_1G_ASSOC_SHFT 28 +#define L1_DAT_TLB_1G_ASSOC_MASK (0xf << L1_DAT_TLB_1G_ASSOC_SHFT) +#define L1_DAT_TLB_1G_SIZE_SHFT 16 +#define L1_DAT_TLB_1G_SIZE_MASK (0xfff << L1_DAT_TLB_1G_SIZE_SHFT) +#define L1_INST_TLB_1G_ASSOC_SHFT 12 +#define L1_INST_TLB_1G_ASSOC_MASK (0xf << L1_INST_TLB_1G_ASSOC_SHFT) +#define L1_INST_TLB_1G_SIZE_SHFT 0 +#define L1_INST_TLB_1G_SIZE_MASK (0xfff << L1_INST_TLB_1G_SIZE_SHFT) +/* Fn0x80000019_EBX */ +#define L2_DAT_TLB_1G_ASSOC_SHFT 28 +#define L2_DAT_TLB_1G_ASSOC_MASK (0xf << L2_DAT_TLB_1G_ASSOC_SHFT) +#define L2_DAT_TLB_1G_SIZE_SHFT 16 +#define L2_DAT_TLB_1G_SIZE_MASK (0xfff << L2_DAT_TLB_1G_SIZE_SHFT) +#define L2_INST_TLB_1G_ASSOC_SHFT 12 +#define L2_INST_TLB_1G_ASSOC_MASK (0xf << L2_INST_TLB_1G_ASSOC_SHFT) +#define L2_INST_TLB_1G_SIZE_SHFT 0 +#define L2_INST_TLB_1G_SIZE_MASK (0xfff << L2_INST_TLB_1G_SIZE_SHFT) + +#define CPUID_CACHE_PROPS 0x8000001D +#define CACHE_PROPS_0 0 +#define CACHE_PROPS_1 1 +#define CACHE_PROPS_2 2 +#define CACHE_PROPS_3 3 +#define NUM_SHARE_CACHE_SHFT 14 +#define NUM_SHARE_CACHE_MASK (0xfff << NUM_SHARE_CACHE_SHFT) +#define CACHE_INCLUSIVE_SHFT 1 +#define CACHE_INCLUSIVE_MASK (0x1 << CACHE_INCLUSIVE_SHFT) + +#define CPUID_EBX_CORE_ID 0x8000001E +#define CPUID_EBX_THREADS_SHIFT 8 +#define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT) + +#endif /* CPU_AMD_CPUID_H */ diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index f9e7b2033dc..78676de2660 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -10,11 +10,6 @@ #include -#define CPUID_EXT_PM 0x80000007 -#define CPUID_MODEL 1 -#define CPUID_EBX_CORE_ID 0x8000001E -#define CPUID_EBX_THREADS_SHIFT 8 -#define CPUID_EBX_THREADS_MASK (0xFF << CPUID_EBX_THREADS_SHIFT) #define MC4_MISC0 0x00000413 #define MC4_MISC1 0xC0000408 #define MC4_MISC2 0xC0000409 diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index da0f0bb68d1..935ac30096a 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -14,4 +14,6 @@ #define MSR_PLATFORM_INFO 0xce +#define MSR_PKG_C10_RESIDENCY 0x632 + #endif /* CPU_INTEL_MSR_H */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 6dfe08df1a3..91068428404 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -22,11 +22,10 @@ #define APM_CNT_PST_CONTROL 0x80 #define APM_CNT_ACPI_DISABLE 0x1e #define APM_CNT_ACPI_ENABLE 0xe1 -#define APM_CNT_MBI_UPDATE 0xeb -#define APM_CNT_GNVS_UPDATE 0xea #define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed #define APM_CNT_ELOG_GSMI 0xef diff --git a/src/include/device/device.h b/src/include/device/device.h index 786a640f39e..1fc5e62bdc9 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -6,6 +6,7 @@ #include #include #include +#include #include struct fw_config; @@ -16,6 +17,7 @@ struct smbus_bus_operations; struct pnp_mode_ops; struct spi_bus_operations; struct usb_bus_operations; +struct gpio_operations; /* Chip operations */ struct chip_operations { @@ -62,6 +64,7 @@ struct device_operations { const struct spi_bus_operations *ops_spi_bus; const struct smbus_bus_operations *ops_smbus_bus; const struct pnp_mode_ops *ops_pnp_mode; + const struct gpio_operations *ops_gpio; }; /** @@ -385,11 +388,11 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev) devtree_die(); } -/* config_of_soc() either returns a non-NULL pointer or dies in the config_of() call. */ -static inline DEVTREE_CONST void *config_of_soc(void) -{ - return config_of(pcidev_on_root(0, 0)); -} +/* + * Returns pointer to config structure of root device (B:D:F = 0:00:0) defined by + * sconfig in static.{h/c}. + */ +#define config_of_soc() __pci_0_00_0_config void enable_static_device(struct device *dev); void enable_static_devices(struct device *bus); diff --git a/src/include/device/gpio.h b/src/include/device/gpio.h new file mode 100644 index 00000000000..67975b3c450 --- /dev/null +++ b/src/include/device/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DEVICE_GPIO_H__ +#define __DEVICE_GPIO_H__ + +#include + +struct gpio_operations { + int (*get)(uint32_t gpio); + void (*set)(uint32_t gpio, int value); + void (*input_pulldown)(uint32_t gpio); + void (*input_pullup)(uint32_t gpio); + void (*input)(uint32_t gpio); + void (*output)(uint32_t gpio, int value); +}; + +/* Helper for getting gpio operations from a device */ +const struct gpio_operations *dev_get_gpio_ops(struct device *dev); + +#endif /* __DEVICE_GPIO_H__ */ diff --git a/src/include/device/path.h b/src/include/device/path.h index 5690badc4cf..0cdb997726d 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -21,6 +21,7 @@ enum device_path_type { DEVICE_PATH_MMIO, DEVICE_PATH_ESPI, DEVICE_PATH_LPC, + DEVICE_PATH_GPIO, /* * When adding path types to this table, please also update the @@ -46,6 +47,7 @@ enum device_path_type { "DEVICE_PATH_MMIO", \ "DEVICE_PATH_ESPI", \ "DEVICE_PATH_LPC", \ + "DEVICE_PATH_GPIO", \ } struct domain_path { @@ -116,6 +118,10 @@ struct lpc_path { uintptr_t addr; }; +struct gpio_path { + unsigned int id; +}; + struct device_path { enum device_path_type type; union { @@ -134,6 +140,7 @@ struct device_path { struct mmio_path mmio; struct espi_path espi; struct lpc_path lpc; + struct gpio_path gpio; }; }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8ac29c5436c..45f3092243a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2959,6 +2959,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32 0x5181 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33 0x5182 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 @@ -2991,6 +2992,38 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29 0x7a9d #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30 0x7a9e #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_0 0x5480 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_1 0x5481 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_2 0x5482 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_3 0x5483 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_4 0x5484 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_5 0x5485 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_6 0x5486 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_7 0x5487 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_8 0x5488 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_9 0x5489 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_10 0x548a +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_11 0x548b +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_12 0x548c +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_13 0x548d +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_14 0x548e +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_15 0x548f +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_16 0x5490 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_17 0x5491 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_18 0x5482 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_19 0x5493 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_20 0x5494 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_21 0x5495 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_22 0x5496 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_23 0x5497 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_24 0x5498 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_25 0x5499 +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_26 0x549a +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_27 0x549b +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_28 0x548c +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3286,6 +3319,17 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27 0x7aca #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP1 0x54b8 +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP2 0x54b9 +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP3 0x54ba +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP4 0x54bb +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP5 0x54bc +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP6 0x54bd +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP7 0x54be +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP8 0x54bf +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP9 0x54b0 +#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP10 0x54b1 + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 #define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 @@ -3352,6 +3396,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_SATA_4 0x7ae5 #define PCI_DEVICE_ID_INTEL_ADP_S_SATA_5 0x7ae6 #define PCI_DEVICE_ID_INTEL_ADP_S_SATA_6 0x7ae7 +#define PCI_DEVICE_ID_INTEL_ADP_M_SATA_1 0x54d3 +#define PCI_DEVICE_ID_INTEL_ADP_M_SATA_2 0x54d7 +#define PCI_DEVICE_ID_INTEL_ADP_M_SATA_3 0x282a /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3371,6 +3418,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 #define PCI_DEVICE_ID_INTEL_ADP_P_PMC 0x7a21 #define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 +#define PCI_DEVICE_ID_INTEL_ADP_M_PMC 0x54a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3465,6 +3513,13 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_I2C4 0x7afc #define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd +#define PCI_DEVICE_ID_INTEL_ADP_M_I2C0 0x54e8 +#define PCI_DEVICE_ID_INTEL_ADP_M_I2C1 0x54e9 +#define PCI_DEVICE_ID_INTEL_ADP_M_I2C2 0x54ea +#define PCI_DEVICE_ID_INTEL_ADP_M_I2C3 0x54eb +#define PCI_DEVICE_ID_INTEL_ADP_M_I2C4 0x54c5 +#define PCI_DEVICE_ID_INTEL_ADP_M_I2C5 0x54c6 + /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DEVICE_ID_INTEL_LPT_LP_UART1 0x9c64 @@ -3526,6 +3581,11 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_UART5 0x7ade #define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf +#define PCI_DEVICE_ID_INTEL_ADP_M_UART0 0x54a8 +#define PCI_DEVICE_ID_INTEL_ADP_M_UART1 0x54a9 +#define PCI_DEVICE_ID_INTEL_ADP_M_UART2 0x54c7 +#define PCI_DEVICE_ID_INTEL_ADP_M_UART3 0x54da + /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1 0x9c66 @@ -3535,7 +3595,7 @@ #define PCI_DEVICE_ID_INTEL_APL_SPI0 0x5ac2 #define PCI_DEVICE_ID_INTEL_APL_SPI1 0x5ac4 #define PCI_DEVICE_ID_INTEL_APL_SPI2 0x5ac6 -#define PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI 0x5a96 +#define PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI 0x5a96 #define PCI_DEVICE_ID_INTEL_GLK_SPI0 0x31c2 #define PCI_DEVICE_ID_INTEL_GLK_SPI1 0x31c4 #define PCI_DEVICE_ID_INTEL_GLK_SPI2 0x31c6 @@ -3596,6 +3656,11 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_SPI5 0x7aee #define PCI_DEVICE_ID_INTEL_ADP_S_SPI6 0x7aef +#define PCI_DEVICE_ID_INTEL_ADP_M_HWSEQ_SPI 0x54a4 +#define PCI_DEVICE_ID_INTEL_ADP_M_SPI0 0x54aa +#define PCI_DEVICE_ID_INTEL_ADP_M_SPI1 0x54ab +#define PCI_DEVICE_ID_INTEL_ADP_M_SPI2 0x54fb + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3845,6 +3910,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 +#define PCI_DEVICE_ID_INTEL_ADP_M_SMBUS 0x54a3 /* Intel EHCI device IDs */ #define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -3873,6 +3939,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI 0x461e +#define PCI_DEVICE_ID_INTEL_ADP_M_XHCI 0x54ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3892,6 +3959,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0 #define PCI_DEVICE_ID_INTEL_ADP_P_P2SB 0x7a20 #define PCI_DEVICE_ID_INTEL_ADP_S_P2SB 0x7aa0 +#define PCI_DEVICE_ID_INTEL_ADP_M_P2SB 0x54a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3906,6 +3974,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def #define PCI_DEVICE_ID_INTEL_ADP_P_SRAM 0x7a6f #define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 +#define PCI_DEVICE_ID_INTEL_ADP_M_SRAM 0x54ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20 @@ -3936,6 +4005,14 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8 0x7ad7 #define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_1 0x54c8 +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_2 0x54c9 +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_3 0x54ca +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_4 0x54cb +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_5 0x54cc +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_6 0x54cd +#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_7 0x54ce + /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DEVICE_ID_INTEL_LPT_LP_MEI 0x9c3a @@ -3970,6 +4047,10 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_CSE1 0x7ae9 #define PCI_DEVICE_ID_INTEL_ADP_S_CSE2 0x7aec #define PCI_DEVICE_ID_INTEL_ADP_S_CSE3 0x7aed +#define PCI_DEVICE_ID_INTEL_ADP_M_CSE0 0x54e0 +#define PCI_DEVICE_ID_INTEL_ADP_M_CSE1 0x54e1 +#define PCI_DEVICE_ID_INTEL_ADP_M_CSE2 0x54e4 +#define PCI_DEVICE_ID_INTEL_ADP_M_CSE3 0x54e5 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3987,6 +4068,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 #define PCI_DEVICE_ID_INTEL_ADP_TCSS_XDCI 0x460e +#define PCI_DEVICE_ID_INTEL_ADP_M_XDCI 0x54ee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 635876b902c..955eac29acc 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -38,31 +38,32 @@ struct pnp_info { #define PNP_SKIP_FUNCTION 0xffff u16 function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; -#define PNP_IO0 0x000001 -#define PNP_IO1 0x000002 -#define PNP_IO2 0x000004 -#define PNP_IO3 0x000008 -#define PNP_IRQ0 0x000010 -#define PNP_IRQ1 0x000020 -#define PNP_DRQ0 0x000040 -#define PNP_DRQ1 0x000080 -#define PNP_EN 0x000100 -#define PNP_MSC0 0x000200 -#define PNP_MSC1 0x000400 -#define PNP_MSC2 0x000800 -#define PNP_MSC3 0x001000 -#define PNP_MSC4 0x002000 -#define PNP_MSC5 0x004000 -#define PNP_MSC6 0x008000 -#define PNP_MSC7 0x010000 -#define PNP_MSC8 0x020000 -#define PNP_MSC9 0x040000 -#define PNP_MSCA 0x080000 -#define PNP_MSCB 0x100000 -#define PNP_MSCC 0x200000 -#define PNP_MSCD 0x400000 -#define PNP_MSCE 0x800000 - u16 io0, io1, io2, io3; +#define PNP_IO0 0x0000001 +#define PNP_IO1 0x0000002 +#define PNP_IO2 0x0000004 +#define PNP_IO3 0x0000008 +#define PNP_IO4 0x0000010 +#define PNP_IRQ0 0x0000020 +#define PNP_IRQ1 0x0000040 +#define PNP_DRQ0 0x0000080 +#define PNP_DRQ1 0x0000100 +#define PNP_EN 0x0000200 +#define PNP_MSC0 0x0000400 +#define PNP_MSC1 0x0000800 +#define PNP_MSC2 0x0001000 +#define PNP_MSC3 0x0002000 +#define PNP_MSC4 0x0004000 +#define PNP_MSC5 0x0008000 +#define PNP_MSC6 0x0010000 +#define PNP_MSC7 0x0020000 +#define PNP_MSC8 0x0040000 +#define PNP_MSC9 0x0080000 +#define PNP_MSCA 0x0100000 +#define PNP_MSCB 0x0200000 +#define PNP_MSCC 0x0400000 +#define PNP_MSCD 0x0800000 +#define PNP_MSCE 0x1000000 + u16 io0, io1, io2, io3, io4; }; struct resource *pnp_get_resource(struct device *dev, unsigned int index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, diff --git a/src/include/device/pnp_def.h b/src/include/device/pnp_def.h index 7701d842f2c..712357bb7c7 100644 --- a/src/include/device/pnp_def.h +++ b/src/include/device/pnp_def.h @@ -6,6 +6,7 @@ #define PNP_IDX_IO1 0x62 #define PNP_IDX_IO2 0x64 #define PNP_IDX_IO3 0x66 +#define PNP_IDX_IO4 0x68 #define PNP_IDX_IRQ0 0x70 #define PNP_IDX_IRQ1 0x72 #define PNP_IDX_DRQ0 0x74 diff --git a/src/include/edid.h b/src/include/edid.h index 691cf76b97f..b2d6aa2cab7 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -41,7 +41,7 @@ struct edid_mode { /* structure for communicating EDID information from a raw EDID block to * higher level functions. * The size of the data types is not critical, so we leave them as - * unsigned int. We can move more into into this struct as needed. + * unsigned int. We can move more into this struct as needed. */ #define EDID_ASCII_STRING_LENGTH 13 diff --git a/src/include/lib.h b/src/include/lib.h index 5c6eef2a709..359626c9648 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -12,9 +12,9 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn); /* Defined in src/lib/ramtest.c */ /* Assumption is 32-bit addressable UC memory. */ -void ram_check(unsigned long start, unsigned long stop); -int ram_check_nodie(unsigned long start, unsigned long stop); -int ram_check_noprint_nodie(unsigned long start, unsigned long stop); +void ram_check(uintptr_t start); +int ram_check_nodie(uintptr_t start); +int ram_check_noprint_nodie(uintptr_t start); void quick_ram_check_or_die(uintptr_t dst); /* Defined in primitive_memtest.c */ diff --git a/src/include/memrange.h b/src/include/memrange.h index 80db5985ed2..a8a8de9c2d3 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -52,7 +52,7 @@ static inline resource_t range_entry_end(const struct range_entry *r) return r->end + 1; } -/* Return size of of memory range. */ +/* Return size of memory range. */ static inline resource_t range_entry_size(const struct range_entry *r) { return r->end - r->begin + 1; diff --git a/src/include/smbios.h b/src/include/smbios.h index e451d17ef8c..d8ac4caff28 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -55,6 +55,9 @@ const char *smbios_chassis_version(void); const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); +/* This string could be filled late in payload. */ +void smbios_type0_bios_version(uintptr_t address); + void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo); diff --git a/src/include/types.h b/src/include/types.h index 2d10ae483af..cbdb67a0cad 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -18,4 +18,6 @@ #define BIT(x) (1ul << (x)) #endif +#define BITS_PER_BYTE 8 + #endif /* __TYPES_H */ diff --git a/src/lib/Kconfig.cbfs_verification b/src/lib/Kconfig.cbfs_verification index 4e2ed8cf01f..a28df1ff6da 100644 --- a/src/lib/Kconfig.cbfs_verification +++ b/src/lib/Kconfig.cbfs_verification @@ -1,7 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later # -# This file is part of the coreboot project. -# # This file is sourced from src/security/Kconfig for menuconfig convenience. #menu "CBFS verification" # TODO: enable once it works diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9212981883d..1871015e17f 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -26,13 +27,6 @@ #if CONFIG(USE_OPTION_TABLE) #include #endif -#if CONFIG(CHROMEOS) -#if CONFIG(HAVE_ACPI_TABLES) -#include -#endif -#include -#include -#endif #if CONFIG(PLATFORM_USES_FSP2_0) #include #else @@ -158,7 +152,6 @@ void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, gpios->size += table_size; } -#if CONFIG(CHROMEOS) static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; @@ -197,6 +190,7 @@ static void lb_gpios(struct lb_header *header) } } +#if CONFIG(CHROMEOS) static void lb_vbnv(struct lb_header *header) { #if CONFIG(PC80_SYSTEM) @@ -494,10 +488,11 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Record our framebuffer */ lb_framebuffer(head); -#if CONFIG(CHROMEOS) /* Record our GPIO settings (ChromeOS specific) */ - lb_gpios(head); + if (CONFIG(CHROMEOS)) + lb_gpios(head); +#if CONFIG(CHROMEOS) /* pass along VBNV offsets in CMOS */ lb_vbnv(head); #endif @@ -518,15 +513,17 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Add board-specific table entries, if any. */ lb_board(head); -#if CONFIG(CHROMEOS_RAMOOPS) - lb_ramoops(head); -#endif + if (CONFIG(CHROMEOS_RAMOOPS)) + lb_ramoops(head); lb_boot_media_params(head); /* Board configuration information (including straps) */ lb_board_config(head); + if (CONFIG(TPM_PPI)) + lb_tpm_ppi(head); + /* Add architecture records. */ lb_arch_add_records(head); diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index cb81d3248c5..1fd8874047c 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -1346,7 +1346,7 @@ static int dt_fixup_all_externals(struct device_tree *tree, if (!path) return -1; - /* Find node the label pointed to to figure out its phandle. */ + /* Find node the label pointed to figure out its phandle. */ struct device_tree_node *node = dt_find_node_by_path(tree, path, NULL, NULL, 0); if (!node) diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 712cd0f5257..7e8aa951809 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -48,10 +48,17 @@ fb_add_framebuffer_info_ex(const struct lb_framebuffer *fb) bpp_mask = fb->blue_mask_size + fb->green_mask_size + fb->red_mask_size + fb->reserved_mask_size; - if (fb->bits_per_pixel != bpp_mask) { - printk(BIOS_ERR, "%s: BPP=%d and channel bit mask=%d doesn't match." - " This is a driver bug.\n", __func__, fb->bits_per_pixel, bpp_mask); + if (bpp_mask > fb->bits_per_pixel) { + printk(BIOS_ERR, + "%s: channel bit mask=%d is greater than BPP=%d ." + " This is a driver bug. Framebuffer is invalid.\n", + __func__, bpp_mask, fb->bits_per_pixel); return NULL; + } else if (bpp_mask != fb->bits_per_pixel) { + printk(BIOS_WARNING, + "%s: channel bit mask=%d and BPP=%d don't match." + " This is a driver bug.\n", + __func__, bpp_mask, fb->bits_per_pixel); } info = fb_new_framebuffer_info(); diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 173ee971922..895a9422223 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -447,6 +448,10 @@ void main(void) acpi_is_wakeup_s3(); threads_initialize(); + /* Initialise GNVS early. */ + if (CONFIG(ACPI_SOC_NVS)) + acpi_create_gnvs(); + /* Schedule the static boot state entries. */ boot_state_schedule_static_entries(); diff --git a/src/lib/program.ld b/src/lib/program.ld index d419ab60b1d..3eebd6cc228 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -13,6 +13,9 @@ .text . : { _program = .; _text = .; + *(.init._start); + *(.init); + *(.init.*); *(.text._start); *(.text.stage_entry); KEEP(*(.metadata_hash_anchor)); diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index c6cd7a4a1d7..224393f6f09 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -67,7 +67,7 @@ static inline void test_pattern(unsigned short int idx, * * @param start System memory offset, aligned to 128bytes */ -static int ram_bitset_nodie(unsigned long start) +static int ram_bitset_nodie(uintptr_t start) { unsigned long addr, value, value2; unsigned short int idx; @@ -117,7 +117,7 @@ static int ram_bitset_nodie(unsigned long start) } -void ram_check(unsigned long start, unsigned long stop) +void ram_check(uintptr_t start) { /* * This is much more of a "Is my DRAM properly configured?" @@ -131,7 +131,7 @@ void ram_check(unsigned long start, unsigned long stop) } -int ram_check_nodie(unsigned long start, unsigned long stop) +int ram_check_nodie(uintptr_t start) { int ret; /* @@ -146,7 +146,7 @@ int ram_check_nodie(unsigned long start, unsigned long stop) return ret; } -int ram_check_noprint_nodie(unsigned long start, unsigned long stop) +int ram_check_noprint_nodie(uintptr_t start) { unsigned long addr, value, value2; unsigned short int idx; diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index 0a7a822f7b2..faa2bc9f04f 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -55,12 +55,23 @@ int romstage_handoff_init(int is_s3_resume) int romstage_handoff_is_resume(void) { + static int once, s3_resume; struct romstage_handoff *handoff; - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (once) + return s3_resume; + /* Only try evaluate handoff once for s3 resume state. */ + once = 1; + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); if (handoff == NULL) return 0; - return handoff->s3_resume; + s3_resume = handoff->s3_resume; + if (s3_resume) + printk(BIOS_DEBUG, "S3 Resume\n"); + else + printk(BIOS_DEBUG, "Normal boot\n"); + + return s3_resume; } diff --git a/src/mainboard/51nb/Kconfig b/src/mainboard/51nb/Kconfig index 5124fdb411a..d0efbc61c14 100644 --- a/src/mainboard/51nb/Kconfig +++ b/src/mainboard/51nb/Kconfig @@ -12,7 +12,6 @@ endchoice source "src/mainboard/51nb/*/Kconfig" config MAINBOARD_VENDOR - string "Mainboard Vendor" default "51NB" endif # VENDOR_51NB diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig index 824e8b36083..efd21da26e1 100644 --- a/src/mainboard/51nb/x210/Kconfig +++ b/src/mainboard/51nb/x210/Kconfig @@ -28,10 +28,6 @@ config MAINBOARD_DIR string default "51nb/x210" -config MAX_CPUS - int - default 8 - config VGA_BIOS_ID string default "8086,5917" diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl index e703ba1936b..e57753888c3 100644 --- a/src/mainboard/51nb/x210/acpi/graphics.asl +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) Method (_DOS, 1, NotSerialized) { /* We never do anything in firmware, so _DOS is a noop */ diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index b51c73c4861..433bc22fbbe 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -1,11 +1,13 @@ chip soc/intel/skylake # Enable Panel as eDP and configure power delays - register "gpu_pp_up_delay_ms" = "210" # T3 - register "gpu_pp_down_delay_ms" = "500" # T10 - register "gpu_pp_cycle_delay_ms" = "5000" # T12 - register "gpu_pp_backlight_on_delay_ms" = "1" # T7 - register "gpu_pp_backlight_off_delay_ms" = "200" # T9 + register "panel_cfg" = "{ + .up_delay_ms = 210, // T3 + .down_delay_ms = 500, // T10 + .cycle_delay_ms = 5000, // T12 + .backlight_on_delay_ms = 1, // T7 + .backlight_off_delay_ms = 200, // T9 + }" # Enable deep Sx states register "deep_s3_enable_ac" = "1" diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c index 1485b674392..67e7b1a0b24 100644 --- a/src/mainboard/acer/g43t-am3/acpi_tables.c +++ b/src/mainboard/acer/g43t-am3/acpi_tables.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ } diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index cb3237c624f..ce8a4982632 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -4,7 +4,9 @@ if BOARD_AMD_MAJOLICA config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_16384 select SOC_AMD_CEZANNE + select AMD_SOC_CONSOLE_UART config FMDFILE string @@ -16,6 +18,12 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "MAJOLICA" +config AMD_FWM_POSITION_INDEX + int + default 4 + help + TODO: might need to be adapted for better placement of files in cbfs + config MAJOLICA_HAVE_MCHP_FW bool "Have Microchip EC firmware?" default n diff --git a/src/mainboard/amd/majolica/Makefile.inc b/src/mainboard/amd/majolica/Makefile.inc index ce3119c65d9..56eb6f26c4a 100644 --- a/src/mainboard/amd/majolica/Makefile.inc +++ b/src/mainboard/amd/majolica/Makefile.inc @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only -PHONY+=add_mchp_fw -INTERMEDIATE+=add_mchp_fw +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_Updatable.bin +APCB_SOURCES_68 = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_Updatable_68.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin ifeq ($(CONFIG_MAJOLICA_HAVE_MCHP_FW),y) -add_mchp_fw: $(obj)/coreboot.pre +$(call add_intermediate, add_mchp_fw) $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MAJOLICA_MCHP_FW_FILE) --fill-upward else files_added:: warn_no_mchp diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index c1d68fa58b4..7c9387a144f 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO - select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN select BOARD_ROMSIZE_KB_16384 if BOARD_AMD_CEREME select AZALIA_PLUGIN_SUPPORT diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 448c12ad993..bff7e6385a8 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -16,12 +16,9 @@ else # CONFIG_BOARD_AMD_CEREME APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_cereme.bin endif -PHONY+=add_mchp_fw -INTERMEDIATE+=add_mchp_fw - ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) -add_mchp_fw: $(obj)/coreboot.pre +$(call add_intermediate, add_mchp_fw) $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MANDOLIN_MCHP_FW_FILE) --fill-upward else diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index b509282f8b5..6718d656a64 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -29,39 +29,19 @@ static uint8_t fch_apic_routing[0x80]; _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), "PIC and APIC FCH interrupt tables must be the same size"); -/* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - static const struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; uint8_t apic_irq_num; } mandolin_fch[] = { - { PIRQ_A, 8, 16 }, - { PIRQ_B, 10, 17 }, - { PIRQ_C, 11, 18 }, - { PIRQ_D, 12, 19 }, + { PIRQ_A, 10, PIRQ_NC }, + { PIRQ_B, 11, PIRQ_NC }, + { PIRQ_C, 12, PIRQ_NC }, + { PIRQ_D, 13, PIRQ_NC }, + { PIRQ_E, 13, PIRQ_NC }, + { PIRQ_F, 12, PIRQ_NC }, + { PIRQ_G, 11, PIRQ_NC }, + { PIRQ_H, 10, PIRQ_NC }, { PIRQ_SCI, 9, 9 }, { PIRQ_SD, PIRQ_NC, 16 }, { PIRQ_SDIO, PIRQ_NC, 16 }, @@ -100,9 +80,6 @@ static void init_tables(void) static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc index b4f8b6573a7..58198971cde 100644 --- a/src/mainboard/apple/macbook21/Makefile.inc +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -1,3 +1,5 @@ romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c + +ramstage-y += cstates.c diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl index abba5abf251..e1e33a2b3b7 100644 --- a/src/mainboard/apple/macbook21/acpi/platform.asl +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -42,14 +42,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If ((OSYS == 2001) && MPEN) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c deleted file mode 100644 index 52c2fbbec13..00000000000 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - -} diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c new file mode 100644 index 00000000000..8f295040f77 --- /dev/null +++ b/src/mainboard/apple/macbook21/cstates.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static acpi_cstate_t cst_entries[] = { + { + .ctype = 1, + .latency = 1, + .power = 1000, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, + .addrl = 0, + .addrh = 0, + } + }, + { + .ctype = 2, + .latency = 1, + .power = 500, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, + .addrl = 0x10, + .addrh = 0, + } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 447837ba54f..27d0363e4f7 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -2,47 +2,11 @@ #include #include -#include #include #include #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -static acpi_cstate_t cst_entries[] = { - { - .ctype = 1, - .latency = 1, - .power = 1000, - .resource = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 0, - .addrh = 0, - } - }, - { - .ctype = 2, - .latency = 1, - .power = 500, - .resource = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 0x10, - .addrh = 0, - } - }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - static void mainboard_init(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index d6fe4709281..8219d60a35b 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #define GPE_EC_SCI 12 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index f6b01769c9e..50507586ee1 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -15,12 +15,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x13121312" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 846f0797bc5..5ec2f71212f 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 2fc7c8844c4..af69d5872e8 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -15,12 +15,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x00000000" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c index eed290d500f..230584ee4a1 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi_tables.c +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 024d1f0e1f2..43a65f81975 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,13 +5,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index 9eef15936a6..566cad75bbf 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index d923c30d3c3..cec5db84135 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -29,14 +29,6 @@ config MAINBOARD_PART_NUMBER string default "H110M" -config MAX_CPUS - int - default 8 - -config DEVICETREE - string - default "devicetree.cb" - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 @@ -45,9 +37,4 @@ config DIMM_SPD_SIZE int default 512 #DDR4 -# This is overridden if CMOS is used for configuration values. -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - endif diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 909c0504120..4cb873585fa 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -2,10 +2,6 @@ chip soc/intel/skylake - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_WAKE_PIN" register "eist_enable" = "1" @@ -38,88 +34,6 @@ chip soc/intel/skylake # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # VR Settings Configuration - #+----------------+-------+-------+-------------+-------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax* | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------+ - # * - is set automatically in the vr_config.c - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(4), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0 ,\ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), \ - .psi2threshold = VR_CFG_AMP(5), \ - .psi3threshold = VR_CFG_AMP(1), \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x0, \ - .voltage_limit = 1520 \ - }" - - # PCH UART, SPI, I2C - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - # PL2 override 91W register "power_limits_config" = "{ .tdp_pl2_override = 91, @@ -138,7 +52,6 @@ chip soc/intel/skylake device pci 01.0 on # PEG subsystemid 0x1849 0x1901 register "Peg0MaxLinkWidth" = "Peg0_x16" - register "SkipExtGfxScan" = "0" # Configure PCIe clockgen in PCH register "PcieRpClkReqSupport[0]" = "1" @@ -210,10 +123,6 @@ chip soc/intel/skylake [1] = 1, \ [2] = 1, \ [3] = 1, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ }" end device pci 19.0 off end # UART #2 @@ -380,7 +289,6 @@ chip soc/intel/skylake device pci 1f.2 on end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaVcType" = "Vc1" - register "DspEnable" = "0" end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c deleted file mode 100644 index 8ec5b118c58..00000000000 --- a/src/mainboard/asrock/h81m-hds/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 45119f9476e..7b08af96d86 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -5,13 +5,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c deleted file mode 100644 index 852b0b4ae74..00000000000 --- a/src/mainboard/asus/h61m-cs/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/h61m-cs/devicetree.cb b/src/mainboard/asus/h61m-cs/devicetree.cb index ea2a5d8c1a5..60f8191f38d 100644 --- a/src/mainboard/asus/h61m-cs/devicetree.cb +++ b/src/mainboard/asus/h61m-cs/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c deleted file mode 100644 index 14a79f87fb4..00000000000 --- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index a0b631261b3..7b901494dbc 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index a0dc96e7c56..ff3bbca46e5 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_512 select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_GMA_HAVE_VBT - select NO_CBFS_MCACHE config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c deleted file mode 100644 index 496d4190c6f..00000000000 --- a/src/mainboard/asus/p5gc-mx/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c index 65db55f5cba..1ac09572f16 100644 --- a/src/mainboard/asus/p5qc/acpi_tables.c +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -1,13 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig index 12dc0d9761d..e68b92e3ffe 100644 --- a/src/mainboard/asus/p5ql-em/Kconfig +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -4,7 +4,6 @@ if BOARD_ASUS_P5QL_EM config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc index 097c9f9aa94..4a5e88d0229 100644 --- a/src/mainboard/asus/p5ql-em/Makefile.inc +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -5,4 +5,6 @@ bootblock-y += early_init.c romstage-y += gpio.c romstage-y += early_init.c +ramstage-y += cstates.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c index 4f59ed01f87..1ac09572f16 100644 --- a/src/mainboard/asus/p5ql-em/acpi_tables.c +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -1,20 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ -} - -/* TODO: Could work... */ -int get_cst_entries(acpi_cstate_t **entries) -{ - return 0; } diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c new file mode 100644 index 00000000000..791f78e38db --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* TODO: Could work... */ +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c index 9eef15936a6..566cad75bbf 100644 --- a/src/mainboard/asus/p5qpl-am/acpi_tables.c +++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c deleted file mode 100644 index 14a79f87fb4..00000000000 --- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index 4a29baa579b..eddca8144c4 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb index 757c5ccde88..317f9cc22b2 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index b318573b40f..969169c139e 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c index e401b656fa9..a4204f1c54c 100644 --- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* critical temp that will shutdown the pc == 95C degrees */ gnvs->tcrt = 95; diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb index 90feb7ac6c5..1d1a244b9f6 100644 --- a/src/mainboard/asus/p8z77-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 33ff9615225..0fc6dc15b70 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/biostar/am1ml/acpi/ide.asl b/src/mainboard/biostar/am1ml/acpi/ide.asl index 56f760de40c..766fcb31405 100644 --- a/src/mainboard/biostar/am1ml/acpi/ide.asl +++ b/src/mainboard/biostar/am1ml/acpi/ide.asl @@ -52,11 +52,11 @@ OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ Method(GTTM, 1) /* get total time*/ { - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) + Local0 = Arg0 & 0x0F /* Recovery Width */ + Local0++ + Local1 = Arg0 >> 4 /* Command Width */ + Local1++ + Return(30 * (Local0 + Local1)) } Device(PRID) @@ -78,32 +78,32 @@ Device(PRID) CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ + If (PPCR & 0x01) { /* primary PIO control */ Return(OTBF) } /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) + BFFG |= 0x1A /* save total time of primary PIO master timing to PIO spd0 */ - Store(GTTM(PPTM), PSD0) + PSD0 = GTTM (PPTM) /* save total time of primary PIO slave Timing to PIO spd1 */ - Store(GTTM(PPTS), PSD1) + PSD1 = GTTM (PPTS) - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) + If (PDCR & 0x01) { /* It's under UDMA mode */ + BFFG |= 0x01 + DSD0 = DerefOf(UDTT [PDMM]) } Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing, DmaSpd0 */ } - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) + If (PDCR & 0x02) { /* It's under UDMA mode */ + BFFG |= 0x04 + DSD1 = DerefOf(UDTT [PDSM]) } Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing, DmaSpd0 */ } Return(OTBF) /* out buffer */ @@ -124,35 +124,35 @@ Device(PRID) CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0) + PPMM = Local0 % 5 /* Primary PIO master Mode */ + Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0) + PPSM = Local1 % 5 /* Primary PIO slave Mode */ - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */ + PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */ - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) + If (BFFG & 0x01) { /* Drive 0 is under UDMA mode */ + Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0) + PDMM = Local0 % 7 + PDCR |= 0x01 } Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) + If (DSD0 != 0xFFFFFFFF) { + Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0) + PMTM = DerefOf(MDRT [Local0]) } } - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) + If (BFFG & 0x04) { /* Drive 1 is under UDMA mode */ + Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0) + PDSM = Local0 % 7 + PDCR |= 0x02 } Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) + If (DSD1 != 0xFFFFFFFF) { + Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0) + PMTS = DerefOf(MDRT [Local0]) } } /* Return(INBF) */ @@ -172,21 +172,19 @@ Device(PRID) CreateByteField(CMBF, 12, CMDB) CreateByteField(CMBF, 19, CMDC) - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) + CMDA = 0xA0 + CMDB = 0xA0 + CMDC = 0xA0 - Or(PPMM, 0x08, POMD) + POMD = PPMM | 0x08 - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) + If (PDCR & 0x01) { + DMMD = PDMM | 0x40 } Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) + Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0) + If (Local0 < 3) { + DMMD = Local0 | 0x20 } } Return(CMBF) @@ -208,21 +206,19 @@ Device(PRID) CreateByteField(CMBF, 12, CMDB) CreateByteField(CMBF, 19, CMDC) - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) + CMDA = 0xB0 + CMDB = 0xB0 + CMDC = 0xB0 - Or(PPSM, 0x08, POMD) + POMD = PPSM | 0x08 - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) + If (PDCR & 0x02) { + DMMD = PDSM | 0x40 } Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) + Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0) + If (Local0 < 3) { + DMMD = Local0 | 0x20 } } Return(CMBF) diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index d1a4ee72c7c..31b93748b8b 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -33,7 +33,7 @@ Device(PMRY) Device(PMST) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P0IS,0)) { + if (P0IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -46,7 +46,7 @@ Device(PMRY) { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P1IS,0)) { + if (P1IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -68,7 +68,7 @@ Device(SEDY) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P2IS,0)) { + if (P2IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -81,7 +81,7 @@ Device(SEDY) { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P3IS,0)) { + if (P3IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -95,35 +95,35 @@ Device(SEDY) Scope(\_GPE) { Method(_L1F,0x0,NotSerialized) { if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { + if (\_SB.P0IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) + \_SB.P0PR = 1 } if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { + if (\_SB.P1IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) + \_SB.P1PR = 1 } if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { + if (\_SB.P2IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) + \_SB.P2PR = 1 } if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { + if (\_SB.P3IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) + \_SB.P3PR = 1 } } } diff --git a/src/mainboard/biostar/am1ml/acpi/sio.asl b/src/mainboard/biostar/am1ml/acpi/sio.asl index ef0bca59f4e..bf4ff3daed6 100644 --- a/src/mainboard/biostar/am1ml/acpi/sio.asl +++ b/src/mainboard/biostar/am1ml/acpi/sio.asl @@ -26,17 +26,17 @@ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) /* Enter the 8728 Config */ Method (EPNP) { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) + SIOI = 0x87 + SIOI = 0x01 + SIOI = 0x55 + SIOI = 0x55 } /* Exit the 8728 Config */ Method (XPNP) { - Store (0x02, SIOI) - Store (0x02, SIOD) + SIOI = 0x02 + SIOD = 0x02 } /* @@ -46,20 +46,20 @@ Method (XPNP) Method (SIOS, 1) { /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) + If (Arg0 < 0x05) { EPNP() /* DBGO("8728F\n") */ - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ + LDN = 0x4 + ACTR = 1 /* Enable EC */ /* - Store (0x4, LDN) - Store (0x04, APC4) + LDN = 0x4 + APC4 = 0x04 */ /* falling edge. which mode? Not sure. */ - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + LDN = 0x4 + APC1 = 0x08 /* clear PME status, Use 0x18 for mouse & KBD */ + LDN = 0x4 + APC0 = 0x08 /* enable PME, Use 0x18 for mouse & KBD */ XPNP() } } diff --git a/src/mainboard/biostar/am1ml/acpi/sleep.asl b/src/mainboard/biostar/am1ml/acpi/sleep.asl index 47dd1460b17..fc26c306d9e 100644 --- a/src/mainboard/biostar/am1ml/acpi/sleep.asl +++ b/src/mainboard/biostar/am1ml/acpi/sleep.asl @@ -30,9 +30,9 @@ Method(_PTS, 1) { /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -56,7 +56,7 @@ Method(\_WAK, 1) { /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ - Store(1,USBS) + USBS = 1 \_SB.AWAK(Arg0) diff --git a/src/mainboard/biostar/am1ml/acpi/superio.asl b/src/mainboard/biostar/am1ml/acpi/superio.asl index a4eda2bb2e2..03683b36910 100644 --- a/src/mainboard/biostar/am1ml/acpi/superio.asl +++ b/src/mainboard/biostar/am1ml/acpi/superio.asl @@ -12,8 +12,8 @@ Device (PS2M) { IRQNoFlags () {12} }) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) @@ -24,8 +24,8 @@ Device (PS2M) { Device (PS2K) { Name (_HID, EisaId ("PNP0303")) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) @@ -42,8 +42,8 @@ Device (COM1) { Name (_HID, EISAID ("PNP0501")) Name (_UID, 1) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) @@ -65,8 +65,8 @@ Device (LPT1) { Name (_HID, EISAID ("PNP0400")) Name (_UID, 1) Method (_STA, 0, NotSerialized) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { + Local0 = FLG0 & 0x04 + If (Local0 == 0x04) { Return (0x0F) } Else { Return (0x00) diff --git a/src/mainboard/biostar/th61-itx/acpi_tables.c b/src/mainboard/biostar/th61-itx/acpi_tables.c deleted file mode 100644 index 852b0b4ae74..00000000000 --- a/src/mainboard/biostar/th61-itx/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 2329bb23e31..118a58eab43 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/bostentech/gbyt4/acpi_tables.c b/src/mainboard/bostentech/gbyt4/acpi_tables.c index 7445fb057ee..dc0d7a2873b 100644 --- a/src/mainboard/bostentech/gbyt4/acpi_tables.c +++ b/src/mainboard/bostentech/gbyt4/acpi_tables.c @@ -5,10 +5,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 3f6f6753aaf..5653fb4365f 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -1,18 +1,15 @@ -if BOARD_CLEVO_L140CU - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_CLEVO_CMLU_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_HID - select EC_SYSTEM76_EC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_SMI_HANDLER - select HAVE_SPD_IN_CBFS - select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO @@ -21,6 +18,14 @@ config BOARD_SPECIFIC_OPTIONS select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config BOARD_CLEVO_L140CU_OPTIONS + bool + select BOARD_CLEVO_CMLU_COMMON + select EC_SYSTEM76_EC + select HAVE_SPD_IN_CBFS + +if BOARD_CLEVO_CMLU_COMMON + config MAINBOARD_DIR string default "clevo/cml-u" @@ -61,10 +66,6 @@ config DIMM_SPD_SIZE int default 512 -config VGA_BIOS_FILE - string - default "pci8086,9b41.rom" - config VGA_BIOS_ID string default "8086,9b41" diff --git a/src/mainboard/clevo/cml-u/Kconfig.name b/src/mainboard/clevo/cml-u/Kconfig.name index f8f22cc531a..92555ffd956 100644 --- a/src/mainboard/clevo/cml-u/Kconfig.name +++ b/src/mainboard/clevo/cml-u/Kconfig.name @@ -2,3 +2,4 @@ comment "Comet Lake U" config BOARD_CLEVO_L140CU bool "L140CU / L141CU" + select BOARD_CLEVO_L140CU_OPTIONS diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc index b69c2579664..213e62f1eeb 100644 --- a/src/mainboard/clevo/cml-u/Makefile.inc +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -6,5 +6,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c index 389a7a986dd..0b5965a9050 100644 --- a/src/mainboard/clevo/cml-u/bootblock.c +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -4,7 +4,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); } diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl index 7555246700c..05e297b2066 100644 --- a/src/mainboard/clevo/cml-u/dsdt.asl +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -18,6 +18,7 @@ DefinitionBlock( { #include #include + #include } #include diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 3329f638be8..4a93065e767 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -65,7 +65,17 @@ chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1401 inherit device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_pwm_hz = 1000, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + }" + end device pci 04.0 on # SA Thermal device register "Device4Enable" = "1" end @@ -97,7 +107,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 15 on end diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads b/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads new file mode 100644 index 00000000000..8402b39a949 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c index d5744ef3dbb..e567ef79d12 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c @@ -62,7 +62,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B2, UP_20K), /* CNVI_WAKE# (UART_WAKE# in M.2 spec; unused) */ - PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),/* GPP_B3 (touchpad interrupt) */ + PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST), /* GPP_B3 (touchpad interrupt) */ PAD_NC(GPP_B4, UP_20K), PAD_NC(GPP_B5, UP_20K), PAD_NC(GPP_B6, UP_20K), diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index ed0600a0181..a99f9c6b232 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_CLEVO_N130WU - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_CLEVO_KBLU_COMMON + def_bool n select BOARD_ROMSIZE_KB_8192 select EC_ACPI select HAVE_ACPI_RESUME @@ -21,6 +19,12 @@ config BOARD_SPECIFIC_OPTIONS select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config BOARD_CLEVO_N130WU_OPTIONS + bool + select BOARD_CLEVO_KBLU_COMMON + +if BOARD_CLEVO_KBLU_COMMON + config VBOOT select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN @@ -55,10 +59,6 @@ config FMDFILE # default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB # default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name index 5a6f699c679..05a49cda7c7 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig.name +++ b/src/mainboard/clevo/kbl-u/Kconfig.name @@ -4,3 +4,4 @@ comment "Kaby Lake U" config BOARD_CLEVO_N130WU bool "N130WU / N131WU" + select BOARD_CLEVO_N130WU_OPTIONS diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index a223b7e5295..29f57bd6432 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -1,13 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" # T3 - register "gpu_pp_down_delay_ms" = " 0" # T10 - register "gpu_pp_cycle_delay_ms" = "500" # T12 - register "gpu_pp_backlight_on_delay_ms" = " 50" # T7 - register "gpu_pp_backlight_off_delay_ms" = " 0" # T9 - - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, // T3 + .down_delay_ms = 0, // T10 + .cycle_delay_ms = 500, // T12 + .backlight_on_delay_ms = 50, // T7 + .backlight_off_delay_ms = 0, // T9 + .backlight_pwm_hz = 200, + }" # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" @@ -46,9 +47,6 @@ chip soc/intel/skylake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem - device pci 05.0 off end # Imaging Unit - device pci 08.0 on end # Gaussian Mixture Model - device pci 13.0 off end # Sensor Hub device pci 14.0 on # USB xHCI register "SsicPortEnable" = "0" # USB2 @@ -65,20 +63,10 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end - device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera - device pci 15.0 off end # I2C0 - device pci 15.1 off end # I2C1 - device pci 15.2 off end # I2C2 - device pci 15.3 off end # I2C3 device pci 16.0 on # Management Engine Interface 1 register "HeciEnabled" = "1" end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA register "SataSalpSupport" = "0" # Ports @@ -87,8 +75,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[2]" = "1" end device pci 19.0 on end # UART 2 - device pci 19.1 off end # I2C5 - device pci 19.2 off end # I2C4 device pci 1c.0 on # PCI Express Port 1 device pci 00.0 on end # x4 TBT register "PcieRpEnable[0]" = "1" @@ -99,9 +85,6 @@ chip soc/intel/skylake register "PcieRpLtrEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" end - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 on # PCI Express Port 5 device pci 00.0 on end # x1 LAN register "PcieRpEnable[4]" = "1" @@ -119,8 +102,6 @@ chip soc/intel/skylake register "PcieRpLtrEnable[5]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 device pci 00.0 on end # x4 M.2/M (J_SSD1) register "PcieRpEnable[8]" = "1" @@ -130,16 +111,6 @@ chip soc/intel/skylake register "PcieRpLtrEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 off end # UART 0 - device pci 1e.1 off end # UART 1 - device pci 1e.2 off end # GSPI 0 - device pci 1e.3 off end # GSPI 1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" @@ -159,7 +130,5 @@ chip soc/intel/skylake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - device pci 1f.7 off end # Trace Hub end end diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c index f9051870d65..e8e26579998 100644 --- a/src/mainboard/compulab/intense_pc/acpi_tables.c +++ b/src/mainboard/compulab/intense_pc/acpi_tables.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include /* FIXME: check this function. */ -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 414c410b10e..b48dae31697 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -8,12 +8,9 @@ chip northbridge/intel/sandybridge # FIXME: check gfx device cpu_cluster 0x0 on chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/dell/optiplex_9010/Makefile.inc b/src/mainboard/dell/optiplex_9010/Makefile.inc index 7a8a68423a8..964a7af97af 100644 --- a/src/mainboard/dell/optiplex_9010/Makefile.inc +++ b/src/mainboard/dell/optiplex_9010/Makefile.inc @@ -1,7 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c - bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/dell/optiplex_9010/acpi_tables.c b/src/mainboard/dell/optiplex_9010/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/dell/optiplex_9010/acpi_tables.c +++ b/src/mainboard/dell/optiplex_9010/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index 6a21d20b74b..c805b1f35c9 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -1,12 +1,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" register "tcc_offset" = "5" # TCC of 95C device lapic 0 on end device lapic 0xacac off end diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 62c23ca5afe..1b618718b30 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -27,6 +27,15 @@ config VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP +if ARCH_BOOTBLOCK_X86_64 +# Need to install page tables in DRAM as the virtual MMU has problems translating paging +# request when the page table resides in emulated ROM. This causes undefined behaviour +# when handling data requests, as well as fetching and decoding instructions +# Real hardware didn't show any problems until now. +config ARCH_X86_64_PGTBL_LOC + default 0x8000 +endif + if VBOOT config VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 929743ac462..bc97554442d 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -28,8 +28,19 @@ static void qemu_nb_init(struct device *dev) pci_assign_irqs(pcidev_on_root(i, 0), qemu_i440fx_irqs + (i % 4)); } +static void qemu_nb_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ + reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, + (6 * 0x1000) / KiB); + } +} + static struct device_operations nb_operations = { - .read_resources = pci_dev_read_resources, + .read_resources = qemu_nb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = qemu_nb_init, diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index b30b3816c5e..75ab352b694 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -4,6 +4,7 @@ #include #include #include +#include #include "memory.h" #include "fw_cfg.h" @@ -50,6 +51,11 @@ void *cbmem_top_chipset(void) top = (uintptr_t)qemu_get_memory_size() * 1024; } + if (CONFIG(BOARD_EMULATION_QEMU_X86_Q35)) { + size_t smm_size; + smm_region(&top, &smm_size); + } + return (void *)top; } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index edd2b2c6d6a..d88d0da7fff 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -32,6 +32,15 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB +if ARCH_BOOTBLOCK_X86_64 +# Need to install page tables in DRAM as the virtual MMU has problems translating paging +# request when the page table resides in emulated ROM. This causes undefined behaviour +# when handling data requests, as well as fetching and decoding instructions +# Real hardware didn't show any problems until now. +config ARCH_X86_64_PGTBL_LOC + default 0x8000 +endif + if VBOOT config VBOOT_SLOTS_RW_A diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index ddcf6da0627..4bd91f02174 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -2,17 +2,21 @@ bootblock-y += bootblock.c romstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memmap.c +romstage-y += memmap.c postcar-y += ../qemu-i440fx/fw_cfg.c postcar-y += ../qemu-i440fx/memmap.c postcar-y += ../qemu-i440fx/exit_car.S +postcar-y += memmap.c ramstage-y += ../qemu-i440fx/fw_cfg.c ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c +ramstage-y += memmap.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += memmap.c diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 104e5d0883d..08ddf57223c 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -11,17 +10,6 @@ #include "../qemu-i440fx/fw_cfg.h" #include "../qemu-i440fx/acpi.h" -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; -} void mainboard_fill_fadt(acpi_fadt_t *fadt) { diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index d329e5affbe..c88874f4f2a 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -44,6 +44,12 @@ static void qemu_nb_read_resources(struct device *dev) /* reserve mmconfig */ fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10, IORESOURCE_RESERVE); + + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */ + reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB, + (6 * 0x1000) / KiB); + } } diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c new file mode 100644 index 00000000000..a8b14337149 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include + +#define EXT_TSEG_MBYTES 0x50 + +#define SMRAMC 0x9d +#define G_SMRAME (1 << 3) +#define D_LCK (1 << 4) +#define D_CLS (1 << 5) +#define D_OPEN (1 << 6) +#define ESMRAMC 0x9e +#define T_EN (1 << 0) +#define TSEG_SZ_MASK (3 << 1) +#define H_SMRAME (1 << 7) + +void smm_region(uintptr_t *start, size_t *size) +{ + uint8_t esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + + switch ((esmramc & TSEG_SZ_MASK) >> 1) { + case 0: + *size = 1 * MiB; + break; + case 1: + *size = 2 * MiB; + break; + case 2: + *size = 8 * MiB; + break; + default: + *size = pci_read_config16(PCI_DEV(0, 0, 0), EXT_TSEG_MBYTES) * MiB; + } + + *start = qemu_get_memory_size() * KiB - *size; + printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB); +} diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index eda65ee1fc9..9e7ab69aac2 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_SPD_IN_CBFS config USE_VENDORCODE_ELTAN - depends on !VBOOT default y if VBOOT diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 5fe4a4260e8..7538af02313 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -6,10 +6,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index 93ce3891341..e0aed55cf00 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c deleted file mode 100644 index 496d4190c6f..00000000000 --- a/src/mainboard/foxconn/d41s/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c index 781abcce7ef..3bdb266fdac 100644 --- a/src/mainboard/foxconn/g41s-k/acpi_tables.c +++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c @@ -1,13 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 1; /* COM 1 port */ - gnvs->cmap = 1; /* COM 2 port */ - gnvs->lptp = 0; /* LPT port */ - gnvs->fdcp = 0; /* Floppy Disk Controller */ } diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index d7b642aab51..4eca3f01093 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -18,10 +18,10 @@ Scope(\_SB) { Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT) { - Return(0x1f) + If (\_SB.PCI0.LPCB.EC0.BAT) { + Return (0x1f) } Else { - Return(0x0f) + Return (0x0f) } } @@ -45,67 +45,67 @@ Scope(\_SB) { }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC0, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV0, Index(PBIF, 4)) + PBIF [1] = \_SB.PCI0.LPCB.EC0.BDC0 + PBIF [4] = \_SB.PCI0.LPCB.EC0.BDV0 - Store(\_SB.PCI0.LPCB.EC0.BFC0, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = \_SB.PCI0.LPCB.EC0.BFC0 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTYP) { - Store(NIMH, Index(PBIF, 11)) + If (\_SB.PCI0.LPCB.EC0.BTYP) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } - Return(PBIF) + Return (PBIF) } /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT) { - Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) + If (\_SB.PCI0.LPCB.EC0.BAT) { + PBST [3] = \_SB.PCI0.LPCB.EC0.BPV0 - Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, , Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) - Divide(Local3, 0x64, , Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = \_SB.PCI0.LPCB.EC0.BRC0 * 100 + Local0 = Local3 / \_SB.PCI0.LPCB.EC0.BFC0 + Local3 = \_SB.PCI0.LPCB.EC0.BFC0 * Local0 + Local0 = Local3 / 100 + Local0++ + PBST [2] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC0, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR0, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = \_SB.PCI0.LPCB.EC0.BRC0 + Local0 = \_SB.PCI0.LPCB.EC0.BPR0 + Local0 = ~Local0 & 0xFFFF + PBST [1] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CHRG) { - Store(2, Index(PBST, 0)) + If (\_SB.PCI0.LPCB.EC0.ADP) { + If (\_SB.PCI0.LPCB.EC0.CHRG) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 1 } } } - Return(PBST) + Return (PBST) } } @@ -123,10 +123,10 @@ Scope(\_SB) { Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT2) { - Return(0x1f) + If (\_SB.PCI0.LPCB.EC0.BAT2) { + Return (0x1f) } Else { - Return(0x0f) + Return (0x0f) } } @@ -150,67 +150,67 @@ Scope(\_SB) { }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC2, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV2, Index(PBIF, 4)) + PBIF [1] = \_SB.PCI0.LPCB.EC0.BDC2 + PBIF [4] = \_SB.PCI0.LPCB.EC0.BDV2 - Store(\_SB.PCI0.LPCB.EC0.BFC2, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = \_SB.PCI0.LPCB.EC0.BFC2 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTY2) { - Store(NIMH, Index(PBIF, 11)) + If (\_SB.PCI0.LPCB.EC0.BTY2) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } - Return(PBIF) + Return (PBIF) } /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT2) { - Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) + If (\_SB.PCI0.LPCB.EC0.BAT2) { + PBST [3] = \_SB.PCI0.LPCB.EC0.BPV2 - Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, , Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) - Divide(Local3, 0x64, , Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = \_SB.PCI0.LPCB.EC0.BRC2 * 100 + Local0 = Local3 / \_SB.PCI0.LPCB.EC0.BRC2 + Local3 = \_SB.PCI0.LPCB.EC0.BFC2 * Local0 + Local0 = Local3 / 100 + Local0++ + PBST [2] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC2, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR2, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = \_SB.PCI0.LPCB.EC0.BRC2 + Local0 = \_SB.PCI0.LPCB.EC0.BPR2 + Local0 = ~Local0 & 0xFFFF + PBST [1] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CRG2) { - Store(2, Index(PBST, 0)) + If (\_SB.PCI0.LPCB.EC0.ADP) { + If (\_SB.PCI0.LPCB.EC0.CRG2) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 1 } } } - Return(PBST) + Return (PBST) } } @@ -223,12 +223,12 @@ Scope(\_SB) { Name (ACST, 0x00) Method (_PSR, 0) { - If(ACFG) { - Store(ACST, Local0) + If (ACFG) { + Local0 = ACST } Else { - Store(\_SB.PCI0.LPCB.EC0.ADP, Local0) - Store(Local0, ACST) - Store(1, ACFG) + Local0 = \_SB.PCI0.LPCB.EC0.ADP + ACST = Local0 + ACFG = 1 } Sleep(120) Return (Local0) diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 1e8d64eac5c..2de388a74bc 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -3,19 +3,10 @@ #include #include #include -#include #include -#include #include "mainboard.h" -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - /* Enable COM port(s) */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x00; -} - static long acpi_create_ecdt(acpi_ecdt_t * ecdt) { /* Attention: Make sure these match the values from diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 21f4e3e21fe..e69627af5d1 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include "ec_oem.c" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index f6a99e7fdbb..9a8bf5bc902 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L select INTEL_GMA_HAVE_VBT - select NO_CBFS_MCACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c deleted file mode 100644 index 496d4190c6f..00000000000 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index 3012052a246..64f3f04bd06 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index fbc31b7788f..0c24a9db5bd 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -2,12 +2,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" # Magic APIC ID to locate this chip device lapic 0x0 on end device lapic 0xacac off end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c index f7296e14f2e..1ac09572f16 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -1,15 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->lptp = 0; /* LPT port */ - gnvs->fdcp = 0; /* Floppy Disk Controller */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c deleted file mode 100644 index 852b0b4ae74..00000000000 --- a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index cb7b9189628..d0ec09c8c14 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index a57392bc045..56a1084e814 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -15,6 +15,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_H1_AP_INT); gpio_input_pullup(GPIO_SD_CD); gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_EN_SPK_AMP, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -24,6 +25,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h index 90de583f77e..ae34d33313a 100644 --- a/src/mainboard/google/asurada/gpio.h +++ b/src/mainboard/google/asurada/gpio.h @@ -14,6 +14,8 @@ #define GPIO_SD_CD GPIO(EINT17) /* AP_EC_WARM_RST_REQ */ #define GPIO_RESET GPIO(CAM_PDN2) +/* EN_SPK */ +#define GPIO_EN_SPK_AMP GPIO(CAM_PDN1) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index f836724df64..812cb006daf 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -193,10 +193,23 @@ static void configure_sdcard(void) mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); } +static void configure_audio(void) +{ + /* Audio PWR */ + mtcmos_audio_power_on(); + + /* SoC I2S */ + gpio_set_mode(GPIO(I2S3_MCK), PAD_I2S3_MCK_FUNC_I2S3_MCK); + gpio_set_mode(GPIO(I2S3_BCK), PAD_I2S3_BCK_FUNC_I2S3_BCK); + gpio_set_mode(GPIO(I2S3_LRCK), PAD_I2S3_LRCK_FUNC_I2S3_LRCK); + gpio_set_mode(GPIO(I2S3_DO), PAD_I2S3_DO_FUNC_I2S3_DO); +} + static void mainboard_init(struct device *dev) { configure_emmc(); configure_sdcard(); + configure_audio(); setup_usb_host(); register_reset_to_bl31(); diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c index 3a97ee5393b..91ee7c074de 100644 --- a/src/mainboard/google/asurada/reset.c +++ b/src/mainboard/google/asurada/reset.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include "gpio.h" + void do_board_reset(void) { + gpio_output(GPIO_RESET, 1); } diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 8e492556a78..5301e32571b 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -58,10 +58,6 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME default "samus" if BOARD_GOOGLE_SAMUS default "" -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 7d31655177d..f642243667f 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -6,7 +6,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c +romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 746efa24836..1be0a472185 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -19,8 +19,8 @@ Scope (\_SB.PCI0.RP01) Method (_DSW, 3, NotSerialized) { - Store (BOARD_WLAN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_WLAN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl index 4be4fe5c2a5..fd05e7350fe 100644 --- a/src/mainboard/google/auron/acpi/thermal.asl +++ b/src/mainboard/google/auron/acpi/thermal.asl @@ -24,10 +24,10 @@ Scope (\_TZ) // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -53,56 +53,56 @@ Scope (\_TZ) Method (TCHK, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } Method (_TMP, 0, Serialized) { // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for EC to re-poll Sleep (1000) // Re-read temperature from EC - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) @@ -110,7 +110,7 @@ Scope (\_TZ) /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (CTL_TDP_THRESHOLD_OFF)) } Else { Return (CTOK (CTL_TDP_THRESHOLD_ON)) @@ -119,7 +119,7 @@ Scope (\_TZ) /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) } Else { Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) @@ -132,14 +132,14 @@ Scope (\_TZ) PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 /* Enable Power Limit */ \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT) @@ -147,7 +147,7 @@ Scope (\_TZ) Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 /* Disable Power Limit */ \_SB.PCI0.MCHC.CTLD () @@ -159,18 +159,18 @@ Scope (\_TZ) PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 5284cef29f0..501f54b4cf7 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -6,7 +6,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 26a53366b42..39c6554f1e2 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,13 +12,13 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - register "s0ix_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + register "s0ix_enable" = "1" + + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c deleted file mode 100644 index ed1780050ac..00000000000 --- a/src/mainboard/google/auron/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include "variant.h" - -__weak void variant_romstage_entry(struct romstage_params *rp) -{ -} - -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); - mainboard_fill_spd_data(&rp->pei_data); - -} - -void mainboard_post_raminit(struct romstage_params *rp) -{ - /* Do variant-specific init */ - variant_romstage_entry(rp); -} diff --git a/src/mainboard/google/auron/spd.c b/src/mainboard/google/auron/spd.c new file mode 100644 index 00000000000..20d7498a7be --- /dev/null +++ b/src/mainboard/google/auron/spd.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " + "density %d Mb\n", banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +void fill_spd_for_index(uint8_t spd[], unsigned int spd_index) +{ + size_t spd_file_len; + uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); + + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + memcpy(spd, spd_file + (spd_index * SPD_LEN), SPD_LEN); + + /* Make sure a valid SPD was found */ + if (spd[0] == 0) + die("Invalid SPD data."); + + mainboard_print_spd_info(spd); +} diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index 095096b27d3..ba4c58a9e1b 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -5,10 +5,14 @@ #include #include +#include int variant_smbios_data(struct device *dev, int *handle, unsigned long *current); -void variant_romstage_entry(struct romstage_params *rp); void lan_init(void); +void fill_spd_for_index(uint8_t spd[], unsigned int index); + +#define SPD_LEN 256 + #endif diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl index febaffeb251..cc26de68593 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Scope (\_SB.PCI0.I2C0) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h deleted file mode 100644 index 74e3cdffde6..00000000000 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Auron board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 81110408c14..62e42b17188 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 12a9d7cb12a..ba829d0a785 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -9,59 +9,12 @@ #include #include #include -#include +#include -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - , banks, ranks, rows, cols); - printk(BIOS_INFO, "density %d Mb\n", capmb); - - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} +/* Auron board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) @@ -73,8 +26,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; int spd_gpio[3]; int spd_index; - size_t spd_file_len; - char *spd_file; spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); @@ -88,31 +39,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } + fill_spd_for_index(pei_data->spd_data[0][0], spd_index); - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - memcpy(pei_data->spd_data[0][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); /* Index 0-2 are 4GB config with both CH0 and CH1. * Index 4-6 are 2GB config with CH0 only. */ if (spd_index > 3) pei_data->dimm_channel1_disabled = 3; else - memcpy(pei_data->spd_data[1][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); + memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN); } diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl index febaffeb251..cc26de68593 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Scope (\_SB.PCI0.I2C0) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h deleted file mode 100644 index 74e3cdffde6..00000000000 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Auron board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index eb33d433e83..174463d0b7d 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 12a9d7cb12a..ba829d0a785 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -9,59 +9,12 @@ #include #include #include -#include +#include -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - , banks, ranks, rows, cols); - printk(BIOS_INFO, "density %d Mb\n", capmb); - - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} +/* Auron board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) @@ -73,8 +26,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; int spd_gpio[3]; int spd_index; - size_t spd_file_len; - char *spd_file; spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); @@ -88,31 +39,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } + fill_spd_for_index(pei_data->spd_data[0][0], spd_index); - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - memcpy(pei_data->spd_data[0][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); /* Index 0-2 are 4GB config with both CH0 and CH1. * Index 4-6 are 2GB config with CH0 only. */ if (spd_index > 3) pei_data->dimm_channel1_disabled = 3; else - memcpy(pei_data->spd_data[1][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); + memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN); } diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index b3dc42c8ae3..4b0ac45c096 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -24,7 +24,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -59,7 +59,7 @@ Scope (\_SB.PCI0.I2C1) Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -70,8 +70,8 @@ Scope (\_SB.PCI0.I2C1) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -96,7 +96,7 @@ Scope (\_SB.PCI0.RP01) { Store (BUDDY_NIC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h b/src/mainboard/google/auron/variants/buddy/include/variant/spd.h deleted file mode 100644 index 5ebd8c233a2..00000000000 --- a/src/mainboard/google/auron/variants/buddy/include/variant/spd.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 60fb08cbf7c..0570cdca558 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -1,13 +1,22 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "s0ix_enable" = "0" + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "s0ix_enable" = "0" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c index 4dd1de6a799..9a5480e2be5 100644 --- a/src/mainboard/google/auron/variants/buddy/spd/spd.c +++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl index febaffeb251..cc26de68593 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Scope (\_SB.PCI0.I2C0) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h b/src/mainboard/google/auron/variants/gandof/include/variant/spd.h deleted file mode 100644 index 2263672e8c0..00000000000 --- a/src/mainboard/google/auron/variants/gandof/include/variant/spd.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Gandof board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index c7e2421ee83..ca5d6166590 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "500" # 50ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 50, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 12a9d7cb12a..5cd3ddcb154 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -9,59 +9,12 @@ #include #include #include -#include +#include -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - , banks, ranks, rows, cols); - printk(BIOS_INFO, "density %d Mb\n", capmb); - - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} +/* Gandof board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) @@ -73,8 +26,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; int spd_gpio[3]; int spd_index; - size_t spd_file_len; - char *spd_file; spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); @@ -88,31 +39,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } + fill_spd_for_index(pei_data->spd_data[0][0], spd_index); - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - memcpy(pei_data->spd_data[0][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); /* Index 0-2 are 4GB config with both CH0 and CH1. * Index 4-6 are 2GB config with CH0 only. */ if (spd_index > 3) pei_data->dimm_channel1_disabled = 3; else - memcpy(pei_data->spd_data[1][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); + memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN); } diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index acf2a2d2cde..b93e2c1472d 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -24,8 +24,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) return len; } -void variant_romstage_entry(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { - if (rp->power_state->prev_sleep_state != ACPI_S3) + if (!s3resume) google_chromeec_kbbacklight(75); } diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl index 76e1f2ec9fb..35f0d3c206d 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl @@ -31,17 +31,17 @@ Scope (\_SB.PCI0.I2C0) Method(_DSM, 0x4, NotSerialized) { - If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) /* I2C-HID UUID */ + If (Arg0 == ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")) /* I2C-HID UUID */ { - If (LEqual(Arg2, Zero)) /* DSM Function */ + If (Arg2 == 0) /* DSM Function */ { /* Function 0: Query function, return based on revision */ - If (LEqual(Arg1, One)) /* Arg1 DSM Revision */ + If (Arg1 == 1) /* Arg1 DSM Revision */ { /* Revision 1: Function 0 supported */ Return(Buffer(One) { 0x03 }) } - } ElseIf (LEqual(Arg2, One)) /* Function 1 : HID Function */ + } ElseIf (Arg2 == 1) /* Function 1 : HID Function */ { Return(0x0020) /* HID Descriptor Address */ } @@ -52,7 +52,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -63,8 +63,8 @@ Scope (\_SB.PCI0.I2C0) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -100,7 +100,7 @@ Scope (\_SB.PCI0.I2C1) Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -111,8 +111,8 @@ Scope (\_SB.PCI0.I2C1) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h deleted file mode 100644 index 903b60a545a..00000000000 --- a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Lulu board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 13 -#define SPD_GPIO_BIT1 9 -#define SPD_GPIO_BIT2 47 -#define SPD_GPIO_BIT3 8 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 81110408c14..62e42b17188 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -1,11 +1,13 @@ chip soc/intel/broadwell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 7, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index 905e196f7b5..d80d3c0424b 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -9,59 +9,13 @@ #include #include #include -#include +#include -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - , banks, ranks, rows, cols); - printk(BIOS_INFO, "density %d Mb\n", capmb); - - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} +/* Lulu board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 +#define SPD_GPIO_BIT3 8 /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) @@ -74,8 +28,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; int spd_gpio[4]; int spd_index; - size_t spd_file_len; - char *spd_file; spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); @@ -92,32 +44,12 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - /* CH0 */ - memcpy(pei_data->spd_data[0][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); + fill_spd_for_index(pei_data->spd_data[0][0], spd_index); /* CH1 not used in 2GB configurations */ if (!((spd_index == 0b0000) || (spd_index == 0b0011) || (spd_index == 0b1010))) { - memcpy(pei_data->spd_data[1][0], - spd_file + (spd_index * SPD_LEN), SPD_LEN); + memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN); } - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); } diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index e8b31745f93..8349acaeff6 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -34,8 +34,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) return len; } -void variant_romstage_entry(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { - if (rp->power_state->prev_sleep_state != ACPI_S3) + if (!s3resume) google_chromeec_kbbacklight(75); } diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 4329d5f9ab5..9ca592f4018 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -30,8 +30,8 @@ Scope (\_SB.PCI0.I2C0) Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -39,7 +39,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -141,8 +141,8 @@ Scope (\_SB.PCI0.I2C0) Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_CODEC_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -150,7 +150,7 @@ Scope (\_SB.PCI0.I2C0) Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -188,8 +188,8 @@ Scope (\_SB.PCI0.I2C1) Method (_DSW, 3, NotSerialized) { - Store (BOARD_CODEC_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_CODEC_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GPIO.GWAK (Local0) } @@ -198,7 +198,7 @@ Scope (\_SB.PCI0.I2C1) Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h deleted file mode 100644 index c9b04989c11..00000000000 --- a/src/mainboard/google/auron/variants/samus/include/variant/spd.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 69 -#define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 67 -#define SPD_GPIO_BIT3 65 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index d8aec0ae040..0a92efe70b4 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -3,18 +3,29 @@ chip soc/intel/broadwell # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - - # Disable S0ix for now - register "s0ix_enable" = "0" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 200, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + + device cpu_cluster 0 on + chip cpu/intel/haswell + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index 4cad47432c4..25ff928b6d1 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -9,57 +9,13 @@ #include #include #include -#include +#include -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - "density %d Mb\n", banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} +/* Samus board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 69 +#define SPD_GPIO_BIT1 68 +#define SPD_GPIO_BIT2 67 +#define SPD_GPIO_BIT3 65 /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) @@ -72,8 +28,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; int spd_gpio[4]; int spd_index; - size_t spd_file_len; - char *spd_file; spd_gpio[0] = get_gpio(spd_bits[0]); spd_gpio[1] = get_gpio(spd_bits[1]); @@ -88,26 +42,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_map("spd.bin", &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); + fill_spd_for_index(pei_data->spd_data[0][0], spd_index); /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); + memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN); } diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 12f4e862729..1e4a2587498 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -21,9 +21,9 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current) return 0; } -void variant_romstage_entry(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { - if (rp->power_state->prev_sleep_state != ACPI_S3) + if (!s3resume) google_chromeec_kbbacklight(100); printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version()); diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index cbf9dc40dc1..9cd71a852f8 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -62,4 +62,8 @@ config ENABLE_DDR_2X_REFRESH config PCIEXP_AER def_bool n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 8c5d6c5eb9e..e12aa15e695 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -7,7 +7,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c ramstage-y += lan.c -smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c +smm-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 9756695c3d6..c3c90a4e5b5 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -3,13 +3,11 @@ #include #include #include -#include -#include +#include #include -#include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -22,11 +20,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - // SuperIO is always RO - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - gnvs->f4of = FAN4_THRESHOLD_OFF; gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 176fced5ed3..8c54f6a6d09 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -18,14 +18,6 @@ chip northbridge/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end diff --git a/src/mainboard/google/beltino/smihandler.c b/src/mainboard/google/beltino/smihandler.c index 3e09606debd..4280f7a24cd 100644 --- a/src/mainboard/google/beltino/smihandler.c +++ b/src/mainboard/google/beltino/smihandler.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2989621c2a7..4f1854c4eab 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,6 +1,11 @@ config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9324 + select DRIVERS_SPI_ACPI + select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index a186bfc3243..a7bc42587c1 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -9,8 +9,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/baseboard diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 12e725f70c8..f91dcc8d33d 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -7,12 +7,381 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_ALERT0# ==> NC */ + PAD_NC(GPP_A5, NONE), + /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_A6, NONE, DEEP), + /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT), + /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ + /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6), + /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6), + /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), + + /* B0 : SOC_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : SOC_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> SAR2_INT_L */ + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9 : NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, NONE), + /* B19 : NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* C7 : SML1DATA ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), + + /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> WCAM_RST_L */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_D5, 1, DEEP), + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), + /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), + /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ + PAD_CFG_GPI(GPP_D17, NONE, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E1, NONE, DEEP), + /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : PROC_GP0 ==> HPS_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : PROC_GP1 ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), + /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_E17, NONE, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), + /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT), + /* F15 : GSXSRESET# ==> FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F17, NONE, PLTRST, LEVEL, INVERT), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_F19, NONE, DEEP), + /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F21, NONE, DEEP, LEVEL, INVERT), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* F23 : NC */ + PAD_NC(GPP_F23, NONE), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_H3, NONE, DEEP), + /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16 : NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : SRCCLKREQ4# ==> SAR1_INT_L */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE), + /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_NC(GPD7, NONE), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPD11, NONE, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* ToDo: Fill early gpio configuration */ + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb new file mode 100644 index 00000000000..701a13fd7b2 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -0,0 +1,295 @@ +chip soc/intel/alderlake + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_E" + register "pmc_gpe0_dw2" = "GPP_F" + + register "SaGv" = "SaGv_Disabled" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + device domain 0 on + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SIS9815"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR1 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on end + end + chip drivers/i2c/sx9324 + register "desc" = ""SAR2 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 2C on end + end + end + device ref i2c3 on end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F15)" + register "wake" = "GPE0_DW2_15" + device spi 1 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref pmc hidden end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 342c9f7dde3..33a97f5e078 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -7,8 +7,6 @@ ramstage-y += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c -smm-y += mainboard_smi.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 315fd6d7bbe..29faea3fd0d 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -19,7 +18,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) // The firmware read/write status is a "virtual" switch and // will be handled elsewhere. Until then hard-code to // read/write instead of read-only for developer mode. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW; + if (CONFIG(CHROMEOS)) + gnvs_set_ecfw_rw(); // the lid is open by default. gnvs->lids = 1; @@ -27,5 +27,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* EC handles all thermal and fan control on Butterfly. */ gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; - } diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 94e5a2151af..2b9753a361c 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -26,13 +26,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 2ffa3aa5e91..c439fe2e733 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -7,9 +7,6 @@ #include #include #include -#if CONFIG(CHROMEOS) -#include -#endif void mainboard_late_rcba_config(void) { diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/smihandler.c similarity index 97% rename from src/mainboard/google/butterfly/mainboard_smi.c rename to src/mainboard/google/butterfly/smihandler.c index d71d9bf028d..1f45055b0e3 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 1ecc55e6977..4d10b660a07 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -10,8 +10,6 @@ ramstage-y += ec.c ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-y += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index 2f2f298f8e3..e70290873ba 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -3,13 +3,12 @@ #include #include #include +#include #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; @@ -24,6 +23,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* Disable PMIC I2C port for ACPI for all boards except cyan */ if (!CONFIG(BOARD_GOOGLE_CYAN)) gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; + + gnvs->bdid = board_id(); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 94a0a90259c..69280025ee3 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9324 select DRIVERS_INTEL_DPTF select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI @@ -99,6 +100,7 @@ config MAINBOARD_PART_NUMBER default "Galtic" if BOARD_GOOGLE_GALTIC default "Sasuke" if BOARD_GOOGLE_SASUKE default "Storo" if BOARD_GOOGLE_STORO + default "Sasukette" if BOARD_GOOGLE_SASUKETTE config MAX_CPUS int @@ -133,5 +135,6 @@ config VARIANT_DIR default "galtic" if BOARD_GOOGLE_GALTIC default "sasuke" if BOARD_GOOGLE_SASUKE default "storo" if BOARD_GOOGLE_STORO + default "sasukette" if BOARD_GOOGLE_SASUKETTE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 334865529b8..883a6840ee8 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BOTEN bool "Boten" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_BOTEN_LEGACY bool "Boten (Legacy)" @@ -91,8 +92,14 @@ config BOARD_GOOGLE_SASUKE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_STORO bool "-> Storo" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_SASUKETTE + bool "-> Sasukette" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index cd73bb08a19..1b5503d40f4 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -10,8 +10,6 @@ ramstage-y += mainboard.c ramstage-y += ec.c ramstage-y += board_info.c -smm-y += smihandler.c - VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/baseboard diff --git a/src/mainboard/google/dedede/bootblock.c b/src/mainboard/google/dedede/bootblock.c index 328480e3bcd..6ee655ee587 100644 --- a/src/mainboard/google/dedede/bootblock.c +++ b/src/mainboard/google/dedede/bootblock.c @@ -3,7 +3,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2785ad0b928..bb76c9c9ed2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -199,14 +199,16 @@ chip soc/intel/jasperlake register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000) + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000) }" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN) + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN) }" ## Power Limits Control @@ -229,6 +231,15 @@ chip soc/intel/jasperlake register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" device generic 0 on end end diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 1d8d21d7889..c162ac37802 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -407,6 +407,11 @@ static const struct pad_config early_gpio_table[] = { /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C20 : UART2 RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2 TX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* D1 : WLAN_PERST_L */ PAD_CFG_GPO(GPP_D1, 1, DEEP), diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 0c81872ab9c..dc71295361a 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -8,14 +8,21 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ - PAD_CFG_GPO(GPP_A10, 0, PLTRST), + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* B7 : WWAN_SAR_DETECT_R_ODL */ + PAD_CFG_GPO(GPP_B7, 1, DEEP), /* C12 : AP_PEN_DET_ODL */ - PAD_CFG_GPI_SCI(GPP_C12, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), /* C19 : AP_I2C_EMR_SCL */ PAD_NC(GPP_C19, NONE), + /* C22 : UART2_RTS_N */ + PAD_NC(GPP_C22, NONE), + /* C23 : UART2_CTS_N */ + PAD_NC(GPP_C23, NONE), /* D12 : WCAM_RST_L */ PAD_NC(GPP_D12, NONE), @@ -25,6 +32,12 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D14, NONE), /* D15 : UCAM_RST_L */ PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), /* D22 : AP_I2C_SUB_SDA*/ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* D23 : AP_I2C_SUB_SCL */ @@ -37,6 +50,9 @@ static const struct pad_config gpio_table[] = { /* E11 : AP_I2C_SUB_INT_ODL */ PAD_CFG_GPI_INT(GPP_E11, NONE, PLTRST, EDGE_BOTH), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + /* H6 : AP_I2C_CAM_SDA */ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL */ diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index d2540e3d15e..6c0fdd62d16 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -21,15 +21,33 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[5] = { .speed = I2C_SPEED_FAST, @@ -116,18 +134,17 @@ chip soc/intel/jasperlake end end # I2C 0 device pci 15.2 on - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_C12)" - register "key.wake_gpe" = "GPE0_DW1_12" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -144,6 +161,26 @@ chip soc/intel/jasperlake register "hid_desc_reg_offset" = "0x01" device i2c 0x5d on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN901C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end end # I2C 2 device pci 15.3 off end # I2C 3 device pci 19.0 on @@ -172,11 +209,56 @@ chip soc/intel/jasperlake end end # I2C 4 device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""STH9324"" - register "name" = ""SEMTECH SX9324"" + chip drivers/i2c/sx9324 register "desc" = ""SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x0a" + register "reg_gnrl_ctrl1" = "0x22" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x37" + register "reg_afe_ph1" = "0x10" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x1c" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x20" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x6f" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x01" device i2c 28 on end end end # I2C 5 diff --git a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc index 24c75d1d9ad..04eb9a4877f 100644 --- a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-or-later +ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c new file mode 100644 index 00000000000..a91a94ee551 --- /dev/null +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config pre_board6_gpio_table[] = { + + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), +}; + +/* bid6: Pad configuration for board version 6 afterward in ramstage*/ +static const struct pad_config board6_gpio_table[] = { + + /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + uint32_t board_version; + *num = ARRAY_SIZE(pre_board6_gpio_table); + + if (!google_chromeec_cbi_get_board_version(&board_version)) { + if (board_version >= 6) { + *num = ARRAY_SIZE(board6_gpio_table); + return board6_gpio_table; + } + } + + return pre_board6_gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 493854c34d9..fbc6f0b8a5e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -63,13 +63,12 @@ chip soc/intel/jasperlake }" register "tcc_offset" = "20" # TCC of 85C - register "ImonOffset" = "1400" # Imon Offset = 1.4 - register "ImonSlope" = "100" # Imon Slope = 1.0 # Enable Acoustic noise mitigation and set slew rate to 1/4 # Rest of the parameters are 0 by default. register "AcousticNoiseMitigation" = "1" - register "SlowSlewRate" = "1" + register "SlowSlewRate" = "SlewRateFastBy4" + register "FastPkgCRampDisable" = "1" device domain 0 on device pci 05.0 on # IPU - MIPI Camera @@ -163,6 +162,17 @@ chip soc/intel/jasperlake end end #I2C 0 device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" diff --git a/src/mainboard/google/dedede/variants/galtic/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/Makefile.inc new file mode 100644 index 00000000000..eb2c9bc021c --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/galtic/gpio.c b/src/mainboard/google/dedede/variants/galtic/gpio.c new file mode 100644 index 00000000000..79646b5e2e5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP3300_CAMERA */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E17 : HDMI_DDC_SCL */ + PAD_NC(GPP_E17, NONE), + + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc index b0ca2223a81..048c4fd1f3c 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -2,4 +2,7 @@ ## This is an auto-generated file. Do not edit!! ## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE , MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt index fa247902eee..570f6802b41 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -1 +1,5 @@ DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt index 59381dcf5b4..9fae7692620 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -4,3 +4,7 @@ # See util/spd_tools/lp4x/README.md for more details and instructions. # Part Name +H9HCNNNBKMMLXR-NEE, 0 +MT53E512M32D2NP-046 WT:E, 0 +MT53E1G32D2NP-046 WT:A, 1 +H9HCNNNCPMMLXR-NEE, 2 diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 404024b1d62..e9815411223 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -9,9 +9,7 @@ chip soc/intel/jasperlake #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -22,21 +20,98 @@ chip soc/intel/jasperlake .i2c[0] = { .speed = I2C_SPEED_FAST, }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, }" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + }" + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + device domain 0 on - device pci 15.0 on end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2702"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0001"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 10 on end + end + end # I2C 2 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index 1b87bcba61a..18d654f5c62 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -33,16 +33,76 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + }" + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3800, + .max_power = 5800, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index c7f39952c54..e754882ee74 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -61,6 +61,11 @@ chip soc/intel/jasperlake register "tcc_offset" = "10" # TCC of 95C + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "2" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf @@ -117,7 +122,7 @@ chip soc/intel/jasperlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "180" register "generic.reset_off_delay_ms" = "2" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h index 08870e0627b..27c930d4f25 100644 --- a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h @@ -5,4 +5,7 @@ #include +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index d502c915d65..78d5ddea37c 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -151,21 +151,6 @@ chip soc/intel/jasperlake end end # I2C 0 device pci 15.2 on - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "2" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x5d on end - end chip drivers/i2c/hid register "generic.hid" = ""ELAN6915"" register "generic.desc" = ""ELAN Touchscreen"" @@ -202,7 +187,7 @@ chip soc/intel/jasperlake register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "reset_delay_ms" = "1" + register "reset_delay_ms" = "100" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "enable_delay_ms" = "50" register "has_power_resource" = "1" diff --git a/src/mainboard/google/dedede/variants/metaknight/Makefile.inc b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc new file mode 100644 index 00000000000..67a7ab235ad --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/metaknight/gpio.c b/src/mainboard/google/dedede/variants/metaknight/gpio.c new file mode 100644 index 00000000000..d6a7fd599f1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/gpio.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 7034f5c2730..322f72c7881 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -25,15 +25,33 @@ chip soc/intel/jasperlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" @@ -50,6 +68,16 @@ chip soc/intel/jasperlake device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 2.3 on end + end chip drivers/usb/acpi register "desc" = ""User Facing Camera"" register "type" = "UPC_TYPE_INTERNAL" @@ -60,6 +88,11 @@ chip soc/intel/jasperlake register "type" = "UPC_TYPE_INTERNAL" device usb 2.6 on end end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end end end end # USB xHCI @@ -89,7 +122,7 @@ chip soc/intel/jasperlake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "180" register "generic.reset_off_delay_ms" = "2" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/dedede/variants/metaknight/variant.c b/src/mainboard/google/dedede/variants/metaknight/variant.c new file mode 100644 index 00000000000..2540fc7f2a6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/metaknight/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} diff --git a/src/mainboard/google/dedede/variants/sasuke/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/Makefile.inc new file mode 100644 index 00000000000..fd60a18b694 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/sasuke/gpio.c b/src/mainboard/google/dedede/variants/sasuke/gpio.c new file mode 100644 index 00000000000..3654973bd75 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/gpio.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + /* A11 : TOUCH_RPT_EN ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_B7, NONE, DEEP, LEVEL, INVERT), + /* B8 : WLAN_CLKREQ_ODL ==> NC */ + PAD_NC(GPP_B8, NONE), + + /* C18 : AP_I2C_EMR_SDA ==> NC */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL ==> NC */ + PAD_NC(GPP_C19, NONE), + + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D1 : WLAN_PERST_L ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D3 : WLAN_PCIE_WAKE_ODL ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : TOUCH_INT_ODL ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> NC */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> NC */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> NC */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + + /* S2 : DMIC1_CLK ==> NC */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index 69ea1e16f29..b2dd66f2698 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -1,6 +1,43 @@ chip soc/intel/jasperlake + # Disable PCIe Root Port 8 (index 7) + register "PcieRpEnable[7]" = "0" + # Disable PCIe Clock Source 4 (index 3) + register "PcieClkSrcUsage[3]" = "0xff" # USB Port Configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port C0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_16P9MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port C1 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_16P9MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A0 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera # Intel Common SoC Config @@ -48,11 +85,67 @@ chip soc/intel/jasperlake }, }" device domain 0 on - device pci 14.0 on end - device pci 15.0 on end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "enable_delay_ms" = "20" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 device pci 15.2 on end - device pci 1c.7 on end - device pci 19.0 on end - device pci 1f.3 on end + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 19.0 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/sasuke/variant.c b/src/mainboard/google/dedede/variants/sasuke/variant.c new file mode 100644 index 00000000000..22caa069d37 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(20); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} diff --git a/src/mainboard/google/dedede/variants/sasukette/include/variant/ec.h b/src/mainboard/google/dedede/variants/sasukette/include/variant/ec.h new file mode 100644 index 00000000000..08870e0627b --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/sasukette/include/variant/gpio.h b/src/mainboard/google/dedede/variants/sasukette/include/variant/gpio.h new file mode 100644 index 00000000000..9078664608f --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc new file mode 100644 index 00000000000..b0ca2223a81 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt new file mode 100644 index 00000000000..fa247902eee --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt similarity index 51% rename from src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt rename to src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt index f51b3af398e..59381dcf5b4 100644 --- a/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt @@ -1,4 +1,6 @@ # This is a CSV file containing a list of memory parts used by this variant. # Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb new file mode 100644 index 00000000000..404024b1d62 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end diff --git a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc index b0ca2223a81..c0e2fffb6b8 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt index fa247902eee..ad6374dcce0 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt @@ -1 +1,5 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt index 59381dcf5b4..43363e7e0de 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt @@ -1,6 +1,4 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/lp4x -# See util/spd_tools/lp4x/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc index 5881615cc64..8adb5845990 100644 --- a/src/mainboard/google/deltaur/Makefile.inc +++ b/src/mainboard/google/deltaur/Makefile.inc @@ -16,8 +16,6 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += ec.c -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index f5e5fb6b6df..7a4ed08f590 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); void variant_memory_init(FSP_M_CONFIG *mem_cfg); /* SKU ID structure */ diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index 2184f9b16f4..09e0987ed91 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -5,56 +5,76 @@ #include #include -static const struct mb_ddr4_cfg baseboard_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, + /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */ - { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */ - { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ - { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */ - { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ - { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ - { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ - { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ + .ddr4_dq_map = { + .ddr0 = { + .dq0 = { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */ + .dq1 = { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */ + .dq2 = { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ + .dq3 = { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */ + .dq4 = { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ + .dq5 = { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ + .dq6 = { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ + .dq7 = { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ }, - [1] = { - { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */ - { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ - { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ - { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ - { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ - { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ - { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ - { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ + .ddr1 = { + .dq0 = { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */ + .dq1 = { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ + .dq2 = { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ + .dq3 = { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ + .dq4 = { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ + .dq5 = { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ + .dq6 = { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ + .dq7 = { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - { 1, 0, 1, 0, 0, 1, 1, 0 }, - { 1, 0, 1, 0, 1, 0, 1, 0 } + .ddr4_dqs_map = { + .ddr0 = { + .dqs0 = 1, + .dqs1 = 0, + .dqs2 = 1, + .dqs3 = 0, + .dqs4 = 0, + .dqs5 = 1, + .dqs6 = 1, + .dqs7 = 0, + }, + .ddr1 = { + .dqs0 = 1, + .dqs1 = 0, + .dqs2 = 1, + .dqs3 = 0, + .dqs4 = 1, + .dqs5 = 0, + .dqs6 = 1, + .dqs7 = 0, + } }, - .ect = 0, /* Disable Early Command Training */ + .ect = false, /* Disable Early Command Training */ }; void variant_memory_init(FSP_M_CONFIG *mem_cfg) { - const struct spd_info spd_info = { - .topology = SODIMM, - .smbus_info[0] = {.addr_dimm0 = 0x50, - .addr_dimm1 = 0 }, - .smbus_info[1] = {.addr_dimm0 = 0x52, - .addr_dimm1 = 0 }, + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, }; const bool half_populated = false; - struct mb_ddr4_cfg new_board_cfg_ddr4; + struct mb_cfg new_board_cfg_ddr4; memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg)); - new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); + new_board_cfg_ddr4.ddr4_config.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); - meminit_ddr4(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); + memcfg_init(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); } diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c index 68c8d0e991b..f8506df54b3 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/memory.c +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -5,59 +5,61 @@ #include #include -static const struct lpddr4x_cfg baseboard_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ - { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ - { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ - { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ - { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ - { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ - { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 0, /* Early Command Training */ + .ect = false, /* Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } @@ -77,12 +79,11 @@ static int variant_memory_sku(void) void variant_memory_init(FSP_M_CONFIG *mem_cfg) { - const struct lpddr4x_cfg *board_cfg = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *board_cfg = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; const bool half_populated = false; - meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 6c90eed9a85..747010702c2 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index 4c8b888aad5..3c355c5a2ec 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -6,8 +6,6 @@ ramstage-y += ramstage.c romstage-y += romstage.c -smm-y += smihandler.c - bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/drallion/bootblock.c b/src/mainboard/google/drallion/bootblock.c index 5bd5d029fdd..2419a0084fb 100644 --- a/src/mainboard/google/drallion/bootblock.c +++ b/src/mainboard/google/drallion/bootblock.c @@ -5,7 +5,7 @@ #include #include -static void early_config_gpio(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *early_gpio_table; size_t num_gpios = 0; @@ -16,6 +16,5 @@ static void early_config_gpio(void) void bootblock_mainboard_init(void) { - early_config_gpio(); wilco_ec_early_init(); } diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index 8725b836362..384e44bb57b 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -2,33 +2,12 @@ #include #include -#include #include #include #include #include #include -#define VPD_KEY_SYSTEM_SERIAL "serial_number" -#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" -#define VPD_SERIAL_LEN 64 - -const char *smbios_system_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - -const char *smbios_mainboard_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index ece0119a3ea..af5f8cd0fec 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -62,10 +62,6 @@ config MAINBOARD_FAMILY string default "Google_Eve" -config MAX_CPUS - int - default 8 - config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_RT5514 diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index ef8b0bd110a..fc6dc660f18 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -13,5 +13,3 @@ ramstage-y += mainboard.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads - -smm-y += smihandler.c diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 84b10efdd27..2579c8b63fd 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -11,7 +11,7 @@ static void early_config_gpio(void) gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { early_config_gpio(); } diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 0e76de140f8..c0531fa2385 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -3,13 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "100" - register "gpu_pp_down_delay_ms" = "500" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Enable deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index e09f8533372..afa8f900317 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -60,10 +60,6 @@ config MAINBOARD_FAMILY default "Google_Kalista" if BOARD_GOOGLE_KARMA default "Google_Endeavour" if BOARD_GOOGLE_ENDEAVOUR -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 @@ -99,4 +95,8 @@ config UART_FOR_CONSOLE config USE_PM_ACPI_TIMER default n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif # BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 13bf370c403..e192cffd3da 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -13,8 +13,6 @@ ramstage-y += mainboard.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/fizz/bootblock.c b/src/mainboard/google/fizz/bootblock.c index efab9994dc2..b3afb18bb96 100644 --- a/src/mainboard/google/fizz/bootblock.c +++ b/src/mainboard/google/fizz/bootblock.c @@ -6,7 +6,7 @@ #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 8c31f9ac706..e9d5a3544ad 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -1,12 +1,13 @@ chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 144fe97b8b1..bd4e649fbed 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -65,10 +65,6 @@ config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 9bf68727de2..9fd41f89a7a 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -15,8 +15,6 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -smm-y += smihandler.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/glados/bootblock_mainboard.c b/src/mainboard/google/glados/bootblock_mainboard.c index 19c5e9efb81..41105826fb8 100644 --- a/src/mainboard/google/glados/bootblock_mainboard.c +++ b/src/mainboard/google/glados/bootblock_mainboard.c @@ -12,7 +12,7 @@ static void early_config_gpio(void) gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { early_config_gpio(); } diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 127334e1bad..5a48c5db474 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -3,13 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Enable deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index b4c65baa90c..17c24a2ed72 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -217,6 +217,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 24e7b33cc27..f570006180a 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -234,6 +234,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 7d000f5d6ef..45e1f675316 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -226,6 +226,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 6d415ca30a4..1c92e51df92 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -222,6 +222,8 @@ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 9ee00d2cf9c..a7bcdd74357 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -224,6 +224,8 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index 3d00c353d71..acbf157ac0a 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -213,6 +213,8 @@ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 717e930d24b..a2052a3379a 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -221,6 +221,8 @@ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 40460e2dbd4..fe20162e952 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -7,8 +7,13 @@ if BOARD_GOOGLE_BASEBOARD_GUYBRUSH config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_16384 select SOC_AMD_CEZANNE +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + config MAINBOARD_DIR string default "google/guybrush" @@ -17,6 +22,12 @@ config MAINBOARD_PART_NUMBER string default "Guybrush" if BOARD_GOOGLE_GUYBRUSH +config AMD_FWM_POSITION_INDEX + int + default 3 + help + TODO: might need to be adapted for better placement of files in cbfs + config DEVICETREE string default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index a4e91b6b0af..d0883413241 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -11,7 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_PUFF select RT8168_SET_LED_MODE select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD - select SOC_INTEL_CSE_LITE_SKU if CHROMEOS + select SOC_INTEL_CSE_LITE_SKU select DRIVERS_INTEL_DPTF select DPTF_USE_EISA_HID @@ -188,4 +188,8 @@ config VBOOT config USE_PM_ACPI_TIMER default n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 if BOARD_GOOGLE_BASEBOARD_PUFF + endif # BOARD_GOOGLE_HATCH_COMMON diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index f82325f177d..debe94295f3 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -12,7 +12,6 @@ romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c index 041ffcffd22..6e2f34d10ed 100644 --- a/src/mainboard/google/hatch/bootblock.c +++ b/src/mainboard/google/hatch/bootblock.c @@ -4,7 +4,7 @@ #include #include -static void early_config_gpio(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *variant_early_table; size_t variant_gpios; @@ -12,8 +12,3 @@ static void early_config_gpio(void) variant_early_table = variant_early_gpio_table(&variant_gpios); gpio_configure_pads(variant_early_table, variant_gpios); } - -void bootblock_mainboard_init(void) -{ - early_config_gpio(); -} diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 1395c8f2044..d66844062fc 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -26,6 +26,9 @@ DefinitionBlock( { #include #include +#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) + #include +#endif } } diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 7694b0c930c..b08f062186e 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -152,6 +152,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 8ae350c5099..97a6eaf8834 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -72,6 +72,9 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 45c43cc98c2..69d142886b2 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -9,7 +9,7 @@ chip soc/intel/cannonlake register "TetonGlacierMode" = "1" register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index f50f8f23a0c..32591b82bff 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -78,6 +78,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 3b094a34a8e..3605196c116 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -69,6 +69,9 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 5870261cbb5..cfd324892d0 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -50,6 +50,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index e13270f85f4..01afa160003 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -68,6 +68,9 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 1c4f862a9a6..98858021403 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -114,6 +114,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 4241a466400..c93562059aa 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -60,6 +60,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 6fbe95058f9..129bb269f56 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -76,6 +76,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 4029f062dbe..a0658b091a5 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -80,6 +80,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 750e068bb64..16402af7843 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -69,6 +69,9 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 02.0 on chip drivers/gfx/generic register "device_count" = "1" diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 8073e095bff..b147e41118f 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -210,6 +210,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index c06f35b9cbf..f27423f537c 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -105,6 +105,9 @@ chip soc/intel/cannonlake register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 6a3d0da428c..d45e9cb0fff 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -96,6 +96,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 740a7d86ffe..266346b3b56 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -73,6 +73,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index e421a1a2fdf..582d68e6a29 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -54,6 +54,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 29b87e4ce2d..74b3e1f4e8f 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -88,6 +88,9 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc index 05f77adafcf..c0a68a889d6 100644 --- a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = LP_8G_2133 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += LP_16G_2133 # 0b001 SPD_SOURCES += LP_4G_2133 # 0b010 romstage-y += memory.c diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index eb6217ded96..1ab10a84af9 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -110,6 +110,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index ff61d80906f..8805a324af3 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -121,6 +121,9 @@ chip soc/intel/cannonlake register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 3675375b281..c4d6f50dd7d 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -118,6 +118,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 8cdb2a9fb37..b7f6ff2ca5c 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -57,6 +57,9 @@ chip soc/intel/cannonlake }" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 6629e76d6bf..fd8a55c09db 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -70,6 +70,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 3611e582b32..aa73ab6df36 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -58,6 +58,9 @@ chip soc/intel/cannonlake register "sdcard_cd_gpio" = "vSD3_CD_B" device domain 0 on + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 4851bd7a686..b04cc465fb0 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -39,10 +39,6 @@ config MAINBOARD_PART_NUMBER default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" @@ -59,4 +55,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER config PCIEXP_AER def_bool n +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + endif diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 845fb0bd2ce..ed74d751095 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -6,7 +6,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c -smm-y += smihandler.c led.c +smm-y += led.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 1197c0ca1ca..189f7f44deb 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -7,7 +7,7 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 94fd8044c1a..08b2c957c79 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -10,7 +10,10 @@ chip soc/intel/broadwell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 612901123e3..5c978baabbc 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -8,17 +8,9 @@ #include #include #include -#include #include "onboard.h" -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); - mainboard_fill_spd_data(&rp->pei_data); -} - -void mainboard_post_raminit(struct romstage_params *rp) +void mainboard_post_raminit(const int s3resume) { if (CONFIG(CHROMEOS)) init_bootmode_straps(); diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 911cf604bec..f4454b8fa53 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) diff --git a/src/mainboard/google/jecht/spd/spd.h b/src/mainboard/google/jecht/spd/spd.h deleted file mode 100644 index 5ebd8c233a2..00000000000 --- a/src/mainboard/google/jecht/spd/spd.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 8e2639c2a40..2c84782c9d7 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -19,7 +19,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS select SERIRQ_CONTINUOUS_MODE - select STONEYRIDGE_UART + select AMD_SOC_CONSOLE_UART select SOC_AMD_SMU_FANLESS select HAVE_ACPI_RESUME select DRIVERS_GENERIC_BH720 diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index faa2496a19d..94705922a6e 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -16,8 +16,6 @@ ramstage-y += OemCustomize.c verstage-y += chromeos.c verstage-y += ec.c -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/kahlee/acpi_tables.c b/src/mainboard/google/kahlee/acpi_tables.c new file mode 100644 index 00000000000..ab36f40a350 --- /dev/null +++ b/src/mainboard/google/kahlee/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index b40b4bc8e03..570f20ce310 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -5,14 +5,12 @@ #include #include #include -#include #include #include #include #include #include #include -#include #include #include #include @@ -161,19 +159,6 @@ static void kahlee_enable(struct device *dev) dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } -static void mainboard_final(void *chip_info) -{ - struct global_nvs *gnvs; - - gnvs = acpi_get_gnvs(); - - if (gnvs) { - gnvs->tmps = CTL_TDP_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - } -} - int mainboard_get_xhci_oc_map(uint16_t *map) { return variant_get_xhci_oc_map(map); @@ -192,7 +177,6 @@ void mainboard_suspend_resume(void) struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = kahlee_enable, - .final = mainboard_final, }; /* Variants may override these functions so see definitions in variants/ */ diff --git a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc index 24e0090c5e5..3a8e8607ad7 100644 --- a/src/mainboard/google/kahlee/variants/aleena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/aleena/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc index 9f33a0b224c..a41ba22e8be 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc @@ -11,6 +11,7 @@ romstage-y += memory.c romstage-y += tpm_tis.c ramstage-y += gpio.c +ramstage-y += mainboard.c ramstage-y += tpm_tis.c # Add OEM ID table diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index cd19d7cab56..e50e6b9db57 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -4,5 +4,3 @@ subdirs-y += ./spd bootblock-y += variant.c romstage-y += variant.c - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc index 24e0090c5e5..3a8e8607ad7 100644 --- a/src/mainboard/google/kahlee/variants/grunt/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/grunt/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/liara/Makefile.inc b/src/mainboard/google/kahlee/variants/liara/Makefile.inc index 24e0090c5e5..3a8e8607ad7 100644 --- a/src/mainboard/google/kahlee/variants/liara/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/liara/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ../baseboard/spd - -ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc index c4dcffc780c..21b0276a720 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/nuwani/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd - -ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb index 8c9f1cd47f6..9d4ff0e6a48 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/devicetree.cb @@ -62,6 +62,7 @@ chip soc/amd/stoneyridge device pci 2.4 on chip drivers/generic/bayhub register "power_saving" = "1" + register "vih_tuning_value" = "0x35" device pci 00.0 on end end end # diff --git a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c b/src/mainboard/google/kahlee/variants/nuwani/mainboard.c deleted file mode 100644 index ce98d62c184..00000000000 --- a/src/mainboard/google/kahlee/variants/nuwani/mainboard.c +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -uint32_t sku_id(void) -{ - static int sku = -1; - - if (sku == -1) - sku = google_chromeec_get_sku_id(); - - return sku; -} - -uint8_t variant_board_sku(void) -{ - return sku_id(); -} - -void variant_mainboard_suspend_resume(void) -{ - /* Enable backlight - GPIO 133 active low */ - gpio_set(GPIO_133, 0); -} - -void board_bh720(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - - /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); - - /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); - - /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); - - /* Tune VIH */ - pci_write_config32(dev, BH720_PROTECT, - BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); - bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL); - bh720_pcr_data &= 0xFFFFFF00; - /* CLK = 3 and DAT = 2 */ - bh720_pcr_data |= 0x35; - pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data); - pci_write_config32(dev, BH720_PROTECT, - BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); -} - -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_bin_data[11]; - static const char *manuf; - - if (!CONFIG(USE_OEM_BIN)) - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - if (manuf) - return manuf; - - if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) - manuf = &oem_bin_data[0]; - else - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - return manuf; -} diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index c4dcffc780c..21b0276a720 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd - -ramstage-y += mainboard.c diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 132172e7506..183e3ddacd5 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -62,6 +62,7 @@ chip soc/amd/stoneyridge device pci 2.4 on chip drivers/generic/bayhub register "power_saving" = "1" + register "vih_tuning_value" = "0x35" device pci 00.0 on end end end # diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c deleted file mode 100644 index ce98d62c184..00000000000 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -uint32_t sku_id(void) -{ - static int sku = -1; - - if (sku == -1) - sku = google_chromeec_get_sku_id(); - - return sku; -} - -uint8_t variant_board_sku(void) -{ - return sku_id(); -} - -void variant_mainboard_suspend_resume(void) -{ - /* Enable backlight - GPIO 133 active low */ - gpio_set(GPIO_133, 0); -} - -void board_bh720(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); - - /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - bh720_pcr_data &= 0x0000FFFF; - bh720_pcr_data |= 0x2510 << 16; - write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); - - /* Use PLL Base clock PCR 0x3E4[22] = 1 */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_READ | BH720_PCR_CSR); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); - write32((void *)(sdbar + BH720_MEM_RW_ADR), - BH720_MEM_RW_WRITE | BH720_PCR_CSR); - - /* Disable Memory Access */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); - - /* Tune VIH */ - pci_write_config32(dev, BH720_PROTECT, - BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF); - bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL); - bh720_pcr_data &= 0xFFFFFF00; - /* CLK = 3 and DAT = 2 */ - bh720_pcr_data |= 0x35; - pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data); - pci_write_config32(dev, BH720_PROTECT, - BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON); -} - -const char *smbios_mainboard_manufacturer(void) -{ - static char oem_bin_data[11]; - static const char *manuf; - - if (!CONFIG(USE_OEM_BIN)) - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - if (manuf) - return manuf; - - if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) - manuf = &oem_bin_data[0]; - else - manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - - return manuf; -} diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 0e3a4dc23c8..3e9374e1b0a 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER - select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU + select MT8183_DRAM_EMCP if BOARD_GOOGLE_KRANE || BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU config MAINBOARD_DIR string @@ -59,6 +59,7 @@ config MAINBOARD_PART_NUMBER default "Esche" if BOARD_GOOGLE_ESCHE default "Burnet" if BOARD_GOOGLE_BURNET default "Fennel" if BOARD_GOOGLE_FENNEL + default "Katsu" if BOARD_GOOGLE_KATSU config DRIVER_TPM_SPI_BUS hex @@ -75,6 +76,7 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS config BOARD_SDRAM_TABLE_OFFSET hex default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN + default 0x20 if BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU default 0x0 config BOARD_OVERRIDE_LCM_ID diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 63cd3e74ac4..072c93bb267 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -20,6 +20,10 @@ config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON +config BOARD_GOOGLE_KATSU + bool "-> Katsu" + select BOARD_GOOGLE_KUKUI_COMMON + comment "Jacuzzi" config BOARD_GOOGLE_JACUZZI diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 7e065a3d8d8..968ee19627d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -21,6 +21,7 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c ramstage-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel_kakadu.c +ramstage-$(CONFIG_BOARD_GOOGLE_KATSU) += panel_katsu.c ramstage-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index a197a7f0096..7efa01b0cc5 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -168,6 +168,10 @@ static bool configure_display(void) printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); return false; } + + if (panel->post_power_on) + panel->post_power_on(); + mtk_ddp_mode_set(edid); struct fb_info *info = fb_new_framebuffer_info_from_edid(edid, 0); if (info) diff --git a/src/mainboard/google/kukui/panel.h b/src/mainboard/google/kukui/panel.h index 7ae31dd7915..174956551db 100644 --- a/src/mainboard/google/kukui/panel.h +++ b/src/mainboard/google/kukui/panel.h @@ -21,6 +21,7 @@ struct panel_description { const char *name; /* Panel name for constructing CBFS file name */ struct panel_serializable_data *s; void (*power_on)(void); /* Callback to turn on panel */ + void (*post_power_on)(void); /* Callback to run after panel is turned on */ }; /* Returns the panel description from given ID. */ diff --git a/src/mainboard/google/kukui/panel_anx7625.c b/src/mainboard/google/kukui/panel_anx7625.c index cc41c86e63b..aa22cf3edf3 100644 --- a/src/mainboard/google/kukui/panel_anx7625.c +++ b/src/mainboard/google/kukui/panel_anx7625.c @@ -9,6 +9,33 @@ #include "panel.h" +#define ANX7625_I2C_BUS 4 + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static void dummy_power_on(void) +{ + /* + * The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static void start_anx7625(void) +{ + if (anx7625_dp_start(ANX7625_I2C_BUS, &anx7625_data.edid) < 0) + printk(BIOS_ERR, "Can't start display via ANX7625.\n"); +} + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, + .post_power_on = start_anx7625, +}; + static void power_on_anx7625(void) { /* Disable backlight before turning on bridge */ @@ -27,43 +54,21 @@ static void power_on_anx7625(void) gpio_output(GPIO_PP3300_LCM_EN, 1); } -static void dummy_power_on(void) -{ - /* The panel has been already powered on when getting panel information - * so we should do nothing here. - */ -} - -static struct panel_serializable_data anx7625_data = { - .orientation = LB_FB_ORIENTATION_NORMAL, - .init = { INIT_END_CMD }, -}; - -static struct panel_description anx7625_panel = { - .s = &anx7625_data, - .power_on = dummy_power_on, -}; - struct panel_description *get_panel_description(int panel_id) { /* To read panel EDID, we have to first power on anx7625. */ power_on_anx7625(); - u8 i2c_bus = 4; - mtk_i2c_bus_init(i2c_bus); + mtk_i2c_bus_init(ANX7625_I2C_BUS); - if (anx7625_init(i2c_bus)) { + if (anx7625_init(ANX7625_I2C_BUS)) { printk(BIOS_ERR, "Can't init ANX7625 bridge.\n"); return NULL; } - struct edid *edid = &anx7625_data.edid; - if (anx7625_dp_get_edid(i2c_bus, edid)) { + + if (anx7625_dp_get_edid(ANX7625_I2C_BUS, &anx7625_data.edid)) { printk(BIOS_ERR, "Can't get panel's edid.\n"); return NULL; } - if (anx7625_dp_start(i2c_bus, edid) < 0) { - printk(BIOS_ERR, "Can't start display via ANX7625.\n"); - return NULL; - } return &anx7625_panel; } diff --git a/src/mainboard/google/kukui/panel_katsu.c b/src/mainboard/google/kukui/panel_katsu.c new file mode 100644 index 00000000000..f2a20701460 --- /dev/null +++ b/src/mainboard/google/kukui/panel_katsu.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "panel.h" + +static struct panel_description katsu_panels[] = { + [1] = { .name = "BOE_TV105WUM_NW0", }, + [2] = { .name = "STA_2081101QFH032011_53G", }, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + if (panel_id < 0 || panel_id >= ARRAY_SIZE(katsu_panels)) + return NULL; + + return get_panel_from_cbfs(&katsu_panels[panel_id]); +} diff --git a/src/mainboard/google/kukui/panel_params/Makefile.inc b/src/mainboard/google/kukui/panel_params/Makefile.inc index 3bd605d9b27..5d84f96ffd7 100644 --- a/src/mainboard/google/kukui/panel_params/Makefile.inc +++ b/src/mainboard/google/kukui/panel_params/Makefile.inc @@ -9,6 +9,8 @@ panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-AUO_NT51021D8P panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-BOE_TV080WUM_NG0 panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-BOE_TV101WUM_NG0 panel-params-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel-INX_OTA7290D10P +panel-params-$(CONFIG_BOARD_GOOGLE_KATSU) += panel-STA_2081101QFH032011_53G +panel-params-$(CONFIG_BOARD_GOOGLE_KATSU) += panel-BOE_TV105WUM_NW0 $(foreach params,$(panel-params-y), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c new file mode 100644 index 00000000000..baf3dacc745 --- /dev/null +++ b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../panel.h" + +struct panel_serializable_data STA_QFH032011_53G = { + .edid = { + .ascii_string = "QFH032011-53G", + .manufacturer_name = "STA", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 150451, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 210, .hso = 100, .hspw = 10, + .va = 1920, .vbl = 39, .vso = 14, .vspw = 10, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 217, + }, + }, + .orientation = LB_FB_ORIENTATION_LEFT_UP, + .init = { + INIT_DCS_CMD(0xB0, 0x41), + INIT_DCS_CMD(0xC3, 0x4F), + INIT_DCS_CMD(0xC4, 0x40), + INIT_DCS_CMD(0xC5, 0x40), + INIT_DCS_CMD(0xC6, 0x40), + INIT_DCS_CMD(0xC7, 0x40), + INIT_DCS_CMD(0xC8, 0x4D), + INIT_DCS_CMD(0xC9, 0x52), + INIT_DCS_CMD(0xCA, 0x51), + INIT_DCS_CMD(0xCD, 0x5D), + INIT_DCS_CMD(0xCE, 0x5B), + INIT_DCS_CMD(0xCF, 0x4B), + INIT_DCS_CMD(0xD0, 0x49), + INIT_DCS_CMD(0xD1, 0x47), + INIT_DCS_CMD(0xD2, 0x45), + INIT_DCS_CMD(0xD3, 0x41), + INIT_DCS_CMD(0xD7, 0x50), + INIT_DCS_CMD(0xD8, 0x40), + INIT_DCS_CMD(0xD9, 0x40), + INIT_DCS_CMD(0xDA, 0x40), + INIT_DCS_CMD(0xDB, 0x40), + INIT_DCS_CMD(0xDC, 0x4E), + INIT_DCS_CMD(0xDD, 0x52), + INIT_DCS_CMD(0xDE, 0x51), + INIT_DCS_CMD(0xE1, 0x5E), + INIT_DCS_CMD(0xE2, 0x5C), + INIT_DCS_CMD(0xE3, 0x4C), + INIT_DCS_CMD(0xE4, 0x4A), + INIT_DCS_CMD(0xE5, 0x48), + INIT_DCS_CMD(0xE6, 0x46), + INIT_DCS_CMD(0xE7, 0x42), + INIT_DCS_CMD(0xB0, 0x03), + INIT_DCS_CMD(0xBE, 0x03), + INIT_DCS_CMD(0xCC, 0x44), + INIT_DCS_CMD(0xC8, 0x07), + INIT_DCS_CMD(0xC9, 0x05), + INIT_DCS_CMD(0xCA, 0x42), + INIT_DCS_CMD(0xCD, 0x3E), + INIT_DCS_CMD(0xCF, 0x60), + INIT_DCS_CMD(0xD2, 0x04), + INIT_DCS_CMD(0xD3, 0x04), + INIT_DCS_CMD(0xD4, 0x01), + INIT_DCS_CMD(0xD5, 0x00), + INIT_DCS_CMD(0xC6, 0x03), + INIT_DCS_CMD(0xD7, 0x04), + INIT_DCS_CMD(0xD9, 0x01), + INIT_DCS_CMD(0xDB, 0x01), + INIT_DCS_CMD(0xE4, 0xF0), + INIT_DCS_CMD(0xE5, 0x0A), + INIT_DCS_CMD(0xB0, 0x00), + INIT_DCS_CMD(0xC2, 0x08), + INIT_DCS_CMD(0xC4, 0x10), + INIT_DCS_CMD(0xB0, 0x02), + INIT_DCS_CMD(0xC0, 0x00), + INIT_DCS_CMD(0xC1, 0x0A), + INIT_DCS_CMD(0xC2, 0x20), + INIT_DCS_CMD(0xC3, 0x24), + INIT_DCS_CMD(0xC4, 0x23), + INIT_DCS_CMD(0xC5, 0x29), + INIT_DCS_CMD(0xC6, 0x23), + INIT_DCS_CMD(0xC7, 0x1C), + INIT_DCS_CMD(0xC8, 0x19), + INIT_DCS_CMD(0xC9, 0x17), + INIT_DCS_CMD(0xCA, 0x17), + INIT_DCS_CMD(0xCB, 0x18), + INIT_DCS_CMD(0xCC, 0x1A), + INIT_DCS_CMD(0xCD, 0x1E), + INIT_DCS_CMD(0xCE, 0x20), + INIT_DCS_CMD(0xCF, 0x23), + INIT_DCS_CMD(0xD0, 0x07), + INIT_DCS_CMD(0xD1, 0x00), + INIT_DCS_CMD(0xD2, 0x00), + INIT_DCS_CMD(0xD3, 0x0A), + INIT_DCS_CMD(0xD4, 0x13), + INIT_DCS_CMD(0xD5, 0x1C), + INIT_DCS_CMD(0xD6, 0x1A), + INIT_DCS_CMD(0xD7, 0x13), + INIT_DCS_CMD(0xD8, 0x17), + INIT_DCS_CMD(0xD9, 0x1C), + INIT_DCS_CMD(0xDA, 0x19), + INIT_DCS_CMD(0xDB, 0x17), + INIT_DCS_CMD(0xDC, 0x17), + INIT_DCS_CMD(0xDD, 0x18), + INIT_DCS_CMD(0xDE, 0x1A), + INIT_DCS_CMD(0xDF, 0x1E), + INIT_DCS_CMD(0xE0, 0x20), + INIT_DCS_CMD(0xE1, 0x23), + INIT_DCS_CMD(0xE2, 0x07), + INIT_DCS_CMD(0X11), + INIT_DELAY_CMD(120), + INIT_DCS_CMD(0X29), + INIT_DELAY_CMD(50), + INIT_END_CMD, + }, +}; diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 57f5e6e7654..f00bec82c81 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -24,13 +24,25 @@ static const char *const sdram_configs[] = { [0x09] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", [0x0a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", - /* Table shared by Burnet and its variants, offset = 0x10 */ + /* Table shared by Burnet and its variants, Fennel and Cerise, offset = 0x10 */ [0x10] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", [0x11] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x14] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + + /* Table shared by Kakadu and its variants, offset = 0x20 */ + [0x20] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x21] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x22] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x23] = "sdram-lpddr4x-KMDH6001DA-B422-4GB", + [0x24] = "sdram-lpddr4x-KMDP6001DA-B425-4GB", + [0x25] = "sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB", + [0x26] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", + [0x27] = "sdram-lpddr4x-SDADA4CR-128G-4GB", + [0x28] = "sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB", + }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 719b3c29e94..eaba5825f31 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -10,6 +10,9 @@ sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB sdram-params += sdram-lpddr4x-MT53E1G32D4NQ-4GB sdram-params += sdram-lpddr4x-MT53E2G32D4NQ-046-8GB sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB +sdram-params += sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB +sdram-params += sdram-lpddr4x-MT53E1G32D2NP-046-4GB +sdram-params += sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index 767fa4af128..ddc829fd5c3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c index 05cd6df89dc..77edc7f36a3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c @@ -6,6 +6,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .frequency = 1600, + .rank_num = 2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c new file mode 100644 index 00000000000..b440c7f65c9 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_RK0_RK1_BYTE_8GB_4_4, + .frequency = 1600, + .rank_num = 2, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_BYTE_MODE1, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 17347970428..0125c9c6f92 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -4,6 +4,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .rank_num = 2, .frequency = 1600, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c index 17347970428..3c4c09083e7 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index a7f2123fafe..1ee43472efd 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 8141d2aafe9..b52f7dd1899 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -4,6 +4,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .rank_num = 2, .frequency = 1600, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 74e81876549..6a13e8a13ce 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 53028b067e8..158df284c31 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB.c new file mode 100644 index 00000000000..20f0c4a30df --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, + .frequency = 1600, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c new file mode 100644 index 00000000000..86c3e8f04e9 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D2NP-046-4GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .rank_num = 1, + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 26b12bfea39..5248db99b79 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c index 20f0c4a30df..8d53d5f451c 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E2G32D4NQ-046-8GB.c @@ -6,6 +6,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .ddr_geometry = DDR_TYPE_2CH_2RK_8GB_4_4, .frequency = 1600, + .rank_num = 2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 1dd5d94a213..448122ffc4d 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -5,6 +5,7 @@ struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .rank_num = 2, .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index ee411c2f28e..6b3f1b568cb 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -6,8 +6,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += mainboard_smi.c - # Order of names in SPD_SOURCES is important! SPD_SOURCES = elpida_4Gb_1600_x16 SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index f37f37e6cf0..9a23474363d 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -16,11 +14,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = CTDP_SENSOR_ID; gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 6ce51a3961d..a99d618eb8b 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -25,13 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/smihandler.c similarity index 98% rename from src/mainboard/google/link/mainboard_smi.c rename to src/mainboard/google/link/smihandler.c index 827ec17de82..8d4b4bd5af2 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/smihandler.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 6e3dbf493c5..64f7649227a 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -34,12 +34,14 @@ config BOARD_GOOGLE_BOBBA select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_MEEP bool "-> Meep" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_AMPTON bool "-> Ampton" diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index aa055246d27..1acd8c688e4 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -8,7 +8,6 @@ ramstage-y += ec.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c index 0add4535b27..1802695b7d1 100644 --- a/src/mainboard/google/octopus/bootblock.c +++ b/src/mainboard/google/octopus/bootblock.c @@ -3,16 +3,22 @@ #include #include #include -#include #include +void bootblock_mainboard_early_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = mainboard_early_bootblock_gpio_table(&num); + gpio_configure_pads(pads, num); +}; + void bootblock_mainboard_init(void) { const struct pad_config *pads, *override_pads; size_t num, override_num; - lpc_configure_pads(); - /* * Perform EC init before configuring GPIOs. This is because variant * might talk to the EC to get board id and hence it will require EC diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index f87b96282ef..513db663fe9 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -25,6 +25,7 @@ DefinitionBlock( #include #include #include + #include } } diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index e6dbd0330bf..91d29cf61cf 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -8,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +24,9 @@ #include #include +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_da7219_ops; + static bool is_cnvi_held_in_reset(void) { struct device *dev = pcidev_path_on_root(PCH_DEVFN_CNVI); @@ -46,6 +51,41 @@ static void disable_wifi_wake(void) gpio_configure_pads(wifi_wake_gpio, ARRAY_SIZE(wifi_wake_gpio)); } +/* + * GPIO_137 for two audio codecs right now has the different configuration so + * if SSFC indicates that codec is different than default one then GPIO_137 + * needs to be overridden for the corresponding second source. + */ +static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) +{ + /* For RT5682, GPIO 137 should be set as EDGE_BOTH. */ + const struct pad_config rt5682_gpio_137 = PAD_CFG_GPI_APIC_IOS(GPIO_137, + NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, DISPUPD); + + if (table == NULL || num == 0) + return; + + /* + * Currently we only have the case of RT5682 as the second source. And + * in case of Ampton which used RT5682 as the default source, it didn't + * provide override_table right now so it will be returned ealier since + * table above is NULL. + */ + if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) + return; + + while (num--) { + if (table->pad == GPIO_137) { + *table = rt5682_gpio_137; + printk(BIOS_INFO, + "Configure GPIO 137 based on SSFC.\n"); + return; + } + + table++; + } +} + static void mainboard_init(void *chip_info) { int boardid; @@ -58,6 +98,8 @@ static void mainboard_init(void *chip_info) base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); + gpio_modification_by_ssfc((struct pad_config *)override_pads, + override_num); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); @@ -128,10 +170,47 @@ static void wifi_device_update(void) dev->enabled = 0; } +/* + * Base on SSFC value in the CBI from EC to enable one of audio codec sources in + * the device tree. + */ +static void audio_codec_device_update(void) +{ + struct device *audio_dev = NULL; + struct bus *audio_i2c_bus = + pcidev_path_on_root(PCH_DEVFN_I2C5)->link_list; + enum ssfc_audio_codec codec = ssfc_get_audio_codec(); + + while ((audio_dev = dev_bus_each_child(audio_i2c_bus, audio_dev))) { + if (audio_dev->chip_info == NULL) + continue; + + if ((audio_dev->chip_ops == &drivers_i2c_da7219_ops) && + (codec == SSFC_AUDIO_CODEC_DA7219)) { + printk(BIOS_INFO, "enable DA7219.\n"); + continue; + } + + if ((audio_dev->chip_ops == &drivers_i2c_generic_ops) && + (codec == SSFC_AUDIO_CODEC_RT5682)) { + struct drivers_i2c_generic_config *cfg = + audio_dev->chip_info; + + if (cfg != NULL && !strcmp(cfg->hid, "10EC5682")) { + printk(BIOS_INFO, "enable RT5682.\n"); + continue; + } + } + + audio_dev->enabled = 0; + } +} + void mainboard_devtree_update(struct device *dev) { /* Apply common devtree updates. */ wifi_device_update(); + audio_codec_device_update(); /* Defer to variant for board-specific updates. */ variant_update_devtree(dev); diff --git a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc index 63b03a61188..f28c3d6ce5b 100644 --- a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc @@ -4,5 +4,6 @@ romstage-y += memory.c ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += cbi_ssfc.c smm-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c b/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c new file mode 100644 index 00000000000..589f92e139b --- /dev/null +++ b/src/mainboard/google/octopus/variants/baseboard/cbi_ssfc.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static int get_ssfc(uint32_t *val) +{ + static uint32_t known_value; + static enum { + SSFC_NOT_READ, + SSFC_AVAILABLE, + } ssfc_state = SSFC_NOT_READ; + + if (ssfc_state == SSFC_AVAILABLE) { + *val = known_value; + return 0; + } + + /* + * If SSFC field is not in the CBI then the value of SSFC will be 0 for + * further processing later since 0 of each bits group means default + * component in a variant. For more detail, please refer to cbi_ssfc.h. + */ + if (google_chromeec_cbi_get_ssfc(&known_value) != 0) { + printk(BIOS_DEBUG, "SSFC not set in CBI\n"); + return -1; + } + + ssfc_state = SSFC_AVAILABLE; + *val = known_value; + printk(BIOS_INFO, "SSFC 0x%x.\n", known_value); + + return 0; +} + +static unsigned int extract_field(uint32_t mask, int shift) +{ + uint32_t ssfc; + + /* On errors nothing is assumed to be set. */ + if (get_ssfc(&ssfc)) + return 0; + + return (ssfc >> shift) & mask; +} + +static enum ssfc_audio_codec ssfc_get_default_audio_codec(void) +{ + /* + * Octopus has two reference boards; yorp is with DA7219 and bip is with + * RT5682. Currently only AMPTON derived from bip so only it uses + * RT5682 as the default source in the first MP devices. + */ + if (CONFIG(BOARD_GOOGLE_AMPTON)) + return SSFC_AUDIO_CODEC_RT5682; + + return SSFC_AUDIO_CODEC_DA7219; +} + +enum ssfc_audio_codec ssfc_get_audio_codec(void) +{ + uint32_t codec = extract_field( + SSFC_AUDIO_CODEC_MASK, SSFC_AUDIO_CODEC_OFFSET); + + if (codec != SSFC_AUDIO_CODEC_DEFAULT) + return codec; + + return ssfc_get_default_audio_codec(); +} diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index cbcd48aab41..3dbc5ef080a 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -112,7 +112,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 off end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Gaussian Mixture Model (GMM) device pci 0c.0 on chip drivers/wifi/generic diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 21d42683df7..85b0cc0afc6 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -292,6 +292,18 @@ const struct pad_config *__weak variant_early_override_gpio_table(size_t *num) return NULL; } +static const struct pad_config early_bootblock_gpio_table[] = { + PAD_NC(GPIO_154, NONE), /* LPC_CLKRUNB -- NC for eSPI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ +}; + +const struct pad_config *mainboard_early_bootblock_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_bootblock_gpio_table); + return early_bootblock_gpio_table; +} + /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h new file mode 100644 index 00000000000..84020d7eb32 --- /dev/null +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OCTOPUS_CBI_SSFC__H_ +#define _OCTOPUS_CBI_SSFC__H_ + +#include + +/**************************************************************************** + * Octopus CBI Second Source Factory Cache + * + * SSFC was introduced after variants were MPed already so we can expect there + * can be devices in the field without SSFC field in the CBI. For devices + * without SSFC field in the CBI, the value of SSFC will be 0 set by get_ssfc() + * in the cbi_ssfc.c. + * + * On the other hand, taking audio codec as the example there are two sources - + * DA7219 and RT5682 used in the MPed devices before introducing SSFC. As a + * result, the value 0 of each bits group for a specific component is defined as + * DEFAULT and different variants should transform this DEFAULT to one of + * sources they used as the first sources. In the example here, either DA7219 or + * RT5682 should be transformed. + */ + +/* + * Audio Codec (Bits 9-11) + * + */ +enum ssfc_audio_codec { + SSFC_AUDIO_CODEC_DEFAULT, + SSFC_AUDIO_CODEC_DA7219, + SSFC_AUDIO_CODEC_RT5682, +}; +#define SSFC_AUDIO_CODEC_OFFSET 9 +#define SSFC_AUDIO_CODEC_MASK 0x7 + +enum ssfc_audio_codec ssfc_get_audio_codec(void); + +#endif /* _OCTOPUS_CBI_SSFC__H_ */ diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index f39a786f111..5f2c6e25bb2 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -10,6 +10,7 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ +const struct pad_config *mainboard_early_bootblock_gpio_table(size_t *num); const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index f1304f47208..9c9316c67a7 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,8 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) { + enum ssfc_audio_codec codec = ssfc_get_audio_codec(); + /* 2 Channel DMIC array. */ if (!nhlt_soc_add_dmic_array(nhlt, 2)) printk(BIOS_ERR, "Added 2CH DMIC array.\n"); @@ -19,13 +22,13 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) * Headset codec is bi-directional but uses the same configuration * settings for render and capture endpoints. */ - if (CONFIG(NHLT_DA7219)) { + if (CONFIG(NHLT_DA7219) && codec == SSFC_AUDIO_CODEC_DA7219) { /* Dialog for Headset codec */ if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); } - if (CONFIG(NHLT_RT5682)) { + if (CONFIG(NHLT_RT5682) && codec == SSFC_AUDIO_CODEC_RT5682) { /* Realtek for Headset codec */ if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added ALC5682 codec.\n"); diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index fd943775827..11fe9b5eecc 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -17,6 +17,10 @@ enum { static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), @@ -28,6 +32,10 @@ static const struct pad_config lte_override_table[] = { /* Default override table. */ PAD_NC(GPIO_104, UP_20K), + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 3c7187e048f..73adfef9ab6 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -165,6 +165,19 @@ chip soc/intel/apollolake register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 00e5d326e15..e48de7ceaa5 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -19,9 +19,13 @@ const char *mainboard_vbt_filename(void) switch (sku_id) { case SKU_9_HDMI: case SKU_19_HDMI_TS: + return "vbt_garg_hdmi.bin"; + case SKU_49_2A2C_TS: + case SKU_51_2A2C: + return "vbt_garfour.bin"; case SKU_50_HDMI: case SKU_52_HDMI_TS: - return "vbt_garg_hdmi.bin"; + return "vbt_garfour_hdmi.bin"; default: return "vbt.bin"; } diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 31cd64e2092..3aa8d9dac2f 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -10,6 +10,10 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), @@ -24,6 +28,11 @@ static const struct pad_config hdmi_sku_override_table[] = { /* HV_DDI1_DDC_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + + /* GPIO_137 -- HP_INT_ODL and would be amend by SSFC. */ + PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, + DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index a29d6fae7aa..87521413d10 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -181,6 +181,19 @@ chip soc/intel/apollolake register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end end # - I2C 5 device pci 17.2 on chip drivers/i2c/generic diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index e25f8fa0934..fb2936ac67d 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -171,6 +171,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "70" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 62e52c483fa..1cb45975c46 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -3,16 +3,15 @@ #include #include #include -#include #include #include "ec.h" #include -#include +#include #include "thermal.h" #include "onboard.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -22,10 +21,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif + if (CONFIG(CHROMEOS) && !parrot_ec_running_ro()) + gnvs_set_ecfw_rw(); /* EC handles all active thermal and fan control on Parrot. */ gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 61e51d0df35..a384d873873 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -25,13 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f0ffc9fe4cc..b7ed73c6cff 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -68,7 +68,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index 3aa58c35a61..f4187eb4f26 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -17,18 +17,18 @@ void parrot_ec_init(void) /* Report EC info */ /* EC version: cmd 0x51 - returns three bytes */ ec_kbc_write_cmd(0x51); - printk(BIOS_DEBUG," EC version %x.%x.%x\n", + printk(BIOS_DEBUG, " EC version %x.%x.%x\n", ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); /* EC Project name: cmd 0x52, 0xA0 - returns five bytes */ ec_kbc_write_cmd(0x52); ec_kbc_write_ib(0xA0); - printk(BIOS_DEBUG," EC Project: %c%c%c%c%c\n", - ec_kbc_read_ob(),ec_kbc_read_ob(),ec_kbc_read_ob(), + printk(BIOS_DEBUG, " EC Project: %c%c%c%c%c\n", + ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob()); /* Print the hardware revision */ - printk(BIOS_DEBUG," Parrot Revision %x\n", parrot_rev()); + printk(BIOS_DEBUG, " Parrot Revision %x\n", parrot_rev()); /* US Keyboard */ ec_kbc_write_cmd(0x59); diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 22e372dead8..c5fb853c36d 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include #include @@ -18,7 +18,7 @@ static u8 mainboard_smi_ec(void) ec_kbc_write_cmd(0x56); src = ec_kbc_read_ob(); - printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src); + printk(BIOS_DEBUG, "%s src: %x\n", __func__, src); switch (src) { case EC_BATTERY_CRITICAL: @@ -36,12 +36,11 @@ static u8 mainboard_smi_ec(void) void mainboard_smi_gpi(u32 gpi_sts) { - printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); + printk(BIOS_DEBUG, "%s: %x\n", __func__, gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ - while (mainboard_smi_ec() != EC_NO_EVENT); - } - else if (gpi_sts & (1 << EC_LID_GPI)) { + do {} while (mainboard_smi_ec() != EC_NO_EVENT); + } else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ @@ -51,7 +50,7 @@ void mainboard_smi_gpi(u32 gpi_sts) void mainboard_smi_sleep(u8 slp_typ) { - printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); + printk(BIOS_DEBUG, "%s: %x\n", __func__, slp_typ); /* Disable SCI and SMI events */ /* Clear pending events that may trigger immediate wake */ @@ -67,7 +66,7 @@ void mainboard_smi_sleep(u8 slp_typ) int mainboard_smi_apmc(u8 apmc) { - printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc); + printk(BIOS_DEBUG, "%s: %x\n", __func__, apmc); switch (apmc) { case APM_CNT_ACPI_ENABLE: printk(BIOS_DEBUG, "APMC: ACPI_EN\n"); diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 2656d281732..134246c173e 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -108,10 +108,6 @@ config MAINBOARD_PART_NUMBER default "Rammus" if BOARD_GOOGLE_RAMMUS default "Soraka" if BOARD_GOOGLE_SORAKA -config MAX_CPUS - int - default 8 - config OEM_BIN_FILE string "OEM ID table" default "" diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 3b545316259..9f36e794633 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -13,7 +13,6 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/poppy/bootblock.c b/src/mainboard/google/poppy/bootblock.c index efab9994dc2..b3afb18bb96 100644 --- a/src/mainboard/google/poppy/bootblock.c +++ b/src/mainboard/google/poppy/bootblock.c @@ -6,7 +6,7 @@ #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index a14e927b0f6..d3e351ad4f5 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -3,12 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = "50" - register "gpu_pp_cycle_delay_ms" = "600" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 600, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl index a390b615846..cfc84b53345 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl @@ -22,8 +22,8 @@ Scope (\_SB.PCI0.I2C2) ) }) - Name (_PR0, Package () { ^^I2C2.PMIC.OVTH }) - Name (_PR3, Package () { ^^I2C2.PMIC.OVTH }) + Name (_PR0, Package () { ^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH }) + Name (_PR3, Package () { ^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH }) /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index 17fb82b62dc..c3449a7f662 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -6,7 +6,7 @@ Scope (\_SB.PCI0.I2C3) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual(STA, 0)) { + If (STA == 0) { CTXS (GPIO_FCAM_RST_L) STXS (GPIO_FCAM_PWR_EN) STXS (GPIO_PCH_FCAM_CLK_EN) @@ -22,15 +22,15 @@ Scope (\_SB.PCI0.I2C3) * sequence completes */ Sleep (11) - Store (1, STA) + STA = 1 } } Method (_OFF, 0, Serialized) { - If (LEqual(STA, 1)) { + If (STA == 1) { CTXS (GPIO_PCH_FCAM_CLK_EN) CTXS (GPIO_FCAM_RST_L) CTXS (GPIO_FCAM_PWR_EN) - Store (0, STA) + STA = 0 } } Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl index a9349017cd9..0e31eee538f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl @@ -6,7 +6,7 @@ Scope (\_SB.PCI0.I2C5) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual(STA, 0)) { + If (STA == 0) { CTXS (GPIO_RCAM_RST_L) STXS (GPIO_RCAM_PWR_EN) STXS (GPIO_PCH_RCAM_CLK_EN) @@ -21,15 +21,15 @@ Scope (\_SB.PCI0.I2C5) * on sequence completes */ Sleep (12) - Store (1, STA) + STA = 1 } } Method (_OFF, 0, Serialized) { - If (LEqual(STA, 1)) { + If (STA == 1) { CTXS (GPIO_PCH_RCAM_CLK_EN) CTXS (GPIO_RCAM_RST_L) CTXS (GPIO_RCAM_PWR_EN) - Store (0, STA) + STA = 0 } } Method (_STA, 0, NotSerialized) { diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ff117c8aa26..162b437f329 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -3,12 +3,14 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = "500" - register "gpu_pp_cycle_delay_ms" = "600" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - register "gpu_pch_backlight_pwm_hz" = "1000" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 500, + .cycle_delay_ms = 600, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" # Deep Sx states register "deep_s3_enable_ac" = "0" diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index da2e4746145..e0d552476eb 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -6,8 +6,6 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-y += mainboard_smi.c - ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index dedec211225..161f68d7491 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -5,10 +5,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/smihandler.c similarity index 100% rename from src/mainboard/google/rambi/mainboard_smi.c rename to src/mainboard/google/rambi/smihandler.c diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index a115677773b..dd49610f89c 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -8,7 +8,6 @@ ramstage-y += ec.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c index 3e9f51afd01..0cbf3e62c26 100644 --- a/src/mainboard/google/reef/bootblock.c +++ b/src/mainboard/google/reef/bootblock.c @@ -3,17 +3,19 @@ #include #include #include -#include #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; - lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); +} + +void bootblock_mainboard_init(void) +{ mainboard_ec_init(); } diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index f87b96282ef..ecd44f6c926 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -25,6 +25,7 @@ DefinitionBlock( #include #include #include + #include } } diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index a1b7a4c335d..9aadc9ed528 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -125,7 +125,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 28203cfb5a0..6604a70cfe7 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -60,7 +60,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ - /* LPC */ + /* + * LPC + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ @@ -340,11 +343,28 @@ const struct pad_config * __weak variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 649293138d0..e8f8cc334ae 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -125,7 +125,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 87d3529d61c..01e4734e621 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -61,7 +61,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP), /* SMB_CLK */ PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ - /* LPC */ + /* + * LPC + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ @@ -341,11 +344,28 @@ const struct pad_config *variant_gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */ + + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 0dbaa295521..af459bebefc 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -134,7 +134,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index ba19369f185..91555ad6c8d 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -121,7 +121,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 3be68ddb5cc..d4e9705fc31 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -130,7 +130,9 @@ chip soc/intel/apollolake device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen + device pci 02.0 on # - Gen + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device pci 03.0 on end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9b0d25158ce..444234af459 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index e7bfc53aa09..e7c23b108bd 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -8,8 +8,6 @@ ramstage-y += sku.c romstage-y += romstage.c -smm-y += smihandler.c - bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/sarien/bootblock.c b/src/mainboard/google/sarien/bootblock.c index 5bd5d029fdd..2419a0084fb 100644 --- a/src/mainboard/google/sarien/bootblock.c +++ b/src/mainboard/google/sarien/bootblock.c @@ -5,7 +5,7 @@ #include #include -static void early_config_gpio(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *early_gpio_table; size_t num_gpios = 0; @@ -16,6 +16,5 @@ static void early_config_gpio(void) void bootblock_mainboard_init(void) { - early_config_gpio(); wilco_ec_early_init(); } diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index f4704faf86e..de97c686ee7 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -2,33 +2,12 @@ #include #include -#include #include #include #include #include #if CONFIG(GENERATE_SMBIOS_TABLES) -#define VPD_KEY_SYSTEM_SERIAL "serial_number" -#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number" -#define VPD_SERIAL_LEN 64 - -const char *smbios_system_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - -const char *smbios_mainboard_serial_number(void) -{ - static char serial[VPD_SERIAL_LEN]; - if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO)) - return serial; - return ""; -} - /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 8f75d72b15d..2a2541d477e 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -5,8 +5,6 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c - romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 666143cbe10..1198f4150e9 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -3,14 +3,12 @@ #include #include #include -#include -#include #include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -23,11 +21,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index a6fab83a5b1..d98954535fd 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -11,9 +11,6 @@ chip northbridge/intel/haswell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - register "ec_present" = "true" register "usb_xhci_on_resume" = "true" @@ -23,14 +20,6 @@ chip northbridge/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 7ac5ef7353b..81fcb0aafa5 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb index 7df0ca1a6f0..fc77345dab4 100644 --- a/src/mainboard/google/slippy/variants/falco/overridetree.cb +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) - register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) - register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + register "panel_cfg" = "{ + .up_delay_ms = 60, + .down_delay_ms = 60, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb index 6dee38e36e9..1d50086c58b 100644 --- a/src/mainboard/google/slippy/variants/leon/overridetree.cb +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index 689fee4cf34..e732a9270cf 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + register "panel_cfg" = "{ + .up_delay_ms = 40, + .down_delay_ms = 15, + .cycle_delay_ms = 400, + .backlight_on_delay_ms = 210, + .backlight_off_delay_ms = 210, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb index de61839cc7e..824694720dd 100644 --- a/src/mainboard/google/slippy/variants/wolf/overridetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -1,11 +1,13 @@ chip northbridge/intel/haswell - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) - register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) - register "gpu_panel_power_down_delay" = "500" # 50ms (T10) - register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" device domain 0 on diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index f547fd01f19..852e73de673 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -203,8 +203,8 @@ struct chip_operations mainboard_ops = { void lb_board(struct lb_header *header) { -#if CONFIG(CHROMEOS) - lb_table_add_serialno_from_vpd(header); -#endif + if (CONFIG(CHROMEOS)) + lb_table_add_serialno_from_vpd(header); + soc_add_mtc(header); } diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 57fc1d07fa0..6a89be04dfe 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -110,8 +110,7 @@ void lb_board(struct lb_header *header) dma->range_start = (uintptr_t)_dma_coherent; dma->range_size = REGION_SIZE(dma_coherent); -#if CONFIG(CHROMEOS) /* Retrieve the switch interface MAC addresses. */ - lb_table_add_macs_from_vpd(header); -#endif + if (CONFIG(CHROMEOS)) + lb_table_add_macs_from_vpd(header); } diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 5c196f07f08..a773a2d7ddc 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -5,7 +5,6 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c -smm-y += mainboard_smi.c smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index f994e57912d..fe12e30ccdd 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -3,17 +3,16 @@ #include #include #include -#include #include #include #include "ec.h" #include "onboard.h" #include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Disable USB ports in S3 by default */ gnvs->s3u0 = 0; @@ -23,10 +22,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG(CHROMEOS) - gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif + if (CONFIG(CHROMEOS) && !get_recovery_mode_switch()) + gnvs_set_ecfw_rw(); /* EC handles all thermal and fan control on Stout. */ gnvs->tcrt = CRITICAL_TEMPERATURE; diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index bd91506b396..5461b15dd9f 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -27,13 +27,9 @@ chip northbridge/intel/sandybridge register "tcc_offset" = "5" # TCC of 95C - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/smihandler.c similarity index 98% rename from src/mainboard/google/stout/mainboard_smi.c rename to src/mainboard/google/stout/smihandler.c index ef4b4cd1cad..d282bc7f237 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/smihandler.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 989bf6902e5..d6b1836f9d2 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -12,6 +12,9 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_SD_CD_L); gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); gpio_output(GPIO_AMP_ENABLE, 0); + gpio_output(GPIO_BACKLIGHT_ENABLE, 0); + gpio_output(GPIO_EN_PP3300_DX_EDP, 0); + gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -27,6 +30,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) "SD card detect"}, {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), "speaker enable"}, + {GPIO_BACKLIGHT_ENABLE.addr, ACTIVE_HIGH, + gpio_get(GPIO_BACKLIGHT_ENABLE), "backlight"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 0f469e065b8..7465c636271 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -102,9 +102,6 @@ static void display_startup(void) return; printk(BIOS_INFO, "display init!\n"); - - /* Configure backlight */ - gpio_output(GPIO_BACKLIGHT_ENABLE, 1); display_init(&ed); fb_new_framebuffer_info_from_edid(&ed, (uintptr_t)0); } else diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index c776ba1912f..cfe8dde46e8 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select EC_GOOGLE_CHROMEEC_LPC select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 8777994ae72..0dcb64ff28a 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -22,7 +22,7 @@ config BOARD_GOOGLE_LINDAR select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM - select CHROMEOS_DSM_CALIB + select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_MALEFOR @@ -96,7 +96,9 @@ config BOARD_GOOGLE_VOEMA config BOARD_GOOGLE_DROBIT bool "-> Drobit" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU config BOARD_GOOGLE_COPANO bool "-> Copano" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index c01f993d026..1847d56b6a1 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -11,8 +11,6 @@ ramstage-y += ec.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += mainboard.c -smm-y += smihandler.c - verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c index 328480e3bcd..6ee655ee587 100644 --- a/src/mainboard/google/volteer/bootblock.c +++ b/src/mainboard/google/volteer/bootblock.c @@ -3,7 +3,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 67d3489b03f..f3fb454eb3f 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -14,13 +14,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct ddr_memory_cfg *board_cfg = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *board_cfg = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 01bbf1e06bd..d74476af165 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -221,16 +221,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkSndwEnable[1]" = "0" # TCSS USB3 + register "UsbTcPortEn" = "0x3" register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" - register "IomTypeCPortPadCfg[0]" = "0x09000000" - register "IomTypeCPortPadCfg[1]" = "0x09000000" - register "IomTypeCPortPadCfg[2]" = "0x09000000" - register "IomTypeCPortPadCfg[3]" = "0x09000000" - register "IomTypeCPortPadCfg[4]" = "0x09000000" - register "IomTypeCPortPadCfg[5]" = "0x09000000" - register "IomTypeCPortPadCfg[6]" = "0x09000000" - register "IomTypeCPortPadCfg[7]" = "0x09000000" # DP port register "DdiPortAConfig" = "1" # eDP diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 922d3d1def7..5ae3a02a431 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -308,7 +308,7 @@ static const struct pad_config gpio_table[] = { /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H11 : SRCCLKREQ5# ==> NC */ PAD_NC(GPP_H11, NONE), /* H12 : M2_SKT2_CFG0 ==> NONE */ @@ -398,6 +398,11 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 4d5dc87cb9e..2431c59cdca 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct ddr_memory_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); int variant_memory_sku(void); /* Modify devictree settings during ramstage. */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b3a60..1998a1fb27e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -4,64 +4,59 @@ #include #include -static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { - /* DQ CPU<>DRAM map */ - .dq_map = { - [0] = { - { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &baseboard_lpddr4x_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/copano/Makefile.inc b/src/mainboard/google/volteer/variants/copano/Makefile.inc new file mode 100644 index 00000000000..343c7dbb954 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/copano/gpio.c b/src/mainboard/google/volteer/variants/copano/gpio.c new file mode 100644 index 00000000000..d5498d0748d --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/gpio.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/copano/memory.c b/src/mainboard/google/volteer/variants/copano/memory.c new file mode 100644 index 00000000000..b4414d4019e --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = true, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc index 511ab5b2341..7b9a85e0d69 100644 --- a/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc @@ -2,6 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE, MT53D512M64D4NW-046 WT:F +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53D512M64D4NW-046 WT:F, H9HCNNNCRMBLPR-NEE SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53D1G64D4NW-046 WT:A SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNFBMBLPR-NEE diff --git a/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt index a8b78f56251..413301e52c3 100644 --- a/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt @@ -1,6 +1,5 @@ DRAM Part Name ID to assign -MT53E512M64D4NW-046 WT:E 0 (0000) +MT53D512M64D4NW-046 WT:F 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) -MT53D512M64D4NW-046 WT:F 0 (0000) diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt index 4afc39046c6..c1d262300c8 100644 --- a/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt @@ -1,5 +1,4 @@ -MT53E512M64D4NW-046 WT:E +MT53D512M64D4NW-046 WT:F H9HCNNNCRMBLPR-NEE MT53D1G64D4NW-046 WT:A H9HCNNNFBMBLPR-NEE -MT53D512M64D4NW-046 WT:F diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 32204c58e7d..d4e07460a20 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -1,6 +1,212 @@ chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0000"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end - end diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5571ee87ca8..dbf4677511a 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -125,6 +125,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 9d8ad405ce0..6ccb5034d68 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -2,64 +2,59 @@ #include -static const struct lpddr4x_cfg delbin_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &delbin_memcfg + .ect = true, }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 577404737b6..5e9600b26f4 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -51,7 +51,9 @@ chip soc/intel/tigerlake .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_56P3MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + .type_c = 1, }" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Acoustic settings register "AcousticNoiseMitigation" = "1" @@ -67,7 +69,7 @@ chip soc/intel/tigerlake register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 15, + .tdp_pl1_override = 18, .tdp_pl2_override = 51, .tdp_pl4 = 105, }" @@ -102,11 +104,11 @@ chip soc/intel/tigerlake [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" ## Power Limits Control - # 3-15W PL1 in 200mW increments, avg over 28-32s interval - # PL2 is 15-51W, avg over 28-32s interval + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is 51W, avg over 28-32s interval register "controls.power_limits" = "{ - .pl1 = {.min_power = 3000, - .max_power = 15000, + .pl1 = {.min_power = 12000, + .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, diff --git a/src/mainboard/google/volteer/variants/drobit/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/Makefile.inc new file mode 100644 index 00000000000..343c7dbb954 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/drobit/gpio.c b/src/mainboard/google/volteer/variants/drobit/gpio.c new file mode 100644 index 00000000000..8feadff3c00 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/gpio.c @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E10 : USB_C0_AUXP_DC ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E13 : USB_C0_AUXN_DC ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F11 : GPPF11_THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H8 : I2C4_SDA ==> PCB_ID0 */ + PAD_CFG_GPI(GPP_H8, NONE, DEEP), + /* H9 : I2C4_SCL ==> PCB_ID1 */ + PAD_CFG_GPI(GPP_H9, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT# */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/drobit/memory.c b/src/mainboard/google/volteer/variants/drobit/memory.c new file mode 100644 index 00000000000..2b4ec290924 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = true, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc index b0ca2223a81..c0e2fffb6b8 100644 --- a/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt index fa247902eee..b5bd3ef2b63 100644 --- a/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt @@ -1 +1,5 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt new file mode 100644 index 00000000000..b99b8110537 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53E512M32D2NP-046 WT:E +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 32204c58e7d..96c109fbb5e 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -1,6 +1,221 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + + register "tcc_offset" = "8" + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | MISC | + #| I2C3 | Camera | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2701"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port4 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + end + end + end end - end diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index e92f6b100ba..6810ba50b6c 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -24,7 +24,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ @@ -164,6 +164,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c index 577734dbcf7..04dbe4492e1 100644 --- a/src/mainboard/google/volteer/variants/eldrid/memory.c +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -4,16 +4,11 @@ #include #include -/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ -static const struct mb_ddr4_cfg eldrid_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_DDR4, - .ddr4_cfg = &eldrid_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 1b86e0ef6cb..37e0ab9efc4 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -66,17 +66,29 @@ chip soc/intel/tigerlake register "usb2_ports[2]" = "USB2_PORT_EMPTY" #improve the USB2 Port1 eye diagram - register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_39P35MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_39P35MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }" #lower camera driving register "usb2_ports[4]" = "{ .enable = 1, - .tx_bias = 0, - .tx_emp_enable = 0, - .pre_emp_bias = 0, - .pre_emp_bit = 0, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_EMP_OFF, + .pre_emp_bias = USB2_BIAS_0MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, }" + #Type-A / Type-C C0 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" + device domain 0 on device ref dptf on # DPTF Policy for Eldrid board @@ -175,6 +187,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c index ecb3c1985fb..bbdb517bb1d 100644 --- a/src/mainboard/google/volteer/variants/elemi/gpio.c +++ b/src/mainboard/google/volteer/variants/elemi/gpio.c @@ -178,6 +178,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c index 32b7abca171..8ec6996d11a 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory.c +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -4,16 +4,11 @@ #include #include -/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ -static const struct mb_ddr4_cfg elemi_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_DDR4, - .ddr4_cfg = &elemi_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index af58b81701a..2c36bc9dd7e 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -36,9 +36,21 @@ chip soc/intel/tigerlake }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 75, + .sda_hold = 36, + }, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 75, + .sda_hold = 36, + }, }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -48,10 +60,77 @@ chip soc/intel/tigerlake }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, }" + # Disable M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + + # Type-A / Type-C C1 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" + + # Type-A / Type-C C0 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" + device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 70, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 6000)}" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 70, SHUTDOWN)}" + + ## Power Limits Control + # 3-17W PL1 in 200mW increments, avg over 28-32s interval + # PL2 set to 60W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 17000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 60000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6500, 220, 2200, }, + [1] = { 90, 5900, 180, 1800, }, + [2] = { 80, 5400, 145, 1450, }, + [3] = { 70, 4900, 115, 1150, }, + [4] = { 63, 4600, 90, 900, }, + [5] = { 58, 4300, 55, 550, }, + [6] = { 54, 4100, 30, 300, }, + [7] = { 50, 3800, 15, 150, }, + [8] = { 45, 3500, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 + device ref north_xhci on chip drivers/usb/acpi device ref tcss_root_hub on diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 378c150202a..c98003b2cf2 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -196,6 +196,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c index edbb681a4e2..ef039a4526c 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -2,64 +2,61 @@ #include -static const struct lpddr4x_cfg halvor_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ + .dq1 = { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &halvor_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/lindar/gpio.c b/src/mainboard/google/volteer/variants/lindar/gpio.c index 1d3d693e465..44e3148e287 100644 --- a/src/mainboard/google/volteer/variants/lindar/gpio.c +++ b/src/mainboard/google/volteer/variants/lindar/gpio.c @@ -107,6 +107,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c index 11bcf4ca890..f9350d14712 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory.c +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -2,64 +2,60 @@ #include -static const struct lpddr4x_cfg lindar_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &lindar_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 70e432d55a0..3140b85e462 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -6,14 +6,13 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[1]" = "0x090E000D" # USB Port Config register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 - register "SaGv" = "SaGv_Disabled" #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -157,6 +156,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A22)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/malefor/gpio.c b/src/mainboard/google/volteer/variants/malefor/gpio.c index 24989816545..3a9808121b1 100644 --- a/src/mainboard/google/volteer/variants/malefor/gpio.c +++ b/src/mainboard/google/volteer/variants/malefor/gpio.c @@ -153,6 +153,11 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 2c879e09b4d..f9350d14712 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -2,64 +2,60 @@ #include -static const struct lpddr4x_cfg malefor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &malefor_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index d5498d0748d..80e1b964eaf 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -139,7 +139,7 @@ static const struct pad_config override_gpio_table[] = { /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -187,6 +187,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 7d956588911..b4414d4019e 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -2,64 +2,61 @@ #include -static const struct lpddr4x_cfg terrador_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &terrador_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c index 40d25a52c7b..5611ccabae1 100644 --- a/src/mainboard/google/volteer/variants/todor/gpio.c +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -147,7 +147,7 @@ static const struct pad_config override_gpio_table[] = { /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -195,6 +195,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index c8b4ab4e3cf..b4414d4019e 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -2,64 +2,61 @@ #include -static const struct lpddr4x_cfg todor_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &todor_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/trondo/gpio.c b/src/mainboard/google/volteer/variants/trondo/gpio.c index a54aeca16a9..11b051b8e81 100644 --- a/src/mainboard/google/volteer/variants/trondo/gpio.c +++ b/src/mainboard/google/volteer/variants/trondo/gpio.c @@ -17,7 +17,10 @@ const struct pad_config *variant_base_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c index d905daec700..da8526093d3 100644 --- a/src/mainboard/google/volteer/variants/voema/gpio.c +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -137,7 +137,7 @@ static const struct pad_config override_gpio_table[] = { /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ @@ -185,6 +185,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/voema/memory.c b/src/mainboard/google/volteer/variants/voema/memory.c index b611af5161d..b4414d4019e 100644 --- a/src/mainboard/google/volteer/variants/voema/memory.c +++ b/src/mainboard/google/volteer/variants/voema/memory.c @@ -2,64 +2,61 @@ #include -static const struct lpddr4x_cfg voema_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &voema_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 9efcdb22f33..86b71ee9a48 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,11 +5,26 @@ chip soc/intel/tigerlake # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" - # Disable SRCCLKREQ1# and SRCCLKREQ3# + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 1 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Port 0 + + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + + # Disable WLAN PCIE 7 + register "PcieRpEnable[6]" = "0" + register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + # Disable SD Card PCIE 8 + register "PcieRpEnable[7]" = "0" + register "PcieRpLtrEnable[7]" = "0" + register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" device domain 0 on + device ref ipu on end # IPU device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -81,6 +96,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. @@ -89,8 +112,6 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "1" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index 0d230fd96c2..0dab148cc11 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -208,6 +208,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index cfd9e8b1f67..262c0161acd 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -210,6 +210,11 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/voxel/gpio.c b/src/mainboard/google/volteer/variants/voxel/gpio.c index d6df489f0d6..b8d1f399363 100644 --- a/src/mainboard/google/volteer/variants/voxel/gpio.c +++ b/src/mainboard/google/volteer/variants/voxel/gpio.c @@ -237,6 +237,11 @@ const struct pad_config *variant_override_gpio_table(size_t *num) /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C8 : UART0 RX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0 TX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 40b108660d3..fe2b2b1999b 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -2,64 +2,61 @@ #include -static const struct lpddr4x_cfg voxel_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ - { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ - { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ - { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ - { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ - { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ - { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ - { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &voxel_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2caec2a7c62..82f0bfd09ec 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -13,6 +13,9 @@ chip soc/intel/tigerlake .tdp_pl4 = 105, }" + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C Cl + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-A / Type-C C0 + # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 88d6e97651f..4fce3b86162 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select ELOG select ELOG_BOOT_COUNT select ELOG_GSMI - select HAVE_ACPI_TABLES select GFXUMA select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 96c97b68d38..8a9d7af89af 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -11,8 +11,6 @@ ramstage-y += sku_id.c verstage-y += verstage.c -smm-y += smihandler.c - subdirs-y += variants/baseboard subdirs-y += spd diff --git a/src/mainboard/google/zork/acpi_tables.c b/src/mainboard/google/zork/acpi_tables.c new file mode 100644 index 00000000000..ab36f40a350 --- /dev/null +++ b/src/mainboard/google/zork/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index dce2eafe4e8..1de593ed49f 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -17,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -50,43 +48,31 @@ static uint8_t fch_apic_routing[0x80]; _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), "PIC and APIC FCH interrupt tables must be the same size"); -/* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - /* * This controls the device -> IRQ routing. - * The PIC values are limited to 0,1, 3 - 12, 14, 15. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 <- ec/google/chromeec/acpi/superio.asl + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + * 12: i8042 <- ec/google/chromeec/acpi/superio.asl */ static const struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; uint8_t apic_irq_num; } fch_pirq[] = { - { PIRQ_A, 6, 16 }, - { PIRQ_B, 6, 17 }, - { PIRQ_C, 14, 18 }, - { PIRQ_D, 15, 19 }, + { PIRQ_A, 6, PIRQ_NC }, + { PIRQ_B, 13, PIRQ_NC }, + { PIRQ_C, 14, PIRQ_NC }, + { PIRQ_D, 15, PIRQ_NC }, + { PIRQ_E, 15, PIRQ_NC }, + { PIRQ_F, 14, PIRQ_NC }, + { PIRQ_G, 13, PIRQ_NC }, + { PIRQ_H, 6, PIRQ_NC }, + { PIRQ_SCI, 9, 9 }, { PIRQ_EMMC, 5, 5 }, { PIRQ_GPIO, 7, 7 }, @@ -121,9 +107,6 @@ static void init_tables(void) static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } @@ -231,16 +214,6 @@ static void zork_enable(struct device *dev) static void mainboard_final(void *chip_info) { - struct global_nvs *gnvs; - - gnvs = acpi_get_gnvs(); - - if (gnvs) { - gnvs->tmps = CTL_TDP_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - } - finalize_gpios(acpi_get_sleep_type()); } diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 0b64855dad6..e014ce302cc 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -338,12 +338,6 @@ chip soc/amd/picasso end end end - chip ec/google/chromeec/i2c_tunnel - register "name" = ""MSTH"" - register "uid" = "1" - register "remote_bus" = "9" - device generic 1.0 on end - end chip ec/google/chromeec/audio_codec register "uid" = "1" device generic 0 on end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 4181b4ad81f..40e2ed5223c 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -347,7 +347,7 @@ chip soc/amd/picasso chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel - register "uid" = "1" + register "uid" = "0" register "remote_bus" = "8" device generic 0.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d12a8ed4077..00e7a033cb8 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -40,12 +40,15 @@ enum { /* SD controller type */ FW_CONFIG_MASK_SD_CTRLR = 0x7, FW_CONFIG_SHIFT_SD_CTRLR = 20, - /* SPI speed value */ - FW_CONFIG_MASK_SPI_SPEED = 0xf, - FW_CONFIG_SHIFT_SPI_SPEED = 23, + /* SAR presence */ + FW_CONFIG_MASK_SAR = 0x7, + FW_CONFIG_SHIFT_SAR = 23, /* Fan information */ FW_CONFIG_MASK_FAN = 0x3, FW_CONFIG_SHIFT_FAN = 27, + /* WWAN presence */ + FW_CONFIG_MASK_WWAN = 0x1, + FW_CONFIG_SHIFT_WWAN = 29, }; static int get_fw_config(uint64_t *val) @@ -78,6 +81,11 @@ static unsigned int extract_field(uint64_t mask, int shift) return (fw_config >> shift) & mask; } +int variant_gets_sar_config(void) +{ + return extract_field(FW_CONFIG_MASK_SAR, FW_CONFIG_SHIFT_SAR); +} + int variant_has_emmc(void) { return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC); @@ -88,6 +96,11 @@ int variant_has_nvme(void) return !!extract_field(FW_CONFIG_MASK_NVME, FW_CONFIG_SHIFT_NVME); } +int variant_has_wwan(void) +{ + return !!extract_field(FW_CONFIG_MASK_WWAN, FW_CONFIG_SHIFT_WWAN); +} + bool variant_uses_v3_schematics(void) { uint32_t board_version; diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index dc06a7843f2..46177fccfb8 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -38,7 +38,8 @@ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index f6e7e7c232a..ac600de2550 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -59,10 +59,14 @@ const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num); const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num); /* Retrieve attributes from FW_CONFIG in CBI. */ +/* Return value of SAR config. */ +int variant_gets_sar_config(void); /* Return 0 if non-existent, 1 if present. */ int variant_has_emmc(void); /* Return 0 if non-existent, 1 if present. */ int variant_has_nvme(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_wwan(void); /* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */ int boot_is_factory_unprovisioned(void); diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc index 1f871a983b9..9c661323cc0 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -6,7 +6,7 @@ SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = K4A8G165WC-BCTD SPD_SOURCES += ddr4-spd-8.hex # ID = 1(0b0001) Parts = K4AAG165WA-BCTD SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC -SPD_SOURCES += ddr4-spd-empty.hex # ID = 4(0b0100) +SPD_SOURCES += ddr4-spd-9.hex # ID = 4(0b0100) Parts = H5ANAG6NCJR-XNC SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = K4A8G165WC-BCWE SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NCMR-XNC diff --git a/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt index 2522cdb3deb..f475d9f1504 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt @@ -7,3 +7,4 @@ MT40A1G16KD-062E:E 6 (0110) H5ANAG6NCMR-XNC 7 (0111) K4AAG165WA-BCWE 8 (1000) K4AAG165WA-BCTD 1 (0001) +H5ANAG6NCJR-XNC 4 (0100) diff --git a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt index 1e5ee8a961b..2af091fc8c7 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt @@ -15,3 +15,4 @@ MT40A1G16KD-062E:E, 6 H5ANAG6NCMR-XNC, 7 K4AAG165WA-BCWE, 8 K4AAG165WA-BCTD +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index efd1dfc1fa7..554cdeac943 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -12,7 +12,7 @@ chip soc/amd/picasso register "slow_ppt_limit_mW" = "6000" register "fast_ppt_limit_mW" = "9000" register "slow_ppt_time_constant_s" = "5" - register "stapm_time_constant_s" = "2500" + register "stapm_time_constant_s" = "1640" register "sustained_power_limit_mW" = "4800" register "telemetry_vddcr_vdd_slope_mA" = "42465" @@ -21,6 +21,45 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration + # USB 2.0 strength - MB type-C C0 + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xe, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB 2.0 strength - DB type-A + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x0, + .tx_vref_tune = 0xe, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB 2.0 strength - DB type-C C1 + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x0, + .tx_vref_tune = 0xe, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/zork/variants/gumboz/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/Makefile.inc index 295acd25c94..51d19fe9bab 100644 --- a/src/mainboard/google/zork/variants/gumboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/gumboz/Makefile.inc @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./spd + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/gumboz/gpio.c b/src/mainboard/google/zork/variants/gumboz/gpio.c new file mode 100644 index 00000000000..aac25bb353f --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/gpio.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; +} diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f2774..00000000000 --- a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl deleted file mode 100644 index a1161edb5fd..00000000000 --- a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb index 1cc2364f5e9..73a4a282ffe 100644 --- a/src/mainboard/google/zork/variants/gumboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-or-later - chip soc/amd/picasso # Start : OPN Performance Configuration @@ -16,27 +15,113 @@ chip soc/amd/picasso register "stapm_time_constant_s" = "2500" register "sustained_power_limit_mW" = "4800" + register "telemetry_vddcr_vdd_slope_mA" = "42465" + register "telemetry_vddcr_vdd_offset" = "69" + register "telemetry_vddcr_soc_slope_mA" = "42667" + register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration - # I2C2 for touchscreen and trackpad + # USB 2.0 strength - MB type-C C0 + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0xe, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB 2.0 strength - DB type-A + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x0, + .tx_vref_tune = 0xe, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB 2.0 strength - DB type-C C1 + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x07, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x0, + .tx_vref_tune = 0xe, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ }" # I2C3 for H1 - register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ .early_init = true, }" + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + .init_khz_preset = 400, + }" + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit end # domain device mmio 0xfedc4000 on # APU_I2C2_BASE - end # device - + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "generic.reset_delay_ms" = "50" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc index 3edeb9606cb..6d8a906c98b 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc @@ -1,5 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = ddr4-spd-empty.hex +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD +SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) +SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += ddr4-spd-2.hex # ID = 6(0b0110) Parts = H5ANAG6NCMR-XNC +SPD_SOURCES += ddr4-spd-1.hex # ID = 7(0b0111) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = MT40A1G16KD-062E:E +SPD_SOURCES += ddr4-spd-8.hex # ID = 9(0b1001) Parts = K4AAG165WA-BCTD +SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = K4AAG165WA-BCWE diff --git a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt index fa247902eee..d6d5d091947 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt @@ -1 +1,10 @@ DRAM Part Name ID to assign +K4A8G165WC-BCTD 2 (0010) +K4A8G165WC-BCWE 4 (0100) +H5AN8G6NDJR-XNC 5 (0101) +H5ANAG6NCMR-XNC 6 (0110) +MT40A512M16TB-062E:J 7 (0111) +MT40A1G16KD-062E:E 8 (1000) +K4AAG165WA-BCTD 9 (1001) +K4AAG165WA-BCWE 10 (1010) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt index 106a705a364..e5cd7e29989 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt @@ -7,3 +7,13 @@ # See util/spd_tools/ddr4/README.md for more details and instructions. # Part Name, Fixed ID (optional) +# Gumboz shares the same DRAM IDs as Dirinboz since two variants use the same PCB. +K4A8G165WC-BCTD, 2 +K4A8G165WC-BCWE, 4 +H5AN8G6NDJR-XNC, 5 +H5ANAG6NCMR-XNC, 6 +MT40A512M16TB-062E:J, 7 +MT40A1G16KD-062E:E, 8 +K4AAG165WA-BCTD, 9 +K4AAG165WA-BCWE, 10 +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/zork/variants/gumboz/variant.c b/src/mainboard/google/zork/variants/gumboz/variant.c new file mode 100644 index 00000000000..ff57f503a50 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/variant.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); +} diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h index 3afa327935c..3564d542cd3 100644 --- a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -14,7 +14,8 @@ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) /* Enable trackpoint S3 wakeups */ #define MAINBOARD_EC_S3_DEVICE_EVENTS \ (EC_DEVICE_EVENT_MASK(EC_DEVICE_EVENT_TRACKPAD)) diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc index 2eb864df2b4..805ede4975d 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-7.hex # ID = 0(0b0000) Parts = K4AAG165WA-BCWE +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E diff --git a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt index 7210071bd16..b0610003378 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/dram_id.generated.txt @@ -1,5 +1,4 @@ DRAM Part Name ID to assign -K4AAG165WA-BCWE 0 (0000) MT40A512M16TB-062E:J 2 (0010) MT40A1G16KD-062E:E 3 (0011) K4A8G165WC-BCWE 4 (0100) @@ -8,3 +7,4 @@ MT40A512M16TB-062E:J 6 (0110) K4AAG165WA-BCWE 7 (0111) H5ANAG6NCMR-XNC 8 (1000) K4A8G165WC-BCWE 9 (1001) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt index 329763962e2..87bbb36613d 100644 --- a/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/morphius/spd/mem_parts_used.txt @@ -7,7 +7,6 @@ # See util/spd_tools/ddr4/README.md for more details and instructions. # Part Name, Fixed ID (optional) -K4AAG165WA-BCWE, 0 MT40A512M16TB-062E:J, 2 MT40A1G16KD-062E:E, 3 K4A8G165WC-BCWE, 4 @@ -16,3 +15,4 @@ MT40A512M16TB-062E:J, 6 K4AAG165WA-BCWE, 7 H5ANAG6NCMR-XNC, 8 K4A8G165WC-BCWE, 9 +H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/zork/variants/shuboz/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/Makefile.inc index 2a8f0f72ed6..e5ec76de14e 100644 --- a/src/mainboard/google/zork/variants/shuboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/shuboz/Makefile.inc @@ -2,3 +2,4 @@ subdirs-y += ./spd ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 1cc2364f5e9..7160899267a 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -13,21 +13,30 @@ chip soc/amd/picasso register "slow_ppt_limit_mW" = "6000" register "fast_ppt_limit_mW" = "9000" register "slow_ppt_time_constant_s" = "5" - register "stapm_time_constant_s" = "2500" + register "stapm_time_constant_s" = "1400" register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration + register "telemetry_vddcr_vdd_slope_mA" = "30518" + register "telemetry_vddcr_vdd_offset" = "435" + register "telemetry_vddcr_soc_slope_mA" = "22965" + register "telemetry_vddcr_soc_offset" = "165" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ }" # I2C3 for H1 register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ .early_init = true, }" @@ -37,6 +46,25 @@ chip soc/amd/picasso end # domain device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end end # device - end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c new file mode 100644 index 00000000000..8a84a75f2fb --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); +} diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a3c2c978cf5..c3afe1372ad 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -23,6 +23,28 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_slope_mA" = "20001" register "telemetry_vddcr_soc_offset" = "168" + # eDP phy tuning settings + register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + + # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, + # and "0" as default value + register "edp_pwr_adjust_enable" = "1" + register "pwron_digon_to_de" = "0" + register "pwron_de_to_varybl" = "0" + register "pwrdown_varybloff_to_de" = "0" + register "pwrdown_de_to_digoff" = "0" + register "pwroff_delay" = "0" + register "pwron_varybl_to_blon" = "5" + register "pwrdown_bloff_to_varybloff" = "5" + register "min_allowed_bl_level" = "0" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x0, + .deemph_6db4 = 0x004b, + .boostadj = 0x0, + .margin_deemph = 0x80, + }" + # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 @@ -108,7 +130,7 @@ chip soc/amd/picasso register "generic.reset_off_delay_ms" = "2" register "generic.reset_delay_ms" = "20" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" - register "generic.stop_delay_ms" = "100" + register "generic.stop_delay_ms" = "160" register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index cbc160e5c77..3816aac2038 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -2,6 +2,8 @@ #include #include +#include +#include static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP @@ -31,3 +33,60 @@ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *soc_cfg; + soc_cfg = config_of_soc(); + + /* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */ + if (variant_has_wwan()) + soc_cfg->acp_i2s_use_external_48mhz_osc = 1; +} + +/* ++----------+------+--------+--------+------+--+---------+--+---------+ +| |Vilboz|Vilboz14|Vilboz14|Vilboz|NA|Vilboz360|NA|Vilboz360| +| |WiFi |WiFi |LTE |LTE | |WiFi | |LTE | ++----------+------+--------+--------+------+--+---------+--+---------+ +|SAR[26] |0 |0 |0 |0 |0 |0 |0 |0 | +|SAR[25] |0 |0 |0 |0 |1 |1 |1 |1 | +|SAR[24] |0 |0 |1 |1 |0 |0 |1 |1 | +|SAR[23] |0 |1 |0 |1 |0 |1 |0 |1 | ++----------+------+--------+--------+------+--+---------+--+---------+ +|SAR_config|0 |1 |2 |3 |4 |5 |6 |7 | ++----------+------+--------+--------+------+--+---------+--+---------+ +*/ + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + int sar_config; + + sar_config = variant_gets_sar_config(); + + switch (sar_config) { + case 1: + filename = "wifi_sar-vilboz-0.hex"; + break; + case 3: + /* + TODO: Set default first. It will be replaced after the + new table is generated. + */ + filename = "wifi_sar_defaults.hex"; + break; + case 5: + filename = "wifi_sar-vilboz-1.hex"; + break; + case 7: + /* + TODO: Set default first. It will be replaced after the + new table is generated. + */ + filename = "wifi_sar_defaults.hex"; + break; + } + + return filename; +} diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 7bd312803ed..fbff203d688 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -8,12 +8,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/hp/folio_9480m/acpi_tables.c b/src/mainboard/hp/folio_9480m/acpi_tables.c index 00963e10b08..7aac816f325 100644 --- a/src/mainboard/hp/folio_9480m/acpi_tables.c +++ b/src/mainboard/hp/folio_9480m/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->lids = 1; diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 140aa844f5f..a56a48b1ee7 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -4,23 +4,17 @@ chip northbridge/intel/haswell register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" - register "gpu_panel_power_backlight_off_delay" = "1" - register "gpu_panel_power_backlight_on_delay" = "1" - register "gpu_panel_power_cycle_delay" = "6" - register "gpu_panel_power_down_delay" = "500" - register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight_pwm_hz" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 200, + }" register "usb_xhci_on_resume" = "true" device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_battery" = "2" - register "c2_battery" = "3" - register "c3_battery" = "9" - - register "c1_acpower" = "2" - register "c2_acpower" = "3" - register "c3_acpower" = "9" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index dd4c42b968f..1fb15968c16 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -7,8 +7,7 @@ #include #include -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -41,10 +40,9 @@ static const CODEC_ENTRY Parmer_Alc272_VerbTbl[] = { {0xff, 0xffffffff} }; -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Parmer_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +static const CODEC_TBL_LIST CodecTableList[] = { + {0x10ec0272, (CODEC_ENTRY *)&Parmer_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} }; #define FAN_INPUT_INTERNAL_DIODE 0 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 77ae870b6c5..5d42edabf4e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -8,5 +8,3 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += ec.c - -smm-y += mainboard_smi.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 95f2c93004d..b6cdc867aef 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -183,15 +183,14 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) * data from the table. Otherwise, it will use its default conservative settings */ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PSO_END }; void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index c620be253e7..e4c60d15c90 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -8,20 +8,30 @@ #include u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F + 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F }; u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 }; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) @@ -73,20 +83,20 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + for (byte = 0x0; byte < sizeof(picr_data); byte++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + for (byte = 0x0; byte < sizeof(intr_data); byte++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/smihandler.c similarity index 100% rename from src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c rename to src/mainboard/hp/pavilion_m6_1035dx/smihandler.c diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c index 8999b7297c1..06ca470083e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c +++ b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index acdd4b34960..c1e80c858b8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -17,12 +17,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x02880288" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c +++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index bfabacce6cf..61535df242c 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -8,12 +8,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c deleted file mode 100644 index 52c2fbbec13..00000000000 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - -} diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 369ce21e05b..35224a14ce8 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -75,7 +75,7 @@ config ADL_CHROME_EC config ADL_INTEL_EC bool "Intel EC" select EC_ACPI - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT endchoice config PCIEXP_HOTPLUG_BUSES @@ -93,7 +93,6 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA - select HAS_RECOVERY_MRC_CACHE config UART_FOR_CONSOLE int diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index de924067d1a..75c8cf8e209 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -13,8 +13,6 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c romstage-y += memory.c -smm-y += smihandler.c - ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 48666629db4..e8755ba49e5 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,5 +1,5 @@ FLASH@0xfe000000 32M { - SI_ALL 0x1081000 { + SI_ALL@0x0 0x1000000 { SI_DESC 0x1000 SI_EC 0x80000 SI_ME @@ -16,7 +16,7 @@ FLASH@0xfe000000 32M { RW_FWID_B 0x40 } RW_MISC 0x30000 { - UNIFIED_MRC_CACHE 0x20000 { + UNIFIED_MRC_CACHE(PRESERVE) 0x20000 { RECOVERY_MRC_CACHE 0x10000 RW_MRC_CACHE 0x10000 } diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 12cd47561a6..cf9afaf68c3 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,41 +40,52 @@ chip soc/intel/alderlake register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 2 - register "PcieRpEnable[4]" = "1" + register "PchPcieRpEnable[4]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcUsage[2]" = "0x4" register "PcieRpClkReqDetect[4]" = "1" # Enable PCH PCIE RP 6 using CLK 5 - register "PcieRpEnable[5]" = "1" + register "PchPcieRpEnable[5]" = "1" register "PcieClkSrcClkReq[5]" = "5" register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" # Enable PCH PCIE RP 8 using CLK 6 - register "PcieRpEnable[7]" = "1" + register "PchPcieRpEnable[7]" = "1" register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6 register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK register "PcieRpClkReqDetect[6]" = "1" # Enable PCH PCIE RP 9 using CLK 1 - register "PcieRpEnable[8]" = "1" + register "PchPcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" # Enable PCH PCIE RP 11 for optane - register "PcieRpEnable[10]" = "1" + register "PchPcieRpEnable[10]" = "1" # Hybrid storage mode register "HybridStorageMode" = "1" - # Enable CPU PCIE RP 1 using PEG CLK 0 + # Enable CPU PCIE RP 1 using CLK 0 + register "CpuPcieRpEnable[0]" = "1" register "PcieClkSrcUsage[0]" = "0x40" - # Enable PCU PCIE PEG Slot 1 and 2 + # Enable CPU PCIE RP 2 using CLK 3 + register "CpuPcieRpEnable[1]" = "1" register "PcieClkSrcUsage[3]" = "0x41" + + # Enable CPU PCIE RP 3 using CLK 4 + register "CpuPcieRpEnable[2]" = "1" register "PcieClkSrcUsage[4]" = "0x42" + # W/A to FSP issue where FSP is using PCH PCIE port + # enable UPD to download FW on CPU PCIE + register "PchPcieRpEnable[0]" = "1" + register "PchPcieRpEnable[2]" = "1" + register "PchPcieRpEnable[3]" = "1" + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" @@ -177,10 +188,12 @@ chip soc/intel/alderlake device domain 0 on device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PEG10 device pci 02.0 on end # Graphics device pci 04.0 on end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 + device pci 06.2 on end # PEG62 device pci 07.0 on end # TBT_PCIe0 device pci 07.1 on end # TBT_PCIe1 device pci 07.2 on end # TBT_PCIe2 @@ -246,8 +259,8 @@ chip soc/intel/alderlake device pci 19.2 off end # UART2 device pci 1c.0 on end # RP1 device pci 1c.1 off end # RP2 - device pci 1c.2 off end # RP3 - device pci 1c.3 off end # RP4 + device pci 1c.2 on end # RP3 # W/A to FSP issue + device pci 1c.3 on end # RP4 # W/A to FSP issue device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 1943a667d80..3131cc0c054 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -243,16 +243,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D8, NONE), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), @@ -265,7 +265,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + PAD_NC(GPP_H23, NONE), /* A21 : HDMI CRLS CTRLCLK */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index 75c34ddc524..8501868fbfe 100644 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1 +1 @@ -#Nothing here yet +bootblock-y += bootblock.c diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c new file mode 100644 index 00000000000..0728701332e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/bootblock.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/apollolake_rvp/gpio.h b/src/mainboard/intel/apollolake_rvp/gpio.h new file mode 100644 index 00000000000..db6f6010f95 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 46c9af28b7e..9e605009dac 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -5,5 +5,3 @@ romstage-y += gpio.c romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c - -smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index c0c488a33fe..7e83b8d2f78 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -3,13 +3,12 @@ #include #include #include -#include #include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -25,11 +24,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; -#if CONFIG(CHROMEOS) - /* Emerald Lake has no EC (?) */ - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - gnvs->f4of = FAN4_THRESHOLD_OFF; gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 784c926d5f6..37cff88f308 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -16,14 +16,6 @@ chip northbridge/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/smihandler.c similarity index 94% rename from src/mainboard/intel/baskingridge/mainboard_smi.c rename to src/mainboard/intel/baskingridge/smihandler.c index 2c4e44e643e..59a3c044f5a 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig deleted file mode 100644 index c0647e11bde..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select HAVE_SPD_IN_CBFS - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select MAINBOARD_HAS_CHROMEOS - select HAVE_SPD_IN_CBFS - select DRIVERS_I2C_HID - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_MAX98373 - select DRIVERS_GENERIC_MAX98357A - select SOC_INTEL_CANNONLAKE - select MAINBOARD_USES_IFD_EC_REGION - select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_LPC_TPM - -config MAINBOARD_DIR - string - default "intel/cannonlake_rvp" - -config VARIANT_DIR - string - default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU - default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY - -config MAINBOARD_PART_NUMBER - string - default "Cannonlake RVP" - -config MAINBOARD_FAMILY - string - default "Intel_cannonlake_rvp" - -config MAX_CPUS - int - default 8 - -config DEVICETREE - string - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" - -config INCLUDE_SND_MAX98357_DA7219_NHLT - bool "Include blobs for audio with MAX98357_DA7219" - select NHLT_DMIC_4CH_16B - select NHLT_DMIC_2CH_16B - select NHLT_DA7219 - select NHLT_MAX98357 - -config INCLUDE_SND_MAX98373_NHLT - bool "Include blobs for audio with MAX98373" - select NHLT_DMIC_4CH_16B - select NHLT_DMIC_2CH_16B - select NHLT_MAX98373 - -config DIMM_SPD_SIZE - int - default 512 - -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA - -config UART_FOR_CONSOLE - int - default 2 -endif diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig.name b/src/mainboard/intel/cannonlake_rvp/Kconfig.name deleted file mode 100644 index 29d1bd8d214..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -config BOARD_INTEL_CANNONLAKE_RVPU - bool "Cannonlake U LPDDR4 RVP" -config BOARD_INTEL_CANNONLAKE_RVPY - bool "Cannonlake Y LPDDR4 RVP" diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc deleted file mode 100644 index 695b1ff3490..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -subdirs-y += spd - -bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c - -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-y += romstage_fsp_params.c - -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += mainboard.c - -smm-y += smihandler.c -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include - -subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/cannonlake_rvp/bootblock.c b/src/mainboard/intel/cannonlake_rvp/bootblock.c deleted file mode 100644 index 22d63b973c1..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/bootblock.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void bootblock_mainboard_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); -} diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c deleted file mode 100644 index 98205bc62a3..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd deleted file mode 100644 index 39bd6c52379..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ /dev/null @@ -1,45 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x380000 { - SI_DESC@0x0 0x1000 - SI_EC@0x01000 0x80000 - SI_ME@0x81000 0x2ff000 - } - SI_BIOS@0x380000 0xc80000 { - RW_SECTION_A@0x0 0x368000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 - } - RW_SECTION_B@0x368000 0x368000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 - } - RW_MISC@0x6d0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 - } - SMMSTORE(PRESERVE)@0x700000 0x40000 - RW_LEGACY(CBFS)@0x740000 0x1c0000 - WP_RO@0x900000 0x380000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x280000 - } - } - } -} diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl deleted file mode 100644 index 21faf11af91..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include - - // global NVS and variables - #include - - Scope (\_SB) { - Device (PCI0) - { - #include - #include - } - } - - #if CONFIG(CHROMEOS) - // Chrome OS specific - #include - #endif - - #include - -} diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c deleted file mode 100644 index 950e24d88bb..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void mainboard_init(void *chip_info) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} - -static unsigned long mainboard_write_acpi_tables(const struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - variant_nhlt_init(nhlt); - - end_addr = nhlt_soc_serialize(nhlt, start_addr); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - -struct chip_operations mainboard_ops = { - .init = mainboard_init, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c deleted file mode 100644 index 5b7445f0677..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include "spd/spd.h" -#include - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; - u8 spd_index; - - mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); - mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; - - struct region_device spd_rdev; - - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found\n"); - - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; -} diff --git a/src/mainboard/intel/cannonlake_rvp/smihandler.c b/src/mainboard/intel/cannonlake_rvp/smihandler.c deleted file mode 100644 index 734ab8ce8c2..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/smihandler.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - gnvs->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - return 1; -} diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc deleted file mode 100644 index f0521424312..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -romstage-y += spd_util.c - -SPD_SOURCES = empty # 0b000 -SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB -SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB -SPD_SOURCES += empty # 0b011 -SPD_SOURCES += empty # 0b100 -SPD_SOURCES += empty # 0b101 -SPD_SOURCES += empty # 0b110 -SPD_SOURCES += empty # 0b111 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex deleted file mode 100644 index 67b46cd2396..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex deleted file mode 100644 index 49db2374f42..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08 -00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20 -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31 -34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE -00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00 -01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex deleted file mode 100644 index d2986293421..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 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00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h deleted file mode 100644 index 978f01daa52..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr); -void mainboard_fill_dq_map_ch1(void *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -#endif diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c deleted file mode 100644 index e4b4b383b9e..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include "spd.h" - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dq_map_ch1(void *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; - - const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; - - if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); -} - -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; - - const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; - - if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[5] = { 80, 40, 40, 40, 30 }; - - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc deleted file mode 100644 index 0ad298b5f46..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -bootblock-y += gpio.c - -ramstage-y += gpio.c -ramstage-y += nhlt.c diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c deleted file mode 100644 index 72011861686..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ /dev/null @@ -1,306 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -/* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { - /* GPPC */ - /* A0 : RCINB_TIME_SYNC_1 */ - /* A1 : ESPI_IO_0 */ - /* A2 : ESPI_IO_1 */ - /* A3 : ESPI_IO_2 */ - /* A4 : ESPI_IO_3 */ - /* A5 : ESPI_CSB */ - /* A6 : SERIRQ */ - /* A7 : PRIQAB_GSP10_CS1B */ - PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), - /* A8 : CLKRUNB */ - PAD_CFG_GPO(GPP_A8, 1, PLTRST), - /* A9 : CLKOUT_LPC_0_ESPI_CLK */ - /* A10 : CLKOUT_LPC_1 */ - /* A11 : PMEB_GSP11_CS1B */ - PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL), - /* A12 : BM_BUSYB_ISH__GP_6 */ - /* A13 : SUSWARNB_SUSPWRDNACK */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), - /* A14 : SUS_STATB_ESPI_RESETB */ - /* A15 : SUSACKB */ - PAD_CFG_GPO(GPP_A15, 1, PLTRST), - /* A16 : SD_1P8_SEL */ - PAD_CFG_GPO(GPP_A16, 0, PLTRST), - /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ - /* A18 : ISH_GP_0 */ - PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1), - /* A19 : ISH_GP_1 */ - PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), - /* A20 : aduio codec irq */ - PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP), - /* A21 : ISH_GP_3 */ - PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), - /* A22 : ISH_GP_4 */ - PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1), - /* A23 : ISH_GP_5 */ - PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), - - /* B0 : CORE_VID_0 */ - /* B1 : CORE_VID_1 */ - /* B2 : VRALERTB */ - PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE), - /* B3 : CPU_GP_2 */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE), - /* B4 : CPU_GP_3 */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* B5 : SRCCLKREQB_0 */ - /* B6 : SRCCLKREQB_1 */ - /* B7 : SRCCLKREQB_2 */ - /* B8 : SRCCLKREQB_3 */ - /* B9 : SRCCLKREQB_4 */ - /* B10 : SRCCLKREQB_5 */ - /* B11 : EXT_PWR_GATEB */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), - /* B12 : SLP_S0B */ - /* B13 : PLTRSTB */ - /* B14 : SPKR */ - PAD_CFG_GPO(GPP_B14, 1, PLTRST), - /* B15 : GSPI0_CS0B */ - PAD_CFG_GPO(GPP_B15, 0, DEEP), - /* B16 : GSPI0_CLK */ - PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), - /* B17 : GSPI0_MISO */ - PAD_CFG_GPO(GPP_B17, 1, PLTRST), - /* B18 : GSPI0_MOSI */ - PAD_CFG_GPO(GPP_B18, 1, PLTRST), - /* B19 : GSPI1_CS0B */ - /* B20 : GSPI1_CLK_NFC_CLK */ - /* B21 : GSPI1_MISO_NFC_CLKREQ */ - /* B22 : GSP1_MOSI */ - /* B23 : SML1ALERTB_PCHHOTB */ - PAD_CFG_GPO(GPP_B23, 1, DEEP), - - /* C0 : SMBCLK */ - /* C1 : SMBDATA */ - /* C2 : SMBALERTB */ - PAD_CFG_GPO(GPP_C2, 1, DEEP), - /* C3 : SML0CLK */ - /* C4 : SML0DATA */ - /* C5 : SML0ALERTB */ - PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), - /* C6 : SML1CLK */ - /* C7 : SML1DATA */ - /* C8 : UART0_RXD */ - PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT), - /* C9 : UART0_TXD */ - PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), - /* C10 : UART0_RTSB */ - PAD_CFG_GPO(GPP_C10, 0, PLTRST), - /* C11 : UART0_CTSB */ - PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL), - /* C12 : UART1_RXD_ISH_UART1_RXD */ - PAD_CFG_GPO(GPP_C12, 1, PLTRST), - /* C13 : UART1_RXD_ISH_UART1_TXD */ - /* C14 : UART1_RXD_ISH_UART1_RTSB */ - /* C15 : UART1_RXD_ISH_UART1_CTSB */ - PAD_CFG_GPO(GPP_C15, 1, PLTRST), - /* C16 : I2C0_SDA */ - /* C17 : I2C0_SCL */ - /* C18 : I2C1_SDA */ - /* C19 : I2C1_SCL */ - /* C20 : UART2_RXD */ - /* C21 : UART2_TXD */ - /* C22 : UART2_RTSB */ - /* C23 : UART2_CTSB */ - - /* D0 : SPI1_CSB_BK_0 */ - /* D1 : SPI1_CLK_BK_1 */ - /* D2 : SPI1_MISO_IO_1_BK_2 */ - /* D3 : SPI1_MOSI_IO_0_BK_3 */ - /* D4 : IMGCLKOUT_0_BK_4 */ - /* D5 : ISH_I2C0_SDA */ - /* D6 : ISH_I2C0_SCL */ - /* D7 : ISH_I2C1_SDA */ - /* D8 : ISH_I2C1_SCL */ - /* D9 : ISH_SPI_CSB */ - PAD_CFG_GPO(GPP_D9, 1, PLTRST), - /* D10 : ISH_SPI_CLK */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE), - /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ - PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), - /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ - /* D13 : ISH_UART0_RXD_SML0BDATA */ - PAD_CFG_GPO(GPP_D13, 1, DEEP), - /* D14 : ISH_UART0_TXD_SML0BCLK */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), - /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ - /* D16 : ISH_UART0_CTSB_SML0BALERTB */ - PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), - /* D17 : DMIC_CLK_1_SNDW3_CLK */ - PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1), - /* D18 : DMIC_DATA_1_SNDW3_DATA */ - PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1), - /* D19 : DMIC_CLK_0_SNDW4_CLK */ - PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1), - /* D20 : DMIC_DATA_0_SNDW4_DATA */ - PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1), - /* D21 : SPI1_IO_2 */ - PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), - /* D22 : SPI1_IO_3 */ - PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), - /* D23 : SPP_MCLK */ - PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), - /* E0 : SATAXPCIE_0_SATAGP_0 */ -#if CONFIG(BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), -#endif - /* E1 : SATAXPCIE_1_SATAGP_1 */ - /* E2 : SATAXPCIE_2_SATAGP_2 */ - PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), - /* E3 : CPU_GP_0 */ - PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), - /* E4 : SATA_DEVSLP_0 */ - PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP_1 */ - /* E6 : SATA_DEVSLP_2 */ - PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), - /* E7 : CPU_GP_1 */ - PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), - /* E8 : SATA_LEDB */ - /* E9 : USB2_OCB_0_GP_BSSB_CLK */ - /* E10 : USB2_OCB_1_GP_BSSB_DI */ - /* E11 : USB2_OCB_2 */ - /* E12 : USB2_OCB_3 */ - /* E13 : DDSP_HPD_0_DISP_MISC_0 */ - /* E14 : DDSP_HPD_0_DISP_MISC_1 */ - /* E15 : DDSP_HPD_0_DISP_MISC_2 */ - /* E16 : EMMC_EN */ - PAD_CFG_GPO(GPP_E16, 1, PLTRST), - /* E17 : EDP_HPD_DISP_MISC_4 */ - /* E18 : DDPB_CTRLCLK */ - /* E19 : DDPB_CTRLDATA */ - /* E20 : DDPC_CTRLCLK */ - /* E21 : DDPC_CTRLDATA */ - /* E22 : DDPD_CTRLCLK */ - /* E23 : DDPD_CTRLDATA */ - - /* F0 : CNV_GNSS_PA_BLANKING */ - PAD_CFG_GPI(GPP_F0, NONE, PLTRST), - /* F1 : CNV_GNSS_FAT */ - PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP), - /* F2 : CNV_GNSS_SYSCK */ - PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), - /* F3 : GPP_F_3 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), - /* F4 : CNV_BRI_DT_UART0_RTSB */ - /* F5 : CNV_BRI_RSP_UART0_RXD */ - /* F6 : CNV_RGI_DT_UART0_TXD */ - /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */ - /* F8 : CNV_MFUART2_RXD */ - PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), - /* F9 : CNV_MFUART2_TXD */ - PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1), - /* F10 : GPP_F_10 */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - /* F11 : EMMC_CMD */ - /* F12 : EMMC_DATA0 */ - /* F13 : EMMC_DATA1 */ - /* F14 : EMMC_DATA2 */ - /* F15 : EMMC_DATA3 */ - /* F16 : EMMC_DATA4 */ - /* F17 : EMMC_DATA5 */ - /* F18 : EMMC_DATA6 */ - /* F19 : EMMC_DATA9 */ - /* F20 : EMMC_RCLK */ - /* F21 : EMMC_CLK */ - /* F22 : EMMC_RESETB */ - /* F23 : BIOS_REC */ - PAD_CFG_GPI(GPP_F23, UP_20K, DEEP), - /* G0 : SD3_D2 */ - /* G1 : SD3_D0_SD4_RCLK_P */ - /* G2 : SD3_D1_SD4_RCLK_N */ - /* G3 : SD3_D2 */ - /* G4 : SD3_D3 */ - /* G5 : SD3_CDB */ - PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1), - /* G6 : SD3_CLK */ - /* G7 : SD3_WP */ - PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), - - /* H0 : SSP2_SCLK */ - /* H1 : SSP2_SFRM */ - /* H2 : SSP2_TXD */ - /* H3 : SSP2_RXD */ - /* H4 : I2C2_SDA */ - /* H5 : I2C2_SCL */ - /* H6 : I2C3_SDA */ - PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1), - /* H7 : I2C3_SCL */ - PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1), - /* H8 : I2C4_SDA */ - /* H9 : I2C4_SCL */ - /* H10 : I2C5_SDA_ISH_I2C2_SDA */ - PAD_CFG_GPO(GPP_H10, 1, PLTRST), - /* H11 : I2C5_SCL_ISH_I2C2_SCL */ - PAD_CFG_GPO(GPP_H11, 1, PLTRST), - /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */ - PAD_CFG_GPO(GPP_H12, 1, PLTRST), - /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */ - PAD_CFG_GPO(GPP_H13, 1, PLTRST), - /* H14 : M2_SKT2_CFG_2 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), - /* H15 : M2_SKT2_CFG_3 */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), - /* H16 : CAM5_PWR_EN */ - PAD_CFG_GPO(GPP_H16, 1, PLTRST), - /* H17 : CAM5_FLASH_STROBE */ - PAD_CFG_GPO(GPP_H17, 1, PLTRST), - /* H18 : BOOTMPC */ - /* H19 : TIMESYNC_0 */ - PAD_CFG_GPO(GPP_H19, 1, PLTRST), - /* H20 : IMGCLKOUT_1 */ - /* H21 : GPPC_H_21 */ - /* H22 : GPPC_H_22 */ - PAD_CFG_GPO(GPP_H22, 1, PLTRST), - /* H23 : GPPC_H_23 */ - - /* GPD */ - /* GPD_0 : BATLOWB */ - /* GPD_1 : ACPRESENT */ - /* GPD_2 : LAN_WAKEB */ - /* GPD_3 : PWRBTNB */ - /* GPD_4 : SLP_S3B */ - /* GPD_5 : SLP_S4B */ - /* GPD_6 : SLP_AB */ - /* GPD_7 : GPD_7 */ - /* GPD-8 : SUSCLK */ - /* GPD-9 : SLP_WLANB */ - /* GPD-10 : SLP_5B */ - /* GPD_11 : LANPHYPC */ -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -}; - -const struct pad_config *__weak variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__weak - variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index 102f5e12eba..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index f77d38bfb30..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_VARIANTS_H__ -#define __BASEBOARD_VARIANTS_H__ - -#include -#include - -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ - -const struct pad_config *variant_gpio_table(size_t *num); -const struct pad_config *variant_early_gpio_table(size_t *num); - -const struct cros_gpio *variant_cros_gpios(size_t *num); - -/* Seed the NHLT tables with the board specific information. */ -struct nhlt; -void variant_nhlt_init(struct nhlt *nhlt); - -#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c deleted file mode 100644 index 6599cbd1cba..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void __weak variant_nhlt_init(struct nhlt *nhlt) -{ - /* 1-dmic configuration */ - if (CONFIG(NHLT_DMIC_1CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 1)) - printk(BIOS_ERR, "Added 1CH DMIC array.\n"); - /* 2-dmic configuration */ - if (CONFIG(NHLT_DMIC_2CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Added 2CH DMIC array.\n"); - /* 4-dmic configuration */ - if (CONFIG(NHLT_DMIC_4CH_16B) && - !nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Added 4CH DMIC array.\n"); - - if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT)) - { - /* Dialog for Headset codec. - * Headset codec is bi-directional but uses the same configuration - * settings for render and capture endpoints. - */ - if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) - printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); - - /* MAXIM Smart Amps for left and right speakers. */ - if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); - } - - if (CONFIG(INCLUDE_SND_MAX98373_NHLT) && - !nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Added Maxim_98373 codec.\n"); -} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb deleted file mode 100644 index 535ae49da60..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ /dev/null @@ -1,161 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - register "PcieRpEnable[14]" = "1" - register "PcieRpEnable[15]" = "1" - - register "PcieClkSrcUsage[0]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "13" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcUsage[5]" = "14" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C3 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[3] = { - .speed = I2C_SPEED_STANDARD, - .rise_time_ns = 104, - .fall_time_ns = 52, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "interleave_mode" = "1" - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 32 on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 - register "PcieRpSlotImplemented[0]" = "1" - end - device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN - register "PcieRpSlotImplemented[4]" = "1" - end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 - register "PcieRpSlotImplemented[8]" = "1" - end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h deleted file mode 100644 index 33ccb11351b..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb deleted file mode 100644 index bbdd38b534a..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ /dev/null @@ -1,181 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" - - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[6]" = "1" - register "PcieRpEnable[7]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "1" - register "PcieRpEnable[13]" = "1" - - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" - - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0001"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "hid_desc_reg_offset" = "0x1" - device i2c 2C on end - end - end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - chip drivers/i2c/da7219 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 - register "PcieRpSlotImplemented[0]" = "1" - end - device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN - register "PcieRpSlotImplemented[4]" = "1" - end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 - register "PcieRpSlotImplemented[8]" = "1" - end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h deleted file mode 100644 index 33ccb11351b..00000000000 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include - -#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index c39a8ff9ba1..90833269e40 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -4,7 +4,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 5700f064b01..f9eba5c5805 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -107,8 +107,14 @@ static const struct pad_config gpio_table[] = { /* C17 : I2C0_SCL */ /* C18 : I2C1_SDA */ /* C19 : I2C1_SCL */ + + /* + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ /* C20 : UART2_RXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTSB */ /* C23 : UART2_CTSB */ @@ -579,6 +585,10 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C20 : UART2_RXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART2_TXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index cd6260bbae6..6e7552cb531 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c deleted file mode 100644 index 496d4190c6f..00000000000 --- a/src/mainboard/intel/d510mo/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c deleted file mode 100644 index 496d4190c6f..00000000000 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 28bc7c7cc9f..08aa2ddde79 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -3,4 +3,3 @@ romstage-y += early_southbridge.c bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index 43e5062bb84..b8d4421f9e3 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 by default */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index b865d1a49e3..7a5684447e8 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -17,13 +17,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" - - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" end end device domain 0x0 on diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index 9eef15936a6..566cad75bbf 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c index 65db55f5cba..1ac09572f16 100644 --- a/src/mainboard/intel/dg43gt/acpi_tables.c +++ b/src/mainboard/intel/dg43gt/acpi_tables.c @@ -1,13 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ - gnvs->apic = 1; /* Enable APIC */ - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 302966a7d68..3e75d32dc43 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -3,12 +3,11 @@ #include #include #include -#include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -44,7 +43,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; - - // Stumpy has no arms^H^H^H^HEC. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 3b4ee6532ad..b2f4e6b544e 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -17,13 +17,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index 5c088a3d878..57b4394725b 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -7,7 +7,7 @@ void lumpy_ec_init(void) { - printk(BIOS_DEBUG, "lumpy_ec_init\n"); + printk(BIOS_DEBUG, "%s\n", __func__); if (acpi_is_wakeup_s3()) return; diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index 19712d9a3bf..b1676d4fab6 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc index ea5b2c65c64..37b60d0fae4 100644 --- a/src/mainboard/intel/glkrvp/Makefile.inc +++ b/src/mainboard/intel/glkrvp/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += ec.c ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/glkrvp/bootblock.c b/src/mainboard/intel/glkrvp/bootblock.c index 3e9f51afd01..0cbf3e62c26 100644 --- a/src/mainboard/intel/glkrvp/bootblock.c +++ b/src/mainboard/intel/glkrvp/bootblock.c @@ -3,17 +3,19 @@ #include #include #include -#include #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; - lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); +} + +void bootblock_mainboard_init(void) +{ mainboard_ec_init(); } diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 56df5260569..9a8188ba5d8 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -236,6 +236,9 @@ const struct pad_config * __weak variant_gpio_table(size_t *num) static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */ + PAD_NC(GPIO_154, NONE), /* LPC_CLKRUNB -- NC for eSPI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/* LPSS_UART2_TXD */ }; const struct pad_config * __weak diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 821de5f5ec4..c3f90dac6b4 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -8,10 +8,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Disable USB ports in S5 */ gnvs->s5u0 = 0; gnvs->s5u1 = 0; diff --git a/src/mainboard/intel/icelake_rvp/bootblock.c b/src/mainboard/intel/icelake_rvp/bootblock.c index a8f7e41433d..d7f3255974a 100644 --- a/src/mainboard/intel/icelake_rvp/bootblock.c +++ b/src/mainboard/intel/icelake_rvp/bootblock.c @@ -5,7 +5,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index 286753a8202..30e249c22ea 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -86,6 +86,10 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* UART2 RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART2 TX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index 286753a8202..30e249c22ea 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -86,6 +86,10 @@ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* UART2 RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART2 TX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig.name b/src/mainboard/intel/jasperlake_rvp/Kconfig.name index 5c7a0077d85..68419ac1f5f 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig.name +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig.name @@ -7,5 +7,5 @@ config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC" select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC - select EC_GOOGLE_CHROMEEC_SWITCHES + select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc index 2ac1b07befb..c680b23b5bf 100644 --- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc @@ -15,8 +15,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c -smm-y += smihandler.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/jasperlake_rvp/bootblock.c b/src/mainboard/intel/jasperlake_rvp/bootblock.c index a8f7e41433d..d7f3255974a 100644 --- a/src/mainboard/intel/jasperlake_rvp/bootblock.c +++ b/src/mainboard/intel/jasperlake_rvp/bootblock.c @@ -5,7 +5,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 21e25ab8963..c44ce52990f 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -310,6 +310,13 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +#if CONFIG(BOARD_INTEL_JASPERLAKE_RVP_EXT_EC) + /* UART2 RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + + /* UART2 TX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +#endif /* GSPI1_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 5dccdaed93d..fcce402d857 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_FAMILY string default "Intel_Kblrvp" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index c168b6dbf36..80821eb6457 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -19,7 +19,5 @@ ramstage-y += ramstage.c ramstage-y += hda_verb.c -smm-y += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c index 19c5e9efb81..41105826fb8 100644 --- a/src/mainboard/intel/kblrvp/bootblock.c +++ b/src/mainboard/intel/kblrvp/bootblock.c @@ -12,7 +12,7 @@ static void early_config_gpio(void) gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { early_config_gpio(); } diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index 4f7f002bff8..354a4ff157d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -267,6 +267,8 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index ff4647f1d21..a60850545f1 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -197,6 +197,8 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index 37193cfcda4..5b588a10c32 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -163,6 +163,8 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index b9b7d5a3940..cf67ca18d0e 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -41,10 +41,6 @@ config MAINBOARD_FAMILY string default "Intel_Kunimitsu" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 63c39cf5e71..f7ea681fb9b 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -13,5 +13,3 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c - -smm-y += smihandler.c diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c index fdaaaa182bd..4cd1e6a4cfb 100644 --- a/src/mainboard/intel/leafhill/bootblock.c +++ b/src/mainboard/intel/leafhill/bootblock.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void bootblock_mainboard_init(void) +#include "brd_gpio_early.h" + +void bootblock_mainboard_early_init(void) { - lpc_configure_pads(); + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/intel/leafhill/brd_gpio_early.h b/src/mainboard/intel/leafhill/brd_gpio_early.h new file mode 100644 index 00000000000..8b40f537210 --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio_early.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pad_config early_gpio_table[] = { + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1), + + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c index 61f3c92ef31..e2a339138ff 100644 --- a/src/mainboard/intel/minnow3/bootblock.c +++ b/src/mainboard/intel/minnow3/bootblock.c @@ -1,17 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include + #include "gpio.h" -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; - lpc_configure_pads(); - - /* Configure GPIOs needed prior to ramstage. */ pads = early_gpio_table(&num); gpio_configure_pads(pads, num); } diff --git a/src/mainboard/intel/minnow3/gpio.c b/src/mainboard/intel/minnow3/gpio.c index 2e356d60c29..4c0515d8e95 100644 --- a/src/mainboard/intel/minnow3/gpio.c +++ b/src/mainboard/intel/minnow3/gpio.c @@ -279,6 +279,9 @@ const struct pad_config *gpio_table(size_t *num) /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table_config[] = { + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */ + PAD_CFG_NF(GPIO_134, UP_20K, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ PAD_CFG_NF(GPIO_135, UP_20K, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ PAD_CFG_NF(GPIO_136, UP_20K, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 873f25727c1..e7aaae50c8a 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,10 +32,6 @@ config MAINBOARD_FAMILY string default "Intel_SaddleBrook" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig new file mode 100644 index 00000000000..a822bcc350d --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -0,0 +1,25 @@ +if BOARD_INTEL_SHADOWMOUNTAIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_ALDERLAKE + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "intel/shadowmountain" + +config MAINBOARD_FAMILY + string + default "Intel_shadowmountain" + +config MAINBOARD_PART_NUMBER + string + default "shadowmountain" + +endif # BOARD_INTEL_SHADOWMOUNTAIN diff --git a/src/mainboard/intel/shadowmountain/Kconfig.name b/src/mainboard/intel/shadowmountain/Kconfig.name new file mode 100644 index 00000000000..e4890394005 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SHADOWMOUNTAIN + bool "shadowmountain" diff --git a/src/mainboard/intel/cannonlake_rvp/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt similarity index 74% rename from src/mainboard/intel/cannonlake_rvp/board_info.txt rename to src/mainboard/intel/shadowmountain/board_info.txt index 2fe64680dda..7e0cccf015d 100644 --- a/src/mainboard/intel/cannonlake_rvp/board_info.txt +++ b/src/mainboard/intel/shadowmountain/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Intel -Board name: Cannonlake rvp +Board name: Alderlake Pre-CEP Category: eval ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl new file mode 100644 index 00000000000..10d08e26e2d --- /dev/null +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb new file mode 100644 index 00000000000..fbd7d72f9f5 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end +end diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 640f5d4e91e..4ea5885e0dc 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -47,10 +47,6 @@ config VGA_BIOS_ID The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "strago" - config CBFS_SIZE hex default 0x200000 diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index bf35b669a87..21ae380e4b3 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -10,5 +10,3 @@ ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c - -smm-y += smihandler.c diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 25d6a37a05b..97795cd0eaf 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -10,10 +10,8 @@ #include #include "onboard.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index fa23e9faa9b..55424c2a0f9 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -15,7 +15,7 @@ void mainboard_ec_init(void) .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, }; - printk(BIOS_DEBUG, "mainboard_ec_init\n"); + printk(BIOS_DEBUG, "%s\n", __func__); post_code(0xf0); google_chromeec_events_init(&info, acpi_is_wakeup_s3()); diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index 2ca32f37603..93c9c493e05 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -11,8 +11,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c -smm-y += smihandler.c - ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c index a8f7e41433d..d7f3255974a 100644 --- a/src/mainboard/intel/tglrvp/bootblock.c +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -5,7 +5,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 47507f4eeda..33415684edf 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -42,14 +42,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct lpddr4x_cfg *mem_config = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *mem_config = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = mainboard_get_spd_index(), }; bool half_populated = false; - meminit_lpddr4x(mem_cfg, mem_config, &spd_info, half_populated); + memcfg_init(mem_cfg, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index bad9e9e8280..fbb86f7b002 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -15,6 +15,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 51b301d3cf9..448aa41ecca 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -63,6 +63,10 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c index 490a14591cf..e965e6bfc93 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c @@ -9,59 +9,61 @@ size_t __weak variant_memory_sku(void) return 0; } -static const struct lpddr4x_cfg mem_config = { +static const struct mb_cfg mem_config = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */ }, - [1] = { - { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */ - { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */ - { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */ - { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */ - { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */ - { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */ - { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */ - { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Early Command Training */ + .ect = true, /* Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 77da5cce5c2..18dab082a2b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -59,6 +59,10 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index ca60357e84e..8e7bb14ba09 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -9,59 +9,61 @@ size_t __weak variant_memory_sku(void) return 0; } -static const struct lpddr4x_cfg mem_config = { +static const struct mb_cfg mem_config = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ - { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ - { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ - { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ - { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ - { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ - { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Early Command Training */ + .ect = true, /* Early Command Training */ }; -const struct lpddr4x_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &mem_config; } diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 2f6b21e9ceb..7ac5f1c9aab 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -25,11 +25,6 @@ config MAINBOARD_PART_NUMBER string default "WHITETIP MOUNTAIN 2" - -config MAX_CPUS - int - default 16 - config VGA_BIOS_FILE string default "pci8086,0166.rom" diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 21a94bca8df..c6d4ce8a7bf 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -7,7 +7,7 @@ #include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 29041aaecad..9090999153f 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -10,7 +10,10 @@ chip soc/intel/broadwell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on device pci 00.0 on end # host bridge diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c deleted file mode 100644 index 9e222509355..00000000000 --- a/src/mainboard/intel/wtm2/romstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); -} - -void mainboard_post_raminit(struct romstage_params *rp) -{ -} diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c deleted file mode 100644 index 52c2fbbec13..00000000000 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - -} diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index 437c5a3e525..dd8f4fac48a 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -1,15 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_KONTRON_BSL6 || BOARD_SIEMENS_BOXER26 - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_KONTRON_BSL6_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_SKYLAKE select SKYLAKE_SOC_PCH_H select EXCLUDE_NATIVE_SD_INTERFACE select NO_FADT_8042 - select HAVE_ACPI_RESUME if BOARD_KONTRON_BSL6 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -17,8 +14,19 @@ config BOARD_SPECIFIC_OPTIONS select EC_KONTRON_KEMPLD select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_I2C_NCT7802Y - select DRIVERS_I2C_LM96000 if BOARD_SIEMENS_BOXER26 - select SECUNET_DMI if BOARD_SIEMENS_BOXER26 + +config BOARD_KONTRON_BSL6_OPTIONS + bool + select BOARD_KONTRON_BSL6_COMMON + select HAVE_ACPI_RESUME + +config BOARD_KONTRON_BOXER26_OPTIONS + bool + select BOARD_KONTRON_BSL6_COMMON + select DRIVERS_I2C_LM96000 + select SECUNET_DMI + +if BOARD_KONTRON_BSL6_COMMON config MAINBOARD_DIR string @@ -46,10 +54,6 @@ config CBFS_SIZE hex default 0x600000 if BOARD_SIEMENS_BOXER26 -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 diff --git a/src/mainboard/kontron/bsl6/Kconfig.name b/src/mainboard/kontron/bsl6/Kconfig.name index 0f0577e5dbf..90bf1c474f9 100644 --- a/src/mainboard/kontron/bsl6/Kconfig.name +++ b/src/mainboard/kontron/bsl6/Kconfig.name @@ -1,5 +1,7 @@ config BOARD_KONTRON_BSL6 bool "COMe-bSL6" + select BOARD_KONTRON_BSL6_OPTIONS config BOARD_SIEMENS_BOXER26 bool "COMe-bSL6 on Siemens/Boxer26" + select BOARD_KONTRON_BOXER26_OPTIONS diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 8ad785251d8..910a49da755 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -82,17 +82,8 @@ chip soc/intel/skylake register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug end - device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on # SATA register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" @@ -100,11 +91,6 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" # SataPortsDevSlp not supported end - device pci 19.0 off end # UART #2 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 (COMe 0) register "PcieRpEnable[8]" = "1" end @@ -114,10 +100,6 @@ chip soc/intel/skylake device pci 1d.2 on # PCI Express Port 11 (COMe 2) register "PcieRpEnable[10]" = "1" end - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -134,7 +116,6 @@ chip soc/intel/skylake end device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA device pci 1f.4 on # SMBus chip drivers/i2c/nct7802y device i2c 0x2e on end diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb b/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb index 9dd57e1987c..88335ae285f 100644 --- a/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/boxer26/overridetree.cb @@ -5,11 +5,6 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" device domain 0 on - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on chip ec/kontron/kempld device generic 1.0 on # I2C diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index 3012052a246..64f3f04bd06 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index db0c9e24f9c..71c96116397 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -8,13 +8,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "0" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "0" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "0" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/kontron/mal10/Makefile.inc b/src/mainboard/kontron/mal10/Makefile.inc index 885786fc557..7fbab00337b 100644 --- a/src/mainboard/kontron/mal10/Makefile.inc +++ b/src/mainboard/kontron/mal10/Makefile.inc @@ -3,7 +3,5 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include - subdirs-y += carriers/$(CARRIER_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/carriers/$(CARRIER_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h b/src/mainboard/kontron/mal10/include/carrier/gpio.h similarity index 89% rename from src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h rename to src/mainboard/kontron/mal10/include/carrier/gpio.h index 9c9c8edc839..9466b24dba6 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h +++ b/src/mainboard/kontron/mal10/include/carrier/gpio.h @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef T10_TNI_CFG_GPIO_H -#define T10_TNI_CFG_GPIO_H +#ifndef CARRIER_GPIO_H +#define CARRIER_GPIO_H #include -#include /* * Bidirectional GPIO port when both RX and TX buffer is enabled @@ -29,4 +28,4 @@ void carrier_gpio_configure(void); -#endif /* T10_TNI_CFG_GPIO_H */ +#endif /* CARRIER_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/include/variant/gpio.h similarity index 50% rename from src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h rename to src/mainboard/kontron/mal10/include/variant/gpio.h index d97e199fb81..a3ff7c0c312 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h +++ b/src/mainboard/kontron/mal10/include/variant/gpio.h @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAL_10_CFG_GPIO_H -#define MAL_10_CFG_GPIO_H +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H #include -#include void variant_early_gpio_configure(void); -#endif /* MAL_10_CFG_GPIO_H */ +#endif /* VARIANT_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c index 48194e6848a..3d259d8ea79 100644 --- a/src/mainboard/kontron/mal10/ramstage.c +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -2,7 +2,6 @@ #include #include -#include void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) { diff --git a/src/mainboard/kontron/mal10/romstage.c b/src/mainboard/kontron/mal10/romstage.c index 9f1d7eb87d2..dba78f7909a 100644 --- a/src/mainboard/kontron/mal10/romstage.c +++ b/src/mainboard/kontron/mal10/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index 77ae870b6c5..5d42edabf4e 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -8,5 +8,3 @@ ramstage-y += buildOpts.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += ec.c - -smm-y += mainboard_smi.c diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index 910d2e66a83..f1376069748 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -15,7 +15,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* USB controller PME# */ Method(_L0B) { - Store("USB PME", Debug) + Debug = "USB PME" /* Notify devices of wake event */ Notify(\_SB.PCI0.UOH1, 0x02) Notify(\_SB.PCI0.UOH2, 0x02) @@ -37,16 +37,16 @@ Scope(\_GPE) { /* Start Scope GPE */ /* Lid switch opened or closed */ Method(_L16) { - Store("Lid status changed", Debug) + Debug = "Lid status changed" /* Flip trigger polarity */ - Not(LPOL, LPOL) + LPOL = ~LPOL /* Notify lid object of status change */ Notify(\_SB.LID, 0x80) } /* GPIO0 or GEvent8 event */ Method(_L18) { - Store("PCI bridge wake event", Debug) + Debug = "PCI bridge wake event" /* Notify PCI bridges of wake event */ Notify(\_SB.PCI0.PBR4, 0x02) Notify(\_SB.PCI0.PBR5, 0x02) diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl index dd3318e3ccf..be686309ca4 100644 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl @@ -56,7 +56,7 @@ */ Method (PNOT) { - Store("Received PNOT call (probably from EC)", Debug) + Debug = "Received PNOT call (probably from EC)" /* TODO: Implement this */ } @@ -75,7 +75,7 @@ Scope (\_SB) { /* Make sure lid trigger polarity is set so that we * trigger an SCI when lid status changes. */ - Not(GE22, LPOL) + LPOL = ~GE22 } } @@ -95,7 +95,7 @@ Scope (\_SB) { /* Toggle wireless */ Method (WLTG) { - Store( Not(GP57), GP57 ) + GP57 = ~GP57 } /* Return lid state */ Method (LIDS) diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl index dde9c37cd00..cd714cec874 100644 --- a/src/mainboard/lenovo/g505s/acpi/sleep.asl +++ b/src/mainboard/lenovo/g505s/acpi/sleep.asl @@ -26,20 +26,20 @@ Method(\_PTS, 1) { /* DBGO("\n") */ /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 - Store (0x07, UPWS) + UPWS = 0x07 } /* End Method(\_PTS) */ /* @@ -64,7 +64,7 @@ Method(\_WAK, 1) { /* DBGO(" to S0\n") */ /* Re-enable HPET */ - Store(1,USBS) + USBS = 1 Return(WKST) } /* End Method(\_WAK) */ diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/smihandler.c similarity index 100% rename from src/mainboard/lenovo/g505s/mainboard_smi.c rename to src/mainboard/lenovo/g505s/smihandler.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 0126a75fa04..e4b6fbf0f0a 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += gpio.c romstage-y += gpio.c -smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ b/src/mainboard/lenovo/l520/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index bab1d54f398..6505d139c17 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -14,12 +14,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index 12e77097e4d..31bb642edf5 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,7 +1,6 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += ec.c -smm-y += smihandler.c # FIXME: SPD images for samsung_8gb and hynix_8gb are missing. # It's possible that no mainboards with that variation were manufactured. diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 20a90963957..7365d748253 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -127,7 +127,7 @@ Device (EC0) /* Switched to AC power */ Method (_Q26, 0, NotSerialized) { - Store (One, PWRS) + PWRS = 1 Notify (^AC, 0x80) Notify (^BAT0, 0x80) \PNOT () @@ -137,7 +137,7 @@ Device (EC0) /* Switched to battery power */ Method (_Q27, 0, NotSerialized) { - Store (Zero, PWRS) + PWRS = 0 Notify (^AC, 0x80) Notify (^BAT0, 0x80) \PNOT () @@ -147,7 +147,7 @@ Device (EC0) /* Lid openend */ Method (_Q2A, 0, NotSerialized) { - Store (One, LIDS) + LIDS = 1 Notify(^LID, 0x80) ^HKEY.MHKQ (0x5002) } @@ -155,7 +155,7 @@ Device (EC0) /* Lid closed */ Method (_Q2B, 0, NotSerialized) { - Store (Zero, LIDS) + LIDS = 0 Notify(^LID, 0x80) ^HKEY.MHKQ (0x5001) } @@ -236,7 +236,7 @@ Device (EC0) /* FN+Esc pressed / FN row mode switch */ Method (_Q74, 0, NotSerialized) { - XOr(One, HKFA, HKFA) + HKFA = 1 ^ HKFA ^HKEY.MHKQ (0x6060) } @@ -270,11 +270,11 @@ Device (EC0) { Acquire (XDHK, 0xFFFF) - ShiftLeft (One, Decrement (Arg0), Local0) + Local0 = 1 << Arg0-- If (Arg1) { - Or (Local0, DHKN, DHKN) + DHKN |= Local0 } Else { - And (Not(Local0), DHKN, DHKN) + DHKN &= ~Local0 } Release (XDHK) @@ -284,7 +284,7 @@ Device (EC0) { Acquire (XDHK, 0xFFFF) - Store (Arg0, DHKC) + DHKC = Arg0 Release (XDHK) } @@ -293,11 +293,11 @@ Device (EC0) { Acquire (XDHK, 0xFFFF) - Store (Zero, Local0) + Local0 = 0 if (DHKV) { - Store (DHKV, Local0) - Store (Zero, DHKV) + Local0 = DHKV + DHKV = 0 } Release (XDHK) @@ -309,7 +309,7 @@ Device (EC0) { Acquire (XDHK, 0xFFFF) - Store (Arg0, DHKV) + DHKV = Arg0 Release (XDHK) @@ -320,7 +320,7 @@ Device (EC0) /* LED support for thinkpad-acpi */ Method (LED, 2, NotSerialized) { - Or (Arg0, Arg1, HLCL) + HLCL = Arg0 | Arg1 } Device (AC) diff --git a/src/mainboard/lenovo/s230u/acpi/platform.asl b/src/mainboard/lenovo/s230u/acpi/platform.asl index 149fb3a8741..9ad3ff1f0ee 100644 --- a/src/mainboard/lenovo/s230u/acpi/platform.asl +++ b/src/mainboard/lenovo/s230u/acpi/platform.asl @@ -3,8 +3,8 @@ Method(_WAK,1) { /* Turn on radios */ - Store (One, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ - Store (One, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + GP33 = 1 /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + GP36 = 1 /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ /* There also is RF_OFF# on pin 20, controlled by the EC */ Return(Package(){0,0}) @@ -13,8 +13,8 @@ Method(_WAK,1) Method(_PTS,1) { /* Turn off radios */ - Store (Zero, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ - Store (Zero, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + GP33 = 0 /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + GP36 = 0 /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ /* There also is RF_OFF# on pin 20, controlled by the EC */ } @@ -22,7 +22,7 @@ Scope(\_SI) { Method(_SST, 1, NotSerialized) { - If (LLess(Arg0, 2)) + If (Arg0 < 2) { /* Thinkpad LED on */ \_SB.PCI0.LPCB.EC0.LED (Zero, 0x80) diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/s230u/acpi_tables.c +++ b/src/mainboard/lenovo/s230u/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index f3b8c277844..eb92d78ae84 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -13,12 +13,9 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x041e041e" device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c index 62bba4480b9..8f22063228c 100644 --- a/src/mainboard/lenovo/s230u/smihandler.c +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -74,7 +74,7 @@ void mainboard_smi_gpi(u32 gpi_sts) int mainboard_smi_apmc(u8 data) { - printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data); + printk(BIOS_INFO, "%s(%02x)\n", __func__, data); switch (data) { case APM_CNT_ACPI_ENABLE: diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl index 9a6d354be92..dce1d1a5a52 100644 --- a/src/mainboard/lenovo/t400/acpi/dock.asl +++ b/src/mainboard/lenovo/t400/acpi/dock.asl @@ -12,14 +12,14 @@ Scope (\_SB) { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } diff --git a/src/mainboard/lenovo/t400/acpi/gpe.asl b/src/mainboard/lenovo/t400/acpi/gpe.asl index 62e7b37bb47..99846368606 100644 --- a/src/mainboard/lenovo/t400/acpi/gpe.asl +++ b/src/mainboard/lenovo/t400/acpi/gpe.asl @@ -5,8 +5,8 @@ Scope (\_GPE) Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 8780e2f4db6..5559bfcfa72 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -26,19 +26,19 @@ Field (GPCM, ByteAcc, NoLock, Preserve) { Method(SHYB, 1) { /* Switch hybrid graphics */ - if (LEqual(Arg0, One)) + if (Arg0 == One) { /* Discrete graphics requested */ - Or(GPLV, HYG1, GPLV) - Or(GQLV, HYG2, GQLV) + GPLV |= HYG1 + GQLV |= HYG2 } else { /* Integrated graphics requested */ - Xor(HYG1, 0xFFFFFFFF, Local0) - And(GPLV, Local0, GPLV) - Xor(HYG2, 0xFFFFFFFF, Local0) - And(GQLV, Local0, GQLV) + Local0 = HYG1 ^ 0xFFFFFFFF + GPLV &= Local0 + Local0 = HYG2 ^ 0xFFFFFFFF + GQLV &= Local0 } } @@ -53,21 +53,21 @@ Method (ATPX, 2, Serialized) { CreateDWordField (ATPR, 0x04, FUNC) /* Version request */ - if (LEqual(Arg0, 0x0)) + if (Arg0 == 0x0) { /* Assemble and return version information */ - Store (0x08, SIZE) /* Response length */ - Store (0x01, VERS) /* Version number */ - Store (0x0F, FUNC) /* Supported functions? */ + SIZE = 0x08 /* Response length */ + VERS = 0x01 /* Version number */ + FUNC = 0x0F /* Supported functions? */ Return (ATPR) } /* Mux select */ - if (LEqual(Arg0, 0x2)) + if (Arg0 == 0x2) { CreateByteField (Arg1, 0x02, PWST) - Store (PWST, Local0) - And (Local0, 0x01, Local0) + Local0 = PWST + Local0 &= 0x01 If (Local0) { /* Enable discrete graphics */ diff --git a/src/mainboard/lenovo/t400/acpi/platform.asl b/src/mainboard/lenovo/t400/acpi/platform.asl index 10cadf2dbf6..3d2805d19f6 100644 --- a/src/mainboard/lenovo/t400/acpi/platform.asl +++ b/src/mainboard/lenovo/t400/acpi/platform.asl @@ -61,14 +61,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index b26996e4383..9e0ae85adc0 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -5,17 +5,10 @@ #include #include #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 20ec7604c9a..3b410c48587 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -3,7 +3,6 @@ bootblock-y += early_init.c smm-y += dock.c -smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads romstage-y += dock.c diff --git a/src/mainboard/lenovo/t410/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl index 4771c5197e8..a94762f83ff 100644 --- a/src/mainboard/lenovo/t410/acpi/dock.asl +++ b/src/mainboard/lenovo/t410/acpi/dock.asl @@ -12,18 +12,18 @@ Scope (\_SB) { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - Store (1, \_SB.PCI0.LPCB.EC.DKR2) - Store (1, \_SB.PCI0.LPCB.EC.DKR3) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 + \_SB.PCI0.LPCB.EC.DKR2 = 1 + \_SB.PCI0.LPCB.EC.DKR3 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) - Store (0, \_SB.PCI0.LPCB.EC.DKR2) - Store (0, \_SB.PCI0.LPCB.EC.DKR3) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 + \_SB.PCI0.LPCB.EC.DKR2 = 0 + \_SB.PCI0.LPCB.EC.DKR3 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl index 62e7b37bb47..99846368606 100644 --- a/src/mainboard/lenovo/t410/acpi/gpe.asl +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -5,8 +5,8 @@ Scope (\_GPE) Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c index f957656b516..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/t410/acpi_tables.c +++ b/src/mainboard/lenovo/t410/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index 8751f0248ca..40a57cb578d 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -20,7 +20,7 @@ DefinitionBlock( #include "acpi/platform.asl" /* global NVS and variables */ - #include + #include /* General Purpose Events */ #include "acpi/gpe.asl" diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 08b5d2f9099..ad88a2eb71b 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 991eadbff2b..e4b6fbf0f0a 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/t420/acpi/platform.asl +++ b/src/mainboard/lenovo/t420/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/t420/acpi_tables.c +++ b/src/mainboard/lenovo/t420/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index ef40fc4dde3..ffd1d2491f7 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 991eadbff2b..e4b6fbf0f0a 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 71068d00051..4b9567579f1 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 0f49600c7d1..e402ffa605c 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,6 +1,5 @@ bootblock-y += gpio.c romstage-y += gpio.c -smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/t430/acpi/platform.asl +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index 5cb1fd38d5f..43c73025f26 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f3524cd9995..cafc2dffb20 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -16,12 +16,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 196a0981f67..43a2a923017 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 4bdb923b12f..d9ececa7a1d 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -20,13 +20,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t440p/Makefile.inc b/src/mainboard/lenovo/t440p/Makefile.inc index fa6e7af2025..ebe01aea99c 100644 --- a/src/mainboard/lenovo/t440p/Makefile.inc +++ b/src/mainboard/lenovo/t440p/Makefile.inc @@ -1,3 +1,2 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl index c389fb6ba4b..f5a4df75f43 100644 --- a/src/mainboard/lenovo/t440p/acpi/platform.asl +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -3,8 +3,8 @@ Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c index c235d1228a5..0301443f88b 100644 --- a/src/mainboard/lenovo/t440p/acpi_tables.c +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default. */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 9359bb4e5da..8db28cbfaec 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -4,21 +4,17 @@ chip northbridge/intel/haswell register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - register "gpu_panel_power_backlight_off_delay" = "1" - register "gpu_panel_power_backlight_on_delay" = "1" - register "gpu_panel_power_cycle_delay" = "6" - register "gpu_panel_power_down_delay" = "500" - register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight_pwm_hz" = "220" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 220, + }" register "ec_present" = "true" device cpu_cluster 0x0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index ab5aa4de91b..a3b838ba10c 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index cc1e7f29996..296be73181f 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index ab5aa4de91b..a3b838ba10c 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index e4655b2f29d..7adc0f5c14d 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index 5ded71b41a4..000367bc30d 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -7,3 +7,4 @@ bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c +ramstage-y += cstates.c diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl index c9551b5ca18..2e3bfc06c8d 100644 --- a/src/mainboard/lenovo/t60/acpi/platform.asl +++ b/src/mainboard/lenovo/t60/acpi/platform.asl @@ -56,14 +56,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index 62fcfe95e65..8f4f83b826e 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/t60/cstates.c b/src/mainboard/lenovo/t60/cstates.c new file mode 100644 index 00000000000..7a1e4d60016 --- /dev/null +++ b/src/mainboard/lenovo/t60/cstates.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, + { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, + { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index ee5ec8feb81..7ebe25e0af3 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -12,18 +12,6 @@ #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -static acpi_cstate_t cst_entries[] = { - { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, - { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, - { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - static void mainboard_init(struct device *dev) { struct southbridge_intel_i82801gx_config *config; diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 69ffe332099..12a1e53be0b 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include "dock.h" diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c index 9eef15936a6..566cad75bbf 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c +++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->pwrs = 1; /* Power state (AC = 1) */ - gnvs->cmap = 0x01; /* Enable COM 1 port */ } diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/x131e/acpi/platform.asl +++ b/src/mainboard/lenovo/x131e/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/x131e/acpi_tables.c +++ b/src/mainboard/lenovo/x131e/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index ddbfd984914..18ed380428e 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -20,13 +20,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" - - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" end end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index e9e74ddf3fe..ea3bd287b59 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += spd -smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 34eaa75c13f..b4d3800aa26 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -18,13 +18,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/x200/acpi/dock.asl b/src/mainboard/lenovo/x200/acpi/dock.asl index b612f0687d2..ba8f46ef39d 100644 --- a/src/mainboard/lenovo/x200/acpi/dock.asl +++ b/src/mainboard/lenovo/x200/acpi/dock.asl @@ -12,14 +12,14 @@ Scope (\_SB) { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } @@ -32,16 +32,15 @@ Scope (\_SB) /* Returns 0x7 (dock absent) or 0x3 (dock present) */ Method(GGID, 0, NotSerialized) { - Store(G_ID, Local0) - if (LEqual(Local0, 0xFFFFFFFF)) + Local0 = G_ID + if (Local0 == 0xFFFFFFFF) { - Store(Or (Or (GP02, ShiftLeft(GP03, 1)), - ShiftLeft(GP04, 2)), Local0) - If (LEqual(Local0, 0x00)) + Local0 = GP02 | (GP03 << 1) | (GP04 << 2) + If (Local0 == 0x00) { - Store(0x03, Local0) + Local0 = 0x03 } - Store(Local0, G_ID) + G_ID = Local0 } return (Local0) } @@ -68,8 +67,8 @@ Scope(\_SB.PCI0.LPCB.EC) /* Undock button on dock */ Method(_Q50, 0, NotSerialized) { - Store(\_SB.DOCK.GGID (), Local0) - if (LNotEqual(Local0, 0x07)) + Local0 = \_SB.DOCK.GGID () + if (Local0 != 0x07) { Notify(\_SB.DOCK, 3) } @@ -83,16 +82,16 @@ Scope(\_SB.PCI0.LPCB.EC) /* Unplug power: only disconnect dock on force eject */ Method(_Q5A, 0, NotSerialized) { - Store(\_SB.DOCK.GGID (), Local0) - if (LEqual(Local0, 0x07)) + Local0 = \_SB.DOCK.GGID () + if (Local0 == 0x07) { Notify(\_SB.DOCK, 3) } - if (LEqual(Local0, 0x03)) + if (Local0 == 0x03) { Sleep(0x64) - Store(DKR1, Local1) - if (LEqual(Local1, 1)) + Local1 = DKR1 + if (Local1 == 1) { Notify(\_SB.DOCK, 0) } diff --git a/src/mainboard/lenovo/x200/acpi/gpe.asl b/src/mainboard/lenovo/x200/acpi/gpe.asl index 62e7b37bb47..99846368606 100644 --- a/src/mainboard/lenovo/x200/acpi/gpe.asl +++ b/src/mainboard/lenovo/x200/acpi/gpe.asl @@ -5,8 +5,8 @@ Scope (\_GPE) Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index 10cadf2dbf6..aa292487043 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -26,12 +26,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -61,14 +61,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index b26996e4383..9e0ae85adc0 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -5,17 +5,10 @@ #include #include #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index 80e513cd723..d185f5cbe54 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -3,7 +3,6 @@ bootblock-y += early_init.c smm-y += dock.c -smm-y += smihandler.c romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl index 0bf5a2542e9..311e620ab70 100644 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ b/src/mainboard/lenovo/x201/acpi/dock.asl @@ -12,18 +12,18 @@ Scope (\_SB) { if (Arg0) { /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - Store (1, \_SB.PCI0.LPCB.EC.DKR2) - Store (1, \_SB.PCI0.LPCB.EC.DKR3) + \GP28 = 1 + \_SB.PCI0.LPCB.EC.DKR1 = 1 + \_SB.PCI0.LPCB.EC.DKR2 = 1 + \_SB.PCI0.LPCB.EC.DKR3 = 1 } else { /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) - Store (0, \_SB.PCI0.LPCB.EC.DKR2) - Store (0, \_SB.PCI0.LPCB.EC.DKR3) + \GP28 = 0 + \_SB.PCI0.LPCB.EC.DKR1 = 0 + \_SB.PCI0.LPCB.EC.DKR2 = 0 + \_SB.PCI0.LPCB.EC.DKR3 = 0 } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Local0 = Arg0 ^ \_SB.PCI0.LPCB.EC.DKR1 Return (Local0) } diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index 62e7b37bb47..99846368606 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -5,8 +5,8 @@ Scope (\_GPE) Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index b03f45f8f07..44b06c6a05d 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) @@ -56,47 +56,47 @@ Scope(\_SB) */ /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) + OSYS = 2000 If (CondRefOf(_OSI)) { If (_OSI("Windows 2001")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + OSYS = 2002 } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2006")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + OSYS = 2009 } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + OSYS = 2012 } } } diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index f957656b516..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 8751f0248ca..40a57cb578d 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -20,7 +20,7 @@ DefinitionBlock( #include "acpi/platform.asl" /* global NVS and variables */ - #include + #include /* General Purpose Events */ #include "acpi/gpe.asl" diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 08b5d2f9099..ad88a2eb71b 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index d870c4dd198..b104bb52a98 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 609036d61c5..667b280f0cd 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 5316d24d880..8e801f145dd 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/early_init.c bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/early_init.c diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index 40b9a535b61..c4becafc2ae 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -16,8 +16,8 @@ Method(_PTS,1) Method(_WAK,1) { /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) + \_TZ.MEB1 = 0 + \_TZ.MEB2 = 0 /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 0f32e9f90cd..36d3e85c1ef 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 27d42b68bed..de91bbacd56 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -21,13 +21,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index 56fa18b13ae..7bdd496a5fb 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -8,3 +8,4 @@ bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c +ramstage-y += cstates.c diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index 26f555f4348..5fd69781fba 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -27,7 +27,7 @@ Scope (\_SB) TRAP(SMI_DOCK_DISCONNECT) } - Xor(Arg0, DSTA, Local0) + Local0 = Arg0 ^ DSTA Return (Local0) } diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 62e7b37bb47..99846368606 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -5,8 +5,8 @@ Scope (\_GPE) Method(_L18, 0, NotSerialized) { /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + Local0 = \_SB.PCI0.LPCB.EC.WAKE /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } } diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index c9551b5ca18..50da033b2d4 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -24,12 +24,12 @@ Method(_WAK,1) // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -56,14 +56,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index 62fcfe95e65..8f4f83b826e 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -1,14 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable both COM ports */ - gnvs->cmap = 0x01; - gnvs->cmbp = 0x01; - /* Temperature at which OS will shutdown */ gnvs->tcrt = 100; /* Temperature at which OS will throttle CPU */ diff --git a/src/mainboard/lenovo/x60/cstates.c b/src/mainboard/lenovo/x60/cstates.c new file mode 100644 index 00000000000..c6237bc5924 --- /dev/null +++ b/src/mainboard/lenovo/x60/cstates.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#define MWAIT_RES(state, sub_state) \ + { \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, \ + .addrl = (((state) << 4) | (sub_state)), \ + .addrh = 0, \ + } + +static acpi_cstate_t cst_entries[] = { + { + .ctype = 1, + .latency = 1, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + .ctype = 2, + .latency = 1, + .power = 500, + .resource = MWAIT_RES(1, 0), + }, + { + .ctype = 3, + .latency = 17, + .power = 250, + .resource = MWAIT_RES(2, 0), + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index f6930bb93f8..a9946b25d1e 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -15,43 +15,6 @@ #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT -#define MWAIT_RES(state, sub_state) \ - { \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_ACCESS_SIZE_UNDEFINED, \ - .addrl = (((state) << 4) | (sub_state)), \ - .addrh = 0, \ - } - -static acpi_cstate_t cst_entries[] = { - { - .ctype = 1, - .latency = 1, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - { - .ctype = 2, - .latency = 1, - .power = 500, - .resource = MWAIT_RES(1, 0), - }, - { - .ctype = 3, - .latency = 17, - .power = 250, - .resource = MWAIT_RES(2, 0), - }, -}; - -int get_cst_entries(acpi_cstate_t **entries) -{ - *entries = cst_entries; - return ARRAY_SIZE(cst_entries); -} - static void mainboard_init(struct device *dev) { struct device *idedev, *sdhci_dev; diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index b5889db4061..ab8a1e89a8b 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/libretrend/Kconfig b/src/mainboard/libretrend/Kconfig index 7e1eacdd71b..0612ec7fb38 100644 --- a/src/mainboard/libretrend/Kconfig +++ b/src/mainboard/libretrend/Kconfig @@ -10,7 +10,6 @@ endchoice source "src/mainboard/libretrend/*/Kconfig" config MAINBOARD_VENDOR - string "Mainboard Vendor" default "Libretrend" endif # VENDOR_LIBRETREND diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index ca9e002a366..59f7d921ddb 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -2,134 +2,134 @@ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) + CMTI = 0x13 + GPSL = 0 } /* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { +If (UOM0 <= 9) { Scope (\_GPE) { Method (_L13) { UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + if (GPB0 == PLC0) { + PLC0 = ~PLC0 + \_SB.PT0D = PLC0 } } } } /* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { +If (UOM1 <= 9) { Scope (\_GPE) { Method (_L14) { UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + if (GPB1 == PLC1) { + PLC1 = ~PLC1 + \_SB.PT1D = PLC1 } } } } /* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { +If (UOM2 <= 9) { Scope (\_GPE) { Method (_L15) { UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + if (GPB2 == PLC2) { + PLC2 = ~PLC2 + \_SB.PT2D = PLC2 } } } } /* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { +If (UOM3 <= 9) { Scope (\_GPE) { Method (_L16) { UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + if (GPB3 == PLC3) { + PLC3 = ~PLC3 + \_SB.PT3D = PLC3 } } } } /* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { +If (UOM4 <= 9) { Scope (\_GPE) { Method (_L19) { UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + if (GPB4 == PLC4) { + PLC4 = ~PLC4 + \_SB.PT4D = PLC4 } } } } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { +If (UOM5 <= 9) { Scope (\_GPE) { Method (_L1A) { UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + if (GPB5 == PLC5) { + PLC5 = ~PLC5 + \_SB.PT5D = PLC5 } } } } /* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { +If (UOM6 <= 9) { Scope (\_GPE) { /* Method (_L1C) { */ Method (_L06) { UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + if (GPB6 == PLC6) { + PLC6 = ~PLC6 + \_SB.PT6D = PLC6 } } } } /* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { +If (UOM7 <= 9) { Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + if (GPB7 == PLC7) { + PLC7 = ~PLC7 + \_SB.PT7D = PLC7 } } } } /* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { +If (UOM8 <= 9) { Scope (\_GPE) { Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + if (G8IS == PLC8) { + PLC8 = ~PLC8 + \_SB.PT8D = PLC8 } } } } /* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { +If (UOM9 <= 9) { Scope (\_GPE) { Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + if (G9IS == 0) { + \_SB.PT9D = 1 } } } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index e0804ed1593..5b5fa2b048a 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -369,20 +369,20 @@ DefinitionBlock ( Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return(OSVR)} /* OS version was already detected */ if(CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } Return(OSVR) @@ -394,17 +394,17 @@ DefinitionBlock ( { \_SB.CIRQ() } - Store(Arg0, PMOD) + PMOD = Arg0 } Method(CIRQ, 0x00, NotSerialized){ - Store(0, PIRA) - Store(0, PIRB) - Store(0, PIRC) - Store(0, PIRD) - Store(0, PIRE) - Store(0, PIRF) - Store(0, PIRG) - Store(0, PIRH) + PIRA = 0 + PIRB = 0 + PIRC = 0 + PIRD = 0 + PIRE = 0 + PIRF = 0 + PIRG = 0 + PIRH = 0 } Name(IRQB, ResourceTemplate(){ @@ -432,7 +432,7 @@ DefinitionBlock ( } /* End Method(_SB.INTA._STA) */ Method(_DIS ,0) { - Store(0, PIRA) + PIRA = 0 } /* End Method(_SB.INTA._DIS) */ Method(_PRS ,0) { @@ -441,7 +441,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRA, IRQN) + IRQN = 1 << PIRA Return(IRQB) } /* Method(_SB.INTA._CRS) */ @@ -451,9 +451,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRA) + PIRA = Local0 } /* End Method(_SB.INTA._SRS) */ } /* End Device(INTA) */ @@ -470,7 +470,7 @@ DefinitionBlock ( } /* End Method(_SB.INTB._STA) */ Method(_DIS ,0) { - Store(0, PIRB) + PIRB = 0 } /* End Method(_SB.INTB._DIS) */ Method(_PRS ,0) { @@ -479,7 +479,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRB, IRQN) + IRQN = 1 << PIRB Return(IRQB) } /* Method(_SB.INTB._CRS) */ @@ -489,9 +489,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRB) + PIRB = Local0 } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -508,7 +508,7 @@ DefinitionBlock ( } /* End Method(_SB.INTC._STA) */ Method(_DIS ,0) { - Store(0, PIRC) + PIRC = 0 } /* End Method(_SB.INTC._DIS) */ Method(_PRS ,0) { @@ -517,7 +517,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRC, IRQN) + IRQN = 1 << PIRC Return(IRQB) } /* Method(_SB.INTC._CRS) */ @@ -527,9 +527,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRC) + PIRC = Local0 } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -546,7 +546,7 @@ DefinitionBlock ( } /* End Method(_SB.INTD._STA) */ Method(_DIS ,0) { - Store(0, PIRD) + PIRD = 0 } /* End Method(_SB.INTD._DIS) */ Method(_PRS ,0) { @@ -555,7 +555,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRD, IRQN) + IRQN = 1 << PIRD Return(IRQB) } /* Method(_SB.INTD._CRS) */ @@ -565,9 +565,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRD) + PIRD = Local0 } /* End Method(_SB.INTD._SRS) */ } /* End Device(INTD) */ @@ -584,7 +584,7 @@ DefinitionBlock ( } /* End Method(_SB.INTE._STA) */ Method(_DIS ,0) { - Store(0, PIRE) + PIRE = 0 } /* End Method(_SB.INTE._DIS) */ Method(_PRS ,0) { @@ -593,7 +593,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRE, IRQN) + IRQN = 1 << PIRE Return(IRQB) } /* Method(_SB.INTE._CRS) */ @@ -603,9 +603,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRE) + PIRE = Local0 } /* End Method(_SB.INTE._SRS) */ } /* End Device(INTE) */ @@ -622,7 +622,7 @@ DefinitionBlock ( } /* End Method(_SB.INTF._STA) */ Method(_DIS ,0) { - Store(0, PIRF) + PIRF = 0 } /* End Method(_SB.INTF._DIS) */ Method(_PRS ,0) { @@ -631,7 +631,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRF, IRQN) + IRQN = 1 << PIRF Return(IRQB) } /* Method(_SB.INTF._CRS) */ @@ -641,9 +641,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRF) + PIRF = Local0 } /* End Method(_SB.INTF._SRS) */ } /* End Device(INTF) */ @@ -660,7 +660,7 @@ DefinitionBlock ( } /* End Method(_SB.INTG._STA) */ Method(_DIS ,0) { - Store(0, PIRG) + PIRG = 0 } /* End Method(_SB.INTG._DIS) */ Method(_PRS ,0) { @@ -669,7 +669,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRG, IRQN) + IRQN = 1 << PIRG Return(IRQB) } /* Method(_SB.INTG._CRS) */ @@ -679,9 +679,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRG) + PIRG = Local0 } /* End Method(_SB.INTG._SRS) */ } /* End Device(INTG) */ @@ -698,7 +698,7 @@ DefinitionBlock ( } /* End Method(_SB.INTH._STA) */ Method(_DIS ,0) { - Store(0, PIRH) + PIRH = 0 } /* End Method(_SB.INTH._DIS) */ Method(_PRS ,0) { @@ -707,7 +707,7 @@ DefinitionBlock ( Method(_CRS ,0) { CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIRH, IRQN) + IRQN = 1 << PIRH Return(IRQB) } /* Method(_SB.INTH._CRS) */ @@ -717,9 +717,9 @@ DefinitionBlock ( /* Use lowest available IRQ */ FindSetRightBit(IRQM, Local0) if (Local0) { - Decrement(Local0) + Local0-- } - Store(Local0, PIRH) + PIRH = Local0 } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ @@ -750,13 +750,13 @@ DefinitionBlock ( Method(\_PTS, 1) { /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) + if (Arg0 == 3){ + URRE = 0 } /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 } /* End Method(\_PTS) */ /* @@ -777,16 +777,16 @@ DefinitionBlock ( Method(\_WAK, 1) { /* Re-enable HPET */ - Store(1,HPDE) + HPDE = 1 /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) + if (Arg0 == 3){ + URRE = 1 } /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) + Local1 = PWST + PWST = Local1 Return(WKST) } /* End Method(\_WAK) */ @@ -861,7 +861,7 @@ DefinitionBlock ( Method (_OSC, 4) { /* Check for PCI/PCI-X/PCIe GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -870,7 +870,7 @@ DefinitionBlock ( { /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } /* End _OSC */ @@ -1210,10 +1210,10 @@ DefinitionBlock ( * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + MM1B = TOM1 + Local0 = 0x10000000 << 4 + Local0 -= TOM1 + MM1L = Local0 Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/msi/ms7707/acpi_tables.c +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index db48656489a..2ccf7c63ab9 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,12 +1,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index d51391da424..8b6e3aea6c7 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -51,6 +51,7 @@ chip soc/intel/xeon_sp/cpx end device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 on end # Host bridge device pci 04.0 on end # Intel SkyLake-E CBDMA Registers device pci 04.1 on end # Intel SkyLake-E CBDMA Registers @@ -63,6 +64,9 @@ chip soc/intel/xeon_sp/cpx device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers device pci 05.2 on end # Intel SkyLake-E RAS device pci 05.4 on end # Intel SkyLake-E IOAPIC + device pci 07.0 on end + device pci 07.4 on end + device pci 07.7 on end device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers @@ -83,8 +87,11 @@ chip soc/intel/xeon_sp/cpx device pci 1f.0 on chip drivers/ipmi # BMC KCS device pnp ca2.0 on end + use pch_gpio as gpio_dev register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" + register "post_complete_gpio" = "GPP_B20" + register "post_complete_invert" = "1" end chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index 415b26d5d8c..7adbcf24442 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -100,9 +100,8 @@ enum cb_err ipmi_set_post_start(const int port) void init_frb2_wdt(void) { - char val[VPD_LEN]; - uint8_t enable, action; - uint16_t countdown; + uint8_t enable; + int action, countdown; if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { printk(BIOS_DEBUG, "Got VPD %s value: %d\n", FRB2_TIMER, enable); @@ -113,8 +112,7 @@ void init_frb2_wdt(void) } if (enable) { - if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { - countdown = (uint16_t)atol(val); + if (vpd_get_int(FRB2_COUNTDOWN, VPD_RW_THEN_RO, &countdown)) { printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", countdown * 100); } else { @@ -123,15 +121,15 @@ void init_frb2_wdt(void) countdown = FRB2_COUNTDOWN_DEFAULT; } - if (vpd_gets(FRB2_ACTION, val, VPD_LEN, VPD_RW_THEN_RO)) { - action = (uint8_t)atol(val); + if (vpd_get_int(FRB2_ACTION, VPD_RW_THEN_RO, &action)) { printk(BIOS_DEBUG, "FRB2 timer action set to: %d\n", action); } else { printk(BIOS_DEBUG, "FRB2 timer action use default value: %d\n", FRB2_ACTION_DEFAULT); action = FRB2_ACTION_DEFAULT; } - ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, action); + ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, (uint16_t)countdown, + (uint8_t)action); } else { printk(BIOS_DEBUG, "Disable FRB2 timer\n"); ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); diff --git a/src/mainboard/ocp/deltalake/loglevel_vpd.c b/src/mainboard/ocp/deltalake/loglevel_vpd.c index 3faf37a0ead..78808797a8c 100644 --- a/src/mainboard/ocp/deltalake/loglevel_vpd.c +++ b/src/mainboard/ocp/deltalake/loglevel_vpd.c @@ -9,10 +9,8 @@ int get_console_loglevel(void) { int log_level = COREBOOT_LOG_LEVEL_DEFAULT; - char val_str[VPD_LEN]; - if (vpd_gets(COREBOOT_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { - log_level = (int)atol(val_str); + if (vpd_get_int(COREBOOT_LOG_LEVEL, VPD_RW_THEN_RO, &log_level)) { if (log_level < 0 || log_level >= BIOS_NEVER) log_level = COREBOOT_LOG_LEVEL_DEFAULT; } diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 72a74daeccc..74980635be7 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -5,8 +5,6 @@ #include #include #include -#include -#include #include #include #include @@ -215,7 +213,7 @@ static int create_smbios_type9(int *handle, unsigned long *current) uint8_t characteristics_1 = 0; uint8_t characteristics_2 = 0; uint32_t vendor_device_id; - uint32_t stack_busnos[6]; + uint8_t stack_busnos[MAX_IIO_STACK]; pci_devfn_t pci_dev; unsigned int cap; uint16_t sltcap; @@ -223,7 +221,8 @@ static int create_smbios_type9(int *handle, unsigned long *current) if (ipmi_get_pcie_config(&pcie_config) != CB_SUCCESS) printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); - get_stack_busnos(stack_busnos); + for (index = 0; index < ARRAY_SIZE(stack_busnos); index++) + stack_busnos[index] = get_stack_busno(index); for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { if (pcie_config == PCIE_CONFIG_A) { @@ -367,11 +366,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, }; - -static void pull_post_complete_pin(void *unused) -{ - /* Pull Low post complete pin */ - gpio_output(GPP_B20, 0); -} - -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index f0cdd3dbb76..9b182a215c3 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -19,7 +19,7 @@ static void mainboard_config_upd(FSPM_UPD *mupd) { uint8_t val; - char val_str[VPD_LEN]; + int val_int; /* Send FSP log message to SOL */ if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) @@ -33,15 +33,14 @@ static void mainboard_config_upd(FSPM_UPD *mupd) if (mupd->FspmConfig.SerialIoUartDebugEnable) { /* FSP debug log level */ - if (vpd_gets(FSP_LOG_LEVEL, val_str, VPD_LEN, VPD_RW_THEN_RO)) { - val = (uint8_t)atol(val_str); - if (val > 0x0f) { + if (vpd_get_int(FSP_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) { + if (val_int < 0 || val_int > 0x0f) { printk(BIOS_DEBUG, "Invalid DebugPrintLevel value from VPD: " - "%d\n", val); - val = FSP_LOG_LEVEL_DEFAULT; + "%d\n", val_int); + val_int = FSP_LOG_LEVEL_DEFAULT; } - printk(BIOS_DEBUG, "Setting DebugPrintLevel %d from VPD\n", val); - mupd->FspmConfig.DebugPrintLevel = val; + printk(BIOS_DEBUG, "Setting DebugPrintLevel %d from VPD\n", val_int); + mupd->FspmConfig.DebugPrintLevel = (uint8_t)val_int; } else { printk(BIOS_INFO, "Not able to get VPD %s, default set " "DebugPrintLevel to %d\n", FSP_LOG_LEVEL, @@ -65,15 +64,14 @@ static void mainboard_config_upd(FSPM_UPD *mupd) * Following code is effective when MemRefreshWaterMark patch is added to FSP * and when corresponding VPD variable is set. */ - if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { - val = (uint8_t)atol(val_str); - if (val > 2) { + if (vpd_get_int(FSPM_MEMREFRESHWATERMARK, VPD_RW_THEN_RO, &val_int)) { + if (val_int < 0 || val_int > 2) { printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: " - "%d\n", val); - val = FSPM_MEMREFRESHWATERMARK_DEFAULT; + "%d\n", val_int); + val_int = FSPM_MEMREFRESHWATERMARK_DEFAULT; } - printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val); - mupd->FspmConfig.UnusedUpdSpace0[0] = val; + printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val_int); + mupd->FspmConfig.UnusedUpdSpace0[0] = (uint8_t)val_int; } } diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 71a3b092023..82989ffd78a 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -3,9 +3,6 @@ #ifndef DELTALAKE_VPD_H #define DELTALAKE_VPD_H -/* VPD variable maximum length */ -#define VPD_LEN 10 - /* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */ #define FRB2_TIMER "frb2_timer_enable" #define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */ diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c index 300e8f62787..b6e3846f281 100644 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ b/src/mainboard/ocp/tiogapass/acpi_tables.c @@ -1,12 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - acpi_init_gnvs(gnvs); -} void mainboard_fill_fadt(acpi_fadt_t *fadt) { diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 0e520f015d7..29148d14eca 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index 9b1ea087bdd..86b9433353e 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 297eeb4f31c..9ec8e6ef41f 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -46,47 +46,47 @@ Scope(\_SB) */ /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) + OSYS = 2000 If (CondRefOf(_OSI)) { If (_OSI("Windows 2001")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) + OSYS = 2002 } If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) + OSYS = 2001 } If (_OSI("Windows 2006")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) + OSYS = 2006 } If (_OSI("Windows 2009")) { - Store (2009, OSYS) + OSYS = 2009 } If (_OSI("Windows 2012")) { - Store (2012, OSYS) + OSYS = 2012 } } } diff --git a/src/mainboard/packardbell/ms2290/acpi/thermal.asl b/src/mainboard/packardbell/ms2290/acpi/thermal.asl index 8d24127748f..a6935041b84 100644 --- a/src/mainboard/packardbell/ms2290/acpi/thermal.asl +++ b/src/mainboard/packardbell/ms2290/acpi/thermal.asl @@ -6,13 +6,13 @@ Scope(\_TZ) Method(C2K, 1, NotSerialized) { - Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) - if (LLessEqual(Local0, 2732)) { + Local0 = Arg0 * 10 + Local0 += 2732 + if (Local0 <= 2732) { Return (3000) } - if (LGreater(Local0, 4012)) { + if (Local0 > 4012) { Return (3000) } Return (Local0) @@ -25,10 +25,10 @@ Scope(\_TZ) } Method(_TMP) { /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + If (!MEBT && (\_SB.PCI0.LPCB.EC.TMP0 == 128)) { Return (C2K(40)) } - Store (1, MEBT) + MEBT = 1 Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) } } diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c deleted file mode 100644 index 17ed31edb44..00000000000 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index 591cc1ddf59..f576551fd86 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -15,7 +15,7 @@ DefinitionBlock( #include "acpi/platform.asl" /* global NVS and variables */ - #include + #include /* General Purpose Events */ #include "acpi/gpe.asl" diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index b7f9aa93c9d..517c5e50b3f 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index 5fe4a4260e8..7538af02313 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -6,10 +6,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index a8a22711d60..203e7a5464e 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -15,7 +15,7 @@ config BOARD_PRODRIVE_HERMES_BASEBOARD select SOC_INTEL_COMMON_BLOCK_HDA_VERB select AZALIA_PLUGIN_SUPPORT select ONBOARD_VGA_IS_PRIMARY - select DISABLE_ACPI_HIBERNATE + select HAVE_ACPI_RESUME if BOARD_PRODRIVE_HERMES_BASEBOARD diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 25fde349e6e..d7ecdeca482 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -3,17 +3,20 @@ #include #include #include +#include #include "variants/baseboard/include/eeprom.h" +#define I2C_ADDR_EEPROM 0x57 + /* * Check Signature in EEPROM (M24C32-FMN6TP) * If signature is there we assume that that the content is valid */ -int check_signature(u8 addr, const size_t offset, const uint64_t signature) +int check_signature(const size_t offset, const uint64_t signature) { u8 blob[8] = {0}; - if (!read_write_config(addr, blob, offset, 0, ARRAY_SIZE(blob))) { + if (!read_write_config(blob, offset, 0, ARRAY_SIZE(blob))) { /* Check signature */ if (*(uint64_t *)blob == signature) { printk(BIOS_DEBUG, "CFG EEPROM: Signature valid.\n"); @@ -26,13 +29,12 @@ int check_signature(u8 addr, const size_t offset, const uint64_t signature) } /* Read data from offset and write it to offset in UPD */ -bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, - size_t size) +bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size) { int ret = 0; u32 smb_ctrl_reg = pci_read_config32(PCH_DEV_SMBUS, HOSTC); - pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); + pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg | I2C_EN); printk(BIOS_SPEW, "%s\tOffset: %04zx\tSize: %02zx\n", __func__, read_offset, size); @@ -41,7 +43,7 @@ bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_off for (size_t i = 0; i < size; i = i + 2) { u8 tmp[2] = {0}; - ret = do_smbus_process_call(SMBUS_IO_BASE, addr, 0, + ret = do_smbus_process_call(SMBUS_IO_BASE, I2C_ADDR_EEPROM, 0, swab16(read_offset + i), (uint16_t *)&tmp[0]); if (ret < 0) break; diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 72ae014409d..b879be77952 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -19,13 +19,13 @@ void mainboard_silicon_init_params(FSPS_UPD *supd) params->SataLedEnable = 1; /* Overwrite params */ - if (!check_signature(I2C_ADDR_EEPROM, EEPROM_OFFSET_FSP_SIGNATURE, FSP_UPD_SIGNATURE)) + if (!check_signature(EEPROM_OFFSET_FSP_SIGNATURE, FSP_UPD_SIGNATURE)) return; for (u8 i = 0; i <= ARRAY_SIZE(parmas_list); i++) { if (ARRAY_SIZE(parmas_list) == 0) break; - read_write_config(I2C_ADDR_EEPROM, params, EEPROM_OFFSET_FSP_CONFIG + + read_write_config(params, EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, parmas_list[i].size); diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c index 6e88413f842..0ba9f451fdb 100644 --- a/src/mainboard/prodrive/hermes/romstage.c +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -19,11 +19,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); /* Overwrite memupd */ - if (!check_signature(I2C_ADDR_EEPROM, EEPROM_OFFSET_FSP_SIGNATURE, FSP_UPD_SIGNATURE)) + if (!check_signature(EEPROM_OFFSET_FSP_SIGNATURE, FSP_UPD_SIGNATURE)) return; for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) { - read_write_config(I2C_ADDR_EEPROM, memupd, EEPROM_OFFSET_FSP_CONFIG + + read_write_config(memupd, EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, parmas_list[i].size); diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index 096dc35785f..7f81842e212 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -102,11 +102,11 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D4, NONE), - /* I2S2 */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* M2_E_BT_PCMFRM_CRF_RST_n */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* M2_E_BT_PCMOUT_CLKREQ0 */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* M2_E_BT_PCMIN */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* M2_E_BT_PCMCLK */ + /* CNVi */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), /* M2_E_BT_PCMFRM_CRF_RST_n */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), /* M2_E_BT_PCMOUT_CLKREQ0 */ + PAD_NC(GPP_D7, NONE), /* M2_E_BT_PCMIN */ + PAD_NC(GPP_D8, NONE), /* M2_E_BT_PCMCLK */ /* ISH SPI */ PAD_NC(GPP_D9, NONE), @@ -389,6 +389,18 @@ const struct pad_config early_gpio_table[] = { /* LED */ PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */ + + /* UART0 */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + + /* UART1 */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ + + /* UART2 */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ }; void program_gpio_pads(void) diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index 85edbcf903b..95024b6ccd4 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -2,11 +2,6 @@ #include -#define HOSTC 0x40 -#define SMBUS_IO_BASE 0xefa0 -#define HOSTC_I2C_EN (1 << 2) -#define I2C_ADDR_EEPROM 0x57 - #if ENV_ROMSTAGE #define FSP_UPD_SIGNATURE FSPM_UPD_SIGNATURE #define EEPROM_OFFSET_FSP_SIGNATURE 0 @@ -28,6 +23,5 @@ typedef struct { size_t size; } fsp_params; -bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, - size_t size); -int check_signature(u8 addr, const size_t offset, const uint64_t signature); +bool read_write_config(void *blob, size_t read_offset, size_t write_offset, size_t size); +int check_signature(const size_t offset, const uint64_t signature); diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index b543a78c5c1..4d35c47ddba 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -85,43 +85,47 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n + # USB OC5-7: not connected + register "usb2_ports" = "{ + +#define HERMES_USB2_CONFIG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + [0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */ + [1] = HERMES_USB2_CONFIG(OC0), + [2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */ + [3] = HERMES_USB2_CONFIG(OC1), + [4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */ + [5] = HERMES_USB2_CONFIG(OC2), + [6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */ + [7] = HERMES_USB2_CONFIG(OC3), + [8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */ + [9] = HERMES_USB2_CONFIG(OC4), + [10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */ + [11] = USB2_PORT_EMPTY, + [12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */ + [13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */ + }" + # USB Config 2.0/3.0 # Enumeration starts at 0 # USB 3.0 # USB OC0: RP1 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB OC1: RP2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)" # USB OC2: Internal Header CN_USB3_HDR register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC2)" - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)" - - # USB 2.0 - # USB OC3: Internal Header USB2_HDR1 - register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" - - # USB OC4: Internal Header USB2_HDR2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC4)" - - # USB OC5-7: not connected - # BMC - register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" - # piggy-back - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - # M2 key E - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Thermal register "tcc_offset" = "1" # TCC of 99C diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c index c40769af982..6fc71fe0606 100644 --- a/src/mainboard/protectli/vault_bsw/acpi_tables.c +++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c @@ -3,14 +3,11 @@ #include #include #include +#include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 275594b48d9..ad764b7fd61 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -52,10 +52,6 @@ config MAINBOARD_VERSION default "1.0" if BOARD_PURISM_LIBREM13_V1 default "2.0" if BOARD_PURISM_LIBREM15_V2 -config MAX_CPUS - int - default 8 - config PRE_GRAPHICS_DELAY int default 50 diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c deleted file mode 100644 index e127a56a262..00000000000 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 0d0fc720f79..9995f6bd6f6 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -6,18 +6,20 @@ chip soc/intel/broadwell # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Set panel power delays - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 200, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on device pci 00.0 on end # host bridge diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c deleted file mode 100644 index 8fc2f9eaf7f..00000000000 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -void mainboard_pre_raminit(struct romstage_params *rp) -{ - /* Fill out PEI DATA */ - mainboard_fill_pei_data(&rp->pei_data); -} - -void mainboard_post_raminit(struct romstage_params *rp) -{ -} diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c index c3daf3c5ed1..93dd2702bfc 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c @@ -8,15 +8,16 @@ const u32 cim_verb_data[] = { 11, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x10ec0000), - AZALIA_PIN_CFG(0, 0x12, 0x40000000), - AZALIA_PIN_CFG(0, 0x15, 0x01214010), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x01a19130), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40422201), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x14, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x15, 0x02211010), /* Jack analog out */ + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x18, 0x02a11020), /* Jack analog mic */ + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* NC */ 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ 0x80860101, /* Subsystem ID */ @@ -24,8 +25,8 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(2, 0x80860101), AZALIA_PIN_CFG(2, 0x05, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560020), - AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index cd8fc66c1c1..c59f7fa9b0a 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -47,10 +47,6 @@ config OVERRIDE_DEVICETREE string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config MAX_CPUS - int - default 8 - config VGA_BIOS_ID string default "8086,1916" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index c59df405187..c3a9567ccfe 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -1,16 +1,17 @@ chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" - # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl index 241d090a036..8f195550eb3 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl @@ -40,21 +40,21 @@ Device (BAT) Method (_BIF, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BFCP, Index (PBIF, 2)) + PBIF [2] = BFCP /* Design Voltage */ - Store (BDVT, Index (PBIF, 4)) + PBIF [4] = BDVT /* Design Capacity */ - Store (BDCP, Index (PBIF, 1)) + PBIF [1] = BDCP /* Design Capacity of Warning */ - Store (BDCP / 0x32, Index (PBIF, 5)) + PBIF [5] = BDCP / 50 /* Design Capacity of Low */ - Store (BDCP / 0x64, Index (PBIF, 6)) + PBIF [6] = BDCP / 100 - Store (ToString (BSER, Ones), Index (PBIF, 0x0A)) + PBIF [10] = ToString (BSER, Ones) Return (PBIF) } @@ -72,34 +72,34 @@ Device (BAT) /* Check if AC is present */ If (ACEX) { /* Read battery status from EC */ - Store (BCST, Local0) + Local0 = BCST } Else { /* Always discharging when on battery power */ - Store (0x01, Local0) + Local0 = 0x01 } - Store (Local0, Index (PBST, 0)) + PBST [0] = Local0 /* Notify if battery state has changed since last time */ - If (LNotEqual (Local0, BSTP)) { - Store (Local0, BSTP) + If (Local0 != BSTP) { + BSTP = Local0 Notify (BAT, 0x80) } /* * 1: BATTERY PRESENT RATE */ - Store (BCRT, Index (PBST, 1)) + PBST [1] = BCRT /* * 2: BATTERY REMAINING CAPACITY */ - Store (BRCP, Index (PBST, 2)) + PBST [2] = BRCP /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BCVT, Index (PBST, 3)) + PBST [3] = BCVT Return (PBST) } diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 5698dcbbcf6..72eaca4bebd 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -56,24 +56,24 @@ Device (EC) Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (PWRS - 0x82, ACEX) + ACEX = PWRS - 0x82 /* Initialize LID switch state */ - Store (LIDS, \LIDS) + \LIDS = LIDS } // Close ? Method (_Q14, 0, NotSerialized) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } //Open Method (_Q15, 0, NotSerialized) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } @@ -81,7 +81,7 @@ Device (EC) // AC plugged Method (_Q13, 0, NotSerialized) { - Store (PWRS - 0x82, ACEX) + ACEX = PWRS - 0x82 Notify (BAT, 0x80) // Status Change Notify (BAT, 0x81) // Information Change Notify (AC, 0x80) // Status Change diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index 6b29a2ccd62..da471edd79a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -6,164 +6,174 @@ #include #include +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(UP_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)), -/* GPP_C6 - RESERVED */ -/* GPP_C7 - RESERVED */ -/* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), -/* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), -/* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE), 0), -/* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(DN_20K)), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)), -/* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8), -/* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), -/* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_A11, NONE, DEEP), + PAD_CFG_GPO(GPP_A12, 1, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_A23, NONE, DEEP), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_NC(GPP_B8, NONE), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), + PAD_CFG_GPO(GPP_B15, 0, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP), + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_E0, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_E6, 0, DEEP), + PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E9, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), + PAD_CFG_GPI_APIC_LOW(GPP_E22, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), }; -#endif +#endif /* __ACPI__ */ -#endif +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index d62e051ad00..42277c4c76a 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -52,14 +52,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If ((OSYS == 2001) && MPEN) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index 52c2fbbec13..cc64c301049 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl index b4d67f598b2..d003016c08c 100644 --- a/src/mainboard/roda/rk9/acpi/platform.asl +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -55,14 +55,6 @@ Scope(\_SB) \GOS() - /* And the OS workarounds start right after we know what we're - * running: Windows XP SP1 needs to have C-State coordination - * enabled in SMM. - */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { - // TRAP(61) // TODO - } - /* SMM power state and C4-on-C3 settings need to be updated */ // TRAP(43) // TODO } diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index b0e8993f11c..41b83c5d711 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -5,12 +5,10 @@ #include #include #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ /* Enable both COM ports */ gnvs->cmap = 0x01; diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index 95ecd11f354..d4115286984 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include diff --git a/src/mainboard/roda/rv11/acpi_tables.c b/src/mainboard/roda/rv11/acpi_tables.c index aea50a1774a..765575ca643 100644 --- a/src/mainboard/roda/rv11/acpi_tables.c +++ b/src/mainboard/roda/rv11/acpi_tables.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default */ gnvs->lids = 1; diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index f3108dbed9d..dc307752dc9 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -23,13 +23,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "0" - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "0" + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c3" = "0" end end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index a1edcaa3f45..fdba6719f5a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -23,13 +23,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "0" - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "0" + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c3" = "0" end end diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 1a3317d3717..c6974573d8b 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -4,14 +4,11 @@ #include #include #include -#if CONFIG(CHROMEOS) -#include -#endif -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* * Disable 3G in suspend by default. @@ -47,5 +44,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->tmax = MAX_TEMPERATURE; gnvs->flvl = 5; - gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO; + if (CONFIG(CHROMEOS) && ec_read(0xcb)) + gnvs_set_ecfw_rw(); } diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 06efaf8ff91..0f3ee5cdced 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -25,13 +25,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 0d6a2ac61f9..773c3441c3d 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index b2c1fcaf631..dfe9f476d52 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -3,12 +3,11 @@ #include #include #include -#include -#include +#include #include "thermal.h" -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* Enable Front USB ports in S3 by default */ gnvs->s3u0 = 1; @@ -45,7 +44,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; gnvs->flvl = 5; - - // Stumpy has no arms^H^H^H^HEC. - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index df640b55fd2..20c994eb795 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -17,13 +17,9 @@ chip northbridge/intel/sandybridge device lapic 0x0 on end device lapic 0xacac off end - register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) - register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) + register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 9cd81db1efe..635cc52edf9 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c index ccbb75ca14b..92b9d1c25d4 100644 --- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 2bef030268f..82117fb2969 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -3,12 +3,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0x0 on chip cpu/intel/model_206ax - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index a251d225461..cfaffe32a81 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -4,10 +4,8 @@ #include #include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Disable USB ports in S5 */ gnvs->s5u0 = 0; gnvs->s5u1 = 0; diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig index fda571dcfe8..a261abcb435 100644 --- a/src/mainboard/siemens/chili/Kconfig +++ b/src/mainboard/siemens/chili/Kconfig @@ -1,29 +1,37 @@ # SPDX-License-Identifier: GPL-2.0-only -if BOARD_SIEMENS_CHILI_BASE || BOARD_SIEMENS_CHILI_CHILI - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_SIEMENS_CHILI_COMMON + def_bool n select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID - select DRIVERS_I2C_LM96000 if BOARD_SIEMENS_CHILI_CHILI - select DRIVERS_UART_8250IO if BOARD_SIEMENS_CHILI_BASE select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT - select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_SIEMENS_CHILI_CHILI select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION - select SMBIOS_PROVIDED_BY_MOBO if BOARD_SIEMENS_CHILI_CHILI select SOC_INTEL_CANNONLAKE_PCH_H select SOC_INTEL_COFFEELAKE - select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_SIEMENS_CHILI_CHILI - select SECUNET_DMI if BOARD_SIEMENS_CHILI_CHILI + +config BOARD_SIEMENS_CHILI_BASE_OPTIONS + bool + select BOARD_SIEMENS_CHILI_COMMON + select DRIVERS_UART_8250IO + +config BOARD_SIEMENS_CHILI_CHILI_OPTIONS + bool + select BOARD_SIEMENS_CHILI_COMMON + select DRIVERS_I2C_LM96000 + select INTEL_LPSS_UART_FOR_CONSOLE + select SECUNET_DMI + select SMBIOS_PROVIDED_BY_MOBO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +if BOARD_SIEMENS_CHILI_COMMON config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name index ac4e31eef4e..1c8dab5f7f1 100644 --- a/src/mainboard/siemens/chili/Kconfig.name +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -4,6 +4,8 @@ comment "CHILI" config BOARD_SIEMENS_CHILI_BASE bool "-> Base board" + select BOARD_SIEMENS_CHILI_BASE_OPTIONS config BOARD_SIEMENS_CHILI_CHILI bool "-> Chili (AiO)" + select BOARD_SIEMENS_CHILI_CHILI_OPTIONS diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc index c57c0a50dc5..f3461344c31 100644 --- a/src/mainboard/siemens/chili/Makefile.inc +++ b/src/mainboard/siemens/chili/Makefile.inc @@ -2,6 +2,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +bootblock-y += bootblock.c + romstage-y += romstage.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/chili/bootblock.c b/src/mainboard/siemens/chili/bootblock.c new file mode 100644 index 00000000000..7ea7eb01865 --- /dev/null +++ b/src/mainboard/siemens/chili/bootblock.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +__weak void variant_configure_early_gpios(void) {} + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpios(); +} diff --git a/src/mainboard/siemens/chili/include/variant/gpio.h b/src/mainboard/siemens/chili/include/variant/gpio.h index 4258325cf9e..95d576294f6 100644 --- a/src/mainboard/siemens/chili/include/variant/gpio.h +++ b/src/mainboard/siemens/chili/include/variant/gpio.h @@ -3,6 +3,7 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H +void variant_configure_early_gpios(void); void variant_configure_gpios(void); #endif diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 949380177b8..ccbe8047f87 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -86,8 +86,9 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[5]" = "0" end device pci 1c.6 on # PCI Express Port 7 - register "PcieRpEnable[6]" = "1" # x1 M.2 (WLAN / BT) + register "PcieRpEnable[6]" = "1" register "PcieRpSlotImplemented[6]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 @@ -99,10 +100,11 @@ chip soc/intel/cannonlake device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 device pci 1b.0 on # PCI Express Port 17 - register "PcieRpEnable[16]" = "1" # x4 M.2/M + register "PcieRpEnable[16]" = "1" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1b.1 off end # PCI Express Port 18 device pci 1b.2 off end # PCI Express Port 19 diff --git a/src/mainboard/siemens/chili/variants/chili/Makefile.inc b/src/mainboard/siemens/chili/variants/chili/Makefile.inc index 251a2916a2d..4f1d0655fa8 100644 --- a/src/mainboard/siemens/chili/variants/chili/Makefile.inc +++ b/src/mainboard/siemens/chili/variants/chili/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio_early.c + romstage-y += romstage.c romstage-y += gpio.c diff --git a/src/mainboard/siemens/chili/variants/chili/gpio_early.c b/src/mainboard/siemens/chili/variants/chili/gpio_early.c new file mode 100644 index 00000000000..62d7783c4b1 --- /dev/null +++ b/src/mainboard/siemens/chili/variants/chili/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { +/* GPP_C8 UART0A_RXD 0x0000005044000702 */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* GPP_C9 UART0A_TXD 0x0000005144000700 */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* GPP_C20 UART2_RXD 0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GPP_C21 UART2_TXD 0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index fdaaaa182bd..01c8e93d289 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -1,9 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include +#include void bootblock_mainboard_init(void) { - lpc_configure_pads(); + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); } diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index b2cd449b874..bca0cbb4c85 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -173,6 +174,29 @@ static void config_pmic_imon(void) printk(BIOS_DEBUG, "PMIC: Configure PMIC IMON - End\n"); } +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + + /* Disable CPU power states (C-states) */ + silconfig->EnableCx = 0; + + /* Set max Pkg Cstate to PkgC0C1 */ + silconfig->PkgCStateLimit = 0; + + /* Disable PCIe Transmitter Half Swing for all RPs */ + memset(silconfig->PcieRpTransmitterHalfSwing, 0, + sizeof(silconfig->PcieRpTransmitterHalfSwing)); + + /* Disable PCI Express Active State Power Management for all RPs */ + memset(silconfig->PcieRpAspm, 0, + sizeof(silconfig->PcieRpAspm)); + + /* Disable PCI Express L1 Substate for all RPs */ + memset(silconfig->PcieRpL1Substates, 0, + sizeof(silconfig->PcieRpL1Substates)); +} + static void mainboard_init(void *chip_info) { const struct pad_config *pads; diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index bb45bbcfa6f..a29b7a60b4e 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -11,15 +11,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct pad_config *pads; const struct lpddr4_swizzle_cfg *cfg; const struct lpddr4_chan_swizzle_cfg *chan; uint8_t spd[0x80]; - size_t num; - - /* setup early gpio before memory */ - pads = variant_early_gpio_table(&num); - gpio_configure_pads(pads, num); /* * Get DRAM configuration data from hwinfo block. diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc index 07ebf9b0494..1d38b77ea02 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc @@ -1,4 +1,5 @@ -romstage-y += gpio.c +bootblock-y += gpio.c + romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 2e43648dd74..92b4e7c1b87 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -6,14 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. @@ -72,12 +64,28 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY - device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY - device pci 13.2 off end # - RP 4 - PCIe-A 2 - device pci 13.3 off end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY + register "pcie_rp_clkreq_pin[2]" = "0" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 - MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 off # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + end + device pci 13.3 off # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[0]" = "3" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 - FPGA + register "pcie_rp_clkreq_pin[1]" = "2" + register "pcie_rp_hotplug_enable[1]" = "0" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc index a6b80e0832e..152b46ece11 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += gpio.c +bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 1ac551a3739..047d9b11b95 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -6,15 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable all clkreq of PCIe root ports as SMARC interface do not - # have this pins. - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. @@ -64,12 +55,30 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - device pci 13.1 on end # - RP 3 - PCIe A 1 - device pci 13.2 on end # - RP 4 - PCIe-A 2 - device pci 13.3 on end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[1]" = "0" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc index a6b80e0832e..152b46ece11 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += gpio.c +bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index bc5a9cf6a72..66ff911a950 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -6,14 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. @@ -60,12 +52,30 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - device pci 13.1 on end # - RP 3 - PCIe A 1 - device pci 13.2 on end # - RP 4 - PCIe-A 2 - device pci 13.3 on end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[1]" = "0" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc index b1e6a0f74f2..e26339c5484 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc @@ -1,5 +1,6 @@ +bootblock-y += gpio.c + romstage-y += memory.c -romstage-y += gpio.c ramstage-y += gpio.c ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 7e5166650cc..6f378482384 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -6,15 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable all clkreq of PCIe root ports as SMARC interface do not - # have this pins. - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. @@ -61,12 +52,30 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - device pci 13.1 on end # - RP 3 - PCIe A 1 - device pci 13.2 on end # - RP 4 - PCIe-A 2 - device pci 13.3 on end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[1]" = "0" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc index bd81552afc6..3629aca053d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += gpio.c +bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index b5fb33b1a4f..5d288c0c6b1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -6,14 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "1" # 14.0 - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" # 14.1 - register "pcie_rp_clkreq_pin[2]" = "0" # 13.0 - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" # 13.1 - register "pcie_rp_clkreq_pin[4]" = "2" # 13.2 - register "pcie_rp_clkreq_pin[5]" = "3" # 13.3 - # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. @@ -63,12 +55,28 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - device pci 13.1 off end # - RP 3 - PCIe A 1 - device pci 13.2 on end # - RP 4 - PCIe-A 2 - device pci 13.3 on end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - device pci 14.1 off end # - RP 1 - PCIe-B 1 + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "0" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 off # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "2" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "3" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "1" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 off # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc index a6b80e0832e..152b46ece11 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += gpio.c +bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 024f2c5e076..9c1054a9e79 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -6,14 +6,6 @@ chip soc/intel/apollolake register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "1" @@ -34,12 +26,30 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - device pci 13.1 on end # - RP 3 - PCIe A 1 - device pci 13.2 on end # - RP 4 - PCIe-A 2 - device pci 13.3 on end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - device pci 14.1 on end # - RP 1 - PCIe-B 1 + device pci 13.0 on # - RP 2 - PCIe A 0 + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[2]" = "0" + end + device pci 13.1 on # - RP 3 - PCIe A 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[3]" = "0" + end + device pci 13.2 on # - RP 4 - PCIe-A 2 + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[4]" = "0" + end + device pci 13.3 on # - RP 5 - PCIe-A 3 + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[5]" = "0" + end + device pci 14.0 on # - RP 0 - PCIe-B 0 + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[0]" = "0" + end + device pci 14.1 on # - RP 1 - PCIe-B 1 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_hotplug_enable[1]" = "0" + end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c deleted file mode 100644 index 8ec5b118c58..00000000000 --- a/src/mainboard/supermicro/x10slm-f/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 6d64a902217..6cd3ab79335 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -4,13 +4,6 @@ chip northbridge/intel/haswell device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index bbd54b0e86f..b7057b07c9b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -13,6 +13,7 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND select NO_FADT_8042 + select DRIVERS_UART_8250IO if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES @@ -62,6 +63,10 @@ config FMDFILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB +config DRIVERS_IPMI_SUPERMICRO_OEM + bool + default y + config CBFS_SIZE hex default 0xb00000 @@ -70,10 +75,6 @@ config IRQ_SLOT_COUNT int default 18 -config MAX_CPUS - int - default 8 - config CONSOLE_POST bool default y diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c index 06d3bd43c34..00faa2e3f6c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c @@ -50,7 +50,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B17, NONE), PAD_NC(GPP_B18, NONE), PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */ PAD_NC(GPP_B21, NONE), PAD_NC(GPP_B22, NONE), PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c index 3ea21e03210..e3c5c4d9821 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c @@ -14,6 +14,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */ }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 093786cbd5a..d7f5df8c8be 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -76,6 +76,8 @@ chip soc/intel/skylake end device pci 1f.0 on # LPC Interface chip drivers/ipmi + use pch_gpio as gpio_dev + register "post_complete_gpio" = "GPP_B20" # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" register "bmc_boot_timeout" = "60" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c index 3ea21e03210..ea3ec6d0ae0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c @@ -14,6 +14,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* BMC POST_COMPLETE */ + PAD_CFG_GPO(GPP_B20, 0, PLTRST), }; void mainboard_configure_early_gpios(void) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 7757b69b3fd..58456071421 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -89,6 +89,9 @@ chip soc/intel/skylake end device pci 1f.0 on # LPC Interface chip drivers/ipmi + use pch_gpio as gpio_dev + register "bmc_jumper_gpio" = "GPP_D22" # JPB1 + register "post_complete_gpio" = "GPP_B20" # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" register "bmc_boot_timeout" = "60" diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c index 28c9d8ee6ed..230584ee4a1 100644 --- a/src/mainboard/supermicro/x9scl/acpi_tables.c +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { gnvs->tcrt = 100; gnvs->tpsv = 90; diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 9236f6f3da3..e1924c179ec 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -1,12 +1,9 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax # FIXME: check all registers - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c index 2b673021b5c..fd6070c06bc 100644 --- a/src/mainboard/system76/lemp9/bootblock.c +++ b/src/mainboard/system76/lemp9/bootblock.c @@ -4,7 +4,7 @@ #include #include "gpio.h" -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/up/squared/bootblock.c b/src/mainboard/up/squared/bootblock.c index fdaaaa182bd..34154e82d9b 100644 --- a/src/mainboard/up/squared/bootblock.c +++ b/src/mainboard/up/squared/bootblock.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include -void bootblock_mainboard_init(void) +#include "gpio_early.h" + +void bootblock_mainboard_early_init(void) { - lpc_configure_pads(); + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 31826750522..1aecc189c13 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -725,6 +725,11 @@ static const struct pad_config gpio_table[] = { /* SMB_DATA - SMB_DATA */ PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + /* + * LPC + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ + /* LPC_ILB_SERIRQ - LPC_ILB_SERIRQ */ PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), @@ -751,6 +756,25 @@ static const struct pad_config gpio_table[] = { /* LPC_FRAMEB - LPC_FRAMEB */ PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* ------- GPIO Group North ------- */ + + /* + * LPSS UART + * Note: It's unconfirmed if this redundancy to the bootblock table is necessary. + */ + + /* GPIO_38 - LPSS_UART0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* GPIO_39 - LPSS_UART0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), + + /* GPIO_42 - LPSS_UART1_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* GPIO_43 - LPSS_UART1_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), }; #endif /* CFG_GPIO_H */ diff --git a/src/mainboard/up/squared/gpio_early.h b/src/mainboard/up/squared/gpio_early.h new file mode 100644 index 00000000000..00aefc2d94d --- /dev/null +++ b/src/mainboard/up/squared/gpio_early.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#ifndef CFG_GPIO_EARLY_H +#define CFG_GPIO_EARLY_H + +static const struct pad_config early_gpio_table[] = { + /* ------- GPIO Group South-West ------- */ + + /* LPC_ILB_SERIRQ - LPC_ILB_SERIRQ */ + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + + /* LPC_CLKOUT0 - LPC_CLKOUT0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_CLKOUT1 - LPC_CLKOUT1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_AD0 - LPC_AD0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_AD1 - LPC_AD1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_AD2 - LPC_AD2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_AD3 - LPC_AD3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_CLKRUNB - LPC_CLKRUNB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* LPC_FRAMEB - LPC_FRAMEB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* ------- GPIO Group North ------- */ + + /* GPIO_38 - LPSS_UART0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* GPIO_39 - LPSS_UART0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), + + /* GPIO_42 - LPSS_UART1_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + + /* GPIO_43 - LPSS_UART1_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), +}; + +#endif /* CFG_GPIO_EARLY_H */ diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 833afae9df9..15e685b2110 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -29,7 +29,6 @@ config S3_VGA_ROM_RUN source "src/northbridge/amd/pi/00630F01/Kconfig" source "src/northbridge/amd/pi/00730F01/Kconfig" -source "src/northbridge/amd/pi/00660F01/Kconfig" config HW_MEM_HOLE_SIZEK hex diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index e4d8d66993c..f13133d6efb 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -33,3 +33,6 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index a0e8fc06312..2e41981e753 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -12,7 +12,7 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use + * true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 4d8a923c575..6854b73cf9f 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -218,9 +218,9 @@ enum { * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define HPLLVCO_MCHBAR 0x0c0f @@ -251,47 +251,47 @@ enum { #define DCC_SET_EREG (4 << DCC_CMD_SHIFT) #define DCC_SET_EREG_SHIFT 21 #define DCC_SET_EREG_MASK (DCC_CMD_MASK | (3 << DCC_SET_EREG_SHIFT)) -#define DCC_SET_EREGx(x) ((DCC_SET_EREG | \ - ((x - 1) << DCC_SET_EREG_SHIFT)) & \ +#define DCC_SET_EREGx(x) ((DCC_SET_EREG | \ + (((x) - 1) << DCC_SET_EREG_SHIFT)) & \ DCC_SET_EREG_MASK) /* Per channel DRAM Row Attribute registers (32-bit) */ -#define CxDRA_MCHBAR(x) (0x1208 + (x * 0x0100)) -#define CxDRA_PAGESIZE_SHIFT(r) (r * 4) /* Per rank r */ +#define CxDRA_MCHBAR(x) (0x1208 + ((x) * 0x0100)) +#define CxDRA_PAGESIZE_SHIFT(r) ((r) * 4) /* Per rank r */ #define CxDRA_PAGESIZE_MASKr(r) (0x7 << CxDRA_PAGESIZE_SHIFT(r)) #define CxDRA_PAGESIZE_MASK 0x0000ffff #define CxDRA_PAGESIZE(r, p) /* for log2(dimm page size in bytes) p */ \ - (((p - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r)) -#define CxDRA_BANKS_SHIFT(r) ((r * 3) + 16) + ((((p) - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r)) +#define CxDRA_BANKS_SHIFT(r) (((r) * 3) + 16) #define CxDRA_BANKS_MASKr(r) (0x3 << CxDRA_BANKS_SHIFT(r)) #define CxDRA_BANKS_MASK 0x07ff0000 #define CxDRA_BANKS(r, b) /* for number of banks b */ \ - ((b << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r)) + (((b) << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r)) /* * Per channel DRAM Row Boundary registers (32-bit) * Every two ranks share one register and must be programmed at the same time. * All registers (4 ranks per channel) have to be set. */ -#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r / 2) * 4)) -#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16) +#define CxDRBy_MCHBAR(x, r) (0x1200 + ((x) * 0x0100) + (((r) / 2) * 4)) +#define CxDRBy_BOUND_SHIFT(r) (((r) % 2) * 16) #define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r)) #define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \ - (((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r)) + ((((b) >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r)) -#define CxDRC0_MCHBAR(x) (0x1230 + (x * 0x0100)) +#define CxDRC0_MCHBAR(x) (0x1230 + ((x) * 0x0100)) #define CxDRC0_RANKEN0 (1 << 24) /* Rank Enable */ #define CxDRC0_RANKEN1 (1 << 25) #define CxDRC0_RANKEN2 (1 << 26) #define CxDRC0_RANKEN3 (1 << 27) -#define CxDRC0_RANKEN(r) (1 << (24 + r)) +#define CxDRC0_RANKEN(r) (1 << (24 + (r))) #define CxDRC0_RANKEN_MASK (0xf << 24) #define CxDRC0_RMS_SHIFT 8 /* Refresh Mode Select */ #define CxDRC0_RMS_MASK (7 << CxDRC0_RMS_SHIFT) #define CxDRC0_RMS_78US (2 << CxDRC0_RMS_SHIFT) #define CxDRC0_RMS_39US (3 << CxDRC0_RMS_SHIFT) -#define CxDRC1_MCHBAR(x) (0x1234 + (x * 0x0100)) +#define CxDRC1_MCHBAR(x) (0x1234 + ((x) * 0x0100)) #define CxDRC1_SSDS_SHIFT 24 #define CxDRC1_SSDS_MASK (0xff << CxDRC1_SSDS_SHIFT) #define CxDRC1_DS (0x91 << CxDRC1_SSDS_SHIFT) @@ -300,51 +300,51 @@ enum { #define CxDRC1_NOTPOP_MASK (0xf << 16) #define CxDRC1_MUSTWR (3 << 11) -#define CxDRC2_MCHBAR(x) (0x1238 + (x * 0x0100)) -#define CxDRC2_NOTPOP(r) (1 << (24 + r)) /* Write 1 for Not Populated */ +#define CxDRC2_MCHBAR(x) (0x1238 + ((x) * 0x0100)) +#define CxDRC2_NOTPOP(r) (1 << (24 + (r))) /* Write 1 for Not Populated */ #define CxDRC2_NOTPOP_MASK (0xf << 24) #define CxDRC2_MUSTWR (1 << 12) #define CxDRC2_CLK1067MT (1 << 0) /* DRAM Timing registers (32-bit each) */ -#define CxDRT0_MCHBAR(x) (0x1210 + (x * 0x0100)) +#define CxDRT0_MCHBAR(x) (0x1210 + ((x) * 0x0100)) #define CxDRT0_BtB_WtP_SHIFT 26 #define CxDRT0_BtB_WtP_MASK (0x1f << CxDRT0_BtB_WtP_SHIFT) #define CxDRT0_BtB_WtR_SHIFT 20 #define CxDRT0_BtB_WtR_MASK (0x1f << CxDRT0_BtB_WtR_SHIFT) -#define CxDRT1_MCHBAR(x) (0x1214 + (x * 0x0100)) -#define CxDRT2_MCHBAR(x) (0x1218 + (x * 0x0100)) -#define CxDRT3_MCHBAR(x) (0x121c + (x * 0x0100)) -#define CxDRT4_MCHBAR(x) (0x1220 + (x * 0x0100)) -#define CxDRT5_MCHBAR(x) (0x1224 + (x * 0x0100)) -#define CxDRT6_MCHBAR(x) (0x1228 + (x * 0x0100)) +#define CxDRT1_MCHBAR(x) (0x1214 + ((x) * 0x0100)) +#define CxDRT2_MCHBAR(x) (0x1218 + ((x) * 0x0100)) +#define CxDRT3_MCHBAR(x) (0x121c + ((x) * 0x0100)) +#define CxDRT4_MCHBAR(x) (0x1220 + ((x) * 0x0100)) +#define CxDRT5_MCHBAR(x) (0x1224 + ((x) * 0x0100)) +#define CxDRT6_MCHBAR(x) (0x1228 + ((x) * 0x0100)) /* Clock disable registers (32-bit each) */ -#define CxDCLKDIS_MCHBAR(x) (0x120c + (x * 0x0100)) +#define CxDCLKDIS_MCHBAR(x) (0x120c + ((x) * 0x0100)) #define CxDCLKDIS_MASK 3 #define CxDCLKDIS_ENABLE 3 /* Always enable both clock pairs. */ /* On-Die-Termination registers (2x 32-bit per channel) */ -#define CxODT_HIGH(x) (0x124c + (x * 0x0100)) -#define CxODT_LOW(x) (0x1248 + (x * 0x0100)) +#define CxODT_HIGH(x) (0x124c + ((x) * 0x0100)) +#define CxODT_LOW(x) (0x1248 + ((x) * 0x0100)) /* Write Training registers. */ -#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4)) +#define CxWRTy_MCHBAR(ch, s) (0x1470 + ((ch) * 0x0100) + ((3 - (s)) * 4)) -#define CxGTEW(x) (0x1270 + (x * 0x100)) -#define CxGTC(x) (0x1274 + (x * 0x100)) -#define CxDTPEW(x) (0x1278 + (x * 0x100)) -#define CxDTAEW(x) (0x1280 + (x * 0x100)) -#define CxDTC(x) (0x1288 + (x * 0x100)) +#define CxGTEW(x) (0x1270 + ((x) * 0x100)) +#define CxGTC(x) (0x1274 + ((x) * 0x100)) +#define CxDTPEW(x) (0x1278 + ((x) * 0x100)) +#define CxDTAEW(x) (0x1280 + ((x) * 0x100)) +#define CxDTC(x) (0x1288 + ((x) * 0x100)) /* * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -374,9 +374,9 @@ enum { * EPBAR */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCTL 0x00c /* 32bit */ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8c27d50eb6a..3458cbfefad 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -14,13 +14,6 @@ #include "chip.h" #include "gm45.h" -/* Reserve segments A and B: - * - * 0xa0000 - 0xbffff: legacy VGA - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 128; - int decode_pcie_bar(u32 *const base, u32 *const len) { *base = 0; @@ -133,10 +126,20 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); - /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (tomk - (legacy_hole_base_k + legacy_hole_size_k))); + /* Report lowest memory region */ + ram_resource(dev, 3, 0, 0xa0000 / KiB); + + /* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: Legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, 4, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); + reserved_ram_resource(dev, 5, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB); + + /* Report < 4GB memory */ + ram_resource(dev, 6, 1*MiB / KiB, tomk - 1*MiB / KiB); /* * If >= 4GB installed then memory from TOLUD to 4GB @@ -144,7 +147,7 @@ static void mch_domain_read_resources(struct device *dev) */ touud >>= 10; /* Convert to KB */ if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + ram_resource(dev, 7, 4096 * 1024, touud - (4096 * 1024)); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096); } @@ -152,12 +155,12 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); /* Don't use uma_resource() as our UMA touches the PCI hole. */ - fixed_mem_resource(dev, 6, tomk, uma_sizek, IORESOURCE_RESERVE); + fixed_mem_resource(dev, 8, tomk, uma_sizek, IORESOURCE_RESERVE); if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, 7, pcie_config_base >> 10, + fixed_mem_resource(dev, 9, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } } @@ -167,7 +170,7 @@ static void mch_domain_set_resources(struct device *dev) struct resource *resource; int i; - for (i = 3; i < 8; ++i) { + for (i = 3; i <= 9; ++i) { /* Report read resources. */ resource = probe_resource(dev, i); if (resource) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 28a33d842ce..a930afe875f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -204,3 +204,6 @@ Device (PDRC) /* PCI Express Graphics */ #include "peg.asl" #endif + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 73375d788de..99102b67707 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -3,7 +3,7 @@ #ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H #define NORTHBRIDGE_INTEL_HASWELL_CHIP_H -#include +#include /* * Digital Port Hotplug Enable: @@ -17,17 +17,8 @@ struct northbridge_intel_haswell_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ - u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ - u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ - - unsigned int gpu_pch_backlight_pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } gpu_pch_backlight_polarity; + /* IGD panel configuration */ + struct i915_gpu_panel_config panel_cfg; bool gpu_ddi_e_connected; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0bca230b643..21053ec1c04 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -243,6 +243,7 @@ static void init_display_planes(void) static void gma_setup_panel(struct device *dev) { struct northbridge_intel_haswell_config *conf = config_of(dev); + const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg; u32 reg32; /* Setup Digital Port Hotplug */ @@ -257,30 +258,30 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay) { + if (panel_cfg->cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); - reg32 &= ~0xff; - reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + reg32 &= ~0x1f; + reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } /* Enforce the PCH PWM function, as so does Linux. The CPU PWM controls are disabled after reset. */ - if (conf->gpu_pch_backlight_pwm_hz) { + if (panel_cfg->backlight_pwm_hz) { /* Reference clock is either 24MHz or 135MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ @@ -290,7 +291,7 @@ static void gma_setup_panel(struct device *dev) u32 south_chicken2; south_chicken2 = gtt_read(SOUTH_CHICKEN2); - if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + if (panel_cfg->backlight_pwm_hz > hz_limit) { pwm_increment = 16; south_chicken2 |= LPT_PWM_GRANULARITY; } else { @@ -299,7 +300,7 @@ static void gma_setup_panel(struct device *dev) } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz; printk(BIOS_INFO, "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", refclock / MHz, pwm_increment, pwm_period, @@ -309,7 +310,7 @@ static void gma_setup_panel(struct device *dev) gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); gtt_write(BLC_PWM_PCH_CTL1, - (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index ac3b1dbef00..0ff7b52074f 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -3,13 +3,9 @@ #ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ -/* Intel Enhanced Debug region */ -#define IED_SIZE CONFIG_IED_REGION_SIZE - -/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_MCHBAR 0xfed10000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 97ae433412b..a61036aca37 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -34,6 +34,31 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define SSKPD 0x5d10 /* 64-bit scratchpad register */ + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 + +/* Errors are returned back in bits 7:0 */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 + #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index cdc77b5fa7a..c2142cc50a7 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -77,4 +77,5 @@ Device (PDRC) #include "peg.asl" // Integrated graphics 0:2.0 +#include #include "igd.asl" diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 5258c526723..4fc2da25582 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (GFX0) +Scope (GFX0) { - Name (_ADR, 0x00020000) - Name (BRIG, Package (0x12) { 0xf, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index cfa527f4cc2..d2256729e95 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -74,7 +74,7 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_DEBUG, "IGD decoded, subtracting "); int uma_size = decode_igd_memory_size((reg16 >> 4) & 7); - printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); + printk(BIOS_DEBUG, "%dM UMA\n", uma_size / KiB); tomk_stolen -= uma_size; /* For reserving UMA memory in the memory map */ @@ -85,15 +85,15 @@ static void mch_domain_read_resources(struct device *dev) (unsigned int)uma_memory_base); } - tseg_sizek = decode_tseg_size(pci_read_config8(d0f0, ESMRAMC)) >> 10; - printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); + tseg_sizek = decode_tseg_size(pci_read_config8(d0f0, ESMRAMC)) / KiB; + printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek / KiB); tomk_stolen -= tseg_sizek; tseg_memory_base = tomk_stolen * 1024ULL; tseg_memory_size = tseg_sizek * 1024ULL; /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = ((uint32_t)cbmem_top() >> 10); + cbmem_topk = ((uint32_t)cbmem_top() / KiB); delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem; @@ -103,16 +103,18 @@ static void mch_domain_read_resources(struct device *dev) * number is always 0 */ printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk_stolen); - printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen >> 10)); + printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen / KiB)); /* Report the memory regions */ - ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, (tomk - 768)); - uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); - mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + ram_resource(dev, 3, 0, 0xa0000 / KiB); + ram_resource(dev, 4, 1 * MiB / KiB, (tomk - 1 * MiB / KiB)); + uma_resource(dev, 5, uma_memory_base / KiB, uma_memory_size / KiB); + mmio_resource(dev, 6, tseg_memory_base / KiB, tseg_memory_size / KiB); uma_resource(dev, 7, cbmem_topk, delta_cbmem); /* legacy VGA memory */ - mmio_resource(dev, 8, 640, 768 - 640); + mmio_resource(dev, 8, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); + /* RAM to be used for option roms and BIOS */ + reserved_ram_resource(dev, 9, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB); } static void mch_domain_set_resources(struct device *dev) diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 3cf597daf70..a6e32da3819 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -19,15 +19,6 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH - -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - - /* Required for SandyBridge sighting 3715511 */ - Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) - Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) }) // Current Resource Settings @@ -36,3 +27,6 @@ Device (PDRC) Return(PDRS) } } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 68dcf7d13fe..9dc38ec3d41 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -9,6 +9,7 @@ #include #include #include "chip.h" +#include #include "ironlake.h" #include @@ -52,15 +53,8 @@ static void add_fixed_resources(struct device *dev, int index) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); - - reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); - -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB); } #if CONFIG(HAVE_ACPI_TABLES) @@ -110,10 +104,10 @@ static void mc_read_resources(struct device *dev) printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); /* Report the memory regions */ - ram_resource(dev, index++, 0, 640); - ram_resource(dev, index++, 768, ((tseg_base >> 10) - 768)); + ram_resource(dev, index++, 0, 0xa0000 / KiB); + ram_resource(dev, index++, 1 * MiB / KiB, (tseg_base - 1 * MiB) / KiB); - mmio_resource(dev, index++, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); + mmio_resource(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB); reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); const int uma_sizes_gtt[16] = @@ -135,17 +129,17 @@ static void mc_read_resources(struct device *dev) if (gtt_base > tseg_end) { /* Reserve the gap. MMIO doesn't work in this range. Keep it uncacheable, though, for easier MTRR allocation. */ - mmio_resource(dev, index++, tseg_end >> 10, (gtt_base - tseg_end) >> 10); + mmio_resource(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB); } - mmio_resource(dev, index++, gtt_base >> 10, uma_size_gtt << 10); - mmio_resource(dev, index++, igd_base >> 10, uma_size_igd << 10); + mmio_resource(dev, index++, gtt_base / KiB, uma_size_gtt * KiB); + mmio_resource(dev, index++, igd_base / KiB, uma_size_igd * KiB); if (touud > 4096) - ram_resource(dev, index++, (4096 << 10), ((touud - 4096) << 10)); + ram_resource(dev, index++, (4096 * KiB), ((touud - 4096) * KiB)); /* This memory is not DMA-capable. */ if (touud >= 8192 - 64) - bad_ram_resource(dev, index++, 0x1fc000000ULL >> 10, 0x004000000 >> 10); + bad_ram_resource(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB); add_fixed_resources(dev, index); } diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index beb22445fef..1a66e1cf5fc 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -490,11 +490,11 @@ static void set_334(int zero) ; } -static void rmw_1d0(u16 addr, u32 and, u32 or, int split, int flag) +static void rmw_1d0(u16 addr, u32 and, u32 or, int split) { u32 v; v = read_1d0(addr, split); - write_1d0((v & and) | or, addr, split, flag); + write_1d0((v & and) | or, addr, split, 1); } static int find_highest_bit_set(u16 val) @@ -1207,7 +1207,7 @@ static void program_board_delay(struct raminfo *info) if (info->revision >= 0x10 && info->clock_speed_index <= 1 && (info->silicon_revision == 2 || info->silicon_revision == 3)) - rmw_1d0(0x116, 5, 2, 4, 1); + rmw_1d0(0x116, 5, 2, 4); } MCHBAR32(0x120) = (1 << (info->max_slots_used_in_channel + 28)) | 0x188e7f9f; @@ -1480,10 +1480,14 @@ static void collect_system_info(struct raminfo *info) info->memory_reserved_for_heci_mb = intel_early_me_uma_size(); } - for (i = 0; i < 3; i++) - gav(capid0[i] = - pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2))); - gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); + for (i = 0; i < 3; i++) { + capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2)); + printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]); + } + info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID); + printk(BIOS_DEBUG, "Revision ID: 0x%x\n", info->revision); + printk(BIOS_DEBUG, "Device ID: 0x%x\n", pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID)); + info->max_supported_clock_speed_index = (~capid0[1] & 7); if ((capid0[1] >> 11) & 1) @@ -4248,7 +4252,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) write_500(&info, 1, 1, 0x6b3, 4, 1); write_500(&info, 1, 1, 0x6cf, 4, 1); - rmw_1d0(0x21c, 0x38, 0, 6, 1); + rmw_1d0(0x21c, 0x38, 0, 6); write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info. populated_ranks[0] @@ -4357,22 +4361,20 @@ void raminit(const int s3resume, const u8 *spd_addrmap) val_a1 = read_1d0(0xa1, 6); // = 0x1cf4040 // !!!! t = read_1d0(0x2f3, 6); // = 0x10a4040 // !!!! rmw_1d0(0x320, 0x07, - (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6, 1); + (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6); rmw_1d0(0x14b, 0x78, ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & - 4), 7, - 1); + 4), 7); rmw_1d0(0xce, 0x38, ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & - 4), 6, - 1); + 4), 6); } for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 1); - rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!! + rmw_1d0(0x116, 0xe, 1, 4); // = 0x4040432 // !!!! MCHBAR32(0x144); // !!!! write_1d0(2, 0xae, 6, 1); write_1d0(2, 0x300, 6, 1); @@ -4708,7 +4710,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) if (s3resume && cbmem_wasnot_inited) { u32 reg32; printk(BIOS_ERR, "Failed S3 resume.\n"); - ram_check(0x100000, 0x200000); + ram_check_nodie(1 * MiB); /* Clear SLP_TYPE. */ reg32 = inl(DEFAULT_PMBASE + 0x04); diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 9515c317a9b..5fb2b1233e6 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -32,3 +32,6 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index e98c16bd923..0b31766dc5d 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -65,39 +66,39 @@ static void mch_domain_read_resources(struct device *dev) printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", touud, tolud, tom); - tomk = tolud >> 10; + tomk = tolud / KiB; /* Graphics memory */ const u16 ggc = pci_read_config16(mch, GGC); const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); - printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + printk(BIOS_DEBUG, "%uM UMA", gms_sizek / KiB); tomk -= gms_sizek; /* GTT Graphics Stolen Memory Size (GGMS) */ const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); - printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek / KiB); tomk -= gsm_sizek; - const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10; - const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10; - const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10; + const u32 tseg_basek = pci_read_config32(mch, TSEG) / KiB; + const u32 igd_basek = pci_read_config32(mch, GBSM) / KiB; + const u32 gtt_basek = pci_read_config32(mch, BGSM) / KiB; /* Subtract TSEG size */ tseg_sizek = gtt_basek - tseg_basek; tomk -= tseg_sizek; - printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); + printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek / KiB); /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = (uint32_t)cbmem_top() >> 10; + cbmem_topk = (uint32_t)cbmem_top() / KiB; delta_cbmem = tomk - cbmem_topk; tomk -= delta_cbmem; printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", delta_cbmem); /* Report the memory regions */ - ram_resource(dev, index++, 0, 640); - ram_resource(dev, index++, 768, tomk - 768); + ram_resource(dev, index++, 0, 0xa0000 / KiB); + ram_resource(dev, index++, 1 * MiB / KiB, tomk - 1 * MiB / KiB); mmio_resource(dev, index++, tseg_basek, tseg_sizek); mmio_resource(dev, index++, gtt_basek, gsm_sizek); mmio_resource(dev, index++, igd_basek, gms_sizek); @@ -111,15 +112,15 @@ static void mch_domain_read_resources(struct device *dev) if (touud > top32memk) { ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud - top32memk) >> 10); + (touud - top32memk) / KiB); } if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, index++, pcie_config_base >> 10, - pcie_config_size >> 10, IORESOURCE_RESERVE); + fixed_mem_resource(dev, index++, pcie_config_base / KiB, + pcie_config_size / KiB, IORESOURCE_RESERVE); } add_fixed_resources(dev, index); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 2248d03c899..dd728e8a47e 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "pineview.h" #include "raminit.h" #include @@ -529,20 +530,6 @@ static void sdram_detect_ram_speed(struct sysinfo *s) } } -#define HPET_BASE 0xfed00000 -#define HPET32(x) *((volatile u32 *)(HPET_BASE + x)) -static void enable_hpet(void) -{ - u32 reg32; - reg32 = RCBA32(HPTC); - reg32 &= ~0x03; - reg32 |= (1 << 7); - RCBA32(HPTC) = reg32; - /* On NM10 this only works if read back */ - RCBA32(HPTC); - HPET32(0x10) = HPET32(0x10) | 1; -} - static void sdram_clk_crossing(struct sysinfo *s) { u8 ddr_freq, fsb_freq; @@ -1595,27 +1582,6 @@ static void sdram_mmap(struct sysinfo *s) pci_write_config32(HOST_BRIDGE, 0xac, tsegmb[s->dimm_config[0]]); } -static void hpet_udelay(u32 del) -{ - u32 start, finish, now; - - del *= 15; /* now in usec */ - - start = HPET32(0xf0); - finish = start + del; - while (1) { - now = HPET32(0xf0); - if (finish > start) { - if (now >= finish) - break; - } else { - if ((now < start) && (now >= finish)) { - break; - } - } - } -} - static u8 sdram_checkrcompoverride(void) { u32 xcomp; diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 9cd522f85b9..1388b8770d8 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -64,6 +64,19 @@ config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS Disabled by default as it might cause system instability. Handle with care! +config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE + bool "Ignore XMP profile requested voltage" + default n + depends on USE_NATIVE_RAMINIT + help + Native raminit only supports 1.5V operation, but there are DIMMs + which request 1.65V operation in XMP profiles. This option allows + raminit to use these XMP profiles anyway, instead of falling back + to non-XMP settings. + Disabled by default because it allows forcing memory to run out of + specification. Consider this to be an overclocking option. + Handle with care! + config CBFS_SIZE hex default 0x100000 diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 728d8e3ff52..1e47c1f21bd 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -52,3 +52,6 @@ Device (PDRC) Return(PDRS) } } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index dad61f9ee8f..bea85f4f8ec 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -10,7 +10,7 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all + * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index bcf3e4ce4df..6f17cc16878 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -1,13 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include -void early_init_dmi(void) +static void dmi_recipe(void) { + const u32 cpuid = cpu_get_cpuid(); + int i; + /* The DMI recipe is only needed on Ivy Bridge */ + if (!IS_IVY_CPU(cpuid)) + return; + for (i = 0; i < 2; i++) { DMIBAR32(0x0914 + (i << 5)) |= (1 << 31); } @@ -158,6 +166,11 @@ void early_init_dmi(void) DMIBAR32(DMIL0SLAT); // !!! = 0x00c26460 DMIBAR32(DMIL0SLAT) = 0x00c2403c; +} + +void early_init_dmi(void) +{ + dmi_recipe(); early_pch_init_native_dmi_pre(); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4d87878fa24..dc1be32ee16 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -256,17 +256,15 @@ static void northbridge_dmi_init(struct device *dev) { const bool is_sandy = is_sandybridge(); - u32 reg32; + const u8 stepping = cpu_stepping(); - /* Clear error status bits */ - DMIBAR32(DMIUESTS) = 0xffffffff; - DMIBAR32(DMICESTS) = 0xffffffff; + u32 reg32; /* Steps prior to DMI ASPM */ if (is_sandy) { reg32 = DMIBAR32(0x250); - reg32 &= ~((1 << 22) | (1 << 20)); - reg32 |= (1 << 21); + reg32 &= ~(7 << 20); + reg32 |= (2 << 20); DMIBAR32(0x250) = reg32; } @@ -274,12 +272,14 @@ static void northbridge_dmi_init(struct device *dev) reg32 |= (1 << 29); DMIBAR32(DMILLTC) = reg32; - if (!is_sandy || cpu_stepping() >= SNB_STEP_D0) { - reg32 = DMIBAR32(0x1f8); - reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; + if (is_sandy && stepping == SNB_STEP_C0) { + reg32 = DMIBAR32(0xbc8); + reg32 &= ~(0xfff << 7); + reg32 |= (0x7d3 << 7); + DMIBAR32(0xbc8) = reg32; + } - } else if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) { + if (!is_sandy || stepping >= SNB_STEP_D1) { reg32 = DMIBAR32(0x1f8); reg32 &= ~(1 << 26); reg32 |= (1 << 16); @@ -288,8 +288,20 @@ static void northbridge_dmi_init(struct device *dev) reg32 = DMIBAR32(0x1fc); reg32 |= (1 << 12) | (1 << 23); DMIBAR32(0x1fc) = reg32; + + } else if (stepping >= SNB_STEP_D0) { + reg32 = DMIBAR32(0x1f8); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; } + /* Clear error status bits */ + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; + + if (!is_sandy) + DMIBAR32(0xc34) = 0xffffffff; + /* Enable ASPM on SNB link, should happen before PCH link */ if (is_sandy) { reg32 = DMIBAR32(0xd04); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 319fea3a5d8..1d4354c83d3 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -153,7 +153,6 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) int dimms = 0, ch_dimms; int channel, slot, spd_slot; bool can_use_ecc = ctrl->ecc_supported; - dimm_info *dimm = &ctrl->info; memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); @@ -176,70 +175,74 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) spd_slot = 2 * channel + slot; printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); + dimm_attr *const dimm = &ctrl->info.dimm[channel][slot]; + /* Search for XMP profile */ - spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot], + spd_xmp_decode_ddr3(dimm, spd[spd_slot], DDR3_XMP_PROFILE_1); - if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { + if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { printram("No valid XMP profile found.\n"); - spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); + spd_decode_ddr3(dimm, spd[spd_slot]); - } else if (ch_dimms > dimm->dimm[channel][slot].dimms_per_channel) { + } else if (ch_dimms > dimm->dimms_per_channel) { printram( "XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", - dimm->dimm[channel][slot].dimms_per_channel, ch_dimms); + dimm->dimms_per_channel, ch_dimms); if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); else - spd_decode_ddr3(&dimm->dimm[channel][slot], - spd[spd_slot]); + spd_decode_ddr3(dimm, spd[spd_slot]); - } else if (dimm->dimm[channel][slot].voltage != 1500) { + } else if (dimm->voltage != 1500) { /* TODO: Support DDR3 voltages other than 1500mV */ printram("XMP profile's requested %u mV is unsupported.\n", - dimm->dimm[channel][slot].voltage); - spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); + dimm->voltage); + + if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE)) + printk(BIOS_WARNING, + "XMP requested voltage will be ignored.\n"); + else + spd_decode_ddr3(dimm, spd[spd_slot]); } /* Fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); - if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { + if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { /* Mark DIMM as invalid */ - dimm->dimm[channel][slot].ranks = 0; - dimm->dimm[channel][slot].size_mb = 0; + dimm->ranks = 0; + dimm->size_mb = 0; continue; } - dram_print_spd_ddr3(&dimm->dimm[channel][slot]); + dram_print_spd_ddr3(dimm); dimms++; ctrl->rank_mirror[channel][slot * 2] = 0; - ctrl->rank_mirror[channel][slot * 2 + 1] = - dimm->dimm[channel][slot].flags.pins_mirrored; + ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->flags.pins_mirrored; - ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; + ctrl->channel_size_mb[channel] += dimm->size_mb; - if (!dimm->dimm[channel][slot].flags.is_ecc) + if (!dimm->flags.is_ecc) can_use_ecc = false; - ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; + ctrl->auto_self_refresh &= dimm->flags.asr; - ctrl->extended_temperature_range &= - dimm->dimm[channel][slot].flags.ext_temp_refresh; + ctrl->extended_temperature_range &= dimm->flags.ext_temp_refresh; - ctrl->rankmap[channel] |= - ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); + ctrl->rankmap[channel] |= ((1 << dimm->ranks) - 1) << (2 * slot); printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, ctrl->rankmap[channel]); } - if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c) - && dimm->dimm[channel][0].reference_card <= 5 - && dimm->dimm[channel][1].reference_card <= 5) { + const u8 rc_0 = ctrl->info.dimm[channel][0].reference_card; + const u8 rc_1 = ctrl->info.dimm[channel][1].reference_card; + + if (ch_dimms == NUM_SLOTS && rc_0 < 6 && rc_1 < 6) { const int ref_card_offset_table[6][6] = { { 0, 0, 0, 0, 2, 2 }, { 0, 0, 0, 0, 2, 2 }, @@ -248,9 +251,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { 2, 2, 2, 1, 0, 0 }, { 2, 2, 2, 1, 0, 0 }, }; - ctrl->ref_card_offset[channel] = ref_card_offset_table - [dimm->dimm[channel][0].reference_card] - [dimm->dimm[channel][1].reference_card]; + ctrl->ref_card_offset[channel] = ref_card_offset_table[rc_0][rc_1]; } else { ctrl->ref_card_offset[channel] = 0; } @@ -308,7 +309,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) wait_txt_clear(); - wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); + wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 }); const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7252574ad6c..cef01316dca 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,7 @@ static u32 get_XOVER_CMD(u8 rankmap) u32 reg; /* Enable xover cmd */ - reg = 0x4000; + reg = 1 << 14; /* Enable xover ctl */ if (rankmap & 0x03) @@ -429,7 +430,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; touudbase = remaplimit + 1; } else { - // Reclaim not possible + /* Reclaim not possible */ reclaim = 0; touudbase = tom - me_uma_size; } @@ -546,11 +547,7 @@ static void write_reset(ramctr_timing *ctrl) iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); - /* - * Execute command queue - why is bit 22 set here?! - * - * This is actually using the IOSAV state machine as a timer, so refresh is allowed. - */ + /* This is actually using the IOSAV state machine as a timer */ iosav_run_queue(channel, 1, 1); wait_for_iosav(channel); @@ -684,8 +681,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); } /* Obtain optimal power down mode for current configuration */ @@ -756,11 +752,11 @@ static u32 encode_odt(u32 odt) { switch (odt) { case 30: - return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 + return (1 << 9) | (1 << 2); /* RZQ/8, RZQ/4 */ case 60: - return (1 << 2); // RZQ/4 + return (1 << 2); /* RZQ/4 */ case 120: - return (1 << 6); // RZQ/2 + return (1 << 6); /* RZQ/2 */ default: case 0: return 0; @@ -882,7 +878,7 @@ void dram_mrscommands(ramctr_timing *ctrl) .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = 0, @@ -895,11 +891,9 @@ void dram_mrscommands(ramctr_timing *ctrl) }; iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence)); - /* Execute command queue on all channels. Do it four times. */ iosav_run_queue(BROADCAST_CH, 4, 0); FOR_ALL_CHANNELS { - /* Wait for ref drained */ wait_for_iosav(channel); } @@ -913,16 +907,11 @@ void dram_mrscommands(ramctr_timing *ctrl) slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - /* Drain */ wait_for_iosav(channel); iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); - /* Execute command queue */ - iosav_run_once(channel); - - /* Drain */ - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } } @@ -932,6 +921,9 @@ static const u32 lane_base[] = { LANEBASE_ECC }; +/* Maximum delay for command, control, clock */ +#define CCC_MAX_PI (2 * QCLK_PI - 1) + void program_timings(ramctr_timing *ctrl, int channel) { u32 reg_roundtrip_latency, reg_io_latency; @@ -946,71 +938,73 @@ void program_timings(ramctr_timing *ctrl, int channel) u32 clk_logic_dly = 0; /* - * Apply command delay if desired setting is negative. Find the - * most negative value: 'cmd_delay' will be the absolute value. + * Compute command timing as abs() of the most negative PI code + * across all ranks. Use zero if none of the values is negative. */ FOR_ALL_POPULATED_RANKS { - if (cmd_delay < -ctrl->timings[channel][slotrank].pi_coding) - cmd_delay = -ctrl->timings[channel][slotrank].pi_coding; - } - if (cmd_delay < 0) { - printk(BIOS_ERR, "C%d command delay underflow: %d\n", channel, cmd_delay); - cmd_delay = 0; + cmd_delay = MAX(cmd_delay, -ctrl->timings[channel][slotrank].pi_coding); } - if (cmd_delay >= 128) { + if (cmd_delay > CCC_MAX_PI) { printk(BIOS_ERR, "C%d command delay overflow: %d\n", channel, cmd_delay); - cmd_delay = 127; + cmd_delay = CCC_MAX_PI; } - /* Apply control and clock delay if desired setting is positive */ - if (cmd_delay == 0) { - for (slot = 0; slot < NUM_SLOTS; slot++) { - const int pi_coding_0 = ctrl->timings[channel][2 * slot + 0].pi_coding; - const int pi_coding_1 = ctrl->timings[channel][2 * slot + 1].pi_coding; + for (slot = 0; slot < NUM_SLOTS; slot++) { + const int pi_coding_0 = ctrl->timings[channel][2 * slot + 0].pi_coding; + const int pi_coding_1 = ctrl->timings[channel][2 * slot + 1].pi_coding; - const u8 slot_map = (ctrl->rankmap[channel] >> (2 * slot)) & 3; + const u8 slot_map = (ctrl->rankmap[channel] >> (2 * slot)) & 3; - if (slot_map & 1) - ctl_delay[slot] += pi_coding_0 + cmd_delay; + if (slot_map & 1) + ctl_delay[slot] += pi_coding_0 + cmd_delay; - if (slot_map & 2) - ctl_delay[slot] += pi_coding_1 + cmd_delay; + if (slot_map & 2) + ctl_delay[slot] += pi_coding_1 + cmd_delay; - /* If both ranks in a slot are populated, use the average */ - if (slot_map == 3) - ctl_delay[slot] /= 2; + /* If both ranks in a slot are populated, use the average */ + if (slot_map == 3) + ctl_delay[slot] /= 2; - if (ctl_delay[slot] >= 128) { - printk(BIOS_ERR, "C%dS%d control delay overflow: %d\n", - channel, slot, ctl_delay[slot]); - ctl_delay[slot] = 127; - } + if (ctl_delay[slot] > CCC_MAX_PI) { + printk(BIOS_ERR, "C%dS%d control delay overflow: %d\n", + channel, slot, ctl_delay[slot]); + ctl_delay[slot] = CCC_MAX_PI; } - FOR_ALL_POPULATED_RANKS { - u32 clk_delay = ctrl->timings[channel][slotrank].pi_coding + cmd_delay; + } + FOR_ALL_POPULATED_RANKS { + int clk_delay = ctrl->timings[channel][slotrank].pi_coding + cmd_delay; - if (clk_delay >= 128) { - printk(BIOS_ERR, "C%dR%d clock delay overflow: %d\n", - channel, slotrank, clk_delay); - clk_delay = 127; - } + /* + * Clock is a differential signal, whereas command and control are not. + * This affects its timing, and it is also why it needs a magic offset. + */ + clk_delay += ctrl->pi_code_offset; - clk_pi_coding |= (clk_delay % 64) << (6 * slotrank); - clk_logic_dly |= (clk_delay / 64) << slotrank; + /* Can never happen with valid values */ + if (clk_delay < 0) { + printk(BIOS_ERR, "C%dR%d clock delay underflow: %d\n", + channel, slotrank, clk_delay); + clk_delay = 0; } + + /* Clock can safely wrap around because it is a periodic signal */ + clk_delay %= CCC_MAX_PI + 1; + + clk_pi_coding |= (clk_delay % QCLK_PI) << (6 * slotrank); + clk_logic_dly |= (clk_delay / QCLK_PI) << slotrank; } /* Enable CMD XOVER */ union gdcr_cmd_pi_coding_reg cmd_pi_coding = { .raw = get_XOVER_CMD(ctrl->rankmap[channel]), }; - cmd_pi_coding.cmd_pi_code = cmd_delay % 64; - cmd_pi_coding.cmd_logic_delay = cmd_delay / 64; + cmd_pi_coding.cmd_pi_code = cmd_delay % QCLK_PI; + cmd_pi_coding.cmd_logic_delay = cmd_delay / QCLK_PI; - cmd_pi_coding.ctl_pi_code_d0 = ctl_delay[0] % 64; - cmd_pi_coding.ctl_pi_code_d1 = ctl_delay[1] % 64; - cmd_pi_coding.ctl_logic_delay_d0 = ctl_delay[0] / 64; - cmd_pi_coding.ctl_logic_delay_d1 = ctl_delay[1] / 64; + cmd_pi_coding.ctl_pi_code_d0 = ctl_delay[0] % QCLK_PI; + cmd_pi_coding.ctl_pi_code_d1 = ctl_delay[1] % QCLK_PI; + cmd_pi_coding.ctl_logic_delay_d0 = ctl_delay[0] / QCLK_PI; + cmd_pi_coding.ctl_logic_delay_d1 = ctl_delay[1] / QCLK_PI; MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; @@ -1023,95 +1017,54 @@ void program_timings(ramctr_timing *ctrl, int channel) reg_roundtrip_latency = 0; FOR_ALL_POPULATED_RANKS { - int post_timA_min_high = 7, pre_timA_min_high = 7; - int post_timA_max_high = 0, pre_timA_max_high = 0; - int shift_402x = 0; - int shift = ctrl->timings[channel][slotrank].pi_coding + cmd_delay; - - if (shift < 0) - shift = 0; - - FOR_ALL_LANES { - post_timA_min_high = MIN(post_timA_min_high, - (ctrl->timings[channel][slotrank].lanes[lane]. - timA + shift) >> 6); - pre_timA_min_high = MIN(pre_timA_min_high, - ctrl->timings[channel][slotrank].lanes[lane]. - timA >> 6); - post_timA_max_high = MAX(post_timA_max_high, - (ctrl->timings[channel][slotrank].lanes[lane]. - timA + shift) >> 6); - pre_timA_max_high = MAX(pre_timA_max_high, - ctrl->timings[channel][slotrank].lanes[lane]. - timA >> 6); - } - - if (pre_timA_max_high - pre_timA_min_high < - post_timA_max_high - post_timA_min_high) - shift_402x = +1; - - else if (pre_timA_max_high - pre_timA_min_high > - post_timA_max_high - post_timA_min_high) - shift_402x = -1; - - reg_io_latency |= - (ctrl->timings[channel][slotrank].io_latency + shift_402x - - post_timA_min_high) << (4 * slotrank); + reg_io_latency |= ctrl->timings[channel][slotrank].io_latency << (4 * slotrank); reg_roundtrip_latency |= - (ctrl->timings[channel][slotrank].roundtrip_latency + - shift_402x) << (8 * slotrank); + ctrl->timings[channel][slotrank].roundtrip_latency << (8 * slotrank); FOR_ALL_LANES { - MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = - (((ctrl->timings[channel][slotrank].lanes[lane]. - timA + shift) & 0x3f) - | - ((ctrl->timings[channel][slotrank].lanes[lane]. - rising + shift) << 8) - | - (((ctrl->timings[channel][slotrank].lanes[lane]. - timA + shift - - (post_timA_min_high << 6)) & 0x1c0) << 10) - | ((ctrl->timings[channel][slotrank].lanes[lane]. - falling + shift) << 20)); - - MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = - (((ctrl->timings[channel][slotrank].lanes[lane]. - timC + shift) & 0x3f) - | - (((ctrl->timings[channel][slotrank].lanes[lane]. - timB + shift) & 0x3f) << 8) - | - (((ctrl->timings[channel][slotrank].lanes[lane]. - timB + shift) & 0x1c0) << 9) - | - (((ctrl->timings[channel][slotrank].lanes[lane]. - timC + shift) & 0x40) << 13)); + const u16 rcven = ctrl->timings[channel][slotrank].lanes[lane].rcven; + const u8 dqs_p = ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p; + const u8 dqs_n = ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n; + const union gdcr_rx_reg gdcr_rx = { + .rcven_pi_code = rcven % QCLK_PI, + .rx_dqs_p_pi_code = dqs_p, + .rcven_logic_delay = rcven / QCLK_PI, + .rx_dqs_n_pi_code = dqs_n, + }; + MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = gdcr_rx.raw; + + const u16 tx_dqs = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; + const int tx_dq = ctrl->timings[channel][slotrank].lanes[lane].tx_dq; + const union gdcr_tx_reg gdcr_tx = { + .tx_dq_pi_code = tx_dq % QCLK_PI, + .tx_dqs_pi_code = tx_dqs % QCLK_PI, + .tx_dqs_logic_delay = tx_dqs / QCLK_PI, + .tx_dq_logic_delay = tx_dq / QCLK_PI, + }; + MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = gdcr_tx.raw; } } MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; } -static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) +static void test_rcven(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); + /* Send a burst of 16 back-to-back read commands (4 DCLK apart) */ iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) { - u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; + u32 rcven = ctrl->timings[channel][slotrank].lanes[lane].rcven; return (MCHBAR32(lane_base[lane] + - GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; + GDCRTRAININGRESULT(channel, (rcven / 32) & 1)) >> (rcven % 32)) & 1; } struct run { @@ -1155,56 +1108,57 @@ static struct run get_longest_zero_run(int *seq, int sz) return ret; } +#define RCVEN_COARSE_PI_LENGTH (2 * QCLK_PI) + static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { - int timA; - int statistics[NUM_LANES][128]; + int rcven; + int statistics[NUM_LANES][RCVEN_COARSE_PI_LENGTH]; int lane; - for (timA = 0; timA < 128; timA++) { + for (rcven = 0; rcven < RCVEN_COARSE_PI_LENGTH; rcven++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA = timA; + ctrl->timings[channel][slotrank].lanes[lane].rcven = rcven; } program_timings(ctrl, channel); - test_timA(ctrl, channel, slotrank); + test_rcven(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); + statistics[lane][rcven] = + !does_lane_work(ctrl, channel, slotrank, lane); } } FOR_ALL_LANES { - struct run rn = get_longest_zero_run(statistics[lane], 128); - ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; + struct run rn = get_longest_zero_run(statistics[lane], RCVEN_COARSE_PI_LENGTH); + ctrl->timings[channel][slotrank].lanes[lane].rcven = rn.middle; upperA[lane] = rn.end; if (upperA[lane] < rn.middle) - upperA[lane] += 128; + upperA[lane] += 2 * QCLK_PI; - printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + printram("rcven: %d, %d, %d: % 4d-% 4d-% 4d\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } } static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { - int timA_delta; - int statistics[NUM_LANES][51]; + int rcven_delta; + int statistics[NUM_LANES][51] = {0}; int lane, i; - memset(statistics, 0, sizeof(statistics)); - - for (timA_delta = -25; timA_delta <= 25; timA_delta++) { + for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA - = upperA[lane] + timA_delta + 0x40; + ctrl->timings[channel][slotrank].lanes[lane].rcven + = upperA[lane] + rcven_delta + QCLK_PI; } program_timings(ctrl, channel); for (i = 0; i < 100; i++) { - test_timA(ctrl, channel, slotrank); + test_rcven(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timA_delta + 25] += + statistics[lane][rcven_delta + 25] += does_lane_work(ctrl, channel, slotrank, lane); } } @@ -1223,14 +1177,20 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i printram("lane %d: %d, %d\n", lane, last_zero, first_all); - ctrl->timings[channel][slotrank].lanes[lane].timA = + ctrl->timings[channel][slotrank].lanes[lane].rcven = (last_zero + first_all) / 2 + upperA[lane]; - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: % 4d\n", channel, slotrank, + lane, ctrl->timings[channel][slotrank].lanes[lane].rcven); } } +/* + * Once the DQS high phase has been found (for each DRAM) the next stage + * is to find out the round trip latency, by locating the preamble cycle. + * This is achieved by trying smaller and smaller roundtrip values until + * the strobe sampling is done on the preamble cycle. + */ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; @@ -1240,7 +1200,7 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank int all_works = 1, some_works = 0; program_timings(ctrl, channel); - test_timA(ctrl, channel, slotrank); + test_rcven(ctrl, channel, slotrank); FOR_ALL_LANES { works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); @@ -1250,12 +1210,19 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank else all_works = 0; } + + /* If every lane is working, exit */ if (all_works) return 0; + /* + * If all bits are one (everyone is failing), decrement + * the roundtrip value by two, and do another iteration. + */ if (!some_works) { + /* Guard against roundtrip latency underflow */ if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { - printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", + printk(BIOS_EMERG, "Roundtrip latency underflow: %d, %d\n", channel, slotrank); return MAKE_ERR; } @@ -1263,17 +1230,24 @@ static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank printram("4024 -= 2;\n"); continue; } + + /* + * Else (if some lanes are failing), increase the rank's + * I/O latency by 2, and increase rcven logic delay by 2 + * on the working lanes, then perform another iteration. + */ ctrl->timings[channel][slotrank].io_latency += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { - printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", + /* Guard against I/O latency overflow */ + if (ctrl->timings[channel][slotrank].io_latency >= 16) { + printk(BIOS_EMERG, "I/O latency overflow: %d, %d\n", channel, slotrank); return MAKE_ERR; } FOR_ALL_LANES if (works[lane]) { - ctrl->timings[channel][slotrank].lanes[lane].timA += 128; - upperA[lane] += 128; + ctrl->timings[channel][slotrank].lanes[lane].rcven += 2 * QCLK_PI; + upperA[lane] += 2 * QCLK_PI; printram("increment %d, %d, %d\n", channel, slotrank, lane); } } @@ -1287,7 +1261,7 @@ static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int slotrank) u16 logic_delay_max = 0; FOR_ALL_LANES { - const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].rcven >> 6; logic_delay_min = MIN(logic_delay_min, logic_delay); logic_delay_max = MAX(logic_delay_max, logic_delay); @@ -1333,7 +1307,7 @@ static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slot int lane; FOR_ALL_LANES { - const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].rcven >> 6; logic_delay_min = MIN(logic_delay_min, logic_delay); } @@ -1344,7 +1318,7 @@ static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slot } FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= logic_delay_min << 6; + ctrl->timings[channel][slotrank].lanes[lane].rcven -= logic_delay_min << 6; } ctrl->timings[channel][slotrank].io_latency -= logic_delay_min; printram("4028 -= %d;\n", logic_delay_min); @@ -1364,8 +1338,7 @@ int receive_enable_calibration(ramctr_timing *ctrl) iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); const union gdcr_training_mod_reg training_mod = { .receive_enable_mode = 1, @@ -1383,7 +1356,7 @@ int receive_enable_calibration(ramctr_timing *ctrl) all_high = 1; some_high = 0; FOR_ALL_LANES { - if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) + if (ctrl->timings[channel][slotrank].lanes[lane].rcven >= QCLK_PI) some_high = 1; else all_high = 0; @@ -1393,8 +1366,8 @@ int receive_enable_calibration(ramctr_timing *ctrl) ctrl->timings[channel][slotrank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; - upperA[lane] -= 0x40; + ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI; + upperA[lane] -= QCLK_PI; } } else if (some_high) { @@ -1422,14 +1395,14 @@ int receive_enable_calibration(ramctr_timing *ctrl) align_rt_io_latency(ctrl, channel, slotrank, prev); - printram("4/8: %d, %d, %x, %x\n", channel, slotrank, + printram("4/8: %d, %d, % 4d, % 4d\n", channel, slotrank, ctrl->timings[channel][slotrank].roundtrip_latency, ctrl->timings[channel][slotrank].io_latency); printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, - ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: % 4d\n", channel, slotrank, lane, + ctrl->timings[channel][slotrank].lanes[lane].rcven); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1457,17 +1430,11 @@ static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) iosav_write_misc_write_sequence(ctrl, channel, slotrank, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); iosav_write_prea_act_read_sequence(ctrl, channel, slotrank); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } static void tx_dq_threshold_process(int *data, const int count) @@ -1492,18 +1459,17 @@ static void tx_dq_threshold_process(int *data, const int count) static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) { int tx_dq; - int stats[NUM_LANES][MAX_TIMC + 1]; + int stats[NUM_LANES][MAX_TX_DQ + 1]; int lane; wait_for_iosav(channel); iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); - for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = tx_dq; + for (tx_dq = 0; tx_dq <= MAX_TX_DQ; tx_dq++) { + FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].tx_dq = tx_dq; program_timings(ctrl, channel); test_tx_dq(ctrl, channel, slotrank); @@ -1516,7 +1482,7 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); if (rn.all || rn.length < 8) { - printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", + printk(BIOS_EMERG, "tx_dq write leveling failed: %d, %d, %d\n", channel, slotrank, lane); /* * With command training not being done yet, the lane can be erroneous. @@ -1526,12 +1492,12 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); if (rn.all || rn.length < 8) { - printk(BIOS_EMERG, "timC recovery failed\n"); + printk(BIOS_EMERG, "tx_dq recovery failed\n"); return MAKE_ERR; } } - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; - printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + ctrl->timings[channel][slotrank].lanes[lane].tx_dq = rn.middle; + printram("tx_dq: %d, %d, %d: % 4d-% 4d-% 4d\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; @@ -1556,7 +1522,7 @@ static void program_wdb_pattern_length(int channel, const unsigned int num_cache static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) { unsigned int j; - unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; + unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64; for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); @@ -1577,8 +1543,8 @@ static int num_of_channels(const ramctr_timing *ctrl) static void fill_pattern1(ramctr_timing *ctrl, int channel) { unsigned int j; - unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - unsigned int channel_step = 0x40 * num_of_channels(ctrl); + unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64; + unsigned int channel_step = 64 * num_of_channels(ctrl); for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); @@ -1591,10 +1557,12 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel) program_wdb_pattern_length(channel, 16); } +#define TX_DQS_PI_LENGTH (2 * QCLK_PI) + static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) { - int timB; - int statistics[NUM_LANES][128]; + int tx_dqs; + int statistics[NUM_LANES][TX_DQS_PI_LENGTH]; int lane; const union gdcr_training_mod_reg training_mod = { @@ -1616,47 +1584,44 @@ static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); - for (timB = 0; timB < 128; timB++) { + for (tx_dqs = 0; tx_dqs < TX_DQS_PI_LENGTH; tx_dqs++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timB = timB; + ctrl->timings[channel][slotrank].lanes[lane].tx_dqs = tx_dqs; } program_timings(ctrl, channel); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); FOR_ALL_LANES { - statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + - GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> - (timB % 32)) & 1); + statistics[lane][tx_dqs] = !((MCHBAR32(lane_base[lane] + + GDCRTRAININGRESULT(channel, (tx_dqs / 32) & 1)) >> + (tx_dqs % 32)) & 1); } } FOR_ALL_LANES { - struct run rn = get_longest_zero_run(statistics[lane], 128); + struct run rn = get_longest_zero_run(statistics[lane], TX_DQS_PI_LENGTH); /* - * timC is a direct function of timB's 6 LSBs. Some tests increments the value - * of timB by a small value, which might cause the 6-bit value to overflow if + * tx_dq is a direct function of tx_dqs's 6 LSBs. Some tests increment the value + * of tx_dqs by a small value, which might cause the 6-bit value to overflow if * it's close to 0x3f. Increment the value by a small offset if it's likely * to overflow, to make sure it won't overflow while running tests and bricks - * the system due to a non matching timC. + * the system due to a non matching tx_dq. * - * TODO: find out why some tests (edge write discovery) increment timB. + * TODO: find out why some tests (edge write discovery) increment tx_dqs. */ if ((rn.start & 0x3f) == 0x3e) rn.start += 2; else if ((rn.start & 0x3f) == 0x3f) rn.start += 1; - ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + ctrl->timings[channel][slotrank].lanes[lane].tx_dqs = rn.start; if (rn.all) { - printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", + printk(BIOS_EMERG, "JEDEC write leveling failed: %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; } - printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + printram("tx_dqs: %d, %d, %d: % 4d-% 4d-% 4d\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; @@ -1703,10 +1668,7 @@ static void train_write_flyby(ramctr_timing *ctrl) iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); const struct iosav_ssq rd_sequence[] = { /* DRAM command PREA */ @@ -1722,7 +1684,7 @@ static void train_write_flyby(ramctr_timing *ctrl) .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -1774,22 +1736,20 @@ static void train_write_flyby(ramctr_timing *ctrl) }; iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); - wait_for_iosav(channel); FOR_ALL_LANES { u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); res |= ((u64) MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_dqs_flyby_adjust(res) * 64; + old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; + ctrl->timings[channel][slotrank].lanes[lane].tx_dqs += + get_dqs_flyby_adjust(res) * QCLK_PI; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, - old, ctrl->timings[channel][slotrank].lanes[lane].timB); + printram("Bval+: %d, %d, %d, % 4d -> % 4d\n", channel, slotrank, lane, + old, ctrl->timings[channel][slotrank].lanes[lane].tx_dqs); } } MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1805,10 +1765,7 @@ static void disable_refresh_machine(ramctr_timing *ctrl) iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } @@ -1818,9 +1775,7 @@ static void disable_refresh_machine(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { /* Execute the same command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } } @@ -1860,7 +1815,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) toggle_io_reset(); - /* Set any valid value for timB, it gets corrected later */ + /* Set any valid value for tx_dqs, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { const int err = write_level_rank(ctrl, channel, slotrank); if (err) @@ -1886,10 +1841,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } toggle_io_reset(); @@ -1902,6 +1854,10 @@ int write_training(ramctr_timing *ctrl) int channel, slotrank; int err; + /* + * Set the DEC_WRD bit, required for the write flyby algorithm. + * Needs to be done before starting the write training procedure. + */ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); @@ -1926,7 +1882,7 @@ int write_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - /* measure and adjust timB timings */ + /* measure and adjust tx_dqs timings */ train_write_flyby(ctrl); FOR_ALL_POPULATED_CHANNELS @@ -1938,15 +1894,15 @@ int write_training(ramctr_timing *ctrl) static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) { struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; - int timC_delta; + int tx_dq_delta; int lanes_ok = 0; int ctr = 0; int lane; - for (timC_delta = -5; timC_delta <= 5; timC_delta++) { + for (tx_dq_delta = -5; tx_dq_delta <= 5; tx_dq_delta++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timC = - saved_rt.lanes[lane].timC + timC_delta; + ctrl->timings[channel][slotrank].lanes[lane].tx_dq = + saved_rt.lanes[lane].tx_dq + tx_dq_delta; } program_timings(ctrl, channel); FOR_ALL_LANES { @@ -1964,10 +1920,8 @@ static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); - wait_for_iosav(channel); FOR_ALL_LANES { u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); @@ -1987,8 +1941,8 @@ static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) { unsigned int i, j; - unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; - unsigned int step = 0x40 * num_of_channels(ctrl); + unsigned int offset = get_precedening_channels(ctrl, channel) * 64; + unsigned int step = 64 * num_of_channels(ctrl); if (patno) { u8 base8 = 0x80 >> ((patno - 1) % 8); @@ -2029,8 +1983,8 @@ static void reprogram_320c(ramctr_timing *ctrl) toggle_io_reset(); } -#define CT_MIN_PI -127 -#define CT_MAX_PI 128 +#define CT_MIN_PI (-CCC_MAX_PI) +#define CT_MAX_PI (+CCC_MAX_PI + 1) #define CT_PI_LENGTH (CT_MAX_PI - CT_MIN_PI + 1) #define MIN_C320C_LEN 13 @@ -2086,7 +2040,7 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; - printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", + printram("cmd_stretch: %d, %d: % 4d-% 4d-% 4d\n", channel, slotrank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2119,7 +2073,7 @@ int command_training(ramctr_timing *ctrl) /* * Dual DIMM per channel: * Issue: - * While c320c discovery seems to succeed raminit will fail in write training. + * While command training seems to succeed, raminit will fail in write training. * * Workaround: * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. @@ -2141,7 +2095,7 @@ int command_training(ramctr_timing *ctrl) } if (err) { - printk(BIOS_EMERG, "c320c discovery failed\n"); + printk(BIOS_EMERG, "Command training failed: %d\n", channel); return err; } @@ -2163,8 +2117,8 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = dqs_pi; - ctrl->timings[channel][slotrank].lanes[lane].falling = dqs_pi; + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = dqs_pi; + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = dqs_pi; } program_timings(ctrl, channel); @@ -2178,10 +2132,7 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, iosav_write_read_mpr_sequence( channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); FOR_ALL_LANES { stats[lane][dqs_pi] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); @@ -2193,11 +2144,11 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, edges[lane] = rn.middle; if (rn.all) { - printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, + printk(BIOS_EMERG, "Read MPR training failed: %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; } - printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); + printram("eval %d, %d, %d: % 4d\n", channel, slotrank, lane, edges[lane]); } return 0; } @@ -2213,8 +2164,8 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = 16; + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = 16; + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = 16; } program_timings(ctrl, channel); @@ -2225,17 +2176,14 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) iosav_write_read_mpr_sequence( channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } /* XXX: check any measured value ? */ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = 48; + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = 48; } program_timings(ctrl, channel); @@ -2246,10 +2194,7 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) iosav_write_read_mpr_sequence( channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } /* XXX: check any measured value ? */ @@ -2281,8 +2226,8 @@ int read_mpr_training(ramctr_timing *ctrl) * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will * also use a single loop. It would seem that it is a debugging configuration. */ - MCHBAR32(IOSAV_DC_MASK) = 0x300; - printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); + MCHBAR32(IOSAV_DC_MASK) = 3 << 8; + printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = find_read_mpr_margin(ctrl, channel, slotrank, @@ -2291,8 +2236,8 @@ int read_mpr_training(ramctr_timing *ctrl) return err; } - MCHBAR32(IOSAV_DC_MASK) = 0x200; - printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); + MCHBAR32(IOSAV_DC_MASK) = 2 << 8; + printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = find_read_mpr_margin(ctrl, channel, slotrank, @@ -2304,9 +2249,9 @@ int read_mpr_training(ramctr_timing *ctrl) MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = falling_edges[channel][slotrank][lane]; - ctrl->timings[channel][slotrank].lanes[lane].rising = + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = rising_edges[channel][slotrank][lane]; } @@ -2347,10 +2292,10 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane]. - rising = read_pi; - ctrl->timings[channel][slotrank].lanes[lane]. - falling = read_pi; + ctrl->timings[channel][slotrank].lanes[lane] + .rx_dqs_p = read_pi; + ctrl->timings[channel][slotrank].lanes[lane] + .rx_dqs_n = read_pi; } program_timings(ctrl, channel); @@ -2362,10 +2307,8 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank iosav_write_data_write_sequence(ctrl, channel, slotrank); - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); - wait_for_iosav(channel); FOR_ALL_LANES { MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } @@ -2383,8 +2326,8 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, + printram("edges: %d, %d, %d: % 4d-% 4d-% 4d, " + "% 4d-% 4d\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); @@ -2393,7 +2336,7 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank edges[lane] = (lower[lane] + upper[lane]) / 2; if (rn.all || (lower[lane] > upper[lane])) { - printk(BIOS_EMERG, "edge write discovery failed: " + printk(BIOS_EMERG, "Aggressive read training failed: " "%d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -2418,8 +2361,8 @@ int aggressive_read_training(ramctr_timing *ctrl) * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will * also use a single loop. It would seem that it is a debugging configuration. */ - MCHBAR32(IOSAV_DC_MASK) = 0x300; - printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); + MCHBAR32(IOSAV_DC_MASK) = 3 << 8; + printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = find_agrsv_read_margin(ctrl, channel, slotrank, @@ -2428,8 +2371,8 @@ int aggressive_read_training(ramctr_timing *ctrl) return err; } - MCHBAR32(IOSAV_DC_MASK) = 0x200; - printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); + MCHBAR32(IOSAV_DC_MASK) = 2 << 8; + printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = find_agrsv_read_margin(ctrl, channel, slotrank, @@ -2441,10 +2384,10 @@ int aggressive_read_training(ramctr_timing *ctrl) MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = falling_edges[channel][slotrank][lane]; - ctrl->timings[channel][slotrank].lanes[lane].rising = + ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_p = rising_edges[channel][slotrank][lane]; } @@ -2460,10 +2403,7 @@ static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); + iosav_run_once_and_wait(channel); } static void set_write_vref(const int channel, const u8 wr_vref) @@ -2490,7 +2430,7 @@ int aggressive_write_training(ramctr_timing *ctrl) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { lower[channel][slotrank][lane] = 0; - upper[channel][slotrank][lane] = MAX_TIMC; + upper[channel][slotrank][lane] = MAX_TX_DQ; } /* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ @@ -2499,7 +2439,7 @@ int aggressive_write_training(ramctr_timing *ctrl) if (enable_iosav_opt) MCHBAR32(MCMNTS_SPARE) = 1; - printram("discover timC write:\n"); + printram("Aggresive write training:\n"); for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { @@ -2507,56 +2447,56 @@ int aggressive_write_training(ramctr_timing *ctrl) for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { - int timC; - u32 raw_stats[MAX_TIMC + 1]; - int stats[MAX_TIMC + 1]; + int tx_dq; + u32 raw_stats[MAX_TX_DQ + 1]; + int stats[MAX_TX_DQ + 1]; /* Make sure rn.start < rn.end */ - stats[MAX_TIMC] = 1; + stats[MAX_TX_DQ] = 1; fill_pattern5(ctrl, channel, pat); - for (timC = 0; timC < MAX_TIMC; timC++) { + for (tx_dq = 0; tx_dq < MAX_TX_DQ; tx_dq++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank] - .lanes[lane].timC = timC; + .lanes[lane].tx_dq = tx_dq; } program_timings(ctrl, channel); test_aggressive_write(ctrl, channel, slotrank); - raw_stats[timC] = MCHBAR32( + raw_stats[tx_dq] = MCHBAR32( IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { struct run rn; - for (timC = 0; timC < MAX_TIMC; timC++) { - stats[timC] = !!(raw_stats[timC] + for (tx_dq = 0; tx_dq < MAX_TX_DQ; tx_dq++) { + stats[tx_dq] = !!(raw_stats[tx_dq] & (1 << lane)); } - rn = get_longest_zero_run(stats, MAX_TIMC + 1); + rn = get_longest_zero_run(stats, MAX_TX_DQ + 1); if (rn.all) { - printk(BIOS_EMERG, - "timC write discovery failed: " + printk(BIOS_EMERG, "Aggressive " + "write training failed: " "%d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; } - printram("timC: %d, %d, %d: " - "0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, + printram("tx_dq: %d, %d, %d: " + "% 4d-% 4d-% 4d, " + "% 4d-% 4d\n", channel, slotrank, i, rn.start, rn.middle, rn.end, - rn.start + ctrl->timC_offset[i], - rn.end - ctrl->timC_offset[i]); + rn.start + ctrl->tx_dq_offset[i], + rn.end - ctrl->tx_dq_offset[i]); lower[channel][slotrank][lane] = - MAX(rn.start + ctrl->timC_offset[i], + MAX(rn.start + ctrl->tx_dq_offset[i], lower[channel][slotrank][lane]); upper[channel][slotrank][lane] = - MIN(rn.end - ctrl->timC_offset[i], + MIN(rn.end - ctrl->tx_dq_offset[i], upper[channel][slotrank][lane]); } @@ -2577,11 +2517,11 @@ int aggressive_write_training(ramctr_timing *ctrl) printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, + printram("tx_dq %d, %d, %d: % 4d\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); - ctrl->timings[channel][slotrank].lanes[lane].timC = + ctrl->timings[channel][slotrank].lanes[lane].tx_dq = (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2; } @@ -2600,7 +2540,7 @@ void normalize_training(ramctr_timing *ctrl) int delta; mat = 0; FOR_ALL_LANES mat = - MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][slotrank].lanes[lane].rcven, mat); printram("normalize %d, %d, %d: mat %d\n", channel, slotrank, lane, mat); @@ -2642,10 +2582,8 @@ int channel_test(ramctr_timing *ctrl) iosav_write_memory_test_sequence(ctrl, channel, slotrank); - /* Execute command queue */ - iosav_run_once(channel); + iosav_run_once_and_wait(channel); - wait_for_iosav(channel); FOR_ALL_LANES if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", @@ -2765,7 +2703,6 @@ void channel_scrub(ramctr_timing *ctrl) }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); - /* Execute command queue */ iosav_run_queue(channel, 16, 0); wait_for_iosav(channel); @@ -2892,8 +2829,8 @@ void final_registers(ramctr_timing *ctrl) FOR_ALL_CHANNELS MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; - MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK - MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK + MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; + MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { @@ -3042,7 +2979,7 @@ void restore_timings(ramctr_timing *ctrl) MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; FOR_ALL_CHANNELS { - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24)); udelay(2); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index debfaa2f2aa..0015a098194 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -3,23 +3,12 @@ #ifndef RAMINIT_COMMON_H #define RAMINIT_COMMON_H +#include #include #define BASEFREQ 133 #define tDLLK 512 -#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) -#define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) -#define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) -#define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) -#define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) - -#define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) -#define IS_IVY_CPU_C(x) ((x & 0xf) == 4) -#define IS_IVY_CPU_K(x) ((x & 0xf) == 5) -#define IS_IVY_CPU_D(x) ((x & 0xf) == 6) -#define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) - #define NUM_CHANNELS 2 #define NUM_SLOTRANKS 4 #define NUM_SLOTS 2 @@ -98,6 +87,34 @@ struct iosav_ssq { } addr_update; }; +union gdcr_rx_reg { + struct { + u32 rcven_pi_code : 6; /* [ 5.. 0] */ + u32 : 2; + u32 rx_dqs_p_pi_code : 7; /* [14.. 8] */ + u32 : 1; + u32 rcven_logic_delay : 3; /* [18..16] */ + u32 : 1; + u32 rx_dqs_n_pi_code : 7; /* [26..20] */ + u32 : 5; + }; + u32 raw; +}; + +union gdcr_tx_reg { + struct { + u32 tx_dq_pi_code : 6; /* [ 5.. 0] */ + u32 : 2; + u32 tx_dqs_pi_code : 6; /* [13.. 8] */ + u32 : 1; + u32 tx_dqs_logic_delay : 3; /* [17..15] */ + u32 : 1; + u32 tx_dq_logic_delay : 1; /* [19..19] */ + u32 : 12; + }; + u32 raw; +}; + union gdcr_cmd_pi_coding_reg { struct { u32 cmd_pi_code : 6; /* [ 5.. 0] */ @@ -263,8 +280,8 @@ typedef struct ramctr_timing_st ramctr_timing; void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); -void iosav_run_once(const int ch); void wait_for_iosav(int channel); +void iosav_run_once_and_wait(const int ch); void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap); void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); @@ -321,14 +338,14 @@ struct ram_rank_timings { int pi_coding; struct ram_lane_timings { - /* Lane register offset 0x10 */ - u16 timA; /* bits 0 - 5, bits 16 - 18 */ - u8 rising; /* bits 8 - 14 */ - u8 falling; /* bits 20 - 26 */ - - /* Lane register offset 0x20 */ - int timC; /* bits 0 - 5, 19 */ - u16 timB; /* bits 8 - 13, 15 - 17 */ + /* GDCR RX timings */ + u16 rcven; + u8 rx_dqs_p; + u8 rx_dqs_n; + + /* GDCR TX timings */ + int tx_dq; + u16 tx_dqs; } lanes[NUM_LANES]; }; @@ -391,7 +408,7 @@ typedef struct ramctr_timing_st { bool ecc_enabled; int lanes; /* active lanes: 8 or 9 */ int edge_offset[3]; - int timC_offset[3]; + int tx_dq_offset[3]; int extended_temperature_range; int auto_self_refresh; @@ -410,12 +427,18 @@ typedef struct ramctr_timing_st { #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) #define MAX_EDGE_TIMING 71 -#define MAX_TIMC 127 -#define MAX_TIMB 511 -#define MAX_TIMA 127 +#define MAX_TX_DQ 127 +#define MAX_TX_DQS 511 +#define MAX_RCVEN 127 #define MAX_CAS 18 #define MIN_CAS 4 +/* + * 1 QCLK (quarter of a clock cycle) equals 64 PI (phase interpolator) ticks. + * Logic delay values in I/O register bitfields are expressed in QCLKs. + */ +#define QCLK_PI 64 + #define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) #define GET_ERR_CHANNEL(x) (x >> 16) diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index d83dfd8e9a1..86b3baaa01d 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -36,11 +36,6 @@ void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); } -void iosav_run_once(const int ch) -{ - iosav_run_queue(ch, 1, 0); -} - void wait_for_iosav(int channel) { while (1) { @@ -49,6 +44,12 @@ void wait_for_iosav(int channel) } } +void iosav_run_once_and_wait(const int ch) +{ + iosav_run_queue(ch, 1, 0); + wait_for_iosav(ch); +} + void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap) { const struct iosav_ssq sequence[] = { @@ -93,7 +94,7 @@ void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap) .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -215,7 +216,7 @@ void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int sl .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -283,7 +284,7 @@ void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int sl .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -571,7 +572,7 @@ void iosav_write_command_training_sequence( .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -669,7 +670,7 @@ void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotr .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -764,7 +765,7 @@ void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, @@ -859,7 +860,7 @@ void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slot .data_direction = SSQ_NA, }, .sp_cmd_addr = { - .address = 1024, + .address = 1 << 10, .rowbits = 6, .bank = 0, .rank = slotrank, diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 3522e96eccb..9961e890698 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -395,99 +396,99 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->edge_offset[0] = 18; //XXX: guessed ctrl->edge_offset[1] = 8; ctrl->edge_offset[2] = 8; - ctrl->timC_offset[0] = 20; //XXX: guessed - ctrl->timC_offset[1] = 8; - ctrl->timC_offset[2] = 8; + ctrl->tx_dq_offset[0] = 20; //XXX: guessed + ctrl->tx_dq_offset[1] = 8; + ctrl->tx_dq_offset[2] = 8; ctrl->pi_coding_threshold = 10; } else if (ctrl->tCK == TCK_1100MHZ) { ctrl->edge_offset[0] = 17; //XXX: guessed ctrl->edge_offset[1] = 7; ctrl->edge_offset[2] = 7; - ctrl->timC_offset[0] = 19; //XXX: guessed - ctrl->timC_offset[1] = 7; - ctrl->timC_offset[2] = 7; + ctrl->tx_dq_offset[0] = 19; //XXX: guessed + ctrl->tx_dq_offset[1] = 7; + ctrl->tx_dq_offset[2] = 7; ctrl->pi_coding_threshold = 13; } else if (ctrl->tCK == TCK_1066MHZ) { ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; ctrl->edge_offset[2] = 7; - ctrl->timC_offset[0] = 18; - ctrl->timC_offset[1] = 7; - ctrl->timC_offset[2] = 7; + ctrl->tx_dq_offset[0] = 18; + ctrl->tx_dq_offset[1] = 7; + ctrl->tx_dq_offset[2] = 7; ctrl->pi_coding_threshold = 13; } else if (ctrl->tCK == TCK_1000MHZ) { ctrl->edge_offset[0] = 15; //XXX: guessed ctrl->edge_offset[1] = 6; ctrl->edge_offset[2] = 6; - ctrl->timC_offset[0] = 17; //XXX: guessed - ctrl->timC_offset[1] = 6; - ctrl->timC_offset[2] = 6; + ctrl->tx_dq_offset[0] = 17; //XXX: guessed + ctrl->tx_dq_offset[1] = 6; + ctrl->tx_dq_offset[2] = 6; ctrl->pi_coding_threshold = 13; } else if (ctrl->tCK == TCK_933MHZ) { ctrl->edge_offset[0] = 14; ctrl->edge_offset[1] = 6; ctrl->edge_offset[2] = 6; - ctrl->timC_offset[0] = 15; - ctrl->timC_offset[1] = 6; - ctrl->timC_offset[2] = 6; + ctrl->tx_dq_offset[0] = 15; + ctrl->tx_dq_offset[1] = 6; + ctrl->tx_dq_offset[2] = 6; ctrl->pi_coding_threshold = 15; } else if (ctrl->tCK == TCK_900MHZ) { ctrl->edge_offset[0] = 14; //XXX: guessed ctrl->edge_offset[1] = 6; ctrl->edge_offset[2] = 6; - ctrl->timC_offset[0] = 15; //XXX: guessed - ctrl->timC_offset[1] = 6; - ctrl->timC_offset[2] = 6; + ctrl->tx_dq_offset[0] = 15; //XXX: guessed + ctrl->tx_dq_offset[1] = 6; + ctrl->tx_dq_offset[2] = 6; ctrl->pi_coding_threshold = 12; } else if (ctrl->tCK == TCK_800MHZ) { ctrl->edge_offset[0] = 13; ctrl->edge_offset[1] = 5; ctrl->edge_offset[2] = 5; - ctrl->timC_offset[0] = 14; - ctrl->timC_offset[1] = 5; - ctrl->timC_offset[2] = 5; + ctrl->tx_dq_offset[0] = 14; + ctrl->tx_dq_offset[1] = 5; + ctrl->tx_dq_offset[2] = 5; ctrl->pi_coding_threshold = 15; } else if (ctrl->tCK == TCK_700MHZ) { ctrl->edge_offset[0] = 13; //XXX: guessed ctrl->edge_offset[1] = 5; ctrl->edge_offset[2] = 5; - ctrl->timC_offset[0] = 14; //XXX: guessed - ctrl->timC_offset[1] = 5; - ctrl->timC_offset[2] = 5; + ctrl->tx_dq_offset[0] = 14; //XXX: guessed + ctrl->tx_dq_offset[1] = 5; + ctrl->tx_dq_offset[2] = 5; ctrl->pi_coding_threshold = 16; } else if (ctrl->tCK == TCK_666MHZ) { ctrl->edge_offset[0] = 10; ctrl->edge_offset[1] = 4; ctrl->edge_offset[2] = 4; - ctrl->timC_offset[0] = 11; - ctrl->timC_offset[1] = 4; - ctrl->timC_offset[2] = 4; + ctrl->tx_dq_offset[0] = 11; + ctrl->tx_dq_offset[1] = 4; + ctrl->tx_dq_offset[2] = 4; ctrl->pi_coding_threshold = 16; } else if (ctrl->tCK == TCK_533MHZ) { ctrl->edge_offset[0] = 8; ctrl->edge_offset[1] = 3; ctrl->edge_offset[2] = 3; - ctrl->timC_offset[0] = 9; - ctrl->timC_offset[1] = 3; - ctrl->timC_offset[2] = 3; + ctrl->tx_dq_offset[0] = 9; + ctrl->tx_dq_offset[1] = 3; + ctrl->tx_dq_offset[2] = 3; ctrl->pi_coding_threshold = 17; } else { /* TCK_400MHZ */ ctrl->edge_offset[0] = 6; ctrl->edge_offset[1] = 2; ctrl->edge_offset[2] = 2; - ctrl->timC_offset[0] = 6; - ctrl->timC_offset[1] = 2; - ctrl->timC_offset[2] = 2; + ctrl->tx_dq_offset[0] = 6; + ctrl->tx_dq_offset[1] = 2; + ctrl->tx_dq_offset[2] = 2; ctrl->pi_coding_threshold = 17; } @@ -577,13 +578,13 @@ static void dram_freq(ramctr_timing *ctrl) /* Step 2 - Select frequency in the MCU */ reg1 = ctrl->FRQ; if (ctrl->base_freq == 100) - reg1 |= 0x100; /* Enable 100Mhz REF clock */ + reg1 |= (1 << 8); /* Enable 100Mhz REF clock */ - reg1 |= 0x80000000; /* set running bit */ + reg1 |= (1 << 31); /* set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; int i = 0; printk(BIOS_DEBUG, "PLL busy... "); - while (reg1 & 0x80000000) { + while (reg1 & (1 << 31)) { udelay(10); i++; reg1 = MCHBAR32(MC_BIOS_REQ); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e5f2132ab8e..235ca0e1947 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -8,18 +8,6 @@ #define BASE_REV_IVB 0x50 #define BASE_REV_MASK 0x50 -/* SandyBridge CPU stepping */ -#define SNB_STEP_D0 5 /* Also J0 */ -#define SNB_STEP_D1 6 -#define SNB_STEP_D2 7 /* Also J1/Q0 */ - -/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 0 -#define IVB_STEP_B0 2 -#define IVB_STEP_C0 4 -#define IVB_STEP_K0 5 -#define IVB_STEP_D0 6 - #include "memmap.h" /* Everything below this line is ignored in the DSDT */ diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8226fe90ee1..00e9a3ad210 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,7 +13,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select CACHE_MRC_SETTINGS select PARALLEL_MP select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES - select NO_CBFS_MCACHE config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 5a3c0b61324..b013da7814d 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -30,3 +30,6 @@ Device (PDRC) // PCIe graphics port 0:1.0 #include "peg.asl" + +// Integrated graphics 0:2.0 +#include diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 4362bd6307b..4722dfe7a60 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -278,7 +278,7 @@ int do_write_training(struct sysinfo *s) s->dq_settings[channel][lane] = s->dqs_settings[channel][lane]; } memset(dq_lower, 0, sizeof(dq_lower)); - /* Start from DQS settings */ + /* Start from DQS settings */ memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting)); if (find_dq_limit(s, channel, dq_setting, dq_lower, @@ -525,49 +525,49 @@ static void set_rank_write_level(struct sysinfo *s, u8 channel, u8 config, /* Is shifted by bits 2 later so u8 can be used to reduce size */ static const u8 emrs1_lut[8][4][4] = { /* [Config][Leveling Rank][Rank] */ - { /* Config 0: 2R2R */ + { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x91, 0x00, 0x00, 0x11} }, - { // Config 1: 2R1R + { /* Config 1: 2R1R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 2: 1R2R + { /* Config 2: 1R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x91, 0x00, 0x00, 0x11} }, - { // Config 3: 1R1R + { /* Config 3: 1R1R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 4: 2R0R + { /* Config 4: 2R0R */ {0x11, 0x00, 0x00, 0x00}, {0x00, 0x11, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 5: 0R2R + { /* Config 5: 0R2R */ {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x11, 0x00}, {0x00, 0x00, 0x00, 0x11} }, - { // Config 6: 1R0R + { /* Config 6: 1R0R */ {0x11, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 7: 0R1R + { /* Config 7: 0R1R */ {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x11, 0x00}, @@ -746,7 +746,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank) * DDR3 uses flyby topology where the clock signal takes a different path * than the data signal, to allow for better signal intergrity. * Therefore the delay on the data signals needs to account for this. - * This is done by by sampleling the the DQS write (tx) signal back over + * This is done by sampleling the DQS write (tx) signal back over * the DQ signal and looking for delay values where the sample transitions * from high to low. * Here the following is done: diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 00cc6096a33..586df389a8c 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -635,8 +635,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) /* verify MRC cache for fast boot */ if (boot_path != BOOT_PATH_RESUME && ctrl_cached) { - /* check SPD checksum to make sure the DIMMs haven't been - * replaced */ + /* check SPD checksum to make sure the DIMMs haven't been replaced */ fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS; if (!fast_boot) { printk(BIOS_DEBUG, "SPD checksums don't match," diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 43b9b90cfe5..fc39a5d6420 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -221,7 +221,7 @@ static void launch_dram(struct sysinfo *s) if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) s->nmode = 1; - /* 2N on DDR3 1066 with with 2 dimms per channel */ + /* 2N on DDR3 1066 with 2 dimms per channel */ if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) @@ -399,18 +399,18 @@ static void program_timings(struct sysinfo *s) adjusted_cas = s->selected_timings.CAS - 3; u16 fsb_to_ps[3] = { - 5000, // 800 - 3750, // 1067 - 3000 // 1333 + 5000, /* 800 */ + 3750, /* 1067 */ + 3000 /* 1333 */ }; u16 ddr_to_ps[6] = { - 5000, // 400 - 3750, // 533 - 3000, // 667 - 2500, // 800 - 1875, // 1067 - 1500 // 1333 + 5000, /* 400 */ + 3750, /* 533 */ + 3000, /* 667 */ + 2500, /* 800 */ + 1875, /* 1067 */ + 1500 /* 1333 */ }; u16 lut1[6] = { @@ -634,7 +634,7 @@ static void program_timings(struct sysinfo *s) MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32); MCHBAR8_AND(0x400*i + 0x271, ~0x80); MCHBAR8_AND(0x400*i + 0x274, ~0x6); - } // END EACH POPULATED CHANNEL + } /* END EACH POPULATED CHANNEL */ reg16 = 0x1f << 5; reg16 |= 0xe << 10; @@ -701,19 +701,19 @@ static void program_dll(struct sysinfo *s) udelay(1); MCHBAR8_AND(0x190, ~1); - udelay(1); // 533ns + udelay(1); /* 533ns */ MCHBAR32_AND(0x198, ~0x11554000); udelay(1); MCHBAR32_AND(0x198, ~0x1455); udelay(1); MCHBAR8_AND(0x583, ~0x1c); MCHBAR8_AND(0x983, ~0x1c); - udelay(1); // 533ns + udelay(1); /* 533ns */ MCHBAR8_AND(0x583, ~0x3); MCHBAR8_AND(0x983, ~0x3); - udelay(1); // 533ns + udelay(1); /* 533ns */ - // ME related + /* ME related */ MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801); @@ -778,7 +778,7 @@ static void program_dll(struct sysinfo *s) } //reg8 = 0x00; // FIXME don't switch on all clocks anyway - } // END EACH CHANNEL + } /* END EACH CHANNEL */ if (s->spd_type == DDR2) { MCHBAR8_OR(0x1a8, 1); @@ -788,7 +788,7 @@ static void program_dll(struct sysinfo *s) MCHBAR8_OR(0x1a8, 0x4); } - // Update DLL timing + /* Update DLL timing */ MCHBAR8_AND(0x1a4, ~0x80); MCHBAR8_OR(0x1a4, 0x40); MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400); @@ -833,7 +833,7 @@ static void program_dll(struct sysinfo *s) cmdset(i, &setting[CMD]); } - // XXX if not async mode + /* XXX if not async mode */ MCHBAR16_AND(0x180, ~0x8200); MCHBAR8_OR(0x180, 0x4); j = 0; @@ -1016,7 +1016,7 @@ static void select_default_dq_dqs_settings(struct sysinfo *s) */ static void set_all_dq_dqs_dll_settings(struct sysinfo *s) { - // Program DQ/DQS dll settings + /* Program DQ/DQS dll settings */ int ch, lane, rank; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { @@ -1138,7 +1138,7 @@ static void prog_rcomp(struct sysinfo *s) MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8); MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8); MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8); - } // END EACH POPULATED CHANNEL + } /* END EACH POPULATED CHANNEL */ MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00); MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff); @@ -1157,41 +1157,41 @@ static void program_odt(struct sysinfo *s) { u8 i; static u16 ddr2_odt[16][2] = { - { 0x0000, 0x0000 }, // NC_NC - { 0x0000, 0x0001 }, // x8SS_NC - { 0x0000, 0x0011 }, // x8DS_NC - { 0x0000, 0x0001 }, // x16SS_NC - { 0x0004, 0x0000 }, // NC_x8SS - { 0x0101, 0x0404 }, // x8SS_x8SS - { 0x0101, 0x4444 }, // x8DS_x8SS - { 0x0101, 0x0404 }, // x16SS_x8SS - { 0x0044, 0x0000 }, // NC_x8DS - { 0x1111, 0x0404 }, // x8SS_x8DS - { 0x1111, 0x4444 }, // x8DS_x8DS - { 0x1111, 0x0404 }, // x16SS_x8DS - { 0x0004, 0x0000 }, // NC_x16SS - { 0x0101, 0x0404 }, // x8SS_x16SS - { 0x0101, 0x4444 }, // x8DS_x16SS - { 0x0101, 0x0404 }, // x16SS_x16SS + { 0x0000, 0x0000 }, /* NC_NC */ + { 0x0000, 0x0001 }, /* x8SS_NC */ + { 0x0000, 0x0011 }, /* x8DS_NC */ + { 0x0000, 0x0001 }, /* x16SS_NC */ + { 0x0004, 0x0000 }, /* NC_x8SS */ + { 0x0101, 0x0404 }, /* x8SS_x8SS */ + { 0x0101, 0x4444 }, /* x8DS_x8SS */ + { 0x0101, 0x0404 }, /* x16SS_x8SS */ + { 0x0044, 0x0000 }, /* NC_x8DS */ + { 0x1111, 0x0404 }, /* x8SS_x8DS */ + { 0x1111, 0x4444 }, /* x8DS_x8DS */ + { 0x1111, 0x0404 }, /* x16SS_x8DS */ + { 0x0004, 0x0000 }, /* NC_x16SS */ + { 0x0101, 0x0404 }, /* x8SS_x16SS */ + { 0x0101, 0x4444 }, /* x8DS_x16SS */ + { 0x0101, 0x0404 }, /* x16SS_x16SS */ }; static const u16 ddr3_odt[16][2] = { - { 0x0000, 0x0000 }, // NC_NC - { 0x0000, 0x0001 }, // x8SS_NC - { 0x0000, 0x0021 }, // x8DS_NC - { 0x0000, 0x0001 }, // x16SS_NC - { 0x0004, 0x0000 }, // NC_x8SS - { 0x0105, 0x0405 }, // x8SS_x8SS - { 0x0105, 0x4465 }, // x8DS_x8SS - { 0x0105, 0x0405 }, // x16SS_x8SS - { 0x0084, 0x0000 }, // NC_x8DS - { 0x1195, 0x0405 }, // x8SS_x8DS - { 0x1195, 0x4465 }, // x8DS_x8DS - { 0x1195, 0x0405 }, // x16SS_x8DS - { 0x0004, 0x0000 }, // NC_x16SS - { 0x0105, 0x0405 }, // x8SS_x16SS - { 0x0105, 0x4465 }, // x8DS_x16SS - { 0x0105, 0x0405 }, // x16SS_x16SS + { 0x0000, 0x0000 }, /* NC_NC */ + { 0x0000, 0x0001 }, /* x8SS_NC */ + { 0x0000, 0x0021 }, /* x8DS_NC */ + { 0x0000, 0x0001 }, /* x16SS_NC */ + { 0x0004, 0x0000 }, /* NC_x8SS */ + { 0x0105, 0x0405 }, /* x8SS_x8SS */ + { 0x0105, 0x4465 }, /* x8DS_x8SS */ + { 0x0105, 0x0405 }, /* x16SS_x8SS */ + { 0x0084, 0x0000 }, /* NC_x8DS */ + { 0x1195, 0x0405 }, /* x8SS_x8DS */ + { 0x1195, 0x4465 }, /* x8DS_x8DS */ + { 0x1195, 0x0405 }, /* x16SS_x8DS */ + { 0x0004, 0x0000 }, /* NC_x16SS */ + { 0x0105, 0x0405 }, /* x8SS_x16SS */ + { 0x0105, 0x4465 }, /* x8DS_x16SS */ + { 0x0105, 0x0405 }, /* x16SS_x16SS */ }; FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { @@ -1283,8 +1283,8 @@ u32 test_address(int channel, int rank) } /* DDR3 Rank1 Address mirror - * swap the following pins: - * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ + swap the following pins: + A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ static u32 mirror_shift_bit(const u32 data, u8 bit) { u32 temp0 = data, temp1 = data; @@ -1353,12 +1353,12 @@ static void jedec_ddr2(struct sysinfo *s) {EMRS2_CMD, 0x0}, {EMRS3_CMD, 0x0}, {EMRS1_CMD, 0x0}, - {MRS_CMD, 0x100}, // DLL Reset + {MRS_CMD, 0x100}, /* DLL Reset */ {PRECHARGE_CMD, 0x0}, {CBR_CMD, 0x0}, {CBR_CMD, 0x0}, - {MRS_CMD, 0x0}, // DLL out of reset - {EMRS1_CMD, 0x380}, // OCD calib default + {MRS_CMD, 0x0}, /* DLL out of reset */ + {EMRS1_CMD, 0x380}, /* OCD calib default */ {EMRS1_CMD, 0x0} }; @@ -1430,7 +1430,7 @@ static void jedec_ddr3(struct sysinfo *s) cmd |= (1 << 1); send_jedec_cmd(s, r, ch, EMRS1_CMD, cmd); /* Burst type interleaved, burst length 8, Reset DLL, - * Precharge PD: DLL on */ + Precharge PD: DLL on */ send_jedec_cmd(s, r, ch, MRS_CMD, (1 << 3) | (1 << 8) | (1 << 12) | ((s->selected_timings.CAS - 4) << 4) | ((s->selected_timings.tWR - 4) << 9)); @@ -1519,7 +1519,7 @@ static void set_dradrb(struct sysinfo *s) u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; - // DRA + /* DRA */ rankpop0 = 0; rankpop1 = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { @@ -1563,7 +1563,7 @@ static void set_dradrb(struct sysinfo *s) ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) MCHBAR8_OR(0x660, 1); - // DRB + /* DRB */ lastrank_ch1 = 0; FOR_EACH_RANK(ch, r) { if (ch == 0) { @@ -1703,7 +1703,7 @@ static void configure_mmap(struct sysinfo *s) /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ tsegsize = 2; - mmiosize = 0x800; // 2GB MMIO + mmiosize = 0x800; /* 2GB MMIO */ umasizem = gfxsize + gttsize + tsegsize; mmiostart = 0x1000 - mmiosize + umasizem; tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; @@ -1890,7 +1890,7 @@ static void power_settings(struct sysinfo *s) MCHBAR16(0x115) = (u16) reg1; MCHBAR32_AND_OR(0x117, ~0xffffff, reg2); MCHBAR8(0x124) = 0x7; - // not sure if dummy reads are needed + /* not sure if dummy reads are needed */ MCHBAR16_AND_OR(0x12a, 0, 0x80); MCHBAR8_AND_OR(0x12c, 0, 0xa0); MCHBAR16_AND(0x174, ~(1 << 15)); @@ -1899,14 +1899,14 @@ static void power_settings(struct sysinfo *s) MCHBAR8_OR(0x192, 1); MCHBAR8_OR(0x193, 0xf); MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80); - MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); // | clockgatingiii - // non-aligned access: possible bug? + MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); /* clockgating iii */ + /* non-aligned access: possible bug? */ MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate); MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f); MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0); MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70); - // non-aligned access: possible bug? - MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); // | clockgatingi + /* non-aligned access: possible bug? */ + MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); /* clockgating i */ MCHBAR32(0x2d4) = 0x40453600; MCHBAR32(0x300) = 0xc0b0a08; MCHBAR32(0x304) = 0x6040201; @@ -1980,30 +1980,30 @@ void do_raminit(struct sysinfo *s, int fast_boot) u32 reg32; if (s->boot_path != BOOT_PATH_WARM_RESET) { - // Clear self refresh + /* Clear self refresh */ MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) | PMSTS_BOTH_SELFREFRESH; - // Clear host clk gate reg + /* Clear host clk gate reg */ MCHBAR32_OR(0x1c, 0xffffffff); - // Select type + /* Select type */ if (s->spd_type == DDR2) MCHBAR8_AND(0x1a8, ~0x4); else MCHBAR8_OR(0x1a8, 0x4); - // Set freq + /* Set frequency */ MCHBAR32_AND_OR(0xc00, ~0x70, (s->selected_timings.mem_clk << 4) | (1 << 10)); - // Overwrite freq if chipset rejects it + /* Overwrite value if chipset rejects it */ s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; if (s->selected_timings.mem_clk > (s->max_fsb + 3)) die("Error: DDR is faster than FSB, halt\n"); } - // Program clock crossing + /* Program clock crossing */ program_crossclock(s); printk(BIOS_DEBUG, "Done clk crossing\n"); @@ -2012,31 +2012,31 @@ void do_raminit(struct sysinfo *s, int fast_boot) printk(BIOS_DEBUG, "Done I/O clk\n"); } - // Grant to launch + /* Grant to launch */ launch_dram(s); printk(BIOS_DEBUG, "Done launch\n"); - // Program DRAM timings + /* Program DRAM timings */ program_timings(s); printk(BIOS_DEBUG, "Done timings\n"); - // Program DLL + /* Program DLL */ program_dll(s); if (!fast_boot) select_default_dq_dqs_settings(s); set_all_dq_dqs_dll_settings(s); - // RCOMP + /* RCOMP */ if (s->boot_path != BOOT_PATH_WARM_RESET) { prog_rcomp(s); printk(BIOS_DEBUG, "RCOMP\n"); } - // ODT + /* ODT */ program_odt(s); printk(BIOS_DEBUG, "Done ODT\n"); - // RCOMP update + /* RCOMP update */ if (s->boot_path != BOOT_PATH_WARM_RESET) { while (MCHBAR8(0x130) & 1) ; @@ -2045,7 +2045,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) pre_jedec_memory_map(); - // IOBUFACT + /* IOBUFACT */ if (CHANNEL_IS_POPULATED(s->dimms, 0)) { MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); MCHBAR8_OR(0x5d8, 0x7); @@ -2070,7 +2070,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) udelay(500); } - // Pre jedec + /* Pre jedec */ MCHBAR8_OR(0x40, 0x2); FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { MCHBAR32_OR(0x400*ch + 0x260, 1 << 27); @@ -2079,7 +2079,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) MCHBAR16_OR(0x212, 0xf00); printk(BIOS_DEBUG, "Done pre-jedec\n"); - // JEDEC reset + /* JEDEC reset */ if (s->boot_path != BOOT_PATH_RESUME) { if (s->spd_type == DDR2) jedec_ddr2(s); @@ -2096,7 +2096,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) software_ddr3_reset(s); } - // After JEDEC reset + /* After JEDEC reset */ MCHBAR8_AND(0x40, ~0x2); FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { reg32 = (2 << 18); @@ -2128,12 +2128,12 @@ void do_raminit(struct sysinfo *s, int fast_boot) printk(BIOS_DEBUG, "Done post-jedec\n"); - // Set DDR init complete + /* Set DDR init complete */ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000); } - // Dummy reads + /* Dummy reads */ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) @@ -2142,11 +2142,11 @@ void do_raminit(struct sysinfo *s, int fast_boot) } printk(BIOS_DEBUG, "Done dummy reads\n"); - // Receive enable + /* Receive enable */ sdram_program_receive_enable(s, fast_boot); printk(BIOS_DEBUG, "Done rcven\n"); - // Finish rcven + /* Finish rcven */ FOR_EACH_CHANNEL(ch) { MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe); MCHBAR8_OR(0x400*ch + 0x5d8, 0x2); @@ -2157,7 +2157,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) MCHBAR8_AND(0x5dc, ~0x80); MCHBAR8_OR(0x5dc, 0x80); - // XXX tRD + /* XXX tRD */ if (!fast_boot) { if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { @@ -2168,29 +2168,29 @@ void do_raminit(struct sysinfo *s, int fast_boot) die("DQS read training failed!"); } - // DRADRB + /* DRADRB */ set_dradrb(s); printk(BIOS_DEBUG, "Done DRADRB\n"); - // Memory map + /* Memory map */ configure_mmap(s); printk(BIOS_DEBUG, "Done memory map\n"); - // Enhanced mode + /* Enhanced mode */ set_enhanced_mode(s); printk(BIOS_DEBUG, "Done enhanced mode\n"); - // Periodic RCOMP + /* Periodic RCOMP */ MCHBAR16_AND_OR(0x160, ~0xfff, 0x999); MCHBAR16_OR(0x1b4, 0x3000); MCHBAR8_OR(0x130, 0x82); printk(BIOS_DEBUG, "Done PRCOMP\n"); - // Power settings + /* Power settings */ power_settings(s); printk(BIOS_DEBUG, "Done power settings\n"); - // ME related + /* ME related */ /* * FIXME: This locks some registers like bit1 of GGC * and is only needed in case of ME being used. diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 8a86ce9cb55..1f49beb61c2 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -28,11 +28,13 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel) { u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; - /* Reset the DQS probe */ - MCHBAR8(RESET_CNTL(channel)) &= ~0x2; - udelay(2); - MCHBAR8(RESET_CNTL(channel)) |= 0x2; - udelay(2); + /* Reset the DQS probe, on both channels? */ + for (u8 i = 0; i < TOTAL_CHANNELS; i++) { + MCHBAR8(RESET_CNTL(i)) &= ~0x2; + udelay(1); + MCHBAR8(RESET_CNTL(i)) |= 0x2; + udelay(1); + } mfence(); /* Read strobe */ read32((u32 *)addr); diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index f2e5c76dbaa..b612a81655f 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -6,8 +6,7 @@ boot_policy_manifest.bin-file := $(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY boot_policy_manifest.bin-type := raw boot_policy_manifest.bin-align := 0x10 -INTERMEDIATE+=add_bpm_fit -add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_bpm_fit, $(IFITTOOL)) $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< endif @@ -17,8 +16,7 @@ key_manifest.bin-file := $(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY) key_manifest.bin-type := raw key_manifest.bin-align := 0x10 -INTERMEDIATE+=add_km_fit -add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_km_fit, $(IFITTOOL)) $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< endif diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index abd76673555..cbb111adf04 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -164,7 +164,7 @@ void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); - //setup the the list + //setup the list add_resources_cmd(); stm_load_status = load_stm_image(mseg); diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index f9e4bc4bf43..c1442c86ee7 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -70,4 +70,20 @@ config INTEL_TXT_CBFS_SINIT_ACM string default "txt_sinit_acm.bin" +config INTEL_TXT_SINIT_SIZE + hex + default 0x20000 + help + This is the size that will be programmed in TXT_SINIT_SIZE. + This needs to be at least the size of the SINIT ACM. + This is platform dependent. For instance on CPX this has + to be the ACM size + 64K. + +config INTEL_TXT_HEAP_SIZE + hex + default 0xe0000 + help + This is the size that will be programmed in TXT_HEAP_SIZE. + This is platform dependent. + endif diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 77a5f69f2ad..bac4eb8faab 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -28,8 +28,7 @@ endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -INTERMEDIATE+=add_acm_fit -add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_acm_fit, $(IFITTOOL)) $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< @@ -42,8 +41,7 @@ ibb-files := $(foreach file,$(cbfs-files), \ ibb-files += bootblock -INTERMEDIATE+=add_ibb_fit -add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) +$(call add_intermediate, add_ibb_fit, $(IFITTOOL)) $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT)) true diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 81d2dd1083e..3401aef3364 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -89,23 +89,21 @@ static void check_secrets_txt(void *unused) if (status & ACMSTS_TXT_DISABLED) return; - /* Check for fatal ACM error and TXT reset */ - if (get_wake_error_status()) { - /* - * Check if secrets bit needs to be reset. Only platforms that support - * CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code. - * Assume all memory really was cleared. - * - * TXT will issue a platform reset to come up sober. - */ - if (intel_txt_memory_has_secrets()) { - printk(BIOS_INFO, "TEE-TXT: Wiping TEE...\n"); - intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); + /* + * Check if secrets bit needs to be reset. Only platforms that support + * CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code. + * On some platforms FSP-M takes care of the DRAM clearing. + * Assume all memory really was cleared. + * + * TXT will issue a platform reset to come up sober. + */ + if (intel_txt_memory_has_secrets()) { + printk(BIOS_INFO, "TEE-TXT: Wiping TEE...\n"); + intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); - /* Should never reach this point ... */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); - die("Waiting for platform reset...\n"); - } + /* Should never reach this point ... */ + intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + die("Waiting for platform reset...\n"); } } @@ -173,7 +171,7 @@ static void init_intel_txt(void *unused) } int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { + if (!s3resume && !CONFIG(INTEL_CBNT_SUPPORT)) { printk(BIOS_INFO, "TEE-TXT: Scheck...\n"); if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); @@ -372,6 +370,9 @@ static void lockdown_intel_txt(void *unused) return; } + _Static_assert(CONFIG_INTEL_TXT_HEAP_SIZE + CONFIG_INTEL_TXT_SINIT_SIZE + < CONFIG_INTEL_TXT_DPR_SIZE * MiB, "TXT Heap and Sinit must fit DPR"); + if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) { printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n"); return; @@ -396,7 +397,7 @@ static void lockdown_intel_txt(void *unused) * Document Number: 558294 * Chapter 5.5.6.3 Intel TXT Heap Memory Region */ - write64((void *)TXT_HEAP_SIZE, 0xE0000); + write64((void *)TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); write64((void *)TXT_HEAP_BASE, ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); @@ -404,7 +405,7 @@ static void lockdown_intel_txt(void *unused) * Document Number: 558294 * Chapter 5.5.6.2 SINIT Memory Region */ - write64((void *)TXT_SINIT_SIZE, 0x20000); + write64((void *)TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); write64((void *)TXT_SINIT_BASE, ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - read64((void *)TXT_SINIT_SIZE), 4096)); diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index a3d02353657..8b7778ddb24 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -208,7 +208,7 @@ uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length) const int total_length = kTpmRequestHeaderLength + kWriteInfoLength + length; - VBDEBUG("TPM: tlcl_write(0x%x, %d)\n", index, length); + VBDEBUG("TPM: %s(0x%x, %d)\n", __func__, index, length); memcpy(&cmd, &tpm_nv_write_cmd, sizeof(cmd)); assert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); set_tpm_command_size(cmd.buffer, total_length); @@ -227,7 +227,7 @@ uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) uint32_t result_length; uint32_t result; - VBDEBUG("TPM: tlcl_read(0x%x, %d)\n", index, length); + VBDEBUG("TPM: %s(0x%x, %d)\n", __func__, index, length); memcpy(&cmd, &tpm_nv_read_cmd, sizeof(cmd)); to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.length, length); diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 0e14575f61b..db5f2e773e7 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -221,7 +221,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) * Define and set rec hash space, if available. No need to * create the RW hash space because we will definitely boot * once in normal mode before shipping, meaning that the space - * will get created with correct permissions while still in in + * will get created with correct permissions while still in * our hands. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index be4d43294f1..9b766736f0e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -14,14 +14,27 @@ config SOC_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_CF9_RESET + select IDT_IN_EVERY_STAGE select IOAPIC + select PLATFORM_USES_FSP2_0 select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H + select SOC_AMD_COMMON_BLOCK_UART + select SSE2 + select UDK_2017_BINDING + select X86_AMD_FIXED_MTRRS + +config CHIPSET_DEVICETREE + string + default "soc/amd/cezanne/chipset.cb" config EARLY_RESERVED_DRAM_BASE hex @@ -83,6 +96,12 @@ config FSP_M_SIZE help Sets the size of DRAM allocation for FSP-M in linker script. +config FSP_TEMP_RAM_SIZE + hex + default 0x40000 + help + The amount of coreboot-allocated heap and stack usage by the FSP. + config RAMBASE hex default 0x10000000 @@ -99,4 +118,83 @@ config MMCONF_BUS_NUMBER int default 64 +config MAX_CPUS + int + default 16 + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART + hex + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + +menu "PSP Configuration Options" + +config AMD_FWM_POSITION_INDEX + int "Firmware Directory Table location (0 to 5)" + range 0 5 + default 0 if BOARD_ROMSIZE_KB_512 + default 1 if BOARD_ROMSIZE_KB_1024 + default 2 if BOARD_ROMSIZE_KB_2048 + default 3 if BOARD_ROMSIZE_KB_4096 + default 4 if BOARD_ROMSIZE_KB_8192 + default 5 if BOARD_ROMSIZE_KB_16384 + help + Typically this is calculated by the ROM size, but there may + be situations where you want to put the firmware directory + table in a different location. + 0: 512 KB - 0xFFFA0000 + 1: 1 MB - 0xFFF20000 + 2: 2 MB - 0xFFE20000 + 3: 4 MB - 0xFFC20000 + 4: 8 MB - 0xFF820000 + 5: 16 MB - 0xFF020000 + +comment "AMD Firmware Directory Table set to location for 512KB ROM" + depends on AMD_FWM_POSITION_INDEX = 0 +comment "AMD Firmware Directory Table set to location for 1MB ROM" + depends on AMD_FWM_POSITION_INDEX = 1 +comment "AMD Firmware Directory Table set to location for 2MB ROM" + depends on AMD_FWM_POSITION_INDEX = 2 +comment "AMD Firmware Directory Table set to location for 4MB ROM" + depends on AMD_FWM_POSITION_INDEX = 3 +comment "AMD Firmware Directory Table set to location for 8MB ROM" + depends on AMD_FWM_POSITION_INDEX = 4 +comment "AMD Firmware Directory Table set to location for 16MB ROM" + depends on AMD_FWM_POSITION_INDEX = 5 + +config AMDFW_CONFIG_FILE + string + default "src/soc/amd/cezanne/fw.cfg" + +config USE_PSPSECUREOS + bool + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool + default n + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'n' + +config PSP_LOAD_S0I3_FW + bool + default n + help + Select this item to include the S0i3 file into the PSP build. + +config PSP_UNLOCK_SECURE_DEBUG + bool "Unlock secure debug" + default y + help + Select this item to enable secure debug options in PSP. + +endmenu + endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 2852b6a6522..46ac199649f 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -2,23 +2,182 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) +subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr # Beware that all-y also adds the compilation unit to verstage on PSP -all-y += config.c +all-y += config.c +all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += gpio.c bootblock-y += reset.c +bootblock-y += uart.c +verstage_x86-y += gpio.c verstage_x86-y += reset.c +verstage_x86-y += uart.c +romstage-y += gpio.c romstage-y += reset.c romstage-y += romstage.c +romstage-y += uart.c ramstage-y += chip.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c ramstage-y += reset.c +ramstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) + +MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) + +# ROMSIG Normally At ROMBASE + 0x20000 +# Overridden by CONFIG_AMD_FWM_POSITION_INDEX +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA | | | | +# +-----------+---------------+----------------+------------+ +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + +CEZANNE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +# types = 0x2 +OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos" +endif + + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_68) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +# type = 0x66 + +# type = 0xb - See #55758 (NDA) for bit definitions. +PSP_SOFTFUSE_BITS += 28 + +#hardcode post code to eSPI +PSP_SOFTFUSE_BITS += 15 6 + +# Helper function to return a value with given bit set +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --soc-name "Cezanne" \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(CEZANNE_FWM_POSITION) +apu/amdfw-type := raw + +endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/cezanne/aoac.c b/src/soc/amd/cezanne/aoac.c new file mode 100644 index 00000000000..9c58bb54426 --- /dev/null +++ b/src/soc/amd/cezanne/aoac.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : -1) +#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. The console UART is handled separately from this table. + * + * TODO: Find out which I2C controllers we really need to enable here. + */ +const static unsigned int aoac_devs[] = { + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_ESPI, +}; + +void wait_for_aoac_enabled(unsigned int dev) +{ + while (!is_aoac_device_enabled(dev)) + udelay(100); +} + +void enable_aoac_devices(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); + + /* Wait for AOAC devices to indicate power and clock OK */ + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + wait_for_aoac_enabled(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb new file mode 100644 index 00000000000..49bd0c8b180 --- /dev/null +++ b/src/soc/amd/cezanne/chipset.cb @@ -0,0 +1,5 @@ +chip soc/amd/cezanne + device domain 0 on + device pci 00.0 alias gnb on end + end +end diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 6616d075b98..37ba4c7a1a5 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -4,6 +4,7 @@ #include #include #include +#include /* Before console init */ void fch_pre_init(void) @@ -12,6 +13,16 @@ void fch_pre_init(void) fch_smbus_init(); fch_enable_cf9_io(); fch_enable_legacy_io(); + enable_aoac_devices(); + + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); } /* After console init */ diff --git a/src/soc/amd/cezanne/fsp_params.c b/src/soc/amd/cezanne/fsp_params.c new file mode 100644 index 00000000000..d3f9fcf555a --- /dev/null +++ b/src/soc/amd/cezanne/fsp_params.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ +} diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg new file mode 100644 index 00000000000..189bc9d0d6a --- /dev/null +++ b/src/soc/amd/cezanne/fw.cfg @@ -0,0 +1,38 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP + +# type file +# PSP +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin +PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin + +# BDT +PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/src/soc/amd/cezanne/gpio.c b/src/soc/amd/cezanne/gpio.c new file mode 100644 index 00000000000..d14f8505365 --- /dev/null +++ b/src/soc/amd/cezanne/gpio.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */ +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_7, GEVENT_11 }, + { GPIO_8, GEVENT_23 }, + { GPIO_9, GEVENT_22 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_18, GEVENT_14 }, + { GPIO_21, GEVENT_5 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_15 }, + { GPIO_40, GEVENT_20 }, + { GPIO_84, GEVENT_18 }, + { GPIO_86, GEVENT_9 }, + { GPIO_89, GEVENT_0 }, + { GPIO_90, GEVENT_1 }, + { GPIO_91, GEVENT_6 }, + { GPIO_129, GEVENT_17 }, +}; + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} + +void soc_gpio_hook(uint8_t gpio, uint8_t mux) +{ + /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ + if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) + soc_route_sci(GPIO_2_EVENT); +} diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index b377ee31fb5..20f70371f08 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,14 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +/* FCH AL2AHB Registers */ +#define ALINK_AHB_ADDRESS 0xfedc0000 + +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 + /* MMIO Ranges */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/cezanne/include/soc/pci_devs.h b/src/soc/amd/cezanne/include/soc/pci_devs.h new file mode 100644 index 00000000000..8f5793bbb95 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/pci_devs.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_PCI_DEVS_H +#define AMD_CEZANNE_PCI_DEVS_H + +#include +#include + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) +#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) + +/* PCIe GFX/GPP Bridge device 1 with up to 3 ports */ +#define PCIE_GPP_BRIDGE_1_DEV 0x1 + +#define PCIE_GPP_1_0_FUNC 1 +#define PCIE_GPP_1_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_0_FUNC) +#define SOC_GPP_1_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_0_FUNC) + +#define PCIE_GPP_1_1_FUNC 2 +#define PCIE_GPP_1_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) +#define SOC_GPP_1_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_1_FUNC) + +#define PCIE_GPP_1_2_FUNC 3 +#define PCIE_GPP_1_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) +#define SOC_GPP_1_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_1_DEV, PCIE_GPP_1_2_FUNC) + +/* PCIe GPP Bridge device 2 with up to 7 ports */ +#define PCIE_GPP_BRIDGE_2_DEV 0x2 + +#define PCIE_GPP_2_0_FUNC 1 +#define PCIE_GPP_2_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) +#define SOC_GPP_2_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) + +#define PCIE_GPP_2_1_FUNC 2 +#define PCIE_GPP_2_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) +#define SOC_GPP_2_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) + +#define PCIE_GPP_2_2_FUNC 3 +#define PCIE_GPP_2_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) +#define SOC_GPP_2_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) + +#define PCIE_GPP_2_3_FUNC 4 +#define PCIE_GPP_2_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) +#define SOC_GPP_2_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) + +#define PCIE_GPP_2_4_FUNC 5 +#define PCIE_GPP_2_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) +#define SOC_GPP_2_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) + +#define PCIE_GPP_2_5_FUNC 6 +#define PCIE_GPP_2_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) +#define SOC_GPP_2_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) + +#define PCIE_GPP_2_6_FUNC 7 +#define PCIE_GPP_2_6_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) +#define SOC_GPP_2_6_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_6_FUNC) + +/* PCIe Bridges to Bus A, Bus B and Bus C devices */ +#define PCIE_ABC_BRIDGE_DEV 0x8 + +#define PCIE_ABC_A_FUNC 1 +#define PCIE_ABC_A_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_A_FUNC) +#define SOC_PCIE_ABC_A_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_A_FUNC) + +#define GFX_DEV 0x0 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +#define GFX_HDA_DEV 0x0 +#define GFX_HDA_FUNC 1 +#define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC) + +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) + +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) + +#define AUDIO_DEV 0x0 +#define AUDIO_FUNC 5 +#define AUDIO_DEVFN PCI_DEVFN(AUDIO_DEV, AUDIO_FUNC) + +#define HD_AUDIO_DEV 0x0 +#define HD_AUDIO_FUNC 6 +#define HD_AUDIO_DEVFN PCI_DEVFN(HD_AUDIO_DEV, HD_AUDIO_FUNC) + +#define PCIE_ABC_B_FUNC 2 +#define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) +#define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) + +#define SATA0_DEV 0x0 +#define SATA0_FUNC 0 +#define SATA0_DEVFN PCI_DEVFN(SATA0_DEV, SATA0_FUNC) + +#define SATA1_DEV 0x0 +#define SATA1_FUNC 1 +#define SATA1_DEVFN PCI_DEVFN(SATA1_DEV, SATA1_FUNC) + +#define PCIE_ABC_C_FUNC 3 +#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) + +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + +#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7) +#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7) + +#endif /* AMD_CEZANNE_PCI_DEVS_H */ diff --git a/src/soc/amd/cezanne/include/soc/smi.h b/src/soc/amd/cezanne/include/soc/smi.h new file mode 100644 index 00000000000..dc299a5a95a --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/smi.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_CEZANNE_SMI_H +#define AMD_CEZANNE_SMI_H + +#include + +#define SMI_GEVENTS 24 +#define SCIMAPS 58 +#define SCI_GPES 32 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +/* SMI source and status */ +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_GENINT2_L 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_LPCPME 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_LPCPD 5 +#define SMITYPE_G_SPKR 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_LPC_SMI_L 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO7 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_USBOC2_L 14 +#define SMITYPE_G_USBOC3_L 15 +#define SMITYPE_G_AGPIO23 16 +#define SMITYPE_G_ESPI_RESET_L 17 +#define SMITYPE_G_FANIN0 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO40 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPIO9 22 +#define SMITYPE_G_AGPIO8 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_GENINT2_L) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_LPCPME) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_LPCPD) \ + | (1 << SMITYPE_G_SPKR) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO7) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_USBOC2_L) \ + | (1 << SMITYPE_G_USBOC3_L) \ + | (1 << SMITYPE_G_AGPIO23) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ + | (1 << SMITYPE_G_FANIN0) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO40) \ + | (1 << SMITYPE_G_PWR_BTN_L) \ + | (1 << SMITYPE_G_AGPIO9) \ + | (1 << SMITYPE_G_AGPIO8)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L2 32 +#define SMITYPE_PSP 33 +/* 34,35 Reserved */ +#define SMITYPE_ESPI_SCI_B 36 +#define SMITYPE_WLAN_WLAN_PME 37 +#define SMITYPE_WLAN_BT_PME 38 +#define SMITYPE_AZPME 39 +#define SMITYPE_USB_PD_I2C4 40 +#define SMITYPE_GPIO_CTL 41 +/* 42 Reserved */ +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +/* 59-63 Reserved */ +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +/* 67-71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +/* 145 Reserved */ +#define SMITYPE_ESPI_SMI 146 +/* 147 Reserved */ +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ +#define NUMBER_SMITYPES 160 +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 + +#define SMI_MODE_MASK 0x03 + +#endif /* AMD_CEZANNE_SMI_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 03ee2bb2d19..2a294e96efe 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -8,10 +8,30 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_ACPI_SMI_CMD 0x6a + +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ + +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_I2C4 9 +#define FCH_AOAC_DEV_I2C5 10 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_UART2 16 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_UART3 26 +#define FCH_AOAC_DEV_ESPI 27 /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT (1 << 7) /* Write-once */ +void enable_aoac_devices(void); +void wait_for_aoac_enabled(unsigned int dev); void fch_pre_init(void); void fch_early_init(void); diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h new file mode 100644 index 00000000000..9b99cd4b247 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/uart.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H + +#include + +void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ +void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ + +#endif /* AMD_PICASSO_UART_H */ diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 91074b20125..509addfa521 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,7 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include +#include + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ +} asmlinkage void car_stage_entry(void) { + post_code(0x40); + console_init(); + + post_code(0x41); + + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + fsp_memory_init(false); /* no S3 resume yet */ + + run_ramstage(); } diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c new file mode 100644 index 00000000000..9d10fd0eff7 --- /dev/null +++ b/src/soc/amd/cezanne/uart.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct { + uintptr_t base; + struct soc_amd_gpio mux[2]; +} uart_info[] = { + [0] = { APU_UART0_BASE, { + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + } }, + [1] = { APU_UART1_BASE, { + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), + } }, +}; + +uintptr_t get_uart_base(unsigned int idx) +{ + if (idx >= ARRAY_SIZE(uart_info)) + return 0; + + return uart_info[idx].base; +} + +void clear_uart_legacy_config(void) +{ + write16((void *)FCH_LEGACY_UART_DECODE, 0); +} + +void set_uart_config(unsigned int idx) +{ + if (idx >= ARRAY_SIZE(uart_info)) + return; + + program_gpios(uart_info[idx].mux, 2); +} + +/* Even though this is called enable, it gets called for both enabled and disabled devices. */ +static void uart_enable(struct device *dev) +{ + unsigned int dev_id; + + switch (dev->path.mmio.addr) { + case APU_UART0_BASE: + dev_id = FCH_AOAC_DEV_UART0; + break; + case APU_UART1_BASE: + dev_id = FCH_AOAC_DEV_UART1; + break; + default: + printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); + return; + } + + if (dev->enabled) { + power_on_aoac_device(dev_id); + wait_for_aoac_enabled(dev_id); + } else { + power_off_aoac_device(dev_id); + } +} + +struct device_operations cezanne_uart_mmio_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .enable = uart_enable, +}; diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 9686ddc1c98..df55cbfa47d 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include /* Get pin control MMIO address */ Method (GPAD, 0x1) @@ -117,3 +118,63 @@ Method (GPW3, 0x2) /* Arg1 - Value for control register */ GPSB (Arg0, 3, Arg1) } + +/* + * Set GPIO Output Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 |= GPIO_OUTPUT_VALUE +} + +/* + * Clear GPIO Output Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 &= ~GPIO_OUTPUT_VALUE +} + +/* + * Get GPIO Input Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = (GPIO_INPUT_VALUE & VAL0) >> GPIO_INPUT_SHIFT + + Return (Local0) +} + +/* + * Get GPIO Output Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = (GPIO_OUTPUT_VALUE & VAL0) >> GPIO_OUTPUT_SHIFT + + Return (Local0) +} diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index d2224e8f134..254fc69793d 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -22,6 +22,7 @@ Device(LPCB) { Device(LDRC) // LPC device: Resource consumption { Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources + Name (_UID, 0x3278) Name (CRS, ResourceTemplate () // Current Motherboard resources { Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address @@ -68,6 +69,7 @@ Device(LPCB) { Device(SPKR) { /* Speaker */ Name(_HID,EISAID(IO61_HID)) + Name (_UID, 0x7239) Name(_CRS, ResourceTemplate() { IO(Decode16, 0x0061, 0x0061, 0, 1) }) diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 10e522f0646..c6a4725b859 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -7,4 +7,6 @@ ramstage-y += acpi.c postcar-y += acpi.c smm-y += acpi.c +ramstage-y += pm_state.c + endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 4ca65995368..43cc49ccb00 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -3,12 +3,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include void poweroff(void) { @@ -117,44 +119,6 @@ void acpi_clear_pm_gpe_status(void) acpi_write32(MMIO_ACPI_GPE0_STS, acpi_read32(MMIO_ACPI_GPE0_STS)); } -static int get_index_bit(uint32_t value, uint16_t limit) -{ - uint16_t i; - uint32_t t; - - if (limit >= TOTAL_BITS(uint32_t)) - return -1; - - /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; - if ((value & t) == 0) - return -1; - t = 1; - for (i = 0; i < limit; i++) { - if (value & t) - break; - t <<= 1; - } - return i; -} - -void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state) -{ - int index; - - index = get_index_bit(state->pm1_sts & state->pm1_en, PM1_LIMIT); - if (index < 0) - gnvs->pm1i = ~0ULL; - else - gnvs->pm1i = index; - - index = get_index_bit(state->gpe0_sts & state->gpe0_en, GPE0_LIMIT); - if (index < 0) - gnvs->gpei = ~0ULL; - else - gnvs->gpei = index; -} - int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(acpi_read16(MMIO_ACPI_PM1_CNT_BLK)); diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c new file mode 100644 index 00000000000..ed97afbcf55 --- /dev/null +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static int get_index_bit(uint32_t value, uint16_t limit) +{ + uint16_t i; + uint32_t t; + + if (limit >= TOTAL_BITS(uint32_t)) + return -1; + + /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ + t = (1 << limit) - 1; + if ((value & t) == 0) + return -1; + t = 1; + for (i = 0; i < limit; i++) { + if (value & t) + break; + t <<= 1; + } + return i; +} + +static void pm_fill_gnvs(const struct acpi_pm_gpe_state *state) +{ + int index; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (gnvs == NULL) + return; + + index = get_index_bit(state->pm1_sts & state->pm1_en, PM1_LIMIT); + if (index < 0) + gnvs->pm1i = ~0ULL; + else + gnvs->pm1i = index; + + index = get_index_bit(state->gpe0_sts & state->gpe0_en, GPE0_LIMIT); + if (index < 0) + gnvs->gpei = ~0ULL; + else + gnvs->gpei = index; +} + +static void set_nvs_sws(void *unused) +{ + struct chipset_power_state *state; + + state = acpi_get_pm_state(); + if (state == NULL) + return; + + pm_fill_gnvs(&state->gpe_state); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 3eb76707840..6282d7e5719 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,9 +8,16 @@ ****************************************************************************** */ -#include "gcccar.inc" #include +.section .init + +.code32 + +_cache_as_ram_setup: + +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -43,3 +50,5 @@ before_carstage: post_code(POST_DEAD_CODE) hlt jmp .halt_forever + +_cache_as_ram_setup_end: diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 6fae1ed1cbe..520e3c08b0e 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -2,6 +2,8 @@ #include +.section .init, "ax", @progbits + .global bootblock_resume_entry bootblock_resume_entry: post_code(0xb0) diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 8e340a3147c..bdc243fa2cb 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -147,23 +147,24 @@ void gpio_set(gpio_t gpio_num, int value) void gpio_input_pulldown(gpio_t gpio_num) { - gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLDOWN_ENABLE); + gpio_setbits32(gpio_num, GPIO_PULL_MASK | GPIO_OUTPUT_ENABLE, GPIO_PULLDOWN_ENABLE); } void gpio_input_pullup(gpio_t gpio_num) { - gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLUP_ENABLE); + gpio_setbits32(gpio_num, GPIO_PULL_MASK | GPIO_OUTPUT_ENABLE, GPIO_PULLUP_ENABLE); } void gpio_input(gpio_t gpio_num) { - gpio_and32(gpio_num, ~GPIO_OUTPUT_ENABLE); + gpio_and32(gpio_num, ~(GPIO_PULL_MASK | GPIO_OUTPUT_ENABLE)); } void gpio_output(gpio_t gpio_num, int value) { - gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); + /* set GPIO output value before setting the direction to output to avoid glitches */ gpio_set(gpio_num, value); + gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); } const char *gpio_acpi_path(gpio_t gpio) diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index c6e242adaab..74b8408488b 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -4,7 +4,6 @@ #define AMD_BLOCK_ACPI_H #include -#include /* ACPI MMIO registers 0xfed80800 */ #define MMIO_ACPI_PM1_STS 0x00 @@ -33,8 +32,6 @@ void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state); void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state); /* Clear PM and GPE status registers. */ void acpi_clear_pm_gpe_status(void); -/* Fill GNVS object from PM GPE object. */ -void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state); /* * If a system reset is about to be requested, modify the PM1 register so it diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index b6162d7e7f4..6524d05a54d 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -4,6 +4,7 @@ #define AMD_BLOCK_GPIO_BANKS_H #include +#include "gpio_defs.h" struct soc_amd_gpio { uint8_t gpio; @@ -17,13 +18,6 @@ struct soc_amd_event { uint8_t event; }; -#define GPIO_MASTER_SWITCH 0xFC -#define GPIO_MASK_STS_EN BIT(28) -#define GPIO_INTERRUPT_EN BIT(30) -#define GPIO_WAKE_EN BIT(31) - -#define GPIO_WAKE_STAT_0 0x2F0 -#define GPIO_WAKE_STAT_1 0x2F4 struct gpio_wake_state { uint32_t control_switch; uint32_t wake_stat[2]; @@ -38,59 +32,6 @@ void gpio_fill_wake_state(struct gpio_wake_state *state); /* Add gpio events to the eventlog. */ void gpio_add_events(const struct gpio_wake_state *state); -#define GPIO_PIN_IN (1 << 0) /* for byte access */ -#define GPIO_PIN_OUT (1 << 6) /* for byte access */ - -/* Pad trigger type - Level or Edge */ -#define GPIO_TRIGGER_EDGE (0 << 8) -#define GPIO_TRIGGER_LEVEL (1 << 8) -#define GPIO_TRIGGER_MASK (1 << 8) - -/* - * Pad polarity: - * Level trigger - High or Low - * Edge trigger - High (Rising), Low (Falling), Both - */ -#define GPIO_ACTIVE_HIGH (0 << 9) -#define GPIO_ACTIVE_LOW (1 << 9) -#define GPIO_ACTIVE_BOTH (2 << 9) -#define GPIO_ACTIVE_MASK (3 << 9) - -/* - * Pad trigger and polarity configuration. - * This determines the filtering applied on the input signal at the pad. - */ -#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) -#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) -#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) - -#define GPIO_INT_ENABLE_STATUS (1 << 11) -#define GPIO_INT_ENABLE_DELIVERY (1 << 12) -#define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_INT_ENABLE_MASK (3 << 11) - -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) - -#define GPIO_PIN_STS (1 << 16) -#define GPIO_8KPULLUP_SELECT (1 << 19) -#define GPIO_PULLUP_ENABLE (1 << 20) -#define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (7 << 19) - -#define GPIO_OUTPUT_SHIFT 22 -#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) -#define GPIO_OUTPUT_ENABLE (1 << 23) -#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) - -#define GPIO_INT_STATUS (1 << 28) -#define GPIO_WAKE_STATUS (1 << 29) -#define GPIO_STATUS_MASK (3 << 28) - enum { GEVENT_0, GEVENT_1, @@ -126,39 +67,6 @@ enum { GEVENT_31, }; -#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) -#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE - -#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) -#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE -#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE -#define GPIO_PULL_PULL_NONE 0 - -#define AMD_GPIO_MUX_MASK 0x03 - -/* - * Flags used for GPIO configuration. These provide additional information that does not go - * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. - */ -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) -#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) -#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) -#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) -#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) -#define GPIO_FLAG_SCI (1 << 2) -#define GPIO_FLAG_SMI (1 << 3) - -/* Trigger configuration for GPIO SCI/SMI events. */ -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ - GPIO_FLAG_EVENT_ACTIVE_HIGH) -#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ - GPIO_FLAG_EVENT_ACTIVE_LOW) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ - GPIO_FLAG_EVENT_ACTIVE_HIGH) -#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ - GPIO_FLAG_EVENT_ACTIVE_LOW) - static inline bool is_gpio_event_level_triggered(uint32_t flags) { return (flags & GPIO_FLAG_EVENT_TRIGGER_MASK) == GPIO_FLAG_EVENT_TRIGGER_LEVEL; @@ -179,152 +87,6 @@ static inline bool is_gpio_event_active_low(uint32_t flags) return (flags & GPIO_FLAG_EVENT_ACTIVE_MASK) == GPIO_FLAG_EVENT_ACTIVE_LOW; } -#define DEB_GLITCH_SHIFT 5 -#define DEB_GLITCH_LOW 1 -#define DEB_GLITCH_HIGH 2 -#define DEB_GLITCH_NONE 3 -#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) -#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) -#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) - -#define GPIO_TIMEBASE_61uS 0 -#define GPIO_TIMEBASE_183uS (1 << 4) -#define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) -#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) -#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) -#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) -#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) - -#define GPIO_DEB_MASK 0xff - -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (7 << 13) - -/* - * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` - * Bits that are preserved/untouched: - * - Reserved bits - * - Drive strength bits - * - Read only bits - */ -#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ - GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ - GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) - -/* - * Several macros are available to declare programming of GPIO pins. The defined macros and - * their parameters are: - * PAD_NF Define native alternate function for the pin. - * pin the pin to be programmed - * function the native function - * pull pull up, pull down or no pull - * PAD_GPI The pin is a GPIO input - * pin the pin to be programmed - * pull pull up, pull down or no pull - * PAD_GPO The pin is a GPIO output - * pin the pin to be programmed - * direction high or low - * PAD_INT The pin is regular interrupt that works while booting - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * action STATUS, DELIVER, STATUS_DELIVER - * PAD_SCI The pin is a SCI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH - * PAD_SMI The pin is a SMI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * event trigger LEVEL_LOW, LEVEL_HIGH - * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) - * PAD_DEBOUNCE The input or interrupt will be debounced - * pin the pin to be programmed - * pull pull up, pull down or no pull - * debounce_type preserve low glitch, preserve high glitch, no glitch - * debounce_time the debounce time - */ - -#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ - { \ - .gpio = __pin, \ - .function = __function, \ - .control = __control, \ - .flags = __flags, \ - } - -#define PAD_CFG_STRUCT(__pin, __function, __control) \ - PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) - -#define PAD_PULL(__pull) GPIO_PULL_ ## __pull -#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir -#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig -#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action -#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig -#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake -#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb - -/* Native function pad configuration */ -#define PAD_NF(pin, func, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) - -/* General purpose input pad configuration */ -#define PAD_GPI(pin, pull) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) - -/* General purpose output pad configuration */ -#define PAD_GPO(pin, direction) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) - -/* Legacy interrupt pad configuration */ -#define PAD_INT(pin, pull, trigger, action) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) - -/* SCI pad configuration */ -#define PAD_SCI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ - PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) - -/* SMI pad configuration */ -#define PAD_SMI(pin, pull, trigger) \ - PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ - PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) - -/* WAKE pad configuration */ -#define PAD_WAKE(pin, pull, trigger, type) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) - -/* pin debounce configuration */ -#define PAD_DEBOUNCE(pin, pull, type, time) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ - PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) - -/* No-connect pad - configured as input with PULL_DOWN */ -#define PAD_NC(pin) \ - PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) - typedef uint32_t gpio_t; /* diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h new file mode 100644 index 00000000000..f0c6f660d05 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_GPIO_DEFS_H +#define AMD_BLOCK_GPIO_DEFS_H + +#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASK_STS_EN BIT(28) +#define GPIO_INTERRUPT_EN BIT(30) +#define GPIO_WAKE_EN BIT(31) + +#define GPIO_WAKE_STAT_0 0x2F0 +#define GPIO_WAKE_STAT_1 0x2F4 + +#define GPIO_PIN_IN (1 << 0) /* for byte access */ +#define GPIO_PIN_OUT (1 << 6) /* for byte access */ + +/* Pad trigger type - Level or Edge */ +#define GPIO_TRIGGER_EDGE (0 << 8) +#define GPIO_TRIGGER_LEVEL (1 << 8) +#define GPIO_TRIGGER_MASK (1 << 8) + +/* + * Pad polarity: + * Level trigger - High or Low + * Edge trigger - High (Rising), Low (Falling), Both + */ +#define GPIO_ACTIVE_HIGH (0 << 9) +#define GPIO_ACTIVE_LOW (1 << 9) +#define GPIO_ACTIVE_BOTH (2 << 9) +#define GPIO_ACTIVE_MASK (3 << 9) + +/* + * Pad trigger and polarity configuration. + * This determines the filtering applied on the input signal at the pad. + */ +#define GPIO_TRIGGER_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_TRIGGER_EDGE) +#define GPIO_TRIGGER_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_TRIGGER_LEVEL) +#define GPIO_TRIGGER_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_TRIGGER_LEVEL) + +#define GPIO_INT_ENABLE_STATUS (1 << 11) +#define GPIO_INT_ENABLE_DELIVERY (1 << 12) +#define GPIO_INT_ENABLE_STATUS_DELIVERY \ + (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) +#define GPIO_INT_ENABLE_MASK (3 << 11) + +#define GPIO_S0I3_WAKE_EN (1 << 13) +#define GPIO_S3_WAKE_EN (1 << 14) +#define GPIO_S4_S5_WAKE_EN (1 << 15) + +#define GPIO_PIN_STS (1 << 16) +#define GPIO_8KPULLUP_SELECT (1 << 19) +#define GPIO_PULLUP_ENABLE (1 << 20) +#define GPIO_PULLDOWN_ENABLE (1 << 21) +#define GPIO_PULL_MASK (7 << 19) + +#define GPIO_INPUT_SHIFT 16 +#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) + +#define GPIO_OUTPUT_SHIFT 22 +#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) +#define GPIO_OUTPUT_ENABLE (1 << 23) +#define GPIO_OUTPUT_MASK (3 << GPIO_OUTPUT_SHIFT) + +#define GPIO_INT_STATUS (1 << 28) +#define GPIO_WAKE_STATUS (1 << 29) +#define GPIO_STATUS_MASK (3 << 28) + +#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) +#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE + +#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) +#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE +#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE +#define GPIO_PULL_PULL_NONE 0 + +#define AMD_GPIO_MUX_MASK 0x03 + +/* + * Flags used for GPIO configuration. These provide additional information that does not go + * directly into GPIO control register. These are stored in `flags` field in soc_amd_gpio. + */ +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL (1 << 0) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE (0 << 0) +#define GPIO_FLAG_EVENT_TRIGGER_MASK (1 << 0) +#define GPIO_FLAG_EVENT_ACTIVE_HIGH (1 << 1) +#define GPIO_FLAG_EVENT_ACTIVE_LOW (0 << 1) +#define GPIO_FLAG_EVENT_ACTIVE_MASK (1 << 1) +#define GPIO_FLAG_SCI (1 << 2) +#define GPIO_FLAG_SMI (1 << 3) + +/* Trigger configuration for GPIO SCI/SMI events. */ +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_HIGH (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ + GPIO_FLAG_EVENT_ACTIVE_HIGH) +#define GPIO_FLAG_EVENT_TRIGGER_LEVEL_LOW (GPIO_FLAG_EVENT_TRIGGER_LEVEL | \ + GPIO_FLAG_EVENT_ACTIVE_LOW) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE_HIGH (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ + GPIO_FLAG_EVENT_ACTIVE_HIGH) +#define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ + GPIO_FLAG_EVENT_ACTIVE_LOW) +#define DEB_GLITCH_SHIFT 5 +#define DEB_GLITCH_LOW 1 +#define DEB_GLITCH_HIGH 2 +#define DEB_GLITCH_NONE 3 +#define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) +#define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) +#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) + +#define GPIO_TIMEBASE_61uS 0 +#define GPIO_TIMEBASE_183uS (1 << 4) +#define GPIO_TIMEBASE_15560uS (1 << 7) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ + GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_200uS (3 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_500uS (8 | GPIO_TIMEBASE_61uS) +#define GPIO_DEB_1mS (5 | GPIO_TIMEBASE_183uS) +#define GPIO_DEB_2mS (11 | GPIO_TIMEBASE_183uS) +#define GPIO_DEB_15mS (1 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_50mS (3 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_100mS (6 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_200mS (13 | GPIO_TIMEBASE_15560uS) +#define GPIO_DEB_500mS (8 | GPIO_TIMEBASE_62440uS) + +#define GPIO_DEB_MASK 0xff + +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_MASK (7 << 13) + +/* + * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` + * Bits that are preserved/untouched: + * - Reserved bits + * - Drive strength bits + * - Read only bits + */ +#define PAD_CFG_MASK (GPIO_DEB_MASK | GPIO_TRIGGER_MASK | GPIO_ACTIVE_MASK | \ + GPIO_INT_ENABLE_MASK | GPIO_WAKE_MASK | GPIO_PULL_MASK | \ + GPIO_OUTPUT_MASK | GPIO_STATUS_MASK) + +/* + * Several macros are available to declare programming of GPIO pins. The defined macros and + * their parameters are: + * PAD_NF Define native alternate function for the pin. + * pin the pin to be programmed + * function the native function + * pull pull up, pull down or no pull + * PAD_GPI The pin is a GPIO input + * pin the pin to be programmed + * pull pull up, pull down or no pull + * PAD_GPO The pin is a GPIO output + * pin the pin to be programmed + * direction high or low + * PAD_INT The pin is regular interrupt that works while booting + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * action STATUS, DELIVER, STATUS_DELIVER + * PAD_SCI The pin is a SCI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * event trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH + * PAD_SMI The pin is a SMI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * event trigger LEVEL_LOW, LEVEL_HIGH + * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) + * PAD_DEBOUNCE The input or interrupt will be debounced + * pin the pin to be programmed + * pull pull up, pull down or no pull + * debounce_type preserve low glitch, preserve high glitch, no glitch + * debounce_time the debounce time + */ + +#define PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, __flags) \ + { \ + .gpio = __pin, \ + .function = __function, \ + .control = __control, \ + .flags = __flags, \ + } + +#define PAD_CFG_STRUCT(__pin, __function, __control) \ + PAD_CFG_STRUCT_FLAGS(__pin, __function, __control, 0) + +#define PAD_PULL(__pull) GPIO_PULL_ ## __pull +#define PAD_OUTPUT(__dir) GPIO_OUTPUT_OUT_ ## __dir +#define PAD_TRIGGER(__trig) GPIO_TRIGGER_ ## __trig +#define PAD_INT_ENABLE(__action) GPIO_INT_ENABLE_ ## __action +#define PAD_FLAG_EVENT_TRIGGER(__trig) GPIO_FLAG_EVENT_TRIGGER_ ## __trig +#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake +#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb + +/* Native function pad configuration */ +#define PAD_NF(pin, func, pull) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull)) + +/* General purpose input pad configuration */ +#define PAD_GPI(pin, pull) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull)) + +/* General purpose output pad configuration */ +#define PAD_GPO(pin, direction) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_OUTPUT(direction)) + +/* Legacy interrupt pad configuration */ +#define PAD_INT(pin, pull, trigger, action) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_INT_ENABLE(action)) + +/* SCI pad configuration */ +#define PAD_SCI(pin, pull, trigger) \ + PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ + PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SCI) + +/* SMI pad configuration */ +#define PAD_SMI(pin, pull, trigger) \ + PAD_CFG_STRUCT_FLAGS(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(LEVEL_HIGH), \ + PAD_FLAG_EVENT_TRIGGER(trigger) | GPIO_FLAG_SMI) + +/* WAKE pad configuration */ +#define PAD_WAKE(pin, pull, trigger, type) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_TRIGGER(trigger) | PAD_WAKE_ENABLE(type)) + +/* pin debounce configuration */ +#define PAD_DEBOUNCE(pin, pull, type, time) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, \ + PAD_PULL(pull) | PAD_DEBOUNCE_CONFIG(type) | PAD_DEBOUNCE_CONFIG(time)) + +/* No-connect pad - configured as input with PULL_DOWN */ +#define PAD_NC(pin) \ + PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(PULL_DOWN)) + +#endif /* AMD_BLOCK_GPIO_DEFS_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/uart.h b/src/soc/amd/common/block/include/amdblocks/uart.h new file mode 100644 index 00000000000..95d73237f76 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/uart.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_UART_H +#define AMD_BLOCK_UART_H + +#include + +uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ + +#endif /* AMD_BLOCK_UART_H */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 107aa4af23b..8a7dc34c6c0 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -19,7 +19,6 @@ #include #include #include -#include #include /* Most systems should have already enabled the bridge */ @@ -100,7 +99,6 @@ static void lpc_init(struct device *dev) static void lpc_read_resources(struct device *dev) { struct resource *res; - struct global_nvs *gnvs; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -134,10 +132,6 @@ static void lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); - - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs); } static void lpc_set_resources(struct device *dev) @@ -328,7 +322,6 @@ static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 363a0abb7c3..907f0ef1476 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) -bootblock-y += psp.c romstage-y += psp.c ramstage-y += psp.c smm-y += psp.c @@ -10,7 +9,6 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) -bootblock-y += psp_gen1.c romstage-y += psp_gen1.c ramstage-y += psp_gen1.c smm-y += psp_gen1.c @@ -19,7 +17,6 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1 ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) -bootblock-y += psp_gen2.c romstage-y += psp_gen2.c ramstage-y += psp_gen2.c smm-y += psp_gen2.c diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 28e662c6505..80a11848f57 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -21,15 +21,13 @@ static void sm_init(struct device *dev) static u32 get_sm_mmio(struct device *dev) { - struct resource *res; - struct bus *pbus; - - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); - if (res->base == SMB_BASE_ADDR) - return (uintptr_t)acpimmio_smbus; - - return (uintptr_t)acpimmio_asf; + /* + * Since SMBus and ASF controller are behind the same PCIe device, we don't know behind + * which controller a device is. We assume here that the devices are behind the SMBus + * controller. The proper solution would be to handle those as MMIO devices instead of + * PCI ones. + */ + return (uintptr_t)acpimmio_smbus; } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index d63f585d9b4..19a4e32e307 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -49,7 +49,7 @@ void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) /* SMI0 source is GEVENT0 and so on */ configure_smi(gevent, mode); - /* And set set the trigger level */ + /* And set the trigger level */ reg32 = smi_read32(SMI_REG_SMITRIG0); reg32 &= ~(1 << gevent); reg32 |= (level & 0x1) << gevent; diff --git a/src/soc/amd/common/block/uart/Kconfig b/src/soc/amd/common/block/uart/Kconfig index 599594ba5e2..c117dccc1a6 100644 --- a/src/soc/amd/common/block/uart/Kconfig +++ b/src/soc/amd/common/block/uart/Kconfig @@ -14,44 +14,5 @@ config AMD_SOC_CONSOLE_UART select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO select UART_OVERRIDE_REFCLK - help - There are four memory-mapped UARTs controllers at: - 0: 0xfedc9000 - 1: 0xfedca000 - 2: 0xfedc3000 - 3: 0xfedcf000 - -choice - prompt "UART Frequency" - depends on AMD_SOC_CONSOLE_UART - default AMD_SOC_UART_48MZ - -config AMD_SOC_UART_48MZ - bool "48 MHz clock" - help - Select this option for the most compatibility. - -config AMD_SOC_UART_1_8MZ - bool "1.8432 MHz clock" - help - Select this option if an old payload or Linux ttyS0 arguments require - a 1.8432 MHz clock source for the UART. - -endchoice - -config AMD_SOC_UART_LEGACY - bool "Decode legacy I/O range" - help - Assign I/O 3F8, 2F8, etc. to an integrated AMD SoC UART. A UART - accessed with I/O does not allow all the features of MMIO. The MMIO - decode is still present when this option is used. - -config CONSOLE_UART_BASE_ADDRESS - depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART - hex - default 0xfedc9000 if UART_FOR_CONSOLE = 0 - default 0xfedca000 if UART_FOR_CONSOLE = 1 - default 0xfedc3000 if UART_FOR_CONSOLE = 2 - default 0xfedcf000 if UART_FOR_CONSOLE = 3 endif # SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/common/block/uart/Makefile.inc b/src/soc/amd/common/block/uart/Makefile.inc index 9d968455dd2..664c5201809 100644 --- a/src/soc/amd/common/block/uart/Makefile.inc +++ b/src/soc/amd/common/block/uart/Makefile.inc @@ -1,12 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) -bootblock-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c - -romstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c - -verstage_x86-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c - -ramstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c +all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c diff --git a/src/soc/amd/common/block/uart/uart_console.c b/src/soc/amd/common/block/uart/uart_console.c index c1c17232fb0..9f37190d240 100644 --- a/src/soc/amd/common/block/uart/uart_console.c +++ b/src/soc/amd/common/block/uart/uart_console.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include /* * uart_platform_base and uart_platform_refclk are used by the console UART driver and need to @@ -15,5 +15,5 @@ uintptr_t uart_platform_base(unsigned int idx) unsigned int uart_platform_refclk(void) { - return CONFIG(AMD_SOC_UART_48MZ) ? 48000000 : 115200 * 16; + return 48000000; } diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e9930e9998e..da3903bfbde 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -17,13 +17,14 @@ config CPU_SPECIFIC_OPTIONS select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI select GENERIC_GPIO_LIB select IDT_IN_EVERY_STAGE select IOAPIC + select HAVE_ACPI_TABLES select HAVE_EM100_SUPPORT - select HAVE_USBDEBUG_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_NONCAR @@ -57,7 +58,7 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS - select ACPI_NO_SMI_GNVS + select NO_CBFS_MCACHE if VBOOT_STARTS_BEFORE_BOOTBLOCK config FSP_M_FILE string "FSP-M (memory init) binary path and filename" @@ -239,10 +240,6 @@ config HEAP_SIZE hex default 0xc0000 -config EHCI_BAR - hex - default 0xfef00000 - config PICASSO_FCH_IOAPIC_ID hex default 0x8 @@ -274,6 +271,14 @@ config PICASSO_ACPI_IO_BASE help Base address for the ACPI registers. +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART + hex + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + default 0xfedc3000 if UART_FOR_CONSOLE = 2 + default 0xfedcf000 if UART_FOR_CONSOLE = 3 + config SMM_TSEG_SIZE hex default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index a0f3ec49a25..8631dfd6b07 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -226,7 +226,6 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_LOAD_MP2_FW) \ $(OPT_PSP_LOAD_S0I3_FW) \ $(OPT_WHITELIST_FILE) \ - $(OPT_SEC_DEBUG_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ --combo-capable \ @@ -249,7 +248,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB0_NV_SIZE) \ $(OPT_APOB0_NV_BASE) \ diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 9ee29551d43..69982f5dc68 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -46,9 +46,6 @@ static void init(struct device *dev) /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable); - - if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) - sb_clk_output_48Mhz(); /* Internal connection to I2S */ } static const char *acp_acpi_name(const struct device *dev) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 17940e97259..ed2be4845c3 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -12,9 +12,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -393,20 +393,8 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_write_hpet(device, current, rsdp); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { - /* Clear out GNVS. */ - memset(gnvs, 0, sizeof(*gnvs)); - - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; @@ -415,120 +403,49 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } -} - -static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) -{ - /* - * Store (\_SB.GPR2 (addr), Local5) - * \_SB.GPR2 is used to read control byte 2 from control register. - * / It is defined in gpio_lib.asl. - */ - acpigen_write_store(); - acpigen_emit_namestring("\\_SB.GPR2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); -} - -static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) { if (gpio_num >= SOC_GPIO_TOTAL_PINS) { printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } - uintptr_t addr = gpio_get_address(gpio_num); - - acpigen_soc_get_gpio_in_local5(addr); - - /* If (And (Local5, mask)) */ - acpigen_write_if_and(LOCAL5_OP, mask); - - /* Store (One, Local0) */ - acpigen_write_store_ops(ONE_OP, LOCAL0_OP); - - acpigen_pop_len(); /* If */ - - /* Else */ - acpigen_write_else(); - - /* Store (Zero, Local0) */ - acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); - - acpigen_pop_len(); /* Else */ - + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); return 0; } -static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) { if (gpio_num >= SOC_GPIO_TOTAL_PINS) { printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } - uintptr_t addr = gpio_get_address(gpio_num); - - /* Store (0x40, Local0) */ + /* Store (op (gpio_num), Local0) */ acpigen_write_store(); - acpigen_write_integer(GPIO_PIN_OUT); + acpigen_soc_gpio_op(op, gpio_num); acpigen_emit_byte(LOCAL0_OP); - - acpigen_soc_get_gpio_in_local5(addr); - - if (val) { - /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); - } else { - /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(LOCAL0_OP, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * SB.GPW2 (addr, Local5) - * \_SB.GPW2 is used to write control byte in control register - * / byte 2. It is defined in gpio_lib.asl. - */ - acpigen_emit_namestring("\\_SB.GPW2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - return 0; } int acpigen_soc_read_rx_gpio(unsigned int gpio_num) { - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); + return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num); } int acpigen_soc_get_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); + return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num); } int acpigen_soc_set_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_set_gpio_val(gpio_num, 1); + return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num); } int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_set_gpio_val(gpio_num, 0); + return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num); } diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 461b78cabc8..d7523dfe235 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include - -#define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \ - PowerResource(DEV_NAME, SX, 0) { \ +#define AOAC_DEVICE(DEV_ID, SX) \ + PowerResource(AOAC, SX, 0) { \ OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \ Field (AOAC, ByteAcc, NoLock, Preserve) { \ /* \ @@ -67,8 +65,6 @@ } \ Method(_STA) { \ Local0 = (PRBS && RCOS && RBS) \ -\ - Printf("AOAC.%s._STA: %o", #DEV_NAME, Local0) \ \ If (Local0) { \ Return (1) \ @@ -77,34 +73,22 @@ } \ } \ Method(_ON, 0, Serialized) { \ - Printf("AOAC.%s._ON", #DEV_NAME) \ -\ ISWC=0 \ POD=1 \ \ While (!PRBS || !RCOS || !RBS) { \ - Printf ("Waiting for device to power on") \ Stall (100) \ } \ -\ - Printf("Done waiting") \ } \ Method(_OFF, 0, Serialized) { \ - Printf("AOAC.%s._OFF", #DEV_NAME) \ -\ ISWC=0 \ POD=0 \ \ While (PRBS || RCOS || RBS) { \ - Printf ("Waiting for device to power off") \ Stall (100) \ } \ -\ - Printf("Done waiting") \ } \ Method(_RST, 0, Serialized) { \ - Printf("AOAC.%s._RST", #DEV_NAME) \ -\ ISWC=1 \ SRB=1 \ \ @@ -119,28 +103,13 @@ Stall (100) \ } \ } \ + } \ + Name (_PR0, Package () { AOAC }) \ + Name (_PR2, Package () { AOAC }) \ + Name (_PR3, Package () { AOAC }) \ + Method (_PS0, 0, Serialized) { \ + ^AOAC.TDS = 1 \ + } \ + Method (_PS3, 0, Serialized) { \ + ^AOAC.TDS = 3 \ } - - -Device (AOAC) { - Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources - - Method (_STA, 0x0, NotSerialized) - { - /* - * This case is used to indicate a valid device for which no - * device driver should be loaded (for example, a bridge - * device.) Children of this device may be present and valid. - * OSPM should continue enumeration below a device whose _STA - * returns this bit combination. - */ - Return (0x08) - } - - AOAC_DEVICE(I2C2, 7, 0) - AOAC_DEVICE(I2C3, 8, 0) - AOAC_DEVICE(FUR0, 11, 0) - AOAC_DEVICE(FUR1, 12, 0) - AOAC_DEVICE(FUR2, 16, 0) - AOAC_DEVICE(FUR3, 26, 0) -} diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index a81d3b27bee..f6e198f5f2b 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -26,18 +26,6 @@ Name(PR0, Package(){ Package() { 0x0000FFFF, 0, INTC, 0 }, Package() { 0x0000FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridges */ - Package() { 0x0001FFFF, 0, INTA, 0 }, - Package() { 0x0001FFFF, 1, INTB, 0 }, - Package() { 0x0001FFFF, 2, INTC, 0 }, - Package() { 0x0001FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 0x08 - F[1:PCI Bridge to Bus A, 2: PCI Bridge to Bus B] */ - Package() { 0x0008FFFF, 0, INTA, 0 }, - Package() { 0x0008FFFF, 1, INTB, 0 }, - Package() { 0x0008FFFF, 2, INTC, 0 }, - Package() { 0x0008FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 0x14 - F[0:SMBus 3:LPC] */ Package() { 0x0014FFFF, 0, INTA, 0 }, Package() { 0x0014FFFF, 1, INTB, 0 }, diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 8114c520431..0a6dec89069 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -20,10 +20,10 @@ } }) -#define PCI_LINK(DEV_NAME, PIC_REG, APIC_REG) \ +#define PCI_LINK(DEV_NAME, PIC_REG, APIC_REG, UID) \ Device(DEV_NAME) { \ Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, 1) \ + Name(_UID, UID) \ \ Method(_STA, 0) { \ If (PMOD) { \ @@ -100,7 +100,11 @@ } \ } -PCI_LINK(INTA, PIRA, IORA) -PCI_LINK(INTB, PIRB, IORB) -PCI_LINK(INTC, PIRC, IORC) -PCI_LINK(INTD, PIRD, IORD) +PCI_LINK(INTA, PIRA, IORA, 0) +PCI_LINK(INTB, PIRB, IORB, 1) +PCI_LINK(INTC, PIRC, IORC, 2) +PCI_LINK(INTD, PIRD, IORD, 3) +PCI_LINK(INTE, PIRE, IORE, 4) +PCI_LINK(INTF, PIRF, IORF, 5) +PCI_LINK(INTG, PIRG, IORG, 6) +PCI_LINK(INTH, PIRH, IORH, 7) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index c4dffed8afc..895abfd70ce 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -3,6 +3,7 @@ #include #include #include +#include Device (AAHB) { @@ -123,17 +124,7 @@ Device (FUR0) } } - Name (_PR0, Package () { \_SB.AOAC.FUR0 }) - Name (_PR2, Package () { \_SB.AOAC.FUR0 }) - Name (_PR3, Package () { \_SB.AOAC.FUR0 }) - Method (_PS0, 0, Serialized) { - Printf("FUR0._PS0") - \_SB.AOAC.FUR0.TDS = 1 - } - Method (_PS3, 0, Serialized) { - Printf("FUR0._PS3") - \_SB.AOAC.FUR0.TDS = 3 - } + AOAC_DEVICE(11, 0) } Device (FUR1) { @@ -166,17 +157,7 @@ Device (FUR1) { } } - Name (_PR0, Package () { \_SB.AOAC.FUR1 }) - Name (_PR2, Package () { \_SB.AOAC.FUR1 }) - Name (_PR3, Package () { \_SB.AOAC.FUR1 }) - Method (_PS0, 0, Serialized) { - Printf("FUR1._PS0") - \_SB.AOAC.FUR1.TDS = 1 - } - Method (_PS3, 0, Serialized) { - Printf("FUR1._PS3") - \_SB.AOAC.FUR1.TDS = 3 - } + AOAC_DEVICE(12, 0) } Device (FUR2) { @@ -209,17 +190,7 @@ Device (FUR2) { } } - Name (_PR0, Package () { \_SB.AOAC.FUR2 }) - Name (_PR2, Package () { \_SB.AOAC.FUR2 }) - Name (_PR3, Package () { \_SB.AOAC.FUR2 }) - Method (_PS0, 0, Serialized) { - Printf("FUR2._PS0") - \_SB.AOAC.FUR2.TDS = 1 - } - Method (_PS3, 0, Serialized) { - Printf("FUR2._PS3") - \_SB.AOAC.FUR2.TDS = 3 - } + AOAC_DEVICE(16, 0) } Device (FUR3) { @@ -252,17 +223,7 @@ Device (FUR3) { } } - Name (_PR0, Package () { \_SB.AOAC.FUR3 }) - Name (_PR2, Package () { \_SB.AOAC.FUR3 }) - Name (_PR3, Package () { \_SB.AOAC.FUR3 }) - Method (_PS0, 0, Serialized) { - Printf("FUR3._PS0") - \_SB.AOAC.FUR3.TDS = 1 - } - Method (_PS3, 0, Serialized) { - Printf("FUR3._PS3") - \_SB.AOAC.FUR3.TDS = 3 - } + AOAC_DEVICE(26, 0) } Device (I2C2) { @@ -298,17 +259,7 @@ Device (I2C2) { Return (0x0F) } - Name (_PR0, Package () { \_SB.AOAC.I2C2 }) - Name (_PR2, Package () { \_SB.AOAC.I2C2 }) - Name (_PR3, Package () { \_SB.AOAC.I2C2 }) - Method (_PS0, 0, Serialized) { - Printf("I2C2._PS0") - \_SB.AOAC.I2C2.TDS = 1 - } - Method (_PS3, 0, Serialized) { - Printf("I2C2._PS3") - \_SB.AOAC.I2C2.TDS = 3 - } + AOAC_DEVICE(7, 0) } Device (I2C3) @@ -344,17 +295,7 @@ Device (I2C3) Return (0x0F) } - Name (_PR0, Package () { \_SB.AOAC.I2C3 }) - Name (_PR2, Package () { \_SB.AOAC.I2C3 }) - Name (_PR3, Package () { \_SB.AOAC.I2C3 }) - Method (_PS0, 0, Serialized) { - Printf("I2C3._PS0") - \_SB.AOAC.I2C3.TDS = 1 - } - Method (_PS3, 0, Serialized) { - Printf("I2C3._PS3") - \_SB.AOAC.I2C3.TDS = 3 - } + AOAC_DEVICE(8, 0) } Device (MISC) diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index ec9924bd26c..23d10ff0395 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1,14 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include +#include +#include #include #include #include #include #include #include +#include +#include #include #include #include @@ -493,14 +498,539 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) return acpi_fill_ivrs11(current, ivrs); } +static unsigned long gen_crat_hsa_entry(struct acpi_crat_header *crat, unsigned long current) +{ + struct crat_hsa_processing_unit *hsa_entry = (struct crat_hsa_processing_unit *)current; + memset(hsa_entry, 0, sizeof(struct crat_hsa_processing_unit)); + + hsa_entry->flags = CRAT_HSA_PR_FLAG_EN | CRAT_HSA_PR_FLAG_CPU_PRES; + hsa_entry->wave_front_size = 4; + hsa_entry->num_cpu_cores = get_cpu_count(); + hsa_entry->length = sizeof(struct crat_hsa_processing_unit); + crat->total_entries++; + + current += hsa_entry->length; + return current; +} + +static unsigned long create_crat_memory_entry(uint32_t domain, uint64_t region_base, + uint64_t region_size, unsigned long current) +{ + struct crat_memory *mem_affinity = (struct crat_memory *)current; + memset(mem_affinity, 0, sizeof(struct crat_memory)); + + mem_affinity->type = CRAT_MEMORY_TYPE; + mem_affinity->length = sizeof(struct crat_memory); + mem_affinity->proximity_domain = 0; + mem_affinity->base_address_low = region_base & 0xffffffff; + mem_affinity->base_address_high = (region_base >> 32) & 0xffffffff; + mem_affinity->length_low = region_size & 0xffffffff; + mem_affinity->length_high = (region_size >> 32) & 0xffffffff; + mem_affinity->flags = CRAT_MEM_FLAG_EN; + mem_affinity->width = 64; + + current += mem_affinity->length; + return current; +} + +static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, + unsigned long current) +{ + uint32_t dram_base_reg, dram_limit_reg, dram_hole_ctl; + uint64_t memory_length, memory_base, hole_base, size_below_hole; + size_t new_entries = 0; + + for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG; + dram_map_idx++) { + dram_base_reg = + data_fabric_read_reg32(0, DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); + + if (dram_base_reg & DRAM_BASE_REG_VALID) { + dram_limit_reg = data_fabric_read_reg32(0, DF_DRAM_LIMIT(dram_map_idx), + IOMS0_FABRIC_ID); + memory_length = + ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 + - ((dram_base_reg & DRAM_BASE_ADDR) >> DRAM_BASE_ADDR_SHFT); + memory_length = memory_length << 28; + memory_base = (dram_base_reg & DRAM_BASE_ADDR) + << (28 - DRAM_BASE_ADDR_SHFT); + + if (memory_base == 0) { + current = + create_crat_memory_entry(0, 0ull, 0xa0000ull, current); + memory_base = (1 * 1024 * 1024); + memory_length = memory_base; + new_entries++; + } + + if (dram_base_reg & DRAM_BASE_HOLE_EN) { + dram_hole_ctl = data_fabric_read_reg32(0, D18F0_DRAM_HOLE_CTL, + IOMS0_FABRIC_ID); + hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); + size_below_hole = hole_base - memory_base; + current = create_crat_memory_entry(0, memory_base, + size_below_hole, current); + memory_length = (((dram_limit_reg & DRAM_LIMIT_ADDR) + >> DRAM_LIMIT_ADDR_SHFT) + + 1 - 0x10) + << 28; + memory_base = 0x100000000; + new_entries++; + } + + current = create_crat_memory_entry(0, memory_base, memory_length, + current); + new_entries++; + } + } + crat->total_entries += new_entries; + return current; +} + +static unsigned long add_crat_cache_entry(struct crat_cache **cache_affinity, + unsigned long current) +{ + *cache_affinity = (struct crat_cache *)current; + memset(*cache_affinity, 0, sizeof(struct crat_cache)); + + (*cache_affinity)->type = CRAT_CACHE_TYPE; + (*cache_affinity)->length = sizeof(struct crat_cache); + (*cache_affinity)->flags = CRAT_CACHE_FLAG_EN | CRAT_CACHE_FLAG_CPU_CACHE; + + current += sizeof(struct crat_cache); + return current; +} + +static uint8_t get_associativity(uint32_t encoded_associativity) +{ + uint8_t associativity = 0; + + switch (encoded_associativity) { + case 0: + case 1: + case 2: + case 3: + case 4: + return encoded_associativity; + case 5: + associativity = 6; + break; + case 6: + associativity = 8; + break; + case 8: + associativity = 16; + break; + case 0xA: + associativity = 32; + break; + case 0xB: + associativity = 48; + break; + case 0xC: + associativity = 64; + break; + case 0xD: + associativity = 96; + break; + case 0xE: + associativity = 128; + break; + case 0xF: + associativity = 0xFF; + break; + default: + return 0; + } + + return associativity; +} + +static unsigned long gen_crat_cache_entry(struct acpi_crat_header *crat, unsigned long current) +{ + size_t total_num_threads, num_threads_sharing0, num_threads_sharing1, + num_threads_sharing2, num_threads_sharing3, thread, new_entries; + struct cpuid_result cache_props0, cache_props1, cache_props2, cache_props3; + uint8_t sibling_mask = 0; + uint32_t l1_data_cache_ids, l1_inst_cache_ids, l2_cache_ids, l3_cache_ids; + struct crat_cache *cache_affinity = NULL; + + total_num_threads = get_cpu_count(); + + cache_props0 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_0); + cache_props1 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_1); + cache_props2 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_2); + cache_props3 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_3); + + l1_data_cache_ids = cpuid_ecx(CPUID_L1_TLB_CACHE_IDS); + l1_inst_cache_ids = cpuid_edx(CPUID_L1_TLB_CACHE_IDS); + l2_cache_ids = cpuid_ecx(CPUID_L2_L3_CACHE_L2_TLB_IDS); + l3_cache_ids = cpuid_edx(CPUID_L2_L3_CACHE_L2_TLB_IDS); + + num_threads_sharing0 = + ((cache_props0.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing1 = + ((cache_props1.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing2 = + ((cache_props2.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing3 = + ((cache_props3.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + + new_entries = 0; + for (thread = 0; thread < total_num_threads; thread++) { + /* L1 data cache */ + if (thread % num_threads_sharing0 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= CRAT_CACHE_FLAG_DATA_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing0; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props0.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + (l1_data_cache_ids & L1_DC_SIZE_MASK) >> L1_DC_SIZE_SHFT; + cache_affinity->cache_level = CRAT_L1_CACHE; + cache_affinity->lines_per_tag = + (l1_data_cache_ids & L1_DC_LINE_TAG_MASK) + >> L1_DC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l1_data_cache_ids & L1_DC_LINE_SIZE_MASK) + >> L1_DC_LINE_SIZE_SHFT; + cache_affinity->associativity = + (l1_data_cache_ids & L1_DC_ASSOC_MASK) >> L1_DC_ASSOC_SHFT; + cache_affinity->cache_latency = 1; + } + + /* L1 instruction cache */ + if (thread % num_threads_sharing1 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= CRAT_CACHE_FLAG_INSTR_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing1; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props1.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + (l1_inst_cache_ids & L1_IC_SIZE_MASK) >> L1_IC_SIZE_SHFT; + cache_affinity->cache_level = CRAT_L1_CACHE; + cache_affinity->lines_per_tag = + (l1_inst_cache_ids & L1_IC_LINE_TAG_MASK) + >> L1_IC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l1_inst_cache_ids & L1_IC_LINE_SIZE_MASK) + >> L1_IC_LINE_SIZE_SHFT; + cache_affinity->associativity = + (l1_inst_cache_ids & L1_IC_ASSOC_MASK) >> L1_IC_ASSOC_SHFT; + cache_affinity->cache_latency = 1; + } + + /* L2 cache */ + if (thread % num_threads_sharing2 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= + CRAT_CACHE_FLAG_DATA_CACHE | CRAT_CACHE_FLAG_INSTR_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props2.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + (l2_cache_ids & L2_DC_SIZE_MASK) >> L2_DC_SIZE_SHFT; + cache_affinity->cache_level = CRAT_L2_CACHE; + cache_affinity->lines_per_tag = + (l2_cache_ids & L2_DC_LINE_TAG_MASK) >> L2_DC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l2_cache_ids & L2_DC_LINE_SIZE_MASK) >> L2_DC_LINE_SIZE_SHFT; + cache_affinity->associativity = get_associativity( + (l2_cache_ids & L2_DC_ASSOC_MASK) >> L2_DC_ASSOC_SHFT); + cache_affinity->cache_latency = 1; + } + + /* L3 cache */ + if (thread % num_threads_sharing3 == 0) { + current = add_crat_cache_entry(&cache_affinity, current); + new_entries++; + + cache_affinity->flags |= + CRAT_CACHE_FLAG_DATA_CACHE | CRAT_CACHE_FLAG_INSTR_CACHE; + cache_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing3; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + cache_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + cache_affinity->cache_properties = + (cache_props0.edx & CACHE_INCLUSIVE_MASK) ? 2 : 0; + cache_affinity->cache_size = + ((l3_cache_ids & L3_DC_SIZE_MASK) >> L3_DC_SIZE_SHFT) * 512; + cache_affinity->cache_level = CRAT_L3_CACHE; + cache_affinity->lines_per_tag = + (l3_cache_ids & L3_DC_LINE_TAG_MASK) >> L3_DC_LINE_TAG_SHFT; + cache_affinity->cache_line_size = + (l3_cache_ids & L3_DC_LINE_SIZE_MASK) >> L3_DC_LINE_SIZE_SHFT; + cache_affinity->associativity = get_associativity( + (l3_cache_ids & L3_DC_ASSOC_MASK) >> L3_DC_ASSOC_SHFT); + cache_affinity->cache_latency = 1; + } + } + crat->total_entries += new_entries; + return current; +} + +static uint8_t get_tlb_size(enum tlb_type type, struct crat_tlb *crat_tlb_entry, + uint16_t raw_assoc_size) +{ + uint8_t tlbsize; + + if (raw_assoc_size >= 256) { + tlbsize = (uint8_t)(raw_assoc_size / 256); + + if (type == tlb_2m) + crat_tlb_entry->flags |= CRAT_TLB_FLAG_2MB_BASE_256; + else if (type == tlb_4k) + crat_tlb_entry->flags |= CRAT_TLB_FLAG_4K_BASE_256; + else if (type == tlb_1g) + crat_tlb_entry->flags |= CRAT_TLB_FLAG_1GB_BASE_256; + } else { + tlbsize = (uint8_t)(raw_assoc_size); + } + return tlbsize; +} + +static unsigned long add_crat_tlb_entry(struct crat_tlb **tlb_affinity, unsigned long current) +{ + *tlb_affinity = (struct crat_tlb *)current; + memset(*tlb_affinity, 0, sizeof(struct crat_tlb)); + + (*tlb_affinity)->type = CRAT_TLB_TYPE; + (*tlb_affinity)->length = sizeof(struct crat_tlb); + (*tlb_affinity)->flags = CRAT_TLB_FLAG_EN | CRAT_TLB_FLAG_CPU_TLB; + + current += sizeof(struct crat_tlb); + return current; +} + +static unsigned long gen_crat_tlb_entry(struct acpi_crat_header *crat, unsigned long current) +{ + size_t total_num_threads, num_threads_sharing0, num_threads_sharing1, + num_threads_sharing2, thread, new_entries; + struct cpuid_result cache_props0, cache_props1, cache_props2; + uint8_t sibling_mask = 0; + uint32_t l1_tlb_2M4M_ids, l1_tlb_4K_ids, l2_tlb_2M4M_ids, l2_tlb_4K_ids, l1_tlb_1G_ids, + l2_tlb_1G_ids; + struct crat_tlb *tlb_affinity = NULL; + + total_num_threads = get_cpu_count(); + cache_props0 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_0); + cache_props1 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_1); + cache_props2 = cpuid_ext(CPUID_CACHE_PROPS, CACHE_PROPS_2); + + l1_tlb_2M4M_ids = cpuid_eax(CPUID_L1_TLB_CACHE_IDS); + l2_tlb_2M4M_ids = cpuid_eax(CPUID_L2_L3_CACHE_L2_TLB_IDS); + l1_tlb_4K_ids = cpuid_ebx(CPUID_L1_TLB_CACHE_IDS); + l2_tlb_4K_ids = cpuid_ebx(CPUID_L2_L3_CACHE_L2_TLB_IDS); + l1_tlb_1G_ids = cpuid_eax(CPUID_TLB_L1L2_1G_IDS); + l2_tlb_1G_ids = cpuid_ebx(CPUID_TLB_L1L2_1G_IDS); + + num_threads_sharing0 = + ((cache_props0.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing1 = + ((cache_props1.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + num_threads_sharing2 = + ((cache_props2.eax & NUM_SHARE_CACHE_MASK) >> NUM_SHARE_CACHE_SHFT) + 1; + + new_entries = 0; + for (thread = 0; thread < total_num_threads; thread++) { + + /* L1 data TLB */ + if (thread % num_threads_sharing0 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_DATA_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing0; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L1_CACHE; + + tlb_affinity->data_tlb_2mb_assoc = + (l1_tlb_2M4M_ids & L1_DAT_TLB_2M4M_ASSOC_MASK) + >> L1_DAT_TLB_2M4M_ASSOC_SHFT; + tlb_affinity->data_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l1_tlb_2M4M_ids & L1_DAT_TLB_2M4M_SIZE_MASK) + >> L1_DAT_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->data_tlb_4k_assoc = + (l1_tlb_4K_ids & L1_DAT_TLB_4K_ASSOC_MASK) + >> L1_DAT_TLB_4K_ASSOC_SHFT; + tlb_affinity->data_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l1_tlb_4K_ids & L1_DAT_TLB_4K_SIZE_MASK) + >> L1_DAT_TLB_4K_SIZE_SHFT); + + tlb_affinity->data_tlb_1g_assoc = + (l1_tlb_1G_ids & L1_DAT_TLB_1G_ASSOC_MASK) + >> L1_DAT_TLB_1G_ASSOC_SHFT; + tlb_affinity->data_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l1_tlb_1G_ids & L1_DAT_TLB_1G_SIZE_MASK) + >> L1_DAT_TLB_1G_SIZE_SHFT); + } + + /* L1 instruction TLB */ + if (thread % num_threads_sharing1 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_INSTR_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing1; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L1_CACHE; + tlb_affinity->instr_tlb_2mb_assoc = + (l1_tlb_2M4M_ids & L1_INST_TLB_2M4M_ASSOC_MASK) + >> L1_INST_TLB_2M4M_ASSOC_SHFT; + tlb_affinity->instr_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l1_tlb_2M4M_ids & L1_INST_TLB_2M4M_SIZE_MASK) + >> L1_INST_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->instr_tlb_4k_assoc = + (l1_tlb_4K_ids & L1_INST_TLB_4K_ASSOC_MASK) + >> L1_INST_TLB_4K_ASSOC_SHFT; + tlb_affinity->instr_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l1_tlb_4K_ids & L1_INST_TLB_4K_SIZE_MASK) + >> L1_INST_TLB_4K_SIZE_SHFT); + + tlb_affinity->instr_tlb_1g_assoc = + (l1_tlb_1G_ids & L1_INST_TLB_1G_ASSOC_MASK) + >> L1_INST_TLB_1G_ASSOC_SHFT; + tlb_affinity->instr_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l1_tlb_1G_ids & L1_INST_TLB_1G_SIZE_MASK) + >> L1_INST_TLB_1G_SIZE_SHFT); + } + + /* L2 Data TLB */ + if (thread % num_threads_sharing2 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_DATA_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L2_CACHE; + tlb_affinity->data_tlb_2mb_assoc = + (l2_tlb_2M4M_ids & L2_DAT_TLB_2M4M_ASSOC_MASK) + >> L2_DAT_TLB_2M4M_ASSOC_SHFT; + tlb_affinity->data_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l2_tlb_2M4M_ids & L2_DAT_TLB_2M4M_SIZE_MASK) + >> L2_DAT_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->data_tlb_4k_assoc = + get_associativity((l2_tlb_4K_ids & L2_DAT_TLB_2M4M_ASSOC_MASK) + >> L2_DAT_TLB_4K_ASSOC_SHFT); + tlb_affinity->data_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l2_tlb_2M4M_ids & L2_DAT_TLB_4K_SIZE_MASK) + >> L2_DAT_TLB_4K_SIZE_SHFT); + + tlb_affinity->data_tlb_1g_assoc = + get_associativity((l2_tlb_1G_ids & L2_DAT_TLB_1G_ASSOC_MASK) + >> L2_DAT_TLB_1G_ASSOC_SHFT); + tlb_affinity->data_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l2_tlb_1G_ids & L2_DAT_TLB_1G_SIZE_MASK) + >> L2_DAT_TLB_1G_SIZE_SHFT); + } + + /* L2 Instruction TLB */ + if (thread % num_threads_sharing2 == 0) { + current = add_crat_tlb_entry(&tlb_affinity, current); + new_entries++; + + tlb_affinity->flags |= CRAT_TLB_FLAG_INSTR_TLB; + tlb_affinity->proc_id_low = thread; + sibling_mask = 1; + for (size_t sibling = 1; sibling < num_threads_sharing2; sibling++) + sibling_mask = (sibling_mask << 1) + 1; + tlb_affinity->sibling_map[thread / 8] = sibling_mask << (thread % 8); + tlb_affinity->tlb_level = CRAT_L2_CACHE; + tlb_affinity->instr_tlb_2mb_assoc = get_associativity( + (l2_tlb_2M4M_ids & L2_INST_TLB_2M4M_ASSOC_MASK) + >> L2_INST_TLB_2M4M_ASSOC_SHFT); + tlb_affinity->instr_tlb_2mb_size = + get_tlb_size(tlb_2m, tlb_affinity, + (l2_tlb_2M4M_ids & L2_INST_TLB_2M4M_SIZE_MASK) + >> L2_INST_TLB_2M4M_SIZE_SHFT); + + tlb_affinity->instr_tlb_4k_assoc = + get_associativity((l2_tlb_4K_ids & L2_INST_TLB_4K_ASSOC_MASK) + >> L2_INST_TLB_4K_ASSOC_SHFT); + tlb_affinity->instr_tlb_4k_size = + get_tlb_size(tlb_4k, tlb_affinity, + (l2_tlb_4K_ids & L2_INST_TLB_4K_SIZE_MASK) + >> L2_INST_TLB_4K_SIZE_SHFT); + + tlb_affinity->instr_tlb_1g_assoc = + get_associativity((l2_tlb_1G_ids & L2_INST_TLB_1G_ASSOC_MASK) + >> L2_INST_TLB_1G_ASSOC_SHFT); + tlb_affinity->instr_tlb_1g_size = + get_tlb_size(tlb_1g, tlb_affinity, + (l2_tlb_1G_ids & L2_INST_TLB_1G_SIZE_MASK) + >> L2_INST_TLB_1G_SIZE_SHFT); + } + } + + crat->total_entries += new_entries; + return current; +} + +static unsigned long acpi_fill_crat(struct acpi_crat_header *crat, unsigned long current) +{ + current = gen_crat_hsa_entry(crat, current); + current = gen_crat_memory_entries(crat, current); + current = gen_crat_cache_entry(crat, current); + current = gen_crat_tlb_entry(crat, current); + crat->num_nodes++; + + return current; +} + uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { acpi_ivrs_t *ivrs; + struct acpi_crat_header *crat; - printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); + /* CRAT */ + current = ALIGN(current, 8); + crat = (struct acpi_crat_header *)current; + acpi_create_crat(crat, acpi_fill_crat); + current += crat->header.length; + acpi_add_table(rsdp, crat); - current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index c0a64576de0..be30efa87cd 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -57,6 +57,18 @@ enum sd_emmc_driver_strength { SD_EMMC_DRIVE_STRENGTH_D, }; +/* dpphy_override */ +enum sysinfo_dpphy_override { + ENABLE_DVI_TUNINGSET = 0x01, + ENABLE_HDMI_TUNINGSET = 0x02, + ENABLE_HDMI6G_TUNINGSET = 0x04, + ENABLE_DP_TUNINGSET = 0x08, + ENABLE_DP_HBR3_TUNINGSET = 0x10, + ENABLE_DP_HBR_TUNINGSET = 0x20, + ENABLE_DP_HBR2_TUNINGSET = 0x40, + ENABLE_EDP_TUNINGSET = 0x80, +}; + struct soc_amd_picasso_config { struct soc_amd_common_config common_config; /* @@ -219,6 +231,32 @@ struct soc_amd_picasso_config { /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ + bool acp_i2s_use_external_48mhz_osc; + + /* eDP phy tuning settings */ + uint8_t dp_phy_override; + + struct { + uint8_t dp_vs_pemph_level; + uint8_t deemph_6db4; + uint8_t boostadj; + uint16_t margin_deemph; + } edp_tuningset; + + /* + * eDP panel power sequence control + * all pwr sequence numbers below are in uint of 4ms and "0" as default value + */ + uint8_t edp_pwr_adjust_enable; + uint8_t pwron_digon_to_de; + uint8_t pwron_de_to_varybl; + uint8_t pwrdown_varybloff_to_de; + uint8_t pwrdown_de_to_digoff; + uint8_t pwroff_delay; + uint8_t pwron_varybl_to_blon; + uint8_t pwrdown_bloff_to_varybloff; + uint8_t min_allowed_bl_level; }; #endif /* __PICASSO_CHIP_H__ */ diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index cda509b0a53..d9a18e1cd2b 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -9,8 +11,6 @@ #include #include #include -#include -#include #include #include #include @@ -22,8 +22,8 @@ #include #include #include +#include #include -#include #include #include "chip.h" @@ -89,9 +89,15 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) void sb_clk_output_48Mhz(void) { u32 ctrl; + const struct soc_amd_picasso_config *cfg; + cfg = config_of_soc(); ctrl = misc_read32(MISC_CLK_CNTL1); - ctrl |= BP_X48M0_OUTPUT_EN; + /* If used external clock source for I2S, disable the internal clock output */ + if (cfg->acp_i2s_use_external_48mhz_osc && cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) + ctrl &= ~BP_X48M0_OUTPUT_EN; + else + ctrl |= BP_X48M0_OUTPUT_EN; misc_write32(MISC_CLK_CNTL1, ctrl); } @@ -138,23 +144,6 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static void set_nvs_sws(void *unused) -{ - struct chipset_state *state; - struct global_nvs *gnvs; - - state = cbmem_find(CBMEM_ID_POWER_STATE); - if (state == NULL) - return; - gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; - - acpi_fill_gnvs(gnvs, &state->gpe_state); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); - /* * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks * and unneeded for Raven/Picasso so gate them to save power. @@ -216,12 +205,12 @@ static void gpp_clk_setup(void) void southbridge_init(void *chip_info) { - struct chipset_state *state; + struct chipset_power_state *state; i2c_soc_init(); sb_init_acpi_ports(); - state = cbmem_find(CBMEM_ID_POWER_STATE); + state = acpi_get_pm_state(); if (state) { acpi_pm_gpe_add_events_print_events(&state->gpe_state); gpio_add_events(&state->gpio_state); @@ -231,6 +220,8 @@ void southbridge_init(void *chip_info) al2ahb_clock_gate(); gpp_clk_setup(); + + sb_clk_output_48Mhz(); } void southbridge_final(void *chip_info) @@ -251,6 +242,9 @@ static void set_pci_irqs(void *unused) /* Write PCI_INTR regs 0xC00/0xC01 */ write_pci_int_table(); + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + /* Write IRQs for all devicetree enabled devices */ write_pci_cfg_irqs(); } diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index c7befe43ddc..731a564416a 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -142,6 +142,29 @@ static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) scfg->fch_ioapic_id = CONFIG_PICASSO_FCH_IOAPIC_ID; } +static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + if (cfg->dp_phy_override & ENABLE_EDP_TUNINGSET) { + scfg->DpPhyOverride = cfg->dp_phy_override; + scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level; + scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph; + scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; + scfg->BoostAdj = cfg->edp_tuningset.boostadj; + } + if (cfg->edp_pwr_adjust_enable) { + scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; + scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl; + scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de; + scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff; + scfg->pwroff_delay = cfg->pwroff_delay; + scfg->pwron_varybl_to_blon = cfg->pwron_varybl_to_blon; + scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff; + scfg->min_allowed_bl_level = cfg->min_allowed_bl_level; + } + +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -152,4 +175,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) fsp_fill_pcie_ddi_descriptors(scfg); fsp_assign_ioapic_upds(scfg); fsp_usb_oem_customization(scfg, cfg); + fsp_edp_tuning_upds(scfg, cfg); } diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 1f68d78bd8f..dc63d0099a1 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -18,7 +18,7 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current const char *soc_acpi_name(const struct device *dev); /* Object to capture state of chipset for logging events. */ -struct chipset_state { +struct chipset_power_state { struct acpi_pm_gpe_state gpe_state; struct gpio_wake_state gpio_state; }; diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 01fdc733887..d64c67a2bd2 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -25,6 +25,38 @@ #define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) #define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) +#define D18F0_DRAM_HOLE_CTL 0x104 +#define DRAM_HOLE_CTL_VALID BIT(0) +#define DRAM_HOLE_CTL_BASE_SHFT 24 +#define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) + +#define D18F0_DRAM_BASE0 0x110 +#define DRAM_BASE_REG_VALID BIT(0) +#define DRAM_BASE_HOLE_EN BIT(1) +#define DRAM_BASE_INTLV_CH_SHFT 4 +#define DRAM_BASE_INTLV_CH (0xf << DRAM_BASE_INTLV_CH_SHFT) +#define DRAM_BASE_INTLV_SEL_SHFT 8 +#define DRAM_BASE_INTLV_SEL (0x7 << DRAM_BASE_INTLV_SEL_SHFT) +#define DRAM_BASE_ADDR_SHFT 12 +#define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT) + +#define D18F0_DRAM_LIMIT0 0x114 +#define DRAM_LIMIT_DST_ID_SHFT 0 +#define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT) +#define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 +#define DRAM_LIMIT_INTLV_NUM_SOCK (0x1 << DRAM_LIMIT_INTLV_NUM_SOCK_SHFT) +#define DRAM_LIMIT_INTLV_NUM_DIE_SHFT 10 +#define DRAM_LIMIT_INTLV_NUM_DIE (0x3 << DRAM_LIMIT_INTLV_NUM_DIE_SHFT) +#define DRAM_LIMIT_ADDR_SHFT 12 +#define DRAM_LIMIT_ADDR (0xfffff << DRAM_LIMIT_ADDR_SHFT) + +#define PICASSO_NUM_DRAM_REG 2 + +#define DF_DRAM_BASE(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ + + D18F0_DRAM_BASE0) +#define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ + + D18F0_DRAM_LIMIT0) + #define DF_FICAA_BIOS 0x5C #define DF_FICAD_LO 0x98 #define DF_FICAD_HI 0x9C diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index d5624d4d750..f10fbdde58d 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -9,9 +9,7 @@ #ifndef AMD_PICASSO_NVS_H #define AMD_PICASSO_NVS_H -#include #include -#include #include struct __packed global_nvs { @@ -25,12 +23,6 @@ struct __packed global_nvs { uint8_t tmps; /* 0x17 - Temperature Sensor ID */ uint8_t tcrt; /* 0x18 - Critical Threshold */ uint8_t tpsv; /* 0x19 - Passive Threshold */ - uint8_t unused[230]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/picasso/include/soc/pci.h b/src/soc/amd/picasso/include/soc/pci.h new file mode 100644 index 00000000000..b6ff3496c5e --- /dev/null +++ b/src/soc/amd/picasso/include/soc/pci.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_PCI_H +#define AMD_PICASSO_PCI_H + +void populate_pirq_data(void); + +#endif /* AMD_PICASSO_PCI_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 220d92ea7a7..c7f30e24ec4 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -13,14 +13,6 @@ * - fixed addresses offset from 0xfed80000 */ -/* SMBus controller registers: 0xfed80000 or D14F0 */ -#define SMB_UART_CONFIG 0xfc -#define SMB_UART3_1_8M BIT(31) /* defaults are 0 = 48MHz */ -#define SMB_UART2_1_8M BIT(30) -#define SMB_UART1_1_8M BIT(29) -#define SMB_UART0_1_8M BIT(28) -#define SMB_UART_1_8M_SHIFT 28 - /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) @@ -144,13 +136,6 @@ #define FCH_AOAC_DEV_ESPI 27 #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ -#define FCH_LEGACY_UART_MAP_SHIFT 8 -#define FCH_LEGACY_UART_MAP_SIZE 2 -#define FCH_LEGACY_UART_MAP_MASK 0x3 -#define FCH_LEGACY_UART_RANGE_2E8 0 -#define FCH_LEGACY_UART_RANGE_2F8 1 -#define FCH_LEGACY_UART_RANGE_3E8 2 -#define FCH_LEGACY_UART_RANGE_3F8 3 #define PM1_LIMIT 16 #define GPE0_LIMIT 28 @@ -196,7 +181,6 @@ void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void fch_pre_init(void); void fch_early_init(void); -void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 051c8bf4d53..9b99cd4b247 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -8,6 +8,4 @@ void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ -uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ - #endif /* AMD_PICASSO_UART_H */ diff --git a/src/soc/amd/picasso/mrc_cache.c b/src/soc/amd/picasso/mrc_cache.c index ad0d9649475..24d86e01ace 100644 --- a/src/soc/amd/picasso/mrc_cache.c +++ b/src/soc/amd/picasso/mrc_cache.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 3c3021e086a..3101eb46378 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -1,13 +1,90 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include +#include +#include #include #include #include #include +#include #include #include +/** + * Each PCI bridge has its INTx lines routed to one of the 8 GNB IOAPIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the + * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IOAPIC. + **/ +struct pci_routing { + unsigned int devfn; + unsigned int group; + uint8_t pin[4]; +}; + +/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ +static const struct pci_routing pci_routing_table[] = { + {PCIE_GPP_0_DEVFN, 0, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_1_DEVFN, 1, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_2_DEVFN, 2, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_3_DEVFN, 3, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_4_DEVFN, 4, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_5_DEVFN, 5, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_6_DEVFN, 6, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_A_DEVFN, 7, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, + {PCIE_GPP_B_DEVFN, 7, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, +}; + +/* + * This data structure is populated from the raw data above. It is used + * by amd/common/block/pci/amd_pci_util to write the PCI_INT_LINE register + * to each PCI device. + */ +static struct pirq_struct pirq_data[ARRAY_SIZE(pci_routing_table)]; + +static const struct pci_routing *get_pci_routing(unsigned int devfn) +{ + for (size_t i = 0; i < ARRAY_SIZE(pci_routing_table); ++i) { + if (devfn == pci_routing_table[i].devfn) + return &pci_routing_table[i]; + } + + return NULL; +} + +static unsigned int calculate_irq(const struct pci_routing *pci_routing, unsigned int i) +{ + unsigned int irq_index; + irq_index = pci_routing->group * 4; + irq_index += pci_routing->pin[i]; + + return irq_index; +} + +void populate_pirq_data(void) +{ + const struct pci_routing *pci_routing; + struct pirq_struct *pirq; + unsigned int irq_index; + + for (size_t i = 0; i < ARRAY_SIZE(pirq_data); ++i) { + pirq = &pirq_data[i]; + pci_routing = &pci_routing_table[i]; + + pirq->devfn = pci_routing->devfn; + for (size_t j = 0; j < 4; ++j) { + irq_index = calculate_irq(pci_routing, j); + + pirq->PIN[j] = irq_index % 8; + } + } + + pirq_data_ptr = pirq_data; + pirq_data_size = ARRAY_SIZE(pirq_data); +} + static const char *pcie_gpp_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) @@ -37,6 +114,184 @@ static const char *pcie_gpp_acpi_name(const struct device *dev) return NULL; } +static void acpigen_write_PRT(const struct device *dev) +{ + char link_template[] = "\\_SB.INTX"; + unsigned int irq_index; + + const struct pci_routing *pci_routing = get_pci_routing(dev->path.pci.devfn); + if (!pci_routing) { + printk(BIOS_ERR, "PCI routing table not found for %s\n", dev_path(dev)); + return; + } + + acpigen_write_method("_PRT", 0); + + /* If (PMOD) */ + acpigen_write_if(); + acpigen_emit_namestring("PMOD"); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + + acpigen_write_package(4); /* Package - APIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + irq_index = calculate_irq(pci_routing, i); + + acpigen_write_package(4); + /* There is only one device attached to the bridge */ + acpigen_write_dword(0x0000FFFF); + acpigen_write_byte(i); + acpigen_write_byte(0); /* Source: GSI */ + /* GNB IO-APIC is located after the FCH IO-APIC */ + acpigen_write_dword(IO_APIC_INTERRUPTS + irq_index); + acpigen_pop_len(); + } + acpigen_pop_len(); /* Package - APIC Routing */ + acpigen_pop_len(); /* End If */ + + /* Else */ + acpigen_write_else(); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + + acpigen_write_package(4); /* Package - PIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + irq_index = calculate_irq(pci_routing, i); + + link_template[8] = 'A' + (irq_index % 8); + + acpigen_write_package(4); + /* There is only one device attached to the bridge */ + acpigen_write_dword(0x0000FFFF); + acpigen_write_byte(i); + acpigen_emit_namestring(link_template); + acpigen_write_dword(0); + acpigen_pop_len(); + } + acpigen_pop_len(); /* Package - PIC Routing */ + + acpigen_pop_len(); /* End Else */ + + acpigen_pop_len(); /* Method */ +} + +/* + * This function writes a PCI device with _ADR, _STA, and _PRT objects: + * Example: + * Scope (\_SB.PCI0) + * { + * Device (PBRA) + * { + * Name (_ADR, 0x0000000000080001) // _ADR: Address + * Method (_STA, 0, NotSerialized) // _STA: Status + * { + * Return (0x0F) + * } + * + * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + * { + * If (PMOD) + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * 0x00, + * 0x00000034 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * 0x00, + * 0x00000035 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * 0x00, + * 0x00000036 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * 0x00, + * 0x00000037 + * } + * }) + * } + * Else + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.INTE, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.INTF, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.INTG, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.INTH, + * 0x00000000 + * } + * }) + * } + * } + * } + * } + */ +static void acpi_device_write_gpp_pci_dev(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + assert(dev->path.type == DEVICE_PATH_PCI); + assert(name); + assert(scope); + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_ADR_pci_device(dev); + acpigen_write_STA(acpi_device_status(dev)); + + acpigen_write_PRT(dev); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + + static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -44,7 +299,7 @@ static struct device_operations internal_pcie_gpp_ops = { .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; static const unsigned short pci_device_ids[] = { @@ -66,7 +321,7 @@ static struct device_operations external_pcie_gpp_ops = { .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; static const struct pci_driver external_pcie_gpp_driver __pci_driver = { diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index bf66759a94b..91b316cd787 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -20,7 +20,7 @@ #include "chip.h" #include -static struct chipset_state chipset_state; +static struct chipset_power_state chipset_state; static void fill_chipset_state(void) { @@ -30,7 +30,7 @@ static void fill_chipset_state(void) static void add_chipset_state_cbmem(int unused) { - struct chipset_state *state; + struct chipset_power_state *state; state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 7ca44b02a72..5166fe5ba7c 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -181,6 +182,11 @@ static void read_resources(struct device *dev) gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void root_complex_init(struct device *dev) +{ + setup_ioapic((u8 *)GNB_IO_APIC_ADDR, CONFIG_PICASSO_GNB_IOAPIC_ID); +} + static void dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) { /* Name (buf_name, Buffer(size) {...} */ @@ -264,7 +270,9 @@ static void root_complex_fill_ssdt(const struct device *device) static struct device_operations root_complex_operations = { .read_resources = read_resources, + .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, + .init = root_complex_init, .acpi_fill_ssdt = root_complex_fill_ssdt, }; diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index b417051b97e..24bc2c0f85b 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -3,16 +3,17 @@ #include #include #include +#include #include #include -#include #include +#include #include #include #include #include -static const struct _uart_info { +static const struct { uintptr_t base; struct soc_amd_gpio mux[2]; } uart_info[] = { @@ -42,71 +43,17 @@ uintptr_t get_uart_base(unsigned int idx) return uart_info[idx].base; } -static bool get_uart_idx(uintptr_t base, unsigned int *idx) -{ - for (unsigned int i = 0; i < ARRAY_SIZE(uart_info); i++) { - if (base == uart_info[i].base) { - *idx = i; - return true; - } - } - - return false; -} - void clear_uart_legacy_config(void) { write16((void *)FCH_LEGACY_UART_DECODE, 0); } -void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx) -{ - uint16_t uart_legacy_decode; - uint8_t uart_map_offset; - - if (uart_idx >= ARRAY_SIZE(uart_info) || range_idx >= ARRAY_SIZE(uart_info)) - return; - - uart_legacy_decode = read16((void *)FCH_LEGACY_UART_DECODE); - /* Map uart_idx to io range_idx */ - uart_map_offset = range_idx * FCH_LEGACY_UART_MAP_SIZE + FCH_LEGACY_UART_MAP_SHIFT; - uart_legacy_decode &= ~(FCH_LEGACY_UART_MAP_MASK << uart_map_offset); - uart_legacy_decode |= uart_idx << uart_map_offset; - /* Enable io range */ - uart_legacy_decode |= 1 << range_idx; - write16((void *)FCH_LEGACY_UART_DECODE, uart_legacy_decode); -} - -static void enable_uart_legacy_decode(uintptr_t base) -{ - unsigned int idx; - const uint8_t range_idx[ARRAY_SIZE(uart_info)] = { - FCH_LEGACY_UART_RANGE_3F8, - FCH_LEGACY_UART_RANGE_2F8, - FCH_LEGACY_UART_RANGE_3E8, - FCH_LEGACY_UART_RANGE_2E8, - }; - - if (get_uart_idx(base, &idx)) { - set_uart_legacy_config(idx, range_idx[idx]); - } -} - void set_uart_config(unsigned int idx) { - uint32_t uart_ctrl; - if (idx >= ARRAY_SIZE(uart_info)) return; program_gpios(uart_info[idx].mux, 2); - - if (CONFIG(AMD_SOC_UART_1_8MZ)) { - uart_ctrl = sm_pci_read32(SMB_UART_CONFIG); - uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx); - sm_pci_write32(SMB_UART_CONFIG, uart_ctrl); - } - } static const char *uart_acpi_name(const struct device *dev) @@ -151,8 +98,6 @@ static void uart_enable(struct device *dev) if (dev->enabled) { power_on_aoac_device(dev_id); wait_for_aoac_enabled(dev_id); - if (CONFIG(AMD_SOC_UART_LEGACY)) - enable_uart_legacy_decode(dev->path.mmio.addr); } else { power_off_aoac_device(dev_id); } diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b95dbf4dbe6..6aebd85e1d3 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -10,7 +10,7 @@ if SOC_AMD_STONEYRIDGE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_AMD_HARDWARE_SLEEP_VALUES - select ACPI_NO_SMI_GNVS + select ACPI_SOC_NVS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select COLLECT_TIMESTAMPS_NO_TSC @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_UART select SSE2 select TSC_SYNC_LFENCE select X86_AMD_FIXED_MTRRS @@ -258,20 +259,6 @@ config STONEYRIDGE_ACPI_IO_BASE Base address for the ACPI registers. This value must match the hardcoded value of AGESA. -config STONEYRIDGE_UART - bool "UART controller on Stoney Ridge" - default n - select DRIVERS_UART_8250MEM - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - select UART_OVERRIDE_REFCLK - help - There are two UART controllers in Stoney Ridge. - The UART registers are memory-mapped. UART - controller 0 registers range from FEDC_6000h - to FEDC_6FFFh. UART controller 1 registers - range from FEDC_8000h to FEDC_8FFFh. - config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL hex diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 969f5129eb2..47ecbe7fc55 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -10,7 +10,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm -bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +bootblock-y += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock.c bootblock-y += gpio.c @@ -28,7 +28,7 @@ romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += smbus_spd.c romstage-y += memmap.c -romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-y += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-y += psp.c @@ -36,11 +36,11 @@ romstage-y += psp.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c -verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +verstage-y += uart.c verstage-y += tsc_freq.c postcar-y += monotonic_timer.c -postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-y += uart.c postcar-y += memmap.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -59,7 +59,7 @@ ramstage-y += northbridge.c ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +ramstage-y += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c @@ -160,8 +160,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -PHONY+=add_amdfw -INTERMEDIATE+=add_amdfw # Calculate firmware position inside the ROM STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ @@ -169,7 +167,7 @@ STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) -add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ "$(STONEYRIDGE_FWM_ROM_POSITION)" dd if=$(obj)/amdfw.rom \ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e62f235952c..19add66f87b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -162,20 +161,8 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_write_hpet(device, current, rsdp); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { - /* Clear out GNVS. */ - memset(gnvs, 0, sizeof(*gnvs)); - - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; @@ -184,22 +171,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } -} - static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) { /* diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 4025f80c964..248ee773a4e 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include @@ -90,7 +89,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - if (CONFIG(STONEYRIDGE_UART)) + if (CONFIG(AMD_SOC_CONSOLE_UART)) assert(CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 1); diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 19f0c811364..a498eb93706 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -4,6 +4,7 @@ #define AMD_STONEYRIDGE_ACPI_H #include +#include #if CONFIG(STONEYRIDGE_LEGACY_FREE) #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE @@ -16,4 +17,8 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, const char *soc_acpi_name(const struct device *dev); +struct chipset_power_state { + struct acpi_pm_gpe_state gpe_state; +}; + #endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 9c479c6e62c..e4a158c7cb2 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -9,9 +9,7 @@ #ifndef __SOC_STONEYRIDGE_NVS_H__ #define __SOC_STONEYRIDGE_NVS_H__ -#include #include -#include #include struct __packed global_nvs { @@ -32,12 +30,6 @@ struct __packed global_nvs { uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */ uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */ uint32_t eh10; /* 0x30 - EHCI BAR */ - uint8_t unused[204]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103efd87c..49279028b64 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -80,7 +80,7 @@ asmlinkage void car_stage_entry(void) * * After setting up DRAM, AGESA also completes the configuration * of the MTRRs, setting regions to WB. Anything written to - * memory between now and and when CAR is dismantled will be + * memory between now and when CAR is dismantled will be * in cache and lost. For now, set the regions UC to ensure * the writes get to DRAM. */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 4436e0ebf0b..2a380969e0b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -401,33 +402,16 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static void set_nvs_sws(void *unused) -{ - struct acpi_pm_gpe_state *state; - struct global_nvs *gnvs; - - state = cbmem_find(CBMEM_ID_POWER_STATE); - if (state == NULL) - return; - gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; - - acpi_fill_gnvs(gnvs, state); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); - void southbridge_init(void *chip_info) { - struct acpi_pm_gpe_state *state; + struct chipset_power_state *state; sb_init_acpi_ports(); state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); if (state) { - acpi_fill_pm_gpe_state(state); - acpi_pm_gpe_add_events_print_events(state); + acpi_fill_pm_gpe_state(&state->gpe_state); + acpi_pm_gpe_add_events_print_events(&state->gpe_state); } acpi_clear_pm_gpe_status(); diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 73346ab658c..573ae967160 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -1,17 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include +#include -uintptr_t uart_platform_base(unsigned int idx) +uintptr_t get_uart_base(unsigned int idx) { if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) return 0; return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); } - -unsigned int uart_platform_refclk(void) -{ - return 48000000; -} diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S index a3501438341..5c5066d7ea1 100644 --- a/src/soc/example/min86/cache_as_ram.S +++ b/src/soc/example/min86/cache_as_ram.S @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry .code32 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 7e693cb3733..e7d37fb953a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -3,6 +3,11 @@ config SOC_INTEL_ALDERLAKE help Intel Alderlake support +config SOC_INTEL_ALDERLAKE_PCH_M + bool + help + Choose this option if you have PCH-M chipset. + if SOC_INTEL_ALDERLAKE config CPU_SPECIFIC_OPTIONS @@ -14,7 +19,9 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB @@ -51,6 +58,9 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_USB4 + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET @@ -96,6 +106,12 @@ config CHIPSET_DEVICETREE string default "soc/intel/alderlake/chipset.cb" +config EXT_BIOS_WIN_BASE + default 0xf8000000 + +config EXT_BIOS_WIN_SIZE + default 0x2000000 + config IFD_CHIPSET string default "adl" @@ -108,12 +124,23 @@ config HEAP_SIZE hex default 0x10000 -config MAX_ROOT_PORTS +config MAX_PCH_ROOT_PORTS int + default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 +config MAX_CPU_ROOT_PORTS + int + default 1 if SOC_INTEL_ALDERLAKE_PCH_M + default 3 + +config MAX_ROOT_PORTS + int + default MAX_PCH_ROOT_PORTS + config MAX_PCIE_CLOCKS int + default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 config SMM_TSEG_SIZE diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75079b..f31cf98dd72 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -25,6 +25,7 @@ bootblock-y += p2sb.c romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c ramstage-y += acpi.c @@ -38,6 +39,7 @@ ramstage-y += gpio.c ramstage-y += lockdown.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smmrelocate.c diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index ca5d7268743..d1ab6a040ac 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -279,30 +278,13 @@ unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long curre return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 3d8e55490ae..744b7ef50ae 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* GFX 00:02.0 */ -#include +#include /* ESPI 0:1f.0 */ #include diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 528e4de46e9..662f33e1b75 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -40,9 +40,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -123,19 +120,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index f0d8f2bdc35..8cc81c13a0a 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -79,6 +79,7 @@ static struct { { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" }, }; static struct { diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 794c3bae0f2..c7e3fb8c2fe 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -13,15 +14,10 @@ #include #include #include +#include #include #include -static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -149,7 +145,7 @@ void soc_init_pre_device(void *chip_info) soc_fill_gpio_pm_configuration(); /* Swap enabled PCI ports in device tree if needed. */ - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); } static struct device_operations pci_domain_ops = { @@ -182,6 +178,8 @@ static void soc_enable(struct device *dev) else if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCH_DEVFN_PMC) dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_alderlake_ops = { diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 38d9671f60a..f23b9d25660 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -118,9 +119,12 @@ struct soc_intel_alderlake_config { uint8_t PchHdaIDispLinkFrequency; uint8_t PchHdaIDispCodecDisconnect; - /* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* CPU PCIe Root Ports */ + uint8_t CpuPcieRpEnable[CONFIG_MAX_CPU_ROOT_PORTS]; + + /* PCH PCIe Root Ports */ + uint8_t PchPcieRpEnable[CONFIG_MAX_PCH_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ @@ -130,21 +134,16 @@ struct soc_intel_alderlake_config { uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ - uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_PCH_ROOT_PORTS]; /* Gfx related */ enum { diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index de880e336b9..173d3e037f0 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -1,19 +1,58 @@ chip soc/intel/alderlake device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end device pci 01.0 alias pcie5 off end device pci 02.0 alias igpu off end device pci 04.0 alias dtt off end device pci 06.0 alias pcie4_0 off end device pci 06.2 alias pcie4_1 off end - device pci 07.0 alias tbt_pcie_rp0 off end - device pci 07.1 alias tbt_pcie_rp1 off end - device pci 07.2 alias tbt_pcie_rp2 off end - device pci 07.3 alias tbt_pcie_rp3 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 0 on end + end + end + device pci 07.3 alias tbt_pcie_rp3 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 1 on end + end + end device pci 08.0 alias gna off end device pci 09.0 alias north_tracehub off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias tcss_xhci off end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias tcss_usb3_port4 off end + end + end + end + end device pci 0d.1 alias tcss_xdci off end device pci 0d.2 alias tcss_dma0 off end device pci 0d.3 alias tcss_dma1 off end @@ -24,7 +63,55 @@ chip soc/intel/alderlake device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias xhci off end + device pci 14.0 alias xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + end + end + end device pci 14.1 alias usb_otg off end device pci 14.2 alias shared_sram off end device pci 14.3 alias cnvi_wifi off end diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 84f0a7ed4ff..8ec11075547 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c9090301673..feec465a922 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -20,24 +20,9 @@ #include #include -/* -* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve -* certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() -{ - return lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -45,15 +30,6 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE void lpc_soc_init(struct device *dev) { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index a21ca4a1b56..35f7a3c2e23 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -89,6 +90,8 @@ __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config * void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; + const struct microcode *microcode_file; + size_t microcode_len; FSP_S_CONFIG *params = &supd->FspsConfig; struct device *dev; @@ -99,6 +102,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Parse device tree and enable/disable Serial I/O devices */ parse_devicetree(params); + microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); + + if ((microcode_file != NULL) && (microcode_len != 0)) { + /* Update CPU Microcode patch base address/size */ + params->MicrocodeRegionBase = (uint32_t)microcode_file; + params->MicrocodeRegionSize = (uint32_t)microcode_len; + } + /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); @@ -259,7 +270,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Hybrid storage auto detection */ params->HybridStorageMode = config->HybridStorageMode; - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { params->PcieRpL1Substates[i] = get_l1_substate_control(config->PcieRpL1Substates[i]); params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index d86e81ddc26..098c31daa57 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -22,6 +22,9 @@ #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif +#define SA_DEV_SLOT_CPU_1 0x01 +#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) @@ -34,8 +37,9 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) -#define SA_DEV_SLOT_CPU_PCIE 0x06 -#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) +#define SA_DEV_SLOT_CPU_6 0x06 +#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 0) +#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(PCH_DEV_SLOT_CPU_6, 2) #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h new file mode 100644 index 00000000000..cd76d09e4a5 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_ALDERLAKE_PCIE_H__ +#define __SOC_ALDERLAKE_PCIE_H__ + +#include + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); +const struct pcie_rp_group *get_cpu_pcie_rp_table(void); + +#endif /* __SOC_ALDERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index baeb7083d7d..e05ecd80b8c 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -32,4 +32,10 @@ #define PID_ITSS 0xc4 #define PID_SERIALIO 0xcb + +/* + * SPI - DMI Destination ID + */ +#define SPI_DMI_DESTINATION_ID 0x23a8 + #endif diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c new file mode 100644 index 00000000000..4ec24c265cf --- /dev/null +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + return pch_lp_rp_groups; +} + +/* + * ADL-P FSP define CPU RP as below: + * RP1: PEG60 : 0:6:0 : x4 CPU Slot + * RP2: PEG10 : 0:1:0 : x8 CPU Slot + * RP3: PEG62 : 0:6:2 : x4 CPU Slot + */ +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 }, + { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_cpu_pcie_rp_table(void) +{ + return cpu_rp_groups; +} diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 79088dd7811..43d5084356b 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -13,8 +13,8 @@ #define __SIMPLE_DEVICE__ +#include #include -#include #include #include #include @@ -187,12 +187,10 @@ static int rtc_failed(uint32_t gen_pmcon_b) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon_b); } diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 7e842a200c1..0154cb48481 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -22,12 +22,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t mask = 0; const struct device *dev; - /* - * If IGD is enabled, set IGD stolen size to 60MB. - * Otherwise, skip IGD init in FSP. - */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = is_dev_enabled(dev); + if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) + m_cfg->InternalGfx = 1; + else + m_cfg->InternalGfx = 0; + + /* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */ m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; @@ -41,8 +42,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set CpuRatio to match existing MSR value */ m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) + for (i = 0; i < ARRAY_SIZE(config->PchPcieRpEnable); i++) { + if (config->PchPcieRpEnable[i]) mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; @@ -155,9 +156,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; - /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ - dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); - m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + mask = 0; + for (i = 0; i < ARRAY_SIZE(config->CpuPcieRpEnable); i++) { + if (config->CpuPcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->CpuPcieRpEnableMask = mask; m_cfg->TmeEnable = CONFIG(INTEL_TME); diff --git a/src/soc/intel/alderlake/spi.c b/src/soc/intel/alderlake/spi.c index 2940de1c12f..b02f2a20fda 100644 --- a/src/soc/intel/alderlake/spi.c +++ b/src/soc/intel/alderlake/spi.c @@ -6,8 +6,10 @@ * Chapter number: 7 */ +#include #include #include +#include int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -25,3 +27,8 @@ int spi_soc_devfn_to_bus(unsigned int devfn) } return -1; } + +uint32_t soc_get_spi_dmi_destination_id(void) +{ + return SPI_DMI_DESTINATION_ID; +} diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index a3bdc4a3ba7..6e64e0faff8 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -17,9 +17,10 @@ #include #include -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ @@ -27,6 +28,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -34,6 +36,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -41,23 +44,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4f762a9cd09..62049b5abe3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -413,4 +413,22 @@ config RO_REGION_ONLY string default "pdpt pt" +config INTEL_GMA_PANEL_2 + bool + default n + +config INTEL_GMA_BCLV_OFFSET + default 0xc8358 if INTEL_GMA_PANEL_2 + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8354 if INTEL_GMA_PANEL_2 + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + endif diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index d0e7a73a3fe..773f56eff24 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -72,29 +72,14 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) return cstate_map; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); - /* Clear out GNVS. */ - memset(gnvs, 0, sizeof(*gnvs)); - - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t) cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Set unknown wake source */ gnvs->pm1i = ~0ULL; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = cfg->dptf_enable; diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 8b03713f059..97677ad02e5 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -12,7 +12,7 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - PCNT, 8, // 0x00 - Processor Count + , 8, // 0x00 - Processor Count PPCM, 8, // 0x01 - Max PPC State LIDS, 8, // 0x02 - LID State PWRS, 8, // 0x03 - AC Power State diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 4a8be47c517..4d4e4dc6fee 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "xhci.asl" /* GFX 00:02.0 */ -#include +#include /* LPC */ #include diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a4ed8bdcbb5..9670a31eba4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -216,6 +216,8 @@ static void enable_dev(struct device *dev) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } /* @@ -315,9 +317,6 @@ static void soc_init(void *data) */ p2sb_unhide(); - /* Allocate ACPI NVS in CBMEM */ - cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip setting RAPL per configuration\n"); } else { diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 6e4c82d5a4d..482b3333062 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -4,6 +4,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include +#include #include #include #include @@ -24,22 +25,6 @@ enum pnp_settings { PNP_PERF_POWER, }; -struct soc_intel_apl_pp { - unsigned int up_delay_ms; - unsigned int down_delay_ms; - unsigned int cycle_delay_ms; - unsigned int backlight_on_delay_ms; - unsigned int backlight_off_delay_ms; -}; - -struct soc_intel_apl_blc { - unsigned int pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } polarity; -}; - struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ @@ -48,12 +33,16 @@ struct soc_intel_apollolake_config { /* Common struct containing power limits configuration info */ struct soc_power_limits_config power_limits_config; - /* IGD panel configuration */ - struct soc_intel_apl_pp gpu_pp[2]; - /* Second backlight control shares logic with other pins (aka. display - utility pin). Be sure it's used for PWM before setting any value for - the secondary controls. */ - struct soc_intel_apl_blc gpu_blc[2]; + /* + * IGD panel configuration + * + * Second backlight control shares logic with other pins (aka. display utility pin). + * Be sure it's used for PWM before setting any secondary backlight value. + */ + struct i915_gpu_panel_config panel_cfg[2]; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index b65ab10e6d6..47b68f1489e 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include #include @@ -23,7 +23,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { const struct xhci_wake_info xhci_wake_info[] = { { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, @@ -65,7 +65,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* RTC Reset */ if (ps->gen_pmcon1 & RPS) @@ -88,14 +88,10 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) void pch_log_state(void) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (ps == NULL) { - printk(BIOS_ERR, - "Not logging power state information. " - "Power state not found in cbmem.\n"); + if (acpi_pm_state_for_elog(&ps) < 0) return; - } /* Power and Reset */ pch_log_power_and_resets(ps); diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 24d47721ab5..257222fdee5 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -11,36 +11,37 @@ #include "chip.h" static void graphics_configure_panelpower( - const struct soc_intel_apl_pp *const pp, + const struct i915_gpu_panel_config *const panel_cfg, uint8_t *const mmio, const unsigned int panel_idx) { const unsigned int offset = panel_idx * 0x100; uint32_t reg32; - reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET; + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; write32(mmio + PCH_PP_CONTROL + offset, reg32); - reg32 = pp->up_delay_ms * 10 << 16; - reg32 |= pp->backlight_on_delay_ms * 10; + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; write32(mmio + PCH_PP_ON_DELAYS + offset, reg32); - reg32 = pp->down_delay_ms * 10 << 16; - reg32 |= pp->backlight_off_delay_ms * 10; + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32); } static void graphics_configure_backlight( - const struct soc_intel_apl_blc *const blc, + const struct i915_gpu_panel_config *const panel_cfg, uint8_t *const mmio, const unsigned int panel_idx) { - if (!blc->pwm_hz) + if (!panel_cfg->backlight_pwm_hz) return; - const unsigned int pwm_period = 19200 * 1000 / blc->pwm_hz; + const unsigned int pwm_period = 19200 * 1000 / panel_cfg->backlight_pwm_hz; write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period); write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2); write32(mmio + BXT_BLC_PWM_CTL(panel_idx), - (blc->polarity ? BXT_BLC_PWM_POLARITY : 0)); + panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0); /* Second backlight control uses display utility pin. */ if (panel_idx == 1) { @@ -50,7 +51,7 @@ static void graphics_configure_backlight( } } -void graphics_soc_init(struct device *const dev) +void graphics_soc_panel_init(struct device *const dev) { const struct soc_intel_apollolake_config *const conf = dev->chip_info; const struct resource *mmio_res; @@ -67,9 +68,16 @@ void graphics_soc_init(struct device *const dev) return; mmio = (void *)(uintptr_t)mmio_res->base; - for (i = 0; i < ARRAY_SIZE(conf->gpu_pp); ++i) - graphics_configure_panelpower(&conf->gpu_pp[i], mmio, i); + for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i) + graphics_configure_panelpower(&conf->panel_cfg[i], mmio, i); - for (i = 0; i < ARRAY_SIZE(conf->gpu_blc); ++i) - graphics_configure_backlight(&conf->gpu_blc[i], mmio, i); + for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i) + graphics_configure_backlight(&conf->panel_cfg[i], mmio, i); +} + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *device) +{ + struct soc_intel_apollolake_config *chip = device->chip_info; + return &chip->gfx; } diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 45301c4aa4f..1f2b8ad4f7d 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -9,12 +9,11 @@ #ifndef _SOC_APOLLOLAKE_NVS_H_ #define _SOC_APOLLOLAKE_NVS_H_ -#include -#include +#include struct __packed global_nvs { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t ppcm; /* 0x01 - Max PPC State */ uint8_t lids; /* 0x02 - LID State */ uint8_t pwrs; /* 0x03 - AC Power State */ @@ -34,12 +33,6 @@ struct __packed global_nvs { uint64_t elng; /* 0x35 - 0x3C EPC Length */ uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */ uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */ - uint8_t unused[179]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 3cca387e5a1..9dbc11c3d62 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -34,8 +34,8 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) -#define SA_GLK_DEV_SLOT_GMM 0x03 -#define SA_GLK_DEVFN_GMM PCI_DEVFN(SA_GLK_DEV_SLOT_GMM, 0) +#define SA_GLK_DEV_SLOT_GMM 0x03 +#define SA_GLK_DEVFN_GMM PCI_DEVFN(SA_GLK_DEV_SLOT_GMM, 0) #define SA_GLK_DEV_GMM PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0) /* PCH Devices */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index ad9211b9c23..4a5f40f42a1 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -3,76 +3,10 @@ #include #include #include -#include #include #include #include "chip.h" -static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = { - { 0xfed40000, 0x8000 }, - { 0xfedc0000, 0x4000 }, - { 0xfed20800, 16 }, - { 0xfed20880, 8 }, - { 0xfed208e0, 16 }, - { 0xfed208f0, 8 }, - { 0xfed30800, 16 }, - { 0xfed30880, 8 }, - { 0xfed308e0, 16 }, - { 0xfed308f0, 8 }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) -{ - return apl_lpc_fixed_mmio_ranges; -} - -static const struct pad_config lpc_gpios[] = { -#if CONFIG(SOC_INTEL_GEMINILAKE) -#if !CONFIG(SOC_ESPI) - PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_CLKOUT0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_CLKOUT1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_AD0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_AD1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_AD2 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_AD3 */ - PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_FRAMEB */ -#else - /* - * LPC_CLKRUNB should be in GPIO mode for eSPI. Other pin settings - * i.e. Rx path enable/disable, Tx path enable/disable, pull up - * enable/disable etc are ignored. Leaving this pin in Native mode - * will keep LPC Controller awake and prevent S0ix entry - */ - PAD_NC(GPIO_154, NONE), -#endif /* !CONFIG(SOC_ESPI) */ -#else - PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) -#endif -}; - -void lpc_configure_pads(void) -{ - gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios)); -} - void lpc_soc_init(struct device *dev) { const struct soc_intel_apollolake_config *cfg; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 6e96b57a072..1d4a55835ee 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -3,9 +3,9 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include -#include #include #include #include @@ -185,12 +185,10 @@ static int rtc_failed(uint32_t gen_pmcon1) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon1); } diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 4e35ee5a0a0..2a2d7a20dfa 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -11,11 +11,11 @@ #include #include -/* UART pad configuration. Support RXD and TXD for now. */ -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { #if CONFIG(SOC_INTEL_GEMINILAKE) { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ @@ -26,6 +26,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ @@ -36,6 +37,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { #else { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */ @@ -43,6 +45,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ @@ -50,6 +53,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ @@ -58,25 +62,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { #endif }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - case 3: - return pcidev_path_on_root(PCH_DEVFN_UART3); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 1144749ab10..d379bebd81b 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -17,12 +17,10 @@ #include #include #include +#include #include #include -#include -#include - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ @@ -58,32 +56,13 @@ static acpi_cstate_t cstate_map[] = { } }; -void acpi_init_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } } int acpi_sci_irq(void) diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index ad77a832a8f..def3fc8f1f9 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ LIDS, 8, /* 0x0f - LID state (open = 1) */ PWRS, 8, /* 0x10 - Power State (AC = 1) */ - PCNT, 8, /* 0x11 - Processor count */ + , 8, /* 0x11 - Processor count */ TPMP, 8, /* 0x12 - TPM Present and Enabled */ TLVL, 8, /* 0x13 - Throttle Level */ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index e3997d75f71..8c715d3d12d 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -37,112 +37,118 @@ Name(_BBN, 0) Name (MCRS, ResourceTemplate() { - // Bus Numbers + /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - // IO Region 0 + /* IO Region 0 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - // PCI Config Space + /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - // IO Region 1 + /* IO Region 1 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - // VGA memory (0xa0000-0xbffff) + /* VGA memory (0xa0000-0xbffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,, ASEG) - // OPROM reserved (0xc0000-0xc3fff) + /* OPROM reserved (0xc0000-0xc3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, 0x00004000,,, OPR0) - // OPROM reserved (0xc4000-0xc7fff) + /* OPROM reserved (0xc4000-0xc7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, 0x00004000,,, OPR1) - // OPROM reserved (0xc8000-0xcbfff) + /* OPROM reserved (0xc8000-0xcbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, 0x00004000,,, OPR2) - // OPROM reserved (0xcc000-0xcffff) + /* OPROM reserved (0xcc000-0xcffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, 0x00004000,,, OPR3) - // OPROM reserved (0xd0000-0xd3fff) + /* OPROM reserved (0xd0000-0xd3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, 0x00004000,,, OPR4) - // OPROM reserved (0xd4000-0xd7fff) + /* OPROM reserved (0xd4000-0xd7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, 0x00004000,,, OPR5) - // OPROM reserved (0xd8000-0xdbfff) + /* OPROM reserved (0xd8000-0xdbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, 0x00004000,,, OPR6) - // OPROM reserved (0xdc000-0xdffff) + /* OPROM reserved (0xdc000-0xdffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, 0x00004000,,, OPR7) - // BIOS Extension (0xe0000-0xe3fff) + /* BIOS Extension (0xe0000-0xe3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, 0x00004000,,, ESG0) - // BIOS Extension (0xe4000-0xe7fff) + /* BIOS Extension (0xe4000-0xe7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, 0x00004000,,, ESG1) - // BIOS Extension (0xe8000-0xebfff) + /* BIOS Extension (0xe8000-0xebfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, 0x00004000,,, ESG2) - // BIOS Extension (0xec000-0xeffff) + /* BIOS Extension (0xec000-0xeffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000ec000, 0x000effff, 0x00000000, 0x00004000,,, ESG3) - // System BIOS (0xf0000-0xfffff) + /* System BIOS (0xf0000-0xfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + /* LPEA Memory Region (0x20000000-0x201FFFFF) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) + 0x00000000,,, LMEM) - // TPM Area (0xfed40000-0xfed44fff) + /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ + DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) + + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, @@ -152,10 +158,27 @@ Name (MCRS, ResourceTemplate() Method (_CRS, 0, Serialized) { + /* Update LPEA resource area */ + CreateDWordField (MCRS, ^LMEM._MIN, LMIN) + CreateDWordField (MCRS, ^LMEM._MAX, LMAX) + CreateDWordField (MCRS, ^LMEM._LEN, LLEN) + If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One))) + { + Store (LPFW, LMIN) + Store (0x00100000, LLEN) + Subtract (Add (LMIN, LLEN), One, LMAX) + } + Else + { + Store (Zero, LMIN) + Store (Zero, LMAX) + Store (Zero, LLEN) + } + /* Update PCI resource area */ - CreateDwordField(MCRS, ^PMEM._MIN, PMIN) - CreateDwordField(MCRS, ^PMEM._MAX, PMAX) - CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + CreateDWordField (MCRS, ^PMEM._MIN, PMIN) + CreateDWordField (MCRS, ^PMEM._MAX, PMAX) + CreateDWordField (MCRS, ^PMEM._LEN, PLEN) /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) @@ -236,7 +259,7 @@ Device (IOSF) /* IRQ routing for each PCI device */ #include "irqroute.asl" -// PCI Express Ports 0:1c.x +/* PCI Express Ports 0:1c.x */ #include "pcie.asl" Scope (\_SB) @@ -253,6 +276,9 @@ Scope (\_SB.PCI0) /* SCC Devices */ #include "scc.asl" - // LPE Device + /* LPE Device */ #include "lpe.asl" } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 2029017e1ff..e624240d925 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -149,7 +149,7 @@ static void get_microcode_info(const void **microcode, int *parallel) const struct pattrs *pattrs = pattrs_get(); *microcode = pattrs->microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 7e92e9037d7..b299c372185 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include #include @@ -76,13 +76,10 @@ static void log_wake_events(const struct chipset_power_state *ps) void southcluster_log_state(void) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (ps == NULL) { - printk(BIOS_DEBUG, - "Not logging power state information. Power state not found in cbmem.\n"); + if (acpi_pm_state_for_elog(&ps) < 0) return; - } log_power_and_resets(ps); log_wake_events(ps); diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index e8253e0b2cd..e672b58bfe2 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -6,8 +6,8 @@ #include #include +#include #include -#include #include #include #include "chip.h" diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 8d9e93ae131..d629b242eb7 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _BAYTRAIL_ACPI_H_ #include -#include int acpi_sci_irq(void); unsigned long acpi_madt_irq_overrides(unsigned long current); diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 41b827e5c9d..105d304f660 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -3,8 +3,7 @@ #ifndef _BAYTRAIL_NVS_H_ #define _BAYTRAIL_NVS_H_ -#include -#include +#include #include struct __packed global_nvs { @@ -22,7 +21,7 @@ struct __packed global_nvs { u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ + u8 unused_was_pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ @@ -49,12 +48,10 @@ struct __packed global_nvs { u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ - chromeos_acpi_t chromeos; + u8 chromeos_reserve[0xf00]; /* Baytrail LPSS (0x1000) */ device_nvs_t dev; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index cc1dd42fc5f..7ab61ac7cf2 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -2,13 +2,13 @@ #include #include +#include #include #include #include #include #include #include -#include #include #include @@ -349,7 +349,7 @@ int rtc_failure(void) { uint32_t gen_pmcon1; int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct chipset_power_state *ps = acpi_get_pm_state(); if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index b15970e7b34..f1401e2411d 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -2,7 +2,9 @@ #include #include -#include +#include +#include +#include #include #include #include @@ -116,14 +118,9 @@ static void fill_in_pattrs(void) } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(struct global_nvs *gnvs) +static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); uint16_t pm1; - - if (!ps) - return; - pm1 = ps->pm1_sts & ps->pm1_en; /* Scan for first set bit in PM1 */ @@ -141,20 +138,21 @@ static void s3_save_acpi_wake_source(struct global_nvs *gnvs) gnvs->pm1i); } -static void s3_resume_prepare(void) +static void acpi_save_wake_source(void *unused) { - struct global_nvs *gnvs; + const struct chipset_power_state *ps; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (gnvs == NULL) + if (acpi_pm_state_for_wake(&ps) < 0) return; - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(struct global_nvs)); - else - s3_save_acpi_wake_source(gnvs); + pm_fill_gnvs(gnvs, ps); } +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); + static void baytrail_enable_2x_refresh_rate(void) { u32 reg; @@ -176,9 +174,6 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); - /* Run reference code. */ baytrail_run_reference_code(); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 10ad93298b3..f922750a362 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include uintptr_t smbus_base(void) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 76aa711fc8f..e9513cd8ec8 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -6,9 +6,6 @@ #include #include #include -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include -#endif #include #include #include @@ -62,7 +59,7 @@ static struct chipset_power_state *fill_power_state(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int chipset_prev_sleep_state(struct chipset_power_state *ps) +static int chipset_prev_sleep_state(const struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0; diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 34a90317ea3..0a015c8667e 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -6,8 +6,8 @@ #include #include +#include #include -#include #include #include #include "chip.h" diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1810821ec8b..6fedba7f693 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -18,8 +18,6 @@ #include #include -static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -282,7 +280,6 @@ static void southbridge_smi_store(void) static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -312,23 +309,6 @@ static void southbridge_smi_apmc(void) enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 967a710c2a8..51b8e09d576 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -20,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -484,33 +482,9 @@ void southcluster_enable_dev(struct device *dev) } } -static void southcluster_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} - static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, - .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = sc_init, .enable = southcluster_enable_dev, diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index fd5ffceb983..70fd9930d98 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -5,25 +5,23 @@ #include #include #include -#include #include #include #include #include #include -#include #include #include #include #include #include #include +#include #include #include #include #include #include -#include #include #define MWAIT_RES(state, sub_state) \ @@ -61,32 +59,19 @@ static acpi_cstate_t cstate_map[] = { } }; -void acpi_init_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } + /* Fill in the Wi-Fi Region ID */ + if (CONFIG(HAVE_REGULATORY_DOMAIN)) + gnvs->cid1 = wifi_regulatory_domain(); + else + gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; } int acpi_sci_irq(void) @@ -376,36 +361,6 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsign return current; } -void southcluster_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Fill in the Wi-Fi Region ID */ - if (CONFIG(HAVE_REGULATORY_DOMAIN)) - gnvs->cid1 = wifi_regulatory_domain(); - else - gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} - __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { } diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index c983d93db7a..564eb437882 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ LIDS, 8, /* 0x0f - LID state (open = 1) */ PWRS, 8, /* 0x10 - Power State (AC = 1) */ - PCNT, 8, /* 0x11 - Processor count */ + , 8, /* 0x11 - Processor count */ TPMP, 8, /* 0x12 - TPM Present and Enabled */ TLVL, 8, /* 0x13 - Throttle Level */ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 2c31d40d224..d74647e98d8 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -272,3 +272,6 @@ Scope (\_SB.PCI0) /* SCC Devices */ #include "scc.asl" } + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 2adda5494f5..d759602f40f 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -50,8 +50,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) struct soc_intel_braswell_config *config; if (!dev) { - printk(BIOS_ERR, "Error! Device (%s) not found, soc_silicon_init_params!\n", - dev_path(dev)); + printk(BIOS_ERR, "Error! Device (%s) not found, %s!\n", + dev_path(dev), __func__); return; } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 04bf1082c3b..0c6f463438b 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -152,7 +152,7 @@ static void get_microcode_info(const void **microcode, int *parallel) const struct pattrs *pattrs = pattrs_get(); *microcode = pattrs->microcode_patch; - *parallel = 1; + *parallel = !intel_ht_supported(); } static void per_cpu_smm_trigger(void) diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 7e92e9037d7..b299c372185 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include #include @@ -76,13 +76,10 @@ static void log_wake_events(const struct chipset_power_state *ps) void southcluster_log_state(void) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (ps == NULL) { - printk(BIOS_DEBUG, - "Not logging power state information. Power state not found in cbmem.\n"); + if (acpi_pm_state_for_elog(&ps) < 0) return; - } log_power_and_resets(ps); log_wake_events(ps); diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 954b5b4b50b..d3c5aa86409 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -6,8 +6,8 @@ #include #include +#include #include -#include #include #include #include "chip.h" diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 3662dd83e13..461913dda3e 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -4,12 +4,10 @@ #define _SOC_ACPI_H_ #include -#include int acpi_sci_irq(void); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -void southcluster_inject_dsdt(const struct device *device); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 35ab47a1e76..41bb5a1a545 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -3,9 +3,8 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include +#include #include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -22,7 +21,7 @@ struct __packed global_nvs { u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ + u8 unused_was_pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ @@ -43,7 +42,7 @@ struct __packed global_nvs { u8 rsvd2[8]; /* Base Addresses */ - u32 cmem; /* 0x30 - CBMEM TOC */ + u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ @@ -51,12 +50,10 @@ struct __packed global_nvs { u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ - chromeos_acpi_t chromeos; + u8 chromeos_reserve[0xf00]; /* LPSS (0x1000) */ device_nvs_t dev; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 2cf9afa6334..3f38de8f2d6 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -11,7 +11,7 @@ void gfx_init(void); void punit_init(void); /* romstage.c functions */ -int chipset_prev_sleep_state(struct chipset_power_state *ps); +int chipset_prev_sleep_state(const struct chipset_power_state *ps); /* Values for FSP's PcdMemoryTypeEnable */ #define MEM_DDR3 0 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index eba15274dd4..f49c760588e 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include #include @@ -14,13 +14,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include #define SHOW_PATTRS 1 @@ -124,9 +122,12 @@ static void fill_in_pattrs(void) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct chipset_power_state *ps = acpi_get_pm_state(); static uint32_t gpe0_sts; + if (!ps) + return -1; + *pm1 = ps->pm1_sts & ps->pm1_en; gpe0_sts = ps->gpe0_sts & ps->gpe0_en; @@ -135,27 +136,6 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) return 1; } -static void s3_resume_prepare(void) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(struct global_nvs)); -} - -static void set_board_id(void) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - gnvs->bdid = board_id(); -} - void soc_init_pre_device(struct soc_intel_braswell_config *config) { struct soc_gpio_config *gpio_config; @@ -165,14 +145,10 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); - /* Perform silicon specific init. */ intel_silicon_init(); set_max_freq(); - set_board_id(); /* Get GPIO initial states from mainboard */ gpio_config = mainboard_get_gpios(); setup_soc_gpios(gpio_config, config->enable_xdp_tap); diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 1738679b1e5..5a1aa0ae736 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -57,7 +57,7 @@ struct chipset_power_state *fill_power_state(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int chipset_prev_sleep_state(struct chipset_power_state *ps) +int chipset_prev_sleep_state(const struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0; diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 5d88016619d..39a44db7729 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -6,8 +6,8 @@ #include #include +#include #include -#include #include #include #include "chip.h" diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 6e250d81ccf..a4fdb013cb7 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -18,8 +18,6 @@ #include #include -static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -261,7 +259,6 @@ static void southbridge_smi_store(void) static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -291,23 +288,6 @@ static void southbridge_smi_apmc(void) enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index e4b62954176..25868640a4d 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -531,7 +531,6 @@ void southcluster_enable_dev(struct device *dev) static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, - .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6e57f0aa8e2..14bbb813ba2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -5,17 +5,17 @@ config SOC_INTEL_BROADWELL if SOC_INTEL_BROADWELL -config CPU_SPECIFIC_OPTIONS +config INTEL_LYNXPOINT_LP + bool + default y if SOC_INTEL_BROADWELL + +config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS + select CPU_INTEL_HASWELL select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -24,14 +24,10 @@ config CPU_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select HAVE_USBDEBUG select IOAPIC + select INTEL_LYNXPOINT_LP select REG_SCRIPT - select PARALLEL_MP select RTC select SPI_FLASH - select SSE2 - select TSC_SYNC_MFENCE - select UDELAY_TSC - select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT @@ -83,18 +79,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config SMM_TSEG_SIZE - hex - default 0x800000 - -config IED_REGION_SIZE - hex - default 0x400000 - -config SMM_RESERVED_SIZE - hex - default 0x100000 - config VGA_BIOS_ID string default "8086,0406" diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7d216651385..5e0ce649bfe 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += cpu subdirs-y += pch bootblock-y += bootblock.c diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9ef7eb..5df44fb39e9 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -14,13 +15,9 @@ #include #include #include -#include -#include #include -#include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 3e7ced02963..2b44c6522f4 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -195,3 +195,6 @@ Device (PDRC) /* Configurable TDP */ #include "ctdp.asl" + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index 5edfaeecaf1..1e32f357a13 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -12,7 +12,7 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use + * true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 81c97807761..045fdbc71cb 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -3,7 +3,7 @@ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ -#include +#include #include struct soc_intel_broadwell_config { @@ -18,19 +18,8 @@ struct soc_intel_broadwell_config { u8 gpu_dp_c_hotplug; u8 gpu_dp_d_hotplug; - /* Panel power sequence timings */ - u8 gpu_panel_power_cycle_delay; - u16 gpu_panel_power_up_delay; - u16 gpu_panel_power_down_delay; - u16 gpu_panel_power_backlight_on_delay; - u16 gpu_panel_power_backlight_off_delay; - - /* Panel backlight settings */ - unsigned int gpu_pch_backlight_pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } gpu_pch_backlight_polarity; + /* IGD panel configuration */ + struct i915_gpu_panel_config panel_cfg; /* * Graphics CD Clock Frequency @@ -42,34 +31,6 @@ struct soc_intel_broadwell_config { int cdclk; struct i915_gpu_controller_info gfx; - - /* - * Minimum voltage for C6/C7 state: - * 0x67 = 1.6V (full swing) - * ... - * 0x79 = 1.7V - * ... - * 0x83 = 1.8V (no swing) - */ - int vr_cpu_min_vid; - - /* - * Set slow VR ramp rate on C-state exit: - * 0 = Fast VR ramp rate / 2 - * 1 = Fast VR ramp rate / 4 - * 2 = Fast VR ramp rate / 8 - * 3 = Fast VR ramp rate / 16 - */ - int vr_slow_ramp_rate_set; - - /* Enable slow VR ramp rate */ - int vr_slow_ramp_rate_enable; - - /* Enable S0iX support */ - int s0ix_enable; - - /* TCC activation offset */ - uint32_t tcc_offset; }; typedef struct soc_intel_broadwell_config config_t; diff --git a/src/soc/intel/broadwell/cpu/Makefile.inc b/src/soc/intel/broadwell/cpu/Makefile.inc deleted file mode 100644 index 803696a1f04..00000000000 --- a/src/soc/intel/broadwell/cpu/Makefile.inc +++ /dev/null @@ -1,30 +0,0 @@ -subdirs-y += ../../../../cpu/x86/lapic -subdirs-y += ../../../../cpu/x86/mtrr -subdirs-y += ../../../../cpu/x86/smm -subdirs-y += ../../../../cpu/x86/tsc -subdirs-y += ../../../../cpu/intel/microcode -subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/intel/common - -bootblock-y += bootblock.c -bootblock-y += ../../../../cpu/intel/car/bootblock.c -bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S -bootblock-y += ../../../../cpu/x86/early_reset.S - -romstage-y += romstage.c -romstage-y += ../../../../cpu/intel/car/romstage.c - -postcar-y += ../../../../cpu/intel/car/non-evict/exit_car.S - -ramstage-y += acpi.c -ramstage-y += cpu.c -ramstage-y += smmrelocate.c - -bootblock-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -postcar-y += tsc_freq.c -verstage-y += tsc_freq.c - -cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c deleted file mode 100644 index ec3d588a44e..00000000000 --- a/src/soc/intel/broadwell/cpu/acpi.c +++ /dev/null @@ -1,395 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; - -static int cstate_set_s0ix[3] = { - C_STATE_C1E, - C_STATE_C7S_LONG_LAT, - C_STATE_C10 -}; - -static int cstate_set_non_s0ix[3] = { - C_STATE_C1E, - C_STATE_C3, - C_STATE_C7S_LONG_LAT -}; - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} diff --git a/src/soc/intel/broadwell/cpu/bootblock.c b/src/soc/intel/broadwell/cpu/bootblock.c deleted file mode 100644 index d6883c64360..00000000000 --- a/src/soc/intel/broadwell/cpu/bootblock.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u32 soft_reset; - u8 nominal_ratio; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); - - /* Delay before reset to avoid potential TPM lockout */ - mdelay(30); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); -} - -void bootblock_early_cpu_init(void) -{ - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); -} diff --git a/src/soc/intel/broadwell/cpu/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c deleted file mode 100644 index 72efa3dc819..00000000000 --- a/src/soc/intel/broadwell/cpu/cpu.c +++ /dev/null @@ -1,642 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - -/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly - * when a core is woken up. */ -static int pcode_ready(void) -{ - int wait_count; - const int delay_step = 10; - - wait_count = 0; - do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) - return 0; - wait_count += delay_step; - udelay(delay_step); - } while (wait_count < 1000); - - return -1; -} - -static void calibrate_24mhz_bclk(void) -{ - int err_code; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return; - } - - /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return; - } - - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - - printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", - err_code); - - /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); - return; - } - - printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); -} - -static u32 pcode_mailbox_read(u32 command) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return 0; - } - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return 0; - } - - /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); -} - -static int pcode_mailbox_write(u32 command, u32 data) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return -1; - } - - MCHBAR32(BIOS_MAILBOX_DATA) = data; - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return -1; - } - - return 0; -} - -static void initialize_vr_config(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - printk(BIOS_DEBUG, "Initializing VR config.\n"); - - /* Configure VR_CURRENT_CONFIG. */ - msr = rdmsr(MSR_VR_CURRENT_CONFIG); - /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid - * on ULT systems. */ - msr.hi &= 0xc0000000; - msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ - msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ - msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ - /* Leave the max instantaneous current limit (12:0) to default. */ - wrmsr(MSR_VR_CURRENT_CONFIG, msr); - - /* Configure VR_MISC_CONFIG MSR. */ - msr = rdmsr(MSR_VR_MISC_CONFIG); - /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ - msr.hi &= ~(0x3ff << (40 - 32)); - msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ - /* Set IOUT_OFFSET to 0. */ - msr.hi &= ~0xff; - /* Set entry ramp rate to slow. */ - msr.hi &= ~(1 << (51 - 32)); - /* Enable decay mode on C-state entry. */ - msr.hi |= (1 << (52 - 32)); - /* Set the slow ramp rate */ - msr.hi &= ~(0x3 << (53 - 32)); - /* Configure the C-state exit ramp rate. */ - if (conf->vr_slow_ramp_rate_enable) { - /* Configured slow ramp rate. */ - msr.hi |= ((conf->vr_slow_ramp_rate_set & 0x3) << (53 - 32)); - /* Set exit ramp rate to slow. */ - msr.hi &= ~(1 << (50 - 32)); - } else { - /* Fast ramp rate / 4. */ - msr.hi |= (0x01 << (53 - 32)); - /* Set exit ramp rate to fast. */ - msr.hi |= (1 << (50 - 32)); - } - /* Set MIN_VID (31:24) to allow CPU to have full control. */ - msr.lo &= ~0xff000000; - msr.lo |= (conf->vr_cpu_min_vid & 0xff) << 24; - wrmsr(MSR_VR_MISC_CONFIG, msr); - - /* Configure VR_MISC_CONFIG2 MSR. */ - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage in 10mV steps. */ - if (cpu_family_model() == BROADWELL_FAMILY_ULT) - msr.lo |= 0x006a; /* 1.56V */ - else - msr.lo |= 0x006f; /* 1.60V */ - wrmsr(MSR_VR_MISC_CONFIG2, msr); - - /* Set C9/C10 VCC Min */ - pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); -} - -static void configure_pch_power_sharing(void) -{ - u32 pch_power, pch_power_ext, pmsync, pmsync2; - int i; - - /* Read PCH Power levels from PCODE */ - pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); - pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); - - printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); - - pmsync = RCBA32(PMSYNC_CONFIG); - pmsync2 = RCBA32(PMSYNC_CONFIG2); - - /* Program PMSYNC_TPR_CONFIG PCH power limit values - * pmsync[0:4] = mailbox[0:5] - * pmsync[8:12] = mailbox[6:11] - * pmsync[16:20] = mailbox[12:17] - */ - for (i = 0; i < 3; i++) { - u32 level = pch_power & 0x3f; - pch_power >>= 6; - pmsync &= ~(0x1f << (i * 8)); - pmsync |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG) = pmsync; - - /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values - * pmsync2[0:4] = mailbox[23:18] - * pmsync2[8:12] = mailbox_ext[6:11] - * pmsync2[16:20] = mailbox_ext[12:17] - * pmsync2[24:28] = mailbox_ext[18:22] - */ - pmsync2 &= ~0x1f; - pmsync2 |= pch_power & 0x1f; - - for (i = 1; i < 4; i++) { - u32 level = pch_power_ext & 0x3f; - pch_power_ext >>= 6; - pmsync2 &= ~(0x1f << (i * 8)); - pmsync2 |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG2) = pmsync2; -} - -int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time; - u8 power_limit_1_val; - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP */ - limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_EN; - /* Power limit 2 time is only programmable on server SKU */ - - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - limit.hi = 0; - limit.lo = msr.lo & 0xff; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - -static void configure_c_states(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 31); // Timed MWAIT Enable - msr.lo |= (1 << 30); // Package c-state Undemotion Enable - msr.lo |= (1 << 29); // Package c-state Demotion Enable - msr.lo |= (1 << 28); // C1 Auto Undemotion Enable - msr.lo |= (1 << 27); // C3 Auto Undemotion Enable - msr.lo |= (1 << 26); // C1 Auto Demotion Enable - msr.lo |= (1 << 25); // C3 Auto Demotion Enable - msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination - wrmsr(MSR_MISC_PWR_MGMT, msr); - - msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 - msr.lo |= (1 << 1); // C1E Enable - msr.lo |= (1 << 0); // Bi-directional PROCHOT# - wrmsr(MSR_POWER_CTL, msr); - - /* C-state Interrupt Response Latency Control 0 - package C3 latency */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); - - /* C-state Interrupt Response Latency Control 1 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - - /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); -} - -static void configure_thermal_target(void) -{ - config_t *conf; - struct device *lapic; - msr_t msr; - - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } -} - -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void set_max_ratio(void) -{ - msr_t msr, perf_ctl; - - perf_ctl.hi = 0; - - /* Check for configurable TDP option */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); -} - -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - -/* All CPUs including BSP will run the following function. */ -static void cpu_core_init(struct device *cpu) -{ - /* Clear out pending MCEs */ - configure_mca(); - - /* Enable the local CPU APICs */ - enable_lapic_tpr(); - setup_lapic(); - - /* Set virtualization based on Kconfig option */ - set_vmx_and_lock(); - - /* Configure C States */ - configure_c_states(); - - /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); - - /* Thermal throttle activation offset */ - configure_thermal_target(); - - /* Enable Direct Cache Access */ - configure_dca_cap(); - - /* Set energy policy */ - set_energy_perf_bias(ENERGY_POLICY_NORMAL); - - /* Enable Turbo */ - enable_turbo(); -} - -/* MP initialization support. */ -static const void *microcode_patch; - -static void pre_mp_init(void) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - - initialize_vr_config(); - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); -} - -static int get_cpu_count(void) -{ - msr_t msr; - int num_threads; - int num_cores; - - msr = rdmsr(MSR_CORE_THREAD_COUNT); - num_threads = (msr.lo >> 0) & 0xffff; - num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); - - return num_threads; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; - *parallel = 1; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - -static void post_mp_init(void) -{ - /* Set Max Ratio */ - set_max_ratio(); - - /* Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. */ - global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, - .per_cpu_smm_trigger = per_cpu_smm_trigger, - .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, -}; - -void broadwell_init_cpus(struct device *dev) -{ - struct bus *cpu_bus = dev->link_list; - - if (mp_init_with_smm(cpu_bus, &mp_ops)) - printk(BIOS_ERR, "MP initialization failure.\n"); -} - -static struct device_operations cpu_dev_ops = { - .init = cpu_core_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, CPUID_HASWELL_ULT }, - { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, - { X86_VENDOR_INTEL, CPUID_BROADWELL_D0 }, - { X86_VENDOR_INTEL, CPUID_BROADWELL_E0 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/soc/intel/broadwell/cpu/smmrelocate.c b/src/soc/intel/broadwell/cpu/smmrelocate.c deleted file mode 100644 index 3d4162abd03..00000000000 --- a/src/soc/intel/broadwell/cpu/smmrelocate.c +++ /dev/null @@ -1,264 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) { - write_prmrr(relo_params); - /* UNCORE_PRMRR msrs are package level. Therefore, only - * configure these MSRs on the BSP. */ - if (cpu == 0) - write_uncore_prmrr(relo_params); - } -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); - - /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_prmrr_base.lo = prmrr_base; - params->uncore_prmrr_base.hi = 0; - params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/broadwell/cpu/tsc_freq.c b/src/soc/intel/broadwell/cpu/tsc_freq.c deleted file mode 100644 index 4a8a34349f8..00000000000 --- a/src/soc/intel/broadwell/cpu/tsc_freq.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); -} diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index d42eebc4f1e..6556dd4e193 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -4,7 +4,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -15,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -284,6 +285,7 @@ int gtt_poll(u32 reg, u32 mask, u32 value) static void gma_setup_panel(struct device *dev) { config_t *conf = config_of(dev); + const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg; u32 reg32; /* Setup Digital Port Hotplug */ @@ -298,30 +300,30 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_ON_DELAYS, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(PCH_PP_OFF_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; - reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; gtt_write(PCH_PP_OFF_DELAYS, reg32); } /* Setup Panel Power Cycle Delay */ - if (conf->gpu_panel_power_cycle_delay) { + if (panel_cfg->cycle_delay_ms) { reg32 = gtt_read(PCH_PP_DIVISOR); - reg32 &= ~0xff; - reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + reg32 &= ~0x1f; + reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } /* So far all devices seem to use the PCH PWM function. The CPU PWM registers are all zero after reset. */ - if (conf->gpu_pch_backlight_pwm_hz) { + if (panel_cfg->backlight_pwm_hz) { /* For Lynx Point-LP: Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less @@ -332,7 +334,7 @@ static void gma_setup_panel(struct device *dev) u32 south_chicken2; south_chicken2 = gtt_read(SOUTH_CHICKEN2); - if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + if (panel_cfg->backlight_pwm_hz > hz_limit) { pwm_increment = 16; south_chicken2 |= 1 << 5; } else { @@ -341,7 +343,7 @@ static void gma_setup_panel(struct device *dev) } gtt_write(SOUTH_CHICKEN2, south_chicken2); - pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz; printk(BIOS_INFO, "GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n", refclock / MHz, pwm_increment, pwm_period, @@ -351,7 +353,7 @@ static void gma_setup_panel(struct device *dev) gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); gtt_write(BLC_PWM_PCH_CTL1, - (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } } @@ -525,7 +527,7 @@ static void igd_init(struct device *dev) reg_script_run_on_dev(dev, broadwell_early_init_script); /* Set GFXPAUSE based on stepping */ - if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && + if (cpu_stepping() <= (CPUID_BROADWELL_ULT_E0 & 0xf) && systemagent_revision() <= 9) { gtt_write(0xa000, 0x300ff); } else { diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 39d6cb46924..4999f8f37f8 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _BROADWELL_ACPI_H_ #include -#include /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h deleted file mode 100644 index bc5d2d76bdf..00000000000 --- a/src/soc/intel/broadwell/include/soc/cpu.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_CPU_H_ -#define _BROADWELL_CPU_H_ - -#include -#include -#include - -/* CPU types */ -#define HASWELL_FAMILY_ULT 0x40650 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Supported CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT 0x40651 -#define CPUID_HASWELL_HALO 0x40661 -#define CPUID_BROADWELL_C0 0x306d2 -#define CPUID_BROADWELL_D0 0x306d3 -#define CPUID_BROADWELL_E0 0x306d4 - -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - -/* Latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); - -/* CPU identification */ -static inline u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -static inline u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -#endif diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h deleted file mode 100644 index 6a5f4dc5f17..00000000000 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _BROADWELL_MSR_H_ -#define _BROADWELL_MSR_H_ - -#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_POWER_CTL 0x1fc -#define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -/* Long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - -#define MSR_VR_CURRENT_CONFIG 0x601 -#define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 -#define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -/* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) - -#endif diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index afeed6f53ee..1b6a2316514 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -3,9 +3,8 @@ #ifndef _BROADWELL_NVS_H_ #define _BROADWELL_NVS_H_ -#include +#include #include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -19,7 +18,7 @@ struct __packed global_nvs { u8 lckf; /* 0x08 - Global Lock function for EC */ u8 prm4; /* 0x09 - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */ - u8 pcnt; /* 0x0b - Processor Count */ + u8 unused_was_pcnt; /* 0x0b - Processor Count */ u8 ppcm; /* 0x0c - Max PPC State */ u8 tmps; /* 0x0d - Temperature Sensor ID */ u8 tlvl; /* 0x0e - Throttle Level Limit */ @@ -32,7 +31,7 @@ struct __packed global_nvs { u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ @@ -41,12 +40,10 @@ struct __packed global_nvs { u8 unused2[76]; /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; + u8 chromeos_reserve[0xf00]; /* Device specific (0x1000) */ device_nvs_t dev; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 5d7eceb4a56..4d057ace117 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -7,7 +7,6 @@ #include void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 721e23f5f5a..8a9953b403e 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -5,23 +5,17 @@ #include -struct chipset_power_state; -struct romstage_params { - struct chipset_power_state *power_state; - struct pei_data pei_data; -}; - -void mainboard_pre_raminit(struct romstage_params *params); -void mainboard_post_raminit(struct romstage_params *params); +void mainboard_fill_spd_data(struct pei_data *pei_data); +void mainboard_post_raminit(const int s3resume); -void raminit(struct pei_data *pei_data); +void sdram_initialize(struct pei_data *pei_data); +void save_mrc_data(struct pei_data *pei_data); +void setup_sdram_meminfo(struct pei_data *pei_data); struct chipset_power_state; struct chipset_power_state *fill_power_state(void); void report_platform_info(void); -void set_max_freq(void); - void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void); diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 5f7d43b76a1..43fa0816fc1 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -10,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -461,7 +461,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = &broadwell_init_cpus, + .init = mp_cpu_bus_init, }; static void broadwell_enable(struct device *dev) diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 712bb46f8a3..9a501c3ab60 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -14,13 +14,9 @@ #include #include #include -#include -#include #include -#include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 7ee7e1396e6..b83b957c6cb 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -26,7 +26,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LCKF, 8, // 0x08 - Global Lock function for EC PRM4, 8, // 0x09 - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter - PCNT, 8, // 0x0b - Processor Count + , 8, // 0x0b - Processor Count PPCM, 8, // 0x0c - Max PPC State TMPS, 8, // 0x0d - Temperature Sensor ID TLVL, 8, // 0x0e - Throttle Level Limit diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 91fa75831cd..35b15b427b7 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -6,46 +6,22 @@ #define SIO_BAR_LEN 0x1000 // Put SerialIO device in D0 state -// Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD0, 2, Serialized) +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD0, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS &= 0xFFFFFFFC - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) &= 0xFFFFFFFC + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones } // Put SerialIO device in D3 state -// Arg0 - BAR1 of device -// Arg1 - Set if device is in ACPI mode -Method (LPD3, 2, Serialized) +// Arg0 - Ref to offset 0x84 of device's PCI config space +Method (LPD3, 1, Serialized) { - // PCI mode devices will be handled by OS PCI bus driver - If (Arg1 == 0) { - Return - } - - OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - SPCS |= 0x3 - Local0 = SPCS // Read back after writing + DeRefOf (Arg0) |= 0x3 + Local0 = DeRefOf (Arg0) // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used Local0 &= Ones @@ -238,14 +214,20 @@ Device (I2C0) } } + OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S1B1, \S1EN) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S1B1, \S1EN) + ^^LPD3 (RefOf (SPCS)) } } @@ -309,14 +291,20 @@ Device (I2C1) } } + OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S2B1, \S2EN) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S2B1, \S2EN) + ^^LPD3 (RefOf (SPCS)) } } @@ -365,14 +353,20 @@ Device (SPI0) } } + OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S3B1, \S3EN) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S3B1, \S3EN) + ^^LPD3 (RefOf (SPCS)) } } @@ -433,14 +427,20 @@ Device (SPI1) } } + OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S4B1, \S4EN) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S4B1, \S4EN) + ^^LPD3 (RefOf (SPCS)) } } @@ -501,14 +501,20 @@ Device (UAR0) } } + OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S5B1, \S5EN) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S5B1, \S5EN) + ^^LPD3 (RefOf (SPCS)) } } @@ -557,14 +563,20 @@ Device (UAR1) } } + OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + Method (_PS0, 0, Serialized) { - ^^LPD0 (\S6B1, \S6EN) + ^^LPD0 (RefOf (SPCS)) } Method (_PS3, 0, Serialized) { - ^^LPD3 (\S6B1, \S6EN) + ^^LPD3 (RefOf (SPCS)) } } diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/soc/intel/broadwell/pch/elog.c index 9271e27872f..3f625560dc0 100644 --- a/src/soc/intel/broadwell/pch/elog.c +++ b/src/soc/intel/broadwell/pch/elog.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include #include #include @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -56,7 +56,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip Status */ if (ps->gen_pmcon2 & THERMTRIP_STS) @@ -106,13 +106,10 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) static void pch_log_state(void *unused) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (ps == NULL) { - printk(BIOS_ERR, "Not logging power state information. " - "Power state not found in cbmem.\n"); + if (acpi_pm_state_for_elog(&ps) < 0) return; - } /* Power and Reset */ pch_log_power_and_resets(ps); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 73b83e4e096..cf6e7d71779 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -12,9 +12,6 @@ #include #include #include -#include -#include -#include #include #include #include @@ -593,8 +590,6 @@ static void pch_lpc_add_io_resources(struct device *dev) static void pch_lpc_read_resources(struct device *dev) { - struct global_nvs *gnvs; - /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -603,57 +598,12 @@ static void pch_lpc_read_resources(struct device *dev) /* Add IO resources. */ pch_lpc_add_io_resources(dev); - - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(struct global_nvs)); } -static void southcluster_inject_dsdt(const struct device *device) +void soc_fill_gnvs(struct global_nvs *gnvs) { - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + /* Set unknown wake source */ + gnvs->pm1i = -1; } static unsigned long broadwell_write_acpi_tables(const struct device *device, @@ -672,7 +622,6 @@ static struct device_operations device_ops = { .read_resources = &pch_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, .scan_bus = &scan_static_bus, diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 40a81d88101..88d2172be9d 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -28,10 +28,7 @@ #include #include -#if CONFIG(CHROMEOS) #include -#include -#endif /* Path that the BIOS should take based on ME state */ static const char *me_bios_path_values[] = { @@ -772,10 +769,9 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index c98201e5ab4..b098dc2af40 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -14,7 +15,6 @@ #include #include #include -#include #include /* Low Power variant has 6 root ports. */ diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index cb1d3e5b9ca..12bee7d1279 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -33,7 +33,7 @@ static void migrate_power_state(int is_recovery) ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int prev_sleep_state(struct chipset_power_state *ps) +static int prev_sleep_state(const struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0; diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index fd5d4522fa5..5ed52d8fbd3 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -23,8 +23,6 @@ #include #include -static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -313,7 +311,6 @@ static void southbridge_smi_store(void) static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -333,24 +330,6 @@ static void southbridge_smi_apmc(void) enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/xhci.c index baaf5ba6e6b..fd36fad4a07 100644 --- a/src/soc/intel/broadwell/pch/xhci.c +++ b/src/soc/intel/broadwell/pch/xhci.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -9,7 +10,6 @@ #include #include #include -#include #ifdef __SIMPLE_DEVICE__ static u8 *usb_xhci_mem_base(pci_devfn_t dev) diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 44a89377d47..1c9d440b0a2 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -9,11 +9,6 @@ #include #include #include -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include -#include -#endif -#include #include #include #include @@ -21,6 +16,17 @@ #include #include +void save_mrc_data(struct pei_data *pei_data) +{ + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, + pei_data->data_to_save_size); + + if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) + mrc_cache_stash_data(MRC_TRAINING_DATA, 0, + pei_data->data_to_save, + pei_data->data_to_save_size); +} + static const char *const ecc_decoder[] = { "inactive", "active on IO", @@ -74,10 +80,9 @@ static void report_memory_config(void) /* * Find PEI executable in coreboot filesystem and execute it. */ -void raminit(struct pei_data *pei_data) +void sdram_initialize(struct pei_data *pei_data) { size_t mrc_size; - struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; @@ -130,22 +135,11 @@ void raminit(struct pei_data *pei_data) (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); +} - if (pei_data->boot_mode != ACPI_S3) { - cbmem_initialize_empty(); - } else if (cbmem_initialize()) { - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - system_reset(); - } - - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, - pei_data->data_to_save_size); - - if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) - mrc_cache_stash_data(MRC_TRAINING_DATA, 0, - pei_data->data_to_save, - pei_data->data_to_save_size); +void setup_sdram_meminfo(struct pei_data *pei_data) +{ + struct memory_info *mem_info; printk(BIOS_DEBUG, "create cbmem for dimm information\n"); mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 57abf952078..0078939145d 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include +#include +#include #include #include #include @@ -11,15 +13,11 @@ #include /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ -static void save_acpi_wake_source(struct global_nvs *gnvs) +static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); uint16_t pm1; int gpe_reg; - if (!ps) - return; - pm1 = ps->pm1_sts & ps->pm1_en; /* Scan for first set bit in PM1 */ @@ -61,22 +59,22 @@ static void save_acpi_wake_source(struct global_nvs *gnvs) gnvs->pm1i, gnvs->gpei); } -static void s3_resume_prepare(void) +static void acpi_save_wake_source(void *unused) { - struct global_nvs *gnvs; + const struct chipset_power_state *ps; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (gnvs == NULL) + if (acpi_pm_state_for_wake(&ps) < 0) return; - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(struct global_nvs)); - else - save_acpi_wake_source(gnvs); + pm_fill_gnvs(gnvs, ps); } +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); + void broadwell_init_pre_device(void *chip_info) { - s3_resume_prepare(); broadwell_run_reference_code(); } diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 4ed84d7cea7..018ea24a565 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -5,27 +5,28 @@ #include #include #include +#include #include #include -#include #include #include #include #include +/* FIXME: Needs an update */ static struct { u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_HASWELL_A0, "Haswell A0" }, - { CPUID_HASWELL_B0, "Haswell B0" }, - { CPUID_HASWELL_C0, "Haswell C0" }, - { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, - { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" }, - { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, - { CPUID_BROADWELL_C0, "Broadwell C0" }, - { CPUID_BROADWELL_D0, "Broadwell D0" }, - { CPUID_BROADWELL_E0, "Broadwell E0 or F0" }, + { CPUID_HASWELL_A0, "Haswell A0" }, + { CPUID_HASWELL_B0, "Haswell B0" }, + { CPUID_HASWELL_C0, "Haswell C0" }, + { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, + { CPUID_HASWELL_ULT_C0, "Haswell ULT C0 or D0" }, + { CPUID_CRYSTALWELL_C0, "Haswell Perf Halo" }, + { CPUID_BROADWELL_ULT_C0, "Broadwell C0" }, + { CPUID_BROADWELL_ULT_D0, "Broadwell D0" }, + { CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" }, }; static struct { diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 2e5db76ce9b..33b4e4a02ae 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -2,21 +2,33 @@ #include #include +#include +#include #include +#include #include #include #include #include #include +#include #include #include #include #include +__weak void mainboard_fill_spd_data(struct pei_data *pei_data) +{ +} + +__weak void mainboard_post_raminit(const int s3resume) +{ +} + /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(void) { - struct romstage_params rp = { 0 }; + struct pei_data pei_data = { 0 }; post_code(0x30); @@ -27,9 +39,9 @@ void mainboard_romstage_entry(void) pch_early_init(); /* Get power state */ - rp.power_state = fill_power_state(); + struct chipset_power_state *const power_state = fill_power_state(); - elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); + elog_boot_notify(power_state->prev_sleep_state == ACPI_S3); /* Print useful platform information */ report_platform_info(); @@ -40,28 +52,40 @@ void mainboard_romstage_entry(void) /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); - /* Fill in mainboard pei_date. */ - mainboard_pre_raminit(&rp); + mainboard_fill_pei_data(&pei_data); + mainboard_fill_spd_data(&pei_data); post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); - rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; + pei_data.boot_mode = power_state->prev_sleep_state; /* Print ME state before MRC */ intel_me_status(); /* Save ME HSIO version */ - intel_me_hsio_version(&rp.power_state->hsio_version, - &rp.power_state->hsio_checksum); + intel_me_hsio_version(&power_state->hsio_version, + &power_state->hsio_checksum); /* Initialize RAM */ - raminit(&rp.pei_data); + sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); - romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); + if (pei_data.boot_mode != ACPI_S3) { + cbmem_initialize_empty(); + } else if (cbmem_initialize()) { + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + system_reset(); + } + + save_mrc_data(&pei_data); + + setup_sdram_meminfo(&pei_data); + + romstage_handoff_init(power_state->prev_sleep_state == ACPI_S3); - mainboard_post_raminit(&rp); + mainboard_post_raminit(power_state->prev_sleep_state == ACPI_S3); } diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ea4fadb113d..259a4a04d35 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -1,25 +1,6 @@ config SOC_INTEL_CANNONLAKE_BASE bool -config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS - bool - default y if SOC_INTEL_CANNONLAKE_BASE && !SOC_INTEL_CANNONLAKE - help - Single Kconfig option to select common base Cannonlake support. - This Kconfig will help to select majority of CNL SoC features. - Major difference that exist today between - SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig - are in FSP Header Files. Hence this Kconfig might help to select - required SoC support FSP headers. Any future Intel SoC would - like to make use of CNL support might just select this Kconfig. - -config SOC_INTEL_CANNONLAKE - bool - select SOC_INTEL_CANNONLAKE_BASE - select MICROCODE_BLOB_NOT_IN_BLOB_REPO - help - Intel Cannonlake support - config SOC_INTEL_COFFEELAKE bool select SOC_INTEL_CANNONLAKE_BASE @@ -89,7 +70,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT select HAVE_SMI_HANDLER - select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI @@ -107,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU @@ -338,7 +319,6 @@ config FSP_HEADER_PATH default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2 default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V - default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE config FSP_FD_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE @@ -366,4 +346,16 @@ config INTEL_TXT_BIOSACM_ALIGNMENT hex default 0x40000 # 256KB +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97d0e7..28b5ad0170b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -36,6 +36,7 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c ramstage-y += lockdown.c @@ -107,7 +108,9 @@ else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y) -ifneq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-02 +else # Missing 06-a6-01 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-00 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index f061c30bf4b..bfb719f1c92 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -20,7 +19,6 @@ #include #include #include -#include #include #include "chip.h" @@ -183,7 +181,7 @@ uint32_t soc_read_sci_irq_select(void) return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { const struct soc_intel_cannonlake_config *config; config = config_of_soc(); @@ -191,24 +189,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - /* Update the mem console pointer. */ - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index fafbbfdcda5..f091d8f500a 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -#include +#include /* LPC 0:1f.0 */ #include diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 7d89665dca6..50c0cb8a0cb 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -67,7 +67,7 @@ Device (XHCI) { Name (_ADR, 0x00140000) - Name (_PRW, Package () { GPE0_PME_B0, 3 }) + Name (_PRW, Package () { GPE0_PME_B0, 4 }) Method (_DSW, 3) { @@ -79,6 +79,9 @@ Device (XHCI) Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ + Name (_S4D, 3) /* D3 supported in S4 */ + Name (_S4W, 3) /* D3 can wake system from S4 */ + OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a05e56549c7..a6189881166 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -38,21 +38,12 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static uint32_t get_pmc_reg_base(void) { - uint8_t pch_series; - - pch_series = get_pch_series(); - - if (pch_series == PCH_H) + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H; - else if (pch_series == PCH_LP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; else - return 0; + return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; } static void soc_config_pwrmbase(void) @@ -146,19 +137,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in LPC PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 17698460f72..0958aace024 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -209,6 +210,8 @@ static void soc_enable(struct device *dev) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_cannonlake_ops = { diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 492ebca9c2f..15592d54fae 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -88,9 +89,6 @@ struct soc_intel_cannonlake_config { enum { SaGv_Disabled, SaGv_FixedLow, -#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) - SaGv_FixedMid, -#endif SaGv_FixedHigh, SaGv_Enabled, } SaGv; @@ -437,6 +435,10 @@ struct soc_intel_cannonlake_config { * Only override CPU flex ratio if don't want to boot with non-turbo max. */ uint8_t cpu_ratio_override; + + struct i915_gpu_panel_config panel_cfg; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 61b19894eb1..f4b72abe757 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -177,14 +177,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) msr_t msr1; msr_t msr2; - /* - * CFL and WHL CPU die are based on KBL CPU so we need to - * have this check, where CNL CPU die is not based on KBL CPU - * so skip this check for CNL. - */ - if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)) - return 0; - /* * If PRMRR/SGX is supported the FIT microcode load will set the msr * 0x08b with the Patch revision id one less than the id in the diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 104a78c2aba..4c39988fff0 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -91,7 +91,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -125,7 +125,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 73b1bb53ed4..075c3283cc7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -349,6 +349,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; + else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0) + config->PcieClkSrcUsage[i] = 0; } memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); @@ -524,6 +526,53 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = 0; params->PavpEnable = CONFIG(PAVP); + + /* + * Prevent FSP from programming write-once subsystem IDs by providing + * a custom SSID table. Must have at least one entry for the FSP to + * use the table. + */ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; /* Register offset */ + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t :4; + uint64_t segment:16; + uint64_t :16; + }; + uint64_t segbusdevfuncregister; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t reserved; + }; + + /* + * The xHCI and HDA devices have RW/L rather than RW/O registers for + * subsystem IDs and so must be written before FspSiliconInit locks + * them with their default values. + */ + const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA }; + static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)]; + + for (i = 0; i < ARRAY_SIZE(devfn_table); i++) { + ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; + ssid_table[i].device = PCI_SLOT(devfn_table[i]); + ssid_table[i].function = PCI_FUNC(devfn_table[i]); + dev = pcidev_path_on_root(devfn_table[i]); + if (dev) { + ssid_table[i].svid = dev->subsystem_vendor; + ssid_table[i].ssid = dev->subsystem_device; + } + } + + params->SiSsidTablePtr = (uintptr_t)ssid_table; + params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c new file mode 100644 index 00000000000..93a84c293aa --- /dev/null +++ b/src/soc/intel/cannonlake/graphics.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void graphics_soc_panel_init(struct device *dev) +{ + const struct soc_intel_cannonlake_config *conf = dev->chip_info; + const struct i915_gpu_panel_config *panel_cfg; + const struct resource *mmio_res; + void *mmio; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + if (!conf) + return; + + panel_cfg = &conf->panel_cfg; + + mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + mmio = (void *)(uintptr_t)mmio_res->base; + + /* Panel timings */ + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + /* Backlight */ + if (panel_cfg->backlight_pwm_hz) { + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); + } +} + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_cannonlake_config *const chip = dev->chip_info; + return &chip->gfx; +} diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index c52bc9f5ec4..a510bc51a93 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -31,15 +31,4 @@ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -/* - * This function will help to differentiate between 2 PCH on single type of soc. - * Since same soc may have LP series pch or H series PCH, we need to - * differentiate by reading upper 8 bits of PCH device ids. - * - * Return: - * Return PCH_LP or PCH_H macro in case of respective device ID found. - * PCH_UNKNOWN_SERIES in case of invalid device ID. - */ -uint8_t get_pch_series(void); - #endif diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 0fbb98533a1..768655f7585 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -3,12 +3,10 @@ #ifndef _SOC_CANNONLAKE_PCH_H_ #define _SOC_CANNONLAKE_PCH_H_ -#define PCH_H 1 -#define PCH_LP 2 -#define PCH_UNKNOWN_SERIES 0xFF - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 +/* Converted to 0, allows 0 to be notused */ +#define PCIE_CLK_RP0 0xFE #endif diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 3576d80969e..7b00398a36a 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -103,6 +103,8 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) +#define SLP_S0_RES 0x193c + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) /* * The values for GPIO_CFG in Intel Document #572235 are incorrect. diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117df06..20704e5bc66 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -18,24 +17,9 @@ #include "chip.h" -/* -* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve -* certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() -{ - return cnl_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -43,53 +27,7 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - -uint8_t get_pch_series(void) -{ - uint16_t lpc_did_hi_byte; - uint8_t pch_series = PCH_UNKNOWN_SERIES; - /* - * Fetch upper 8 bits on LPC device ID to determine PCH type - * Adding 1 to the offset to fetch upper 8 bits - */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1); - - switch (lpc_did_hi_byte) { - case 0x9D: /* CNL-LP */ - case 0x02: /* CML-LP */ - pch_series = PCH_LP; - break; - case 0xA3: /* CFL-H */ - case 0x06: /* CML-H */ - pch_series = PCH_H; - break; - default: - break; - } - return pch_series; -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - uint32_t io_dec_arr[] = { - pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { const config_t *config = dev->chip_info; @@ -109,7 +47,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } /* Fill up LPC IO resource structure inside SoC directory */ diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 785283cee25..b2dbfbe6d02 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -7,8 +7,8 @@ #define __SIMPLE_DEVICE__ +#include #include -#include #include #include #include @@ -180,12 +180,10 @@ static int rtc_failed(uint32_t gen_pmcon_b) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon_b); } diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3cd148bc0fd..d55741ffb28 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -73,9 +73,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) m_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); -#endif if (config->cpu_ratio_override) { m_cfg->CpuRatio = config->cpu_ratio_override; diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index cc0e3a848ba..cc44a61bb57 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -11,9 +11,10 @@ #include #include -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 1f855887daf..e3871396c6a 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -169,6 +169,10 @@ static uint16_t load_table(const struct vr_lookup *tbl, * CML-S (35W) GT2 deca 11.1 140(104) 35 * CML-S (35W) GT2 octa 11.1 140(104) 35 * CML-S (35W) GT2 hex 11.1 104 35 + * CML-S (65W) GT2 quad 11.1 102 35 + * CML-S (35W) GT2 quad 11.1 65 35 + * CML-S (58W) GT2 dual 11.1 60 35 + * CML-S (35W) GT2 dual 11.1 55 35 * * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. * The above values in () are for baseline. @@ -297,6 +301,14 @@ VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) { { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) }, { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, }; +VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) { + { 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 102, 35, 35) }, + { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 65, 35, 35) }, +}; +VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) { + { 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 35, 35) }, + { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 35, 35) }, +}; static const struct vr_lookup vr_config_icc[] = { VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U), @@ -326,6 +338,8 @@ static const struct vr_lookup vr_config_icc[] = { VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2), + VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4), + VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2), }; VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U) { @@ -415,6 +429,13 @@ VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) { {125, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) }, { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) }, }; +VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) { + { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) }, +}; +VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) { + { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) }, +}; + static const struct vr_lookup vr_config_ll[] = { VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U), @@ -445,6 +466,8 @@ static const struct vr_lookup vr_config_ll[] = { VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2), VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2), VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2), + VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4), + VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2), }; VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S) { @@ -537,6 +560,14 @@ VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) { { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 104, 28, 28) }, { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28) }, }; +VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) { + { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 68, 28, 28) }, + { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 42, 28, 28) }, +}; +VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) { + { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 38, 28, 28) }, + { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 25, 28, 28) }, +}; static const struct vr_lookup vr_config_tdc[] = { VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S), @@ -558,6 +589,8 @@ static const struct vr_lookup vr_config_tdc[] = { VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2), VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2), VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2), + VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4), + VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2), }; static uint16_t get_sku_voltagelimit(int domain) diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 1a59d040876..f39571ee442 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -2,6 +2,7 @@ config SOC_INTEL_COMMON bool select AZALIA_PLUGIN_SUPPORT select HAVE_DISPLAY_MTRRS + select ACPI_SOC_NVS help common code for Intel SOCs @@ -58,10 +59,6 @@ config MMA_BLOBS_PATH default "3rdparty/blobs/soc/intel/kabylake/mma-blobs" if SOC_INTEL_KABYLAKE default "3rdparty/blobs/soc/intel/skylake/mma-blobs" if SOC_INTEL_SKYLAKE -config SOC_INTEL_COMMON_ACPI - bool - default n - config SOC_INTEL_COMMON_NHLT bool default n diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index 5e38c4b502e..db12e81cd02 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -16,4 +16,4 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); -#endif /* CONFIG_SOC_INTEL_COMMON_ACPI */ +#endif /* _INTEL_COMMON_ACPI_H_ */ diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig index 1c93244573e..9e0f788eb41 100644 --- a/src/soc/intel/common/basecode/Kconfig +++ b/src/soc/intel/common/basecode/Kconfig @@ -2,10 +2,3 @@ config SOC_INTEL_COMMON_BASECODE bool help Common coreboot stages and non-IP block for Intel platform - -if SOC_INTEL_COMMON_BASECODE - -source "src/soc/intel/common/basecode/*/Kconfig" -source "src/soc/intel/common/basecode/*/*/Kconfig" - -endif diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index d9a7a878595..a4f9844c70b 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -5,6 +5,13 @@ config SOC_INTEL_COMMON_BLOCK_ACPI help Intel Processor common code for ACPI +config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + bool + depends on HAVE_ACPI_TABLES + select ACPI_LPIT + help + Generate LPIT table with LPI state entries. + if SOC_INTEL_COMMON_BLOCK_ACPI config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c6bdac5d3eb..4e3a3236253 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index d2177294465..cbc6a58a38a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,20 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include #include #include #include #include #include -#include #include -#include #include #include +#include #include #include #include #include -#include #include #include #include @@ -86,13 +86,34 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } +__weak const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries) +{ + *entries = 0; + return NULL; +} + unsigned long acpi_fill_madt(unsigned long current) { + const struct madt_ioapic_info *ioapic_table; + size_t ioapic_entries; + /* Local APICs */ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); + ioapic_table = soc_get_ioapic_info(&ioapic_entries); + if (ioapic_entries) { + for (int i = 0; i < ioapic_entries; i++) { + current += acpi_create_madt_ioapic( + (void *)current, + ioapic_table[i].id, + ioapic_table[i].addr, + ioapic_table[i].gsi_base); + } + } else { + /* Default SOC IOAPIC entry */ + current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); + } return acpi_madt_irq_overrides(current); } @@ -192,7 +213,7 @@ static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0) uint32_t pm1_en; int i; - ps = cbmem_find(CBMEM_ID_POWER_STATE); + ps = acpi_get_pm_state(); if (ps == NULL) return -1; @@ -215,34 +236,7 @@ static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0) } #endif -__weak void acpi_create_gnvs(struct global_nvs *gnvs) -{ -} - -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); - acpigen_pop_len(); - } -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) +int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio) { u32 m; u32 power; @@ -263,22 +257,6 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return power; } -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - static void generate_c_state_entries(void) { acpi_cstate_t *c_state_map; @@ -360,7 +338,7 @@ void generate_p_state_entries(int core, int cores_per_package) ratio >= ratio_min; ratio -= ratio_step) { /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); + power = common_calculate_power_ratio(power_max, ratio_max, ratio); clock = (ratio * cpu_get_bus_clock()) / KHz; acpigen_write_PSS_package(clock, /* MHz */ @@ -429,21 +407,25 @@ void generate_cpu_entries(const struct device *device) int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; int plen = 6; int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores / cores_per_package; + unsigned int num_virt; + unsigned int num_phys; + + cpu_read_topology(&num_phys, &num_virt); + + int numcpus = totalcores / num_virt; - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + printk(BIOS_DEBUG, "Found %d CPU(s) with %d/%d physical/logical core(s) each.\n", + numcpus, num_phys, num_virt); for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { - for (core_id = 0; core_id < cores_per_package; core_id++) { + for (core_id = 0; core_id < num_virt; core_id++) { if (core_id > 0) { pcontrol_blk = 0; plen = 0; } /* Generate processor \_SB.CPUx */ - acpigen_write_processor((cpu_id) * cores_per_package + + acpigen_write_processor((cpu_id) * num_virt + core_id, pcontrol_blk, plen); /* Generate C-state tables */ @@ -452,17 +434,17 @@ void generate_cpu_entries(const struct device *device) generate_cppc_entries(core_id); /* Soc specific power states generation */ - soc_power_states_generation(core_id, cores_per_package); + soc_power_states_generation(core_id, num_virt); acpigen_pop_len(); } } /* PPKG is usually used for thermal management of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); + acpigen_write_processor_package("PPKG", 0, num_virt); /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); + acpigen_write_processor_cnot(num_virt); } #if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 826e718da89..6a6970f0a06 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -13,13 +13,13 @@ Name (\PICM, 0) // IOAPIC/8259 External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function - PCNT, 8, // 0x03 - Processor Count + , 8, // 0x03 - Processor Count PPCM, 8, // 0x04 - Max PPC State TLVL, 8, // 0x05 - Throttle Level Limit LIDS, 8, // 0x06 - LID State diff --git a/src/soc/intel/common/block/acpi/lpit.c b/src/soc/intel/common/block/acpi/lpit.c new file mode 100644 index 00000000000..5b9689cead1 --- /dev/null +++ b/src/soc/intel/common/block/acpi/lpit.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +unsigned long acpi_fill_lpit(unsigned long current) +{ + uint16_t uid = 0; + acpi_lpi_desc_ncst_t *pkg_counter; + acpi_lpi_desc_ncst_t *sys_counter; + + /* + * Package C10 (PC10) residency counter + */ + pkg_counter = (void *)current; + current += acpi_create_lpi_desc_ncst((void *)current, uid++); + + /* MWAIT LPI state entry trigger */ + pkg_counter->entry_trigger.addrl = 0x60; /* MWAIT(6,0) / HW C10 */ + pkg_counter->entry_trigger.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT; + pkg_counter->entry_trigger.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL; + pkg_counter->entry_trigger.space_id = ACPI_ADDRESS_SPACE_FIXED; + pkg_counter->entry_trigger.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + + /* PC10 residency counter */ + pkg_counter->residency_counter.addrl = MSR_PKG_C10_RESIDENCY; + pkg_counter->residency_counter.bit_offset = 0; + pkg_counter->residency_counter.bit_width = 64; + pkg_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_FIXED; + pkg_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + pkg_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + + /* Min. residency and worst-case latency (from FSP and vendor dumps) */ + pkg_counter->min_residency = 30000; /* break-even: 30 ms */ + pkg_counter->max_latency = 3000; /* worst-case latency: 3 ms */ + + /* + * System (Slp_S0) residency counter + */ + sys_counter = (void *)current; + current += acpi_create_lpi_desc_ncst((void *)current, uid++); + + /* MWAIT LPI state entry trigger */ + sys_counter->entry_trigger.addrl = 0x60; /* MWAIT(6,0) / HW C10 */ + sys_counter->entry_trigger.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT; + sys_counter->entry_trigger.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL; + sys_counter->entry_trigger.space_id = ACPI_ADDRESS_SPACE_FIXED; + sys_counter->entry_trigger.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + + /* Slp_S0 residency counter */ + sys_counter->residency_counter.addrl = PCH_PWRM_BASE_ADDRESS + SLP_S0_RES; + sys_counter->residency_counter.bit_offset = 0; + sys_counter->residency_counter.bit_width = 32; + sys_counter->residency_counter.space_id = ACPI_ADDRESS_SPACE_MEMORY; + sys_counter->residency_counter.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + sys_counter->counter_frequency = ACPI_LPIT_CTR_FREQ_TSC; + + /* Min. residency and worst-case latency (from FSP and vendor dumps) */ + sys_counter->min_residency = 30000; /* break-even: 30 ms */ + sys_counter->max_latency = 3000; /* worst-case latency: 3 ms */ + + return current; +} diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index aaf6af7d5a8..49b40a8d9aa 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,8 @@ #include #include +.section .init, "ax", @progbits + .code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 04dc5331e11..a2e85b9aac8 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -10,6 +10,8 @@ #define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) #define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) +.section .init, "ax", @progbits + .extern temp_ram_init_params .global bootblock_pre_c_entry diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c3fe40bc185..4fd20743438 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -79,6 +79,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_M_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index fec112b7676..70e6763d210 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -16,7 +16,6 @@ config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM config SOC_INTEL_CSE_LITE_SKU bool default n - depends on CHROMEOS select ME_REGION_ALLOW_CPU_READ_ACCESS help Enables CSE Lite SKU diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d10492bbe00..c6f87b41e9a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -910,6 +910,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_CSE1, PCI_DEVICE_ID_INTEL_ADP_S_CSE2, PCI_DEVICE_ID_INTEL_ADP_S_CSE3, + PCI_DEVICE_ID_INTEL_ADP_M_CSE0, + PCI_DEVICE_ID_INTEL_ADP_M_CSE1, + PCI_DEVICE_ID_INTEL_ADP_M_CSE2, + PCI_DEVICE_ID_INTEL_ADP_M_CSE3, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 776a22b553b..edfbce8db68 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -33,6 +33,13 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6, PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7, PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_1, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_2, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_3, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_4, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_5, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_6, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_7, 0, }; diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc index 79a2f975631..2ee64eb0d63 100644 --- a/src/soc/intel/common/block/fast_spi/Makefile.inc +++ b/src/soc/intel/common/block/fast_spi/Makefile.inc @@ -35,7 +35,7 @@ smm-y += mmap_boot.c # Check to ensure that no sections in the FMAP cross 16MiB boundary if # the platform supports split decode windows for BIOS region greater # than 16MiB. -check-fmap-16mib-crossing: $(obj)/fmap_config.h +$(call add_intermediate, check-fmap-16mib-crossing, $(obj)/fmap_config.h) flash_offset=$$(printf "%d" $$(cat $(obj)/fmap_config.h | grep "FMAP_SECTION_FLASH_START" | awk '{print $$NF}')); \ for x in $$(cat $(obj)/fmap_config.h | grep "FMAP_TERMINAL_SECTIONS" | cut -d\" -f2); do \ start=$$(printf "%d" $$(cat $(obj)/fmap_config.h | grep "FMAP_SECTION_"$$x"_START" | awk '{print $$NF}')); \ @@ -46,8 +46,6 @@ check-fmap-16mib-crossing: $(obj)/fmap_config.h done; \ if [ $$fail -eq 1 ]; then false; fi -INTERMEDIATE+=check-fmap-16mib-crossing - CBFSTOOL_ADD_CMD_OPTIONS += --ext-win-base $(CONFIG_EXT_BIOS_WIN_BASE) --ext-win-size $(CONFIG_EXT_BIOS_WIN_SIZE) endif # CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc index b0ffee308ac..0379e92250f 100644 --- a/src/soc/intel/common/block/gpio/Makefile.inc +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -3,3 +3,5 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio_dev.c diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index fb9287c1f76..28e78fb3667 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/intel/common/block/gpio/gpio_dev.c b/src/soc/intel/common/block/gpio/gpio_dev.c new file mode 100644 index 00000000000..c47d3a28ffb --- /dev/null +++ b/src/soc/intel/common/block/gpio/gpio_dev.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static struct gpio_operations gpio_ops = { + .get = gpio_get, + .set = gpio_set, + .input_pulldown = gpio_input_pulldown, + .input_pullup = gpio_input_pullup, + .input = gpio_input, + .output = gpio_output, +}; + +static struct device_operations block_gpio_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .ops_gpio = &gpio_ops, +}; + +void block_gpio_enable(struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_GPIO); + dev->ops = &block_gpio_ops; +} diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index e632cb9bb09..8288150a73f 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -7,3 +7,12 @@ config SOC_INTEL_CONFIGURE_DDI_A_4_LANES bool help Selected by platforms that require DDI-A bifurcation setup. + +config SOC_INTEL_DISABLE_IGD + bool "Disable Integrated GFX Controller (0:2:0)" + default n + select MAINBOARD_NO_FSP_GOP + help + Selected by mainboard user that need to skip IGD initialization + where OS can only use one GPU hence need to disable IGD and don't + need to run FSP GOP. diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index eac38f8f156..7150babc831 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -16,7 +16,7 @@ #include /* SoC Overrides */ -__weak void graphics_soc_init(struct device *dev) +__weak void graphics_soc_panel_init(struct device *dev) { /* * User needs to implement SoC override in case wishes @@ -34,8 +34,12 @@ static void gma_init(struct device *const dev) { intel_gma_init_igd_opregion(); - /* SoC specific configuration. */ - graphics_soc_init(dev); + /* SoC specific panel init/configuration. + If FSP has already run/configured the IGD, we can assume the + panel/backlight control have already been set up sufficiently + and that we shouldn't attempt to reconfigure things. */ + if (!CONFIG(RUN_FSP_GOP)) + graphics_soc_panel_init(dev); if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 836371372a6..395a14dc7bc 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -448,7 +448,6 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) int devfn; uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = ¶ms; - const struct device *device; /* Only chip select 0 is supported. */ if (dev->cs != 0) { @@ -468,14 +467,9 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) } devfn = gspi_soc_bus_to_devfn(p->gspi_bus); - /* - * devfn is already validated as part of gspi_ctrlr_params_init. - * No need to revalidate it again. - */ - device = pcidev_path_on_root(devfn); /* Ensure controller is in D0 state */ - lpss_set_power_state(device, STATE_D0); + lpss_set_power_state(PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)), STATE_D0); /* Take controller out of reset, keeping DMA in reset. */ gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET); diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index e4bcf9913d1..ece06caaebe 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -81,6 +81,13 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_6, PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_7, PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_1, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_2, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_3, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_4, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_5, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_6, + PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_7, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 5aa7729613a..b466de27b19 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -38,7 +38,6 @@ uintptr_t dw_i2c_get_soc_early_base(unsigned int bus) static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; - const struct device *tree_dev; pci_devfn_t dev; int devfn; uintptr_t base; @@ -52,11 +51,6 @@ static int lpss_i2c_early_init_bus(unsigned int bus) /* Look up the controller device in the devicetree */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = pcidev_path_on_root(devfn); - if (!tree_dev || !tree_dev->enabled) { - printk(BIOS_ERR, "I2C%u device not enabled\n", bus); - return -1; - } /* Skip if not enabled for early init */ config = dw_i2c_get_soc_cfg(bus); @@ -75,7 +69,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus) lpss_reset_release(base); /* Ensure controller is in D0 state */ - lpss_set_power_state(tree_dev, STATE_D0); + lpss_set_power_state(dev, STATE_D0); /* Initialize the controller */ if (dw_i2c_init(bus, config) < 0) { @@ -153,7 +147,7 @@ static void dw_i2c_device_init(struct device *dev) return; /* Ensure controller is in D0 state */ - lpss_set_power_state(dev, STATE_D0); + lpss_set_power_state(PCI_BDF(dev), STATE_D0); /* Take device out of reset if its not done before */ if (lpss_is_controller_in_reset(base_address)) @@ -262,6 +256,12 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_I2C3, PCI_DEVICE_ID_INTEL_ADP_S_I2C4, PCI_DEVICE_ID_INTEL_ADP_S_I2C5, + PCI_DEVICE_ID_INTEL_ADP_M_I2C0, + PCI_DEVICE_ID_INTEL_ADP_M_I2C1, + PCI_DEVICE_ID_INTEL_ADP_M_I2C2, + PCI_DEVICE_ID_INTEL_ADP_M_I2C3, + PCI_DEVICE_ID_INTEL_ADP_M_I2C4, + PCI_DEVICE_ID_INTEL_ADP_M_I2C5, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index d058a5db6b8..d76d95ab114 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -63,4 +63,21 @@ void generate_t_state_entries(int core, int cores_per_package); */ void soc_power_states_generation(int core_id, int cores_per_package); +/* + * Common function to calculate the power ratio for power state generation + */ +int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio); + +struct madt_ioapic_info { + u8 id; + u32 addr; + u32 gsi_base; +}; + +/* + * Returns a table of MADT ioapic_info entries and the number of entries + * If the SOC doesn't implement this hook a default ioapic setting is used. + */ +const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 173a383f1e1..4c29a0c5bae 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -25,6 +25,7 @@ #ifndef __ACPI__ #include +#include /* * GPIO numbers may not be contiguous and instead will have a different @@ -222,5 +223,11 @@ void gpi_clear_int_cfg(void); /* The function performs GPIO Power Management programming. */ void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num); +/* + * Set gpio ops of the device to gpio block ops. + * Shall be called by all SoCs that use intelblocks/gpio. + */ +void block_gpio_enable(struct device *dev); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index e65be4a1af3..3669c7733df 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -12,11 +12,11 @@ */ /* - * Perform Graphics Initialization in ramstage + * Perform Graphics/Panel Initialization in ramstage * Input: * struct device *dev: device structure */ -void graphics_soc_init(struct device *dev); +void graphics_soc_panel_init(struct device *dev); /* i915 controller info for ACPI backlight controls */ const struct i915_gpu_controller_info * diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 2fdcdef3e6a..c22eea3ad02 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -13,30 +13,29 @@ * use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range, * the port range is selectable via the IO decodes register. */ -#define LPC_IOE_EC_4E_4F (1 << 13) -#define LPC_IOE_SUPERIO_2E_2F (1 << 12) -#define LPC_IOE_EC_62_66 (1 << 11) -#define LPC_IOE_KBC_60_64 (1 << 10) -#define LPC_IOE_HGE_208 (1 << 9) -#define LPC_IOE_LGE_200 (1 << 8) -#define LPC_IOE_FDD_EN (1 << 3) -#define LPC_IOE_LPT_EN (1 << 2) -#define LPC_IOE_COMB_EN (1 << 1) -#define LPC_IOE_COMA_EN (1 << 0) -#define LPC_NUM_GENERIC_IO_RANGES 4 +#define LPC_IOE_EC_4E_4F (1 << 13) +#define LPC_IOE_SUPERIO_2E_2F (1 << 12) +#define LPC_IOE_EC_62_66 (1 << 11) +#define LPC_IOE_KBC_60_64 (1 << 10) +#define LPC_IOE_HGE_208 (1 << 9) +#define LPC_IOE_LGE_200 (1 << 8) +#define LPC_IOE_FDD_EN (1 << 3) +#define LPC_IOE_LPT_EN (1 << 2) +#define LPC_IOE_COMB_EN (1 << 1) +#define LPC_IOE_COMA_EN (1 << 0) +#define LPC_NUM_GENERIC_IO_RANGES 4 -#define PCR_DMI_LPCLGIR1 0x2730 -#define PCR_DMI_LPCLGIR2 0x2734 -#define PCR_DMI_LPCLGIR3 0x2738 -#define PCR_DMI_LPCLGIR4 0x273c +#define PCR_DMI_LPCLGIR1 0x2730 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 +#define PCR_DMI_LPCGMR 0x2740 + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 /* LPC PCR configuration */ -#define PCR_LPC_PRC 0x341c -#define PCR_LPC_CCE_EN 0xf -#define PCR_LPC_PCE_EN (9 << 8) +#define PCR_LPC_PRC 0x341c +#define PCR_LPC_CCE_EN 0xf +#define PCR_LPC_PCE_EN (9 << 8) /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ enum serirq_mode { @@ -45,11 +44,6 @@ enum serirq_mode { SERIRQ_OFF, }; -struct lpc_mmio_range { - uintptr_t base; - size_t size; -}; - /* * Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. * Output:I/O Enable Bits @@ -61,21 +55,13 @@ uint16_t lpc_get_fixed_io_decode(void); uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask); /* Open a generic IO window to the LPC bus. Four windows are available. */ void lpc_open_pmio_window(uint16_t base, uint16_t size); -/* Close all generic IO windows to the LPC bus. */ -void lpc_close_pmio_windows(void); /* Open a generic MMIO window to the LPC bus. One window is available. */ void lpc_open_mmio_window(uintptr_t base, size_t size); -/* Returns true if given window is decoded to LPC via a fixed range. */ -bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size); /* Init SoC Specific LPC features. Common definition will be weak and each soc will need to define the init. */ void lpc_soc_init(struct device *dev); /* Fill up LPC IO resource structure inside SoC directory */ void pch_lpc_soc_fill_io_resources(struct device *dev); -/* Init LPC GPIO pads */ -void lpc_configure_pads(void); -/* Get SoC specific MMIO ranges */ -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void); /* Set LPC BIOS Control BILD bit. */ void lpc_set_bios_interface_lock_down(void); /* Set LPC BIOS Control LE bit. */ @@ -98,10 +84,7 @@ void lpc_io_setup_comm_a_b(void); /* Enable PCH LPC by setting up generic decode range registers. */ void pch_enable_lpc(void); /* Get SoC's generic IO decoder range register settings. */ -void soc_get_gen_io_dec_range(const struct device *dev, - uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); -/* Mirror generic IO decoder range register settings into DMI PCR. */ -void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 145857c192e..8d22e7a53e5 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -25,7 +25,7 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); bool lpss_is_controller_in_reset(uintptr_t base); /* Set controller power state to D0 or D3*/ -void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state); +void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); /* * Handler to get list of LPSS controllers. The SOC is expected to send out a diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h new file mode 100644 index 00000000000..cbec04ddb21 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/meminit.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_INTEL_COMMON_BLOCK_MEMINIT_H__ +#define __SOC_INTEL_COMMON_BLOCK_MEMINIT_H__ + +#include +#include +#include + +/* + * Calculates the number of channels depending upon the data bus width of the + * platform and the channel width. + */ +#define CHANNEL_COUNT(ch_width) (CONFIG_DATA_BUS_WIDTH / (ch_width)) + +/* + * UPDs for FSP-M are organized depending upon the MRC's view of channel. Thus, + * the number of channels as seen by the MRC are dependent on the channel width + * assumption in the UPDs. These channels might not necessarily be the same as + * the physical channels supported by the platform. + */ +#define MRC_CHANNELS CHANNEL_COUNT(CONFIG_MRC_CHANNEL_WIDTH) + +/* Different memory topologies supported by the platform. */ +enum mem_topology { + MEM_TOPO_MEMORY_DOWN = BIT(0), + MEM_TOPO_DIMM_MODULE = BIT(1), + MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE, +}; + +/* + * SPD provides information about the memory module. Depending upon the memory + * topology, the SPD data can be obtained from different sources. Example: for + * memory down topology, SPD is read from CBFS using cbfs_index. For DIMM + * modules, SPD is read from EEPROM using the DIMM addresses provided by the + * mainboard. + */ +struct mem_spd { + enum mem_topology topo; + /* + * SPD data is read from CBFS spd.bin file using cbfs_index to locate + * the entry. This is used in case of MEM_TOPO_MEMORY_DOWN and + * MEM_TOPO_MIXED topologies. + */ + size_t cbfs_index; + + /* + * SPD data is read from on-module EEPROM using the DIMM addresses + * provided by the mainboard. This is used in case of + * MEM_TOPO_DIMM_MODULE and MEM_TOPO_MIXED topologies. + * + * Up to a maximum of MRC_CHANNELS * CONFIG_DIMMS_PER_CHANNEL addresses + * can be provided by mainboard. However, depending upon the memory + * technology being used and the number of physical channels supported + * by that technology, the actual channels might be less than + * MRC_CHANNELS. + */ + struct { + uint8_t addr_dimm[CONFIG_DIMMS_PER_CHANNEL]; + } smbus[MRC_CHANNELS]; +}; + +/* Information about memory technology supported by SoC */ +struct soc_mem_cfg { + /* + * Number of physical channels that are supported by the memory + * technology. + */ + size_t num_phys_channels; + + /* + * Map of physical channel numbers to MRC channel numbers. This is + * helpful in identifying what SPD entries need to be filled for a + * physical channel. + * + * Example: MRC supports 8 channels 0 - 7, but a memory technology + * supports only 2 physical channels 0 - 1. In this case, the map could + * be: + * [0] = 0, + * [1] = 4, + * indicating that physical channel 0 is mapped to MRC channel 0 and + * physical channel 1 is mapped to MRC channel 4. + */ + size_t phys_to_mrc_map[MRC_CHANNELS]; + + /* + * Masks to be applied in case of memory down topology. For memory down + * topology, there is no separate EEPROM. Thus, the masks need to be + * hard-coded by the SoC to indicate what combinations are supported. + * This is a mask of physical channels for the memory technology. + * + * Example: For the memory technology supporting 2 physical channels, + * where the population rules restrict use of channel 0 for + * half-channel, half_channel mask would be set to 0x1 indicating + * channel 0 is always populated. + */ + struct { + /* + * Mask of physical channels that are populated in case of + * half-channel configuration. + */ + uint32_t half_channel; + /* + * Mask of physical channels that are populated with memory + * down parts in case of mixed topology. + */ + uint32_t mixed_topo; + } md_phy_masks; +}; + +/* Flags indicating how the channels are populated. */ +enum channel_population { + NO_CHANNEL_POPULATED = 0, + TOP_HALF_POPULATED = BIT(0), + BOTTOM_HALF_POPULATED = BIT(1), + FULLY_POPULATED = TOP_HALF_POPULATED | BOTTOM_HALF_POPULATED, +}; + +/* + * Data for the memory channels that can be used by SoC code to populate FSP + * UPDs. + */ +struct mem_channel_data { + /* Pointer to SPD data for each DIMM of each channel */ + uintptr_t spd[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL]; + /* Length of SPD data */ + size_t spd_len; + /* Flags indicating how channels are populated */ + enum channel_population ch_population_flags; +}; + +/* + * This change populates data regarding memory channels in `struct + * mem_channel_data` using the following inputs from SoC code: + * soc_mem_cfg : SoC-specific information about the memory technology used by + * the mainboard. + * spd_info : Information about the memory topology. + * half_populated: Hint from mainboard if channels are half populated. + */ +void mem_populate_channel_data(const struct soc_mem_cfg *soc_mem_cfg, + const struct mem_spd *spd_info, + bool half_populated, + struct mem_channel_data *data); + +/* + * Given a channel number and the maximum number of supported channels, this + * function returns if a channel is populated. This is useful for populating + * DQ/DQS UPDs by the SoC code. + */ +static inline bool channel_is_populated(size_t curr_ch, size_t max_ch, + enum channel_population flags) +{ + if ((curr_ch * 2) < max_ch) + return !!(flags & BOTTOM_HALF_POPULATED); + + return !!(flags & TOP_HALF_POPULATED); +} + +#endif /* __SOC_INTEL_COMMON_BLOCK_MEMINIT_H__ */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 96b3c0a2c81..7dc85df24ef 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_ELKHARTLAKE_B0 0x90661 #define CPUID_ALDERLAKE_S_A0 0x90670 #define CPUID_ALDERLAKE_P_A0 0x906a0 +#define CPUID_ALDERLAKE_M_A0 0x906a1 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index cc240c57606..abc34009124 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -3,19 +3,18 @@ #ifndef SOC_INTEL_COMMON_BLOCK_NVS_H #define SOC_INTEL_COMMON_BLOCK_NVS_H -#include -#include +#include struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - 0x01 Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 pcnt; /* 0x03 - Processor Count */ + u8 unused_was_pcnt; /* 0x03 - Processor Count */ u8 ppcm; /* 0x04 - Max PPC State */ u8 tlvl; /* 0x05 - Throttle Level Limit */ u8 lids; /* 0x06 - LID State */ u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ + u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ u8 dpte; /* 0x1c - Enable DPTF */ @@ -27,12 +26,6 @@ struct __packed global_nvs { u8 uior; /* 0x2f - UART debug controller init on S3 resume */ u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ - u8 unused[192]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index ca50b13247a..d51b1f1c263 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -3,20 +3,34 @@ #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H +#include + /* * The PCIe Root Ports usually come in groups of up to 8 PCI-device * functions. * * `slot` is the PCI device/slot number of such a group. - * `count` is the number of functions within the group. It is assumed that - * the first group includes the RPs 1 to the first group's `count` and that - * adjacent groups follow without gaps in the numbering. + * `start` is the initial PCI function number within the group. This is useful + * in case the root port numbers are not contiguous within the slot. + * `count` is the number of functions within the group starting with the `start` + * function number. */ struct pcie_rp_group { unsigned int slot; + unsigned int start; unsigned int count; }; +static inline unsigned int rp_start_fn(const struct pcie_rp_group *group) +{ + return group->start; +} + +static inline unsigned int rp_end_fn(const struct pcie_rp_group *group) +{ + return group->start + group->count - 1; +} + /* * Update PCI paths of the root ports in the devicetree. * @@ -31,7 +45,30 @@ struct pcie_rp_group { * enumeration. * * `groups` points to a list of groups terminated by an entry with `count == 0`. + * It is assumed that the first group includes the RPs 1 to the first group's + * `count` and that adjacent groups follow without gaps in the numbering. */ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); +/* + * Return mask of PCIe root ports that are enabled by mainboard. Mask is set in + * the same order as the root ports in pcie_rp_group groups table. + * + * Thus, the status of first root port in the groups table is indicated by bit 0 + * in the returned mask, second root port by bit 1 and so on. + + * 1 in the bit position indicates root port is enabled, whereas 0 indicates root + * port is disabled. This function assumes that the maximum count of root ports + * in the groups table is <= 32. + */ +uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); + +/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */ +enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index fbf9a6ee0e4..71adf5bb9bd 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -58,7 +58,7 @@ enum cb_err pmc_send_ipc_cmd(uint32_t cmd, const struct pmc_ipc_buffer *wbuf, * Provides an ACPI method in the SSDT to read/write to the IPC mailbox which is * defined in the PMC device MMIO address space. * - * One possible use of this method is to to enable/disable the clock for a + * One possible use of this method is to enable/disable the clock for a * particular PCIe root port at runtime when the device is in D3 state. * * The ACPI method takes 7 arguments: diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index 87fdf688687..c3a22bc96b4 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -10,8 +10,10 @@ #define MAX_GPIO_PAD_PER_UART 2 -struct uart_gpio_pad_config { +struct uart_controller_config { int console_index; + /* devfn in PCI_DEVFN() format */ + unsigned int devfn; struct pad_config gpios[MAX_GPIO_PAD_PER_UART]; }; @@ -23,12 +25,6 @@ struct uart_gpio_pad_config { * 4. SOC will allow common code to set UART into legacy mode if supported. */ -/* - * Common routine to initialize UART controller PCI config space, take it out of - * reset and configure M/N dividers. - */ -void uart_common_init(const struct device *dev, uintptr_t baseaddr); - /* * Check if UART debug controller is initialized * Returns: @@ -61,21 +57,4 @@ void uart_bootblock_init(void); */ const struct device *uart_get_device(void); -/**************************** SoC callbacks ***********************************/ - -/* - * SoC should implement soc_uart_console_to_device() function to - * get UART debug controller device structure based on console number - * Caller needs to check proper UART console index supported by SoC. - * If wrong UART console index is passed to function, it'll return NULL. - * - * Input: - * UART console index selected in config - * - * Returns: - * Pointer to device structure = If device has a UART debug controller. - * NULL = otherwise - */ -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console); - #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index 4ae01f8f032..e918651e59e 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -120,7 +120,7 @@ void itss_restore_irq_polarities(int start, int end) if (end < irq_start) break; - /* Track bits within the bounds of of the register. */ + /* Track bits within the bounds of the register. */ irq_start = MAX(start, irq_start) % IRQS_PER_IPC; irq_end = MIN(end, irq_end) % IRQS_PER_IPC; diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index 41e72c474a3..d76620af6fa 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -11,3 +11,10 @@ config SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE help By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection. + +config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI + bool + depends on SOC_INTEL_COMMON_BLOCK_DMI + help + Mirror LPC registers for IO/MMIO to their corresponding DMI registers. + Required for platforms starting from SPT. diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 369b6b1911d..7bdc2b0b494 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -59,14 +59,6 @@ static void pch_lpc_loop_resources(struct device *dev) for (res = dev->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_IO) lpc_open_pmio_window(res->base, res->size); - - if (res->flags & IORESOURCE_MEM) { - /* Check if this is already decoded. */ - if (lpc_fits_fixed_mmio_window(res->base, res->size)) - continue; - - lpc_open_mmio_window(res->base, res->size); - } } pch_lpc_set_child_resources(dev); } @@ -107,7 +99,6 @@ static struct device_operations device_ops = { .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = southbridge_write_acpi_tables, - .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_name = lpc_acpi_name, #endif .init = lpc_soc_init, @@ -273,6 +264,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, @@ -306,6 +299,37 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_0, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_1, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_2, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_3, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_4, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_5, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_7, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_8, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_9, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_10, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_11, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_12, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_13, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_14, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_15, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_16, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_17, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_18, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_19, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_20, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_21, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_22, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_23, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_24, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_25, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_26, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_27, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_28, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31, 0 }; diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 775316986a6..ab9f2018c5e 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -7,8 +7,10 @@ #define LPC_SCNT_EN (1 << 7) #define LPC_SCNT_MODE (1 << 6) #define LPC_IO_DECODE 0x80 -#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/ -#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/ +#define LPC_IOD_COMA_RANGE_MASK (7 << 0) +#define LPC_IOD_COMB_RANGE_MASK (7 << 4) +#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA */ +#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB */ /* Use IO__ style macros defined in lpc_lib.h * to enable decoding of I/O locations for a peripheral. */ #define LPC_IO_ENABLES 0x82 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 67dd6614603..73a472799f1 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -9,10 +9,12 @@ #include #include #include +#include #include #include "lpc_def.h" #include #include +#include uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) { @@ -21,6 +23,8 @@ uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); return io_enables; } @@ -37,6 +41,8 @@ uint16_t lpc_set_fixed_io_ranges(uint16_t io_ranges, uint16_t mask) reg_io_ranges = lpc_get_fixed_io_decode() & ~mask; io_ranges |= reg_io_ranges & mask; pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); return io_ranges; } @@ -60,14 +66,6 @@ static int find_unused_pmio_window(void) return -1; } -void lpc_close_pmio_windows(void) -{ - size_t i; - - for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) - pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), 0); -} - void lpc_open_pmio_window(uint16_t base, uint16_t size) { int i, lgir_reg_num; @@ -113,6 +111,8 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size) lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); printk(BIOS_DEBUG, "LPC: Opened IO window LGIR%d: base %llx size %x\n", @@ -146,28 +146,8 @@ void lpc_open_mmio_window(uintptr_t base, size_t size) lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); -} - -bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size) -{ - resource_t res_end, range_end; - const struct lpc_mmio_range *range; - const struct lpc_mmio_range *lpc_fixed_mmio_ranges = - soc_get_fixed_mmio_ranges(); - - for (range = lpc_fixed_mmio_ranges; range->size; range++) { - range_end = range->base + range->size; - res_end = base + size; - - if ((base >= range->base) && (res_end <= range_end)) { - printk(BIOS_DEBUG, - "Resource %lx size %zx fits in fixed window" - " %lx size %zx\n", - base, size, range->base, range->size); - return true; - } - } - return false; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); } /* @@ -244,15 +224,17 @@ void lpc_io_setup_comm_a_b(void) /* ComA Range 3F8h-3FFh [2:0] */ uint16_t com_ranges = LPC_IOD_COMA_RANGE; uint16_t com_enable = LPC_IOE_COMA_EN; + uint16_t com_mask = LPC_IOD_COMA_RANGE_MASK; /* ComB Range 2F8h-2FFh [6:4] */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { com_ranges |= LPC_IOD_COMB_RANGE; com_enable |= LPC_IOE_COMB_EN; + com_mask |= LPC_IOD_COMB_RANGE_MASK; } /* Setup I/O Decode Range Register for LPC */ - pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges); + lpc_set_fixed_io_ranges(com_ranges, com_mask); /* Enable ComA and ComB Port */ lpc_enable_fixed_io_ranges(com_enable); } @@ -263,24 +245,19 @@ static void lpc_set_gen_decode_range( size_t i; /* Set in PCI generic decode range registers */ - for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) - pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), - gen_io_dec[i]); + for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { + pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); + } } void pch_enable_lpc(void) { - /* Lookup device tree in romstage */ - const struct device *dev; uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); - if (!dev) - return; - - soc_get_gen_io_dec_range(dev, gen_io_dec); + soc_get_gen_io_dec_range(gen_io_dec); lpc_set_gen_decode_range(gen_io_dec); - soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) pch_pirq_init(); } diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 74c7aa15dce..6e33c0f94fe 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -65,16 +65,12 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val) } /* Set controller power state to D0 or D3 */ -void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state) +void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state) { -#if defined(__SIMPLE_DEVICE__) - unsigned int devfn = dev->path.pci.devfn; - pci_devfn_t lpss_dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); -#else - const struct device *lpss_dev = dev; -#endif - - pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state); + uint8_t reg8 = pci_s_read_config8(devfn, PME_CTRL_STATUS); + reg8 &= ~POWER_STATE_MASK; + reg8 |= state; + pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8); } bool is_dev_lpss(const struct device *dev) diff --git a/src/soc/intel/common/block/memory/Kconfig b/src/soc/intel/common/block/memory/Kconfig new file mode 100644 index 00000000000..fdcccbf742d --- /dev/null +++ b/src/soc/intel/common/block/memory/Kconfig @@ -0,0 +1,31 @@ +config SOC_INTEL_COMMON_BLOCK_MEMINIT + bool + help + Intel common block support for performing initialization + of FSPM UPDs. + +if SOC_INTEL_COMMON_BLOCK_MEMINIT + +config DIMMS_PER_CHANNEL + int + default 0 + help + Maximum number of DIMMs per channel if the memory controller + supports DIMM modules for any memory technology. + +config DATA_BUS_WIDTH + int + default 0 + help + Data bus width of the platform. + +config MRC_CHANNEL_WIDTH + int + default 0 + help + Width of the memory channel from the perspective of MRC. This + determines the UPD organization. SoC using this common block + support is expected to set MRC_CHANNEL_WIDTH as per the FSP + MRC expectation. + +endif diff --git a/src/soc/intel/common/block/memory/Makefile.inc b/src/soc/intel/common/block/memory/Makefile.inc new file mode 100644 index 00000000000..1009872702b --- /dev/null +++ b/src/soc/intel/common/block/memory/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_MEMINIT) += meminit.c diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c new file mode 100644 index 00000000000..84987d612be --- /dev/null +++ b/src/soc/intel/common/block/memory/meminit.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +_Static_assert(CONFIG_MRC_CHANNEL_WIDTH > 0, "MRC channel width must be >0!"); +_Static_assert(CONFIG_DATA_BUS_WIDTH > 0, "Data bus width must be >0!"); +_Static_assert(CONFIG_DIMMS_PER_CHANNEL > 0, "DIMMS per channel must be >0!"); + +/* + * Given mask of channels that are populated, this function returns the flags + * indicating which half of the channels are populated. + */ +static enum channel_population populated_mask_to_flag(uint32_t pop_mask, size_t max_channels) +{ + uint32_t full_mask = BIT(max_channels) - 1; + uint32_t bottom_mask = BIT(max_channels / 2) - 1; + uint32_t top_mask = ~bottom_mask & full_mask; + + if (pop_mask == full_mask) + return FULLY_POPULATED; + else if (pop_mask == bottom_mask) + return BOTTOM_HALF_POPULATED; + else if (pop_mask == top_mask) + return TOP_HALF_POPULATED; + else if (pop_mask == 0) + return NO_CHANNEL_POPULATED; + + die("Unsupported channel population mask(0x%x)\n", pop_mask); +} + +static void read_spd_md(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *info, + bool half_populated, struct mem_channel_data *channel_data, + size_t *spd_len) +{ + size_t ch; + size_t num_phys_ch = soc_mem_cfg->num_phys_channels; + struct region_device spd_rdev; + uintptr_t spd_data; + + /* + * For memory down topologies, start with full mask as per the number + * of physical channels and mask out any channels based on mixed + * topology or half populated flag as set by the mainboard. + */ + uint32_t pop_mask = BIT(num_phys_ch) - 1; + + if (!(info->topo & MEM_TOPO_MEMORY_DOWN)) + return; + + if (info->topo == MEM_TOPO_MIXED) + pop_mask &= soc_mem_cfg->md_phy_masks.mixed_topo; + + if (half_populated) + pop_mask &= soc_mem_cfg->md_phy_masks.half_channel; + + if (pop_mask == 0) + die("Memory technology does not support the selected configuration!\n"); + + printk(BIOS_DEBUG, "SPD index = %zu\n", info->cbfs_index); + + if (get_spd_cbfs_rdev(&spd_rdev, info->cbfs_index) < 0) + die("SPD not found in CBFS or incorrect index!\n"); + + /* Memory leak is ok as long as we have memory mapped boot media */ + _Static_assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED), + "Function assumes memory-mapped boot media"); + + spd_data = (uintptr_t)rdev_mmap_full(&spd_rdev); + *spd_len = region_device_sz(&spd_rdev); + + print_spd_info((uint8_t *)spd_data); + + for (ch = 0; ch < num_phys_ch; ch++) { + if (!(pop_mask & BIT(ch))) + continue; + + int mrc_ch = soc_mem_cfg->phys_to_mrc_map[ch]; + + /* + * Memory down topology simulates a DIMM. So, the assumption is + * that there is a single DIMM per channel when using memory + * down topology. As SPD describes a DIMM, only DIMM0 for each + * physical channel is filled here. + */ + channel_data->spd[mrc_ch][0] = spd_data; + } + + channel_data->ch_population_flags |= populated_mask_to_flag(pop_mask, num_phys_ch); +} + +#define CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) + +static void read_spd_dimm(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *info, + bool half_populated, struct mem_channel_data *channel_data, + size_t *spd_len) +{ + size_t ch, dimm; + struct spd_block blk = { 0 }; + size_t num_phys_ch = soc_mem_cfg->num_phys_channels; + + /* + * For DIMM modules, start with mask set to no channels populated. If + * SPD is read successfully from EEPROM for any channel, then that + * channel is marked as populated. + */ + uint32_t pop_mask = 0; + + if (!(info->topo & MEM_TOPO_DIMM_MODULE)) + return; + + for (ch = 0; ch < num_phys_ch; ch++) { + for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + blk.addr_map[CH_DIMM_OFFSET(ch, dimm)] = + info->smbus[ch].addr_dimm[dimm]; + } + } + + get_spd_smbus(&blk); + *spd_len = blk.len; + + for (ch = 0; ch < num_phys_ch; ch++) { + size_t mrc_ch = soc_mem_cfg->phys_to_mrc_map[ch]; + + for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + uint8_t *spd_data = blk.spd_array[CH_DIMM_OFFSET(ch, dimm)]; + if (spd_data == NULL) + continue; + + print_spd_info(spd_data); + + channel_data->spd[mrc_ch][dimm] = (uintptr_t)(void *)spd_data; + pop_mask |= BIT(ch); + } + } + + channel_data->ch_population_flags |= populated_mask_to_flag(pop_mask, num_phys_ch); +} + +void mem_populate_channel_data(const struct soc_mem_cfg *soc_mem_cfg, + const struct mem_spd *spd_info, + bool half_populated, + struct mem_channel_data *data) +{ + size_t spd_md_len = 0, spd_dimm_len = 0; + + memset(data, 0, sizeof(*data)); + + read_spd_md(soc_mem_cfg, spd_info, half_populated, data, &spd_md_len); + read_spd_dimm(soc_mem_cfg, spd_info, half_populated, data, &spd_dimm_len); + + if (data->ch_population_flags == NO_CHANNEL_POPULATED) + die("No channels are populated. Incorrect memory configuration!\n"); + + if (spd_info->topo == MEM_TOPO_MEMORY_DOWN) { + data->spd_len = spd_md_len; + } else if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { + data->spd_len = spd_dimm_len; + } else { + /* + * SPD lengths must match for CBFS and EEPROM SPD for mixed + * topology. + */ + if (spd_md_len != spd_dimm_len) + die("Length of SPD does not match for mixed topology!\n"); + } +} diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 05bef2bc4e8..18c958e84d7 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -193,6 +193,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_P2SB, PCI_DEVICE_ID_INTEL_ADP_P_P2SB, PCI_DEVICE_ID_INTEL_ADP_S_P2SB, + PCI_DEVICE_ID_INTEL_ADP_M_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index e2ad685bc34..521ca6b37ed 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1,4 +1,7 @@ subdirs-y += ./* +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index e5069052836..4f5687fd5f9 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -331,6 +331,16 @@ static const unsigned short pcie_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP26, PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27, PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP10, 0 }; diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c new file mode 100644 index 00000000000..e8ed3be56d9 --- /dev/null +++ b/src/soc/intel/common/block/pcie/pcie_helpers.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static uint32_t pcie_slot_enable_mask(const struct pcie_rp_group *group) +{ + uint32_t mask = 0; + unsigned int fn; + unsigned int i; + const struct device *dev; + + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + dev = pcidev_on_root(group->slot, fn); + if (is_dev_enabled(dev)) + mask |= BIT(i); + } + + return mask; +} + +uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups) +{ + uint32_t mask = 0; + uint32_t offset = 0; + const struct pcie_rp_group *group; + + for (group = groups; group->count; ++group) { + if (group->count + offset >= sizeof(mask) * 8) { + printk(BIOS_ERR, "ERROR: %s: Root port count greater than mask size!\n", + __func__); + break; + } + mask |= pcie_slot_enable_mask(group) << offset; + offset += group->count; + } + + return mask; +} diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 85b218a4abd..1c69f2c3551 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -54,7 +54,7 @@ static void pcie_rp_scan_groups(int mapping[], const struct pcie_rp_group *const const struct pcie_rp_group *group; for (group = groups; group->count; ++group) { unsigned int fn; - for (fn = 0; fn < group->count; ++fn) { + for (fn = rp_start_fn(group); fn <= rp_end_fn(group); ++fn) { const pci_devfn_t dev = PCI_DEV(0, group->slot, fn); const uint16_t did = pci_s_read_config16(dev, PCI_DEVICE_ID); if (did == 0xffff) { @@ -96,7 +96,8 @@ static bool pcie_rp_update_dev( const struct pcie_rp_group *group; for (group = groups; group->count; ++group) { if (PCI_SLOT(dev->path.pci.devfn) == group->slot && - PCI_FUNC(dev->path.pci.devfn) < group->count) + PCI_FUNC(dev->path.pci.devfn) >= rp_start_fn(group) && + PCI_FUNC(dev->path.pci.devfn) <= rp_end_fn(group)) break; offset += group->count; } diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index fe4dca6fa4f..93cbe3692cb 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -99,6 +99,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_PMC, PCI_DEVICE_ID_INTEL_ADP_P_PMC, PCI_DEVICE_ID_INTEL_ADP_S_PMC, + PCI_DEVICE_ID_INTEL_ADP_M_PMC, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 09af749073b..3b7aa0a1693 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -56,7 +57,7 @@ struct chipset_power_state *pmc_get_power_state(void) struct chipset_power_state *ptr = NULL; if (cbmem_possibly_online()) - ptr = cbmem_find(CBMEM_ID_POWER_STATE); + ptr = acpi_get_pm_state(); /* cbmem is online but ptr is not populated yet */ if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 7b234a95004..71c023f9fa5 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -59,6 +59,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_SATA_4, PCI_DEVICE_ID_INTEL_ADP_S_SATA_5, PCI_DEVICE_ID_INTEL_ADP_S_SATA_6, + PCI_DEVICE_ID_INTEL_ADP_M_SATA_1, + PCI_DEVICE_ID_INTEL_ADP_M_SATA_2, + PCI_DEVICE_ID_INTEL_ADP_M_SATA_3, 0 }; diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 8679f1f011c..336ed54f062 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -11,6 +11,7 @@ #include #include #include +#include #include static inline uint64_t sgx_resource(uint32_t low, uint32_t high) diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 59870fbdc84..bc906a6ad19 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -90,6 +90,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_SMBUS, PCI_DEVICE_ID_INTEL_ADP_P_SMBUS, PCI_DEVICE_ID_INTEL_ADP_S_SMBUS, + PCI_DEVICE_ID_INTEL_ADP_M_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index dc329702672..51a30031955 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -330,8 +330,6 @@ void smihandler_southbridge_apmc( const struct smm_save_state_ops *save_state_ops) { uint8_t reg8; - void *state = NULL; - static int smm_initialized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -361,25 +359,6 @@ void smihandler_southbridge_apmc( pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs *)(uintptr_t)reg_ebx; - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(save_state_ops); diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 295df09ed8b..beac64cb69a 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -89,6 +89,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ADP_P_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ADP_S_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_ADP_M_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ADP_P_SPI0, PCI_DEVICE_ID_INTEL_ADP_P_SPI1, PCI_DEVICE_ID_INTEL_ADP_P_SPI2, @@ -103,6 +104,9 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_S_SPI4, PCI_DEVICE_ID_INTEL_ADP_S_SPI5, PCI_DEVICE_ID_INTEL_ADP_S_SPI6, + PCI_DEVICE_ID_INTEL_ADP_M_SPI0, + PCI_DEVICE_ID_INTEL_ADP_M_SPI1, + PCI_DEVICE_ID_INTEL_ADP_M_SPI2, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 426a5f75aea..a9a96edda84 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_SRAM, PCI_DEVICE_ID_INTEL_ADP_P_SRAM, PCI_DEVICE_ID_INTEL_ADP_S_SRAM, + PCI_DEVICE_ID_INTEL_ADP_M_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 6b039e1c01b..ec26fce5baa 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 142a9365a96..4a84935ad4a 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -20,10 +20,10 @@ #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) #define UART_CONSOLE_INVALID_INDEX 0xFF -extern const struct uart_gpio_pad_config uart_gpio_pads[]; -extern const int uart_max_index; +extern const struct uart_controller_config uart_ctrlr_config[]; +extern const int uart_ctrlr_config_size; -static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) +static void uart_lpss_init(pci_devfn_t dev, uintptr_t baseaddr) { /* Ensure controller is in D0 state */ lpss_set_power_state(dev, STATE_D0); @@ -49,8 +49,8 @@ static int uart_get_valid_index(void) { int index; - for (index = 0; index < uart_max_index; index++) { - if (uart_gpio_pads[index].console_index == + for (index = 0; index < uart_ctrlr_config_size; index++) { + if (uart_ctrlr_config[index].console_index == CONFIG_UART_FOR_CONSOLE) return index; } @@ -58,60 +58,49 @@ static int uart_get_valid_index(void) return UART_CONSOLE_INVALID_INDEX; } -void uart_common_init(const struct device *device, uintptr_t baseaddr) +static pci_devfn_t uart_console_get_pci_bdf(void) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_BDF(device); -#else - const struct device *dev = device; -#endif - - /* Set UART base address */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); - - /* Enable memory access and bus master */ - pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); - - uart_lpss_init(device, baseaddr); -} + int devfn; + int index; -const struct device *uart_get_device(void) -{ /* * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE * config option is not selected. * By default return NULL in this case to avoid compilation errors. */ if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) - return NULL; + return PCI_DEV_INVALID; - int console_index = uart_get_valid_index(); + index = uart_get_valid_index(); + if (index == UART_CONSOLE_INVALID_INDEX) + return PCI_DEV_INVALID; - if (console_index != UART_CONSOLE_INVALID_INDEX) - return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE); - else + devfn = uart_ctrlr_config[index].devfn; + return PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); +} + +const struct device *uart_get_device(void) +{ + pci_devfn_t dev = uart_console_get_pci_bdf(); + if (dev == PCI_DEV_INVALID) return NULL; + + return pcidev_path_on_root(PCI_DEV2DEVFN(dev)); } bool uart_is_controller_initialized(void) { uintptr_t base; - const struct device *dev_uart = uart_get_device(); + pci_devfn_t dev = uart_console_get_pci_bdf(); - if (!dev_uart) + if (dev == PCI_DEV_INVALID) return false; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_BDF(dev_uart); -#else - const struct device *dev = dev_uart; -#endif - - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; + base = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; if (!base) return false; - if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) + if ((pci_s_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) != UART_PCI_ENABLE) return false; @@ -123,21 +112,25 @@ static void uart_configure_gpio_pads(void) int index = uart_get_valid_index(); if (index != UART_CONSOLE_INVALID_INDEX) - gpio_configure_pads(uart_gpio_pads[index].gpios, + gpio_configure_pads(uart_ctrlr_config[index].gpios, MAX_GPIO_PAD_PER_UART); } void uart_bootblock_init(void) { - const struct device *dev_uart; + const uint32_t baseaddr = CONFIG_CONSOLE_UART_BASE_ADDRESS; + pci_devfn_t dev = uart_console_get_pci_bdf(); - dev_uart = uart_get_device(); - - if (!dev_uart) + if (dev == PCI_DEV_INVALID) return; - /* Program UART BAR0, command, reset and clock register */ - uart_common_init(dev_uart, CONFIG_CONSOLE_UART_BASE_ADDRESS); + /* Set UART base address */ + pci_s_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); + + /* Enable memory access and bus master */ + pci_s_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); + + uart_lpss_init(dev, baseaddr); /* Configure the 2 pads per UART. */ uart_configure_gpio_pads(); @@ -224,7 +217,7 @@ static void uart_common_enable_resources(struct device *dev) base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; if (base) - uart_lpss_init(dev, base); + uart_lpss_init(PCI_BDF(dev), base); } } @@ -436,6 +429,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_ADP_P_UART4, PCI_DEVICE_ID_INTEL_ADP_P_UART5, PCI_DEVICE_ID_INTEL_ADP_P_UART6, + PCI_DEVICE_ID_INTEL_ADP_M_UART0, + PCI_DEVICE_ID_INTEL_ADP_M_UART1, + PCI_DEVICE_ID_INTEL_ADP_M_UART2, + PCI_DEVICE_ID_INTEL_ADP_M_UART3, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 54cb07650e7..9f15ac1d6ec 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -35,6 +35,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_XDCI, PCI_DEVICE_ID_INTEL_ADP_P_XDCI, PCI_DEVICE_ID_INTEL_ADP_S_XDCI, + PCI_DEVICE_ID_INTEL_ADP_M_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index fb598978bd6..e6a1c0f5daf 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -105,8 +105,9 @@ bool xhci_update_wake_event(const struct xhci_wake_info *wake_info, for (i = 0; i < wake_info_count; ++i) { /* Assumes BAR0 is MBAR */ - mmio_base = pci_s_read_config32(wake_info[i].xhci_dev, - PCI_BASE_ADDRESS_0); + pci_devfn_t devfn = PCI_DEV(0, PCI_SLOT(wake_info[i].xhci_dev), + PCI_FUNC(wake_info[i].xhci_dev)); + mmio_base = pci_s_read_config32(devfn, PCI_BASE_ADDRESS_0); mmio_base &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; usb_info = soc_get_xhci_usb_info(wake_info[i].xhci_dev); diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 705fbb0c622..295bb3917d0 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -123,6 +123,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_JSP_XHCI, PCI_DEVICE_ID_INTEL_ADP_P_XHCI, PCI_DEVICE_ID_INTEL_ADP_S_XHCI, + PCI_DEVICE_ID_INTEL_ADP_M_XHCI, 0 }; diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index b00fc8bb71a..644fed1f4da 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -27,6 +27,7 @@ config PCH_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCIE diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index e7d29ff799e..6ab89af4015 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -59,19 +60,11 @@ static acpi_cstate_t cstate_map[] = { } }; -void acpi_init_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = (uintptr_t)cbmem_top(); -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - /* MMIO Low/High & TSEG base and length */ gnvs->mmiob = (u32)get_top_of_low_memory(); gnvs->mmiol = (u32)(get_pciebase() - 1); @@ -245,29 +238,6 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, return current; } -void southcluster_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32)gnvs); - acpigen_pop_len(); - } -} - __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} static unsigned long acpi_fill_dmar(unsigned long current) diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 4725cec5f86..97fa02f4a24 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Name(\PICM, 0) // IOAPIC/8259 External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) P80D, 32, // 0x0b - Debug port (IO 0x80) value LIDS, 8, // 0x0f - LID state (open = 1) PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count + , 8, // 0x11 - Processor count TPMP, 8, // 0x12 - TPM Present and Enabled TLVL, 8, // 0x13 - Throttle Level PPCM, 8, // 0x14 - Maximum P-state usable by OS diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 86bed0024d9..41a60d08676 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -4,14 +4,12 @@ #define _DENVERTON_NS_ACPI_H_ #include -#include void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(const struct device *device); unsigned long systemagent_write_acpi_tables(const struct device *dev, unsigned long start, struct acpi_rsdp *const rsdp); diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index fb5aafdfc80..c252ca11b6f 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -12,7 +12,6 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 -#define DEFAULT_ACPI_BASE DEFAULT_PMBASE #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h index 4aaabc95384..a978d18dc83 100644 --- a/src/soc/intel/denverton_ns/include/soc/nvs.h +++ b/src/soc/intel/denverton_ns/include/soc/nvs.h @@ -18,7 +18,7 @@ struct __packed global_nvs { u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ + u8 unused_was_pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index e40d2484910..65be16e302e 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -445,7 +445,7 @@ static void pch_enable_serial_irqs(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Get the base address */ @@ -536,7 +536,6 @@ static struct device_operations device_ops = { .read_resources = lpc_read_resources, .set_resources = pci_dev_set_resources, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_inject_dsdt = southcluster_inject_dsdt, .write_acpi_tables = southcluster_write_acpi_tables, #endif .enable_resources = lpc_enable_resources, diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index 33762b04b3d..8fc44c096ff 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -10,7 +10,7 @@ static void npk_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: npk_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* TODO */ } diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8755825db20..d75f7f05a69 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -16,7 +16,7 @@ /* While we read BAR dynamically in case it changed, let's * initialize it with a same value */ -static u16 acpi_base = DEFAULT_ACPI_BASE; +static u16 acpi_base = ACPI_BASE_ADDRESS; static u32 pwrm_base = DEFAULT_PWRM_BASE; static void pch_power_options(struct device *dev) { /* TODO */ } @@ -30,7 +30,7 @@ static void pch_set_acpi_mode(void) static void pmc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: pmc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Get the base address */ acpi_base = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE; diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index cae8b9b5f89..ae15795db93 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -17,8 +17,6 @@ #include #include -static int smm_initialized; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -221,7 +219,6 @@ static void southbridge_smi_store(void) static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -252,20 +249,6 @@ static void southbridge_smi_apmc(void) case APM_CNT_FINALIZE: finalize(); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) southbridge_smi_store(); diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 30317698737..25aea15b07f 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index af837aba5d7..88336feae23 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -247,30 +246,13 @@ unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long curre return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 17d19131b57..02425c444b2 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -15,7 +15,7 @@ #include "gpio.asl" /* GFX 00:02.0 */ -#include +#include /* ESPI 0:1f.0 */ #include diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index e1414f11fe8..288589ae90a 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -37,9 +37,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -121,19 +118,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index 8b4cf0cad9b..359aa11c07a 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -163,6 +164,8 @@ static void soc_enable(struct device *dev) else if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCH_DEVFN_PMC) dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_elkhartlake_ops = { diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 37237bbbc1b..1d97b360843 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -116,12 +117,7 @@ struct soc_intel_elkhartlake_config { uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/elkhartlake/elog.c b/src/soc/intel/elkhartlake/elog.c index c88efc81bce..14e463c9612 100644 --- a/src/soc/intel/elkhartlake/elog.c +++ b/src/soc/intel/elkhartlake/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fccbb08..1737a474acb 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -17,23 +16,9 @@ #include #include -/* -* To reserve certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - return ehl_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) -{ - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -41,29 +26,7 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); - uint32_t io_dec_arr[] = { - pci_read_config32(dev, ESPI_GEN1_DEC), - pci_read_config32(dev, ESPI_GEN2_DEC), - pci_read_config32(dev, ESPI_GEN3_DEC), - pci_read_config32(dev, ESPI_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -84,7 +47,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } #endif diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h index f3319618989..1c8cb1a6744 100644 --- a/src/soc/intel/elkhartlake/include/soc/pmc.h +++ b/src/soc/intel/elkhartlake/include/soc/pmc.h @@ -123,6 +123,8 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 4d5c04d02d3..b969ba5200b 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -7,7 +7,7 @@ #define __SIMPLE_DEVICE__ -#include +#include #include #include #include @@ -180,12 +180,10 @@ static int rtc_failed(uint32_t gen_pmcon_b) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon_b); } diff --git a/src/soc/intel/elkhartlake/uart.c b/src/soc/intel/elkhartlake/uart.c index cc0e3a848ba..cc44a61bb57 100644 --- a/src/soc/intel/elkhartlake/uart.c +++ b/src/soc/intel/elkhartlake/uart.c @@ -11,9 +11,10 @@ #include #include -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index fee52e63a80..d1efa5570ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI @@ -206,15 +207,4 @@ config SOC_INTEL_ICELAKE_DEBUG_CONSENT 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual -config ENABLE_DISPLAY_OVER_EXT_PCIE_GFX - bool "Enable display over external PCIE GFX card" - select ALWAYS_LOAD_OPROM - help - It's possible to bring display through external graphics card over PCIE - in coreboot. This option enables graphics initialization with external - graphics card. - - Selected by mainboard that runs OpRom to perform display - initialization over attached PCIe GFX card. - endif diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index ff66300da56..4a84446bc18 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -18,7 +17,6 @@ #include #include #include -#include #include /* @@ -179,30 +177,13 @@ uint32_t soc_read_sci_irq_select(void) return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 129a88da8c9..925f28f8165 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* GFX 00:02.0 */ -#include +#include /* ESPI 0:1f.0 */ #include diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 08edfeec16f..18e611962bb 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -33,9 +33,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -120,19 +117,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index d0ea732df31..d493f81bbae 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -144,6 +145,8 @@ static void soc_enable(struct device *dev) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_icelake_ops = { diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index cd0a9b03d8d..64bc70ba539 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 235dc6e3cf4..4967fde0011 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2fee2d..489fe34223f 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -17,24 +16,9 @@ #include #include -/* -* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve -* certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - return icl_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) -{ - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -42,47 +26,7 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - -uint8_t get_pch_series(void) -{ - uint16_t lpc_did_hi_byte; - - /* - * Fetch upper 8 bits on ESPI device ID to determine PCH type - * Adding 1 to the offset to fetch upper 8 bits - */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); - - if (lpc_did_hi_byte == 0x9D) - return PCH_LP; - else if (lpc_did_hi_byte == 0xA3) - return PCH_H; - else - return PCH_UNKNOWN_SERIES; -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); - uint32_t io_dec_arr[] = { - pci_read_config32(dev, ESPI_GEN1_DEC), - pci_read_config32(dev, ESPI_GEN2_DEC), - pci_read_config32(dev, ESPI_GEN3_DEC), - pci_read_config32(dev, ESPI_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -103,7 +47,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } /* Fill up ESPI IO resource structure inside SoC directory */ diff --git a/src/soc/intel/icelake/include/soc/espi.h b/src/soc/intel/icelake/include/soc/espi.h index 3ae1b2db228..ec4af4dfac3 100644 --- a/src/soc/intel/icelake/include/soc/espi.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -26,15 +26,4 @@ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -/* - * This function will help to differentiate between 2 PCH on single type of soc. - * Since same soc may have LP series pch or H series PCH, we need to - * differentiate by reading upper 8 bits of PCH device ids. - * - * Return: - * Return PCH_LP or PCH_H macro in case of respective device ID found. - * PCH_UNKNOWN_SERIES in case of invalid device ID. - */ -uint8_t get_pch_series(void); - #endif diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h index c4006eff241..a8c3f4a4479 100644 --- a/src/soc/intel/icelake/include/soc/pch.h +++ b/src/soc/intel/icelake/include/soc/pch.h @@ -3,10 +3,6 @@ #ifndef _SOC_ICELAKE_PCH_H_ #define _SOC_ICELAKE_PCH_H_ -#define PCH_H 1 -#define PCH_LP 2 -#define PCH_UNKNOWN_SERIES 0xFF - #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 26dae7e58d4..2ca3328392b 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -119,6 +119,8 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 66cc73e46f9..263bfa2e341 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -7,8 +7,8 @@ #define __SIMPLE_DEVICE__ +#include #include -#include #include #include #include @@ -180,12 +180,10 @@ static int rtc_failed(uint32_t gen_pmcon_b) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon_b); } diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index cc0e3a848ba..cc44a61bb57 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -11,9 +11,10 @@ #include #include -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 0a15f052d92..9e15a503f25 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 8673da17ea7..ea5fb0b3033 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -274,30 +273,13 @@ unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long curre return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index ebc6fd84433..b97ec58f36a 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* GFX 00:02.0 */ -#include +#include /* ESPI 0:1f.0 */ #include diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index d98d5a82132..4dc5b08591f 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -37,9 +37,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -121,19 +118,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index d34ef557df3..1f58f84c181 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -169,6 +170,8 @@ static void soc_enable(struct device *dev) else if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCH_DEVFN_PMC) dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_jasperlake_ops = { diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 9d4bc5c80aa..6e52efded3b 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -7,8 +7,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -113,12 +115,7 @@ struct soc_intel_jasperlake_config { uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; @@ -352,18 +349,23 @@ struct soc_intel_jasperlake_config { uint8_t FivrSpreadSpectrum; /* - * Disable Fast Slew Rate for Deep Package C States for VR domains + * Disable Fast Slew Rate for Deep Package C States for VCCIN VR domain * Disable Fast Slew Rate for Deep Package C States based on * Acoustic Noise Mitigation feature enabled. */ uint8_t FastPkgCRampDisable; /* - * Slew Rate configuration for Deep Package C States for VR domains + * Slew Rate configuration for Deep Package C States for VCCIN VR domain * based on Acoustic Noise Mitigation feature enabled. * 0: Fast/2 ; 1: Fast/4; 2: Fast/8; 3: Fast/16 */ - uint8_t SlowSlewRate; + enum { + SlewRateFastBy2 = 0, + SlewRateFastBy4, + SlewRateFastBy8, + SlewRateFastBy16 + } SlowSlewRate; /* * Enable or Disable Acoustic Noise Mitigation feature. diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index cb9625a6754..ccf6fd048b7 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -100,7 +100,7 @@ static void pch_log_pme_internal_wake_source(void) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -134,7 +134,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857684e..c3b50de8f0d 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -17,24 +16,9 @@ #include #include -/* -* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve -* certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - return jsl_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) -{ - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -42,29 +26,7 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); - uint32_t io_dec_arr[] = { - pci_read_config32(dev, ESPI_GEN1_DEC), - pci_read_config32(dev, ESPI_GEN2_DEC), - pci_read_config32(dev, ESPI_GEN3_DEC), - pci_read_config32(dev, ESPI_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -85,7 +47,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } #endif diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index d879db94fca..8219f0c1d5e 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -40,6 +40,8 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { + uint32_t reg32; + uint8_t *pmcbase; config_t *config; /* TCO Lock down */ @@ -62,6 +64,17 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); + pmcbase = pmc_mmio_regs(); + if (config->s0ix_enable) { + /* + * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated + * before entering s0ix. + */ + reg32 = read32(pmcbase + CPPMVRIC3); + reg32 &= ~USBSUSPGQDIS; + write32(pmcbase + CPPMVRIC3, reg32); + } + pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index c03e9dd15b1..eefbf6cf0f0 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -236,13 +236,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmPwrCycDur); - /* Fill Acoustic noise mitigation related configuration */ - params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; - params->SlowSlewRate[0] = config->SlowSlewRate; + /* + * Fill Acoustic noise mitigation related configuration + * JSL only has single VR domain (VCCIN VR), thus filling only index 0 for + * Slew rate and FastPkgCRamp for VR0 only. + */ params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; - params->PreWake = config->PreWake; - params->RampUp = config->RampUp; - params->RampDown = config->RampDown; + + if (params->AcousticNoiseMitigation) { + params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable; + params->SlowSlewRate[0] = config->SlowSlewRate; + params->PreWake = config->PreWake; + params->RampUp = config->RampUp; + params->RampDown = config->RampDown; + } /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 34172f86916..1df2c63ab8f 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -119,9 +119,14 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC3 0x1E4C +#define USBSUSPGQDIS (1 << 15) + #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 #define ACTL 0x1BD8 diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index ebe46b1d0e6..7a42d771ae7 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -7,8 +7,8 @@ #define __SIMPLE_DEVICE__ +#include #include -#include #include #include #include @@ -180,12 +180,10 @@ static int rtc_failed(uint32_t gen_pmcon_b) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon_b); } diff --git a/src/soc/intel/jasperlake/uart.c b/src/soc/intel/jasperlake/uart.c index cc0e3a848ba..cc44a61bb57 100644 --- a/src/soc/intel/jasperlake/uart.c +++ b/src/soc/intel/jasperlake/uart.c @@ -11,9 +11,10 @@ #include #include -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index fc1c7c903f4..39ce7bd02d1 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -71,6 +71,8 @@ .equ CFGNONSTICKY_W1_OFFSET, (0x52) .equ FORCE_WARM_RESET, (0x00000001) +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index 76bf4cf79df..e128a09fe65 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -12,7 +12,7 @@ __weak void mainboard_gpio_i2c_init(struct device *dev) { /* Initialize any of the GPIOs or I2C devices */ - printk(BIOS_SPEW, "WEAK; mainboard_gpio_i2c_init\n"); + printk(BIOS_SPEW, "WEAK; %s\n", __func__); } static struct device_operations device_ops = { diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h new file mode 100644 index 00000000000..fee0e42a7df --- /dev/null +++ b/src/soc/intel/quark/include/soc/nvs.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_QUARK_NVS_H +#define SOC_INTEL_QUARK_NVS_H + +#include + +struct __packed global_nvs { + uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ + uint8_t pwrs; /* 0x4 - Power state (AC = 1) */ +}; + +#endif /* SOC_INTEL_QUARK_NVS_H */ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index cfc7c5239c6..0969a9b975d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU @@ -80,6 +81,10 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2015_BINDING +config MAX_CPUS + int + default 8 + config FSP_HYPERTHREADING bool "Enable Hyper-Threading" default y diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 0083be596d8..3545a9425ed 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -2,17 +2,16 @@ #include #include +#include #include #include #include #include -#include #include #include #include #include #include -#include #include #include #include @@ -23,13 +22,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include @@ -157,32 +156,13 @@ static int get_cores_per_package(void) return cores; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { const struct soc_intel_skylake_config *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)(uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; @@ -539,29 +519,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_align_current(current); } -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) (uintptr_t)gnvs); - acpigen_pop_len(); - } -} - /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { @@ -573,7 +530,7 @@ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) int i; const int last_index = GPE0_REG_MAX - 1; - ps = cbmem_find(CBMEM_ID_POWER_STATE); + ps = acpi_get_pm_state(); if (ps == NULL) return -1; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index bc99698e1c7..928c5e6eace 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -13,7 +13,7 @@ Name (\PICM, 0) // IOAPIC/8259 External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -27,7 +27,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LCKF, 8, // 0x08 - Global Lock function for EC PRM4, 8, // 0x09 - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter - PCNT, 8, // 0x0b - Processor Count + , 8, // 0x0b - Processor Count PPCM, 8, // 0x0c - Max PPC State TMPS, 8, // 0x0d - Temperature Sensor ID TLVL, 8, // 0x0e - Throttle Level Limit diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 6eea5bb53a6..02e30f770f4 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -65,3 +65,6 @@ Method (_OSC, 4) #if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include #endif + +/* Integrated graphics 0:2.0 */ +#include diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index a5bbb095b04..9fb2aa1b36a 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -129,21 +129,8 @@ void pch_early_iorange_init(void) } /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * As per PCH BWG 2.5.1.6. - * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in LPC PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * As per PCH BWG 2.5.1.5. - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ef16f388d79..5b05dd20b2c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -103,6 +104,8 @@ static void soc_enable(struct device *dev) dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_skylake_ops = { @@ -247,6 +250,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = pcidev_path_on_root(SA_DEVFN_IMGU); params->SaImguEnable = dev && dev->enabled; + dev = pcidev_path_on_root(SA_DEVFN_CHAP); + tconfig->ChapDeviceEnable = dev && dev->enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); params->Heci3Enabled = dev && dev->enabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 7d9d93460c2..e5592b43582 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include @@ -37,16 +37,7 @@ struct soc_intel_skylake_config { struct soc_power_limits_config power_limits_config; /* IGD panel configuration */ - unsigned int gpu_pp_up_delay_ms; - unsigned int gpu_pp_down_delay_ms; - unsigned int gpu_pp_cycle_delay_ms; - unsigned int gpu_pp_backlight_on_delay_ms; - unsigned int gpu_pp_backlight_off_delay_ms; - unsigned int gpu_pch_backlight_pwm_hz; - enum { - GPU_BACKLIGHT_POLARITY_HIGH = 0, - GPU_BACKLIGHT_POLARITY_LOW, - } gpu_pch_backlight_polarity; + struct i915_gpu_panel_config panel_cfg; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ @@ -316,7 +307,7 @@ struct soc_intel_skylake_config { u8 LockDownConfigGlobalSmi; /* * Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh - * in the upper and and lower 128-byte bank of RTC RAM. + * in the upper and lower 128-byte bank of RTC RAM. */ u8 LockDownConfigRtcLock; diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 136630efa97..428db67d3a6 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -1,5 +1,6 @@ chip soc/intel/skylake device domain 0 on + device gpio 0 alias pch_gpio on end # GPIO device pci 00.0 alias system_agent on end # Host Bridge device pci 01.0 alias peg0 off end # PEG0 device pci 01.1 alias peg1 off end # PEG1 @@ -31,6 +32,10 @@ chip soc/intel/skylake device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18 device pci 1b.2 alias pcie_rp19 off end # PCI Express Port 19 device pci 1b.3 alias pcie_rp20 off end # PCI Express Port 20 + device pci 1b.4 alias pcie_rp21 off end # PCI Express Port 21 + device pci 1b.5 alias pcie_rp22 off end # PCI Express Port 22 + device pci 1b.6 alias pcie_rp23 off end # PCI Express Port 23 + device pci 1b.7 alias pcie_rp24 off end # PCI Express Port 24 device pci 1c.0 alias pcie_rp1 off end # PCI Express Port 1 device pci 1c.1 alias pcie_rp2 off end # PCI Express Port 2 device pci 1c.2 alias pcie_rp3 off end # PCI Express Port 3 diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 1332e2d7cd2..d325a930134 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include #include #include @@ -131,7 +131,7 @@ static void pch_log_rp_wake_source(void) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -173,7 +173,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { bool deep_sx; @@ -231,13 +231,10 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) static void pch_log_state(void *unused) { - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (ps == NULL) { - printk(BIOS_ERR, - "Not logging power state information. Power state not found in cbmem.\n"); + if (acpi_pm_state_for_elog(&ps) < 0) return; - } /* Power and Reset */ pch_log_power_and_resets(ps); diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index f95ca6c08c1..d41c4aa6446 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -12,9 +12,10 @@ #include #include -void graphics_soc_init(struct device *dev) +void graphics_soc_panel_init(struct device *dev) { struct soc_intel_skylake_config *conf = config_of(dev); + const struct i915_gpu_panel_config *panel_cfg; struct resource *mmio_res; uint8_t *base; u32 reg32; @@ -22,27 +23,29 @@ void graphics_soc_init(struct device *dev) if (!conf) return; + panel_cfg = &conf->panel_cfg; + mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!mmio_res || !mmio_res->base) return; base = (void *)(uintptr_t)mmio_res->base; - reg32 = conf->gpu_pp_up_delay_ms * 10 << 16; - reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10; + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; write32(base + PCH_PP_ON_DELAYS, reg32); - reg32 = conf->gpu_pp_down_delay_ms * 10 << 16; - reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10; + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; write32(base + PCH_PP_OFF_DELAYS, reg32); reg32 = read32(base + PCH_PP_DIVISOR); reg32 &= ~0x1f; - reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f; + reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f; write32(base + PCH_PP_DIVISOR, reg32); /* So far all devices seem to use the PCH PWM function. The CPU PWM registers are all zero after reset. */ - if (conf->gpu_pch_backlight_pwm_hz) { + if (panel_cfg->backlight_pwm_hz) { /* Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ @@ -51,7 +54,7 @@ void graphics_soc_init(struct device *dev) u32 south_chicken1; south_chicken1 = read32(base + SOUTH_CHICKEN1); - if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + if (panel_cfg->backlight_pwm_hz > hz_limit) { pwm_increment = 16; south_chicken1 &= ~1; } else { @@ -60,15 +63,12 @@ void graphics_soc_init(struct device *dev) } write32(base + SOUTH_CHICKEN1, south_chicken1); - pwm_period = 24 * 1000 * 1000 / pwm_increment - / conf->gpu_pch_backlight_pwm_hz; + pwm_period = 24 * 1000 * 1000 / pwm_increment / panel_cfg->backlight_pwm_hz; /* Start with a 50% duty cycle. */ - write32(base + BLC_PWM_PCH_CTL2, - pwm_period << 16 | pwm_period / 2); + write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); write32(base + BLC_PWM_PCH_CTL1, - !!conf->gpu_pch_backlight_polarity << 29 | - BLM_PCH_PWM_ENABLE); + !!panel_cfg->backlight_polarity << 29 | BLM_PCH_PWM_ENABLE); } } diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 5f209a704bf..e12a7482916 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _SOC_ACPI_H_ #include -#include /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h deleted file mode 100644 index f776a12b772..00000000000 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_DEVICE_NVS_H_ -#define _SOC_DEVICE_NVS_H_ - -#include - -#define SIO_NVS_I2C0 0 -#define SIO_NVS_I2C1 1 -#define SIO_NVS_I2C2 2 -#define SIO_NVS_I2C3 3 -#define SIO_NVS_I2C4 4 -#define SIO_NVS_I2C5 5 -#define SIO_NVS_SPI0 6 -#define SIO_NVS_SPI1 7 -#define SIO_NVS_UART0 8 -#define SIO_NVS_UART1 9 -#define SIO_NVS_UART2 10 - -typedef struct { - u8 enable[11]; - u32 bar0[11]; - u32 bar1[11]; -} __packed device_nvs_t; - -#endif diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 87f16fb5f9a..39271d3549f 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -3,8 +3,7 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include -#include +#include struct __packed global_nvs { /* Miscellaneous */ @@ -18,7 +17,7 @@ struct __packed global_nvs { u8 lckf; /* 0x08 - Global Lock function for EC */ u8 prm4; /* 0x09 - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */ - u8 pcnt; /* 0x0b - Processor Count */ + u8 unused_was_pcnt; /* 0x0b - Processor Count */ u8 ppcm; /* 0x0c - Max PPC State */ u8 tmps; /* 0x0d - Temperature Sensor ID */ u8 tlvl; /* 0x0e - Throttle Level Limit */ @@ -31,7 +30,7 @@ struct __packed global_nvs { u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 lids; /* 0x16 - LID State */ u8 pwrs; /* 0x17 - AC Power State */ - u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ @@ -47,12 +46,6 @@ struct __packed global_nvs { u64 elng; /* 0x4C - 0x53 EPC Length */ u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */ - u8 rsvd[156]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 319a12b53a0..661ed5cd657 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -42,6 +42,10 @@ #define SA_DEVFN_IMGU PCI_DEVFN(SA_DEV_SLOT_IMGU, 0) #define SA_DEV_IMGU PCI_DEV(0, SA_DEV_SLOT_IMGU, 0) +#define SA_DEV_SLOT_CHAP 0x07 +#define SA_DEVFN_CHAP PCI_DEVFN(SA_DEV_SLOT_CHAP, 0) +#define SA_DEV_CHAP PCI_DEV(0, SA_DEV_SLOT_CHAP, 0) + #define SA_DEV_SLOT_GMM 0x08 #define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) #define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0) diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 350649a2119..8fe3f83cadf 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -84,6 +84,7 @@ #define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 +#define SLP_S0_RES 0x13c #define CPPMVRIC 0x31c #define XTALSDQDIS (1 << 22) #endif diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c663980e3..5abae765c9d 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -15,23 +14,9 @@ #include "chip.h" -/** - PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF -**/ - -static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - return skl_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) -{ - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -39,15 +24,6 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - static const struct reg_script pch_misc_init_script[] = { /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 28ede6fed41..423578847a3 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -10,10 +10,10 @@ #include #include -/* UART pad configuration. Support RXD and TXD for now. */ -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -21,6 +21,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -28,6 +29,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -35,23 +37,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c7e10a9a694..8211d5650b0 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI @@ -53,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM @@ -249,4 +251,16 @@ config EARLY_TCSS_DISPLAY help Enable displays to be detected over Type-C ports during boot. +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config MRC_CHANNEL_WIDTH + int + default 16 + endif diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index c7c544615ea..354e3d267d7 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -274,30 +273,13 @@ unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long curre return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - if (CONFIG(CONSOLE_CBMEM)) - /* Update the mem console pointer. */ - gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 3d8e55490ae..744b7ef50ae 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* GFX 00:02.0 */ -#include +#include /* ESPI 0:1f.0 */ #include diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 5a63b40c21a..96a4487f262 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -42,9 +42,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -126,19 +123,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 62201a2f4f4..f07cc58c958 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -177,6 +178,8 @@ static void soc_enable(struct device *dev) else if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == PCH_DEVFN_PMC) dev->ops = &pmc_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } struct chip_operations soc_intel_tigerlake_ops = { diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fe10d0dbcba..d3062cc7208 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,8 +7,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -246,12 +248,7 @@ struct soc_intel_tigerlake_config { uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; @@ -326,6 +323,13 @@ struct soc_intel_tigerlake_config { uint8_t TcssXhciEn; uint8_t TcssXdciEn; + /* + * Specifies which Type-C Ports are enabled on the system + * each bit represents a port starting at 0 + * Example: set value to 0x3 for ports 0 and 1 to be enabled + */ + uint8_t UsbTcPortEn; + /* * IOM Port Config * If a port orientation needs to be controlled by the SOC this setting must be diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 54f7924b37c..d4bc76c2a4d 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -1,5 +1,6 @@ chip soc/intel/tigerlake device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end device pci 02.0 alias igpu off end device pci 04.0 alias dptf off end diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 7f40a37d2fa..878959a9b58 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -126,7 +126,7 @@ static void pch_log_pme_internal_wake_source(void) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -160,7 +160,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b122440..8386cd9df14 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -23,24 +22,9 @@ #include #include -/* -* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve -* certain memory range as reserved range for BIOS usage. -* For this SOC, the range will be from 0FC800000h till FE7FFFFFh" -*/ -static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { - { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() -{ - return tgl_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -48,29 +32,7 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); - uint32_t io_dec_arr[] = { - pci_read_config32(dev, ESPI_GEN1_DEC), - pci_read_config32(dev, ESPI_GEN2_DEC), - pci_read_config32(dev, ESPI_GEN3_DEC), - pci_read_config32(dev, ESPI_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -91,7 +53,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } #endif diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ed348972747..c0d712ca351 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -123,6 +123,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->D3ColdEnable = !config->TcssD3ColdDisable; + params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; @@ -134,6 +135,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) */ params->ITbtConnectTopologyTimeoutInMs = 0; + /* Disable TcColdOnUsbConnect */ + params->DisableTccoldOnUsbConnected = 1; + /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { params->PchLockDownGlobalSmi = 0; @@ -159,6 +163,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else params->Usb2OverCurrentPin[i] = 0xff; + + if (config->usb2_ports[i].type_c) + params->PortResetMessageEnable[i] = 1; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 4a52298b7a0..8583e669d01 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -5,151 +5,115 @@ #include #include +#include #include +#include -#define BITS_PER_BYTE 8 - -#define LPDDR4X_CHANNELS 8 -#define LPDDR4X_BYTES_PER_CHANNEL 2 +enum mem_type { + MEM_TYPE_DDR4, + MEM_TYPE_LP4X, +}; -#define DDR4_CHANNELS 2 -#define DDR4_BYTES_PER_CHANNEL 8 +struct ddr4_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; + uint8_t dq2[BITS_PER_BYTE]; + uint8_t dq3[BITS_PER_BYTE]; + uint8_t dq4[BITS_PER_BYTE]; + uint8_t dq5[BITS_PER_BYTE]; + uint8_t dq6[BITS_PER_BYTE]; + uint8_t dq7[BITS_PER_BYTE]; +}; -enum mem_topology { - MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */ - SODIMM, /* Supports reading SPD using SMBus (only for DDR4). */ - MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ +struct ddr4_dqs { + uint8_t dqs0; + uint8_t dqs1; + uint8_t dqs2; + uint8_t dqs3; + uint8_t dqs4; + uint8_t dqs5; + uint8_t dqs6; + uint8_t dqs7; }; -enum ddr_memtype { - MEMTYPE_DDR4, /* Uses DDR4 memory */ - MEMTYPE_LPDDR4X, /* Uses LPDDR4x memory */ +struct ddr4_dq_map { + struct ddr4_dq ddr0; + struct ddr4_dq ddr1; }; -enum md_spd_loc { - /* Read SPD from pointer provided to memory location. */ - SPD_MEMPTR, - /* Read SPD using index into spd.bin in CBFS. */ - SPD_CBFS, +struct ddr4_dqs_map { + struct ddr4_dqs ddr0; + struct ddr4_dqs ddr1; }; -struct spd_info { - enum mem_topology topology; +struct lp4x_dq { + uint8_t dq0[BITS_PER_BYTE]; + uint8_t dq1[BITS_PER_BYTE]; +}; - /* SPD info for Memory down topology */ - enum md_spd_loc md_spd_loc; - union { - /* Used for SPD_CBFS */ - uint8_t cbfs_index; - - struct { - /* Used for SPD_MEMPTR */ - uintptr_t data_ptr; - size_t data_len; - }; - }; +struct lp4x_dqs { + uint8_t dqs0; + uint8_t dqs1; +}; - /* - * SPD info for SODIMM topology. - * Leave addr_dimmN as 0 for any DIMMs that are not populated. - */ - struct { - /* SMBus address for DIMM0 within the channel. */ - uint8_t addr_dimm0; - /* SMBus address for DIMM1 within the channel. */ - uint8_t addr_dimm1; - } smbus_info[DDR4_CHANNELS]; +struct lp4x_dq_map { + struct lp4x_dq ddr0; + struct lp4x_dq ddr1; + struct lp4x_dq ddr2; + struct lp4x_dq ddr3; + struct lp4x_dq ddr4; + struct lp4x_dq ddr5; + struct lp4x_dq ddr6; + struct lp4x_dq ddr7; }; -/* Board-specific memory configuration information */ -struct lpddr4x_cfg { - /* - * DQ CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[7-0]_DQ[1-0][7:0], where - * DDR[7-0] : LPDDR4x channel # - * DQ[1-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - - /* - * DQS CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQS pairs(P/N) per channel. Thus, dqs_map is - * represented as DDR[7-0]_DQS[1:0], where - * DDR[7-0] : LPDDR4x channel # - * DQS[1-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; - /* - * Early Command Training Enable/Disable Control - * 1 = enable, 0 = disable - */ - uint8_t ect; +struct lp4x_dqs_map { + struct lp4x_dqs ddr0; + struct lp4x_dqs ddr1; + struct lp4x_dqs ddr2; + struct lp4x_dqs ddr3; + struct lp4x_dqs ddr4; + struct lp4x_dqs ddr5; + struct lp4x_dqs ddr6; + struct lp4x_dqs ddr7; }; -/* Board-specific memory configuration information for DDR4 memory variant */ -struct mb_ddr4_cfg { - /* - * DQ CPU<>DRAM map: - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[1-0]_DQ[7-0][7:0], where - * DDR[1-0] : DDR4 channel # - * DQ[7-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - /* - * DQS CPU<>DRAM map: - * DDR4 memory interface has 8 DQS pairs per channel. Thus, dqs_map is represented as - * DDR[1-0]_DQS[7-0], where - * DDR[1-0] : DDR4 channel # - * DQS[7-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQS pin# on the memory part. - */ - uint8_t dqs_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL]; - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ - uint8_t dq_pins_interleaved; - /* - * Early Command Training Enable/Disable Control - * 1 = enable, 0 = disable - */ - uint8_t ect; +struct mem_ddr4_config { + bool dq_pins_interleaved; }; -/* DDR Memory Information - Supports DDR4 and LPDDR4x */ -struct ddr_memory_cfg { - enum ddr_memtype mem_type; +struct mb_cfg { + enum mem_type type; + union { - const struct mb_ddr4_cfg *ddr4_cfg; - const struct lpddr4x_cfg *lpddr4_cfg; + /* + * DQ CPU<>DRAM map: + * Index of the array represents DQ# on the CPU and the value represents DQ# on + * the DRAM part. + */ + uint8_t dq_map[CONFIG_DATA_BUS_WIDTH]; + struct lp4x_dq_map lp4x_dq_map; + struct ddr4_dq_map ddr4_dq_map; }; -}; -/* Initialize LPDDR4x memory configurations */ -void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *spd, bool half_populated); + union { + /* + * DQS CPU<>DRAM map: + * Index of the array represents DQS# on the CPU and the value represents DQS# + * on the DRAM part. + */ + uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE]; + struct lp4x_dqs_map lp4x_dqs_map; + struct ddr4_dqs_map ddr4_dqs_map; + }; + + /* Early Command Training Enable/Disable Control */ + bool ect; + + struct mem_ddr4_config ddr4_config; +}; -/* Initialize DDR4 memory configurations */ -void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *spd, const bool half_populated); +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated); -/* Determine which DDR memory is used and call appropriate init routine */ -void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, - const struct spd_info *info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index f926799c750..cd0299aa48c 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -152,6 +152,8 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void); #define HPR_CAUSE0_MI_HRPC (1 << 9) #define HPR_CAUSE0_MI_HR (1 << 8) +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 69b5ca89a7a..5dea4bf52e0 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -31,6 +31,7 @@ struct usb2_port_config { uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; }; /* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ enum { .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ } struct usb3_port_config { diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 7e830f051f7..c030bb80acd 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -4,449 +4,174 @@ #include #include #include -#include #include -/* If memory is half-populated, then upper half of the channels need to be left empty. */ -#define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ - ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) - -/* - * Translate DDR4 channel # to FSP UPD index # for the channel. - * Channel 0 -> Index 0 - * Channel 1 -> Index 4 - * Index 1-3 and 5-7 are unused. - */ -#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) - -enum dimm_enable_options { - ENABLE_BOTH_DIMMS = 0, - DISABLE_DIMM0 = 1, - DISABLE_DIMM1 = 2, - DISABLE_BOTH_DIMMS = 3 +#define LP4X_CH_WIDTH 16 +#define LP4X_CHANNELS CHANNEL_COUNT(LP4X_CH_WIDTH) + +#define DDR4_CH_WIDTH 64 +#define DDR4_CHANNELS CHANNEL_COUNT(DDR4_CH_WIDTH) + +static const struct soc_mem_cfg soc_mem_cfg[] = { + [MEM_TYPE_DDR4] = { + .num_phys_channels = DDR4_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 4, + }, + .md_phy_masks = { + /* + * Only physical channel 0 is populated in case of half-populated + * configuration. + */ + .half_channel = BIT(0), + /* In mixed topologies, channel 0 is always memory-down. */ + .mixed_topo = BIT(0), + }, + }, + [MEM_TYPE_LP4X] = { + .num_phys_channels = LP4X_CHANNELS, + .phys_to_mrc_map = { + [0] = 0, + [1] = 1, + [2] = 2, + [3] = 3, + [4] = 4, + [5] = 5, + [6] = 6, + [7] = 7, + }, + .md_phy_masks = { + /* + * Physical channels 0, 1, 2 and 3 are populated in case of + * half-populated configurations. + */ + .half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3), + /* LP4x does not support mixed topologies. */ + }, + }, }; -static uint8_t get_dimm_cfg(uintptr_t dimm0, uintptr_t dimm1) -{ - if (dimm0 && dimm1) - return ENABLE_BOTH_DIMMS; - if (!dimm0 && !dimm1) - return DISABLE_BOTH_DIMMS; - if (!dimm1) - return DISABLE_DIMM1; - if (!dimm0) - die("Disabling of only dimm0 is not supported!\n"); - - return DISABLE_BOTH_DIMMS; -} - -static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, - uintptr_t spd_dimm1) -{ - uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1); - - switch (channel) { - case 0: - mem_cfg->DisableDimmCh0 = dimm_cfg; - mem_cfg->MemorySpdPtr00 = spd_dimm0; - mem_cfg->MemorySpdPtr01 = spd_dimm1; - break; - - case 1: - mem_cfg->DisableDimmCh1 = dimm_cfg; - mem_cfg->MemorySpdPtr02 = spd_dimm0; - mem_cfg->MemorySpdPtr03 = spd_dimm1; - break; - - case 2: - mem_cfg->DisableDimmCh2 = dimm_cfg; - mem_cfg->MemorySpdPtr04 = spd_dimm0; - mem_cfg->MemorySpdPtr05 = spd_dimm1; - break; - - case 3: - mem_cfg->DisableDimmCh3 = dimm_cfg; - mem_cfg->MemorySpdPtr06 = spd_dimm0; - mem_cfg->MemorySpdPtr07 = spd_dimm1; - break; - - case 4: - mem_cfg->DisableDimmCh4 = dimm_cfg; - mem_cfg->MemorySpdPtr08 = spd_dimm0; - mem_cfg->MemorySpdPtr09 = spd_dimm1; - break; - - case 5: - mem_cfg->DisableDimmCh5 = dimm_cfg; - mem_cfg->MemorySpdPtr10 = spd_dimm0; - mem_cfg->MemorySpdPtr11 = spd_dimm1; - break; - - case 6: - mem_cfg->DisableDimmCh6 = dimm_cfg; - mem_cfg->MemorySpdPtr12 = spd_dimm0; - mem_cfg->MemorySpdPtr13 = spd_dimm1; - break; - - case 7: - mem_cfg->DisableDimmCh7 = dimm_cfg; - mem_cfg->MemorySpdPtr14 = spd_dimm0; - mem_cfg->MemorySpdPtr15 = spd_dimm1; - break; - - default: - die("Invalid channel: %d\n", channel); - } -} - -static inline void init_spd_upds_empty(FSP_M_CONFIG *mem_cfg, int channel) -{ - init_spd_upds(mem_cfg, channel, 0, 0); -} - -static inline void init_spd_upds_dimm0(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0) -{ - init_spd_upds(mem_cfg, channel, spd_dimm0, 0); -} - -static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, const uint8_t *dq_byte0, - const uint8_t *dq_byte1) -{ - uint8_t *dq_upd; - - switch (byte_pair) { - case 0: - dq_upd = mem_cfg->DqMapCpu2DramCh0; - break; - case 1: - dq_upd = mem_cfg->DqMapCpu2DramCh1; - break; - case 2: - dq_upd = mem_cfg->DqMapCpu2DramCh2; - break; - case 3: - dq_upd = mem_cfg->DqMapCpu2DramCh3; - break; - case 4: - dq_upd = mem_cfg->DqMapCpu2DramCh4; - break; - case 5: - dq_upd = mem_cfg->DqMapCpu2DramCh5; - break; - case 6: - dq_upd = mem_cfg->DqMapCpu2DramCh6; - break; - case 7: - dq_upd = mem_cfg->DqMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - if (dq_byte0 && dq_byte1) { - memcpy(dq_upd, dq_byte0, BITS_PER_BYTE); - memcpy(dq_upd + BITS_PER_BYTE, dq_byte1, BITS_PER_BYTE); - } else { - memset(dq_upd, 0, BITS_PER_BYTE * 2); - } -} - -static inline void init_dq_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dq_upds(mem_cfg, byte_pair, NULL, NULL); -} - -static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, uint8_t dqs_byte0, - uint8_t dqs_byte1) +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { - uint8_t *dqs_upd; - - switch (byte_pair) { - case 0: - dqs_upd = mem_cfg->DqsMapCpu2DramCh0; - break; - case 1: - dqs_upd = mem_cfg->DqsMapCpu2DramCh1; - break; - case 2: - dqs_upd = mem_cfg->DqsMapCpu2DramCh2; - break; - case 3: - dqs_upd = mem_cfg->DqsMapCpu2DramCh3; - break; - case 4: - dqs_upd = mem_cfg->DqsMapCpu2DramCh4; - break; - case 5: - dqs_upd = mem_cfg->DqsMapCpu2DramCh5; - break; - case 6: - dqs_upd = mem_cfg->DqsMapCpu2DramCh6; - break; - case 7: - dqs_upd = mem_cfg->DqsMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - dqs_upd[0] = dqs_byte0; - dqs_upd[1] = dqs_byte1; -} - -static inline void init_dqs_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dqs_upds(mem_cfg, byte_pair, 0, 0); -} - -static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) -{ - struct region_device spd_rdev; - - printk(BIOS_DEBUG, "SPD INDEX = %u\n", index); - if (get_spd_cbfs_rdev(&spd_rdev, index) < 0) - die("spd.bin not found or incorrect index\n"); - - /* Memory leak is ok since we have memory mapped boot media */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - *len = region_device_sz(&spd_rdev); - *data = (uintptr_t)rdev_mmap_full(&spd_rdev); -} - -static void read_md_spd(const struct spd_info *info, uintptr_t *data, size_t *len) -{ - if (info->md_spd_loc == SPD_MEMPTR) { - *data = info->data_ptr; - *len = info->data_len; - } else if (info->md_spd_loc == SPD_CBFS) { - read_spd_from_cbfs(info->cbfs_index, data, len); - } else { - die("Not a valid location(%d) for Memory-down SPD!\n", info->md_spd_loc); + uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { + [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, + [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, + [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, + [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, + [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, + [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, + [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, + [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + }; + uint8_t *disable_dimm_upds[MRC_CHANNELS] = { + &mem_cfg->DisableDimmCh0, + &mem_cfg->DisableDimmCh1, + &mem_cfg->DisableDimmCh2, + &mem_cfg->DisableDimmCh3, + &mem_cfg->DisableDimmCh4, + &mem_cfg->DisableDimmCh5, + &mem_cfg->DisableDimmCh6, + &mem_cfg->DisableDimmCh7, + }; + int ch, dimm; + + mem_cfg->MemorySpdDataLen = data->spd_len; + + for (ch = 0; ch < MRC_CHANNELS; ch++) { + uint8_t *disable_dimm_ptr = disable_dimm_upds[ch]; + *disable_dimm_ptr = 0; + + for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { + uint32_t *spd_ptr = spd_upds[ch][dimm]; + + *spd_ptr = data->spd[ch][dimm]; + if (!*spd_ptr) + *disable_dimm_ptr |= BIT(dimm); + } } - - print_spd_info((uint8_t *) *data); } -void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *info, bool half_populated) - +static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size, + const struct mem_channel_data *data) { - size_t spd_len; - uintptr_t spd_data; - int i; + size_t i; - if (info->topology != MEMORY_DOWN) - die("LPDDR4x only support memory-down topology.\n"); - - /* LPDDR4x does not allow interleaved memory */ - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->ECT = board_cfg->ect; - - read_md_spd(info, &spd_data, &spd_len); - mem_cfg->MemorySpdDataLen = spd_len; - - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_spd_upds_empty(mem_cfg, i); + for (i = 0; i < MRC_CHANNELS; i++, map += upd_size) { + if (channel_is_populated(i, MRC_CHANNELS, data->ch_population_flags)) + memcpy(upds[i], map, upd_size); else - init_spd_upds_dimm0(mem_cfg, i, spd_data); - } - - /* - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh2 --> dq_map[CHAN=2][0-1] - * DqMapCpu2DramCh3 --> dq_map[CHAN=3][0-1] - * DqMapCpu2DramCh4 --> dq_map[CHAN=4][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=5][0-1] - * DqMapCpu2DramCh6 --> dq_map[CHAN=6][0-1] - * DqMapCpu2DramCh7 --> dq_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dq_upds_empty(mem_cfg, i); - else - init_dq_upds(mem_cfg, i, board_cfg->dq_map[i][0], - board_cfg->dq_map[i][1]); - } - - /* - * LPDDR4x memory interface has 2 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=2][0-1] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=3][0-1] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=4][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=5][0-1] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=6][0-1] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dqs_upds_empty(mem_cfg, i); - else - init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i][0], - board_cfg->dqs_map[i][1]); + memset(upds[i], 0, upd_size); } } -static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) +static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg) { - unsigned int i; - - blk->addr_map[0] = info->smbus_info[0].addr_dimm0; - blk->addr_map[1] = info->smbus_info[0].addr_dimm1; - blk->addr_map[2] = info->smbus_info[1].addr_dimm0; - blk->addr_map[3] = info->smbus_info[1].addr_dimm1; - - get_spd_smbus(blk); - - /* - * SPD gets printed only if: - * a) mainboard provides a non-zero SMBus address and - * b) SPD is successfully read using the SMBus address - */ - for (i = 0; i < ARRAY_SIZE(blk->addr_map); i++) { - if (blk->spd_array[i] != NULL) - print_spd_info((uint8_t *)blk->spd_array[i]); - } + void *dq_upds[MRC_CHANNELS] = { + &mem_cfg->DqMapCpu2DramCh0, + &mem_cfg->DqMapCpu2DramCh1, + &mem_cfg->DqMapCpu2DramCh2, + &mem_cfg->DqMapCpu2DramCh3, + &mem_cfg->DqMapCpu2DramCh4, + &mem_cfg->DqMapCpu2DramCh5, + &mem_cfg->DqMapCpu2DramCh6, + &mem_cfg->DqMapCpu2DramCh7, + }; + + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + + _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); + + mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data); } -static void ddr4_get_spd(unsigned int channel, const uintptr_t *spd_md_data, - const struct spd_block *spd_sodimm_blk, - const struct spd_info *info, - const bool half_populated, uintptr_t *spd_dimm0, - uintptr_t *spd_dimm1) +static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + const struct mb_cfg *mb_cfg) { - if (channel == 0) { - /* For mixed topology, channel 0 can only be Memory_Down */ - if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { - *spd_dimm0 = *spd_md_data; - *spd_dimm1 = 0; - } else if (info->topology == SODIMM) { - *spd_dimm0 = (uintptr_t)spd_sodimm_blk->spd_array[0]; - *spd_dimm1 = (uintptr_t)spd_sodimm_blk->spd_array[1]; - } else - die("Undefined memory topology on Channel 0.\n"); - } else if (channel == 1) { - if (half_populated) { - *spd_dimm0 = *spd_dimm1 = 0; - } else if (info->topology == MEMORY_DOWN) { - *spd_dimm0 = *spd_md_data; - *spd_dimm1 = 0; - /* For mixed topology, channel 1 can only be SODIMM */ - } else if ((info->topology == SODIMM) || (info->topology == MIXED)) { - *spd_dimm0 = (uintptr_t)spd_sodimm_blk->spd_array[2]; - *spd_dimm1 = (uintptr_t)spd_sodimm_blk->spd_array[3]; - } else - die("Undefined memory topology on channel 1.\n"); - } else - die("Unsupported channels.\n"); + void *dqs_upds[MRC_CHANNELS] = { + &mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1, + &mem_cfg->DqsMapCpu2DramCh2, + &mem_cfg->DqsMapCpu2DramCh3, + &mem_cfg->DqsMapCpu2DramCh4, + &mem_cfg->DqsMapCpu2DramCh5, + &mem_cfg->DqsMapCpu2DramCh6, + &mem_cfg->DqsMapCpu2DramCh7, + }; + + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + + _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); + + mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data); } -/* Initialize DDR4 memory configurations */ -void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *info, const bool half_populated) +void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, + const struct mem_spd *spd_info, bool half_populated) { - uintptr_t spd_md_data; - size_t spd_md_len; - uintptr_t spd_dimm0 = 0; - uintptr_t spd_dimm1 = 0; - struct spd_block spd_sodimm_blk; - unsigned int i; - unsigned int index = 0; + struct mem_channel_data data; - /* Early Command Training Enabled */ - mem_cfg->ECT = board_cfg->ect; - mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + if (mb_cfg->type >= ARRAY_SIZE(soc_mem_cfg)) + die("Invalid memory type(%x)!\n", mb_cfg->type); - if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) { - read_md_spd(info, &spd_md_data, &spd_md_len); - mem_cfg->MemorySpdDataLen = spd_md_len; - } - - if ((info->topology == SODIMM) || (info->topology == MIXED)) { - read_sodimm_spd(info, &spd_sodimm_blk); - if ((info->topology == MIXED) && - (mem_cfg->MemorySpdDataLen != spd_sodimm_blk.len)) - die("Mixed topology has incorrect length.\n"); - else - mem_cfg->MemorySpdDataLen = spd_sodimm_blk.len; - } - - for (i = 0; i < DDR4_CHANNELS; i++) { - ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, - half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); - } - - /* - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for every dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=0][2-3] - * DqMapCpu2DramCh2 --> dq_map[CHAN=0][4-5] - * DqMapCpu2DramCh3 --> dq_map[CHAN=0][6-7] - * DqMapCpu2DramCh4 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=1][2-3] - * DqMapCpu2DramCh6 --> dq_map[CHAN=1][4-5] - * DqMapCpu2DramCh7 --> dq_map[CHAN=1][6-7] - */ + mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data); + mem_init_spd_upds(mem_cfg, &data); + mem_init_dq_upds(mem_cfg, &data, mb_cfg); + mem_init_dqs_upds(mem_cfg, &data, mb_cfg); - /* - * DDR4 memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for every dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] - */ + mem_cfg->ECT = mb_cfg->ect; - for (i = 0; i < DDR4_CHANNELS; i++) { - for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b += 2) { - if (half_populated && (i == 1)) { - init_dq_upds_empty(mem_cfg, index); - init_dqs_upds_empty(mem_cfg, index); - } else { - init_dq_upds(mem_cfg, index, board_cfg->dq_map[i][b], - board_cfg->dq_map[i][b+1]); - init_dqs_upds(mem_cfg, index, board_cfg->dqs_map[i][b], - board_cfg->dqs_map[i][b+1]); - } - index++; - } - } -} - -void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, - const struct spd_info *info, bool half_populated) -{ - switch (board_cfg->mem_type) { - case MEMTYPE_DDR4: - meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, half_populated); + switch (mb_cfg->type) { + case MEM_TYPE_DDR4: + mem_cfg->DqPinsInterleaved = mb_cfg->ddr4_config.dq_pins_interleaved; break; - case MEMTYPE_LPDDR4X: - meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, half_populated); + case MEM_TYPE_LP4X: + /* LPDDR4x does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; break; default: - die("Unsupported memory type = %d!\n", board_cfg->mem_type); + die("Unsupported memory type(%d)\n", mb_cfg->type); } + } diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index f2ff483af17..39fc36b46d1 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -13,8 +13,8 @@ #define __SIMPLE_DEVICE__ +#include #include -#include #include #include #include @@ -186,12 +186,10 @@ static int rtc_failed(uint32_t gen_pmcon_b) int soc_get_rtc_failed(void) { - const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + const struct chipset_power_state *ps; - if (!ps) { - printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); + if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - } return rtc_failed(ps->gen_pmcon_b); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index dc9caee9fb5..27630ec0a15 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -22,12 +22,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t cpu_id, mask = 0; const struct device *dev; - /* - * If IGD is enabled, set IGD stolen size to 60MB. - * Otherwise, skip IGD init in FSP. - */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = is_dev_enabled(dev); + if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) + m_cfg->InternalGfx = 1; + else + m_cfg->InternalGfx = 0; + + /* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */ m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c index 08bfa5402d2..a3aee398c4f 100644 --- a/src/soc/intel/tigerlake/uart.c +++ b/src/soc/intel/tigerlake/uart.c @@ -17,9 +17,10 @@ #include #include -const struct uart_gpio_pad_config uart_gpio_pads[] = { +const struct uart_controller_config uart_ctrlr_config[] = { { .console_index = 0, + .devfn = PCH_DEVFN_UART0, .gpios = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ @@ -27,6 +28,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 1, + .devfn = PCH_DEVFN_UART1, .gpios = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */ @@ -34,6 +36,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { }, { .console_index = 2, + .devfn = PCH_DEVFN_UART2, .gpios = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ @@ -41,23 +44,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { } }; -const int uart_max_index = ARRAY_SIZE(uart_gpio_pads); - -DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console) -{ - /* - * if index is valid, this function will return corresponding structure - * for uart console else will return NULL. - */ - switch (uart_console) { - case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); - case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); - case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); - default: - printk(BIOS_ERR, "Invalid UART console index\n"); - return NULL; - } -} +const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 664f9606e37..fac66f78811 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,12 +36,13 @@ config CPU_SPECIFIC_OPTIONS select POSTCAR_STAGE select IOAPIC select PARALLEL_MP - select ACPI_NO_SMI_GNVS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_DMI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_FAST_SPI @@ -54,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_TCO + select SOC_INTEL_COMMON_BLOCK_ACPI select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index cfda7d5d873..b9ce2947d0c 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -8,10 +8,10 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c romstage-y += ../../../cpu/intel/car/romstage.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += nb_acpi.c acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 4c17eeac391..b271264b078 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,19 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include -#include -#include #include #include @@ -23,72 +12,18 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) return NULL; } -static int acpi_sci_irq(void) -{ - int sci_irq = 9; - uint32_t scis; - - scis = soc_read_sci_irq_select(); - scis &= SCI_IRQ_SEL; - scis >>= SCI_IRQ_ADJUST; - - /* Determine how SCI is routed. */ - switch (scis) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = scis - SCIS_IRQ9 + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = scis - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - -static unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - - flags |= soc_madt_sci_irq_polarity(sci); - - /* SCI */ - current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); - - current += - acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0xff, 0x0d, 1); - - return current; -} - -static unsigned long add_madt_ioapic(unsigned long current, int socket, int stack, +static void print_madt_ioapic(int socket, int stack, int ioapic_id, uint32_t ioapic_base, int gsi_base) { printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " "ioapic_base: 0x%x, gsi_base: 0x%x\n", socket, stack, ioapic_id, ioapic_base, gsi_base); - return acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, ioapic_id, - ioapic_base, gsi_base); + return; } -unsigned long acpi_fill_madt(unsigned long current) +const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries) { int cur_index; - int ioapic_id; - int gsi_base; const IIO_UDS *hob = get_iio_uds(); /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ @@ -99,15 +34,16 @@ unsigned long acpi_fill_madt(unsigned long current) #if (CONFIG(SOC_INTEL_SKYLAKE_SP)) const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; #endif - /* Local APICs */ - current = xeonsp_acpi_create_madt_lapics(current); + + static struct madt_ioapic_info madt_tbl[ARRAY_SIZE(gsi_bases)]; cur_index = 0; - gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID, - hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, - gsi_base); - ++cur_index; + madt_tbl[cur_index].id = PCH_IOAPIC_ID; + madt_tbl[cur_index].addr = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase; + madt_tbl[cur_index].gsi_base = gsi_bases[cur_index]; + print_madt_ioapic(0, 0, madt_tbl[cur_index].id, + madt_tbl[cur_index].addr, madt_tbl[cur_index].gsi_base); + ++cur_index; for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { @@ -116,177 +52,24 @@ unsigned long acpi_fill_madt(unsigned long current) if (!is_iio_stack_res(ri)) continue; assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = soc_get_iio_ioapicid(socket, stack); - gsi_base = gsi_bases[cur_index]; - uint32_t ioapic_base = ri->IoApicBase; + madt_tbl[cur_index].id = soc_get_iio_ioapicid(socket, stack); + madt_tbl[cur_index].gsi_base = gsi_bases[cur_index]; + madt_tbl[cur_index].addr = ri->IoApicBase; /* * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. * The IIO IOAPIC is placed at 0x1000 from the reported base. */ if (stack == 0 && socket == 0) - ioapic_base += 0x1000; + madt_tbl[cur_index].addr += 0x1000; - current += add_madt_ioapic(current, socket, stack, ioapic_id, - ioapic_base, gsi_base); + print_madt_ioapic(socket, stack, madt_tbl[cur_index].id, + madt_tbl[cur_index].addr, + madt_tbl[cur_index].gsi_base); ++cur_index; } } - return acpi_madt_irq_overrides(current); -} - -void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - fadt->header.revision = get_acpi_table_revision(FADT); - - fadt->sci_int = acpi_sci_irq(); - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - - fadt->gpe0_blk = pmbase + GPE0_STS(0); - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - - /* GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - - fadt->duty_offset = 1; - fadt->day_alrm = 0xd; - - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; -} - -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - current = acpi_write_hpet(device, current, rsdp); - current = (ALIGN(current, 16)); - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; -} - -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uint32_t)gnvs); - acpigen_pop_len(); - } -} - -int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -acpi_tstate_t *soc_get_tss_table(int *entries) -{ - *entries = 0; - return NULL; -} - -void generate_cpu_entries(const struct device *device) -{ - int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; - int plen = 6; - int total_threads = dev_count_cpu(); - int threads_per_package = get_threads_per_package(); - int numcpus = total_threads / threads_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n", - numcpus, threads_per_package, total_threads); - - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { - for (core_id = 0; core_id < threads_per_package; core_id++) { - if (core_id > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor((cpu_id) * threads_per_package + - core_id, pcontrol_blk, plen); - - /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - - /* Soc specific power states generation */ - soc_power_states_generation(core_id, threads_per_package); - - acpigen_pop_len(); - } - } - /* PPKG is usually used for thermal management of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, threads_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(threads_per_package); + *entries = cur_index; + return madt_tbl; } diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 43337b5b67c..ded69987ea7 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -43,13 +43,22 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex - default 0x140000 + default 0x40000 help The amount of anticipated stack usage in CAR by bootblock and other stages. It needs to include FSP-M stack requirement and CB romstage stack requirement. The integration documentation - says this needs to be 256KiB, but practice show this needs to - be a lot more. + says this needs to be 256KiB. + +config FSP_M_RC_HEAP_SIZE + hex + default 0x130000 + help + On xeon_sp/cpx FSP-M has two separate heap managers, one regular + whose size and base are controllable via the StackBase and + StackSize UPDs and a 'rc' heap manager that is statically + allocated at 0xfe800000 (the CAR base) and consumes about 0x130000 + bytes of memory. config CPU_MICROCODE_CBFS_LOC hex @@ -104,4 +113,21 @@ config DIMM_SPD_SIZE int default 512 +if INTEL_TXT + +config INTEL_TXT_SINIT_SIZE + hex + default 0x50000 + help + According to document number 572782 this needs to be 256KiB + for the SINIT module and 64KiB for SINIT data. + +config INTEL_TXT_HEAP_SIZE + hex + default 0xf0000 + help + This must be 960KiB according to 572782. + +endif # INTEL_TXT + endif diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 592a316e062..778d277a0ce 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,8 @@ static void chip_enable_dev(struct device *dev) attach_iio_stacks(dev); } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_GPIO) { + block_gpio_enable(dev); } } @@ -68,6 +71,18 @@ static void chip_final(void *data) { /* Lock SBI */ pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); + + /* LOCK PAM */ + pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); + + /* + * LOCK SMRAM + * According to the CedarIsland FSP Integration Guide this needs to + * be done with legacy 0xCF8/0xCFC IO ops. + */ + uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); + pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); + p2sb_hide(); set_bios_init_completion(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 434b343bb2a..630bc8e9797 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include +#include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 2f4ab0663e0..4dea1a40a6e 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -51,10 +51,15 @@ static void xeon_configure_mca(void) mca_configure(); } +/* + * On server platforms the FIT mechanism only updates the microcode on + * the BSP. Loading MCU on AP in parallel seems to fail in 10% of the cases + * so do it serialized. + */ void get_microcode_info(const void **microcode, int *parallel) { *microcode = intel_mp_current_microcode(); - *parallel = 1; + *parallel = 0; } const void *intel_mp_current_microcode(void) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 198d3858293..848cb48fbb6 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -53,6 +53,7 @@ #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 #define UBOX_DECS_CPUBUSNO_CSR 0xcc +#define UBOX_DECS_CPUBUSNO1_CSR 0xd0 #define VTD_TOLM_CSR 0xd0 #define VTD_TSEG_BASE_CSR 0xa8 @@ -122,4 +123,13 @@ // ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 +// DMI3 B0D0F0 registers +#define DMI3_DEVID 0x2020 +#define DMIRCBAR 0x50 +#define ERRINJCON 0x1d8 + +// IIO DFX Global D7F7 registers +#define IIO_DFX_TSWCTL0 0x30c +#define IIO_DFX_LCK_CTL 0x504 + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 6f47a302346..e423d0a6d1b 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -163,5 +163,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->VtdSupport = config->vtd_support; m_cfg->X2apic = config->x2apic; + /* Disable ISOC */ + m_cfg->isocEn = 0; + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 8e73008b75a..99326ee6a43 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -8,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -26,13 +26,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -void acpi_create_gnvs(struct global_nvs *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); -} - int soc_madt_sci_irq_polarity(int sci) { if (sci >= 20) @@ -218,7 +211,7 @@ void soc_power_states_generation(int core, int cores_per_package) ratio >= ratio_min; ratio -= ratio_step) { /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); + power = common_calculate_power_ratio(power_max, ratio_max, ratio); clock = ratio * CONFIG_CPU_BCLK_MHZ; //clock = 1; acpigen_write_PSS_package( diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 743251b5fcb..dfa78b2abf3 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -4,27 +4,14 @@ #define _SOC_ACPI_H_ #include -#include #define MEM_BLK_COUNT 0x140 typedef struct { uint8_t buf[32]; } MEM_BLK; -/* P-state configuration */ -#define PSS_MAX_ENTRIES 16 -#define PSS_RATIO_STEP 1 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -uint32_t soc_read_sci_irq_select(void); -int soc_madt_sci_irq_polarity(int sci); -void soc_power_states_generation(int core, int cores_per_package); -acpi_tstate_t *soc_get_tss_table(int *entries); -acpi_cstate_t *soc_get_cstate_map(size_t *entries); -int calculate_power(int tdp, int p1_ratio, int ratio); void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index f5a45c61063..5087e4f68b7 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -70,6 +70,12 @@ #define ENABLE_SMI_PARAMS \ (APMC_EN | GBL_SMI_EN | EOS) +/* P-state configuration */ +#define PSS_MAX_ENTRIES 16 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + /* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ #define ETR 0xac #define CF9_LOCK (1 << 31) diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 2637017c89a..8ff54fc1cbd 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -8,7 +8,7 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); void unlock_pam_regions(void); -void get_stack_busnos(uint32_t *bus); +uint8_t get_stack_busno(const uint8_t stack); msr_t read_msr_ppin(void); int get_threads_per_package(void); int get_platform_thread_count(void); diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545bd4f..f0cb6db63d8 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -3,24 +3,14 @@ #include #include #include -#include #include #include #include -static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { - { 0, 0 } -}; - -const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) -{ - return xeon_lpc_fixed_mmio_ranges; -} - -void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) { - const config_t *config = config_of(dev); + const config_t *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; @@ -28,15 +18,6 @@ void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n"); diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index f101973864f..8b08326fb61 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -37,6 +38,8 @@ static void soc_enable_dev(struct device *dev) attach_iio_stacks(dev); } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_GPIO) { + block_gpio_enable(dev); } } diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index 08608997b38..4ee1ac0a0d0 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -5,6 +5,7 @@ #include #include +#include #include struct soc_intel_xeon_sp_skx_config { diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index d36f11be669..f9cd356efcb 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -193,7 +193,8 @@ static void pre_mp_init(void) { printk(BIOS_DEBUG, "%s: entry\n", __func__); - x86_setup_fixed_mtrrs(); + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); } static void post_mp_init(void) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index ce223cc2d46..39f62123548 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -77,6 +77,7 @@ #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 #define UBOX_DECS_CPUBUSNO_CSR 0xcc +#define UBOX_DECS_CPUBUSNO1_CSR 0xd0 #define VTD_TOLM_CSR 0xd0 #define VTD_TSEG_BASE_CSR 0xa8 @@ -167,4 +168,13 @@ // ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 +// DMI3 B0D0F0 registers +#define DMI3_DEVID 0x2020 +#define DMIRCBAR 0x50 +#define ERRINJCON 0x1d8 + +// IIO DFX Global D7F7 registers +#define IIO_DFX_TSWCTL0 0x30c +#define IIO_DFX_LCK_CTL 0x504 + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 53b9d27b041..2d286231a6f 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -8,10 +7,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -26,17 +25,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); - - /* Update the mem console pointer. */ - if (CONFIG(CONSOLE_CBMEM)) - gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); -} - int soc_madt_sci_irq_polarity(int sci) { if (sci >= 20) diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 8965b3b81f6..dede931fe06 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -12,7 +12,6 @@ #include #include #include -#include struct map_entry { uint32_t reg; @@ -230,8 +229,8 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) configure_dpr(dev); union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; if (dpr.size) { - uint32_t dpr_base_k = (dpr.top - dpr.size) << 10; - uint32_t dpr_size_k = dpr.size << 10; + uint64_t dpr_base_k = (dpr.top - dpr.size) << 10; + uint64_t dpr_size_k = dpr.size << 10; reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k); LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k); } @@ -348,3 +347,60 @@ static const struct pci_driver vtd_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = MMAP_VTD_STACK_CFG_REG_DEVID, }; + +static void dmi3_init(struct device *dev) +{ + /* Disable error injection */ + pci_or_config16(dev, ERRINJCON, 1 << 0); + + /* + * DMIRCBAR registers are not TXT lockable, but the BAR enable + * bit is. TXT requires that DMIRCBAR be disabled for security. + */ + pci_and_config32(dev, DMIRCBAR, ~(1 << 0)); +} + +static struct device_operations dmi3_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = dmi3_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver dmi3_driver __pci_driver = { + .ops = &dmi3_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = DMI3_DEVID, +}; + +static void iio_dfx_global_init(struct device *dev) +{ + uint16_t reg16; + pci_or_config16(dev, IIO_DFX_LCK_CTL, 0x3ff); + reg16 = pci_read_config16(dev, IIO_DFX_TSWCTL0); + reg16 &= ~(1 << 4); // allow ib mmio cfg + reg16 &= ~(1 << 5); // ignore acs p2p ma lpbk + reg16 |= (1 << 3); // me disable + pci_write_config16(dev, IIO_DFX_TSWCTL0, reg16); +} + +static const unsigned short iio_dfx_global_ids[] = { + 0x202d, + 0x203d, + 0 +}; + +static struct device_operations iio_dfx_global_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = iio_dfx_global_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver iio_dfx_global_driver __pci_driver = { + .ops = &iio_dfx_global_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = iio_dfx_global_ids, +}; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index b4f7eaab3c7..c0b05cbf6c3 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -13,19 +13,15 @@ #include #include -void get_stack_busnos(uint32_t *bus) +uint8_t get_stack_busno(const uint8_t stack) { - uint32_t reg1, reg2; - - reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xcc); - reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), - 0xd0); - - for (int i = 0; i < 4; ++i) - bus[i] = ((reg1 >> (i * 8)) & 0xff); - for (int i = 0; i < 2; ++i) - bus[4+i] = ((reg2 >> (i * 8)) & 0xff); + if (stack >= MAX_IIO_STACK) { + printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); + return 0; + } + const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); + const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR; + return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; } void unlock_pam_regions(void) diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2505bbc0752..8254dc5e87d 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -154,8 +154,11 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) break; } - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + tmp_reg |= NON_CONTINUOUS_CLK; + + if (!(mode_flags & MIPI_DSI_MODE_EOT_PACKET)) + tmp_reg |= EOTP_DISABLE; write32(&dsi0->dsi_txrx_ctrl, tmp_reg); } @@ -202,6 +205,10 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes, phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3; u32 delta = 12; + + if (mode_flags & MIPI_DSI_MODE_EOT_PACKET) + delta += 2; + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) delta += 6; diff --git a/src/soc/mediatek/mt8192/flash_controller.c b/src/soc/mediatek/common/flash_controller.c similarity index 66% rename from src/soc/mediatek/mt8192/flash_controller.c rename to src/soc/mediatek/common/flash_controller.c index aa43af6e0d4..cdda056b9f0 100644 --- a/src/soc/mediatek/mt8192/flash_controller.c +++ b/src/soc/mediatek/common/flash_controller.c @@ -3,7 +3,8 @@ #include #include #include -#include +#include +#include #include #include #include @@ -12,6 +13,8 @@ #include #include +static struct mtk_nor_regs *const mtk_nor = (void *)SFLASH_REG_BASE; + #define GET_NTH_BYTE(d, n) ((d >> (8 * n)) & 0xff) static int polling_cmd(u32 val) @@ -20,7 +23,7 @@ static int polling_cmd(u32 val) stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); - while ((read32(&mt8192_nor->cmd) & val) != 0) { + while ((read32(&mtk_nor->cmd) & val) != 0) { if (stopwatch_expired(&sw)) return -1; } @@ -28,20 +31,20 @@ static int polling_cmd(u32 val) return 0; } -static int mt8192_nor_execute_cmd(u8 cmdval) +static int mtk_nor_execute_cmd(u8 cmdval) { u8 val = cmdval & ~SFLASH_AUTOINC; - write8(&mt8192_nor->cmd, cmdval); + write8(&mtk_nor->cmd, cmdval); return polling_cmd(val); } static int sflashhw_read_flash_status(u8 *value) { - if (mt8192_nor_execute_cmd(SFLASH_READSTATUS)) + if (mtk_nor_execute_cmd(SFLASH_READSTATUS)) return -1; - *value = read8(&mt8192_nor->rdsr); + *value = read8(&mtk_nor->rdsr); return 0; } @@ -65,9 +68,9 @@ static int wait_for_write_done(void) /* set serial flash program address */ static void set_sfpaddr(u32 addr) { - write8(&mt8192_nor->radr[2], GET_NTH_BYTE(addr, 2)); - write8(&mt8192_nor->radr[1], GET_NTH_BYTE(addr, 1)); - write8(&mt8192_nor->radr[0], GET_NTH_BYTE(addr, 0)); + write8(&mtk_nor->radr[2], GET_NTH_BYTE(addr, 2)); + write8(&mtk_nor->radr[1], GET_NTH_BYTE(addr, 1)); + write8(&mtk_nor->radr[0], GET_NTH_BYTE(addr, 0)); } static int sector_erase(int offset) @@ -75,16 +78,16 @@ static int sector_erase(int offset) if (wait_for_write_done()) return -1; - write8(&mt8192_nor->prgdata[5], SFLASH_OP_WREN); - write8(&mt8192_nor->cnt, 8); - mt8192_nor_execute_cmd(SFLASH_PRG_CMD); + write8(&mtk_nor->prgdata[5], SFLASH_OP_WREN); + write8(&mtk_nor->cnt, 8); + mtk_nor_execute_cmd(SFLASH_PRG_CMD); - write8(&mt8192_nor->prgdata[5], SECTOR_ERASE_CMD); - write8(&mt8192_nor->prgdata[4], GET_NTH_BYTE(offset, 2)); - write8(&mt8192_nor->prgdata[3], GET_NTH_BYTE(offset, 1)); - write8(&mt8192_nor->prgdata[2], GET_NTH_BYTE(offset, 0)); - write8(&mt8192_nor->cnt, 32); - mt8192_nor_execute_cmd(SFLASH_PRG_CMD); + write8(&mtk_nor->prgdata[5], SECTOR_ERASE_CMD); + write8(&mtk_nor->prgdata[4], GET_NTH_BYTE(offset, 2)); + write8(&mtk_nor->prgdata[3], GET_NTH_BYTE(offset, 1)); + write8(&mtk_nor->prgdata[2], GET_NTH_BYTE(offset, 0)); + write8(&mtk_nor->cnt, 32); + mtk_nor_execute_cmd(SFLASH_PRG_CMD); if (wait_for_write_done()) return -1; @@ -100,17 +103,17 @@ static int dma_read(u32 addr, uintptr_t dma_buf, u32 len) IS_ALIGNED(len, SFLASH_DMA_ALIGN)); /* do dma reset */ - write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_SW_RESET); - write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); + write32(&mtk_nor->fdma_ctl, SFLASH_DMA_SW_RESET); + write32(&mtk_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); /* flash source address and dram dest address */ - write32(&mt8192_nor->fdma_fadr, addr); - write32(&mt8192_nor->fdma_dadr, dma_buf); - write32(&mt8192_nor->fdma_end_dadr, (dma_buf + len)); + write32(&mtk_nor->fdma_fadr, addr); + write32(&mtk_nor->fdma_dadr, dma_buf); + write32(&mtk_nor->fdma_end_dadr, (dma_buf + len)); /* start dma */ - write32(&mt8192_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); + write32(&mtk_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); - while ((read32(&mt8192_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) { + while ((read32(&mtk_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) { if (stopwatch_expired(&sw)) { printk(BIOS_WARNING, "dma read timeout!\n"); return -1; @@ -132,8 +135,18 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, u32 done, read_len, copy_len; uint8_t *dest = (uint8_t *)buf; - setbits8(&mt8192_nor->read_dual, SFLASH_READ_DUAL_EN); - write8(&mt8192_nor->prgdata[3], SFLASH_1_1_2_READ); + /* Refer to CB:13989 for the hardware limitation on mt8173. */ + if (CONFIG(SOC_MEDIATEK_MT8173)) { + if (!ENV_BOOTBLOCK && !ENV_SEPARATE_VERSTAGE) { + dma_buf = (uintptr_t)_dram_dma; + dma_buf_len = REGION_SIZE(dram_dma); + } + } + + if (CONFIG(FLASH_DUAL_READ)) { + setbits8(&mtk_nor->read_dual, SFLASH_READ_DUAL_EN); + write8(&mtk_nor->prgdata[3], SFLASH_1_1_2_READ); + } /* DMA: start [ skip | len | drop ] = total end */ for (done = 0; done < total; dest += copy_len) { @@ -161,8 +174,8 @@ static int nor_write(const struct spi_flash *flash, u32 addr, size_t len, set_sfpaddr(addr); while (len) { - write8(&mt8192_nor->wdata, *buffer); - if (mt8192_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC)) + write8(&mtk_nor->wdata, *buffer); + if (mtk_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC)) return -1; if (wait_for_write_done()) @@ -200,7 +213,7 @@ const struct spi_flash_ops spi_flash_ops = { int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash) { - write32(&mt8192_nor->wrprot, SFLASH_COMMAND_ENABLE); + write32(&mtk_nor->wrprot, SFLASH_COMMAND_ENABLE); memcpy(&flash->spi, spi, sizeof(*spi)); flash->sector_size = 0x1000; diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 7bacec1c779..aebe62aa367 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -118,6 +118,12 @@ enum { MIX_MODE = BIT(17) }; +/* DSI_TXRX_CTRL */ +enum { + EOTP_DISABLE = BIT(6), + NON_CONTINUOUS_CLK = BIT(16), +}; + /* DSI_PSCTRL */ enum { DSI_PS_WC = 0x3fff, diff --git a/src/soc/mediatek/mt8192/include/soc/flash_controller.h b/src/soc/mediatek/common/include/soc/flash_controller_common.h similarity index 82% rename from src/soc/mediatek/mt8192/include/soc/flash_controller.h rename to src/soc/mediatek/common/include/soc/flash_controller_common.h index 5373a87ef3b..2da3805da1e 100644 --- a/src/soc/mediatek/mt8192/include/soc/flash_controller.h +++ b/src/soc/mediatek/common/include/soc/flash_controller_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ -#define __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ +#ifndef __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ +#define __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ #include #include @@ -36,7 +36,7 @@ enum { }; /* register Offset */ -struct mt8192_nor_regs { +struct mtk_nor_regs { u32 cmd; u32 cnt; u32 rdsr; @@ -73,9 +73,8 @@ struct mt8192_nor_regs { u32 fdma_dadr; u32 fdma_end_dadr; }; -check_member(mt8192_nor_regs, fdma_end_dadr, 0x724); -static struct mt8192_nor_regs *const mt8192_nor = (void *)SFLASH_REG_BASE; +check_member(mtk_nor_regs, fdma_end_dadr, 0x724); int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); -#endif /* __SOC_MEDIATEK_MT8192_FLASH_CONTROLLER_H__ */ +#endif /* __SOC_MEDIATEK_COMMON_FLASH_CONTROLLER_COMMON_H__ */ diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d9ba2308e9d..ae6ad64ded5 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -3,6 +3,7 @@ #ifndef SOC_MEDIATEK_PLL_COMMON_H #define SOC_MEDIATEK_PLL_COMMON_H +#include #include #include @@ -54,6 +55,15 @@ struct pll { .div_rate = _div_rate, \ } +/* every PLL can share the same POWER_EN/ISO_EN/EN bits, use the common BITFIELD macro */ +DEFINE_BIT(PLL_ENABLE, 0) + +DEFINE_BIT(PLL_POWER_ENABLE, 0) +DEFINE_BIT(PLL_ISO_ENABLE, 1) +DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0) + +DEFINE_BITFIELD(PLL_CON1, 31, 0) + void pll_set_pcw_change(const struct pll *pll); void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 5159f376bf7..4a864311d90 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -6,7 +6,7 @@ #include #include #include -#include +#include #define RTCTAG "[RTC]" #define rtc_info(fmt, arg ...) printk(BIOS_INFO, RTCTAG "%s,%d: " fmt, \ @@ -95,33 +95,13 @@ enum { }; /* external API */ -int rtc_busy_wait(void); -int rtc_write_trigger(void); -int rtc_writeif_unlock(void); -int rtc_xosc_write(u16 val); -int rtc_reg_init(void); +bool rtc_write_trigger(void); +bool rtc_writeif_unlock(void); +bool rtc_xosc_write(u16 val); +bool rtc_lpen(u16 con); +bool rtc_reg_init(void); +void rtc_osc_init(void); +bool rtc_powerkey_init(void); void rtc_boot_common(void); -static inline s32 rtc_read(u16 addr, u16 *rdata) -{ - s32 ret; - - ret = pwrap_read(addr, rdata); - if (ret < 0) - rtc_info("pwrap_read fail: ret=%d\n", ret); - - return ret; -} - -static inline s32 rtc_write(u16 addr, u16 wdata) -{ - s32 ret; - - ret = pwrap_write(addr, wdata); - if (ret < 0) - rtc_info("pwrap_write fail: ret=%d\n", ret); - - return ret; -} - #endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index 0925f7f6f8f..f36bbc57e47 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -2,11 +2,10 @@ #include #include -#include #include /* ensure rtc write success */ -int rtc_busy_wait(void) +static bool rtc_busy_wait(void) { struct stopwatch sw; u16 bbpu; @@ -18,30 +17,30 @@ int rtc_busy_wait(void) /* Time > 1sec, time out and set recovery mode enable.*/ if (stopwatch_expired(&sw)) { rtc_info("BBPU CBUSY time out !!\n"); - return 0; + return false; } } while (bbpu & RTC_BBPU_CBUSY); - return 1; + return true; } -int rtc_write_trigger(void) +bool rtc_write_trigger(void) { rtc_write(RTC_WRTGR, 1); return rtc_busy_wait(); } /* unlock rtc write interface */ -int rtc_writeif_unlock(void) +bool rtc_writeif_unlock(void) { rtc_write(RTC_PROT, RTC_PROT_UNLOCK1); if (!rtc_write_trigger()) - return 0; + return false; rtc_write(RTC_PROT, RTC_PROT_UNLOCK2); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } /* set rtc time */ @@ -72,20 +71,20 @@ int rtc_get(struct rtc_time *time) } /* set rtc xosc setting */ -int rtc_xosc_write(u16 val) +bool rtc_xosc_write(u16 val) { u16 bbpu; rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); if (!rtc_busy_wait()) - return 0; + return false; rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); if (!rtc_busy_wait()) - return 0; + return false; rtc_write(RTC_OSC32CON, val); if (!rtc_busy_wait()) - return 0; + return false; rtc_read(RTC_BBPU, &bbpu); bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD; @@ -94,8 +93,32 @@ int rtc_xosc_write(u16 val) return rtc_write_trigger(); } +/* enable lpd subroutine */ +bool rtc_lpen(u16 con) +{ + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + + if (!rtc_write_trigger()) + return false; + + con |= RTC_CON_LPRST; + rtc_write(RTC_CON, con); + + if (!rtc_write_trigger()) + return false; + + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + + if (!rtc_write_trigger()) + return false; + + return true; +} + /* initialize rtc related registers */ -int rtc_reg_init(void) +bool rtc_reg_init(void) { u16 irqsta; @@ -113,7 +136,7 @@ int rtc_reg_init(void) rtc_write(RTC_DIFF, 0); rtc_write(RTC_CALI, 0); if (!rtc_write_trigger()) - return 0; + return false; rtc_read(RTC_IRQ_STA, &irqsta); /* read clear */ @@ -129,6 +152,14 @@ int rtc_reg_init(void) return rtc_write_trigger(); } +/* write powerkeys to enable rtc functions */ +bool rtc_powerkey_init(void) +{ + rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + return rtc_write_trigger(); +} + static u8 rtc_check_state(void) { u16 con; @@ -164,18 +195,21 @@ void rtc_boot_common(void) switch (rtc_check_state()) { case RTC_STATE_REBOOT: - pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, - 0xFFFF, 0); + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_write_trigger(); rtc_osc_init(); + rtc_info("RTC_STATE_REBOOT\n"); break; case RTC_STATE_RECOVER: rtc_init(1); + rtc_info("RTC_STATE_RECOVER\n"); break; case RTC_STATE_INIT: default: if (rtc_init(0)) rtc_init(1); + rtc_info("RTC_STATE_INIT\n"); break; } diff --git a/src/soc/mediatek/common/rtc_osc_init.c b/src/soc/mediatek/common/rtc_osc_init.c new file mode 100644 index 00000000000..521e7a09818 --- /dev/null +++ b/src/soc/mediatek/common/rtc_osc_init.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* 32k clock calibration */ +static int rtc_eosc_cali(void) +{ + u16 diff_left, diff_right, cksel; + u16 val = 0; + u16 middle; + u16 left = RTC_XOSCCALI_START; + u16 right = RTC_XOSCCALI_END; + + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + cksel &= ~PMIC_FQMTR_CKSEL_MASK; + /* select EOSC_32 as fixed clock */ + rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K); + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + rtc_info("PMIC_RG_FQMTR_CKSEL=%#x\n", cksel); + + while (left <= right) { + middle = (right + left) / 2; + if (middle == left) + break; + + /* select 26M as target clock */ + val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) + break; + + if (val > RTC_FQMTR_HIGH_BASE) + right = middle; + else + left = middle; + } + + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) + return middle; + + val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); + diff_left = ABS(val - RTC_FQMTR_LOW_BASE); + + val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0); + diff_right = ABS(val - RTC_FQMTR_LOW_BASE); + + rtc_info("left: %d, middle: %d, right: %d\n", left, middle, right); + if (diff_left < diff_right) + return left; + else + return right; +} + +void rtc_osc_init(void) +{ + u16 osc32con; + + /* enable 32K export */ + rtc_gpio_init(); + /* calibrate eosc32 for powerdown clock */ + rtc_read(RTC_OSC32CON, &osc32con); + rtc_info("osc32con val = %#x\n", osc32con); + osc32con &= ~RTC_XOSCCALI_MASK; + osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK; + rtc_xosc_write(osc32con); + rtc_info("EOSC32 cali val = %#x\n", osc32con); +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 871a68995d3..e824e54e14d 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -3,7 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c -bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/spi.c spi.c @@ -27,12 +27,12 @@ verstage-y += ../common/uart.c verstage-y += ../common/timer.c verstage-y += timer.c verstage-y += ../common/wdt.c ../common/reset.c -verstage-$(CONFIG_SPI_FLASH) += flash_controller.c +verstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c ################################################################################ -romstage-$(CONFIG_SPI_FLASH) += flash_controller.c +romstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c @@ -53,7 +53,7 @@ romstage-y += ../common/rtc.c rtc.c ramstage-y += emi.c ramstage-y += ../common/spi.c spi.c -ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c ramstage-y += soc.c ../common/mtcmos.c ramstage-y += ../common/timer.c ramstage-y += timer.c diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 79d54aa784c..32582709d8d 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -1086,7 +1086,7 @@ void perbit_window_cal(u32 channel, u8 type) } if (fail == 1) /* error handling */ - die("fail on perbit_window_cal()\n"); + die("fail on %s()\n", __func__); dramc_dbg_msg("==================================================\n"); dramc_dbg_msg(" dramc_perbit_window_swcal:\n"); diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c deleted file mode 100644 index 64eff2e3098..00000000000 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff) - -static int polling_cmd(u32 val) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); - - while ((read32(&mt8173_nor->cmd) & val) != 0) { - if (stopwatch_expired(&sw)) - return -1; - } - - return 0; -} - -static int mt8173_nor_execute_cmd(u8 cmdval) -{ - u8 val = cmdval & ~(SFLASH_AUTOINC); - - write8(&mt8173_nor->cmd, cmdval); - return polling_cmd(val); -} - -static int sflashhw_read_flash_status(u8 *value) -{ - if (mt8173_nor_execute_cmd(SFLASH_READSTATUS)) - return -1; - - *value = read8(&mt8173_nor->rdsr); - return 0; -} - -static int wait_for_write_done(void) -{ - struct stopwatch sw; - u8 reg; - - stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); - - while (sflashhw_read_flash_status(®) == 0) { - if (!(reg & SFLASH_WRITE_IN_PROGRESS)) - return 0; - if (stopwatch_expired(&sw)) - return -1; - } - - return -1; -} - -/* set serial flash program address */ -static void set_sfpaddr(u32 addr) -{ - write8(&mt8173_nor->radr[2], get_nth_byte(addr, 2)); - write8(&mt8173_nor->radr[1], get_nth_byte(addr, 1)); - write8(&mt8173_nor->radr[0], get_nth_byte(addr, 0)); -} - -static int sector_erase(int offset) -{ - if (wait_for_write_done()) - return -1; - - write8(&mt8173_nor->prgdata[5], SFLASH_OP_WREN); - write8(&mt8173_nor->cnt, 8); - mt8173_nor_execute_cmd(SFLASH_PRG_CMD); - - write8(&mt8173_nor->prgdata[5], SECTOR_ERASE_CMD); - write8(&mt8173_nor->prgdata[4], get_nth_byte(offset, 2)); - write8(&mt8173_nor->prgdata[3], get_nth_byte(offset, 1)); - write8(&mt8173_nor->prgdata[2], get_nth_byte(offset, 0)); - write8(&mt8173_nor->cnt, 32); - mt8173_nor_execute_cmd(SFLASH_PRG_CMD); - - if (wait_for_write_done()) - return -1; - - return 0; -} - -static int dma_read(u32 addr, u8 *buf, u32 len, uintptr_t dma_buf, - size_t dma_buf_len) -{ - struct stopwatch sw; - - assert(IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN) && - IS_ALIGNED(len, SFLASH_DMA_ALIGN) && - len <= dma_buf_len); - - /* do dma reset */ - write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_SW_RESET); - write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_WDLE_EN); - /* flash source address and dram dest address */ - write32(&mt8173_nor->fdma_fadr, addr); - write32(&mt8173_nor->fdma_dadr, dma_buf); - write32(&mt8173_nor->fdma_end_dadr, (dma_buf + len)); - /* start dma */ - write32(&mt8173_nor->fdma_ctl, SFLASH_DMA_TRIGGER | SFLASH_DMA_WDLE_EN); - - stopwatch_init_usecs_expire(&sw, SFLASH_POLLINGREG_US); - while ((read32(&mt8173_nor->fdma_ctl) & SFLASH_DMA_TRIGGER) != 0) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, "dma read timeout!\n"); - return -1; - } - } - - memcpy(buf, (const void *)dma_buf, len); - return 0; -} - -static int pio_read(u32 addr, u8 *buf, u32 len) -{ - set_sfpaddr(addr); - while (len) { - if (mt8173_nor_execute_cmd(SFLASH_RD_TRIGGER | SFLASH_AUTOINC)) - return -1; - - *buf++ = read8(&mt8173_nor->rdata); - len--; - } - return 0; -} - -static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, - void *buf) -{ - u32 next; - - size_t done = 0; - uintptr_t dma_buf; - size_t dma_buf_len; - - if (!IS_ALIGNED((uintptr_t)buf, SFLASH_DMA_ALIGN)) { - next = MIN(ALIGN_UP((uintptr_t)buf, SFLASH_DMA_ALIGN) - - (uintptr_t)buf, len); - if (pio_read(addr, buf, next)) - return -1; - done += next; - } - - if (ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) { - dma_buf = (uintptr_t)_dma_coherent; - dma_buf_len = REGION_SIZE(dma_coherent); - } else { - dma_buf = (uintptr_t)_dram_dma; - dma_buf_len = REGION_SIZE(dram_dma); - } - - while (len - done >= SFLASH_DMA_ALIGN) { - next = MIN(dma_buf_len, ALIGN_DOWN(len - done, - SFLASH_DMA_ALIGN)); - if (dma_read(addr + done, buf + done, next, dma_buf, - dma_buf_len)) - return -1; - done += next; - } - next = len - done; - if (next > 0 && pio_read(addr + done, buf + done, next)) - return -1; - return 0; -} - -static int nor_write(const struct spi_flash *flash, u32 addr, size_t len, - const void *buf) -{ - const u8 *buffer = (const u8 *)buf; - - set_sfpaddr(addr); - while (len) { - write8(&mt8173_nor->wdata, *buffer); - if (mt8173_nor_execute_cmd(SFLASH_WR_TRIGGER | SFLASH_AUTOINC)) - return -1; - - if (wait_for_write_done()) - return -1; - buffer++; - len--; - } - return 0; -} - -static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len) -{ - int sector_start = offset; - int sector_num = (u32)len / flash->sector_size; - - while (sector_num) { - if (!sector_erase(sector_start)) { - sector_start += flash->sector_size; - sector_num--; - } else { - printk(BIOS_WARNING, "Erase failed at 0x%x!\n", - sector_start); - return -1; - } - } - return 0; -} - -const struct spi_flash_ops spi_flash_ops = { - .read = nor_read, - .write = nor_write, - .erase = nor_erase, -}; - -int mtk_spi_flash_probe(const struct spi_slave *spi, - struct spi_flash *flash) -{ - write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE); - memcpy(&flash->spi, spi, sizeof(*spi)); - - flash->sector_size = 0x1000; - flash->erase_cmd = SECTOR_ERASE_CMD; - flash->size = CONFIG_ROM_SIZE; - - flash->ops = &spi_flash_ops; - - return 0; -} diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h deleted file mode 100644 index 6ac8da34716..00000000000 --- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ -#define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ - -#include -#include -#include - -enum { - SFLASH_POLLINGREG_US = 500000, - SFLASH_WRBUF_SIZE = 128, - SFLASHNAME_LENGTH = 16, - SFLASH_WRITE_IN_PROGRESS = 1, - SFLASH_COMMAND_ENABLE = 0x30, - SFLASH_DMA_ALIGN = 0x10, - - /* NOR flash controller commands */ - SFLASH_RD_TRIGGER = 1 << 0, - SFLASH_READSTATUS = 1 << 1, - SFLASH_PRG_CMD = 1 << 2, - SFLASH_WR_TRIGGER = 1 << 4, - SFLASH_WRITESTATUS = 1 << 5, - SFLASH_AUTOINC = 1 << 7, - /* NOR flash commands */ - SFLASH_OP_WREN = 0x6, - SECTOR_ERASE_CMD = 0x20, - SFLASH_UNPROTECTED = 0x0, - /* DMA commands */ - SFLASH_DMA_TRIGGER = 1 << 0, - SFLASH_DMA_SW_RESET = 1 << 1, - SFLASH_DMA_WDLE_EN = 1 << 2 -}; - -/* register Offset */ -struct mt8173_nor_regs { - u32 cmd; - u32 cnt; - u32 rdsr; - u32 rdata; - u32 radr[3]; - u32 wdata; - u32 prgdata[6]; - u32 shreg[10]; - u32 cfg[2]; - u32 shreg10; - u32 status[5]; - u32 timing; - u32 flash_cfg; - u32 reserved2[3]; - u32 sf_time; - u32 reserved3; - u32 diff_addr; - u32 del_sel[2]; - u32 intrstus; - u32 intren; - u32 pp_ctl; - u32 cfg3; - u32 chksum_ctl; - u32 chksum; - u32 aaicmd; - u32 wrprot; - u32 radr3; - u32 read_dual; - u32 delsel[3]; - u32 reserved[397]; - u32 cfg1_bri[2]; - u32 fdma_ctl; - u32 fdma_fadr; - u32 fdma_dadr; - u32 fdma_end_dadr; -}; -check_member(mt8173_nor_regs, fdma_end_dadr, 0x724); -static struct mt8173_nor_regs *const mt8173_nor = (void *)SFLASH_REG_BASE; - -int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); - -#endif /* __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index d0d302366da..e82d514e86c 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -3,7 +3,9 @@ #ifndef SOC_MEDIATEK_MT8173_RTC_H #define SOC_MEDIATEK_MT8173_RTC_H +#include #include +#include #include #include "mt6391.h" @@ -98,8 +100,29 @@ enum { }; /* external API */ -void rtc_osc_init(void); -int rtc_init(u8 recover); +int rtc_init(int recover); void rtc_boot(void); +static inline s32 rtc_read(u16 addr, u16 *rdata) +{ + s32 ret; + + ret = pwrap_read(addr, rdata); + if (ret < 0) + rtc_info("pwrap_read failed: ret=%d\n", ret); + + return ret; +} + +static inline s32 rtc_write(u16 addr, u16 wdata) +{ + s32 ret; + + ret = pwrap_write(addr, wdata); + if (ret < 0) + rtc_info("pwrap_write failed: ret=%d\n", ret); + + return ret; +} + #endif /* SOC_MEDIATEK_MT8173_RTC_H */ diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h index 1cf6dde0c9a..ae5d998c6bd 100644 --- a/src/soc/mediatek/mt8173/include/soc/symbols.h +++ b/src/soc/mediatek/mt8173/include/soc/symbols.h @@ -2,6 +2,7 @@ #ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ #define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ +#include DECLARE_REGION(dram_dma) diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index ba99a13211b..caa15ea182f 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -120,7 +120,7 @@ static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel) pwrap_write_nochk(PMIC_TOP_CKCON2, wdata); pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata); if (rdata != wdata) { - pwrap_err("pwrap_init_reg_clock,rdata=%#x\n", rdata); + pwrap_err("%s,rdata=%#x\n", __func__, rdata); return E_PWR_INIT_REG_CLOCK; } /* Config SPI Waveform according to reg clk */ diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index d08de45325a..d60f722564a 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include +#include #include #include #include @@ -10,7 +10,7 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) /* initialize rtc related gpio */ -static int rtc_gpio_init(void) +static bool rtc_gpio_init(void) { u16 con; @@ -41,25 +41,25 @@ void rtc_osc_init(void) } /* low power detect setting */ -static int rtc_lpd_init(void) +static bool rtc_lpd_init(void) { pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0); if (!rtc_write_trigger()) - return 0; + return false; pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0); if (!rtc_write_trigger()) - return 0; + return false; pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } /* rtc init check */ -int rtc_init(u8 recover) +int rtc_init(int recover) { int ret; @@ -84,6 +84,7 @@ int rtc_init(u8 recover) goto err; } + /* In recovery mode, we need delay for register setting. */ if (recover) mdelay(1000); diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index dd5c2aecdcf..4abd650bd9e 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 744455d5aa3..e0ec81012b0 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -37,7 +37,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c -romstage-y += ../common/rtc.c rtc.c +romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/timer.c @@ -54,7 +54,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmic_wrap.c -ramstage-y += ../common/rtc.c rtc.c +ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += spm.c diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index eba3f5e3483..395c8212a10 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -34,7 +34,7 @@ static void ovl_bgclr_in_sel(u32 idx) static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, int enable_relay) { - write32(®s->size, height << 16 | width); + write32(®s->size, width << 16 | height); if (enable_relay) write32(®s->cfg, PQ_RELAY_MODE); write32(®s->en, PQ_EN); diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 8a5d319b293..99c87a5fbd3 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -735,7 +735,8 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) return 0; } -static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) +static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr, + const struct sdram_params *params) { u8 *MR01Value = mr->MR01Value; u8 MR02Value[FSP_MAX] = {0x12, 0x12}; @@ -744,12 +745,13 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) u8 MR12Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { {{0x5d, 0x5d}, {0x5d, 0x5d} }, {{0x5d, 0x5d}, {0x5d, 0x5d} }, }; - u8 MR13Value; + u8 MR13Value = 0x18; u8 MR14Value[CHANNEL_MAX][RANK_MAX][FSP_MAX] = { {{0x5d, 0x10}, {0x5d, 0x10} }, {{0x5d, 0x10}, {0x5d, 0x10} }, }; u8 MR22Value[FSP_MAX] = {0x38, 0x34}; + u32 cbt_mode = params->cbt_mode_extern; MR01Value[FSP_0] = 0x6; MR01Value[FSP_1] = 0x6; @@ -767,7 +769,7 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) MR01Value[FSP_0] |= (0x5 << 4); MR01Value[FSP_1] |= (0x5 << 4); } else if (freq_group == LP4X_DDR3200) { - MR02Value[0] = 0x12; + MR02Value[0] = 0x1a; MR02Value[1] = 0x2d; MR01Value[FSP_0] |= (0x5 << 4); @@ -780,6 +782,9 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) MR01Value[FSP_1] |= (0x6 << 4); } + if (cbt_mode) + MR11Value[FSP_1] = 0x13; + u8 operate_fsp = get_freq_fsq(freq_group); dramc_dbg("%s operate_fsp:%d, freq:%d\n", __func__, operate_fsp, freq_group); @@ -789,7 +794,7 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) dramc_power_on_sequence(); for (chn = 0; chn < CHANNEL_MAX; chn++) { - for (rank = 0; rank < 2; rank++) { + for (rank = 0; rank < params->rank_num; rank++) { clrsetbits32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24); dramc_zq_calibration(chn, rank); @@ -808,6 +813,15 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) dramc_mode_reg_write(chn, 0x2, MR02Value[fsp]); dramc_mode_reg_write(chn, 0xb, MR11Value[fsp]); + if (cbt_mode == CBT_R0_NORMAL_R1_BYTE) { + if (rank == 0) + MR22Value[FSP_1] = 0x3c; + else + MR22Value[FSP_1] = 0x34; + } else { + MR22Value[FSP_1] = 0x34; + } + dramc_mode_reg_write(chn, 0x16, MR22Value[fsp]); dramc_mode_reg_write(chn, 0xe, MR14Value[chn][rank][fsp]); @@ -856,7 +870,7 @@ static void auto_refresh_cke_off(void) dramc_set_broadcast(broadcast_bak); } -static void dramc_setting_DDR1600(void) +static void dramc_setting_DDR1600(u32 cbt_mode) { clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), @@ -869,8 +883,13 @@ static void dramc_setting_DDR1600(void) clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600); clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600); - clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), - (0x0 << 29) | (0x1 << 31)); + + if (cbt_mode) + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 31), (0x1 << 31)); + else + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), + (0x0 << 29) | (0x1 << 31)); + clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0); for (size_t rank = 0; rank < 2; rank++) { @@ -880,16 +899,21 @@ static void dramc_setting_DDR1600(void) (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (value << 0) | (value << 8) | (value << 16) | (value << 24)); - clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], - (0x7 << 8) | (0x7 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), - (0x2 << 8) | (0x2 << 12) | - (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); - clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], - (0x7 << 8) | (0x7 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), - (0x2 << 8) | (0x2 << 12) | - (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); + for (size_t b = 0; b < 2; b++) { + if (cbt_mode) { + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b], + (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | + (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); + } else { + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b], + (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x2 << 8) | (0x2 << 12) | + (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); + } + } clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], @@ -899,11 +923,20 @@ static void dramc_setting_DDR1600(void) clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20); - clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], - (0x3 << 4) | (0x1 << 7) | (0x1 << 13), - (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); + + if (cbt_mode) + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4), + (0x2 << 4)); + else + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + + if (cbt_mode == 0) + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], + (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -914,7 +947,7 @@ static void dramc_setting_DDR1600(void) } } -static void dramc_setting_DDR2400(void) +static void dramc_setting_DDR2400(u32 cbt_mode) { clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), @@ -927,8 +960,13 @@ static void dramc_setting_DDR2400(void) clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); - clrsetbits32(&ch[0].ao.shu[0].wodt, - (0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31)); + + if (cbt_mode) + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 31), (0x0 << 31)); + else + clrsetbits32(&ch[0].ao.shu[0].wodt, + (0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31)); + clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0); for (size_t rank = 0; rank < 2; rank++) { @@ -939,16 +977,21 @@ static void dramc_setting_DDR2400(void) (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); - clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], - (0x7 << 8) | (0x7 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), - (0x3 << 8) | (0x3 << 12) | - (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); - clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], - (0x7 << 8) | (0x7 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), - (0x3 << 8) | (0x3 << 12) | - (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + for (size_t b = 0; b < 2; b++) { + if (cbt_mode) { + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b], + (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | + (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + } else { + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[b], + (0x7 << 8) | (0x7 << 12) | + (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), + (0x3 << 8) | (0x3 << 12) | + (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + } + } clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], @@ -958,12 +1001,19 @@ static void dramc_setting_DDR2400(void) clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], - (0x3 << 4) | (0x1 << 7) | (0x1 << 13), - (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); + + if (cbt_mode) + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4), (0x1 << 4)); + else + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], - (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); + + if (cbt_mode == 0) + setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { for (size_t b = 0; b < 2; b++) @@ -1288,11 +1338,13 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, (0x4 << 20) | (0x4 << 24) | (0x6 << 28)); udelay(2); - clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien, - (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8)); - clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, - (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), - (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24)); + if (params->cbt_mode_extern == CBT_R0_R1_NORMAL) { + clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien, + (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8)); + clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, + (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), + (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24)); + } setbits32(&ch[0].ao.dramctrl, 0x1 << 19); clrsetbits32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0); @@ -1317,25 +1369,34 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, udelay(1); clrsetbits32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); - clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); - clrsetbits32(&ch[0].ao.perfctl0, - (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); - setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28); - clrbits32(&ch[0].ao.rstmask, 0x1 << 28); - setbits32(&ch[0].ao.rkcfg, 0x1 << 11); - setbits32(&ch[0].ao.mpc_option, 0x1 << 17); - setbits32(&ch[0].ao.eyescan, 0x1 << 2); - setbits32(&ch[0].ao.shu[0].wodt, 0x1 << 29); - setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); - setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); - clrsetbits32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); + if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) { + clrsetbits32(&ch[0].ao.perfctl0, + (0x1 << 18) | (0x1 << 19) | (0x1 << 27), + (0x0 << 18) | (0x1 << 19) | (0x1 << 27)); + clrbits32(&ch[0].ao.rstmask, 0x1 << 28); + setbits32(&ch[0].ao.rkcfg, 0x1 << 11); + setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28); + setbits32(&ch[0].ao.eyescan, 0x1 << 2); + } else { + clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.perfctl0, + (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); + setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28); + clrbits32(&ch[0].ao.rstmask, 0x1 << 28); + setbits32(&ch[0].ao.rkcfg, 0x1 << 11); + setbits32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits32(&ch[0].ao.eyescan, 0x1 << 2); + setbits32(&ch[0].ao.shu[0].wodt, 0x1 << 29); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); + clrsetbits32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); - for (size_t r = 0; r < 2; r++) { - clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[0], - (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); - clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[1], - (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); + for (size_t r = 0; r < 2; r++) + for (size_t b = 0; b < 2; b++) + clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[b], + (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); } + udelay(5); clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16); @@ -1363,9 +1424,26 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, clrsetbits32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4); udelay(12); - clrsetbits32(&ch[0].ao.shu[0].rankctl, - (0xf << 24) | (0xf << 28), (0x4 << 24) | 0x6 << 28); + if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) + clrsetbits32(&ch[0].ao.shu[0].rankctl, + (0xf << 20) | (0xf << 24) | (0xf << 28), + (0x3 << 20) | (0x3 << 24) | (0x5 << 28)); + else + clrsetbits32(&ch[0].ao.shu[0].rankctl, + (0xf << 24) | (0xf << 28), + (0x4 << 24) | (0x6 << 28)); + clrbits32(&ch[0].ao.shu[0].wodt, 0x1 << 31); + + if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) { + clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien, + (0x7f << 0) | (0x7f << 8), + (0x19 << 0) | (0x19 << 8)); + clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, + (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), + (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24)); + } + clrsetbits32(&ch[0].ao.shu[0].rk[0].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24)); @@ -1383,8 +1461,16 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24), (0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24)); - setbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13)); - setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); + + if (params->cbt_mode_extern != CBT_R0_R1_NORMAL) { + setbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12)); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12)); + } else { + setbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x1 << 12) | (0x1 << 13)); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], + (0x1 << 12) | (0x1 << 13)); + } clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); /* The default dramc init settings were tuned at frequency of 3200Mbps. @@ -1392,10 +1478,10 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, the default settings. */ switch (freq_group) { case LP4X_DDR1600: - dramc_setting_DDR1600(); + dramc_setting_DDR1600(params->cbt_mode_extern); break; case LP4X_DDR2400: - dramc_setting_DDR2400(); + dramc_setting_DDR2400(params->cbt_mode_extern); break; case LP4X_DDR3200: /* Do nothing */ @@ -1423,7 +1509,7 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x3 << 16) | (0x1 << 22), (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | - (0x1 << 14) | (0x2 << 16) | (0x1 << 22)); + (0x1 << 14) | (params->rank_num << 16) | (0x1 << 22)); clrsetbits32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28); clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); udelay(1); @@ -1630,7 +1716,150 @@ static const struct ac_time ac_timing_tbl[LP4X_DDRFREQ_MAX] = { }, }; -static void ddr_update_ac_timing(u8 freq_group) +static const struct ac_time ac_timing_cbt_tbl[LP4X_DDRFREQ_MAX] = { + /* LP4x-1600, 800MHz, RDBI_OFF, byte mode */ + [LP4X_DDR1600] = { + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 0, .trpab_05T = 1, + .trc = 4, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 7, .twr_05T = 0, + .twtr = 4, .twtr_05T = 0, + .trrd = 0, .trrd_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .refcnt = 48, + .refcnt_fr_clk = 101, + .txrefcnt = 62, + .tzqcs = 16, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 3, + .xrtr2r = 8, + .r_dmcatrain_intv = 8, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 50, + .trtpd = 7, .trtpd_05T = 0, + .twtpd = 7, .twtpd_05T = 1, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 0, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 11, + }, + /* LP4x-2400, 1200MHz, RDBI_OFF, byte mode */ + [LP4X_DDR2400] = { + .tras = 4, .tras_05T = 1, + .trp = 3, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 10, .trc_05T = 0, + .trfc = 72, .trfc_05T = 0, + .trfcpb = 30, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 1, + .twr = 10, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .trrd = 1, .trrd_05T = 0, + .tfaw = 3, .tfaw_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .refcnt = 73, + .refcnt_fr_clk = 101, + .txrefcnt = 91, + .tzqcs = 25, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 6, + .xrtr2r = 8, + .r_dmcatrain_intv = 9, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 75, + .trtpd = 10, .trtpd_05T = 0, + .twtpd = 10, .twtpd_05T = 0, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 0, + .zqlat2 = 9, + .dqsinctl = 4, .datlat = 14, + }, + /* LP4x-3200, 1600MHz, RDBI_OFF, byte mode */ + [LP4X_DDR3200] = { + .tras = 8, .tras_05T = 1, + .trp = 5, .trp_05T = 1, + .trpab = 1, .trpab_05T = 0, + .trc = 16, .trc_05T = 1, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 6, .trcd_05T = 1, + .twr = 13, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .trrd = 2, .trrd_05T = 0, + .tfaw = 7, .tfaw_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .refcnt = 97, + .refcnt_fr_clk = 101, + .txrefcnt = 119, + .tzqcs = 34, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 7, + .xrtr2r = 9, + .r_dmcatrain_intv = 11, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 100, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 0, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 16, + }, + /* LP4x-3600, 1800MHz, RDBI_OFF, byte mode */ + [LP4X_DDR3600] = { + .tras = 11, .tras_05T = 1, + .trp = 6, .trp_05T = 1, + .trpab = 1, .trpab_05T = 1, + .trc = 20, .trc_05T = 1, + .trfc = 118, .trfc_05T = 1, + .trfcpb = 53, .trfcpb_05T = 1, + .txp = 1, .txp_05T = 1, + .trtp = 2, .trtp_05T = 0, + .trcd = 7, .trcd_05T = 1, + .twr = 15, .twr_05T = 1, + .twtr = 9, .twtr_05T = 0, + .trrd = 3, .trrd_05T = 0, + .tfaw = 10, .tfaw_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .refcnt = 113, + .refcnt_fr_clk = 101, + .txrefcnt = 138, + .tzqcs = 40, + .xrtw2w = 5, + .xrtw2r = 3, + .xrtr2w = 8, + .xrtr2r = 9, + .r_dmcatrain_intv = 13, + .r_dmmrw_intv = 0xf, + .r_dmfspchg_prdcnt = 117, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 0, + .tmrr2w_odt_on = 10, + .ckeprd = 3, + .ckelckcnt = 0, + .zqlat2 = 14, + .dqsinctl = 7, .datlat = 17, + }, +}; + +static void ddr_update_ac_timing(u8 freq_group, u32 cbt_mode) { struct ac_time ac_t; u32 temp, r2w_odt_onoff = ODT_ON; @@ -1638,8 +1867,12 @@ static void ddr_update_ac_timing(u8 freq_group) u8 root = 0, tx_rank_inctl = 0, tx_dly = 0; u8 trtw = 0, trtw_05t = 0, tmrr2w = 0; - memcpy(&ac_t, &ac_timing_tbl[freq_group], sizeof(struct ac_time)); - new_datlat = ac_timing_tbl[freq_group].datlat - 2; + if (cbt_mode) + memcpy(&ac_t, &ac_timing_cbt_tbl[freq_group], sizeof(struct ac_time)); + else + memcpy(&ac_t, &ac_timing_tbl[freq_group], sizeof(struct ac_time)); + + new_datlat = ac_t.datlat - 2; if (freq_group == LP4X_DDR1600) { root = 0; tx_rank_inctl = 0; tx_dly = 1; @@ -1729,10 +1962,13 @@ static void ddr_update_ac_timing(u8 freq_group) (root << 16) | (tx_rank_inctl << 12) | (tx_dly << 8)); } - u8 dram_cbt_mode = 0; clrsetbits32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10); - clrsetbits32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode); - clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); + clrsetbits32(&ch[0].ao.rstmask, 0x3 << 13, cbt_mode << 13); + + if (cbt_mode == 0) + clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, 0 << 13); + else + clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, 1 << 13); } void dramc_init(const struct sdram_params *params, u8 freq_group, @@ -1743,6 +1979,6 @@ void dramc_init(const struct sdram_params *params, u8 freq_group, dramc_duty_calibration(params, freq_group); dvfs_settings(freq_group); - dramc_mode_reg_init(freq_group, &shared->mr); - ddr_update_ac_timing(freq_group); + dramc_mode_reg_init(freq_group, &shared->mr, params); + ddr_update_ac_timing(freq_group, params->cbt_mode_extern); } diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 4a884b19761..d992371fac9 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -347,9 +347,9 @@ static void dramc_phy_low_power_enable(u8 chn) (chn == CHANNEL_A) ? 0xba000 : 0x3a000); } -static void dramc_dummy_read_for_tracking_enable(u8 chn) +static void dramc_dummy_read_for_tracking_enable(u8 chn, u32 rk_num) { - setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16); + setbits32(&ch[chn].ao.dummy_rd, rk_num << 16); for (size_t r = 0; r < 2; r++) for (size_t i = 0; i < 4; i++) @@ -403,7 +403,7 @@ static void dramc_enable_dramc_dcm(void) } } -void dramc_runtime_config(void) +void dramc_runtime_config(u32 rk_num) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) clrbits32(&ch[chn].ao.refctrl0, 0x1 << 29); @@ -412,7 +412,7 @@ void dramc_runtime_config(void) setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - dramc_hw_dqsosc(chn); + dramc_hw_dqsosc(chn, rk_num); /* RX_TRACKING: ON */ dramc_rx_input_delay_tracking(chn); @@ -426,7 +426,7 @@ void dramc_runtime_config(void) (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); /* DUMMY_READ_FOR_TRACKING: ON */ - dramc_dummy_read_for_tracking_enable(chn); + dramc_dummy_read_for_tracking_enable(chn, rk_num); /* ZQCS_ENABLE_LP4: ON */ clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 17fa2306e39..ec39049a8a9 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -266,7 +266,7 @@ static void cbt_set_perbit_delay_cell(u8 chn, u8 rank) } static void set_dram_mr_cbt_on_off(u8 chn, u8 rank, u8 fsp, - u8 cbt_on, struct mr_value *mr) + bool cbt_on, struct mr_value *mr, u32 cbt_mode) { u8 MR13Value = mr->MR13Value; @@ -276,6 +276,9 @@ static void set_dram_mr_cbt_on_off(u8 chn, u8 rank, u8 fsp, MR13Value &= 0x7f; else MR13Value |= 0x80; + + if (cbt_mode) + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_BYTEMODECBTEN, 1); } else { MR13Value &= 0xfe; if (fsp == FSP_1) @@ -322,7 +325,7 @@ static void o1_path_on_off(u8 cbt_on) udelay(1); } -static void cbt_entry(u8 chn, u8 rank, u8 fsp, struct mr_value *mr) +static void cbt_entry(u8 chn, u8 rank, u8 fsp, struct mr_value *mr, u32 cbt_mode) { SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_PHYCLKDYNGEN, 0, @@ -331,26 +334,31 @@ static void cbt_entry(u8 chn, u8 rank, u8 fsp, struct mr_value *mr) SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_MIOCKCTRLOFF, 1); dramc_cke_fix_onoff(CKE_FIXON, chn); - set_dram_mr_cbt_on_off(chn, rank, fsp, 1, mr); - SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_WRITE_LEVEL_EN, 1); + set_dram_mr_cbt_on_off(chn, rank, fsp, true, mr, cbt_mode); + + if (cbt_mode == 0) + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_WRITE_LEVEL_EN, 1); udelay(1); dramc_cke_fix_onoff(CKE_FIXOFF, chn); o1_path_on_off(1); } -static void cbt_exit(u8 chn, u8 rank, u8 fsp, struct mr_value *mr) +static void cbt_exit(u8 chn, u8 rank, u8 fsp, struct mr_value *mr, u32 cbt_mode) { dramc_cke_fix_onoff(CKE_FIXON, chn); udelay(1); - set_dram_mr_cbt_on_off(chn, rank, fsp, 0, mr); + set_dram_mr_cbt_on_off(chn, rank, fsp, false, mr, cbt_mode); o1_path_on_off(0); + + if (cbt_mode) + SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_BYTEMODECBTEN, 0); } -static void cbt_set_vref(u8 chn, u8 rank, u8 vref, bool is_final) +static void cbt_set_vref(u8 chn, u8 rank, u8 vref, bool is_final, u32 cbt_mode) { - if (!is_final) { + if (cbt_mode == 0 && !is_final) { SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DMVREFCA, vref); SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DQS_SEL, 1); SET32_BITFIELDS(&ch[chn].ao.write_lev, WRITE_LEV_DQSBX_G, 0xa); @@ -394,12 +402,18 @@ static void cbt_set_ca_clk_result(u8 chn, u8 rank, } } -static u8 get_cbt_vref_pinmux_value(u8 chn, u8 vref_level) +static u8 get_cbt_vref_pinmux_value(u8 chn, u8 vref_level, u32 cbt_mode) { u8 vref_bit, vref_new, vref_org; vref_new = 0; vref_org = BIT(6) | (vref_level & 0x3f); + + if (cbt_mode) { + dramc_dbg("vref_org: %#x for byte mode\n", vref_org); + + return vref_org; + } for (vref_bit = 0; vref_bit < 8; vref_bit++) { if (vref_org & (1 << vref_bit)) vref_new |= (1 << phy_mapping[chn][vref_bit]); @@ -410,11 +424,14 @@ static u8 get_cbt_vref_pinmux_value(u8 chn, u8 vref_level) return vref_new; } -static void cbt_dramc_dfs_direct_jump(u8 shu_level) +static void cbt_dramc_dfs_direct_jump(u8 shu_level, bool run_dvfs) { u8 shu_ack = 0; static bool phy_pll_en = true; + if (!run_dvfs) + return; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) shu_ack |= (0x1 << chn); @@ -490,20 +507,21 @@ static void cbt_dramc_dfs_direct_jump(u8 shu_level) phy_pll_en = !phy_pll_en; } -static void cbt_switch_freq(cbt_freq freq) +static void cbt_switch_freq(cbt_freq freq, bool run_dvfs) { if (freq == CBT_LOW_FREQ) - cbt_dramc_dfs_direct_jump(DRAM_DFS_SHUFFLE_MAX - 1); + cbt_dramc_dfs_direct_jump(DRAM_DFS_SHUFFLE_MAX - 1, run_dvfs); else - cbt_dramc_dfs_direct_jump(DRAM_DFS_SHUFFLE_1); + cbt_dramc_dfs_direct_jump(DRAM_DFS_SHUFFLE_1, run_dvfs); } static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, - const struct sdram_params *params, const bool fast_calib, - struct mr_value *mr) + const struct sdram_params *params, struct mr_value *mr, + bool run_dvfs) { u8 final_vref, cs_dly; u8 fsp = get_freq_fsq(freq_group); + u32 cbt_mode = params->cbt_mode_extern; cs_dly = params->cbt_cs_dly[chn][rank]; final_vref = params->cbt_final_vref[chn][rank]; @@ -521,6 +539,7 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, regs_bak[i].value = read32(regs_bak[i].addr); dramc_auto_refresh_switch(chn, false); + if (rank == RANK_1) { SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_TXRANK, rank); @@ -530,16 +549,35 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, cbt_set_perbit_delay_cell(chn, rank); - if (fsp == FSP_1) - cbt_switch_freq(CBT_LOW_FREQ); - cbt_entry(chn, rank, fsp, mr); - if (fsp == FSP_1) - cbt_switch_freq(CBT_HIGH_FREQ); + if (cbt_mode == 0) { + cbt_mrr_pinmux_mapping(); + if (fsp == FSP_1) + cbt_switch_freq(CBT_LOW_FREQ, run_dvfs); + cbt_entry(chn, rank, fsp, mr, cbt_mode); + udelay(1); + if (fsp == FSP_1) + cbt_switch_freq(CBT_HIGH_FREQ, run_dvfs); + } - u8 new_vref = get_cbt_vref_pinmux_value(chn, final_vref); - cbt_set_vref(chn, rank, new_vref, 0); + u8 new_vref = get_cbt_vref_pinmux_value(chn, final_vref, cbt_mode); + + if (cbt_mode) { + if (fsp == FSP_1) + cbt_switch_freq(CBT_LOW_FREQ, run_dvfs); + + cbt_set_fsp(chn, rank, fsp, mr); + cbt_set_vref(chn, rank, new_vref, true, cbt_mode); + cbt_entry(chn, rank, fsp, mr, cbt_mode); + udelay(1); + + if (fsp == FSP_1) + cbt_switch_freq(CBT_HIGH_FREQ, run_dvfs); + } else { + cbt_set_vref(chn, rank, new_vref, false, cbt_mode); + } cbt_set_ca_clk_result(chn, rank, params); + udelay(1); for (u8 rk = 0; rk < rank + 1; rk++) { /* Set CLK and CS delay */ @@ -548,14 +586,16 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, } if (fsp == FSP_1) - cbt_switch_freq(CBT_LOW_FREQ); - cbt_exit(chn, rank, fsp, mr); + cbt_switch_freq(CBT_LOW_FREQ, run_dvfs); + cbt_exit(chn, rank, fsp, mr, cbt_mode); - cbt_set_fsp(chn, rank, fsp, mr); - cbt_set_vref(chn, rank, final_vref, 1); + if (cbt_mode == 0) { + cbt_set_fsp(chn, rank, fsp, mr); + cbt_set_vref(chn, rank, final_vref, true, cbt_mode); + } if (fsp == FSP_1) - cbt_switch_freq(CBT_HIGH_FREQ); + cbt_switch_freq(CBT_HIGH_FREQ, run_dvfs); /* restore MRR pinmux */ set_mrr_pinmux_mapping(); @@ -693,7 +733,7 @@ static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group) clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } -void dramc_apply_config_before_calibration(u8 freq_group) +void dramc_apply_config_before_calibration(u8 freq_group, u32 cbt_mode) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { dramc_enable_phy_dcm(chn, false); @@ -710,8 +750,20 @@ void dramc_apply_config_before_calibration(u8 freq_group) clrbits32(&ch[chn].ao.dramctrl, 0x1 << 18); clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 31); clrbits32(&ch[chn].ao.spcmdctrl, 0x1 << 30); - clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); - clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); + + if (cbt_mode == CBT_R0_R1_NORMAL) { + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); + } else if (cbt_mode == CBT_R0_R1_BYTE) { + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); + } else if (cbt_mode == CBT_R0_NORMAL_R1_BYTE) { + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); + } else if (cbt_mode == CBT_R0_BYTE_R1_NORMAL) { + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 26); + clrbits32(&ch[chn].ao.dqsoscr, 0x1 << 25); + } dramc_write_dbi_onoff(chn, false); dramc_read_dbi_onoff(chn, false); @@ -751,9 +803,9 @@ void dramc_apply_config_before_calibration(u8 freq_group) } } -static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr) +static void dramc_set_mr13_vrcg_to_normal(u8 chn, const struct mr_value *mr, u32 rk_num) { - for (u8 rank = 0; rank < RANK_MAX; rank++) + for (u8 rank = 0; rank < rk_num; rank++) dramc_mode_reg_write_by_rank(chn, rank, 13, mr->MR13Value & ~(0x1 << 3)); @@ -761,14 +813,14 @@ static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr) clrbits32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); } -void dramc_apply_config_after_calibration(const struct mr_value *mr) +void dramc_apply_config_after_calibration(const struct mr_value *mr, u32 rk_num) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); clrbits32(&ch[chn].ao.refctrl1, 0x1 << 7); clrbits32(&ch[chn].ao.shuctrl, 0x1 << 2); clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); - dramc_set_mr13_vrcg_to_Normal(chn, mr); + dramc_set_mr13_vrcg_to_normal(chn, mr, rk_num); clrbits32(&ch[chn].phy.b[0].dq[6], 0x3); clrbits32(&ch[chn].phy.b[1].dq[6], 0x3); @@ -2358,7 +2410,7 @@ static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 freq_group, u8 datlat0, u8 dramc_dle_factor_handler(chn, final_datlat, freq_group); } -static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) +static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group, u32 rk_num) { s8 dqsinctl; u32 read_dqsinctl, rankinctl_root, reg_tx_dly_dqsgated_min = 3; @@ -2372,7 +2424,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) reg_tx_dly_dqsgated_min = 1; /* get TXDLY_Cal_min and TXDLY_Cal_max value */ - for (size_t rank = 0; rank < RANK_MAX; rank++) { + for (size_t rank = 0; rank < rk_num; rank++) { u32 dqsg0 = read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0); for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { best_coarse_tune2t[rank][dqs] = (dqsg0 >> (dqs * 8)) & 0x7; @@ -2397,7 +2449,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) txdly_cal_min += dqsinctl; txdly_cal_max += dqsinctl; - for (size_t rank = 0; rank < RANK_MAX; rank++) { + for (size_t rank = 0; rank < rk_num; rank++) { dramc_dbg("Rank: %zd\n", rank); for (size_t dqs = 0; dqs < DQS_NUMBER; dqs++) { best_coarse_tune2t[rank][dqs] += dqsinctl; @@ -2515,7 +2567,7 @@ static void dqsosc_auto(u8 chn, u8 rank, u8 freq_group, SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, dqsosc_cnt[1]); } -void dramc_hw_dqsosc(u8 chn) +void dramc_hw_dqsosc(u8 chn, u32 rk_num) { u32 freq_shu1 = get_shu_freq(DRAM_DFS_SHUFFLE_1); u32 freq_shu2 = get_shu_freq(DRAM_DFS_SHUFFLE_2); @@ -2544,7 +2596,10 @@ void dramc_hw_dqsosc(u8 chn) SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 1); SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_DQSOSCR_RK0EN, 1); - SET32_BITFIELDS(&ch[chn].ao.rk[1].dqsosc, RK1_DQSOSC_DQSOSCR_RK1EN, 1); + + if (rk_num == RANK_MAX) + SET32_BITFIELDS(&ch[chn].ao.rk[1].dqsosc, RK1_DQSOSC_DQSOSCR_RK1EN, 1); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) @@ -2994,7 +3049,7 @@ void dramc_dqs_precalculation_preset(void) } } -void get_dram_info_after_cal(u8 *density_result) +void get_dram_info_after_cal(u8 *density_result, u32 rk_num) { u8 vendor_id, density, max_density = 0; u32 ddr_size, max_size = 0; @@ -3002,7 +3057,7 @@ void get_dram_info_after_cal(u8 *density_result) vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5); dramc_show("Vendor id is %#x\n", vendor_id); - for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + for (u8 rk = RANK_0; rk < rk_num; rk++) { density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8); dramc_dbg("MR8 %#x\n", density); density = (density >> 2) & 0xf; @@ -3044,7 +3099,7 @@ void get_dram_info_after_cal(u8 *density_result) } int dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group, struct mr_value *mr) + u8 freq_group, struct mr_value *mr, bool run_dvfs) { bool fast_calib; switch (pams->source) { @@ -3064,11 +3119,11 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u16 osc_thrd_inc[RANK_MAX]; u16 osc_thrd_dec[RANK_MAX]; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + for (u8 rk = RANK_0; rk < pams->rank_num; rk++) { dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", freq_group, chn, rk); dramc_cmd_bus_training(chn, rk, freq_group, pams, - fast_calib, mr); + mr, run_dvfs); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true); @@ -3092,7 +3147,7 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, } dqsosc_shu_settings(chn, freq_group, osc_thrd_inc, osc_thrd_dec); - dramc_rx_dqs_gating_post_process(chn, freq_group); + dramc_rx_dqs_gating_post_process(chn, freq_group, pams->rank_num); dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); } return 0; diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 8afbef00d87..5e4f01531a8 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -157,6 +157,19 @@ static void set_rank_info_to_conf(const struct sdram_params *params) (is_dual_rank ? 0 : 1) << 12); } +void cbt_mrr_pinmux_mapping(void) +{ + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + const u8 *map = phy_mapping[chn]; + write32(&ch[chn].ao.mrr_bit_mux1, + (map[8] << 0) | (map[9] << 8) | + (map[10] << 16) | (map[11] << 24)); + + write32(&ch[chn].ao.mrr_bit_mux2, + (map[12] << 0) | (map[13] << 8)); + } +} + void set_mrr_pinmux_mapping(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { @@ -432,7 +445,7 @@ static void dfs_init_for_calibration(const struct sdram_params *params, struct dram_shared_data *shared) { dramc_init(params, freq_group, shared); - dramc_apply_config_before_calibration(freq_group); + dramc_apply_config_before_calibration(freq_group, params->cbt_mode_extern); } static void init_dram(const struct sdram_params *params, u8 freq_group, @@ -449,7 +462,7 @@ static void init_dram(const struct sdram_params *params, u8 freq_group, dramc_sw_impedance_cal(params, ODT_ON, &shared->impedance); dramc_init(params, freq_group, shared); - dramc_apply_config_before_calibration(freq_group); + dramc_apply_config_before_calibration(freq_group, params->cbt_mode_extern); emi_init2(params); } @@ -589,9 +602,10 @@ static int run_calib(const struct dramc_param *dparam, *first_run = false; dramc_dbg("Start K (current clock: %u\n", params->frequency); - if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) + if (dramc_calibrate_all_channels(params, freq_group, &shared->mr, + !!(dparam->header.config & DRAMC_CONFIG_DVFS)) != 0) return -1; - get_dram_info_after_cal(&density); + get_dram_info_after_cal(&density, params->rank_num); dramc_ac_timing_optimize(freq_group, density); dramc_dbg("K finished (current clock: %u\n", params->frequency); @@ -599,10 +613,10 @@ static int run_calib(const struct dramc_param *dparam, return 0; } -static void after_calib(const struct mr_value *mr) +static void after_calib(const struct mr_value *mr, u32 rk_num) { - dramc_apply_config_after_calibration(mr); - dramc_runtime_config(); + dramc_apply_config_after_calibration(mr, rk_num); + dramc_runtime_config(rk_num); } int mt_set_emi(const struct dramc_param *dparam) @@ -623,6 +637,6 @@ int mt_set_emi(const struct dramc_param *dparam) if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_1, &first_run) != 0) return -1; - after_calib(&shared.mr); + after_calib(&shared.mr, dparam->freq_params[DRAM_DFS_SHUFFLE_1].rank_num); return 0; } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index c630b5aa908..9ab889b8e19 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -47,6 +47,13 @@ enum { CBT_BYTE_MODE1 }; +enum { + CBT_R0_R1_NORMAL = 0, /* Normal mode */ + CBT_R0_R1_BYTE, /* Byte mode */ + CBT_R0_NORMAL_R1_BYTE, /* Mixed mode R0: Normal R1: Byte */ + CBT_R0_BYTE_R1_NORMAL /* Mixed mode R0: Byte R1: Normal */ +}; + enum { FSP_0 = 0, FSP_1, diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index f925162e4a0..3758547d13e 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -10,7 +10,7 @@ enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 4, + DRAMC_PARAM_HEADER_VERSION = 5, }; enum DRAMC_PARAM_STATUS_CODES { @@ -38,9 +38,13 @@ enum DRAMC_PARAM_FLAGS { }; enum DRAMC_PARAM_GEOMETRY_TYPE { + DDR_TYPE_2CH_1RK_4GB_4, DDR_TYPE_2CH_2RK_4GB_2_2, DDR_TYPE_2CH_2RK_6GB_3_3, DDR_TYPE_2CH_2RK_8GB_4_4, + DDR_TYPE_2CH_RK0_RK1_BYTE_8GB_4_4, + DDR_TYPE_2CH_RK0_NORMAL_RK1_BYTE_8GB_4_4, + DDR_TYPE_2CH_RK0_BYTE_RK1_NORMAL_8GB_4_4, }; struct dramc_param_header { diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index a0937d01c62..b1a0c74f145 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -97,7 +97,7 @@ enum { }; void dramc_get_rank_size(u64 *dram_rank_size); -void dramc_runtime_config(void); +void dramc_runtime_config(u32 rk_num); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); u8 get_freq_fsq(u8 freq_group); @@ -107,18 +107,19 @@ void dramc_sw_impedance_save_reg(u8 freq_group, const struct dram_impedance *impedance); void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, struct dram_impedance *impedance); -void dramc_apply_config_before_calibration(u8 freq_group); -void dramc_apply_config_after_calibration(const struct mr_value *mr); +void dramc_apply_config_before_calibration(u8 freq_group, u32 cbt_mode); +void dramc_apply_config_after_calibration(const struct mr_value *mr, u32 rk_num); int dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group, struct mr_value *mr); + u8 freq_group, struct mr_value *mr, bool run_dvfs); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(u8 chn, bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); u32 get_shu_freq(u8 shu); -void dramc_hw_dqsosc(u8 chn); +void dramc_hw_dqsosc(u8 chn, u32 rk_num); void dramc_dqs_precalculation_preset(void); -void get_dram_info_after_cal(u8 *density); +void get_dram_info_after_cal(u8 *density, u32 rk_num); void set_mrr_pinmux_mapping(void); void dramc_cke_fix_onoff(enum cke_type option, u8 chn); +void cbt_mrr_pinmux_mapping(void); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 6931d5bb815..16f0b2e8f5e 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -15,6 +15,7 @@ enum DRAMC_PARAM_SOURCE { struct sdram_params { u16 source; /* DRAMC_PARAM_SOURCE */ u16 frequency; + u32 rank_num; u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 0e5c598d31f..7ca054a940e 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -3,7 +3,9 @@ #ifndef SOC_MEDIATEK_MT8183_RTC_H #define SOC_MEDIATEK_MT8183_RTC_H +#include #include +#include /* RTC registers */ enum { @@ -203,9 +205,32 @@ enum { /* external API */ void rtc_bbpu_power_on(void); -void rtc_osc_init(void); -int rtc_init(u8 recover); +int rtc_init(int recover); +bool rtc_gpio_init(void); void rtc_boot(void); +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); void mt6358_dcxo_disable_unused(void); +static inline s32 rtc_read(u16 addr, u16 *rdata) +{ + s32 ret; + + ret = pwrap_read(addr, rdata); + if (ret < 0) + rtc_info("pwrap_read failed: ret=%d\n", ret); + + return ret; +} + +static inline s32 rtc_write(u16 addr, u16 wdata) +{ + s32 ret; + + ret = pwrap_write(addr, wdata); + if (ret < 0) + rtc_info("pwrap_write failed: ret=%d\n", ret); + + return ret; +} + #endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 400412fffb6..e90aa9df6ea 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -2,8 +2,8 @@ #include #include -#include #include +#include #include #include #include @@ -11,7 +11,7 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) /* initialize rtc setting of using dcxo clock */ -static int rtc_enable_dcxo(void) +static bool rtc_enable_dcxo(void) { u16 bbpu, con, osc32con, sec; @@ -20,9 +20,9 @@ static int rtc_enable_dcxo(void) rtc_write_trigger(); mdelay(1); - if (!rtc_writeif_unlock()) { /* Unlock for reload */ + if (!rtc_writeif_unlock()) { rtc_info("rtc_writeif_unlock() failed\n"); - return 0; + return false; } rtc_read(RTC_OSC32CON, &osc32con); @@ -32,7 +32,7 @@ static int rtc_enable_dcxo(void) | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; if (!rtc_xosc_write(osc32con)) { rtc_info("rtc_xosc_write() failed\n"); - return 0; + return false; } rtc_read(RTC_CON, &con); @@ -40,11 +40,11 @@ static int rtc_enable_dcxo(void) rtc_read(RTC_AL_SEC, &sec); rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec); - return 1; + return true; } /* initialize rtc related gpio */ -static int rtc_gpio_init(void) +bool rtc_gpio_init(void) { u16 con; @@ -67,7 +67,7 @@ static int rtc_gpio_init(void) return rtc_write_trigger(); } -static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { u16 bbpu, osc32con; u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; @@ -115,7 +115,7 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); if (stopwatch_expired(&sw)) { rtc_info("get frequency time out !!\n"); - return 0; + return false; } } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); @@ -142,95 +142,8 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) return fqmtr_data; } -/* 32k clock calibration */ -static u16 rtc_eosc_cali(void) -{ - u16 middle, diff1, diff2, cksel; - u16 val = 0; - u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; - - rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); - cksel &= ~PMIC_FQMTR_CKSEL_MASK; - /* select EOSC_32 as fixed clock */ - rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K); - rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); - rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel); - - while (left <= right) { - middle = (right + left) / 2; - if (middle == left) - break; - - /* select 26M as target clock */ - val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - - if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) - break; - if (val > RTC_FQMTR_HIGH_BASE) - right = middle; - else - left = middle; - } - - if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) - return middle; - - val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if (val > RTC_FQMTR_LOW_BASE) - diff1 = val - RTC_FQMTR_LOW_BASE; - else - diff1 = RTC_FQMTR_LOW_BASE - val; - - val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if (val > RTC_FQMTR_LOW_BASE) - diff2 = val - RTC_FQMTR_LOW_BASE; - else - diff2 = RTC_FQMTR_LOW_BASE - val; - - if (diff1 < diff2) - return left; - else - return right; -} - -void rtc_osc_init(void) -{ - u16 osc32con; - - /* enable 32K export */ - rtc_gpio_init(); - - /* Calibrate eosc32 for powerdown clock */ - rtc_read(RTC_OSC32CON, &osc32con); - osc32con &= ~RTC_XOSCCALI_MASK; - osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK; - rtc_xosc_write(osc32con); - rtc_info("EOSC32 cali val = 0x%x\n", osc32con); -} - -/* enable lpd subroutine */ -static int rtc_lpen(u16 con) -{ - con &= ~RTC_CON_LPRST; - rtc_write(RTC_CON, con); - if (!rtc_write_trigger()) - return 0; - - con |= RTC_CON_LPRST; - rtc_write(RTC_CON, con); - if (!rtc_write_trigger()) - return 0; - - con &= ~RTC_CON_LPRST; - rtc_write(RTC_CON, con); - if (!rtc_write_trigger()) - return 0; - - return 1; -} - /* low power detect setting */ -static int rtc_lpd_init(void) +static bool rtc_lpd_init(void) { u16 con, sec; @@ -239,19 +152,19 @@ static int rtc_lpd_init(void) sec |= RTC_LPD_OPT_F32K_CK_ALIVE; rtc_write(RTC_AL_SEC, sec); if (!rtc_write_trigger()) - return 0; + return false; /* init XOSC32 to detect 32k clock stop */ rtc_read(RTC_CON, &con); con |= RTC_CON_XOSC32_LPEN; if (!rtc_lpen(con)) - return 0; + return false; /* init EOSC32 to detect rtc low power */ rtc_read(RTC_CON, &con); con |= RTC_CON_EOSC32_LPEN; if (!rtc_lpen(con)) - return 0; + return false; rtc_read(RTC_CON, &con); con &= ~RTC_CON_XOSC32_LPEN; @@ -263,9 +176,9 @@ static int rtc_lpd_init(void) sec |= RTC_LPD_OPT_EOSC_LPD; rtc_write(RTC_AL_SEC, sec); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } static bool rtc_hw_init(void) @@ -291,16 +204,8 @@ static bool rtc_hw_init(void) return true; } -/* write powerkeys to enable rtc functions */ -static int rtc_powerkey_init(void) -{ - rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); - rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); - return rtc_write_trigger(); -} - /* rtc init check */ -int rtc_init(u8 recover) +int rtc_init(int recover) { int ret; @@ -320,6 +225,7 @@ int rtc_init(u8 recover) rtc_osc_init(); + /* In recovery mode, we need 20ms delay for register setting. */ if (recover) mdelay(20); @@ -343,7 +249,8 @@ int rtc_init(u8 recover) goto err; } - /* After lpd init, powerkeys need to be written again to enable + /* + * After lpd init, powerkeys need to be written again to enable * low power detect function. */ if (!rtc_powerkey_init()) { diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 7373fe1579c..e2d7eeac13c 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -75,4 +75,18 @@ config SSPM_FIRMWARE help The file name of the MediaTek SSPM firmware. +config FLASH_DUAL_READ + bool + default y + help + When this option is enabled, the flash controller provides the ability + to dual read mode. + +config SRCLKEN_RC_SUPPORT + bool + default y + help + This option enables clock buffer remote controller module + to control PMIC 26MHz clock output. + endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 1f70e4318ef..ad8b3d984f7 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -2,7 +2,9 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c -bootblock-y += flash_controller.c +bootblock-y += clkbuf.c srclken_rc.c +bootblock-y += eint_event.c +bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c @@ -12,11 +14,12 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c bootblock-y += mt6315.c bootblock-y += mt6359p.c verstage-y += ../common/auxadc.c -verstage-y += flash_controller.c +verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -25,9 +28,10 @@ verstage-y += ../common/uart.c romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c +romstage-y += dramc_utility.c dramc_dvfs.c romstage-y += emi.c -romstage-y += flash_controller.c +romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c mmu_operations.c @@ -40,9 +44,10 @@ romstage-y += mt6359p.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c +ramstage-y += devapc.c ramstage-y += dpm.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c -ramstage-y += flash_controller.c +ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/i2c.c i2c.c ramstage-y += emi.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 7987b1cf8e2..0249b156273 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -1,11 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include #include #include #include +#include +#include #include void bootblock_soc_init(void) @@ -16,4 +20,8 @@ void bootblock_soc_init(void) mtk_pmif_init(); mt6359p_init(); mt6315_init(); + srclken_rc_init(); + clk_buf_init(); + rtc_boot(); + unmask_eint_event_mask(); } diff --git a/src/soc/mediatek/mt8192/clkbuf.c b/src/soc/mediatek/mt8192/clkbuf.c new file mode 100644 index 00000000000..83fdb920674 --- /dev/null +++ b/src/soc/mediatek/mt8192/clkbuf.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + + +#define BUFTAG "[CLKBUF]" +#define buf_info(fmt, arg ...) printk(BIOS_INFO, BUFTAG "%s,%d: " fmt, \ + __func__, __LINE__, ## arg) + +#define _buf_clrset32_impl(addr, clear, set) \ + buf_write(addr, (buf_read(addr) & ~((uint32_t)(clear))) | (set)) + +#define BUF_SET_FIELDS(addr, ...) \ + _BF_IMPL(_buf_clrset32_impl, addr, __VA_ARGS__) +#define BUF_READ_FIELD(addr, name) \ + EXTRACT_BITFIELD(buf_read(addr), name) + +#define PMIC_CW00_INIT_VAL 0x4005 /* 0100 0000 0000 0101 */ +#define PMIC_CW09_INIT_VAL 0x01F0 /* 0000 0001 1111 0000 */ + +static struct pmif *pmif_arb; + +static u32 buf_read(u32 addr) +{ + u32 rdata; + + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + pmif_arb->read(pmif_arb, 0, addr, &rdata); + + return rdata; +} + +static void buf_write(u32 addr, u32 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + pmif_arb->write(pmif_arb, 0, addr, wdata); +} + +static void dump_clkbuf_log(void) +{ + u32 pmic_cw00, pmic_cw09, pmic_cw12, pmic_cw13, pmic_cw15, pmic_cw19, + top_spi_con1, ldo_vrfck_op_en, ldo_vbbck_op_en, ldo_vrfck_en, + ldo_vbbck_en, vrfck_hv_en; + + pmic_cw00 = BUF_READ_FIELD(PMIC_RG_DCXO_CW00, PMIC_REG_COMMON); + pmic_cw09 = BUF_READ_FIELD(PMIC_RG_DCXO_CW09, PMIC_REG_COMMON); + pmic_cw12 = BUF_READ_FIELD(PMIC_RG_DCXO_CW12, PMIC_REG_COMMON); + pmic_cw13 = BUF_READ_FIELD(PMIC_RG_DCXO_CW13, PMIC_REG_COMMON); + pmic_cw15 = BUF_READ_FIELD(PMIC_RG_DCXO_CW15, PMIC_REG_COMMON); + pmic_cw19 = BUF_READ_FIELD(PMIC_RG_DCXO_CW19, PMIC_REG_COMMON); + buf_info("DCXO_CW00/09/12/13/15/19=%#x %#x %#x %#x %#x %#x\n", + pmic_cw00, pmic_cw09, pmic_cw12, + pmic_cw13, pmic_cw15, pmic_cw19); + + top_spi_con1 = BUF_READ_FIELD(PMIC_RG_TOP_SPI_CON1, PMIC_RG_SRCLKEN_IN3_EN); + ldo_vrfck_op_en = BUF_READ_FIELD(PMIC_RG_LDO_VRFCK_OP_EN, + PMIC_RG_LDO_VRFCK_HW14_OP_EN); + ldo_vbbck_op_en = BUF_READ_FIELD(PMIC_RG_LDO_VBBCK_OP_EN, + PMIC_RG_LDO_VBBCK_HW14_OP_EN); + ldo_vrfck_en = BUF_READ_FIELD(PMIC_RG_LDO_VRFCK_CON0, PMIC_RG_LDO_VRFCK_EN); + ldo_vbbck_en = BUF_READ_FIELD(PMIC_RG_LDO_VBBCK_CON0, PMIC_RG_LDO_VBBCK_EN); + buf_info("spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=%#x %#x %#x %#x %#x\n", + top_spi_con1, ldo_vrfck_op_en, ldo_vbbck_op_en, + ldo_vrfck_en, ldo_vbbck_en); + + vrfck_hv_en = BUF_READ_FIELD(PMIC_RG_DCXO_ADLDO_BIAS_ELR_0, PMIC_RG_VRFCK_HV_EN); + buf_info("clk buf vrfck_hv_en=%#x\n", vrfck_hv_en); +} + +int clk_buf_init(void) +{ + /* Dump registers before setting */ + dump_clkbuf_log(); + + /* Unlock pmic key */ + BUF_SET_FIELDS(PMIC_TOP_TMA_KEY, PMIC_REG_COMMON, PMIC_TOP_TMA_KEY_UNLOCK); + + /* 1.1 Set VRFCK input supply(11.ac mode) */ + BUF_SET_FIELDS(PMIC_RG_DCXO_ADLDO_BIAS_ELR_0, PMIC_RG_VRFCK_HV_EN, 0x0); + + /* 1.2.0 Set VRFCK En = 0 */ + BUF_SET_FIELDS(PMIC_RG_LDO_VRFCK_CON0, PMIC_RG_LDO_VRFCK_EN, 0x0); + /* 1.2.1 Set VRFCK1 as power src */ + BUF_SET_FIELDS(PMIC_RG_LDO_VRFCK_ELR, PMIC_RG_LDO_VRFCK_ANA_SEL, 0x1); + + /* 1.2.2 Switch LDO-RFCK to LDO-RFCK1 */ + BUF_SET_FIELDS(PMIC_RG_DCXO_ADLDO_BIAS_ELR_0, PMIC_RG_VRFCK_NDIS_EN, 0x0); + BUF_SET_FIELDS(PMIC_RG_DCXO_ADLDO_BIAS_ELR_1, PMIC_RG_VRFCK_1_NDIS_EN, 0x1); + + /* 1.2.0 Set VRFCK En = 1 */ + BUF_SET_FIELDS(PMIC_RG_LDO_VRFCK_CON0, PMIC_RG_LDO_VRFCK_EN, 0x1); + + /* 1.2.3 Lock pmic key */ + BUF_SET_FIELDS(PMIC_TOP_TMA_KEY, PMIC_REG_COMMON, 0x0); + + /* Enable XO LDO */ + BUF_SET_FIELDS(PMIC_RG_LDO_VRFCK_OP_EN_SET, PMIC_RG_LDO_VRFCK_HW14_OP_EN, 0x1); + BUF_SET_FIELDS(PMIC_RG_LDO_VBBCK_OP_EN_SET, PMIC_RG_LDO_VBBCK_HW14_OP_EN, 0x1); + BUF_SET_FIELDS(PMIC_RG_LDO_VRFCK_CON0, PMIC_RG_LDO_VRFCK_EN, 0x0); + BUF_SET_FIELDS(PMIC_RG_LDO_VBBCK_CON0, PMIC_RG_LDO_VBBCK_EN, 0x0); + + /* Enable 26M control */ + if (!CONFIG(SRCLKEN_RC_SUPPORT)) { + /* Legacy co-clock mode */ + BUF_SET_FIELDS(PMIC_RG_TOP_SPI_CON1, PMIC_RG_SRCLKEN_IN3_EN, 0x0); + + BUF_SET_FIELDS(PMIC_RG_DCXO_CW00, PMIC_REG_COMMON, PMIC_CW00_INIT_VAL); + BUF_SET_FIELDS(PMIC_RG_DCXO_CW09, PMIC_REG_COMMON, PMIC_CW09_INIT_VAL); + } else { + /* New co-clock mode */ + /* All XO mode should set to 2'b01 */ + BUF_SET_FIELDS(PMIC_RG_DCXO_CW00, PMIC_REG_COMMON, PMIC_CW00_INIT_VAL); + BUF_SET_FIELDS(PMIC_RG_DCXO_CW09, PMIC_REG_COMMON, PMIC_CW09_INIT_VAL); + + /* 1. Update control mapping table */ + BUF_SET_FIELDS(PMIC_RG_XO_BUF_CTL0, PMIC_RG_XO_VOTE, 0x005); + BUF_SET_FIELDS(PMIC_RG_XO_BUF_CTL1, PMIC_RG_XO_VOTE, 0x0); + BUF_SET_FIELDS(PMIC_RG_XO_BUF_CTL2, PMIC_RG_XO_VOTE, 0x0); + BUF_SET_FIELDS(PMIC_RG_XO_BUF_CTL3, PMIC_RG_XO_VOTE, 0x0); + BUF_SET_FIELDS(PMIC_RG_XO_BUF_CTL4, PMIC_RG_XO_VOTE, 0x0); + /* Wait 100us */ + udelay(100); + + /* 2. Switch to new control mode */ + BUF_SET_FIELDS(PMIC_RG_DCXO_CW08, PMIC_RG_XO_PMIC_TOP_DIG_SW, 0x0); + } + + /* Check if the setting is ok */ + dump_clkbuf_log(); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c new file mode 100644 index 00000000000..77d5fc5fff5 --- /dev/null +++ b/src/soc/mediatek/mt8192/devapc.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void *getreg(uintptr_t base, unsigned int offset) +{ + return (void *)(base + offset); +} + +static void infra_master_init(uintptr_t base) +{ + /* Sidband */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1); + + /* Domain */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1); + SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2, + CPU_EB_DOM, MAS_DOMAIN_2); +} + +static void peri_master_init(uintptr_t base) +{ + /* Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, MAS_DOMAIN_2); +} + +static uintptr_t devapc_base[DEVAPC_AO_MAX] = { + DEVAPC_INFRA_AO_BASE, + DEVAPC_PERI_AO_BASE, + DEVAPC_PERI2_AO_BASE, + DEVAPC_PERI_PAR_AO_BASE, + DEVAPC_FMEM_AO_BASE, +}; + +static void (*master_init[DEVAPC_AO_MAX])(uintptr_t) = { + infra_master_init, + peri_master_init, +}; + +void dapc_init(void) +{ + int i; + uintptr_t devapc_ao_base; + + for (i = 0; i < ARRAY_SIZE(devapc_base); i++) { + devapc_ao_base = devapc_base[i]; + + /* Init dapc */ + write32(getreg(devapc_ao_base, AO_APC_CON), 0x0); + write32(getreg(devapc_ao_base, AO_APC_CON), 0x1); + + /* Init master */ + if (master_init[i]) + master_init[i](devapc_ao_base); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c new file mode 100644 index 00000000000..7fc8d28fd9e --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void enable_dfs_hw_mode_clk(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 0x3, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0x1, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0x1, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 0x0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 0x1); + } +} + +void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level) +{ + u8 shu_ack = 0; + u8 tmp_level; + u8 pll_mode = *(cali->pll_mode); + u32 *shu_ack_reg = &mtk_dpm->status_4; + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("Disable CLRPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + } else { + dramc_dbg("Disable PHYPLL\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + shu_ack |= (0x1 << chn); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 1); + + if (shu_level == DRAM_DFS_SHU0) + tmp_level = shu_level; + else + tmp_level = 1; + + if (pll_mode == PHYPLL_MODE) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 1); + } + dramc_dbg("Enable CLRPLL\n"); + } else { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 1); + } + dramc_dbg("Enable PHYPLL\n"); + } + udelay(1); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 1); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1); + + udelay(20); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 1); + while ((READ32_BITFIELD(shu_ack_reg, LPIF_STATUS_4_SHU_EN_ACK) & shu_ack) != shu_ack) + dramc_dbg("Waiting shu_en ack\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0); + + if (pll_mode == PHYPLL_MODE) + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + else + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0); + + dramc_dbg("Shuffle flow completed\n"); + + pll_mode = !pll_mode; + *(cali->pll_mode) = pll_mode; +} + +void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("Waiting dramc to shuffle sram, tmp: %u\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); +} + +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst) +{ + u8 tmp; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SRAM_WR_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_WR_MODE, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 1); + do { + tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_SRAM_DONE); + tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0, + MISC_DMA_DEBUG0_APB_DONE) << 1); + dramc_dbg("Waiting shuffle sram to dramc, tmp: %u\n", tmp); + } while (tmp != 0x3); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_DMA_FIRE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_SW_MODE, 0); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 1dae23b3488..173edf44df7 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include +#include static const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { [PINMUX_DSC] = { @@ -108,6 +111,4304 @@ void global_option_init(struct ddr_cali *cali) set_dqo1_pinmux_mapping(cali); } +static void dramc_init_default_mr_value(const struct ddr_cali *cali) +{ + struct mr_values *mr_value = cali->mr_value; + dram_freq_grp freq_group = cali->freq_group; + u8 highest_freq = get_highest_freq_group(); + + mr_value->mr01[FSP_0] = 0x26; + mr_value->mr01[FSP_1] = 0x56; + mr_value->mr02[FSP_0] = 0x1a; + mr_value->mr02[FSP_1] = 0x1a; + + mr_value->mr03[FSP_0] = 0x30 | 0x4; + mr_value->mr03[FSP_1] = 0x30 | 0x4 | 0x2; + + mr_value->mr04[RANK_0] = 0x3; + mr_value->mr04[RANK_1] = 0x3; + + mr_value->mr21[FSP_0] = 0x0; + mr_value->mr21[FSP_1] = 0x0; + mr_value->mr51[FSP_0] = 0x0; + mr_value->mr51[FSP_1] = 0x0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rk = 0; rk < RANK_MAX; rk++) { + mr_value->mr23[chn][rk] = 0x3f; + for (u8 fsp = 0; fsp < FSP_MAX; fsp++) { + mr_value->mr14[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x18; + mr_value->mr12[chn][rk][fsp] = (fsp == FSP_0) ? 0x5d : 0x1b; + } + } + + mr_value->mr01[FSP_0] &= 0x8F; + mr_value->mr01[FSP_1] &= 0x8F; + + if (highest_freq == DDRFREQ_2133) { + mr_value->mr01[FSP_0] |= (0x7 << 4); + mr_value->mr01[FSP_1] |= (0x7 << 4); + } else { + mr_value->mr01[FSP_0] |= (0x5 << 4); + mr_value->mr01[FSP_1] |= (0x5 << 4); + } + + switch (freq_group) { + case DDRFREQ_400: + mr_value->mr02[FSP_0] = 0x12; + break; + case DDRFREQ_600: + case DDRFREQ_800: + mr_value->mr02[FSP_0] = 0x12; + break; + case DDRFREQ_933: + mr_value->mr02[FSP_0] = 0x1b; + break; + case DDRFREQ_1200: + mr_value->mr02[FSP_0] = 0x24; + break; + case DDRFREQ_1600: + mr_value->mr02[FSP_1] = 0x2d; + break; + case DDRFREQ_2133: + mr_value->mr02[FSP_1] = 0x3f; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } +} + +static void sv_algorithm_assistance_lp4_800(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0e, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xff5, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x00b); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x0e, + MISC_SHU_RDAT_DATLAT_DSEL, 0x0e, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0e); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x3, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x4, + MISC_SHU_RANKCTL_RANKINCTL, 0x4, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x4, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x6); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x4, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x4, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x4); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x6, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x8, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x6, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x8, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x4, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x5, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x06); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x06); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1f, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x07); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1f, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x07); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x06, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x06, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1f, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x07, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1f, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x07, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x6, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x5, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x0, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x1, + SHURK_SELPH_DQ2_DLY_DQ1, 0x1, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x1, + SHURK_SELPH_DQ3_DLY_DQM1, 0x1, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x1, + SHURK_SELPH_DQ2_DLY_DQ1, 0x1, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x1, + SHURK_SELPH_DQ3_DLY_DQM1, 0x1, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x18, + SHURK_PI_RK0_ARPI_DQ_B0, 0x18, + SHURK_PI_RK0_ARPI_DQM_B1, 0x18, + SHURK_PI_RK0_ARPI_DQM_B0, 0x18); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x18, + SHURK_PI_RK0_ARPI_DQ_B0, 0x18, + SHURK_PI_RK0_ARPI_DQM_B1, 0x18, + SHURK_PI_RK0_ARPI_DQM_B0, 0x18); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x30, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x30, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x30, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x30); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x30, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x30, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x30, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x30); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x30, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x20, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x20, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x20, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x20); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x20, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x20, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x20, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x20); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x20, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x1, + SHU_AC_DERATING0_TRRD_DERATE, 0x2, + SHU_AC_DERATING0_TRCD_DERATE, 0x4); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0x3, + SHU_AC_DERATING1_TRP_DERATE, 0x2, + SHU_AC_DERATING1_TRAS_DERATE, 0x01, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x05, + SHU_ACTIM_XRT_XRTR2W, 0x0a, + SHU_ACTIM_XRT_XRTW2R, 0x6, + SHU_ACTIM_XRT_XRTW2W, 0x09); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x0a, + SHU_ACTIM0_TWR, 0x0c, + SHU_ACTIM0_TRRD, 0x1, + SHU_ACTIM0_TRCD, 0x4, + SHU_ACTIM0_CKELCKCNT, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0x3, + SHU_ACTIM1_TMRWCKEL, 0x7, + SHU_ACTIM1_TRP, 0x2, + SHU_ACTIM1_TRAS, 0x01, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x0, + SHU_ACTIM2_TMRRI, 0x07, + SHU_ACTIM2_TRTP, 0x3, + SHU_ACTIM2_TR2W, 0x0a, + SHU_ACTIM2_TFAW, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x1a, + SHU_ACTIM3_MANTMRR, 0x8, + SHU_ACTIM3_TR2MRR, 0x8, + SHU_ACTIM3_TRFC, 0x40, + SHU_ACTIM3_TWTR_L, 0x25); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x04e, + SHU_ACTIM4_TMRR2MRW, 0x0f, + SHU_ACTIM4_TMRR2W, 0x0c, + SHU_ACTIM4_TZQCS, 0x10); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x10, + SHU_ACTIM5_TWTPD, 0x0f, + SHU_ACTIM5_TPBR2PBR, 0x15, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x06, + SHU_ACTIM6_TMRD, 0x6, + SHU_ACTIM6_TMRW, 0x5, + SHU_ACTIM6_TW2MRW, 0x0d, + SHU_ACTIM6_TR2MRW, 0x11); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x0, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x3, + SHU_CKECTRL_TPDX, 0x3, + SHU_CKECTRL_TCKEPRD, 0x2, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0031, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0031, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x7, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x7, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17e, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17e); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17d, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17e, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17e); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17d, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x03, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x03, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x35, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x35); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x03, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x03, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x35, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x35); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static void sv_algorithm_assistance_lp4_1600(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x09, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfeb, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x015); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x09, + MISC_SHU_RDAT_DATLAT_DSEL, 0x09, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x0, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x1, + MISC_SHU_RANKCTL_RANKINCTL, 0x0, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x0, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x3); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0xc, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0xc, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x1, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x7, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x7, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x7, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x7, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x11, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x11, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x09, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x0d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x09, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x0d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x11, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x0c, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x11, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x0c, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x19, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x19, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x1f, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x1f, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x1, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x0, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x0, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x0, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x2, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x2, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, 0x1, + SHU_SELPH_DQS1_DLY_DQS1, 0x1, + SHU_SELPH_DQS1_DLY_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_DQS3, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x1, + SHURK_SELPH_DQ2_DLY_DQ1, 0x1, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x6, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x6, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x1, + SHURK_SELPH_DQ3_DLY_DQM1, 0x1, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x6, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x6, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x019, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x01f); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x019, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x01f); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x019, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x01f); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x1f, + SHURK_PI_RK0_ARPI_DQ_B0, 0x19, + SHURK_PI_RK0_ARPI_DQM_B1, 0x1f, + SHURK_PI_RK0_ARPI_DQM_B0, 0x19); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x12, + SHURK_PI_RK0_ARPI_DQ_B0, 0x13, + SHURK_PI_RK0_ARPI_DQM_B1, 0x12, + SHURK_PI_RK0_ARPI_DQM_B0, 0x13); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x3c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x3c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x0, + SHU_AC_DERATING0_TRRD_DERATE, 0x1, + SHU_AC_DERATING0_TRCD_DERATE, 0x4); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0x3, + SHU_AC_DERATING1_TRP_DERATE, 0x2, + SHU_AC_DERATING1_TRAS_DERATE, 0x00, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRC_05T, 0x0, + SHU_AC_TIME_05T_TRFCPB_05T, 0x0, + SHU_AC_TIME_05T_TRFC_05T, 0x0, + SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, + SHU_AC_TIME_05T_TXP_05T, 0x0, + SHU_AC_TIME_05T_TRTP_05T, 0x1, + SHU_AC_TIME_05T_TRCD_05T, 0x0, + SHU_AC_TIME_05T_TRP_05T, 0x1, + SHU_AC_TIME_05T_TRPAB_05T, 0x0, + SHU_AC_TIME_05T_TRAS_05T, 0x0, + SHU_AC_TIME_05T_TWR_M05T, 0x1, + SHU_AC_TIME_05T_TRRD_05T, 0x0, + SHU_AC_TIME_05T_TFAW_05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, + SHU_AC_TIME_05T_TR2PD_05T, 0x0, + SHU_AC_TIME_05T_TWTPD_M05T, 0x1, + SHU_AC_TIME_05T_TMRRI_05T, 0x1, + SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0, + SHU_AC_TIME_05T_BGTRRD_05T, 0x0, + SHU_AC_TIME_05T_BGTCCD_05T, 0x0, + SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2W_05T, 0x0, + SHU_AC_TIME_05T_TWTR_M05T, 0x1, + SHU_AC_TIME_05T_XRTR2W_05T, 0x0, + SHU_AC_TIME_05T_TMRD_05T, 0x1, + SHU_AC_TIME_05T_TMRW_05T, 0x1, + SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1, + SHU_AC_TIME_05T_TW2MRW_05T, 0x1, + SHU_AC_TIME_05T_TR2MRW_05T, 0x0, + SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1, + SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x03, + SHU_ACTIM_XRT_XRTR2W, 0x03, + SHU_ACTIM_XRT_XRTW2R, 0x3, + SHU_ACTIM_XRT_XRTW2W, 0x04); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x04, + SHU_ACTIM0_TWR, 0x07, + SHU_ACTIM0_TRRD, 0x1, + SHU_ACTIM0_TRCD, 0x4, + SHU_ACTIM0_CKELCKCNT, 0x2); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0x3, + SHU_ACTIM1_TMRWCKEL, 0x4, + SHU_ACTIM1_TRP, 0x2, + SHU_ACTIM1_TRAS, 0x00, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x0, + SHU_ACTIM2_TMRRI, 0x05, + SHU_ACTIM2_TRTP, 0x0, + SHU_ACTIM2_TR2W, 0x03, + SHU_ACTIM2_TFAW, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x1a, + SHU_ACTIM3_MANTMRR, 0x4, + SHU_ACTIM3_TR2MRR, 0x4, + SHU_ACTIM3_TRFC, 0x40, + SHU_ACTIM3_TWTR_L, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x04e, + SHU_ACTIM4_TMRR2MRW, 0x07, + SHU_ACTIM4_TMRR2W, 0x05, + SHU_ACTIM4_TZQCS, 0x10); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x08, + SHU_ACTIM5_TWTPD, 0x09, + SHU_ACTIM5_TPBR2PBR, 0x0b, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x06, + SHU_ACTIM6_TMRD, 0x3, + SHU_ACTIM6_TMRW, 0x2, + SHU_ACTIM6_TW2MRW, 0x06, + SHU_ACTIM6_TR2MRW, 0x09); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x1, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x1, + SHU_CKECTRL_TPDX, 0x1, + SHU_CKECTRL_TCKEPRD, 0x1, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0063, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0063, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x5, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x5, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0da, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0da); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0d9, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0d9); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0da, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0da); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0d9, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0d9); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x6e, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x6e, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x24, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x24); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x6e, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x6e, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x24, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x24); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static void sv_algorithm_assistance_lp4_3733(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0f, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfd0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x030); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x0f, + MISC_SHU_RDAT_DATLAT_DSEL, 0x0f, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6, + MISC_SHU_RANKCTL_RANKINCTL, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x4, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xb, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x4, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xb, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1c); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x7, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x3, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x3, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x3, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x3, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0f, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0f, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1c, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x17); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1c, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x17); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0f, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x10, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x14); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0f, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x10, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x14); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1c, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x17, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1c, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x17, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1b); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x11, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x11, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x16, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x16, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x21, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x21, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x2, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x3, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x3, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, 0x1, + SHU_SELPH_DQS1_DLY_DQS1, 0x1, + SHU_SELPH_DQS1_DLY_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_DQS3, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x3, + SHURK_SELPH_DQ2_DLY_DQ1, 0x3, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x0, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x0, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x3, + SHURK_SELPH_DQ3_DLY_DQM1, 0x3, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x0, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x0, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x011, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x011, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x011, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x016, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x021); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x016, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x021); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x016, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x021); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x12, + SHURK_PI_RK0_ARPI_DQ_B0, 0x11, + SHURK_PI_RK0_ARPI_DQM_B1, 0x12, + SHURK_PI_RK0_ARPI_DQM_B0, 0x11); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x21, + SHURK_PI_RK0_ARPI_DQ_B0, 0x16, + SHURK_PI_RK0_ARPI_DQM_B1, 0x21, + SHURK_PI_RK0_ARPI_DQM_B0, 0x16); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x34, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x34, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x34, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x34); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x34, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x34, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x34, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x34); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x34, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x2, + SHU_TX_RANKCTL_TXRANKINCTL, 0x2, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x0, + SHU_AC_DERATING0_TRRD_DERATE, 0x5, + SHU_AC_DERATING0_TRCD_DERATE, 0x9); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0x9, + SHU_AC_DERATING1_TRP_DERATE, 0x8, + SHU_AC_DERATING1_TRAS_DERATE, 0x0c, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x75, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRC_05T, 0x0, + SHU_AC_TIME_05T_TRFCPB_05T, 0x0, + SHU_AC_TIME_05T_TRFC_05T, 0x1, + SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, + SHU_AC_TIME_05T_TXP_05T, 0x1, + SHU_AC_TIME_05T_TRTP_05T, 0x0, + SHU_AC_TIME_05T_TRCD_05T, 0x1, + SHU_AC_TIME_05T_TRP_05T, 0x0, + SHU_AC_TIME_05T_TRPAB_05T, 0x1, + SHU_AC_TIME_05T_TRAS_05T, 0x1, + SHU_AC_TIME_05T_TWR_M05T, 0x1, + SHU_AC_TIME_05T_TRRD_05T, 0x0, + SHU_AC_TIME_05T_TFAW_05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, + SHU_AC_TIME_05T_TR2PD_05T, 0x0, + SHU_AC_TIME_05T_TWTPD_M05T, 0x1, + SHU_AC_TIME_05T_TMRRI_05T, 0x0, + SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0, + SHU_AC_TIME_05T_BGTRRD_05T, 0x0, + SHU_AC_TIME_05T_BGTCCD_05T, 0x0, + SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2W_05T, 0x0, + SHU_AC_TIME_05T_TWTR_M05T, 0x0, + SHU_AC_TIME_05T_XRTR2W_05T, 0x0, + SHU_AC_TIME_05T_TMRD_05T, 0x1, + SHU_AC_TIME_05T_TMRW_05T, 0x0, + SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1, + SHU_AC_TIME_05T_TW2MRW_05T, 0x0, + SHU_AC_TIME_05T_TR2MRW_05T, 0x1, + SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1, + SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x03, + SHU_ACTIM_XRT_XRTR2W, 0x08, + SHU_ACTIM_XRT_XRTW2R, 0x1, + SHU_ACTIM_XRT_XRTW2W, 0x05); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x08, + SHU_ACTIM0_TWR, 0x0d, + SHU_ACTIM0_TRRD, 0x4, + SHU_ACTIM0_TRCD, 0x8, + SHU_ACTIM0_CKELCKCNT, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0x8, + SHU_ACTIM1_TMRWCKEL, 0x8, + SHU_ACTIM1_TRP, 0x7, + SHU_ACTIM1_TRAS, 0x0b, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x0, + SHU_ACTIM2_TMRRI, 0x0c, + SHU_ACTIM2_TRTP, 0x2, + SHU_ACTIM2_TR2W, 0x09, + SHU_ACTIM2_TFAW, 0x0b); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x4d, + SHU_ACTIM3_MANTMRR, 0x4, + SHU_ACTIM3_TR2MRR, 0x4, + SHU_ACTIM3_TRFC, 0xa5, + SHU_ACTIM3_TWTR_L, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x0b5, + SHU_ACTIM4_TMRR2MRW, 0x0d, + SHU_ACTIM4_TMRR2W, 0x0c, + SHU_ACTIM4_TZQCS, 0x28); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x0e, + SHU_ACTIM5_TWTPD, 0x10, + SHU_ACTIM5_TPBR2PBR, 0x23, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x0e, + SHU_ACTIM6_TMRD, 0x7, + SHU_ACTIM6_TMRW, 0x5, + SHU_ACTIM6_TW2MRW, 0x0a, + SHU_ACTIM6_TR2MRW, 0x10); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x1, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x1, + SHU_CKECTRL_TPDX, 0x1, + SHU_CKECTRL_TCKEPRD, 0x3, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x00e7, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x00e7, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x4, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x4, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x061, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x061); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x060, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x060); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x061, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x061); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x060, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x060); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x75, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x75, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x2d, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x2d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x75, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x75, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x2d, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x2d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static void sv_algorithm_assistance_lp4_4266(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x10, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfcb, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x035); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x10, + MISC_SHU_RDAT_DATLAT_DSEL, 0x0f, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6, + MISC_SHU_RANKCTL_RANKINCTL, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x5, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x01); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x5, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x01); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x7, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x2, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x2, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x01, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x01, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x08, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x19); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x08, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x19); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x01, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x11, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x15); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x01, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x11, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x15); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x08, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x19, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x08, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x19, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x16, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x16, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x2b, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x2b, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x01, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x2b, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x2b, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x01, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, 0x5, + SHU_SELPH_DQS1_DLY_DQS1, 0x5, + SHU_SELPH_DQS1_DLY_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_DQS3, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x2, + SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x2, + SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x6, + SHURK_SELPH_DQ2_DLY_DQ1, 0x6, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x6, + SHURK_SELPH_DQ3_DLY_DQM1, 0x6, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x7, + SHURK_SELPH_DQ2_DLY_DQ1, 0x7, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x7, + SHURK_SELPH_DQ3_DLY_DQM1, 0x7, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x016); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x016); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x016); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x02b, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x02b); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x02b, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x02b); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x02b, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x02b); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x16, + SHURK_PI_RK0_ARPI_DQ_B0, 0x13, + SHURK_PI_RK0_ARPI_DQM_B1, 0x16, + SHURK_PI_RK0_ARPI_DQM_B0, 0x13); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x2b, + SHURK_PI_RK0_ARPI_DQ_B0, 0x2b, + SHURK_PI_RK0_ARPI_DQM_B1, 0x2b, + SHURK_PI_RK0_ARPI_DQM_B0, 0x2b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x0, + SHU_AC_DERATING0_TRRD_DERATE, 0x5, + SHU_AC_DERATING0_TRCD_DERATE, 0xb); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0xb, + SHU_AC_DERATING1_TRP_DERATE, 0x9, + SHU_AC_DERATING1_TRAS_DERATE, 0x0f, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x86, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRC_05T, 0x0, + SHU_AC_TIME_05T_TRFCPB_05T, 0x1, + SHU_AC_TIME_05T_TRFC_05T, 0x0, + SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, + SHU_AC_TIME_05T_TXP_05T, 0x0, + SHU_AC_TIME_05T_TRTP_05T, 0x1, + SHU_AC_TIME_05T_TRCD_05T, 0x0, + SHU_AC_TIME_05T_TRP_05T, 0x1, + SHU_AC_TIME_05T_TRPAB_05T, 0x0, + SHU_AC_TIME_05T_TRAS_05T, 0x0, + SHU_AC_TIME_05T_TWR_M05T, 0x0, + SHU_AC_TIME_05T_TRRD_05T, 0x0, + SHU_AC_TIME_05T_TFAW_05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, + SHU_AC_TIME_05T_TR2PD_05T, 0x1, + SHU_AC_TIME_05T_TWTPD_M05T, 0x0, + SHU_AC_TIME_05T_TMRRI_05T, 0x0, + SHU_AC_TIME_05T_TMRWCKEL_05T, 0x1, + SHU_AC_TIME_05T_BGTRRD_05T, 0x0, + SHU_AC_TIME_05T_BGTCCD_05T, 0x0, + SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2W_05T, 0x0, + SHU_AC_TIME_05T_TWTR_M05T, 0x1, + SHU_AC_TIME_05T_XRTR2W_05T, 0x0, + SHU_AC_TIME_05T_TMRD_05T, 0x0, + SHU_AC_TIME_05T_TMRW_05T, 0x1, + SHU_AC_TIME_05T_TMRR2MRW_05T, 0x0, + SHU_AC_TIME_05T_TW2MRW_05T, 0x0, + SHU_AC_TIME_05T_TR2MRW_05T, 0x0, + SHU_AC_TIME_05T_TPBR2ACT_05T, 0x0, + SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x03, + SHU_ACTIM_XRT_XRTR2W, 0x08, + SHU_ACTIM_XRT_XRTW2R, 0x1, + SHU_ACTIM_XRT_XRTW2W, 0x05); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x0a, + SHU_ACTIM0_TWR, 0x0f, + SHU_ACTIM0_TRRD, 0x3, + SHU_ACTIM0_TRCD, 0xa, + SHU_ACTIM0_CKELCKCNT, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0xa, + SHU_ACTIM1_TMRWCKEL, 0x8, + SHU_ACTIM1_TRP, 0x8, + SHU_ACTIM1_TRAS, 0x0e, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x1, + SHU_ACTIM2_TMRRI, 0x0e, + SHU_ACTIM2_TRTP, 0x2, + SHU_ACTIM2_TR2W, 0x09, + SHU_ACTIM2_TFAW, 0x08); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x59, + SHU_ACTIM3_MANTMRR, 0x4, + SHU_ACTIM3_TR2MRR, 0x4, + SHU_ACTIM3_TRFC, 0xbf, + SHU_ACTIM3_TWTR_L, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x0cf, + SHU_ACTIM4_TMRR2MRW, 0x0f, + SHU_ACTIM4_TMRR2W, 0x0b, + SHU_ACTIM4_TZQCS, 0x2e); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x0f, + SHU_ACTIM5_TWTPD, 0x12, + SHU_ACTIM5_TPBR2PBR, 0x29, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x10, + SHU_ACTIM6_TMRD, 0x8, + SHU_ACTIM6_TMRW, 0x5, + SHU_ACTIM6_TW2MRW, 0x0b, + SHU_ACTIM6_TR2MRW, 0x12); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x1, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x1, + SHU_CKECTRL_TPDX, 0x1, + SHU_CKECTRL_TCKEPRD, 0x3, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0100, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0100, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x3, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x3, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x04a, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x04a); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x038, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x038); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0bd, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0bd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0f4, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0f4); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x5a, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x5a, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x14, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x14); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x53, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x53, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x0d, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x0d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static u32 get_write_latency_by_mr(u8 mr_wl) +{ + u32 write_latency; + + switch (mr_wl) { + case 0: + write_latency = 4; + break; + case 1: + write_latency = 6; + break; + case 2: + write_latency = 8; + break; + case 3: + write_latency = 10; + break; + case 4: + write_latency = 12; + break; + case 5: + write_latency = 14; + break; + case 6: + write_latency = 16; + break; + case 7: + write_latency = 18; + break; + default: + dramc_err("error: unexpected mr_wl: %x\n", mr_wl); + return 0; + } + + dramc_info("mr_wl: %x map to WriteLatency: %d\n", mr_wl, write_latency); + return write_latency; +} + +static void tx_path_algorithm(const struct ddr_cali *cali) +{ + u8 write_latency, wl_mr; + const u8 ckr = 1; + u8 dqs_total_ui; + u8 dqs_oe_total_ui; + u8 dqs_mck, dqs_ui; + u8 dqs_oe_mck, dqs_oe_ui; + u8 shift; + const u8 tx_dq_oe_shift = 3; + + wl_mr = (cali->mr_value->mr02[get_fsp(cali)] & 0x3f) >> 3; + shift = get_mck2ui_div_shift(cali); + write_latency = get_write_latency_by_mr(wl_mr); + dqs_total_ui = write_latency * ckr * 2 + 1; + + dqs_oe_total_ui = dqs_total_ui - tx_dq_oe_shift; + dqs_ui = dqs_total_ui - ((dqs_total_ui >> shift) << shift); + dqs_mck = dqs_total_ui >> shift; + dqs_oe_ui = dqs_oe_total_ui - ((dqs_oe_total_ui >> shift) << shift); + dqs_oe_mck = dqs_oe_total_ui >> shift; + dramc_dbg("[TX_path_calculate] write_latency=%u, DQS_TotalUI=%u\n", + write_latency, dqs_total_ui); + dramc_dbg("[TX_path_calculate] DQS = (%u,%u) DQS_OE = (%u,%u)\n", + dqs_mck, dqs_ui, dqs_oe_mck, dqs_oe_ui); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, dqs_mck, + SHU_SELPH_DQS0_TXDLY_DQS1, dqs_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, dqs_oe_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, dqs_oe_mck); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, dqs_ui, + SHU_SELPH_DQS1_DLY_DQS1, dqs_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS0, dqs_oe_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS1, dqs_oe_ui); + } +} + +static void replace_dv_init(const struct ddr_cali *cali) +{ + bool is_4266; + u8 dq_hyst_sel, ca_hyst_sel; + u8 dq_cap_sel, ca_cap_sel; + u8 dq_bw_sel_b0 = 0, dq_bw_sel_b1 = 0, ca_bw_sel_ca = 0, clk_bw_sel_ca = 0; + + dram_freq_grp freq_group = cali->freq_group; + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs0, + B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 0, + B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs0, + B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 0, + B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 0); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rk].rk_b0_rxdvs2, + RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 0, + RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 0, + RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rk].rk_b0_rxdvs2, + RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 0, + RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 0, + RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 0); + } + + SET32_BITFIELDS(&ch[0].ao.cbt_wlev_ctrl1, CBT_WLEV_CTRL1_CATRAINLAT, 0); + SET32_BITFIELDS(&ch[0].ao.swcmd_ctrl1, SWCMD_CTRL1_WRFIFO_MODE2, 0); + + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + switch (freq_group) { + case DDRFREQ_400: + case DDRFREQ_600: + case DDRFREQ_800: + case DDRFREQ_933: + dq_cap_sel = 0x18; + ca_cap_sel = 0x18; + break; + case DDRFREQ_1200: + dq_cap_sel = 0x14; + ca_cap_sel = 0x14; + break; + case DDRFREQ_1600: + dq_cap_sel = 0x4; + ca_cap_sel = 0x4; + break; + case DDRFREQ_2133: + dq_cap_sel = 0x2; + ca_cap_sel = 0x2; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + if (freq_group <= DDRFREQ_933) { + dq_hyst_sel = 0x1; + ca_hyst_sel = 0x1; + } else { + dq_hyst_sel = 0x0; + ca_hyst_sel = 0x0; + } + + if (freq_group <= DDRFREQ_1200) + clk_bw_sel_ca = 1; + + is_4266 = freq_group >= DDRFREQ_2133; + if (is_4266) { + dq_bw_sel_b0 = 1; + dq_bw_sel_b1 = 1; + ca_bw_sel_ca = 1; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq6, + SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, dq_hyst_sel, + SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, dq_cap_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq6, + SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, dq_hyst_sel, + SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, dq_cap_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, ca_hyst_sel, + SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, ca_cap_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, is_4266, + SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, is_4266, + SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 0, + SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, is_4266, + SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, is_4266, + SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 0, + SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd2, + SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, is_4266, + SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, is_4266, + SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 0, + SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x0); + write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl1, 0x0); + write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl4, 0x0); + write32(&ch[chn].phy_ao.misc_dbg_irq_ctrl7, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2, + MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_MR4INT_LIMITEN, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPEND_OPT1, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en, + DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff, + DRAMC_IRQ_EN_MR4INT_EN, 0x0); + SET32_BITFIELDS(&ch[chn].ao.shu_conf0, SHU_CONF0_PBREFEN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_tx_mck, + CA_TX_MCK_R_DMRESET_FRPHY_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPBINARY, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 0x1, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 0x1, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dll2, + SHU_B0_DLL2_RG_ARDQ_REV_B0, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dll2, + SHU_B1_DLL2_RG_ARDQ_REV_B1, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll2, + SHU_CA_DLL2_RG_ARCMD_REV, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, DUMMY_RD_DQSG_DMYRD_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_dbg_sel1, + DRAMC_DBG_SEL1_DEBUG_SEL_0, 0x1e); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl2, SWCMD_CTRL2_RTSWCMD_AGE, 0x20); + SET32_BITFIELDS(&ch[chn].ao.rtmrw_ctrl0, RTMRW_CTRL0_RTMRW_AGE, 0x20); + SET32_BITFIELDS(&ch[chn].ao.dllfrz_ctrl, + DLLFRZ_CTRL_DLLFRZ, 0, + DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.mpc_ctrl, + MPC_CTRL_RTSWCMD_HPRI_EN, 1, + MPC_CTRL_RTMRW_HPRI_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.hw_mrr_fun, + HW_MRR_FUN_R2MRRHPRICTL, 0, + HW_MRR_FUN_TR2MRR_ENA, 0); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_REFNA_OPT, 1, + ACTIMING_CTRL_SEQCLKRUN3, 1); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, CKECTRL_RUNTIMEMRRCKEFIX, 1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_SYNC_MASK, 0, + DVFS_CTRL0_R_DVFS_SREF_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_timing_ctrl1, + DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 1); + SET32_BITFIELDS(&ch[chn].ao.hmr4, + HMR4_REFRCNT_OPT, 1, + HMR4_REFR_PERIOD_OPT, 0, + HMR4_SPDR_MR4_OPT, 1, + HMR4_HMR4_TOG_OPT, 0); + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_SMRR_UPD_OLD, 0); + SET32_BITFIELDS(&ch[chn].ao.dramctrl, DRAMCTRL_SHORTQ_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.misctl0, + MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1); + SET32_BITFIELDS(&ch[chn].ao.perfctl0, PERFCTL0_EBG_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.clkar, + CLKAR_REQQUECLKRUN, 1, + CLKAR_REQQUE_PACG_DIS, 0x7fff); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, + REFCTRL0_PBREF_BK_REFA_ENA, 0, + REFCTRL0_PBREF_BK_REFA_NUM, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPB2AB_IGZQCS, 0); + SET32_BITFIELDS(&ch[chn].ao.refctrl1, REFCTRL1_REFPENDINGINT_OPT1, 1); + SET32_BITFIELDS(&ch[chn].ao.ref_bounce1, + REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 5); + SET32_BITFIELDS(&ch[chn].ao.refpend2, REFPEND2_MPENDREFCNT_TH8, 8); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl, SCSMCTRL_SC_PG_MAN_DIS, 0); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, + SCSMCTRL_CG_SCSM_CGAR, 1, + SCSMCTRL_CG_SCARB_SM_CGAR, 1); + SET32_BITFIELDS(&ch[chn].ao.rtswcmd_cnt, + RTSWCMD_CNT_RTSWCMD_CNT, 0x30); + SET32_BITFIELDS(&ch[chn].ao.dramc_irq_en, + DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 0x3fff); + SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 1); + SET32_BITFIELDS(&ch[chn].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x1ff, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 11); + SET32_BITFIELDS(&ch[chn].ao.shu_misc, SHU_MISC_REQQUE_MAXCNT, 2); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi4, + B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 1, + B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi4, + B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 1, + B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi4, + CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 1, + CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd11, + CA_CMD11_RG_RRESETB_DRVN, 0xa, + CA_CMD11_RG_RRESETB_DRVP, 0xa); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x1f); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl9, + MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 0, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 0, + MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 0, + MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 0, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 0, + MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 0, + MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 0, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 0, + MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 0, + MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 1, + MISC_DVFSCTL2_RG_DLL_SHUFFLE, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0x10, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 1, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 3, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 1, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ddr_reserve, + MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 0xf); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 1, + MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 1, + MISC_IMPCAL_IMPCAL_DRVUPDOPT, 1, + MISC_IMPCAL_IMPBINARY, 1, + MISC_IMPCAL_DQDRVSWUPD, 1, + MISC_IMPCAL_DRVCGWREF, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfs_emi_clk, + MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, + MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 0, + MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 1, + MISC_CTRL0_IMPCAL_LP_ECO_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_CG_CS, 0, + MISC_CTRL4_R_OPT2_CG_CLK, 0, + MISC_CTRL4_R_OPT2_CG_CMD, 0, + MISC_CTRL4_R_OPT2_CG_DQSIEN, 0, + MISC_CTRL4_R_OPT2_CG_DQ, 0, + MISC_CTRL4_R_OPT2_CG_DQS, 0, + MISC_CTRL4_R_OPT2_CG_DQM, 0, + MISC_CTRL4_R_OPT2_CG_MCK, 0, + MISC_CTRL4_R_OPT2_MPDIV_CG, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl6, + MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1, + MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, + MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 1, + SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 1, + SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 1, + SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 1, + SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 1, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 1, + SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 1, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 1, + SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, dq_bw_sel_b0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, dq_bw_sel_b1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, ca_bw_sel_ca); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd10, + SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, clk_bw_sel_ca); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 1, + SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd8, + SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 1, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 1, + SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 1, + SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_REV, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 2, + MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0, + MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0); + } + + dramc_set_broadcast(bc_bak); +} + +static void rx_picg_setting(const struct ddr_cali *cali) +{ + u8 talk_lat = (get_div_mode(cali) == DIV4_MODE) ? 1 : 0; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_STBCNT_SHU_RST_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, + MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 0); + for (u8 rk = 0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[rk].misc_shu_rk_dqsien_picg_ctrl, + MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, talk_lat, + MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, + MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 0, + MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 0, + MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 0, + MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 0, + MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 0); +} + +static void dqs_stb_settings(void) +{ + u32 dqsien_mode = 1; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, dqsien_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode); +} + +static void rodt_settings(const struct ddr_cali *cali) +{ + u8 vref_sel; + u8 odt_onoff = get_odt_state(cali); + if (get_odt_state(cali) == ODT_ON) + vref_sel = 0x2c; + else + vref_sel = 0x37; + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref, + SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref, + SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, !odt_onoff); + + for (u8 rk = 0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B0, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B0, vref_sel); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B1, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B1, vref_sel); + } + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_vref, + SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_vref, + SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, MISC_SHU_ODTCTRL_RODTEN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, SHU_B0_DQ7_R_DMRODTEN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, SHU_B1_DQ7_R_DMRODTEN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb, + MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 1, + MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 1, + MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, !odt_onoff); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 0); +} + +void dramc_cmd_ui_delay_setting(u8 chn, u8 value) +{ + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca7, + SHU_SELPH_CA7_DLY_RA0, value, + SHU_SELPH_CA7_DLY_RA1, value, + SHU_SELPH_CA7_DLY_RA2, value, + SHU_SELPH_CA7_DLY_RA3, value, + SHU_SELPH_CA7_DLY_RA4, value, + SHU_SELPH_CA7_DLY_RA5, value, + SHU_SELPH_CA7_DLY_RA6, value); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CKE, value); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, SHU_SELPH_CA6_DLY_CKE1, value); +} + +void cbt_delay_ca_clk(u8 chn, u8 rank, s32 delay) +{ + if (delay < 0) + /* Set CLK delay */ + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0, + SHU_R0_CA_CMD0_RG_ARPI_CLK, -delay, + SHU_R0_CA_CMD0_RG_ARPI_CS, -delay); + else + /* Set CA output delay */ + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_ARPI_CMD, delay, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0); +} + +static void set_mck_8x_low_pwr_option(void) +{ + const u32 mck_8x_mode = 1; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, mck_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, mck_8x_mode); +} + +static void update_initial_settings(const struct ddr_cali *cali) +{ + const u8 ca_pi = 0, ca_ui = 1; + u8 fsp = get_fsp(cali); + dram_freq_grp freq_group = get_freq_group(cali); + u8 buf_en_head; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl3, MISC_CTRL3_ARPI_CG_CLK_OPT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, MISC_CTRL4_R_OPT2_CG_CLK, 0); + + replace_dv_init(cali); + + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, + SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 0xc0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0); + + rx_picg_setting(cali); + dramc_sw_impedance_save_register(cali); + dqs_stb_settings(); + rodt_settings(cali); + SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); + + dramc_cmd_ui_delay_setting(CHANNEL_A, ca_ui); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca5, + SHU_SELPH_CA5_DLY_CS, 0x1, + SHU_SELPH_CA5_DLY_CS1, 0x1); + + for (u8 rk = 0; rk < cali->support_ranks; rk++) + cbt_delay_ca_clk(CHANNEL_A, rk, ca_pi); + + SET32_BITFIELDS(&ch[0].ao.refctrl1, REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 0x1); + SET32_BITFIELDS(&ch[0].ao.misctl0, MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0x1); + SET32_BITFIELDS(&ch[0].ao.scheduler_com, SCHEDULER_COM_PBR2PBR_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, SHU_TX_SET0_WPST1P5T, fsp); + SET32_BITFIELDS(&ch[0].ao.dummy_rd, + DUMMY_RD_DMYRD_REORDER_DIS, 0x1, + DUMMY_RD_SREF_DMYRD_EN, 0x1); + SET32_BITFIELDS(&ch[0].ao.dramctrl, + DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 0x0, + DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 0x1, + DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, MISC_STBCAL2_DQSGCNT_BYP_REF, 1); + + if (freq_group <= DDRFREQ_800) + buf_en_head = 0; + else if (freq_group <= DDRFREQ_1200) + buf_en_head = 1; + else + buf_en_head = 2; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, buf_en_head); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_tx_mck, + CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 0xa, + CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 0xa); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x3, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x3, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x3); + set_mck_8x_low_pwr_option(); +} + +static void dramc_setting(const struct ddr_cali *cali) +{ + dram_freq_grp freq_group = cali->freq_group; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + switch (freq_group) { + case DDRFREQ_400: + sv_algorithm_assistance_lp4_800(); + break; + case DDRFREQ_600: + case DDRFREQ_800: + case DDRFREQ_933: + case DDRFREQ_1200: + sv_algorithm_assistance_lp4_1600(); + break; + case DDRFREQ_1600: + sv_algorithm_assistance_lp4_3733(); + break; + case DDRFREQ_2133: + sv_algorithm_assistance_lp4_4266(); + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + update_initial_settings(cali); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); +} + +void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option) +{ + u8 cke_on = 0, cke_off = 0; + bool set_rank1 = (rank == RANK_MAX) && (cali->support_ranks == DUAL_RANK_DDR); + + if (option != CKE_DYNAMIC) { + cke_on = option; + cke_off = 1 - option; + } + + if (rank == RANK_0 || rank == RANK_MAX) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXOFF, cke_off, + CKECTRL_CKEFIXON, cke_on); + } + if (rank == RANK_1 || set_rank1) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE1FIXOFF, cke_off, + CKECTRL_CKE1FIXON, cke_on); + } +} + +static void dramc_power_on_sequence(const struct ddr_cali *cali) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDA_RRESETB_I, 0x0); + cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXOFF); + udelay(200); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDA_RRESETB_I, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_TCKFIXON, 1); + mdelay(2); + cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXON); + udelay(2); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_TCKFIXON, 0); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0); + } +} + +static void dramc_zq_calibration(const struct ddr_cali *cali, u8 chn, u8 rank) +{ + const u32 timeout = 100; + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.swcmd_en}, + {&ch[chn].ao.swcmd_ctrl0}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, + }; + + for (int i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_TCKFIXON, 1); + udelay(1); + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_SWTRIG_ZQ_RK, rank); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 1); + if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, + SPCMDRESP3_ZQC_SWTRIG_RESPONSE))) { + dramc_err("ZQCAL Start failed (time out)\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQCEN_SWTRIG, 0); + + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 1); + if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, + SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE))) { + dramc_err("ZQCAL Latch failed (time out)\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_ZQLATEN_SWTRIG, 0); + + udelay(1); + for (int i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); +} + +u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + const u32 timeout = 10000; + u8 value; + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); + + /* Wait until MRW command fired */ + if (!wait_ms(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp, + SPCMDRESP_MRR_RESPONSE))) { + dramc_err("Read mode register time out\n"); + return -1; + } + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); + dramc_dbg("Read MR%d = %#x\n", mr_idx, value); + + return value; +} + +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u8 rank_bak; + + rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); + + return value; +} + +void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, + u8 chn, u8 rank, u8 mr_idx, u8 value) +{ + u32 bk_bak, ckectrl_bak; + dramc_info("MRW CH%d RK%d MR%d = %#x\n", chn, rank, mr_idx, value); + + bk_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + ckectrl_bak = read32(&ch[chn].ao.ckectrl); + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSOP, value); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 1); + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) == 0) + udelay(1); + + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRWEN, 0); + write32(&ch[chn].ao.ckectrl, ckectrl_bak); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, bk_bak); +} + +void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq) +{ + static u8 _cur_freq = CBT_UNKNOWN_FREQ; + + /* if frequency is the same as before, do nothing */ + if (_cur_freq == freq) + return; + _cur_freq = freq; + + enable_dfs_hw_mode_clk(); + + if (freq == CBT_LOW_FREQ) + dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU1); + else + dramc_dfs_direct_jump_rg_mode(cali, DRAM_DFS_SHU0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); +} + +static void dramc_mode_reg_init(const struct ddr_cali *cali) +{ + u8 chn; + u8 set_mrsrk; + u8 operate_fsp = get_fsp(cali); + struct mr_values *mr_value = cali->mr_value; + + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_power_on_sequence(cali); + + if (get_fsp(cali) == FSP_1) { + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + cbt_switch_freq(cali, CBT_LOW_FREQ); + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + } + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (u8 rk = 0; rk < cali->support_ranks; rk++) { + dramc_dbg("ModeRegInit CH%u RK%u\n", chn, rk); + for (u8 fsp = FSP_0; fsp < FSP_MAX; fsp++) { + if (fsp == FSP_0) { + dramc_dbg("FSP0\n"); + mr_value->mr13[rk] = BIT(4) | BIT(3); + mr_value->mr22[fsp] = 0x38; + mr_value->mr11[fsp] = 0x0; + } else { + dramc_dbg("FSP1\n"); + mr_value->mr13[rk] |= 0x40; + + if (cali->cbt_mode[rk] == CBT_NORMAL_MODE) + mr_value->mr11[fsp] = 0x3 | 0x40; + else + mr_value->mr11[fsp] = 0x3 | 0x20; + + if (rk == RANK_0) + mr_value->mr22[fsp] = 0x4; + else + mr_value->mr22[fsp] = 0x2c; + } + + dramc_mode_reg_write_by_rank(cali, chn, rk, 13, + mr_value->mr13[rk]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 12, + mr_value->mr12[chn][rk][fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 1, + mr_value->mr01[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 2, + mr_value->mr02[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 11, + mr_value->mr11[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 21, + mr_value->mr21[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 51, + mr_value->mr51[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 22, + mr_value->mr22[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 14, + mr_value->mr14[chn][rk][fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 3, + mr_value->mr03[fsp]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 4, + mr_value->mr04[rk]); + dramc_mode_reg_write_by_rank(cali, chn, rk, 3, + mr_value->mr03[fsp]); + } + + dramc_zq_calibration(cali, chn, rk); + + if (operate_fsp == FSP_0) + mr_value->mr13[rk] &= 0x3f; + else + mr_value->mr13[rk] |= 0xc0; + } + + if (cali->support_ranks == DUAL_RANK_DDR) + set_mrsrk = 0x3; + else + set_mrsrk = RANK_0; + + dramc_mode_reg_write_by_rank(cali, chn, set_mrsrk, 13, mr_value->mr13[RANK_0]); + + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, mr_value->mr13[RANK_0] | BIT(3), + SHU_HWSET_MR13_HWSET_MR13_MRSMA, 13); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_HWSET_VRCG_OP, mr_value->mr13[RANK_0] | BIT(3), + SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 13); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, mr_value->mr02[operate_fsp], + SHU_HWSET_MR2_HWSET_MR2_MRSMA, 2); + } + + if (operate_fsp == FSP_1) { + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + cbt_switch_freq(cali, CBT_HIGH_FREQ); + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + } + + for (chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, RANK_0); + + dramc_set_broadcast(bc_bak); +} + +static void ddr_update_ac_timing(const struct ddr_cali *cali) +{ + u8 table_idx; + const struct ac_timing *ac_tim; + const dram_freq_grp freq_group = cali->freq_group; + + u8 rank_inctl, tx_dly, datlat_dsel; + const u8 root = 0; + u8 tx_rank_inctl; + const u8 tref_bw = 0; + u8 tfaw_05t, trrd_05t; + u16 xrtwtw, xtrtrt, xrtw2r, xrtr2w, tfaw; + u16 trtw, trtw_05t, tmrr2w, trrd; + u16 phs_inctl; + u32 rank_inctl_root; + + for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++) + if (ac_timing_tbl[table_idx].freq_group == freq_group && + ac_timing_tbl[table_idx].div_mode == get_div_mode(cali) && + ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali)) { + dramc_dbg("Found matched AC timing table %u\n", table_idx); + break; + } + + if (table_idx == AC_TIMING_NUMBER) { + dramc_err("Error: no matched AC timing table found\n"); + return; + } + + ac_tim = &ac_timing_tbl[table_idx]; + + trtw = ac_tim->trtw_odt_on; + trtw_05t = ac_tim->trtw_odt_on_05T; + xrtw2r = ac_tim->xrtw2r_odt_on; + xrtr2w = ac_tim->xrtr2w_odt_on; + tfaw = ac_tim->tfaw_4266; + tfaw_05t = ac_tim->tfaw_4266_05T; + trrd = ac_tim->trrd_4266; + trrd_05t = ac_tim->trrd_4266_05T; + xtrtrt = ac_tim->xrtr2r_new_mode; + xrtwtw = ac_tim->xrtw2w_new_mode; + tmrr2w = ac_tim->tmrr2w_odt_on; + + if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + datlat_dsel = ac_tim->datlat; + else + datlat_dsel = ac_tim->datlat > 1 ? ac_tim->datlat - 1 : 0; + + if (ac_tim->dqsinctl >= 2) { + rank_inctl_root = ac_tim->dqsinctl - 2; + } else { + dramc_err("rank_inctl_root <2, need check\n"); + rank_inctl_root = 0; + } + phs_inctl = (ac_tim->dqsinctl == 0) ? 0 : (ac_tim->dqsinctl - 1); + + if (freq_group <= DDRFREQ_800) { + if (get_div_mode(cali) == DIV4_MODE) { + tx_rank_inctl = 1; + tx_dly = 2; + } else { + tx_rank_inctl = 0; + tx_dly = 1; + } + } else { + tx_rank_inctl = 1; + tx_dly = 2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim1, + SHU_ACTIM1_TRAS, ac_tim->tras, + SHU_ACTIM1_TRP, ac_tim->trp, + SHU_ACTIM1_TRPAB, ac_tim->trpab, + SHU_ACTIM1_TMRWCKEL, ac_tim->tmrwckel, + SHU_ACTIM1_TRC, ac_tim->trc); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFC, ac_tim->trfc, + SHU_ACTIM3_TR2MRR, ac_tim->tr2mrr, + SHU_ACTIM3_TRFCPB, ac_tim->trfcpb); + SET32_BITFIELDS(&ch[chn].ao.shu_actim2, + SHU_ACTIM2_TXP, ac_tim->txp, + SHU_ACTIM2_TMRRI, ac_tim->tmrri, + SHU_ACTIM2_TFAW, tfaw, + SHU_ACTIM2_TR2W, trtw, + SHU_ACTIM2_TRTP, ac_tim->trtp); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, + SHU_ACTIM0_TRCD, ac_tim->trcd, + SHU_ACTIM0_TWR, ac_tim->twr, + SHU_ACTIM0_TRRD, trrd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, + SHU_ACTIM5_TPBR2PBR, ac_tim->tpbr2pbr, + SHU_ACTIM5_TWTPD, ac_tim->twtpd, + SHU_ACTIM5_TPBR2ACT, ac_tim->tpbr2act); + SET32_BITFIELDS(&ch[chn].ao.shu_actim6, + SHU_ACTIM6_TR2MRW, ac_tim->tr2mrw, + SHU_ACTIM6_TW2MRW, ac_tim->tw2mrw, + SHU_ACTIM6_TMRD, ac_tim->tmrd, + SHU_ACTIM6_TZQLAT2, ac_tim->zqlat2, + SHU_ACTIM6_TMRW, ac_tim->tmrw); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, + SHU_ACTIM4_TMRR2MRW, ac_tim->tmrr2mrw, + SHU_ACTIM4_TMRR2W, tmrr2w, + SHU_ACTIM4_TZQCS, ac_tim->tzqcs, + SHU_ACTIM4_TXREFCNT, ac_tim->txrefcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim->ckeprd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTW2W, xrtwtw, + SHU_ACTIM_XRT_XRTW2R, xrtw2r, + SHU_ACTIM_XRT_XRTR2W, xrtr2w, + SHU_ACTIM_XRT_XRTR2R, xtrtrt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim->vrcgdis_prdcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim->hwset_mr2_op); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim->hwset_mr13_op); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TWTR_M05T, ac_tim->twtr_05T, + SHU_AC_TIME_05T_TR2W_05T, trtw_05t, + SHU_AC_TIME_05T_TWTPD_M05T, ac_tim->twtpd_05T, + SHU_AC_TIME_05T_TFAW_05T, tfaw_05t, + SHU_AC_TIME_05T_TRRD_05T, trrd_05t, + SHU_AC_TIME_05T_TWR_M05T, ac_tim->twr_05T, + SHU_AC_TIME_05T_TRAS_05T, ac_tim->tras_05T, + SHU_AC_TIME_05T_TRPAB_05T, ac_tim->trpab_05T, + SHU_AC_TIME_05T_TRP_05T, ac_tim->trp_05T, + SHU_AC_TIME_05T_TRCD_05T, ac_tim->trcd_05T, + SHU_AC_TIME_05T_TRTP_05T, ac_tim->trtp_05T, + SHU_AC_TIME_05T_TXP_05T, ac_tim->txp_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFC_05T, ac_tim->trfc_05T, + SHU_AC_TIME_05T_TRFCPB_05T, ac_tim->trfcpb_05T, + SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim->tpbr2pbr_05T, + SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim->tpbr2act_05T, + SHU_AC_TIME_05T_TR2MRW_05T, ac_tim->tr2mrw_05T, + SHU_AC_TIME_05T_TW2MRW_05T, ac_tim->tw2mrw_05T, + SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim->tmrr2mrw_05T, + SHU_AC_TIME_05T_TMRW_05T, ac_tim->tmrw_05T, + SHU_AC_TIME_05T_TMRD_05T, ac_tim->tmrd_05T, + SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim->tmrwckel_05T, + SHU_AC_TIME_05T_TMRRI_05T, ac_tim->tmrri_05T, + SHU_AC_TIME_05T_TRC_05T, ac_tim->trc_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim->twtr); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, + SHU_CKECTRL_TPDE, ac_tim->tpde, + SHU_CKECTRL_TPDX, ac_tim->tpdx, + SHU_CKECTRL_TPDE_05T, ac_tim->tpde_05T, + SHU_CKECTRL_TPDX_05T, ac_tim->tpdx_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim->trtpd); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2PD_05T, ac_tim->trtpd_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_TRCD_DERATE, ac_tim->trcd_derate, + SHU_AC_DERATING0_TRRD_DERATE, ac_tim->trrd_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRC_DERATE, ac_tim->trc_derate, + SHU_AC_DERATING1_TRAS_DERATE, ac_tim->tras_derate, + SHU_AC_DERATING1_TRP_DERATE, ac_tim->trp_derate, + SHU_AC_DERATING1_TRPAB_DERATE, ac_tim->trpab_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim->trrd_derate_05T, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim->tras_derate_05T, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim->trpab_derate_05T, + SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim->trp_derate_05T, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim->trcd_derate_05T, + SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim->trc_derate_05T); + SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim->dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODT_LAT, ac_tim->dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim->dqsinctl, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root, + MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, ac_tim->datlat, + MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); + SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf, + SHU_ACTIMING_CONF_REFBW_FR, tref_bw); + rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl); + SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root, + SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly); + } +} + +static void set_cke2rank_independent(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_CKE2RANK, 0); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE2RANK_OPT3, 0, + CKECTRL_CKE2RANK_OPT, 0, + CKECTRL_CKE2RANK_OPT2, 1, + CKECTRL_CKE2RANK_OPT5, 0, + CKECTRL_CKE2RANK_OPT6, 0, + CKECTRL_CKE2RANK_OPT7, 1, + CKECTRL_CKE2RANK_OPT8, 0, + CKECTRL_CKETIMER_SEL, 0, + CKECTRL_FASTWAKE_SEL, 1, + CKECTRL_CKEWAKE_SEL, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_FASTWAKE, 1, + SHU_DCM_CTRL0_FASTWAKE2, 1); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, ACTIMING_CTRL_CLKWITRFC, 0); + } +} + +static void dramc_hw_gating_onoff(bool is_on) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_OPTION, is_on, + MISC_DVFSCTL2_R_DVFS_PARK_N, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_GERRSTOP, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, is_on); + } +} + +static void dramc_reset_delay_chain_before_calibration(void) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + struct ddrphy_ao_regs *phy_ao = &ch[chn].phy_ao; + + SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly0, + SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 0); + SET32_BITFIELDS(&phy_ao->ca_rk[rk].shu_r0_ca_txdly1, + SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 0); + SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0); + SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0); + SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0); + SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0); + SET32_BITFIELDS(&phy_ao->byte[0].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); + SET32_BITFIELDS(&phy_ao->byte[1].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); + } + } + + dramc_set_broadcast(bc_bak); +} + +static void dramc_init(const struct ddr_cali *cali) +{ + dramc_setting(cali); + dramc_reset_delay_chain_before_calibration(); + dramc_8_phase_cal(cali); + dramc_duty_calibration(cali->params); + dramc_mode_reg_init(cali); + + ddr_update_ac_timing(cali); +} + +static void dramc_before_calibration(const struct ddr_cali *cali) +{ + u8 ma_type = get_column_num(); + dram_freq_grp freq_group = cali->freq_group; + u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0 : 1; + + dramc_hw_gating_onoff(false); + + cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_FIXON); + cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_FIXON); + + set_cke2rank_independent(); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 1); + + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPCALCNT, dis_imp_hw ? 0x0 : 0x40); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMPCAL_HW, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_UNTERM_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_zq_set0, + SHU_ZQ_SET0_ZQCSCNT, 0x1ff, + SHU_ZQ_SET0_TZQLAT, 0x1b); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCSDUAL, 1, + ZQ_SET0_ZQCSMASK_OPT, 0, + ZQ_SET0_ZQMASK_CGAR, 0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0); + } + SET32_BITFIELDS(&ch[0].ao.zq_set0, ZQ_SET0_ZQCSMASK, 1); + SET32_BITFIELDS(&ch[1].ao.zq_set0, ZQ_SET0_ZQCSMASK, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.zq_set0, ZQ_SET0_ZQCS_MASK_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 0); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.shu_matype, SHU_MATYPE_MATYPE, ma_type); + } + tx_path_algorithm(cali); +} + void dfs_init_for_calibration(const struct ddr_cali *cali) { + dramc_init_default_mr_value(cali); + dramc_init(cali); + dramc_before_calibration(cali); } diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c new file mode 100644 index 00000000000..e4dc8968296 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -0,0 +1,657 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ + [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, + [ODT_ON] = {0x3a, 0x33, 0x00, 0x3a}, +}; + +static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type) +{ + u8 vref_tmp = imp_vref_sel[odt][drv_type]; + + switch (drv_type) { + case DRVP: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp); + break; + case DRVN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp); + break; + case ODTN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp); + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } +} + +static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type) +{ + u32 drive = 0, cal_res = 0; + u32 change = (drv_type == DRVP) ? 1 : 0; + + static const char *const drv_type_str[IMP_DRV_MAX] = { + [DRVP] = "DRVP", + [DRVN] = "DRVN", + [ODTP] = "ODTP", + [ODTN] = "ODTN", + }; + if (drv_type >= IMP_DRV_MAX) + die("Can't support drv_type %d", drv_type); + + const char *drv_str = drv_type_str[drv_type]; + + for (drive = 0; drive < 32; drive++) { + if (drv_type == DRVP) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drive); + else if (drv_type == DRVN || drv_type == ODTN) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, drive); + + udelay(1); + cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd, + MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); + dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res); + + if (cal_res == change) { + dramc_info("%s calibration passed! result=%d\n", drv_str, drive); + break; + } + } + + if (drive == 32) { + drive = 31; + dramc_err("OCD %s calibration failed! %s=%d\n", drv_str, drv_str, drive); + } + + return drive; +} + +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp) +{ + const u8 chn = 0; + u8 i_chn, enp, enn; + u32 bc_bak, impcal_bak, cal_res; + u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) { + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10, 0x0, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0); + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0); + } + + impcal_bak = read32(&ch[chn].phy_ao.misc_impcal); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, 0, + MISC_IMPCAL_IMPCAL_IMPPDP, 1, + MISC_IMPCAL_IMPCAL_IMPPDN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_IMP_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, 0, + SHU_MISC_IMPCAL1_IMPDRVP, 0); + + for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) { + if (drv_type == ODTP) + continue; + dramc_imp_cal_vref_sel(odt, drv_type); + + switch (drv_type) { + case DRVP: + enp = 0x1; + enn = 0x0; + drvp_result = 0; + break; + case DRVN: + case ODTN: + enp = 0x0; + enn = (drv_type == DRVN) ? 0x0 : 0x1; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENP, enp); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, enn); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drvp_result); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_DRV05, 0); + + cal_res = dramc_sw_imp_cal_result(drv_type); + switch (drv_type) { + case DRVP: + drvp_result = cal_res; + break; + case DRVN: + drvn_result = cal_res; + break; + case ODTN: + odtn_result = cal_res; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + } + + imp->result[odt][DRVP] = drvp_result; + imp->result[odt][DRVN] = drvn_result; + imp->result[odt][ODTP] = 0; + imp->result[odt][ODTN] = odtn_result; + + dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", + odt, drvp_result, drvn_result, odtn_result); + + write32(&ch[chn].phy_ao.misc_impcal, impcal_bak); + dramc_set_broadcast(bc_bak); +} + +void dramc_sw_impedance_save_register(const struct ddr_cali *cali) +{ + u8 ca_term, dq_term; + u32 bc_bak = dramc_get_broadcast(); + const u32 (*result)[IMP_DRV_MAX] = cali->impedance.result; + struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao; + + ca_term = get_odt_state(cali); + dq_term = (get_freq_group(cali) < DDRFREQ_2133) ? ODT_OFF : ODT_ON; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&phy_ao->shu_misc_drving1, + SHU_MISC_DRVING1_DQDRVP2, result[dq_term][DRVP], + SHU_MISC_DRVING1_DQDRVN2, result[dq_term][DRVN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving2, + SHU_MISC_DRVING2_DQDRVP1, result[dq_term][DRVP], + SHU_MISC_DRVING2_DQDRVN1, result[dq_term][DRVN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving3, + SHU_MISC_DRVING3_DQODTP2, result[dq_term][ODTP], + SHU_MISC_DRVING3_DQODTN2, result[dq_term][ODTN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving4, + SHU_MISC_DRVING4_DQODTP1, result[dq_term][ODTP], + SHU_MISC_DRVING4_DQODTN1, result[dq_term][ODTN]); + + SET32_BITFIELDS(&phy_ao->shu_misc_drving1, + SHU_MISC_DRVING1_DQSDRVP2, result[dq_term][DRVP], + SHU_MISC_DRVING1_DQSDRVN2, result[dq_term][DRVN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving1, + SHU_MISC_DRVING1_DQSDRVP1, result[dq_term][DRVP], + SHU_MISC_DRVING1_DQSDRVN1, result[dq_term][DRVN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving3, + SHU_MISC_DRVING3_DQSODTP2, result[dq_term][ODTP], + SHU_MISC_DRVING3_DQSODTN2, result[dq_term][ODTN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving3, + SHU_MISC_DRVING3_DQSODTP, result[dq_term][ODTP], + SHU_MISC_DRVING3_DQSODTN, result[dq_term][ODTN]); + + SET32_BITFIELDS(&phy_ao->shu_misc_drving2, + SHU_MISC_DRVING2_CMDDRVP2, result[ca_term][DRVP], + SHU_MISC_DRVING2_CMDDRVN2, result[ca_term][DRVN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving2, + SHU_MISC_DRVING2_CMDDRVP1, result[ca_term][DRVP], + SHU_MISC_DRVING2_CMDDRVN1, result[ca_term][DRVN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving4, + SHU_MISC_DRVING4_CMDODTP2, result[ca_term][ODTP], + SHU_MISC_DRVING4_CMDODTN2, result[ca_term][ODTN]); + SET32_BITFIELDS(&phy_ao->shu_misc_drving4, + SHU_MISC_DRVING4_CMDODTP1, result[ca_term][ODTP], + SHU_MISC_DRVING4_CMDODTN1, result[ca_term][ODTN]); + + SET32_BITFIELDS(&phy_ao->misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVP, 0xF); + SET32_BITFIELDS(&phy_ao->misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVN, 0x14); + + dramc_set_broadcast(bc_bak); +} + +static void dramc_phy_reset(u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0); + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 0); +} + +static int dramc_8_phase_cal_find_best_dly(u8 phase_sm, u8 ph_dly, u8 ph_dly_back, + int *ph_dly_final, int *ph_dly_loop_break) +{ + const u8 early_break_cnt = 5; + static u8 loop_cnt = 0; + static u16 r0 = 0xffff, r180 = 0xffff, r_tmp = 0xffff, p_tmp = 0xffff; + s16 err_code; + static s16 err_code_min = 0x7fff; + u16 dqs_dly; + const u16 jm_dly_start = 0, jm_dly_end = 512, jm_dly_step = 1; + u32 sample_cnt, ones_cnt; + u8 dqs_level = DQS_LEVEL_UNKNOWN; + + dramc_dbg("8PH dly = %u\n", ph_dly); + *ph_dly_loop_break = 0; + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly); + + for (dqs_dly = jm_dly_start; dqs_dly < jm_dly_end; dqs_dly += jm_dly_step) { + /* Set DQS delay */ + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, + B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, dqs_dly); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, + B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, dqs_dly); + dramc_phy_reset(0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_REG_SW_RST, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_REG_SW_RST, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1); + udelay(10); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0); + sample_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_toggle_cnt, + MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); + ones_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_dqs0_err_cnt, + MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); + + if (ones_cnt < sample_cnt / 2) { + if (dqs_level == DQS_LEVEL_UNKNOWN) + dramc_dbg("[L] %u, %8u\n", dqs_dly, ones_cnt); + dqs_level = 0; + } else if (dqs_level == 0) { + dqs_level = 1; + dramc_dbg("[H] %u, %8u\n", dqs_dly, ones_cnt); + + if (phase_sm == DQS_8PH_DEGREE_0) { + r0 = dqs_dly; + dramc_dbg("R0 = %u\n", r0); + } else if (phase_sm == DQS_8PH_DEGREE_180) { + r180 = dqs_dly; + if (r180 <= r0) { + dqs_level = DQS_LEVEL_UNKNOWN; + continue; + } + + r_tmp = r0 + ((r180 - r0) >> 2); + dramc_dbg("R = %u, R180 = %u\n", r_tmp, r180); + } else if (phase_sm == DQS_8PH_DEGREE_45) { + p_tmp = dqs_dly; + dramc_dbg("p_tmp = %u, R0 = %u\n", p_tmp, r0); + if (p_tmp <= r0) { + dqs_level = DQS_LEVEL_UNKNOWN; + continue; + } + + err_code = ABS(p_tmp - r_tmp); + + if (err_code == 0) { + *ph_dly_final = ph_dly; + *ph_dly_loop_break = 1; + } else if (err_code < err_code_min) { + err_code_min = err_code; + *ph_dly_final = ph_dly; + loop_cnt = 0; + } else { + loop_cnt++; + if (loop_cnt > early_break_cnt) + *ph_dly_loop_break = 1; + } + + dramc_dbg("diff (P-R) = %d, min = %d, break count = %u\n", + err_code, err_code_min, loop_cnt); + } else { + die("Invalid phase_sm: %u!\n", phase_sm); + } + + break; + } + } + + if (dqs_level == DQS_LEVEL_UNKNOWN || dqs_level == 0) { + *ph_dly_final = ph_dly_back; + dramc_err("8-Phase SM_%u failed, falling back to default\n", phase_sm); + return 0; + } else if (*ph_dly_loop_break) { + return -1; + } + + return -2; +} + +static void dramc_8_phase_cal_set_best_dly(const struct ddr_cali *cali, u8 ph_dly_back) +{ + u8 dqsien_pi; + u8 phase_sm, ph_dly, ph_start, ph_end; + int ph_dly_loop_break; + int ph_dly_final = 0xff; /* default delay: 0xff */ + + for (phase_sm = DQS_8PH_DEGREE_0; phase_sm < DQS_8PH_DEGREE_MAX; phase_sm++) { + switch (phase_sm) { + case DQS_8PH_DEGREE_0: + dqsien_pi = 16; + ph_start = 0; + ph_end = 1; + break; + case DQS_8PH_DEGREE_180: + dqsien_pi = 48; + ph_start = 0; + ph_end = 1; + break; + case DQS_8PH_DEGREE_45: + dqsien_pi = 24; + ph_start = 0; + ph_end = 32; + break; + default: + die("Invalid phase_sm: %u!\n", phase_sm); + return; + } + + dramc_dbg("8-Phase SM_%u, 8PH_dly (%u~%u), DQSIEN PI = %u, 8PH_Dly = %u\n", + phase_sm, ph_start, ph_end, dqsien_pi, ph_dly_back); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, dqsien_pi); + + for (ph_dly = ph_start; ph_dly < ph_end; ph_dly++) { + int ret = dramc_8_phase_cal_find_best_dly(phase_sm, ph_dly, + ph_dly_back, &ph_dly_final, &ph_dly_loop_break); + if (ret == 0) + goto final_found; + if (ph_dly_loop_break) + break; + } + } + +final_found: + dramc_dbg("8 phase calibration ph_dly_final = %u\n", ph_dly_final); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly_final); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly_final); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly_final); + } +} + +void dramc_8_phase_cal(const struct ddr_cali *cali) +{ + u8 ph_dly_back = 0; + dram_freq_grp freq_group = cali->freq_group; + /* ch0 and ch1 of phy_ao */ + struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao; + struct ddrphy_ao_regs *phy_ao_ch1 = &ch[1].phy_ao; + + if (freq_group < DDRFREQ_2133) { + dramc_info("Freq %u < 2133, do not need do 8-Phase\n", get_frequency(cali)); + return; + } + + struct reg_bak regs_bak[] = { + {&phy_ao->misc_dutyscan1}, + {&phy_ao->dvs_b[0].b0_dq6}, + {&phy_ao->dvs_b[1].b0_dq6}, + {&phy_ao->dvs_b[0].b0_dq5}, + {&phy_ao->dvs_b[1].b0_dq5}, + {&phy_ao->dvs_b[0].b0_dq3}, + {&phy_ao->dvs_b[1].b0_dq3}, + {&phy_ao->misc_ctrl1}, + {&phy_ao->misc_ctrl4}, + {&phy_ao->dvs_b[0].b0_phy2}, + {&phy_ao->dvs_b[1].b0_phy2}, + {&phy_ao->byte[0].shu_b0_dll_arpi2}, + {&phy_ao->byte[1].shu_b0_dll_arpi2}, + {&phy_ao->byte[0].shu_b0_dq11}, + {&phy_ao->byte[1].shu_b0_dq11}, + {&phy_ao->shu_ca_cmd11}, + {&phy_ao->misc_stbcal}, + {&phy_ao->byte[0].rk[0].shu_rk_b0_dqsien_pi_dly}, + {&phy_ao->byte[0].rk[1].shu_rk_b0_dqsien_pi_dly}, + {&phy_ao->misc_jmeter}, + {&phy_ao->misc_shu_stbcal}, + {&phy_ao->shu_ca_dll1}, + {&phy_ao->byte[0].shu_b0_dll1}, + {&phy_ao->byte[1].shu_b0_dll1}, + {&phy_ao->dvs_b[0].b0_dq2}, + {&phy_ao->dvs_b[1].b0_dq2}, + {&phy_ao->ca_cmd2}, + {&phy_ao->byte[0].shu_b0_dq13}, + {&phy_ao->byte[1].shu_b0_dq13}, + {&phy_ao->shu_ca_cmd13}, + {&phy_ao_ch1->shu_ca_dll1}, + {&phy_ao_ch1->byte[0].shu_b0_dll1}, + {&phy_ao_ch1->byte[1].shu_b0_dll1}, + {&phy_ao_ch1->dvs_b[0].b0_dq2}, + {&phy_ao_ch1->dvs_b[1].b0_dq2}, + {&phy_ao_ch1->ca_cmd2}, + {&phy_ao_ch1->byte[0].shu_b0_dq13}, + {&phy_ao_ch1->byte[1].shu_b0_dq13}, + {&phy_ao_ch1->shu_ca_cmd13}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + phy_ao = &ch[chn].phy_ao; + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq2, + B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 0xff); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq2, + B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 0xff); + SET32_BITFIELDS(&phy_ao->ca_cmd2, + CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 1); + SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 1); + SET32_BITFIELDS(&phy_ao->shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 0, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 1); + } + + phy_ao = &ch[0].phy_ao; + ph_dly_back = READ32_BITFIELD(&phy_ao->byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); + SET32_BITFIELDS(&phy_ao->misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, 0x0, + MISC_SHU_STBCAL_STB_SELPHCALEN, 0x0); + SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0); + SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0); + SET32_BITFIELDS(&phy_ao->shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + phy_ao = &ch[chn].phy_ao; + SET32_BITFIELDS(&phy_ao->shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0x0, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 0x0); + SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0x0, + SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 0x0); + SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0x0, + SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 0x0); + } + + phy_ao = &ch[0].phy_ao; + SET32_BITFIELDS(&phy_ao->misc_ctrl1, MISC_CTRL1_R_DMDQSIENCG_EN, 0); + SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0); + SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0); + SET32_BITFIELDS(&phy_ao->misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1); + SET32_BITFIELDS(&phy_ao->misc_ctrl4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0); + SET32_BITFIELDS(&phy_ao->misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0); + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 1); + SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1); + SET32_BITFIELDS(&phy_ao->misc_dutyscan1, + MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 0x1, + MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 0x1, + MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 0x1); + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq3, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq3, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 1); + SET32_BITFIELDS(&phy_ao->misc_jmeter, MISC_JMETER_JMTR_EN, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 1); + SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 1); + SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 1); + SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0); + SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_DQSERRCNT_DIS, 0); + + dramc_8_phase_cal_set_best_dly(cali, ph_dly_back); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); +} + +static void duty_delay_reg_convert(s8 duty_delay, u8 *delay) +{ + if (duty_delay < 0) + *delay = -duty_delay; + else if (duty_delay > 0) + *delay = duty_delay + (1 << 5); + else + *delay = 0; +} + +static void dramc_duty_set_clk_delay_cell(u8 chn, const s8 *duty_delay) +{ + u8 delay; + + duty_delay_reg_convert(duty_delay[RANK_0], &delay); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_txduty, + SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, delay); +} + +static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8 *duty_delay) +{ + u8 dqs; + u8 delay; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &delay); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, delay); + } +} + +static void dramc_duty_set_wck_delay_cell(u8 chn, const s8 *duty_delay) +{ + u8 dqs; + u8 delay; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &delay); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, delay); + } +} + +static void dramc_duty_set_dqdqm_delay_cell(u8 chn, const s8 *duty_delay, + u8 k_type) +{ + u8 dqs; + u8 delay; + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + duty_delay_reg_convert(duty_delay[dqs], &delay); + + if (k_type == DUTYSCAN_K_DQ) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, delay); + else if (k_type == DUTYSCAN_K_DQM) + SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty, + SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, delay); + } +} + +void dramc_duty_calibration(const struct sdram_params *params) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + dramc_duty_set_clk_delay_cell(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay_cell(chn, params->duty_dqs_delay[chn]); + dramc_duty_set_wck_delay_cell(chn, params->duty_wck_delay[chn]); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dqm_delay[chn], + DUTYSCAN_K_DQM); + dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dq_delay[chn], + DUTYSCAN_K_DQ); + } + + dramc_set_broadcast(bc_bak); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index a2a4dea1c4d..b4e6e1ae960 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -2,8 +2,190 @@ #include #include +#include +#include #include +static void dramc_ac_timing_optimize(const struct ddr_cali *cali) +{ + u8 rf_group, cab_id; + u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + + enum { + TRFCAB_130, + TRFCAB_180, + TRFCAB_280, + TRFCAB_380, + TRFCAB_NUM, + }; + enum { + GRP_DDR800_DIV4_ACTIM, + GRP_DDR1200_ACTIM, + GRP_DDR1600_ACTIM, + GRP_DDR1866_ACTIM, + GRP_DDR2400_ACTIM, + GRP_DDR3200_ACTIM, + GRP_DDR4266_ACTIM, + GRP_ACTIM_NUM, + }; + struct optimize_ac_time { + u8 trfc; + u8 trfc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; + u16 tx_ref_cnt; + }; + + const u8 density = cali->density; + const dram_freq_grp freq_group = get_freq_group(cali); + + /* tRFCab */ + struct optimize_ac_time *ptr_trfcab_opt; + struct optimize_ac_time trfcab_opt[GRP_ACTIM_NUM][TRFCAB_NUM] = { + [GRP_DDR800_DIV4_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1200_ACTIM] = { + {.trfc = 8, .trfc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 21}, + {.trfc = 15, .trfc_05t = 1, .trfc_pb = 2, + .trfrc_pb05t = 0, .tx_ref_cnt = 29}, + {.trfc = 30, .trfc_05t = 1, .trfc_pb = 9, + .trfrc_pb05t = 1, .tx_ref_cnt = 44}, + {.trfc = 45, .trfc_05t = 1, .trfc_pb = 17, + .trfrc_pb05t = 0, .tx_ref_cnt = 59} + }, + [GRP_DDR1600_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1866_ACTIM] = { + {.trfc = 18, .trfc_05t = 1, .trfc_pb = 2, + .trfrc_pb05t = 0, .tx_ref_cnt = 33}, + {.trfc = 30, .trfc_05t = 0, .trfc_pb = 9, + .trfrc_pb05t = 0, .tx_ref_cnt = 44}, + {.trfc = 53, .trfc_05t = 1, .trfc_pb = 21, + .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + {.trfc = 77, .trfc_05t = 0, .trfc_pb = 32, + .trfrc_pb05t = 1, .tx_ref_cnt = 91} + }, + [GRP_DDR2400_ACTIM] = { + {.trfc = 27, .trfc_05t = 1, .trfc_pb = 6, + .trfrc_pb05t = 1, .tx_ref_cnt = 42}, + {.trfc = 42, .trfc_05t = 1, .trfc_pb = 15, + .trfrc_pb05t = 1, .tx_ref_cnt = 57}, + {.trfc = 72, .trfc_05t = 1, .trfc_pb = 30, + .trfrc_pb05t = 1, .tx_ref_cnt = 87}, + {.trfc = 102, .trfc_05t = 1, .trfc_pb = 45, + .trfrc_pb05t = 1, .tx_ref_cnt = 117} + }, + [GRP_DDR3200_ACTIM] = { + {.trfc = 40, .trfc_05t = 0, .trfc_pb = 12, + .trfrc_pb05t = 0, .tx_ref_cnt = 55}, + {.trfc = 60, .trfc_05t = 0, .trfc_pb = 24, + .trfrc_pb05t = 0, .tx_ref_cnt = 75}, + {.trfc = 100, .trfc_05t = 0, .trfc_pb = 44, + .trfrc_pb05t = 0, .tx_ref_cnt = 115}, + {.trfc = 140, .trfc_05t = 0, .trfc_pb = 64, + .trfrc_pb05t = 0, .tx_ref_cnt = 155} + }, + [GRP_DDR4266_ACTIM] = { + {.trfc = 57, .trfc_05t = 1, .trfc_pb = 20, + .trfrc_pb05t = 0, .tx_ref_cnt = 74}, + {.trfc = 84, .trfc_05t = 0, .trfc_pb = 36, + .trfrc_pb05t = 0, .tx_ref_cnt = 100}, + {.trfc = 137, .trfc_05t = 1, .trfc_pb = 63, + .trfrc_pb05t = 0, .tx_ref_cnt = 154}, + {.trfc = 191, .trfc_05t = 0, .trfc_pb = 89, + .trfrc_pb05t = 1, .tx_ref_cnt = 207} + } + }; + + switch (density) { + case 0x0: + rf_group = TRFCAB_130; + break; + case 0x1: + case 0x2: + rf_group = TRFCAB_180; + break; + case 0x3: + case 0x4: + rf_group = TRFCAB_280; + break; + case 0x5: + case 0x6: + rf_group = TRFCAB_380; + break; + default: + die("Invalid DDR density %u\n", density); + return; + } + + switch (freq_group) { + case DDRFREQ_400: + cab_id = GRP_DDR800_DIV4_ACTIM; + break; + case DDRFREQ_600: + cab_id = GRP_DDR1200_ACTIM; + break; + case DDRFREQ_800: + cab_id = GRP_DDR1600_ACTIM; + break; + case DDRFREQ_933: + cab_id = GRP_DDR1866_ACTIM; + break; + case DDRFREQ_1200: + cab_id = GRP_DDR2400_ACTIM; + break; + case DDRFREQ_1600: + cab_id = GRP_DDR3200_ACTIM; + break; + case DDRFREQ_2133: + cab_id = GRP_DDR4266_ACTIM; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + ptr_trfcab_opt = &trfcab_opt[cab_id][0]; + trfc = ptr_trfcab_opt[rf_group].trfc; + trfc_05t = ptr_trfcab_opt[rf_group].trfc_05t; + trfc_pb = ptr_trfcab_opt[rf_group].trfc_pb; + trfrc_pb05t = ptr_trfcab_opt[rf_group].trfrc_pb05t; + tx_ref_cnt = ptr_trfcab_opt[rf_group].tx_ref_cnt; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFC, trfc); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFC_05T, trfc_05t); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, tx_ref_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, trfc_pb); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); + dramc_dbg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, " + "TRFCpb %u, TRFCpb_05T %u\n", + density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + } +} + static void set_vcore_voltage(const struct ddr_cali *cali) { u32 vcore = get_vcore_value(cali); @@ -12,10 +194,83 @@ static void set_vcore_voltage(const struct ddr_cali *cali) mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); } +static void get_dram_info_after_cal(struct ddr_cali *cali) +{ + u8 vendor_id, density, max_density = 0; + u32 size_gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_info("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + /* these case values are from JESD209-4C MR8 Density OP[5:2] */ + case 0x0: + size_gb = 4; + break; + case 0x1: + size_gb = 6; + break; + case 0x2: + size_gb = 8; + break; + case 0x3: + size_gb = 12; + break; + case 0x4: + size_gb = 16; + break; + case 0x5: + size_gb = 24; + break; + case 0x6: + size_gb = 32; + break; + case 0xC: + size_gb = 2; + break; + default: + dramc_err("Unexpected mode register density value: %#x\n", density); + size_gb = 0; + break; + } + if (size_gb > max_size) { + max_size = size_gb; + max_density = density; + } + dramc_dbg("RK%u size %uGb, density:%u\n", rk, size_gb, max_density); + } + + cali->density = max_density; +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { } +static void mem_pll_init(void) +{ + SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_POWER_ISO_ENABLE, 3); + + udelay(30); + SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_ISO_ENABLE, 0); + + udelay(1); + SET32_BITFIELDS(&mtk_apmixed->mpll_con1, PLL_CON1, MPLL_CON1_FREQ); + SET32_BITFIELDS(&mtk_apmixed->mpll_con0, PLL_ENABLE, 1); + + udelay(20); + SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_IOS_SEL, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_EN_SEL, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con1, MPLL_PWR_SEL, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con2, MPLL_BY_ISO_DLY, 0); + SET32_BITFIELDS(&mtk_apmixed->pllon_con3, MPLL_BY_PWR_DLY, 0); +} + void init_dram(const struct dramc_data *dparam) { u32 bc_bak; @@ -35,12 +290,17 @@ void init_dram(const struct dramc_data *dparam) cali.emi_config = &ddr_info->emi_config; dramc_set_broadcast(DRAMC_BROADCAST_ON); + mem_pll_init(); global_option_init(&cali); bc_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); + emi_mdl_init(cali.emi_config); dramc_set_broadcast(bc_bak); + dramc_sw_impedance_cal(ODT_OFF, &cali.impedance); + dramc_sw_impedance_cal(ODT_ON, &cali.impedance); + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) k_shuffle_end = CALI_SEQ_MAX; else @@ -51,8 +311,22 @@ void init_dram(const struct dramc_data *dparam) set_vcore_voltage(&cali); dfs_init_for_calibration(&cali); + if (first_freq_k) + emi_init2(); + dramc_calibration_all_channels(&cali); + /* only need to do once to get DDR's base information */ + if (first_freq_k) + get_dram_info_after_cal(&cali); + + dramc_ac_timing_optimize(&cali); + dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu); + + /* for frequency switch in dramc_mode_reg_init phase */ + if (first_freq_k) + dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1); + first_freq_k = false; } } diff --git a/src/soc/mediatek/mt8192/eint_event.c b/src/soc/mediatek/mt8192/eint_event.c new file mode 100644 index 00000000000..b3538a1ddf0 --- /dev/null +++ b/src/soc/mediatek/mt8192/eint_event.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void unmask_eint_event_mask(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(mtk_eint_event->eint_event_mask_clr); i++) + write32(&mtk_eint_event->eint_event_mask_clr[i], 0xffffffff); +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index f83acd36bcd..80ee9edcc46 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,431 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include +#include + +static struct emi_regs *emi_reg = (void *)EMI_BASE; +static struct emi_mpu_regs *const emi_mpu = (void *)EMI_MPU_BASE; +static struct infra_ao_mem_regs *infra_ao_mem = (void *)INFRACFG_AO_MEM_BASE; + +static void emi_center_config(void) +{ + /* set EMI default settings which EMI hardware needs */ + write32(&emi_reg->cona, 0xf053f154); + write32(&emi_reg->conp, 0x182e2d33); + write32(&emi_reg->conb, 0x0f251025); + write32(&emi_reg->conq, 0x122a1027); + write32(&emi_reg->conc, 0x1a31162d); + write32(&emi_reg->conb_2nd, 0x182e2d33); + write32(&emi_reg->conc_2nd, 0x0f251025); + write32(&emi_reg->conp_2nd, 0x122a1027); + write32(&emi_reg->conq_2nd, 0x1a31162d); + write32(&emi_reg->conb_3rd, 0x1024202c); + write32(&emi_reg->conc_3rd, 0x0b210c21); + write32(&emi_reg->conp_3rd, 0x0f250d23); + write32(&emi_reg->conq_3rd, 0x152b1228); + write32(&emi_reg->conb_4th, 0x0c201a28); + write32(&emi_reg->conc_4th, 0x0d230a20); + write32(&emi_reg->conp_4th, 0x0e260d24); + write32(&emi_reg->conq_4th, 0x132d1229); + write32(&emi_reg->conb_5th, 0x0c201a28); + write32(&emi_reg->conc_5th, 0x0d230a20); + write32(&emi_reg->conp_5th, 0x0e260d24); + write32(&emi_reg->conq_5th, 0x132d1229); + write32(&emi_reg->conb_6th, 0x0c201a28); + write32(&emi_reg->conc_6th, 0x0d230a20); + write32(&emi_reg->conp_6th, 0x0e260d24); + write32(&emi_reg->conq_6th, 0x132d1229); + write32(&emi_reg->conb_7th, 0x0e290e28); + write32(&emi_reg->conc_7th, 0x091e1322); + write32(&emi_reg->mpud26_st, 0x0f29112a); + write32(&emi_reg->conq_7th, 0x0c240a1f); + write32(&emi_reg->conb_8th, 0x0e290e28); + write32(&emi_reg->conc_8th, 0x091e1322); + write32(&emi_reg->conp_8th, 0x0f29112a); + write32(&emi_reg->conq_8th, 0x0c240a1f); + write32(&emi_reg->cong, 0x37373a57); + write32(&emi_reg->conr, 0x3f3f3c39); + write32(&emi_reg->cong_2nd, 0x3836374e); + write32(&emi_reg->conr_2nd, 0x41413d3a); + write32(&emi_reg->cong_3rd, 0x33313241); + write32(&emi_reg->conr_3rd, 0x3a3a3835); + write32(&emi_reg->cong_4th, 0x34343542); + write32(&emi_reg->conr_4th, 0x3b3b3835); + write32(&emi_reg->cong_5th, 0x34343542); + write32(&emi_reg->conr_5th, 0x3b3b3835); + write32(&emi_reg->cong_6th, 0x34343542); + write32(&emi_reg->conr_6th, 0x3b3b3835); + write32(&emi_reg->cong_7th, 0x37333034); + write32(&emi_reg->conr_7th, 0x39393a39); + write32(&emi_reg->cong_8th, 0x37333034); + write32(&emi_reg->conr_8th, 0x39393a39); + write32(&emi_reg->cond, 0x3657587a); + write32(&emi_reg->cone, 0x0000c042); + write32(&emi_reg->conf, 0x08421000); + write32(&emi_reg->conh, 0x00000083); + write32(&emi_reg->conh_2nd, 0x00073210); + write32(&emi_reg->coni, 0x00008802); + write32(&emi_reg->conj, 0x00000000); + write32(&emi_reg->conm, 0x007812ff); + write32(&emi_reg->conn, 0x00000000); + write32(&emi_reg->mdct, 0x11120c1f); + write32(&emi_reg->shf0, 0x11120c1f); + write32(&emi_reg->mdct_2nd, 0x00001123); + write32(&emi_reg->shf1, 0x00001123); + write32(&emi_reg->iocl, 0xa8a8a8a8); + write32(&emi_reg->iocl_2nd, 0x25252525); + write32(&emi_reg->iocm, 0xa8a8a8a8); + write32(&emi_reg->iocm_2nd, 0x25252525); + write32(&emi_reg->testb, 0x00060037); + write32(&emi_reg->testc, 0x384a0014); + write32(&emi_reg->testd, 0xa0000000); + write32(&emi_reg->arba, 0x20107244); + write32(&emi_reg->arbb, 0x10107044); + write32(&emi_reg->arbc, 0x343450df); + write32(&emi_reg->arbd, 0x0000f0d0); + write32(&emi_reg->arbe, 0x10106048); + write32(&emi_reg->arbf, 0x343450df); + write32(&emi_reg->arbg, 0x83837044); + write32(&emi_reg->arbh, 0x83837044); + write32(&emi_reg->arbi, 0x00007108); + write32(&emi_reg->arbi_2nd, 0x00007108); + write32(&emi_reg->arbk, 0x090a4000); + write32(&emi_reg->slct, 0xff0bff00); + write32(&emi_reg->bmen, 0x00ff0001); + write32(&emi_reg->clua, 0x10000008); + write32(&emi_reg->slva, 0xffffffff); + write32(&emi_reg->thro_os0, 0x24240101); + write32(&emi_reg->thro_os1, 0x01012424); + write32(&emi_reg->thro_os2, 0x50500101); + write32(&emi_reg->thro_os3, 0x01015050); + write32(&emi_reg->thro_ctrl0, 0x0fc39a30); + write32(&emi_reg->thro_prd0, 0x05050003); + write32(&emi_reg->thro_prd1, 0x254dffff); + write32(&emi_reg->thro_lat0, 0x465a788c); + write32(&emi_reg->thro_lat1, 0x000003e8); + write32(&emi_reg->thro_lat2, 0x0000036b); + write32(&emi_reg->thro_lat3, 0x00000290); + write32(&emi_reg->thro_lat4, 0x00000200); + write32(&emi_reg->thro_lat5, 0x00000000); + write32(&emi_reg->thro_lat6, 0x00000000); + write32(&emi_reg->thro_ctrl1, 0x02531cff); + write32(&emi_reg->thro_prd2, 0x00002785); + write32(&emi_reg->thro_lat7, 0x000001b5); + write32(&emi_reg->thro_lat8, 0x003c0000); + write32(&emi_reg->thro_prd3, 0x0255250d); + write32(&emi_reg->bwlmta, 0xffff3c59); + write32(&emi_reg->bwlmtb, 0xffff00ff); + write32(&emi_reg->bwlmte, 0xffffffff); + write32(&emi_reg->bwlmtf, 0x0000ffff); + write32(&emi_reg->thro_lat9, 0x0000014b); + write32(&emi_reg->thro_lat10, 0x002d0000); + write32(&emi_reg->thro_lat11, 0x00000185); + write32(&emi_reg->thro_lat12, 0x003c0000); + write32(&emi_reg->thro_lat13, 0x00000185); + write32(&emi_reg->thro_lat14, 0x003c0000); + write32(&emi_reg->bwlmte_2nd, 0xffffffff); + write32(&emi_reg->bwlmtf_2nd, 0xffffffff); + write32(&emi_reg->bwlmtg_2nd, 0xffffffff); + write32(&emi_reg->bwlmte_4th, 0xffffffff); + write32(&emi_reg->bwlmtf_4th, 0x0000ffff); + write32(&emi_reg->bwlmte_5th, 0xffffffff); + write32(&emi_reg->bwlmtf_5th, 0xffffffff); + write32(&emi_reg->bwlmtg_5th, 0xffffffff); + write32(&emi_reg->thro_lat27, 0x41547082); + write32(&emi_reg->thro_lat28, 0x38382a38); + write32(&emi_reg->thro_lat29, 0x000001d4); + write32(&emi_reg->thro_lat30, 0x00000190); + write32(&emi_reg->thro_lat31, 0x0000012c); + write32(&emi_reg->thro_lat32, 0x000000ed); + write32(&emi_reg->thro_lat33, 0x000000c8); + write32(&emi_reg->thro_lat34, 0x00000096); + write32(&emi_reg->thro_lat35, 0x000000c8); + write32(&emi_reg->thro_lat36, 0x000000c8); + write32(&emi_reg->thro_lat41, 0x26304048); + write32(&emi_reg->thro_lat42, 0x20201820); + write32(&emi_reg->thro_lat55, 0x181e282f); + write32(&emi_reg->thro_lat56, 0x14140f18); + write32(&emi_reg->thro_lat69, 0x7496c8ea); + write32(&emi_reg->thro_lat70, 0x64644b64); + write32(&emi_reg->thro_lat83, 0x01010101); + write32(&emi_reg->thro_lat84, 0x01010101); + write32(&emi_reg->thro_lat97, 0x7496c8ea); + write32(&emi_reg->thro_lat98, 0x64644b64); + write32(&emi_reg->thro_lat111, 0x01010101); + write32(&emi_reg->thro_lat112, 0x01010101); + write32(&emi_reg->thro_prd5, 0x300ff025); + write32(&emi_reg->thro_lat113, 0x000003e8); + write32(&emi_reg->thro_lat114, 0x0000036b); + write32(&emi_reg->thro_lat115, 0x00000290); + write32(&emi_reg->thro_lat116, 0x00000200); + write32(&emi_reg->thro_lat117, 0x000001b5); + write32(&emi_reg->thro_lat118, 0x0000014b); + write32(&emi_reg->thro_lat119, 0x00000185); + write32(&emi_reg->thro_lat120, 0x00000185); + write32(&emi_reg->thro_lat125, 0x52698ca0); + write32(&emi_reg->thro_lat126, 0x46463546); + write32(&emi_reg->thro_lat139, 0x01010101); + write32(&emi_reg->thro_lat140, 0x01010101); + write32(&emi_reg->qos_mdr_be0a, 0x00000009); + write32(&emi_reg->qos_mdr_be1a, 0x00000000); + write32(&emi_reg->qos_mdr_shf0, 0x00730000); + write32(&emi_reg->qos_mdr_shf1, 0x00000808); + write32(&emi_reg->qos_mdw_be0a, 0x00000028); + write32(&emi_reg->qos_mdw_be1a, 0x00000000); + write32(&emi_reg->qos_mdw_shf0, 0x00730000); + write32(&emi_reg->qos_mdw_shf1, 0x00000808); + write32(&emi_reg->qos_apr_be0a, 0x00000080); + write32(&emi_reg->qos_apr_be1a, 0x00000000); + write32(&emi_reg->qos_apr_shf0, 0x30201008); + write32(&emi_reg->qos_apw_be0a, 0x00000800); + write32(&emi_reg->qos_apw_be1a, 0x00000000); + write32(&emi_reg->qos_mmr_be0a, 0x00008000); + write32(&emi_reg->qos_mmr_be1a, 0x00020000); + write32(&emi_reg->qos_mmr_be1b, 0x00001000); + write32(&emi_reg->qos_mmr_be2a, 0x00010000); + write32(&emi_reg->qos_mmr_be2b, 0x00000800); + write32(&emi_reg->qos_mmr_shf0, 0x08080000); + write32(&emi_reg->qos_mmr_shf1, 0x00073030); + write32(&emi_reg->qos_mmw_be0a, 0x00040000); + write32(&emi_reg->qos_mmw_be1a, 0x00100000); + write32(&emi_reg->qos_mmw_be1b, 0x00004000); + write32(&emi_reg->qos_mmw_be2a, 0x00080000); + write32(&emi_reg->qos_mmw_be2b, 0x00002000); + write32(&emi_reg->qos_mmw_shf0, 0x08080000); + write32(&emi_reg->qos_mmw_shf1, 0x00074040); + write32(&emi_reg->qos_mdhwr_be0a, 0x00400000); + write32(&emi_reg->qos_mdhwr_be1a, 0x00200000); + write32(&emi_reg->qos_mdhwr_shf0, 0x10100404); + write32(&emi_reg->qos_mdhww_be0a, 0x01000000); + write32(&emi_reg->qos_mdhww_be1a, 0x00800000); + write32(&emi_reg->qos_gpur_be0a, 0x04000000); + write32(&emi_reg->qos_gpur_be1a, 0x02000000); + write32(&emi_reg->qos_gpur_shf0, 0x60602010); + write32(&emi_reg->qos_gpuw_be0a, 0x10000000); + write32(&emi_reg->qos_gpuw_be1a, 0x08000000); + write32(&emi_reg->qos_arbr_be0a, 0x00000009); + write32(&emi_reg->qos_arbr_be1a, 0x04400080); + write32(&emi_reg->qos_arbr_shf0, 0x0f170f11); + write32(&emi_reg->qos_ctrl1, 0x0303f7f7); + write32(&emi_reg->ext_lt_con1_1st, 0x00000166); + write32(&emi_reg->ext_lt_con2_1st, 0xffffffff); + write32(&emi_reg->ext_lt_con3_1st, 0xffffffff); + write32(&emi_reg->ext_lt_con1_2nd, 0x00400166); + write32(&emi_reg->ext_lt_con2_2nd, 0xffffffff); + write32(&emi_reg->ext_lt_con3_2nd, 0xffffffff); + write32(&emi_reg->ext_lt_con1_3rd, 0x00000266); + write32(&emi_reg->ext_lt_con2_3rd, 0xffffffff); + write32(&emi_reg->ext_lt_con3_3rd, 0xffffffff); + write32(&emi_reg->ext_lt_con1_4th, 0x00400266); + write32(&emi_reg->ext_lt_con2_4th, 0xffffffff); + write32(&emi_reg->ext_lt_con3_4th, 0xffffffff); + write32(&emi_reg->prtcl_m0_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m0_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m0_msk, 0xffffffff); + write32(&emi_reg->prtcl_m1_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m1_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m1_msk, 0xffffffff); + write32(&emi_reg->prtcl_m2_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m2_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m2_msk, 0xffffffff); + write32(&emi_reg->prtcl_m3_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m3_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m3_msk, 0xffffffff); + write32(&emi_reg->prtcl_m4_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m4_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m4_msk, 0xffffffff); + write32(&emi_reg->prtcl_m5_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m5_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m5_msk, 0xffffffff); + write32(&emi_reg->prtcl_m6_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m6_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m6_msk, 0xffffffff); + write32(&emi_reg->prtcl_m7_cyc, 0xffffffff); + write32(&emi_reg->prtcl_m7_ctl, 0x001ffc85); + write32(&emi_reg->prtcl_m7_msk, 0xffffffff); + write32(&emi_reg->dvfs_shf_con, 0x00000000); + write32(&emi_reg->mxto0, 0x60606060); + write32(&emi_reg->mxto1, 0x60606060); + write32(&emi_reg->conk, 0x00000000); + write32(&emi_reg->thro_slv_con0, 0x08ffbbff); + write32(&emi_reg->thro_slv_con1, 0xffff5b3c); + write32(&emi_reg->bwlmte_8th, 0xffff00ff); + write32(&emi_reg->bwlmtf_8th, 0x00ffffff); + write32(&emi_reg->bwlmtg_8th, 0xffff00ff); + write32(&emi_reg->bwlmth_8th, 0x00ffffff); + write32(&emi_reg->bwlmtg_7th, 0x00000000); + write32(&emi_reg->chn_hash0, 0xC0000000); +} + +static void emi_chn_config(void) +{ + struct emi_chn_regs *emi_chn = &ch->emi_chn; + + /* set EMI channel default settings which EMI hardware needs */ + write32(&emi_chn->cona, 0x0400f051); + write32(&emi_chn->conb, 0x00ff6048); + write32(&emi_chn->conc, 0x00000004); + write32(&emi_chn->mdct, 0x99f08c03); + write32(&emi_chn->shf0, 0x9a508c17); + write32(&emi_chn->testb, 0x00038137); + write32(&emi_chn->testc, 0x38460002); + write32(&emi_chn->testd, 0x00000000); + write32(&emi_chn->ap_early_cke, 0x000002ff); + write32(&emi_chn->dqfr, 0x00003111); + write32(&emi_chn->arbi, 0x22607188); + write32(&emi_chn->arbi_2nd, 0x22607188); + write32(&emi_chn->arbj, 0x3719595e); + write32(&emi_chn->arbj_2nd, 0x2719595e); + write32(&emi_chn->arbk, 0x64f3ff79); + write32(&emi_chn->arbk_2nd, 0x64f3ff79); + write32(&emi_chn->slct, 0x011b0868); + write32(&emi_chn->arb_rff, 0xa7414222); + write32(&emi_chn->drs_mon0, 0x0000f801); + write32(&emi_chn->drs_mon1, 0x40000000); + write32(&emi_chn->rkarb0, 0x000c802f); + write32(&emi_chn->rkarb1, 0xbd3f3f7e); + write32(&emi_chn->rkarb2, 0x7e003d7e); + write32(&emi_chn->eco3, 0x00000000); + write32(&emi_chn->md_pre_mask, 0xaa0148ff); + write32(&emi_chn->md_pre_mask_shf, 0xaa6168ff); + write32(&emi_chn->md_pre_mask_shf0, 0xaa516cff); + write32(&emi_chn->md_pre_mask_shf1, 0xaa0140ff); + write32(&emi_chn->qos_mdr_shf0, 0x9f658633); +} + +static void emi_init(void) +{ + dramc_set_broadcast(DRAMC_BROADCAST_ON); + emi_center_config(); + emi_chn_config(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); +} + +void emi_mdl_init(const struct emi_mdl *emi_con) +{ + emi_init(); + + write32(&emi_reg->cona, emi_con->cona_val); + write32(&emi_reg->conf, emi_con->conf_val); + write32(&emi_reg->conh, emi_con->conh_val); + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) + write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val); +} + +u32 get_column_num(void) +{ + u32 ma_type = read32(&emi_reg->cona); + u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1; + u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1; + + ma_type = MIN(ma_type_r0, ma_type_r1); + + return ma_type; +} + +static void emi_sw_setting(void) +{ + setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); + setbits32(&emi_mpu->mpu_ctrl_d[7], BIT(4)); + + /* set EMI default bandwidth threshold */ + write32(&emi_reg->bwct0, 0x05008305); + write32(&emi_reg->bwct0_6th, 0x08ff8705); + write32(&emi_reg->bwct0_3rd, 0x0dff8a05); + setbits32(&emi_reg->thro_ctrl1, 0x3 << 8); +} + +static void dramc_dcm_setting(void) +{ + /* set EMI dcm default settgings */ + write32(&infra_ao_mem->emi_idle_bit_en_0, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_idle_bit_en_1, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_idle_bit_en_2, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_idle_bit_en_3, 0xFFFFFFFF); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_0, 0x01F00000); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_1, 0xC0040180); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_2, 0x00000000); + write32(&infra_ao_mem->emi_m0m1_idle_bit_en_3, 0x00000003); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_0, 0x0C000000); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_1, 0x00C00000); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_2, 0x01F08000); + write32(&infra_ao_mem->emi_m2m5_idle_bit_en_3, 0x00000000); + write32(&infra_ao_mem->emi_m3_idle_bit_en_0, 0x20003040); + write32(&infra_ao_mem->emi_m3_idle_bit_en_1, 0x00000000); + write32(&infra_ao_mem->emi_m3_idle_bit_en_2, 0x00001000); + write32(&infra_ao_mem->emi_m3_idle_bit_en_3, 0x00000000); + write32(&infra_ao_mem->emi_m4_idle_bit_en_0, 0x10020F20); + write32(&infra_ao_mem->emi_m4_idle_bit_en_1, 0x00019000); + write32(&infra_ao_mem->emi_m4_idle_bit_en_2, 0x040A0818); + write32(&infra_ao_mem->emi_m4_idle_bit_en_3, 0x00000370); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_0, 0xC001C080); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_1, 0x33000E01); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_2, 0x180067E1); + write32(&infra_ao_mem->emi_m6m7_idle_bit_en_3, 0x000C008C); + write32(&infra_ao_mem->emi_sram_idle_bit_en_0, 0x020C0008); + write32(&infra_ao_mem->emi_sram_idle_bit_en_1, 0x0C00007E); + write32(&infra_ao_mem->emi_sram_idle_bit_en_2, 0x80050006); + write32(&infra_ao_mem->emi_sram_idle_bit_en_3, 0x00030000); + + write32(&infra_ao_mem->emi_dcm_cfg0, 0x0000000F); + write32(&infra_ao_mem->emi_dcm_cfg1, 0x00000000); + write32(&infra_ao_mem->emi_dcm_cfg2, 0x001F0044); + write32(&infra_ao_mem->top_ck_anchor_cfg, 0x200000FF); + + setbits32(&mt8192_infracfg->mem_dcm_ctrl, BIT(27)); +} + +static void dramc_dcm_setting2(void) +{ + u32 emi_temp_data; + + write32(&infra_ao_mem->emi_disph_cfg, 0x00000007); + write32(&infra_ao_mem->emi_disph_cfg, 0x80000007); + + emi_temp_data = read32(&infra_ao_mem->emi_disph_cfg); + emi_temp_data = emi_temp_data & 0xf; + setbits32(&emi_reg->chn_hash0, emi_temp_data); +} + +void emi_init2(void) +{ + u32 tmp; + u32 bc_bak; + struct emi_chn_regs *emi_chn = &ch->emi_chn; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + setbits32(&emi_chn->conc, 0x1); + setbits32(&emi_reg->conm, BIT(10)); + setbits32(&emi_mpu->mpu_ctrl, BIT(4)); + + clrbits32(&emi_chn->rkarb0, 0x1); + tmp = read32(&emi_chn->cona) & 0x1; + setbits32(&emi_chn->rkarb0, tmp); + + dramc_dcm_setting(); + + /* do basic memory read/write for adjusting EMI HW settings */ + write32((void *)_dram, read32((void *)_dram)); + write32((void *)(_dram + 0x100), read32((void *)(_dram + 0x100))); + write32((void *)(_dram + 0x200), read32((void *)(_dram + 0x200))); + write32((void *)(_dram + 0x300), read32((void *)(_dram + 0x300))); + + setbits32(&emi_reg->conn, BIT(22)); + setbits32(&emi_chn->testc, BIT(2)); + + dramc_dcm_setting2(); + + setbits32(&emi_reg->conn, BIT(21)); + setbits32(&emi_chn->testc, BIT(4)); + write32(&emi_chn->ebg_con, 0x40); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + emi_sw_setting(); + dramc_set_broadcast(bc_bak); +} size_t sdram_size(void) { diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 7660bccac15..3a07802f8d9 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -20,6 +20,8 @@ enum { INFRACFG_AO_MEM_BASE = IO_PHYS + 0x00002000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, + RC_BASE = IO_PHYS + 0x00006500, + RC_STATUS_BASE = IO_PHYS + 0x00006E00, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, @@ -28,6 +30,11 @@ enum { PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + DEVAPC_PERI_AO_BASE = IO_PHYS + 0x00034000, + DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000, + DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, + DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, I2C_DMA_BASE = IO_PHYS + 0x00217080, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, diff --git a/src/soc/mediatek/mt8192/include/soc/clkbuf.h b/src/soc/mediatek/mt8192/include/soc/clkbuf.h new file mode 100644 index 00000000000..b5fa3a3f1b6 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/clkbuf.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_CLKBUF_H +#define SOC_MEDIATEK_MT8192_CLKBUF_H + +#include + +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW08 = 0x079C, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW09_CLR = 0x07A2, + PMIC_RG_DCXO_CW10 = 0x07A4, + PMIC_RG_DCXO_CW12 = 0x07A8, + PMIC_RG_DCXO_CW13 = 0x07AA, + PMIC_RG_DCXO_CW15 = 0x07AE, + PMIC_RG_DCXO_CW19 = 0x07B6, +}; + +enum { + PMIC_TOP_TMA_KEY = 0x3A8, + PMIC_RG_TOP_SPI_CON1 = 0x458, +}; + +enum { + PMIC_TOP_TMA_KEY_UNLOCK = 0x9CA6, +}; + +enum { + PMIC_RG_LDO_VRFCK_ELR = 0x1B40, + PMIC_RG_LDO_VRFCK_CON0 = 0x1D1C, + PMIC_RG_LDO_VRFCK_OP_EN = 0x1D22, + PMIC_RG_LDO_VRFCK_OP_EN_SET = 0x1D24, + PMIC_RG_LDO_VBBCK_CON0 = 0x1D2E, + PMIC_RG_LDO_VBBCK_OP_EN = 0x1D34, + PMIC_RG_LDO_VBBCK_OP_EN_SET = 0x1D36, +}; + +enum { + PMIC_RG_DCXO_ADLDO_BIAS_ELR_0 = 0x209C, + PMIC_RG_DCXO_ADLDO_BIAS_ELR_1 = 0x209E, +}; + +enum { + PMIC_RG_XO_BUF_CTL0 = 0x54C, + PMIC_RG_XO_BUF_CTL1 = 0x54E, + PMIC_RG_XO_BUF_CTL2 = 0x550, + PMIC_RG_XO_BUF_CTL3 = 0x552, + PMIC_RG_XO_BUF_CTL4 = 0x554, + PMIC_RG_XO_CONN_BT0 = 0x556, +}; + +DEFINE_BITFIELD(PMIC_REG_COMMON, 15, 0) +DEFINE_BIT(PMIC_RG_VRFCK_HV_EN, 9) +DEFINE_BIT(PMIC_RG_LDO_VRFCK_EN, 0) +DEFINE_BIT(PMIC_RG_LDO_VRFCK_ANA_SEL, 0) +DEFINE_BIT(PMIC_RG_LDO_VBBCK_EN, 0) +DEFINE_BIT(PMIC_RG_VRFCK_NDIS_EN, 11) +DEFINE_BIT(PMIC_RG_VRFCK_1_NDIS_EN, 0) +DEFINE_BIT(PMIC_RG_LDO_VRFCK_HW14_OP_EN, 14) +DEFINE_BIT(PMIC_RG_LDO_VBBCK_HW14_OP_EN, 14) +DEFINE_BIT(PMIC_RG_SRCLKEN_IN3_EN, 0) +DEFINE_BIT(PMIC_RG_XO_PMIC_TOP_DIG_SW, 2) +DEFINE_BITFIELD(PMIC_RG_XO_VOTE, 10, 0) + +int clk_buf_init(void); + +#endif /* SOC_MEDIATEK_MT8192_CLKBUF_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h new file mode 100644 index 00000000000..f227aaadd3d --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_DEVAPC_H +#define SOC_MEDIATEK_MT8192_DEVAPC_H + +#include +#include + +void dapc_init(void); + +#define DEVAPC_AO_MAX 6 + +enum devapc_ao_offset { + MAS_DOM_0 = 0x0900, + MAS_DOM_1 = 0x0904, + MAS_SEC_0 = 0x0A00, + AO_APC_CON = 0x0F00, +}; + +/* INFRA */ +DEFINE_BIT(SCP_SSPM_SEC, 3) +DEFINE_BIT(CPU_EB_SEC, 4) + +DEFINE_BITFIELD(PCIE_DOM, 19, 16) /* 2 */ +DEFINE_BITFIELD(SCP_SSPM_DOM, 3, 0) /* 4 */ +DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 5 */ + +/* PERI */ +DEFINE_BITFIELD(SPM_DOM, 3, 0) /* 0 */ + +enum master_domain { + MAS_DOMAIN_0 = 0, + MAS_DOMAIN_1, + MAS_DOMAIN_2, + MAS_DOMAIN_3, + MAS_DOMAIN_4, + MAS_DOMAIN_5, + MAS_DOMAIN_6, + MAS_DOMAIN_7, + MAS_DOMAIN_8, + MAS_DOMAIN_9, + MAS_DOMAIN_10, + MAS_DOMAIN_11, + MAS_DOMAIN_12, + MAS_DOMAIN_13, + MAS_DOMAIN_14, + MAS_DOMAIN_15, + MAS_DOMAIN_MAX, +}; + + +#endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h new file mode 100644 index 00000000000..f00101a3a99 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h @@ -0,0 +1,972 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ + +#include +#include +#include +#include + +/* Normal Mode and Byte Mode */ +#define AC_TIMING_NUMBER (DDRFREQ_MAX * 2) + +struct ac_timing { + u8 cbt_mode, read_dbi; + u8 div_mode; + u16 freq_group; + u16 read_lat, write_lat; + u16 dqsinctl, datlat; + u16 tras; + u16 trp; + u16 trpab; + u16 trc; + u16 trfc; + u16 trfcpb; + u16 txp; + u16 trtp; + u16 trcd; + u16 twr; + u16 twtr; + u16 tpbr2pbr; + u16 tpbr2act; + u16 tr2mrw; + u16 tw2mrw; + u16 tmrr2mrw; + u16 tmrw; + u16 tmrd; + u16 tmrwckel; + u16 tpde; + u16 tpdx; + u16 tmrri; + u16 trrd; + u16 trrd_4266; + u16 tfaw; + u16 tfaw_4266; + u16 trtw_odt_off; + u16 trtw_odt_on; + u16 txrefcnt; + u16 tzqcs; + u16 xrtw2w_new_mode; + u16 xrtw2w_old_mode; + u16 xrtw2r_odt_on; + u16 xrtw2r_odt_off; + u16 xrtr2w_odt_on; + u16 xrtr2w_odt_off; + u16 xrtr2r_new_mode; + u16 xrtr2r_old_mode; + u16 tr2mrr; + u16 vrcgdis_prdcnt; + u16 hwset_mr2_op; + u16 hwset_mr13_op; + u16 hwset_vrcg_op; + u16 trcd_derate; + u16 trc_derate; + u16 tras_derate; + u16 trpab_derate; + u16 trp_derate; + u16 trrd_derate; + u16 trtpd; + u16 twtpd; + u16 tmrr2w_odt_off; + u16 tmrr2w_odt_on; + u16 ckeprd; + u16 ckelckcnt; + u16 zqlat2; + u16 tras_05T; + u16 trp_05T; + u16 trpab_05T; + u16 trc_05T; + u16 trfc_05T; + u16 trfcpb_05T; + u16 txp_05T; + u16 trtp_05T; + u16 trcd_05T; + u16 twr_05T; + u16 twtr_05T; + u16 tpbr2pbr_05T; + u16 tpbr2act_05T; + u16 tr2mrw_05T; + u16 tw2mrw_05T; + u16 tmrr2mrw_05T; + u16 tmrw_05T; + u16 tmrd_05T; + u16 tmrwckel_05T; + u16 tpde_05T; + u16 tpdx_05T; + u16 tmrri_05T; + u16 trrd_05T; + u16 trrd_4266_05T; + u16 tfaw_05T; + u16 tfaw_4266_05T; + u16 trtw_odt_off_05T; + u16 trtw_odt_on_05T; + u16 trcd_derate_05T; + u16 trc_derate_05T; + u16 tras_derate_05T; + u16 trpab_derate_05T; + u16 trp_derate_05T; + u16 trrd_derate_05T; + u16 trtpd_05T; + u16 twtpd_05T; +}; + +/* Normal Mode and Byte Mode for each frequency */ +static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = { + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 36, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 14, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 40, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 15, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 28, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 1, + .tmrr2w_odt_off = 8, + .tmrr2w_odt_on = 10, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 32, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 6, + .xrtr2w_odt_off = 6, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 24, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 9, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 1, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 26, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 10, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_off = 7, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 20, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 1, + .twtr = 5, .twtr_05T = 1, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 0, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 9, .trtpd_05T = 1, + .twtpd = 10, .twtpd_05T = 1, + .tmrr2w_odt_off = 5, + .tmrr2w_odt_on = 7, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 22, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 0, + .twtr = 5, .twtr_05T = 0, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 1, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 4, + .xrtr2w_odt_off = 4, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 0, + .twtpd = 11, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 0, + .twtr = 4, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 8, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 8, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 4, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, +}; + +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h index a958d0cc15a..2dee0445c31 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -34,6 +34,8 @@ #define REG_SHU_OFFSET_WIDTH 0x700 #define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4) +#define DQS_LEVEL_UNKNOWN 0xff + typedef enum { DDRFREQ_400, DDRFREQ_600, @@ -337,7 +339,7 @@ void ana_clk_div_config(ana_dvfs_core *tr, dvfs_group_config *dfs); void apply_write_dbi_power_improve(bool onoff); void dramc_write_dbi_onoff(u8 onoff); void cbt_delay_ca_clk(u8 chn, u8 rank, s32 iDelay); -void dramc_cmd_UI_delay_setting(u8 chn, u8 value); +void dramc_cmd_ui_delay_setting(u8 chn, u8 value); void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali *cali, u16 *osc_thrd_inc, u16 *osc_thrd_dec); void dqsosc_shu_settings(const struct ddr_cali *cali, diff --git a/src/soc/mediatek/mt8192/include/soc/eint_event.h b/src/soc/mediatek/mt8192/include/soc/eint_event.h new file mode 100644 index 00000000000..05d1fbcb0c8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/eint_event.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_EINT_EVENT_H +#define SOC_MEDIATEK_MT8192_EINT_EVENT_H + +#include +#include + +/* eint event mask cler register */ +struct eint_event_reg { + uint32_t eint_event_mask_clr[7]; +}; + +/* eint_base + 0x880 is eint_event_mask_clr register with access type W1C. */ +static struct eint_event_reg *const mtk_eint_event = (void *)(EINT_BASE + 0x880); + +/* unmask eint event, eint can wakeup by spm */ +void unmask_eint_event_mask(void); + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h index b90e0f55edb..5519cc23833 100644 --- a/src/soc/mediatek/mt8192/include/soc/mt6359p.h +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -8,14 +8,23 @@ enum { PMIC_HWCID = 0x0008, PMIC_SWCID = 0x000a, + PMIC_TOP_CKPDN_CON0 = 0x010c, + PMIC_TOP_CKHWEN_CON0 = 0x012a, PMIC_TOP_RST_MISC_SET = 0x014c, PMIC_TOP_RST_MISC_CLR = 0x014e, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_PWRHOLD = 0x0a08, PMIC_VGPU11_DBG0 = 0x15a6, PMIC_VGPU11_ELR0 = 0x15b4, PMIC_VS2_VOTER = 0x18aa, PMIC_VS2_VOTER_CFG = 0x18b0, PMIC_VS2_ELR0 = 0x18b4, + PMIC_BUCK_VPA_DLC_CON0 = 0x1918, + PMIC_BUCK_VPA_DLC_CON1 = 0x191a, PMIC_VSRAM_PROC1_ELR = 0x1b44, PMIC_VSRAM_PROC2_ELR = 0x1b46, PMIC_VSRAM_PROC1_VOSEL1 = 0x1e90, @@ -30,6 +39,13 @@ struct pmic_setting { unsigned char shift; }; +struct pmic_efuse { + unsigned short efuse_bit; + unsigned short addr; + unsigned short mask; + unsigned char shift; +}; + enum { MT6359P_GPU11 = 0, MT6359P_SRAM_PROC1, @@ -40,6 +56,11 @@ enum { #define VM18_VOL_REG_SHIFT 8 #define VM18_VOL_OFFSET 600 +#define EFUSE_WAIT_US 5000 +#define EFUSE_BUSY 1 + +#define EFUSE_RG_VPA_OC_FT 78 + void mt6359p_init(void); void mt6359p_romstage_init(void); void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv); diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 52bf3c2f38f..cd1c01250cf 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -241,6 +241,8 @@ check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200); check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc); +#define MPLL_CON1_FREQ 0x84200000 + enum { USBPLL_EN = 0x1 << 2, @@ -306,6 +308,12 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BIT(MPLL_IOS_SEL, 2) +DEFINE_BIT(MPLL_EN_SEL, 11) +DEFINE_BIT(MPLL_PWR_SEL, 20) +DEFINE_BIT(MPLL_BY_ISO_DLY, 2) +DEFINE_BIT(MPLL_BY_PWR_DLY, 2) + DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h index fe3def020ac..cfc7fe5f1ec 100644 --- a/src/soc/mediatek/mt8192/include/soc/pmif.h +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -3,6 +3,7 @@ #ifndef __MT8192_SOC_PMIF_H__ #define __MT8192_SOC_PMIF_H__ +#include #include enum { @@ -167,6 +168,36 @@ enum { E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ }; +enum pmic_interface { + PMIF_VLD_RDY = 0, + PMIF_SLP_REQ, +}; + +DEFINE_BIT(PMIFSPI_INF_EN_SRCLKEN_RC_HW, 4) + +DEFINE_BIT(PMIFSPI_OTHER_INF_DXCO0_EN, 0) +DEFINE_BIT(PMIFSPI_OTHER_INF_DXCO1_EN, 1) + +DEFINE_BIT(PMIFSPI_ARB_EN_SRCLKEN_RC_HW, 4) +DEFINE_BIT(PMIFSPI_ARB_EN_DCXO_CONN, 15) +DEFINE_BIT(PMIFSPI_ARB_EN_DCXO_NFC, 16) + +DEFINE_BITFIELD(PMIFSPI_SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(PMIFSPI_SCP_SLEEP_REQ_SEL, 10, 9) + +DEFINE_BIT(PMIFSPI_MD_CTL_PMIF_RDY, 9) +DEFINE_BIT(PMIFSPI_MD_CTL_SRCLK_EN, 10) +DEFINE_BIT(PMIFSPI_MD_CTL_SRVOL_EN, 11) + +DEFINE_BITFIELD(PMIFSPMI_SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(PMIFSPMI_SCP_SLEEP_REQ_SEL, 10, 9) + +DEFINE_BIT(PMIFSPMI_MD_CTL_PMIF_RDY, 9) +DEFINE_BIT(PMIFSPMI_MD_CTL_SRCLK_EN, 10) +DEFINE_BIT(PMIFSPMI_MD_CTL_SRVOL_EN, 11) + +/* External API */ extern struct pmif *get_pmif_controller(int inf, int mstid); +extern void pmwrap_interface_init(void); extern int mtk_pmif_init(void); #endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h new file mode 100644 index 00000000000..46c06f4a52b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_RTC_H +#define SOC_MEDIATEK_MT8192_RTC_H + +#include +#include + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E, +}; + +enum { + RTC_TC_SEC = 0x0592, + RTC_TC_MIN = 0x0594, + RTC_TC_HOU = 0x0596, + RTC_TC_DOM = 0x0598, + RTC_TC_DOW = 0x059A, + RTC_TC_MTH = 0x059C, + RTC_TC_YEA = 0x059E, +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590, +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2, +}; + +enum { + RTC_POWERKEY1 = 0x05B0, + RTC_POWERKEY2 = 0x05B2, +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0, +}; + +enum { + RTC_BBPU_ENABLE_ALARM = 1U << 0, + RTC_BBPU_SPAR_SW = 1U << 1, + RTC_BBPU_RESET_SPAR = 1U << 2, + RTC_BBPU_RESET_ALARM = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + RTC_CBUSY_TIMEOUT_US = 1000000, +}; + +enum { + RTC_CON_VBAT_LPSTA_RAW = 1U << 0, + RTC_CON_EOSC32_LPEN = 1U << 1, + RTC_CON_XOSC32_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15, +}; + +enum { + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_EOSC32_VCT_EN = 1U << 11, + RTC_EOSC32_CHOP_EN = 1U << 12, + RTC_GP_OSC32_CON = 2U << 13, + RTC_REG_XOSC32_ENB = 1U << 15, +}; + +enum { + OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | + RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION | + RTC_EMB_K_EOSC32_MODE, +}; + +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_SCK_TOP_CON0 = 0x050C, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C, +}; + +enum { + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, + PMIC_RG_FQMTR_CK_PDN_SHIFT = 11, +}; + +enum { + PMIC_RG_BANK_FQMTR_RST = 0x522, +}; + +enum { + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4, + PMIC_RG_BANK_FQMTR_RST_SHIFT = 6, +}; + +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013A, + PMIC_RG_FQMTR_CON0 = 0x0546, + PMIC_RG_FQMTR_WINSET = 0x0548, + PMIC_RG_FQMTR_DATA = 0x054A, + FQMTR_TIMEOUT_US = 8000, +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_DCXO1M_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_32K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0, +}; + +enum { + PMIC_FQMTR_RST_SHIFT = 8, +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15, +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2, +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f, +}; + +enum { + RTC_TC_MTH_MASK = 0xf, +}; + +enum { + RTC_K_EOSC_RSV_0 = 1 << 8, + RTC_K_EOSC_RSV_1 = 1 << 9, + RTC_K_EOSC_RSV_2 = 1 << 10, +}; + +void rtc_read(u16 addr, u16 *rdata); +void rtc_write(u16 addr, u16 wdata); +void rtc_bbpu_power_on(void); +int rtc_init(int recover); +bool rtc_gpio_init(void); +void rtc_boot(void); +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); +#endif /* SOC_MEDIATEK_MT8192_RTC_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/srclken_rc.h b/src/soc/mediatek/mt8192/include/soc/srclken_rc.h new file mode 100644 index 00000000000..dc0a0760879 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/srclken_rc.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SRCLKEN_RC_H +#define SOC_MEDIATEK_MT8192_SRCLKEN_RC_H + +#include + +struct mtk_rc_regs { + u32 srclken_rc_cfg; + u32 rc_central_cfg1; + u32 rc_central_cfg2; + u32 rc_cmd_arb_cfg; + u32 rc_pmic_rcen_addr; + u32 rc_pmic_rcen_set_clr_addr; + u32 rc_dcxo_fpm_cfg; + u32 rc_central_cfg3; + u32 rc_mxx_srclken_cfg[13]; + u32 srclken_sw_con_cfg; + u32 rc_central_cfg4; + u32 reserved1; + u32 rc_protocol_chk_cfg; + u32 rc_debug_cfg; + u32 reserved2[19]; + u32 rc_misc_0; + u32 rc_spm_ctrl; + u32 rc_subsys_intf_cfg; +}; + +check_member(mtk_rc_regs, rc_central_cfg1, 0x4); +check_member(mtk_rc_regs, rc_mxx_srclken_cfg[0], 0x20); +check_member(mtk_rc_regs, rc_mxx_srclken_cfg[12], 0x50); +check_member(mtk_rc_regs, rc_central_cfg4, 0x58); +check_member(mtk_rc_regs, rc_protocol_chk_cfg, 0x60); +check_member(mtk_rc_regs, rc_misc_0, 0xb4); +check_member(mtk_rc_regs, rc_subsys_intf_cfg, 0xbc); + +struct mtk_rc_status_regs { + u32 rc_fsm_sta_0; + u32 rc_cmd_sta_0; + u32 rc_cmd_sta_1; + u32 rc_spi_sta_0; + u32 rc_pi_po_sta_0; + u32 rc_mxx_req_sta_0[14]; + u32 reserved2[2]; + u32 rc_debug_trace; +}; + +check_member(mtk_rc_status_regs, rc_cmd_sta_1, 0x8); +check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[0], 0x14); +check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[13], 0x48); +check_member(mtk_rc_status_regs, rc_debug_trace, 0x54); + +/* SPM Register */ +/* SRCLKEN_RC_CFG */ +DEFINE_BIT(SW_RESET, 0) +DEFINE_BIT(CG_32K_EN, 1) +DEFINE_BIT(CG_FCLK_EN, 2) +DEFINE_BIT(CG_FCLK_FR_EN, 3) +DEFINE_BIT(MUX_FCLK_FR, 4) + +/* RC_CENTRAL_CFG1 */ +DEFINE_BIT(SRCLKEN_RC_EN, 0) +DEFINE_BIT(RCEN_ISSUE_M, 1) +DEFINE_BIT(RC_SPI_ACTIVE, 2) +DEFINE_BIT(SRCLKEN_RC_EN_SEL, 3) +DEFINE_BITFIELD(VCORE_SETTLE_T, 7, 5) +DEFINE_BITFIELD(ULPOSC_SETTLE_T, 11, 8) +DEFINE_BITFIELD(NON_DCXO_SETTLE_T, 21, 12) +DEFINE_BITFIELD(DCXO_SETTLE_T, 31, 22) + +/* RC_CENTRAL_CFG2 */ +DEFINE_BITFIELD(SRCVOLTEN_CTRL, 3, 0) +DEFINE_BITFIELD(VREQ_CTRL, 7, 4) +DEFINE_BIT(SRCVOLTEN_VREQ_SEL, 8) +DEFINE_BIT(SRCVOLTEN_VREQ_M, 9) +DEFINE_BITFIELD(ULPOSC_CTRL_M, 15, 12) +DEFINE_BITFIELD(PWRAP_SLP_CTRL_M, 24, 21) +DEFINE_BIT(PWRAP_SLP_MUX_SEL, 25) + +/* RC_DCXO_FPM_CFG */ +DEFINE_BITFIELD(DCXO_FPM_CTRL_M, 3, 0) +DEFINE_BIT(SRCVOLTEN_FPM_MSK_B, 4) +DEFINE_BITFIELD(SUB_SRCLKEN_FPM_MSK_B, 28, 16) + +/* RC_CENTRAL_CFG3 */ +DEFINE_BIT(TO_LPM_SETTLE_EN, 0) +DEFINE_BIT(BLK_SCP_DXCO_MD_TARGET, 1) +DEFINE_BIT(BLK_COANT_DXCO_MD_TARGET, 2) +DEFINE_BIT(TO_BBLPM_SETTLE_EN, 3) +DEFINE_BITFIELD(TO_LPM_SETTLE_T, 21, 12) + +/* RC_CENTRAL_CFG4 */ +DEFINE_BITFIELD(KEEP_RC_SPI_ACTIVE, 8, 0) +DEFINE_BIT(PWRAP_VLD_FORCE, 16) +DEFINE_BIT(SLEEP_VLD_MODE, 17) + +/* RC_MXX_SRCLKEN_CFG */ +DEFINE_BIT(DCXO_SETTLE_BLK_EN, 1) +DEFINE_BIT(BYPASS_CMD_EN, 2) +DEFINE_BIT(SW_SRCLKEN_RC, 3) +DEFINE_BIT(SW_SRCLKEN_FPM, 4) +DEFINE_BIT(SW_SRCLKEN_BBLPM, 5) +DEFINE_BIT(XO_SOC_LINK_EN, 6) +DEFINE_BIT(REQ_ACK_LOW_IMD_EN, 7) +DEFINE_BIT(SRCLKEN_TRACK_M_EN, 8) +DEFINE_BITFIELD(CNT_PRD_STEP, 11, 10) +DEFINE_BITFIELD(XO_STABLE_PRD, 21, 12) +DEFINE_BITFIELD(DCXO_STABLE_PRD, 31, 22) + +enum { + SW_SRCLKEN_FPM_MSK = 0x1, + SW_SRCLKEN_BBLPM_MSK = 0x1, +}; + +/* RC_DEBUG_CFG */ +DEFINE_BIT(TRACE_MODE_EN, 24) + +/* SUBSYS_INTF_CFG */ +DEFINE_BITFIELD(SRCLKEN_FPM_MASK_B, 12, 0) +DEFINE_BITFIELD(SRCLKEN_BBLPM_MASK_B, 28, 16) + +enum { + PMIC_PMRC_CON0 = 0x1A6, + PMIC_PMRC_CON0_SET = 0x1A8, + PMIC_PMRC_CON0_CLR = 0x1AA, +}; + +enum chn_id { + CHN_SUSPEND = 0, + CHN_RF = 1, + CHN_DEEPIDLE = 2, + CHN_MD = 3, + CHN_GPS = 4, + CHN_BT = 5, + CHN_WIFI = 6, + CHN_MCU = 7, + CHN_COANT = 8, + CHN_NFC = 9, + CHN_UFS = 10, + CHN_SCP = 11, + CHN_RESERVE = 12, + MAX_CHN_NUM, +}; + +enum { + SRCLKENAO_MODE, + VREQ_MODE, +}; + +enum { + MERGE_OR_MODE = 0x0, + BYPASS_MODE = 0x1, + MERGE_AND_MODE = 0x1 << 1, + BYPASS_RC_MODE = 0x2 << 1, + BYPASS_OTHER_MODE = 0x3 << 1, + ASYNC_MODE = 0x1 << 3, +}; + +enum { + RC_32K = 0, + RC_ULPOSC1, +}; + +enum rc_ctrl_m { + HW_MODE = 0, + SW_MODE = 1, + INIT_MODE = 0xff, +}; + +enum rc_support { + SRCLKEN_RC_ENABLE = 0, + SRCLKEN_RC_DISABLE, +}; + +struct subsys_rc_con { + unsigned int dcxo_prd; + unsigned int xo_prd; + unsigned int cnt_step; + unsigned int track_en; + unsigned int req_ack_imd_en; + unsigned int xo_soc_link_en; + unsigned int sw_bblpm; + unsigned int sw_fpm; + unsigned int sw_rc; + unsigned int bypass_cmd; + unsigned int dcxo_settle_blk_en; +}; + +extern int srclken_rc_init(void); + +#endif /* SOC_MEDIATEK_MT8192_SRCLKEN_RC_H */ diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index a8e93ca7c6b..e9dadc0d749 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -5,6 +5,18 @@ #include #include #include +#include + +static const struct pmic_setting key_protect_setting[] = { + {0x3A8, 0x9CA6, 0xFFFF, 0}, + {0x44A, 0xBADE, 0xFFFF, 0}, + {0xA3A, 0x4729, 0xFFFF, 0}, + {0xC58, 0x1605, 0xFFFF, 0}, + {0xC5A, 0x1706, 0xFFFF, 0}, + {0xC5C, 0x1807, 0xFFFF, 0}, + {0xFB4, 0x6359, 0xFFFF, 0}, + {0x1432, 0x5543, 0xFFFF, 0}, +}; static const struct pmic_setting init_setting[] = { {0x20, 0xA, 0xA, 0}, @@ -27,7 +39,11 @@ static const struct pmic_setting init_setting[] = { {0xA08, 0x1, 0x1, 0}, {0xA0C, 0x300, 0x300, 0}, {0xA10, 0x0, 0x4000, 0}, - {0xA12, 0x1E0, 0x1E0, 0}, + /* + * RG_STRUP_LONG_PRESS_EXT_SEL + * only allow pwrkey boot after long-press shutdown. + */ + {0xA12, 0x1F2, 0x1F3, 0}, {0xA24, 0xFFFF, 0xFFFF, 0}, {0xA26, 0xFFE0, 0xFFE0, 0}, {0xA2C, 0xC0DF, 0xC0DF, 0}, @@ -90,6 +106,7 @@ static const struct pmic_setting init_setting[] = { {0x19AE, 0x6E, 0x7E, 0}, {0x19B0, 0x3C00, 0x3C00, 0}, {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x19DE, 0x1, 0x1, 6}, /* RG_VGPUVCORE_PH2_OFF, disable phase 2 */ {0x1A08, 0x4200, 0x4680, 0}, {0x1A0A, 0x6E, 0x7E, 0}, {0x1A0C, 0x3C00, 0x3C00, 0}, @@ -165,6 +182,13 @@ static const struct pmic_setting init_setting[] = { {0x202C, 0x8, 0xC, 0}, {0x208C, 0x100, 0xF00, 0}, {0x209C, 0x80, 0x1E0, 0}, + /* + * BUCK_VGPU11_OP_MODE/CFG/EN + * Vreq setting for scp usage + */ + {0x15a0, 0x0, 0x1, 11}, + {0x159a, 0x0, 0x1, 11}, + {0x1594, 0x1, 0x1, 11}, }; static const struct pmic_setting lp_setting[] = { @@ -275,6 +299,32 @@ static const struct pmic_setting lp_setting[] = { {0x1d14, 0x1, 0x1, 0x2}, }; +static const struct pmic_efuse efuse_setting[] = { + {79, 0xa0e, 0x1, 0xf}, + {886, 0x198c, 0xf, 0x8}, + {890, 0x198e, 0xf, 0x0}, + {902, 0x1998, 0xf, 0x8}, + {906, 0x1998, 0xf, 0xc}, + {918, 0x19a2, 0xf, 0x8}, + {922, 0x19a2, 0xf, 0xc}, + {1014, 0x19ae, 0xf, 0x7}, + {1018, 0x19ae, 0xf, 0xb}, + {1158, 0x1a0a, 0xf, 0x7}, + {1162, 0x1a0a, 0xf, 0xb}, + {1206, 0x1a16, 0xf, 0x7}, + {1210, 0x1a16, 0xf, 0xb}, + {1254, 0x1a22, 0xf, 0x7}, + {1258, 0x1a22, 0xf, 0xb}, + {1304, 0x1a2c, 0x7, 0x4}, + {1307, 0x1a32, 0x7, 0x8}, + {1336, 0x1a34, 0x7, 0x4}, + {1339, 0x1a3a, 0x7, 0x8}, + {1683, 0x79c, 0xf, 0x4}, + {1688, 0xc8a, 0x1, 0x3}, + {1689, 0xc88, 0x1, 0x3}, + {1690, 0xc88, 0x7, 0x0}, +}; + static struct pmif *pmif_arb = NULL; static void mt6359p_write(u32 reg, u32 data) { @@ -306,6 +356,52 @@ static void pmic_wdt_set(void) mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0); } +static void pmic_protect_key_setting(bool lock) +{ + for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) + mt6359p_write(key_protect_setting[i].addr, + lock ? 0 : key_protect_setting[i].val); +} + +static int check_idle(u32 timeout, u32 addr, u32 mask) +{ + if (!wait_us(timeout, !mt6359p_read_field(addr, mask, 0))) + return -1; + + return 0; +} + +static u32 pmic_read_efuse(u32 efuse_bit, u32 mask) +{ + u32 efuse_data; + int index, shift; + + index = efuse_bit / 16; + shift = efuse_bit % 16; + mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 0, 0x1, 2); + mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 0, 0x1, 4); + mt6359p_write_field(PMIC_OTP_CON11, 1, 0x1, 0); + mt6359p_write_field(PMIC_OTP_CON0, index * 2, 0xFF, 0); + if (mt6359p_read_field(PMIC_OTP_CON8, 1, 0)) + mt6359p_write_field(PMIC_OTP_CON8, 0, 1, 0); + else + mt6359p_write_field(PMIC_OTP_CON8, 1, 1, 0); + + udelay(300); + if (check_idle(EFUSE_WAIT_US, PMIC_OTP_CON13, EFUSE_BUSY)) + die("[%s] timeout after %d usecs\n", __func__, EFUSE_WAIT_US); + + udelay(100); + + efuse_data = mt6359p_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + efuse_data = (efuse_data >> shift) & mask; + + mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 1, 0x1, 2); + mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 1, 0x1, 4); + + return efuse_data; +} + static void pmic_init_setting(void) { for (int i = 0; i < ARRAY_SIZE(init_setting); i++) @@ -320,6 +416,30 @@ static void pmic_lp_setting(void) lp_setting[i].mask, lp_setting[i].shift); } +static void pmic_efuse_setting(void) +{ + u32 efuse_data; + struct stopwatch sw; + + stopwatch_init(&sw); + + for (int i = 0; i < ARRAY_SIZE(efuse_setting); i++) { + efuse_data = pmic_read_efuse(efuse_setting[i].efuse_bit, efuse_setting[i].mask); + mt6359p_write_field(efuse_setting[i].addr, efuse_data, + efuse_setting[i].mask, efuse_setting[i].shift); + } + + efuse_data = pmic_read_efuse(EFUSE_RG_VPA_OC_FT, 0x1); + if (efuse_data) { + /* restore VPA_DLC initial setting */ + mt6359p_write(PMIC_BUCK_VPA_DLC_CON0, 0x2810); + mt6359p_write(PMIC_BUCK_VPA_DLC_CON1, 0x800); + } + + printk(BIOS_DEBUG, "%s: Set efuses in %ld msecs\n", + __func__, stopwatch_duration_msecs(&sw)); +} + static void pmic_wk_vs2_voter_setting(void) { /* @@ -437,8 +557,11 @@ void mt6359p_init(void) init_pmif_arb(); pmic_set_power_hold(); pmic_wdt_set(); + pmic_protect_key_setting(false); pmic_init_setting(); pmic_lp_setting(); + pmic_efuse_setting(); + pmic_protect_key_setting(true); pmic_wk_vs2_voter_setting(); } diff --git a/src/soc/mediatek/mt8192/pmif.c b/src/soc/mediatek/mt8192/pmif.c index f6b15259159..57fc9d4a3f2 100644 --- a/src/soc/mediatek/mt8192/pmif.c +++ b/src/soc/mediatek/mt8192/pmif.c @@ -177,6 +177,120 @@ struct pmif *get_pmif_controller(int inf, int mstid) return NULL; } +static void pmif_select(enum pmic_interface mode) +{ + unsigned int spi_spm_sleep_req, spi_scp_sleep_req, + spmi_spm_sleep_req, spmi_scp_sleep_req, + spi_md_ctl_pmif_rdy, spi_md_ctl_srclk_en, spi_md_ctl_srvol_en, + spmi_md_ctl_pmif_rdy, spmi_md_ctl_srclk_en, spmi_md_ctl_srvol_en, + spi_inf_srclken_rc_en, spi_other_inf_dcxo0_en, spi_other_inf_dcxo1_en, + spi_arb_srclken_rc_en, spi_arb_dcxo_conn_en, spi_arb_dcxo_nfc_en; + + switch (mode) { + case PMIF_VLD_RDY: + /* spm and scp sleep request disable spi and spmi */ + spi_spm_sleep_req = 1; + spi_scp_sleep_req = 1; + spmi_spm_sleep_req = 1; + spmi_scp_sleep_req = 1; + + /* + * pmic vld/rdy control spi mode enable + * srclken control spi mode disable + * vreq control spi mode disable + */ + spi_md_ctl_pmif_rdy = 1; + spi_md_ctl_srclk_en = 0; + spi_md_ctl_srvol_en = 0; + spmi_md_ctl_pmif_rdy = 1; + spmi_md_ctl_srclk_en = 0; + spmi_md_ctl_srvol_en = 0; + + /* srclken rc interface enable */ + spi_inf_srclken_rc_en = 1; + + /* dcxo interface disable */ + spi_other_inf_dcxo0_en = 0; + spi_other_inf_dcxo1_en = 0; + + /* srclken enable, dcxo0,1 disable */ + spi_arb_srclken_rc_en = 1; + spi_arb_dcxo_conn_en = 0; + spi_arb_dcxo_nfc_en = 0; + break; + + case PMIF_SLP_REQ: + /* spm and scp sleep request enable spi and spmi */ + spi_spm_sleep_req = 0; + spi_scp_sleep_req = 0; + spmi_spm_sleep_req = 0; + spmi_scp_sleep_req = 0; + + /* + * pmic vld/rdy control spi mode disable + * srclken control spi mode enable + * vreq control spi mode enable + */ + spi_md_ctl_pmif_rdy = 0; + spi_md_ctl_srclk_en = 1; + spi_md_ctl_srvol_en = 1; + spmi_md_ctl_pmif_rdy = 0; + spmi_md_ctl_srclk_en = 1; + spmi_md_ctl_srvol_en = 1; + + /* srclken rc interface disable */ + spi_inf_srclken_rc_en = 0; + + /* dcxo interface enable */ + spi_other_inf_dcxo0_en = 1; + spi_other_inf_dcxo1_en = 1; + + /* srclken disable, dcxo0,1 enable */ + spi_arb_srclken_rc_en = 0; + spi_arb_dcxo_conn_en = 1; + spi_arb_dcxo_nfc_en = 1; + break; + + default: + die("Can't support pmif mode %d\n", mode); + } + + SET32_BITFIELDS(&pmif_spi_arb[0].mtk_pmif->sleep_protection_ctrl, + PMIFSPI_SPM_SLEEP_REQ_SEL, spi_spm_sleep_req, + PMIFSPI_SCP_SLEEP_REQ_SEL, spi_scp_sleep_req); + SET32_BITFIELDS(&pmif_spmi_arb[0].mtk_pmif->sleep_protection_ctrl, + PMIFSPMI_SPM_SLEEP_REQ_SEL, spmi_spm_sleep_req, + PMIFSPMI_SCP_SLEEP_REQ_SEL, spmi_scp_sleep_req); + SET32_BITFIELDS(&pmif_spi_arb[0].mtk_pmif->spi_mode_ctrl, + PMIFSPI_MD_CTL_PMIF_RDY, spi_md_ctl_pmif_rdy, + PMIFSPI_MD_CTL_SRCLK_EN, spi_md_ctl_srclk_en, + PMIFSPI_MD_CTL_SRVOL_EN, spi_md_ctl_srvol_en); + SET32_BITFIELDS(&pmif_spmi_arb[0].mtk_pmif->spi_mode_ctrl, + PMIFSPMI_MD_CTL_PMIF_RDY, spmi_md_ctl_pmif_rdy, + PMIFSPMI_MD_CTL_SRCLK_EN, spmi_md_ctl_srclk_en, + PMIFSPMI_MD_CTL_SRVOL_EN, spmi_md_ctl_srvol_en); + SET32_BITFIELDS(&pmif_spi_arb[0].mtk_pmif->inf_en, + PMIFSPI_INF_EN_SRCLKEN_RC_HW, spi_inf_srclken_rc_en); + SET32_BITFIELDS(&pmif_spi_arb[0].mtk_pmif->other_inf_en, + PMIFSPI_OTHER_INF_DXCO0_EN, spi_other_inf_dcxo0_en, + PMIFSPI_OTHER_INF_DXCO1_EN, spi_other_inf_dcxo1_en); + SET32_BITFIELDS(&pmif_spi_arb[0].mtk_pmif->arb_en, + PMIFSPI_ARB_EN_SRCLKEN_RC_HW, spi_arb_srclken_rc_en, + PMIFSPI_ARB_EN_DCXO_CONN, spi_arb_dcxo_conn_en, + PMIFSPI_ARB_EN_DCXO_NFC, spi_arb_dcxo_nfc_en); +} + +void pmwrap_interface_init(void) +{ + if (CONFIG(SRCLKEN_RC_SUPPORT)) { + printk(BIOS_INFO, "%s: Select PMIF_VLD_RDY\n", __func__); + pmif_select(PMIF_VLD_RDY); + } else { + printk(BIOS_INFO, "%s: Select PMIF_SLP_REQ\n", __func__); + pmif_select(PMIF_SLP_REQ); + } +} + int mtk_pmif_init(void) { int ret; diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c new file mode 100644 index 00000000000..b5c381b50da --- /dev/null +++ b/src/soc/mediatek/mt8192/rtc.c @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) + +static struct pmif *pmif_arb = NULL; + +void rtc_read(u16 addr, u16 *rdata) +{ + u32 data; + + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + pmif_arb->read(pmif_arb, 0, (u32)addr, &data); + + *rdata = (u16)data; +} + +void rtc_write(u16 addr, u16 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + pmif_arb->write(pmif_arb, 0, (unsigned int)addr, (unsigned int)wdata); +} + +static void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift) +{ + u16 old, new; + + rtc_read(reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + rtc_write(reg, new); +} + +/* initialize rtc setting of using dcxo clock */ +static bool rtc_enable_dcxo(void) +{ + if (!rtc_writeif_unlock()) { + rtc_info("rtc_writeif_unlock() failed\n"); + return false; + } + + u16 bbpu, con, osc32con, sec; + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &osc32con); + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK); + osc32con |= (OSC32CON_ANALOG_SETTING | RTC_REG_XOSC32_ENB); + + if (!rtc_xosc_write(osc32con)) { + rtc_info("rtc_xosc_write() failed\n"); + return false; + } + + rtc_read(RTC_CON, &con); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_read(RTC_AL_SEC, &sec); + rtc_info("con=%#x, osc32con=%#x, sec=%#x\n", con, osc32con, sec); + return true; +} + +/* initialize rtc related gpio */ +bool rtc_gpio_init(void) +{ + u16 con; + + /* GPI mode and pull down */ + rtc_read(RTC_CON, &con); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); + con |= (RTC_CON_GPEN | RTC_CON_GOE); + con &= ~(RTC_CON_F32KOB); + con &= ~RTC_CON_GPU; + rtc_write(RTC_CON, con); + + return rtc_write_trigger(); +} + +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 bbpu, osc32con; + u16 fqmtr_busy, fqmtr_data, fqmtr_tcksel; + struct stopwatch sw; + + if (val) { + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | + (val & RTC_XOSCCALI_MASK)); + } + + /* RG_BANK_FQMTR_RST=1, reset FQMTR*/ + rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 1, 1, + PMIC_RG_BANK_FQMTR_RST_SHIFT); + udelay(20); + /* RG_BANK_FQMTR_RST=0, release FQMTR*/ + rtc_write_field(PMIC_RG_BANK_FQMTR_RST, 0, 1, + PMIC_RG_BANK_FQMTR_RST_SHIFT); + + /* enable FQMTR clock */ + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + + + rtc_write_field(PMIC_RG_FQMTR_CON0, 1, 1, + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT); + + /* set frequency meter window value (0=1X32K(fixed clock)) */ + rtc_write(PMIC_RG_FQMTR_WINSET, window_size); + /* enable 26M and set test clock source */ + rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); + /* enable 26M -> delay 100us -> enable FQMTR */ + mdelay(1); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* enable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); + mdelay(1); + stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); + /* FQMTR read until ready */ + do { + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + if (stopwatch_expired(&sw)) { + rtc_info("get frequency time out!\n"); + return false; + } + } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); + + /* read data should be closed to 26M/32k = 794 */ + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + + /* disable FQMTR */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); + /* disable FQMTR -> delay 100us -> disable 26M */ + mdelay(1); + /* disable 26M */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, + fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); + rtc_info("input=%d, output=%d\n", val, fqmtr_data); + + /* disable FQMTR clock */ + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + + return fqmtr_data; +} + +/* low power detect setting */ +static bool rtc_lpd_init(void) +{ + u16 con, sec; + + /* enable both XOSC & EOSC LPD */ + rtc_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_F32K_CK_ALIVE; + rtc_write(RTC_AL_SEC, sec); + + if (!rtc_write_trigger()) + return false; + + /* init XOSC32 to detect 32k clock stop */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; + + if (!rtc_lpen(con)) + return false; + + /* init EOSC32 to detect rtc low power */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; + + if (!rtc_lpen(con)) + return false; + + rtc_read(RTC_CON, &con); + rtc_info("check RTC_CON_LPSTA_RAW after LP init: %#x\n", con); + + return true; +} + +static bool rtc_hw_init(void) +{ + u16 bbpu; + + rtc_read(RTC_BBPU, &bbpu); + bbpu |= RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR; + rtc_write(RTC_BBPU, bbpu & (~RTC_BBPU_SPAR_SW)); + rtc_write_trigger(); + udelay(500); + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_BBPU, &bbpu); + + if (bbpu & RTC_BBPU_RESET_ALARM || bbpu & RTC_BBPU_RESET_SPAR) { + rtc_info("timeout\n"); + return false; + } + return true; +} + +/* rtc init check */ +int rtc_init(int recover) +{ + int ret; + u16 year; + + rtc_info("recovery: %d\n", recover); + + /* write powerkeys to enable rtc functions */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + + /* write interface unlock need to be set after powerkey match */ + if (!rtc_writeif_unlock()) { + ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL; + goto err; + } + + rtc_osc_init(); + + /* In recovery mode, we need 20ms delay for register setting. */ + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) { + ret = -RTC_STATUS_GPIO_INIT_FAIL; + goto err; + } + + if (!rtc_hw_init()) { + ret = -RTC_STATUS_HW_INIT_FAIL; + goto err; + } + + if (!rtc_reg_init()) { + ret = -RTC_STATUS_REG_INIT_FAIL; + goto err; + } + + /* solution1 for EOSC cali*/ + rtc_read(RTC_AL_YEA, &year); + rtc_write(RTC_AL_YEA, (year | RTC_K_EOSC_RSV_0) & (~RTC_K_EOSC_RSV_1) + & (~RTC_K_EOSC_RSV_2)); + rtc_write_trigger(); + + if (!rtc_lpd_init()) { + ret = -RTC_STATUS_LPD_INIT_FAIL; + goto err; + } + + /* + * After lpd init, powerkeys need to be written again to enable + * low power detect function. + */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + return RTC_STATUS_OK; + +err: + rtc_info("init failed: ret=%d\n", ret); + return ret; +} + +/* enable rtc bbpu */ +void rtc_bbpu_power_on(void) +{ + u16 bbpu; + int ret; + + /* pull powerhold high, control by pmic */ + rtc_write_field(PMIC_PWRHOLD, 1, 0x1, 0); + bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM; + rtc_write(RTC_BBPU, bbpu); + ret = rtc_write_trigger(); + rtc_info("rtc_write_trigger=%d\n", ret); + rtc_read(RTC_BBPU, &bbpu); + rtc_info("done BBPU=%#x\n", bbpu); +} + +void poweroff(void) +{ + u16 bbpu; + + if (!rtc_writeif_unlock()) + rtc_info("rtc_writeif_unlock() failed\n"); + /* pull PWRBB low */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM; + rtc_write(RTC_BBPU, bbpu); + rtc_write_field(PMIC_PWRHOLD, 0, 0x1, 0); + halt(); +} + +/* the rtc boot flow entry */ +void rtc_boot(void) +{ + u16 tmp; + + /* dcxo 32k init settings */ + rtc_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); + rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp); + rtc_info("PMIC_RG_SCK_TOP_CON0,%#x:%#x\n", PMIC_RG_SCK_TOP_CON0, tmp); + rtc_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp); + rtc_info("PMIC_RG_SCK_TOP_CON0,%#x:%#x\n", PMIC_RG_SCK_TOP_CON0, tmp); + /* use dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() failed\n"); + rtc_boot_common(); + rtc_bbpu_power_on(); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 8696f342d4f..883f4dc8da7 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -16,6 +17,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + dapc_init(); mcupm_init(); sspm_init(); ufs_disable_refclk(); diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c index d35e5ad3ca7..f7a8756d1a0 100644 --- a/src/soc/mediatek/mt8192/spi.c +++ b/src/soc/mediatek/mt8192/spi.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/mediatek/mt8192/srclken_rc.c b/src/soc/mediatek/mt8192/srclken_rc.c new file mode 100644 index 00000000000..f6790c68983 --- /dev/null +++ b/src/soc/mediatek/mt8192/srclken_rc.c @@ -0,0 +1,388 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define RCTAG "[SRCLKEN_RC]" +#define rc_info(fmt, arg ...) printk(BIOS_INFO, RCTAG "%s,%d: " fmt, \ + __func__, __LINE__, ## arg) + +#define SRCLKEN_DBG 1 + +/* RC settle time setting */ +enum { + FULL_SET_HW_MODE = 0, /* dcxo mode use pmrc_en */ + VCORE_SETTLE_TIME = 1, /* ~= 30us */ + ULPOSC_SETTLE_TIME = 4, /* ~= 150us */ + XO_SETTLE_TIME = 0x1, /* 2 ^ (step_sz + 5) * 0x33 * 30.77ns ~= 400us */ + DCXO_SETTLE_TIME = 0x1, /* 2 ^ (step_sz + 5) * 0x87 * 30.77ns ~= 1063us */ + CENTROL_CNT_STEP = 0x3, /* fix in 3, central align with Mxx channel */ + DCXO_STABLE_TIME = 0x70, + XO_STABLE_TIME = 0x70, + KEEP_RC_SPI_ACTIVE_VAL = 1, + SRCLKEN_RC_EN_SEL_VAL = 0, +}; + +enum { + INIT_SUBSYS_FPM_TO_LPM = 1 << CHN_RF | 1 << CHN_DEEPIDLE | 1 << CHN_MD + | 1 << CHN_GPS | 1 << CHN_BT | 1 << CHN_WIFI + | 1 << CHN_MCU | 1 << CHN_COANT | 1 << CHN_NFC + | 1 << CHN_UFS | 1 << CHN_SCP | 1 << CHN_RESERVE, + INIT_SUBSYS_FPM_TO_BBLPM = 1 << CHN_DEEPIDLE, + INIT_SUBSYS_TO_HW = 1 << CHN_SUSPEND | 1 << CHN_DEEPIDLE | 1 << CHN_MCU, +}; + +/* RC central setting */ +enum { + RC_CENTRAL_ENABLE = 1, + RC_CENTRAL_DISABLE = 0, + SPI_TRIG_MODE = SRCLKENAO_MODE, /* use srlckenao to set vcore */ + IS_SPI_DONE_RELEASE = 0, /* release vcore when spi request done */ + IS_SPI2PMIC_SET_CLR = 0, /* register direct write */ + SRCLKENO_0_CTRL_M = MERGE_OR_MODE, /* merge with spm */ + VREQ_CTRL_M = BYPASS_MODE, /* merge with vreq */ + ULPOSC_CTRL_M_VAL = BYPASS_MODE, /* merge with ulposc */ + PWRAP_CTRL_M = MERGE_OR_MODE, /* merge with pwrap_scp */ + SPI_CLK_SRC = RC_32K, /* pmic spec under 200us */ +}; + +/* Other setting */ +enum { + DCXO_FPM_CTRL_MODE = MERGE_OR_MODE | ASYNC_MODE, /* merge with spm */ + PWRAP_TMOUT_VAL = 0xA, /* 31us * 0xa ~= 310us */ + FPM_MSK_B = FULL_SET_HW_MODE, + MD0_SRCLKENO_0_MASK_B = 0, /* md0 control by pmrc */ +}; + +enum { + SUB_BBLPM_SET = 1 << CHN_COANT | 1 << CHN_DEEPIDLE, + SUB_FPM_SET = 1 << CHN_SUSPEND | 1 << CHN_RF | 1 << CHN_MD + | 1 << CHN_GPS | 1 << CHN_BT | 1 << CHN_WIFI + | 1 << CHN_MCU | 1 << CHN_NFC | 1 << CHN_UFS + | 1 << CHN_SCP | 1 << CHN_RESERVE, +}; + +enum { + SW_FPM_LOW = 0, + SW_FPM_HIGH = 1, +}; + +enum { + SW_BBLPM_LOW = 0, + SW_BBLPM_HIGH = 1, +}; + +enum { + DXCO_SETTLE_BLK_DIS = 0, + DXCO_SETTLE_BLK_EN = 1, +}; + +#define SUB_CTRL_CON(_dcxo_prd, _xo_prd, _bypass_cmd, _dcxo_settle_blk_en) { \ + .dcxo_prd = _dcxo_prd, \ + .xo_prd = _xo_prd, \ + .cnt_step = CENTROL_CNT_STEP, \ + .track_en = 0x0, \ + .req_ack_imd_en = 0x1, \ + .xo_soc_link_en = 0x0, \ + .sw_bblpm = SW_BBLPM_LOW, \ + .sw_fpm = SW_FPM_HIGH, \ + .sw_rc = SW_MODE, \ + .bypass_cmd = _bypass_cmd, \ + .dcxo_settle_blk_en = _dcxo_settle_blk_en, \ + } + +static struct mtk_rc_regs *rc_regs = (struct mtk_rc_regs *)RC_BASE; +static struct mtk_rc_status_regs *rc_sta_regs = (struct mtk_rc_status_regs *)RC_STATUS_BASE; + +static struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = { + [CHN_SUSPEND] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_RF] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_DEEPIDLE] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, + 0x0, DXCO_SETTLE_BLK_EN), + [CHN_MD] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_GPS] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_BT] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_WIFI] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_MCU] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_COANT] = SUB_CTRL_CON(0x0, 0x0, 0x1, DXCO_SETTLE_BLK_DIS), + [CHN_NFC] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_UFS] = SUB_CTRL_CON(DCXO_STABLE_TIME, XO_STABLE_TIME, 0x0, DXCO_SETTLE_BLK_EN), + [CHN_SCP] = SUB_CTRL_CON(0x0, 0x0, 0x1, DXCO_SETTLE_BLK_DIS), + [CHN_RESERVE] = SUB_CTRL_CON(0x0, 0x0, 0x1, DXCO_SETTLE_BLK_DIS), +}; + +static void pmic_read(u32 addr, u32 *rdata) +{ + static struct pmif *pmif_arb; + + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + pmif_arb->read(pmif_arb, 0, addr, rdata); +} + +static void rc_dump_reg_info(void) +{ + unsigned int chn_n; + + if (SRCLKEN_DBG) { + rc_info("SRCLKEN_RC_CFG:%#x\n", read32(&rc_regs->srclken_rc_cfg)); + rc_info("RC_CENTRAL_CFG1:%#x\n", read32(&rc_regs->rc_central_cfg1)); + rc_info("RC_CENTRAL_CFG2:%#x\n", read32(&rc_regs->rc_central_cfg2)); + rc_info("RC_CENTRAL_CFG3:%#x\n", read32(&rc_regs->rc_central_cfg3)); + rc_info("RC_CENTRAL_CFG4:%#x\n", read32(&rc_regs->rc_central_cfg4)); + rc_info("RC_DCXO_FPM_CFG:%#x\n", read32(&rc_regs->rc_dcxo_fpm_cfg)); + rc_info("SUBSYS_INTF_CFG:%#x\n", read32(&rc_regs->rc_subsys_intf_cfg)); + rc_info("RC_SPI_STA_0:%#x\n", read32(&rc_sta_regs->rc_spi_sta_0)); + rc_info("RC_PI_PO_STA:%#x\n", read32(&rc_sta_regs->rc_pi_po_sta_0)); + + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { + rc_info("M%02d: %#x\n", chn_n, + read32(&rc_regs->rc_mxx_srclken_cfg[chn_n])); + } + } +} + +/* RC initial flow and relative setting */ +static void __rc_ctrl_mode_switch(enum chn_id id, enum rc_ctrl_m mode) +{ + switch (mode) { + case INIT_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], + DCXO_SETTLE_BLK_EN, rc_ctrl[id].dcxo_settle_blk_en, + BYPASS_CMD_EN, rc_ctrl[id].bypass_cmd, + SW_SRCLKEN_RC, rc_ctrl[id].sw_rc, + SW_SRCLKEN_FPM, rc_ctrl[id].sw_fpm, + SW_SRCLKEN_BBLPM, rc_ctrl[id].sw_bblpm, + XO_SOC_LINK_EN, rc_ctrl[id].xo_soc_link_en, + REQ_ACK_LOW_IMD_EN, rc_ctrl[id].req_ack_imd_en, + SRCLKEN_TRACK_M_EN, rc_ctrl[id].track_en, + CNT_PRD_STEP, rc_ctrl[id].cnt_step, + XO_STABLE_PRD, rc_ctrl[id].xo_prd, + DCXO_STABLE_PRD, rc_ctrl[id].dcxo_prd); + break; + case SW_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 1); + break; + case HW_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 0); + break; + default: + die("Can't support rc_mode %d\n", mode); + } + + rc_info("M%02d: %#x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + + +/* RC subsys FPM control */ +static void __rc_ctrl_fpm_switch(enum chn_id id, unsigned int mode) +{ + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, !!mode); + rc_ctrl[id].sw_fpm = mode; + rc_info("M%02d FPM SWITCH: %#x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + +static void __rc_ctrl_bblpm_switch(enum chn_id id, unsigned int mode) +{ + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_BBLPM, !!mode); + rc_ctrl[id].sw_bblpm = mode; + rc_info("M%02d BBLPM SWITCH: %#x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + +static void rc_init_subsys_hw_mode(void) +{ + unsigned int chn_n; + + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { + if (INIT_SUBSYS_TO_HW & (1 << chn_n)) + __rc_ctrl_mode_switch(chn_n, HW_MODE); + } +} + +static void rc_init_subsys_lpm(void) +{ + unsigned int chn_n; + + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { + if (INIT_SUBSYS_FPM_TO_LPM & (1 << chn_n)) + __rc_ctrl_fpm_switch(chn_n, SW_FPM_LOW); + } + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { + if (INIT_SUBSYS_FPM_TO_BBLPM & (1 << chn_n)) + __rc_ctrl_bblpm_switch(chn_n, SW_BBLPM_HIGH); + } +} + +static void rc_ctrl_mode_switch_init(enum chn_id id) +{ + __rc_ctrl_mode_switch(id, INIT_MODE); +} + +static enum rc_support srclken_rc_chk_init_cfg(void) +{ + pmwrap_interface_init(); + if (!CONFIG(SRCLKEN_RC_SUPPORT)) { + rc_info("Bring-UP : skip srclken_rc init\n"); + return SRCLKEN_RC_DISABLE; + } + if (SRCLKEN_DBG) { + /* Enable debug trace */ + write32(&rc_sta_regs->rc_debug_trace, 1); + SET32_BITFIELDS(&rc_regs->rc_debug_cfg, TRACE_MODE_EN, 1); + } + return SRCLKEN_RC_ENABLE; +} + +int srclken_rc_init(void) +{ + /* New co-clock architecture srclkenrc implement here */ + unsigned int chn_n; + int ret = 0; + + /* Check platform config to proceed init flow */ + if (srclken_rc_chk_init_cfg() != SRCLKEN_RC_ENABLE) + return ret; + + /* Set SW RESET 1 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 1); + + /* Wait 100us */ + udelay(100); + + /* Set SW CG 1 */ + write32(&rc_regs->srclken_rc_cfg, + _BF_VALUE(SW_RESET, 1) | _BF_VALUE(CG_32K_EN, 1) | + _BF_VALUE(CG_FCLK_EN, 1) | _BF_VALUE(CG_FCLK_FR_EN, 1)); + + /* Wait 100us */ + udelay(100); + + /* Set Clock Mux */ + write32(&rc_regs->srclken_rc_cfg, + _BF_VALUE(SW_RESET, 1) | _BF_VALUE(CG_32K_EN, 1) | + _BF_VALUE(CG_FCLK_EN, 1) | _BF_VALUE(CG_FCLK_FR_EN, 1) | + _BF_VALUE(MUX_FCLK_FR, 1)); + + /* Set req_filter m00~m12 as default SW_FPM */ + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) + rc_ctrl_mode_switch_init(chn_n); + + /* Set PMIC addr for SPI CMD */ + write32(&rc_regs->rc_pmic_rcen_addr, PMIC_PMRC_CON0); + + write32(&rc_regs->rc_pmic_rcen_set_clr_addr, + (PMIC_PMRC_CON0_CLR << 16) | PMIC_PMRC_CON0_SET); + + write32(&rc_regs->rc_cmd_arb_cfg, 0); + + /* CFG1 setting for spi cmd config */ + write32(&rc_regs->rc_central_cfg1, + _BF_VALUE(DCXO_SETTLE_T, DCXO_SETTLE_TIME) | + _BF_VALUE(NON_DCXO_SETTLE_T, XO_SETTLE_TIME) | + _BF_VALUE(ULPOSC_SETTLE_T, ULPOSC_SETTLE_TIME) | + _BF_VALUE(VCORE_SETTLE_T, VCORE_SETTLE_TIME) | + _BF_VALUE(SRCLKEN_RC_EN_SEL, SRCLKEN_RC_EN_SEL_VAL) | + _BF_VALUE(RC_SPI_ACTIVE, KEEP_RC_SPI_ACTIVE_VAL) | + _BF_VALUE(RCEN_ISSUE_M, IS_SPI2PMIC_SET_CLR) | + _BF_VALUE(SRCLKEN_RC_EN, RC_CENTRAL_DISABLE)); + + /* CFG2 setting for signal mode of each control mux */ + write32(&rc_regs->rc_central_cfg2, + _BF_VALUE(PWRAP_SLP_MUX_SEL, SPI_CLK_SRC) | + _BF_VALUE(PWRAP_SLP_CTRL_M, PWRAP_CTRL_M) | + _BF_VALUE(ULPOSC_CTRL_M, ULPOSC_CTRL_M_VAL) | + _BF_VALUE(SRCVOLTEN_VREQ_M, IS_SPI_DONE_RELEASE) | + _BF_VALUE(SRCVOLTEN_VREQ_SEL, SPI_TRIG_MODE) | + _BF_VALUE(VREQ_CTRL, VREQ_CTRL_M) | + _BF_VALUE(SRCVOLTEN_CTRL, SRCLKENO_0_CTRL_M)); + + write32(&rc_regs->rc_central_cfg3, + _BF_VALUE(TO_LPM_SETTLE_T, 0x4) | + _BF_VALUE(TO_BBLPM_SETTLE_EN, 1) | + _BF_VALUE(BLK_COANT_DXCO_MD_TARGET, 1) | + _BF_VALUE(BLK_SCP_DXCO_MD_TARGET, 1) | + _BF_VALUE(TO_LPM_SETTLE_EN, 1)); + + /* Set srclkeno_0/conn_bt as factor to allow dcxo change to FPM */ + write32(&rc_regs->rc_dcxo_fpm_cfg, + _BF_VALUE(SUB_SRCLKEN_FPM_MSK_B, FPM_MSK_B) | + _BF_VALUE(SRCVOLTEN_FPM_MSK_B, MD0_SRCLKENO_0_MASK_B) | + _BF_VALUE(DCXO_FPM_CTRL_M, DCXO_FPM_CTRL_MODE)); + + /* Set bblpm/fpm channel */ + write32(&rc_regs->rc_subsys_intf_cfg, + _BF_VALUE(SRCLKEN_BBLPM_MASK_B, SUB_BBLPM_SET) | + _BF_VALUE(SRCLKEN_FPM_MASK_B, SUB_FPM_SET)); + + /* Trigger srclken_rc enable */ + SET32_BITFIELDS(&rc_regs->rc_central_cfg1, + SRCLKEN_RC_EN, RC_CENTRAL_ENABLE); + + write32(&rc_regs->rc_central_cfg4, + _BF_VALUE(SLEEP_VLD_MODE, 0x1) | + _BF_VALUE(PWRAP_VLD_FORCE, 0x1) | + _BF_VALUE(KEEP_RC_SPI_ACTIVE, 0x800)); + + + /* Wait 100us */ + udelay(100); + + /* Set SW RESET 0 */ + write32(&rc_regs->srclken_rc_cfg, + _BF_VALUE(CG_32K_EN, 1) | _BF_VALUE(CG_FCLK_EN, 1) | + _BF_VALUE(CG_FCLK_FR_EN, 1) | _BF_VALUE(MUX_FCLK_FR, 1)); + + /* Wait 100us */ + udelay(100); + + /* Set SW CG 0 */ + write32(&rc_regs->srclken_rc_cfg, _BF_VALUE(MUX_FCLK_FR, 1)); + + /* Wait 500us */ + udelay(500); + + /* Set req_filter m00~m12 FPM to LPM */ + rc_init_subsys_lpm(); + + /* Polling ACK of Initial Subsys Input */ + for (chn_n = 0; chn_n < MAX_CHN_NUM; chn_n++) { + unsigned int chk_sta, shift_chn_n = 0; + int retry; + u32 temp; + + /* Fix RC_MXX_REQ_STA_0 register shift */ + if (chn_n > 0) + shift_chn_n = 1; + + chk_sta = (rc_ctrl[chn_n].sw_fpm & SW_SRCLKEN_FPM_MSK) << 1 | + (rc_ctrl[chn_n].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) << 3; + retry = 200; + while ((read32(&rc_sta_regs->rc_mxx_req_sta_0[chn_n + shift_chn_n]) & 0xa) + != chk_sta && retry-- > 0) + udelay(10); + if (retry < 0) { + pmic_read(PMIC_PMRC_CON0, &temp); + rc_info("polling M%02d failed.(R:%#x)(C:%#x)(PMRC:%#x)\n", + chn_n, + read32(&rc_sta_regs->rc_mxx_req_sta_0[chn_n + shift_chn_n]), + read32(&rc_regs->rc_mxx_srclken_cfg[chn_n]), temp); + ret = -1; + } + } + + /* Set req_filter m00~m12 */ + rc_init_subsys_hw_mode(); + + /* Release force pmic req signal */ + write32(&rc_regs->rc_central_cfg4, + _BF_VALUE(SLEEP_VLD_MODE, 0x1) | + _BF_VALUE(KEEP_RC_SPI_ACTIVE, 0x800)); + + rc_dump_reg_info(); + + return ret; +} diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile index 68a3cb6da77..dc33909befe 100644 --- a/src/soc/nvidia/tegra124/lp0/Makefile +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -1,6 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only --include ../../../../../.xcompile +xcompile ?= ../../../../../build/xcompile +-include $(xcompile) + GCC_PREFIX?=$(CROSS_COMPILE_arm) CC = $(GCC_PREFIX)gcc diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 3a078f8573c..4e0285de5bf 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -605,7 +605,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, * When we enable caching we'll need to clean/invalidate portions of * memory. So we need to be careful about memory alignment. Also, DMA * likes to operate on 4-bytes at a time on the AHB side. So for - * example, if we only want to receive 1 byte, 4 bytes will be be + * example, if we only want to receive 1 byte, 4 bytes will be * written in memory even if those extra 3 bytes are beyond the length * we want. * diff --git a/src/soc/nvidia/tegra210/lp0/Makefile b/src/soc/nvidia/tegra210/lp0/Makefile index 68a3cb6da77..dc33909befe 100644 --- a/src/soc/nvidia/tegra210/lp0/Makefile +++ b/src/soc/nvidia/tegra210/lp0/Makefile @@ -1,6 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only --include ../../../../../.xcompile +xcompile ?= ../../../../../build/xcompile +-include $(xcompile) + GCC_PREFIX?=$(CROSS_COMPILE_arm) CC = $(GCC_PREFIX)gcc diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 66f9fd8c93f..f8db110f7af 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -639,7 +639,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, * When we enable caching we'll need to clean/invalidate portions of * memory. So we need to be careful about memory alignment. Also, DMA * likes to operate on 4-bytes at a time on the AHB side. So for - * example, if we only want to receive 1 byte, 4 bytes will be be + * example, if we only want to receive 1 byte, 4 bytes will be * written in memory even if those extra 3 bytes are beyond the length * we want. * diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index fcf48b86fed..b93a9b8c1aa 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -432,7 +432,7 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) } while (!stopwatch_expired(&sw)); if (i != 4) { - printk(BIOS_DEBUG, "s5p_dp_is_video_stream_on timeout\n"); + printk(BIOS_DEBUG, "%s timeout\n", __func__); return -1; } diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c87d7a09042..6280f3acd0d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index feb930de283..9d5b964efcf 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -158,10 +158,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -PHONY+=add_amdfw -INTERMEDIATE+=add_amdfw - -add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware\n" dd if=$(obj)/amdfw.rom \ of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 diff --git a/src/southbridge/amd/pi/hudson/soc/gpio.h b/src/southbridge/amd/pi/hudson/soc/gpio.h new file mode 100644 index 00000000000..10a47cb101a --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_GPIO_H +#define SOC_GPIO_H + +/* must provide gpio_t. */ +#include + +#endif /* SOC_GPIO_H */ diff --git a/src/southbridge/amd/pi/hudson/soc/smi.h b/src/southbridge/amd/pi/hudson/soc/smi.h new file mode 100644 index 00000000000..da5ddbc2f73 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/smi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SMI_H +#define SOC_SMI_H + +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 + +#endif /* SOC_SMI_H */ diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 3b05a3e678f..06ac5c64552 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -11,6 +11,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 687fc97d4ce..a591aabea03 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,4 +38,6 @@ else romstage-y += early_me_mrc.c early_usb_mrc.c endif +CPPFLAGS_common += -I$(src)/southbridge/intel/bd82x6x/include + endif diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 46096cc66bd..23b6769bed6 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -11,7 +11,7 @@ Name(\PICM, 0) // IOAPIC/8259 */ External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -53,12 +53,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x28 - Enabled by coreboot + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count + , 8, // 0x2d - Processor count /* Super I/O & CMOS config */ Offset (0x32), NATP, 8, // 0x32 - @@ -110,6 +110,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value + CBMC, 32, /* ChromeOS specific */ Offset (0x100), diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index b3510ac5217..46874b2dc4d 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -16,7 +16,7 @@ static void write16p(uintptr_t addr, uint32_t val) write16((u16 *)addr, val); } -static uint16_t read16p (uintptr_t addr) +static uint16_t read16p(uintptr_t addr) { return read16((u16 *)addr); } diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h similarity index 89% rename from src/southbridge/intel/bd82x6x/nvs.h rename to src/southbridge/intel/bd82x6x/include/soc/nvs.h index b75e0ab0254..969d59209b1 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -3,9 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_NVS_H #define SOUTHBRIDGE_INTEL_BD82X6X_NVS_H -#include #include -#include "vendorcode/google/chromeos/gnvs.h" struct __packed global_nvs { /* Miscellaneous */ @@ -46,12 +44,12 @@ struct __packed global_nvs { u8 tmps; /* 0x25 - Temperature Sensor ID */ u8 rsvd3[2]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 unused_was_pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ @@ -100,13 +98,9 @@ struct __packed global_nvs { /* XHCI */ u8 xhci; u8 rsvd12[65]; - u8 tpiq; /* 0xf5 - trackpad IRQ value */ - u8 rsvd13[10]; /* 0xf6 - rsvd */ - /* ChromeOS specific (starts at 0x100)*/ - chromeos_acpi_t chromeos; + u8 tpiq; /* 0xf5 - trackpad IRQ value */ + u32 cbmc; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8af80654e96..d5d39f5ff60 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -12,14 +12,11 @@ #include #include #include -#include #include #include -#include #include #include "chip.h" #include "pch.h" -#include "nvs.h" #include #include #include @@ -642,33 +639,6 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -void southbridge_inject_dsdt(const struct device *dev) -{ - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - - if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - - acpi_create_gnvs(gnvs); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; @@ -716,7 +686,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .write_acpi_tables = acpi_write_hpet, - .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 3876b023064..2adfbd5c98d 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) -#include -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index d47c1da6b8a..b0226a6e9ad 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) -#include -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index ae157d36c30..422c091001d 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -15,6 +15,8 @@ #include "me.h" #include "pch.h" +#include + /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -362,10 +364,6 @@ int intel_mei_setup(struct device *dev) return 0; } -#if CONFIG(CHROMEOS) -#include -#endif - /* Read the Extend register hash of ME firmware */ int intel_me_extend_valid(struct device *dev) { @@ -405,10 +403,9 @@ int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 151627d5ddf..1840a2b0d2c 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -84,7 +84,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) -#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 #define PCH_IOAPIC_PCI_BUS 250 @@ -92,6 +91,14 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_HPET_PCI_BUS 250 #define PCH_HPET_PCI_SLOT 15 +/* PCI Configuration Space (D20:F0): xHCI */ +#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) + +#define XHCI_PWR_CNTL_STS 0x74 + +/* xHCI memory base registers */ +#define XHCI_PORTSC_x_USB3(port) (0x4c0 + (port) * 0x10) + /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIRQ_CNTL 0x64 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f87cd7..bef98fae100 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include "pch.h" -#include "nvs.h" int southbridge_io_trap_handler(int smif) { @@ -70,7 +70,7 @@ void southbridge_gate_memory_reset(void) { u16 gpiobase; - gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCH_LPC_DEV, GPIOBASE) & 0xfffc; if (!gpiobase) return; @@ -86,46 +86,6 @@ void southbridge_gate_memory_reset(void) gpiobase + GP_LVL); } -static void xhci_sleep(u8 slp_typ) -{ - u32 xhci_bar; - u16 reg16; - - switch (slp_typ) { - case ACPI_S3: - case ACPI_S4: - /* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */ - reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 &= ~0x03UL; - pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - - pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; - - /* FIXME: This looks broken (conditions are always false) */ - if ((xhci_bar + 0x4C0) & 1) - pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4D0) & 1) - pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4E0) & 1) - pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4F0) & 1) - pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - - pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, - ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); - - pci_or_config16(PCH_XHCI_DEV, 0x74, 0x03); - break; - - case ACPI_S5: - pci_or_config16(PCH_XHCI_DEV, 0x74, (1 << 8) | 0x03); - break; - } -} - void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) @@ -179,26 +139,76 @@ void southbridge_smi_monitor(void) #undef IOTRAP } -void southbridge_smm_xhci_sleep(u8 slp_type) +/* + * PCH BIOS Spec Rev 0.7.0, Section 13.5 + * Additional xHCI Controller Configurations Prior to Entering S3/S4 + */ +static void xhci_a0_suspend_smm_workaround(void) { - if (gnvs->xhci) - xhci_sleep(slp_type); + /* Workaround only applies to Panther Point stepping A0 */ + if (pch_silicon_revision() != PCH_STEP_A0) + return; + + /* The BAR is 64-bit, account for it being above 4 GiB */ + if (pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0 + 4)) + return; + + /* PCH datasheet indicates that only the upper 16 bits are valid */ + uintptr_t xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + + if (smm_points_to_smram((void *)xhci_bar, 64 * KiB)) + return; + + /* Step 1: Set power state to D0 */ + pci_and_config16(PCH_XHCI_DEV, XHCI_PWR_CNTL_STS, ~(3 << 0)); + + /* Step 2 */ + pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Steps 3 to 6: If USB3 PORTSC current connect status (bit 0) is set, do IOBP magic */ + for (unsigned int port = 0; port < 4; port++) { + if (read32((void *)(xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0)) + pch_iobp_update(0xec000082 + 0x100 * port, ~0, 3 << 2); + } + + /* Step 7 */ + pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); + + /* Step 8: Set power state to D3 */ + pci_or_config16(PCH_XHCI_DEV, XHCI_PWR_CNTL_STS, 3 << 0); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void southbridge_smm_xhci_sleep(u8 slp_type) { - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + /* Only Panther Point has xHCI */ + if (pch_silicon_type() != PCH_TYPE_PPT) + return; + + /* Verify that RCBA is still valid */ + if (pci_read_config32(PCH_LPC_DEV, RCBA) != ((u32)DEFAULT_RCBA | RCBA_ENABLE)) + return; + + if (RCBA32(FD) & PCH_DISABLE_XHCI) + return; + + switch (slp_type) { + case ACPI_S3: + case ACPI_S4: + xhci_a0_suspend_smm_workaround(); + break; + + case ACPI_S5: + /* + * PCH BIOS Spec Rev 0.7.0, Section 13.5 + * Additional xHCI Controller Configurations Prior to Entering S5 + * + * For all steppings: + * Step 1: Set power state to D3 (bits 1:0) + * Step 2: Set PME# enable bit (bit 8) + */ + pci_or_config16(PCH_XHCI_DEV, XHCI_PWR_CNTL_STS, 1 << 8 | 3 << 0); + break; } } diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25757d..a14513deadd 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_HPET + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 6c57481e55e..f11ffa6aef1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -5,6 +5,8 @@ subdirs-y += firmware all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 516cd4d4539..d5a48fd6f97 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -7,7 +7,7 @@ ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) # image outside of CBFS ifeq ($(CONFIG_HAVE_IFD_BIN),y) -INTERMEDIATE+=add_intel_firmware +$(call add_intermediate, add_intel_firmware) else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) files_added:: warn_intel_firmware endif @@ -106,6 +106,6 @@ warn_intel_firmware: printf "board's flash chip! You can use flashrom's IFD or layout\n" printf "parameters to flash only to the BIOS region.\n\n" -PHONY+=add_intel_firmware warn_intel_firmware +PHONY+=warn_intel_firmware endif diff --git a/src/southbridge/intel/common/hpet.c b/src/southbridge/intel/common/hpet.c new file mode 100644 index 00000000000..c48edae59d5 --- /dev/null +++ b/src/southbridge/intel/common/hpet.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "hpet.h" + +#define HPTC 0x3404 + +#define HPET_BASE 0xfed00000 +#define HPET32(x) (*((volatile u32 *)(HPET_BASE + (x)))) + +void enable_hpet(void) +{ + u32 reg32; + reg32 = RCBA32(HPTC); + reg32 &= ~0x03; + reg32 |= (1 << 7); + RCBA32(HPTC) = reg32; + /* Read back for posted write to take effect */ + RCBA32(HPTC); + HPET32(0x10) = HPET32(0x10) | 1; +} + +void hpet_udelay(u32 delay) +{ + u32 start, finish, now; + + delay *= 15; /* now in usec */ + + start = HPET32(0xf0); + finish = start + delay; + while (1) { + now = HPET32(0xf0); + if (finish > start) { + if (now >= finish) + break; + } else { + if ((now < start) && (now >= finish)) + break; + } + } +} diff --git a/src/southbridge/intel/common/hpet.h b/src/southbridge/intel/common/hpet.h new file mode 100644 index 00000000000..1a69178e2e8 --- /dev/null +++ b/src/southbridge/intel/common/hpet.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_HPET_H +#define SOUTHBRIDGE_INTEL_COMMON_HPET_H + +#include + +void enable_hpet(void); +void hpet_udelay(u32 delay); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_HPET_H */ diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c1756474ae6..c9cf544f4eb 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -4,7 +4,6 @@ #define INTEL_COMMON_PMUTIL_H #include -#include #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -129,10 +128,8 @@ void dump_all_status(void); void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7610aa11026..d59e29cdd93 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,8 +17,6 @@ #include "pmutil.h" -static int smm_initialized = 0; - u16 get_pmbase(void) { return lpc_get_pmbase(); @@ -198,7 +196,7 @@ static void southbridge_smi_sleep(void) * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; int node; @@ -302,14 +300,6 @@ static void southbridge_smi_apmc(void) write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - southbridge_update_gnvs(reg8, &smm_initialized); - break; case APM_CNT_FINALIZE: if (mainboard_finalized) { printk(BIOS_DEBUG, "SMI#: Already finalized\n"); diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d3bf24b3eb..c8807935a2f 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select IOAPIC select USE_WATCHDOG_ON_BOOT @@ -21,6 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_HPET if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 11a9c0007dc..95402a1dfc4 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -25,4 +25,6 @@ smm-y += smihandler.c romstage-y += early_init.c romstage-y += early_cir.c +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801gx/include + endif diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 848005dcb9b..8bd222fbc11 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -52,7 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) B2SS, 8, // 0x24 - BAT2 stored status /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot + , 8, // 0x28 - Enabled by coreboot MPEN, 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 @@ -108,4 +108,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable + CBMC, 32, } diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h similarity index 97% rename from src/southbridge/intel/i82801gx/nvs.h rename to src/southbridge/intel/i82801gx/include/soc/nvs.h index d2efc5c8b18..d9e01df05e1 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -40,7 +40,7 @@ struct __packed global_nvs { u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 rsvd3[3]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ u8 mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ @@ -96,7 +96,8 @@ struct __packed global_nvs { /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; - u8 rsvd13[14]; + + u32 cbmc; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9ac894254c7..6c48e9c9062 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -16,15 +16,15 @@ #include #include #include -#include #include #include +#include #include #include +#include #include "chip.h" #include "i82801gx.h" -#include "nvs.h" #define NMI_OFF 0 @@ -269,21 +269,6 @@ static void i82801gx_rtc_init(struct device *dev) cmos_init(rtc_failed); } -static void enable_hpet(void) -{ - u32 reg32; - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; - /* On NM10 this only works if read back */ - RCBA32(HPTC); - - write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); -} - static void enable_clock_gating(void) { u32 reg32; @@ -479,26 +464,10 @@ static void lpc_final(struct device *dev) outb(POST_OS_BOOT, 0x80); } -void southbridge_inject_dsdt(const struct device *dev) +void soc_fill_gnvs(struct global_nvs *gnvs) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - - if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } + /* MPEN, Enable Multi Processing. */ + gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0; } static const char *lpc_acpi_name(const struct device *dev) @@ -515,7 +484,6 @@ static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f1be5c200bf..67a8cf8cf40 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "i82801gx.h" @@ -15,15 +16,8 @@ #define G_SMRANE (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index be640db0c3c..3ee29430907 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER if !NO_SMM select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 516a344e625..8eabd493002 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -29,4 +29,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include + endif diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 5c9e26ea271..021de14e2cf 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -53,7 +53,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) B2SS, 8, // 0x24 - BAT2 stored status /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot + , 8, // 0x28 - Enabled by coreboot MPEN, 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 @@ -110,4 +110,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable + CBMC, 32, } diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h similarity index 97% rename from src/southbridge/intel/i82801ix/nvs.h rename to src/southbridge/intel/i82801ix/include/soc/nvs.h index e0e6bbd68d5..4fa56763bca 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -40,7 +40,7 @@ struct __packed global_nvs { u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 rsvd3[3]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ u8 mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ @@ -96,7 +96,8 @@ struct __packed global_nvs { /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; - u8 rsvd13[14]; + + u32 cbmc; }; #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 652da54103a..5400237fa8f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -15,14 +15,13 @@ #include #include #include -#include #include #include "chip.h" #include "i82801ix.h" -#include "nvs.h" #include #include #include +#include #define NMI_OFF 0 @@ -453,22 +452,10 @@ static void i82801ix_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -void southbridge_inject_dsdt(const struct device *dev) +void soc_fill_gnvs(struct global_nvs *gnvs) { - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - - if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } + /* MPEN, Enable Multi Processing. */ + gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0; } static const char *lpc_acpi_name(const struct device *dev) @@ -489,7 +476,6 @@ static struct device_operations device_ops = { .read_resources = i82801ix_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 537e544f944..0483447e942 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -7,17 +7,13 @@ #include #include "i82801ix.h" -#include "nvs.h" +#include #if !CONFIG(SMM_TSEG) /* For qemu/x86-q35 to build properly. */ struct global_nvs *gnvs; #endif -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 687cb459248..bd553eea762 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 9885bc04193..f4893c2ea44 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -23,4 +23,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801jx/include + endif diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 5c9e26ea271..3d0d3b27909 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) B2SS, 8, // 0x24 - BAT2 stored status /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x28 - Enabled by coreboot + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state @@ -110,4 +110,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable + CBMC, 32, } diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h similarity index 96% rename from src/southbridge/intel/i82801jx/nvs.h rename to src/southbridge/intel/i82801jx/include/soc/nvs.h index 48a7d87fe17..4325a8c1eea 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -39,8 +39,8 @@ struct __packed global_nvs { u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 rsvd3[3]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ @@ -95,7 +95,8 @@ struct __packed global_nvs { /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; - u8 rsvd13[14]; + + u32 cbmc; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 1f4cf29187d..90650693e18 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,15 +12,12 @@ #include #include #include -#include #include #include #include -#include #include #include "chip.h" #include "i82801jx.h" -#include "nvs.h" #include #include #include @@ -477,24 +474,6 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -void southbridge_inject_dsdt(const struct device *dev) -{ - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - - if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; @@ -513,7 +492,6 @@ static struct device_operations device_ops = { .read_resources = i82801jx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 7d79620114d..03a6442eb1a 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -4,20 +4,14 @@ #include #include #include +#include #include #include "i82801jx.h" -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c54c7e4d6c3..cea0efed972 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select IOAPIC select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 277f686ba91..643687f0c86 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -36,4 +36,6 @@ romstage-y += ../bd82x6x/early_rcba.c romstage-y += early_cir.c romstage-y += early_usb.c +CPPFLAGS_common += -I$(src)/southbridge/intel/ibexpeak/include + endif diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl new file mode 100644 index 00000000000..174d12f3c7a --- /dev/null +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 + +/* Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x100) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + /* Thermal policy */ + Offset (0x11), + TLVL, 8, // 0x11 - Throttle Level Limit + FLVL, 8, // 0x12 - Current FAN Level + TCRT, 8, // 0x13 - Critical Threshold + TPSV, 8, // 0x14 - Passive Threshold + TMAX, 8, // 0x15 - CPU Tj_max + F0OF, 8, // 0x16 - FAN 0 OFF Threshold + F0ON, 8, // 0x17 - FAN 0 ON Threshold + F0PW, 8, // 0x18 - FAN 0 PWM value + F1OF, 8, // 0x19 - FAN 1 OFF Threshold + F1ON, 8, // 0x1a - FAN 1 ON Threshold + F1PW, 8, // 0x1b - FAN 1 PWM value + F2OF, 8, // 0x1c - FAN 2 OFF Threshold + F2ON, 8, // 0x1d - FAN 2 ON Threshold + F2PW, 8, // 0x1e - FAN 2 PWM value + F3OF, 8, // 0x1f - FAN 3 OFF Threshold + F3ON, 8, // 0x20 - FAN 3 ON Threshold + F3PW, 8, // 0x21 - FAN 3 PWM value + F4OF, 8, // 0x22 - FAN 4 OFF Threshold + F4ON, 8, // 0x23 - FAN 4 ON Threshold + F4PW, 8, // 0x24 - FAN 4 PWM value + TMPS, 8, // 0x25 - Temperature Sensor ID + /* Processor Identification */ + Offset (0x28), + , 8, // 0x28 - Enabled by coreboot + , 8, // 0x29 - Multi Processor Enable + PCP0, 8, // 0x2a - PDC CPU/CORE 0 + PCP1, 8, // 0x2b - PDC CPU/CORE 1 + PPCM, 8, // 0x2c - Max. PPC state + , 8, // 0x2d - Processor count + /* Super I/O & CMOS config */ + Offset (0x32), + NATP, 8, // 0x32 - + S5U0, 8, // 0x33 - Enable USB0 in S5 + S5U1, 8, // 0x34 - Enable USB1 in S5 + S3U0, 8, // 0x35 - Enable USB0 in S3 + S3U1, 8, // 0x36 - Enable USB1 in S3 + S33G, 8, // 0x37 - Enable 3G in S3 + CMEM, 32, // 0x38 - CBMEM TOC + /* Integrated Graphics Device */ + Offset (0x3c), + IGDS, 8, // 0x3c - IGD state (primary = 1) + TLST, 8, // 0x3d - Display Toggle List pointer + CADL, 8, // 0x3e - Currently Attached Devices List + PADL, 8, // 0x3f - Previously Attached Devices List + /* Backlight Control */ + Offset (0x64), + BLCS, 8, // 0x64 - Backlight control possible? + BRTL, 8, // 0x65 - Brightness Level + ODDS, 8, // 0x66 + /* Ambient Light Sensors */ + Offset (0x6e), + ALSE, 8, // 0x6e - ALS enable + ALAF, 8, // 0x6f - Ambient light adjustment factor + LLOW, 8, // 0x70 - LUX Low + LHIH, 8, // 0x71 - LUX High + /* EMA */ + Offset (0x78), + EMAE, 8, // 0x78 - EMA enable + EMAP, 16, // 0x79 - EMA pointer + EMAL, 16, // 0x7b - EMA length + /* MEF */ + Offset (0x82), + MEFE, 8, // 0x82 - MEF enable + /* TPM support */ + Offset (0x8c), + TPMP, 8, // 0x8c - TPM + TPME, 8, // 0x8d - TPM enable + /* SATA */ + Offset (0x96), + GTF0, 56, // 0x96 - GTF task file buffer for port 0 + GTF1, 56, // 0x9d - GTF task file buffer for port 1 + GTF2, 56, // 0xa4 - GTF task file buffer for port 2 + IDEM, 8, // 0xab - IDE mode (compatible / enhanced) + IDET, 8, // 0xac - IDE + /* XHCI */ + Offset (0xb2), + XHCI, 8, + CBMC, 32, +} + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) + Store (One, \S3U1) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) + Store (Zero, \S3U1) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) + Store (One, \S5U1) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) + Store (Zero, \S5U1) +} + +/* Set flag to enable 3G module in S3 */ +Method (S3GE) +{ + Store (One, \S33G) +} + +/* Set flag to disable 3G module in S3 */ +Method (S3GD) +{ + Store (Zero, \S33G) +} + +/* Set XHCI Mode enable */ +Method (XHCE) +{ + Store (One, \XHCI) +} + +/* Set XHCI Mode disable */ +Method (XHCD) +{ + Store (Zero, \XHCI) +} +External (\_TZ.SKIN) + +Method (TZUP) +{ +#ifdef HAVE_THERMALZONE + /* Update Primary Thermal Zone */ + If (CondRefOf (\_TZ.THRM)) { + Notify (\_TZ.THRM, 0x81) + } +#endif + + /* Update Secondary Thermal Zone */ + If (CondRefOf (\_TZ.SKIN)) { + Notify (\_TZ.SKIN, 0x81) + } +} + +/* Update Fan 0 thresholds */ +Method (F0UT, 2) +{ + Store (Arg0, \F0OF) + Store (Arg1, \F0ON) + TZUP () +} + +/* Update Fan 1 thresholds */ +Method (F1UT, 2) +{ + Store (Arg0, \F1OF) + Store (Arg1, \F1ON) + TZUP () +} + +/* Update Fan 2 thresholds */ +Method (F2UT, 2) +{ + Store (Arg0, \F2OF) + Store (Arg1, \F2ON) + TZUP () +} + +/* Update Fan 3 thresholds */ +Method (F3UT, 2) +{ + Store (Arg0, \F3OF) + Store (Arg1, \F3ON) + TZUP () +} + +/* Update Fan 4 thresholds */ +Method (F4UT, 2) +{ + Store (Arg0, \F4OF) + Store (Arg1, \F4ON) + TZUP () +} + +/* Update Temperature Sensor ID */ +Method (TMPU, 1) +{ + Store (Arg0, \TMPS) + TZUP () +} diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h similarity index 90% rename from src/southbridge/intel/ibexpeak/nvs.h rename to src/southbridge/intel/ibexpeak/include/soc/nvs.h index 8823d837733..5ce88a68b1b 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -5,7 +5,6 @@ #include #include -#include "vendorcode/google/chromeos/gnvs.h" struct __packed global_nvs { /* Miscellaneous */ @@ -46,12 +45,12 @@ struct __packed global_nvs { u8 tmps; /* 0x25 - Temperature Sensor ID */ u8 rsvd3[2]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 unused_was_pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ @@ -99,12 +98,8 @@ struct __packed global_nvs { u8 rsvd11[6]; /* XHCI */ u8 xhci; - u8 rsvd13[76]; /* 0xf5 - rsvd */ - /* ChromeOS specific (starts at 0x100)*/ - chromeos_acpi_t chromeos; + u32 cbmc; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d2a3404880e..361d3a977b2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -13,15 +13,12 @@ #include #include #include -#include #include #include -#include #include #include #include "chip.h" #include "pch.h" -#include "nvs.h" #include #include #include @@ -542,29 +539,6 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -void southbridge_inject_dsdt(const struct device *dev) -{ - struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - - if (gnvs) { - memset(gnvs, 0, sizeof(*gnvs)); - - acpi_create_gnvs(gnvs); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to SSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; @@ -594,7 +568,6 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .write_acpi_tables = acpi_write_hpet, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index bff8d24510b..a38e430a05c 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) -#include -#endif - /* Path that the BIOS should take based on ME state */ static const char *me_bios_path_values[] __unused = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -538,11 +534,6 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) - /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif - return 0; } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954c72a..41f92b5fa05 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -8,13 +8,12 @@ #include #include #include +#include #include #include #include #include "pch.h" -#include "nvs.h" - /* We are using PCIe accesses for now * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind @@ -147,22 +146,6 @@ void southbridge_smi_monitor(void) #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index a88a9a8bc27..7ad3c000277 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 9694cc377fa..d0b342b83a8 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -46,4 +46,6 @@ endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c +CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include + endif diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index e699c5d8e21..aa6e6508cb8 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -5,9 +5,9 @@ #include #include #include +#include #include "pch.h" -#include "nvs.h" static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) { diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 482718a4ea7..758667d02d1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Name (\PICM, 0) // IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -54,12 +54,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x28 - Enabled by coreboot + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state - PCNT, 8, // 0x2d - Processor count + , 8, // 0x2d - Processor count /* Super I/O & CMOS config */ Offset (0x32), NATP, 8, // 0x32 - diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h similarity index 88% rename from src/southbridge/intel/lynxpoint/nvs.h rename to src/southbridge/intel/lynxpoint/include/soc/nvs.h index 154e285a4a5..17ded135893 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h @@ -3,9 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H -#include #include -#include "vendorcode/google/chromeos/gnvs.h" struct __packed global_nvs { /* Miscellaneous */ @@ -46,12 +44,12 @@ struct __packed global_nvs { u8 tmps; /* 0x25 - Temperature Sensor ID */ u8 rsvd3[2]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 unused_was_pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ @@ -75,12 +73,6 @@ struct __packed global_nvs { u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ - u8 rsvd6[92]; - - /* ChromeOS specific (starts at 0x100)*/ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 915c181c2fe..24a5a7ef9a0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -11,13 +11,10 @@ #include #include #include -#include #include -#include #include #include "chip.h" #include "iobp.h" -#include "nvs.h" #include "pch.h" #include #include @@ -661,8 +658,6 @@ static void pch_lpc_add_io_resources(struct device *dev) static void pch_lpc_read_resources(struct device *dev) { - struct global_nvs *gnvs; - /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -671,11 +666,6 @@ static void pch_lpc_read_resources(struct device *dev) /* Add IO resources. */ pch_lpc_add_io_resources(dev); - - /* Allocate ACPI NVS in CBMEM */ - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs)); - if (!acpi_is_wakeup_s3() && gnvs) - memset(gnvs, 0, sizeof(struct global_nvs)); } static void pch_lpc_enable(struct device *dev) @@ -687,41 +677,6 @@ static void pch_lpc_enable(struct device *dev) pch_enable(dev); } -void southbridge_inject_dsdt(const struct device *dev) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); - - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32)gnvs); - acpigen_pop_len(); - } -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; @@ -775,7 +730,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = southbridge_fill_ssdt, - .acpi_inject_dsdt = southbridge_inject_dsdt, .acpi_name = lpc_acpi_name, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 9910658b82a..69192e6ccbe 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -25,10 +25,7 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) #include -#include -#endif /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] __unused = { @@ -755,10 +752,9 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index d212d886212..0687cec6a11 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -7,10 +7,10 @@ #include #include #include +#include #include "chip.h" #include "iobp.h" #include "pch.h" -#include "nvs.h" /* Enable clock in PCI mode */ static void serialio_enable_clock(struct resource *bar0) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9c68a54f06b..22845ec5181 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -14,12 +14,10 @@ #include #include #include +#include #include #include "me.h" #include "pch.h" -#include "nvs.h" - -static u8 smm_initialized = 0; int southbridge_io_trap_handler(int smif) { @@ -262,7 +260,6 @@ static void southbridge_smi_store(void) static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -304,24 +301,6 @@ static void southbridge_smi_apmc(void) enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); break; diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc deleted file mode 100644 index e874f3403ee..00000000000 --- a/src/superio/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -subdirs-y += aspeed -subdirs-y += fintek -subdirs-y += ite -subdirs-y += nsc -subdirs-y += nuvoton -subdirs-y += renesas -subdirs-y += serverengines -subdirs-y += smsc -subdirs-y += winbond - -ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += common/conf_mode.c -ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += common/conf_mode.c diff --git a/src/superio/common/Makefile.inc b/src/superio/common/Makefile.inc new file mode 100644 index 00000000000..46103c68d76 --- /dev/null +++ b/src/superio/common/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += conf_mode.c +ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += conf_mode.c diff --git a/src/vendorcode/amd/fsp/cezanne/FspUpd.h b/src/vendorcode/amd/fsp/cezanne/FspUpd.h new file mode 100644 index 00000000000..c9202cea9cb --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspUpd.h @@ -0,0 +1,22 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#ifdef EFI32 +# include +# include +#else +# include +#endif + +#define FSPM_UPD_SIGNATURE 0x4d5f454e415a4543 /* 'CEZANE_M' */ + +#define FSPS_UPD_SIGNATURE 0x535f454e415a4543 /* 'CEZANE_S' */ + + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h new file mode 100644 index 00000000000..338133c33c1 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -0,0 +1,26 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +/** Fsp M Configuration +**/ +typedef struct __packed { + uint16_t UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd; + /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h new file mode 100644 index 00000000000..2b7f19c6021 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -0,0 +1,23 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +typedef struct __packed { + uint16_t UpdTerminator; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig; +} FSPS_UPD; + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h new file mode 100644 index 00000000000..c477a4ff1fc --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h @@ -0,0 +1,51 @@ +/** @file + * + * C99 common FSP definitions from + * Intel Firmware Support Package External Architecture Specification v2.0 + * + * These definitions come in a format that is usable outside an EFI environment. + **/ +#ifndef FSP_H_C99_H +#define FSP_H_C99_H + +#include + +enum { + FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, + FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, + FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, + FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, + FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, + FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, + FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, + FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, +}; + +typedef enum { + EnumInitPhaseAfterPciEnumeration = 0x20, + EnumInitPhaseReadyToBoot = 0x40, + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +typedef struct __packed { + uint64_t Signature; + uint8_t Revision; + uint8_t Reserved[23]; +} FSP_UPD_HEADER; + +_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); + +typedef struct __packed { + uint8_t Revision; + uint8_t Reserved[3]; + void *NvsBufferPtr; + void *StackBase; + uint32_t StackSize; + uint32_t BootLoaderTolumSize; + uint32_t BootMode; + uint8_t Reserved1[8]; +} FSPM_ARCH_UPD; + +_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); + +#endif /* FSP_H_C99_H */ diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 491ea476dec..ee516f8482c 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,7 +39,26 @@ typedef struct __packed { /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[38]; + /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; + /** Offset 0x0130**/ uint8_t unused4; + /** Offset 0x0131**/ uint8_t DpPhyOverride; + /** Offset 0x0132**/ uint16_t EDpPhySel; + /** Offset 0x0134**/ uint8_t EDpVersion; + /** Offset 0x0135**/ uint8_t EDpTableSize; + /** Offset 0x0136**/ uint8_t DpVsPemphLevel; + /** Offset 0x0137**/ uint16_t MarginDeemPh; + /** Offset 0x0139**/ uint8_t Deemph6db4; + /** Offset 0x013A**/ uint8_t BoostAdj; + /** Offset 0x013B**/ uint16_t backlight_pwmhz; + /** Offset 0x013D**/ uint8_t pwron_digon_to_de; + /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; + /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0141**/ uint8_t pwroff_delay; + /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x0144**/ uint8_t min_allowed_bl_level; + /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index c5ad20e8810..0467090da97 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -76,7 +76,7 @@ export AGESA_CFLAGS := $(AGESA_CFLAGS) CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) -CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI +CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 824570e481e..0de2f0af55a 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -345,12 +345,17 @@ int verified_boot_should_run_oprom(struct rom_header *rom_header) int prog_locate_hook(struct prog *prog) { + static int initialized; + if (ENV_BOOTBLOCK) verified_boot_bootblock_check(); if (ENV_ROMSTAGE) { - if (prog->type == PROG_REFCODE) + if (!initialized && ((prog->type == PROG_REFCODE) || + (prog->type == PROG_POSTCAR))) { verified_boot_early_check(); + initialized = 1; + } if (CONFIG(POSTCAR_STAGE) && prog->type == PROG_POSTCAR) process_verify_list(postcar_verify_list); diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index fb11e11c8d9..ba00d7778c6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -10,6 +10,8 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c + +romstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c bootblock-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 233eb4254f2..315d693f5d6 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -45,6 +45,7 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #endif /* CONFIG_CHROMEOS_RAMOOPS */ void cbmem_add_vpd_calibration_data(void); +void chromeos_set_me_hash(u32*, int); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 74324a0cbfb..3f47a33f9a3 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -10,10 +10,7 @@ /* * chromeos_acpi_t portion of ACPI GNVS is assumed to live at - * 0x100 - 0x1000. When defining global_nvs, use check_member - * to ensure that it is properly aligned: - * - * check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + * 0x100 - 0x1000. */ #define GNVS_CHROMEOS_ACPI_OFFSET 0x100 @@ -45,7 +42,6 @@ typedef struct { } __packed chromeos_acpi_t; void chromeos_init_chromeos_acpi(chromeos_acpi_t *init); -void chromeos_set_me_hash(u32*, int); chromeos_acpi_t *chromeos_get_chromeos_acpi(void); #endif diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h deleted file mode 100644 index fddc168701d..00000000000 --- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h +++ /dev/null @@ -1,1075 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPDVPD_H__ -#define __FSPUPDVPD_H__ - -#pragma pack(push, 1) - - -#define MRC_MAX_RCOMP 3 -#define MRC_MAX_RCOMP_TARGETS 5 -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 - -typedef struct { - UINT16 RcompResistor[MRC_MAX_RCOMP]; ///< Offset 0: Reference RCOMP resistors on motherboard - UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv -} MEMORY_RCOMP; - - -typedef struct { - UINT32 VendorDeviceId; /* Vendor ID/Device ID */ - UINT16 SubSystemId; /* SubSystem ID */ - UINT8 RevisionId; /* Revision ID. 0xFF applies to all steppings */ - UINT8 FrontPanelSupport; /* Front panel support (1=yes, 2=no) */ - UINT16 NumberOfRearJacks; /* Number of Rear Jacks */ - UINT16 NumberOfFrontJacks; /* Number of Front Jacks */ -} SA_HDA_HEADER; - -typedef struct { - UINT16 VendorId; /* Codec Vendor ID */ - UINT16 DeviceId; /* Codec Device ID */ - UINT8 RevisionId; /* Revision ID of the codec. 0xFF matches any revision. */ - UINT8 SdiNo; /* SDI number, 0xFF matches any SDI. */ - UINT16 DataDwords; /* Number of data DWORDs pointed by the codec data buffer. */ - UINT32 Reserved; /* Reserved for future use. Must be set to 0. */ -} AZALIA_HEADER; - -typedef struct { - AZALIA_HEADER Header; /* AZALIA PCH header */ - UINT32 *Data; /* Pointer to the data buffer. Its length is specified in the header */ -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - -/// -/// USB Overcurrent pins definition, the values match the setting of PCH EDS, please refer to PCH EDS for more details -/// -typedef enum { - UsbOverCurrentPin0 = 0, - UsbOverCurrentPin1, - UsbOverCurrentPin2, - UsbOverCurrentPin3, - UsbOverCurrentPin4, - UsbOverCurrentPin5, - UsbOverCurrentPin6, - UsbOverCurrentPin7, - UsbOverCurrentPinSkip, - UsbOverCurrentPinMax -} USB_OVERCURRENT_PIN; - - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; - UINT8 Rsvd[3]; - UINT16 MeChipInitCrc; - UINT16 BiosChipInitCrc; -} CHIPSET_INIT_INFO; - - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - - -/** UPD data structure for FspMemoryInitApi -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT64 Signature; - -/** Offset 0x0028 - Revision - Revision version of the MemoryInitUpd Region -**/ - UINT8 Revision; - -/** Offset 0x0029 -**/ - UINT8 UnusedUpdSpace0[7]; - -/** Offset 0x0030 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE - 0x400000 : 0x400000 -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0038 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data in Memory. Default: 0 for empty channel -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x003C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data in Memory. Default: 0 for empty channel -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0040 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data in Memory. Default: 0 for empty channel -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0044 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data in Memory. Default: 0 for empty channel -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0048 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x004A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0056 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0062 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x006A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0072 - RcompResister settings - Indicates RcompReister settings: Board-dependent -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0078 - RcompTarget settings - RcompTarget settings: board-dependent -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0082 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0083 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0084 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0085 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0086 -**/ - UINT16 UnusedUpdSpace1; - -/** Offset 0x0088 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x008C - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x0090 - MMIO Size - Size of memory address space reserved for MMIO (Memory Mapped I/O) in MB. - 0x0600 : 0x0600 -**/ - UINT16 MmioSize; - -/** Offset 0x0092 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x0093 -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0096 - Enable Trace Hub - Enable/disable Trace Hub function. - $EN_DIS -**/ - UINT8 EnableTraceHub; - -/** Offset 0x0097 -**/ - UINT8 UnusedUpdSpace3[60]; - -/** Offset 0x00D3 - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0 MB, 0x01:32 MB, 0x02:64 MB, 0x03:128 MB, 0x04:256 MB, 0x05:512 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00D4 - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00D5 - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00D6 - SA GV - System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00D7 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00D8 - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00DA - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00DB -**/ - UINT8 UnusedUpdSpace4[105]; - -/** Offset 0x0144 - MMA Test Content Pointer - Pointer to MMA Test Content in Memory -**/ - UINT32 MmaTestContentPtr; - -/** Offset 0x0148 - MMA Test Content Size - Size of MMA Test Content in Memory -**/ - UINT32 MmaTestContentSize; - -/** Offset 0x014C - MMA Test Config Pointer - Pointer to MMA Test Config in Memory -**/ - UINT32 MmaTestConfigPtr; - -/** Offset 0x0150 - MMA Test Config Size - Size of MMA Test Config in Memory -**/ - UINT32 MmaTestConfigSize; - -/** Offset 0x0154 -**/ - UINT32 FspCarBase; - -/** Offset 0x0158 -**/ - UINT32 FspCarSize; - -/** Offset 0x015C - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x015D -**/ - UINT8 ReservedMemoryInitUpd[163]; -} MEMORY_INIT_UPD; - -/** UPD data structure for FspSiliconInitApi -**/ -typedef struct { - -/** Offset 0x0200 -**/ - UINT64 Signature; - -/** Offset 0x0208 - Revision - Revision version of the SiliconInitUpd Region -**/ - UINT8 Revision; - -/** Offset 0x0209 -**/ - UINT8 UnusedUpdSpace5[7]; - -/** Offset 0x0210 - Logo Pointer - Points to PEI Display Logo Image - 0 : 0 -**/ - UINT32 LogoPtr; - -/** Offset 0x0214 - Logo Size - Size of PEI Display Logo Image - 0 : 0 -**/ - UINT32 LogoSize; - -/** Offset 0x0218 - Graphics Configuration Ptr - Points to VBT - 0 : 0 -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x021C - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x021D - Enable Azalia - Enable/disable Azalia controller. - $EN_DIS -**/ - UINT8 EnableAzalia; - -/** Offset 0x021E - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 DspEnable; - -/** Offset 0x021F - Select HDAudio IoBuffer Ownership - Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers. - 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports -**/ - UINT8 IoBufferOwnership; - -/** Offset 0x0220 - Enable CIO2 Controller - Enable/disable SKYCAM CIO2 Controller. - $EN_DIS -**/ - UINT8 Cio2Enable; - -/** Offset 0x0221 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0222 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0223 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x0224 - Enable ISH Controller - Enable/disable ISH Controller. - $EN_DIS -**/ - UINT8 IshEnable; - -/** Offset 0x0225 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x0226 - HSIO HECI Messaging - Enable/Disable. 0: Disable, prevent the HSIO version check and HSIO init messages from being sent, 1: enable - $EN_DIS -**/ - UINT8 HsioMessaging; - -/** Offset 0x0227 - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. This must be enabled if Integrated Touch (iTouch) is supported. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x0228 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x022C - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0230 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0231 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0232 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x023A - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x0242 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x0252 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x025C - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x025D - Enable XHCI SSIC Eanble - Enable/disable XHCI SSIC port. - $EN_DIS -**/ - UINT8 SsicPortEnable; - -/** Offset 0x025E - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x025F - Enable SerialIo Device Mode - 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. -**/ - UINT8 SerialIoDevMode[11]; - -/** Offset 0x026A - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x026E - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x026F - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0277 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. - 0 : 0xFF -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0278 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. - 0 : 0xFF -**/ - UINT8 SciIrqSelect; - -/** Offset 0x0279 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. - 0 : 0xFF -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x027A - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x027B - AzaliaVerbTableNumEntries - Number of Entries in Azalia Verb Table -**/ - UINT8 AzaliaVerbTableNumEntries; - -/** Offset 0x027C - AzaliaVerbTablePtr - Pointer to Array of pointers to Codec Table. -**/ - UINT32 AzaliaVerbTablePtr; - -/** Offset 0x0280 - RTC CMOS RAM LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 LockDownConfigRtcLock; - -/** Offset 0x0281 - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 EnableSata; - -/** Offset 0x0282 - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0283 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x0293 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x02A3 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x02B3 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x02C3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x02CD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x02D7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x02E1 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x02EB - Enable PCIE RP - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpEnable[20]; - -/** Offset 0x02FF - Enable PCIE RP PMSCI - Indicate whether the root port power manager SCI is enabled - 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpPmSci[20]; - -/** Offset 0x0313 - Enable PCIE RP CLKREQ Support - Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqSupport[20]; - -/** Offset 0x0327 - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqNumber[20]; - -/** Offset 0x033B - Enable LAN - Enable/Disable LAN controller. - $EN_DIS -**/ - UINT8 EnableLan; - -/** Offset 0x033C - LAN LTR Programming - Enable/Disable LTR capabilty of PCH internal LAN. - $EN_DIS -**/ - UINT8 LanLtrEnable; - -/** Offset 0x033D - SATA eSATASpeedLimit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable. - $EN_DIS -**/ - UINT8 eSATASpeedLimit; - -/** Offset 0x033E - SATA RST RAID0 - Enable/Disable RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x033F - SATA RST RAID1 - Enable/Disable RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x0340 - SATA RST RAID10 - Enable/Disable RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x0341 - SATA RST RAID5 - Enable/Disable RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x0342 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize, 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x0343 - Enable PCIE RP HotPlug - Enable/disable PCIE Root Ports HogPlug. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpHotPlug[20]; - -/** Offset 0x0357 - Enable PCIE RP Function Swap - Enable/disable PCIE RP function swap. 0: disable, 1: enable. It allows BIOS to use root port function number swapping when root port of function 0 is disabled. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage. Disabling function swap may have adverse impact on power management. - $EN_DIS -**/ - UINT8 RpFunctionSwap; - -/** Offset 0x0358 - USB2 Port Over Current Configuration - Configure over current pin assignment per USB2 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x0368 - USB3 Port Over Current Configuration - Configure over current pin assignment per USB3 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x0372 - Psi1Threshold - Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x037C - Psi2Threshold - Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x0386 - Psi3Threshold - State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x0390 - Psi3Enable - Power State 3 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x0395 - Psi4Enable - Power State 4 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x039A - ImonSlope - Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x039F - ImonOffset - Imon offset correction. Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x03A4 - IccMax - VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT16 IccMax[5]; - -/** Offset 0x03AE - VrVoltageLimit - VR Voltage Limit. Range is 0-7999mV. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x03B8 - VrConfigEnable - BIOS configuration of VR 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x03BD - CPU S3 Resume Data - CPU S3 Resume Data passed from the FSP CPU S3 Resume HOB during normal boot. -**/ - UINT32 CpuS3ResumeHobData; - -/** Offset 0x03C1 - CpuS3ResumeMtrrData - Pointer CPU S3 Resume MTRR Data -**/ - UINT32 CpuS3ResumeMtrrData; - -/** Offset 0x03C5 - CpuS3ResumeMtrrDataSize - Size of S3 resume MTRR data. -**/ - UINT16 CpuS3ResumeMtrrDataSize; - -/** Offset 0x03C7 - Lock Down Config Global Smi - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Value 0: Disable, 1: Enable. - $EN_DIS -**/ - UINT8 LockDownConfigGlobalSmi; - -/** Offset 0x03C8 - Lock Down Config Bios Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. Top Swap bit and the General Control and Status Registers Boot BIOS Straps. Value 0: Disable, 1: Enable. - $EN_DIS -**/ - UINT8 LockDownConfigBiosInterface; - -/** Offset 0x03C9 - Lock Down Config Bios Lock - When enabled, the BIOS Region can only be modified from SMM after EndOfDxe protocol is installed. Value 0: Disable, 1: Enable. - $EN_DIS -**/ - UINT8 LockDownConfigBiosLock; - -/** Offset 0x03CA - Lock Down Config Spi Eiss - Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also in order to write to BIOS regions of SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The BIOS must set the EISS bit while BIOS Guard support is enabled. Value 0: Clear EISS bit, 1: Set EISS bit. - $EN_DIS -**/ - UINT8 LockDownConfigSpiEiss; - -/** Offset 0x03CB - Subsystem Vendor ID - Subsystem Vendor ID of the PCH devices. -**/ - UINT16 PchConfigSubSystemVendorId; - -/** Offset 0x03CD - Subsystem ID - Subsystem ID of the PCH devices. -**/ - UINT16 PchConfigSubSystemId; - -/** Offset 0x03CF - Wol Enable Override - Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. Value 0: Disable, 1: Enable. - $EN_DIS -**/ - UINT8 WakeConfigWolEnableOverride; - -/** Offset 0x03D0 - Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. Value 0: Disable, 1: Enable. - $EN_DIS -**/ - UINT8 WakeConfigPcieWakeFromDeepSx; - -/** Offset 0x03D1 - Power Management DeepSxPolicy - Deep Sx Policy. Values 0: PchDeepSxPolDisable, 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn. - 0 : 0x06 -**/ - UINT8 PmConfigDeepSxPol; - -/** Offset 0x03D2 - Power Management SlpS3MinAssert - SLP_S3 Minimum Assertion Width Policy. Values 0: PchSlpS360us, 1: PchSlpS31ms, 2: PchSlpS350ms, 3: PchSlpS32s. - 0 : 0x03 -**/ - UINT8 PmConfigSlpS3MinAssert; - -/** Offset 0x03D3 - Power Management SlpS4MinAssert - SLP_S4 Minimum Assertion Width Policy. Values 0: PchSlpS4PchTime, 1: PchSlpS41s, 2: PchSlpS42s, 3: PchSlpS43s, 4: PchSlpS44s. - 0 : 0x04 -**/ - UINT8 PmConfigSlpS4MinAssert; - -/** Offset 0x03D4 - Power Management SlpSusMinAssert - SLP_SUS Minimum Assertion Width Policy. Values 0: PchSlpSus0ms, 1: PchSlpSus500ms, 2: PchSlpSus1s, 3: PchSlpSus4s. - 0 : 0x03 -**/ - UINT8 PmConfigSlpSusMinAssert; - -/** Offset 0x03D5 - Power Management SlpAMinAssert - SLP_A Minimum Assertion Width Policy. Values 0: PchSlpA0ms, 1: PchSlpA4s, 2: PchSlpA98ms, 3: PchSlpA2s. - 0 : 0x03 -**/ - UINT8 PmConfigSlpAMinAssert; - -/** Offset 0x03D6 - Power Management Pci Clock Run - This member describes whether or not the PCI ClockRun feature of PCH should be enabled. Values 0: Disabled, 1: Enabled - $EN_DIS -**/ - UINT8 PmConfigPciClockRun; - -/** Offset 0x03D7 - Power Management SLP_X Stretching After SUS Well - SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled - $EN_DIS -**/ - UINT8 PmConfigSlpStrchSusUp; - -/** Offset 0x03D8 - Power Management Power Button Override Period - PCH power button override period. Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s. - 0 : 0x05 -**/ - UINT8 PmConfigPwrBtnOverridePeriod; - -/** Offset 0x03D9 - Power Management Power Reset Power Cycle Duration - Reset Power Cycle Duration could be customized in the unit of second. PCH HW default is 4 seconds, and range is 1~4 seconds. Values: 0x0 - 0s, 0x1 - 1s, 0x2 - 2s, 0x3 - 3s, 0x4 - 4s. - 0 : 0x04 -**/ - UINT8 PmConfigPwrCycDur; - -/** Offset 0x03DA - PCH Serial IRQ Configuration - Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - $EN_DIS -**/ - UINT8 SerialIrqConfigSirqEnable; - -/** Offset 0x03DB - PCH Serial IRQ Mode Select - Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode. - 0 : 0x01 -**/ - UINT8 SerialIrqConfigSirqMode; - -/** Offset 0x03DC - PCH Serial IRQ Start Frame Pulse Width - Start Frame Pulse Width. Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0 : 0x02 -**/ - UINT8 SerialIrqConfigStartFramePulse; - -/** Offset 0x03DD - PSF Unlock - The PSF registers will be locked before 3rd party code execution. This policy unlock the PSF space. NOTE: Do not set this policy "PsfUnlock" unless necessary. - $EN_DIS -**/ - UINT8 PsfUnlock; - -/** Offset 0x03DE - IO voltage for I2C controllers - Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. -**/ - UINT8 SerialIoI2cVoltage[6]; - -/** Offset 0x03E4 - Enable 8254 Static Clock Gating in early POST time - Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this. - $EN_DIS -**/ - UINT8 Early8254ClockGatingEnable; - -/** Offset 0x03E5 - Enable VR specific mailbox command - VR specific mailbox commands, 000b: no VR specific command sent, 001b: A VR mailbox command specifically for the MPS IMPV8 VR will be sent, 010b: VR specific command sent for PS4 exit issue, 011b: VR specific command sent for both MPS IMPV8 & PS4 exit issue. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x03E6 -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x03E7 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x03E8 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x03E9 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x03EA -**/ - UINT8 FastPkgCRampDisable; - -/** Offset 0x03EB -**/ - UINT8 ReservedSiliconInitUpd[15]; -} SILICON_INIT_UPD; - -#define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. -**/ -typedef struct { - -/** Offset 0x0000 -**/ - UINT64 Signature; - -/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build -**/ - UINT8 Revision; - -/** Offset 0x0009 -**/ - UINT8 ReservedUpd0[7]; - -/** Offset 0x0010 - MemoryInitUpdOffset - This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION -**/ - UINT32 MemoryInitUpdOffset; - -/** Offset 0x0014 - SiliconInitUpdOffset - This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION -**/ - UINT32 SiliconInitUpdOffset; - -/** Offset 0x0018 -**/ - UINT64 ReservedUpd1; - -/** Offset 0x0020 -**/ - MEMORY_INIT_UPD MemoryInitUpd; - -/** Offset 0x0200 -**/ - SILICON_INIT_UPD SiliconInitUpd; - -/** Offset 0x03FA - RegionTerminator - This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. -**/ - UINT16 RegionTerminator; -} UPD_DATA_REGION; - -#define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */ -#define FSP_IMAGE_REV 0x01090000 - -/** VPD data structure -**/ -typedef struct { - -/** Offset 0x0000 -**/ - UINT64 PcdVpdRegionSign; - -/** Offset 0x0008 - PcdImageRevision - This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. -**/ - UINT32 PcdImageRevision; - -/** Offset 0x000C -**/ - UINT32 PcdUpdRegionOffset; - -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[32]; - -/** Offset 0x0030 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0031 - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0032 -**/ - UINT32 PcdSerialIoUartInputClock; -} VPD_DATA_REGION; - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 14d29dbcaac..d9cbc5b832e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -102,7 +102,21 @@ typedef struct { /** Offset 0x0055 - Reserved **/ - UINT8 Reserved1[12]; + UINT8 Reserved1[3]; + +/** Offset 0x0058 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x005C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0060 - Reserved +**/ + UINT8 Reserved2; /** Offset 0x0061 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. @@ -124,7 +138,7 @@ typedef struct { /** Offset 0x0072 - Reserved **/ - UINT8 Reserved2[34]; + UINT8 Reserved3[34]; /** Offset 0x0094 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for @@ -146,7 +160,7 @@ typedef struct { /** Offset 0x00AF - Reserved **/ - UINT8 Reserved3[26]; + UINT8 Reserved4[26]; /** Offset 0x00C9 - Enable SATA Enable/disable SATA controller. @@ -168,7 +182,7 @@ typedef struct { /** Offset 0x00D2 - Reserved **/ - UINT8 Reserved4[35]; + UINT8 Reserved5[35]; /** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, @@ -191,7 +205,7 @@ typedef struct { /** Offset 0x010A - Reserved **/ - UINT8 Reserved5[65]; + UINT8 Reserved6[65]; /** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. @@ -200,7 +214,7 @@ typedef struct { /** Offset 0x0152 - Reserved **/ - UINT8 Reserved6[2]; + UINT8 Reserved7[2]; /** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -236,7 +250,7 @@ typedef struct { /** Offset 0x01C5 - Reserved **/ - UINT8 Reserved7[7]; + UINT8 Reserved8[7]; /** Offset 0x01CC - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available @@ -258,7 +272,7 @@ typedef struct { /** Offset 0x0214 - Reserved **/ - UINT8 Reserved8[192]; + UINT8 Reserved9[192]; /** Offset 0x02D4 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, @@ -310,7 +324,7 @@ typedef struct { /** Offset 0x033C - Reserved **/ - UINT8 Reserved9[80]; + UINT8 Reserved10[80]; /** Offset 0x038C - Enable LAN Enable/disable LAN controller. @@ -320,7 +334,7 @@ typedef struct { /** Offset 0x038D - Reserved **/ - UINT8 Reserved10[11]; + UINT8 Reserved11[11]; /** Offset 0x0398 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. @@ -329,7 +343,7 @@ typedef struct { /** Offset 0x03B4 - Reserved **/ - UINT8 Reserved11[81]; + UINT8 Reserved12[81]; /** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX @@ -345,7 +359,7 @@ typedef struct { /** Offset 0x0407 - Reserved **/ - UINT8 Reserved12; + UINT8 Reserved13; /** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage This field has 1us resolution. When value is 0 Transition to 0V is disabled. @@ -354,7 +368,7 @@ typedef struct { /** Offset 0x040A - Reserved **/ - UINT8 Reserved13[50]; + UINT8 Reserved14[50]; /** Offset 0x043C - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -377,7 +391,7 @@ typedef struct { /** Offset 0x043F - Reserved **/ - UINT8 Reserved14; + UINT8 Reserved15; /** Offset 0x0440 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) @@ -394,9 +408,9 @@ typedef struct { /** Offset 0x0448 - Reserved **/ - UINT8 Reserved15[174]; + UINT8 Reserved16[172]; -/** Offset 0x04F6 - CdClock Frequency selection +/** Offset 0x04F4 - CdClock Frequency selection 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, @@ -404,119 +418,119 @@ typedef struct { **/ UINT8 CdClock; -/** Offset 0x04F7 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x04F5 - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x04F8 - Enable D3 Hot in TCSS +/** Offset 0x04F6 - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x04F9 - Reserved +/** Offset 0x04F7 - Reserved **/ - UINT8 Reserved16[3]; + UINT8 Reserved17; -/** Offset 0x04FC - TypeC port GPIO setting +/** Offset 0x04F8 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl = AlderLake) **/ UINT32 IomTypeCPortPadCfg[8]; -/** Offset 0x051C - Reserved +/** Offset 0x0518 - Reserved **/ - UINT8 Reserved17[8]; + UINT8 Reserved18[8]; -/** Offset 0x0524 - Enable D3 Cold in TCSS +/** Offset 0x0520 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x0525 - Reserved +/** Offset 0x0521 - Reserved **/ - UINT8 Reserved18[8]; + UINT8 Reserved19[8]; -/** Offset 0x052D - Enable VMD controller +/** Offset 0x0529 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x052E - Reserved +/** Offset 0x052A - Reserved **/ - UINT8 Reserved19[120]; + UINT8 Reserved20[120]; -/** Offset 0x05A6 - TCSS Aux Orientation Override Enable +/** Offset 0x05A2 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x05A8 - TCSS HSL Orientation Override Enable +/** Offset 0x05A4 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x05AA - Reserved +/** Offset 0x05A6 - Reserved **/ - UINT8 Reserved20[2]; + UINT8 Reserved21; -/** Offset 0x05AC - ITBT Root Port Enable +/** Offset 0x05A7 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable 0:Disable, 1:Enable **/ UINT8 ITbtPcieRootPortEn[4]; -/** Offset 0x05B0 - Reserved +/** Offset 0x05AB - Reserved **/ - UINT8 Reserved21[2]; + UINT8 Reserved22[3]; -/** Offset 0x05B2 - ITbtConnectTopology Timeout value +/** Offset 0x05AE - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x05B4 - Reserved +/** Offset 0x05B0 - Reserved **/ - UINT8 Reserved22[7]; + UINT8 Reserved23[7]; -/** Offset 0x05BB - Enable/Disable PTM +/** Offset 0x05B7 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x05BF - Reserved +/** Offset 0x05BB - Reserved **/ - UINT8 Reserved23[200]; + UINT8 Reserved24[200]; -/** Offset 0x0687 - Skip Multi-Processor Initialization +/** Offset 0x0683 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0688 - Reserved +/** Offset 0x0684 - Reserved **/ - UINT8 Reserved24[8]; + UINT8 Reserved25[8]; -/** Offset 0x0690 - CpuMpPpi +/** Offset 0x068C - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x0694 - Reserved +/** Offset 0x0690 - Reserved **/ - UINT8 Reserved25[70]; + UINT8 Reserved26[74]; /** Offset 0x06DA - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -526,7 +540,7 @@ typedef struct { /** Offset 0x06DB - Reserved **/ - UINT8 Reserved26[33]; + UINT8 Reserved27[33]; /** Offset 0x06FC - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -535,7 +549,7 @@ typedef struct { /** Offset 0x06FD - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved28[2]; /** Offset 0x06FF - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -559,7 +573,7 @@ typedef struct { /** Offset 0x070D - Reserved **/ - UINT8 Reserved28[2]; + UINT8 Reserved29[2]; /** Offset 0x070F - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -570,7 +584,7 @@ typedef struct { /** Offset 0x0710 - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved30[2]; /** Offset 0x0712 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -586,7 +600,7 @@ typedef struct { /** Offset 0x072F - Reserved **/ - UINT8 Reserved30[56]; + UINT8 Reserved31[56]; /** Offset 0x0767 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -600,7 +614,7 @@ typedef struct { /** Offset 0x079F - Reserved **/ - UINT8 Reserved31[196]; + UINT8 Reserved32[196]; /** Offset 0x0863 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. @@ -615,7 +629,7 @@ typedef struct { /** Offset 0x0880 - Reserved **/ - UINT8 Reserved32[5]; + UINT8 Reserved33[5]; /** Offset 0x0885 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -625,7 +639,7 @@ typedef struct { /** Offset 0x0886 - Reserved **/ - UINT8 Reserved33[91]; + UINT8 Reserved34[91]; /** Offset 0x08E1 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -641,7 +655,7 @@ typedef struct { /** Offset 0x0919 - Reserved **/ - UINT8 Reserved34[28]; + UINT8 Reserved35[28]; /** Offset 0x0935 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. @@ -650,7 +664,7 @@ typedef struct { /** Offset 0x0951 - Reserved **/ - UINT8 Reserved35[132]; + UINT8 Reserved36[132]; /** Offset 0x09D5 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -660,7 +674,7 @@ typedef struct { /** Offset 0x09D6 - Reserved **/ - UINT8 Reserved36[50]; + UINT8 Reserved37[50]; /** Offset 0x0A08 - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -674,7 +688,7 @@ typedef struct { /** Offset 0x0A20 - Reserved **/ - UINT8 Reserved37[62]; + UINT8 Reserved38[62]; /** Offset 0x0A5E - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -688,7 +702,7 @@ typedef struct { /** Offset 0x0A78 - Reserved **/ - UINT8 Reserved38[16]; + UINT8 Reserved39[16]; /** Offset 0x0A88 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -708,7 +722,7 @@ typedef struct { /** Offset 0x0A8A - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved40; /** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -719,7 +733,7 @@ typedef struct { /** Offset 0x0A8C - Reserved **/ - UINT8 Reserved40[93]; + UINT8 Reserved41[93]; /** Offset 0x0AE9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power @@ -731,7 +745,7 @@ typedef struct { /** Offset 0x0AEA - Reserved **/ - UINT8 Reserved41[318]; + UINT8 Reserved42[318]; /** Offset 0x0C28 - RpPtmBytes **/ @@ -739,7 +753,7 @@ typedef struct { /** Offset 0x0C2C - Reserved **/ - UINT8 Reserved42[95]; + UINT8 Reserved43[95]; /** Offset 0x0C8B - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport @@ -749,7 +763,7 @@ typedef struct { /** Offset 0x0C8C - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved44; /** Offset 0x0C8D - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -767,7 +781,7 @@ typedef struct { /** Offset 0x0C8E - Reserved **/ - UINT8 Reserved44[24]; + UINT8 Reserved45[24]; /** Offset 0x0CA6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; @@ -778,7 +792,7 @@ typedef struct { /** Offset 0x0CA7 - Reserved **/ - UINT8 Reserved45[8]; + UINT8 Reserved46[8]; /** Offset 0x0CAF - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which @@ -790,7 +804,7 @@ typedef struct { /** Offset 0x0CB0 - Reserved **/ - UINT8 Reserved46[34]; + UINT8 Reserved47[34]; /** Offset 0x0CD2 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable @@ -800,7 +814,7 @@ typedef struct { /** Offset 0x0CD3 - Reserved **/ - UINT8 Reserved47[196]; + UINT8 Reserved48[196]; /** Offset 0x0D97 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. @@ -822,7 +836,7 @@ typedef struct { /** Offset 0x0D9A - Reserved **/ - UINT8 Reserved48[2]; + UINT8 Reserved49[2]; /** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -836,7 +850,7 @@ typedef struct { /** Offset 0x0E0C - Reserved **/ - UINT8 Reserved49[313]; + UINT8 Reserved50[313]; /** Offset 0x0F45 - LpmStateEnableMask **/ @@ -844,7 +858,7 @@ typedef struct { /** Offset 0x0F46 - Reserved **/ - UINT8 Reserved50[698]; + UINT8 Reserved51[698]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -865,7 +879,7 @@ typedef struct { /** Offset 0x1200 **/ - UINT8 UnusedUpdSpace44[6]; + UINT8 UnusedUpdSpace45[6]; /** Offset 0x1206 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FirmwareVersionInfoHob.h deleted file mode 100644 index 0dbafffa868..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @file - Header file for Firmware Version Information - - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
- - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h deleted file mode 100644 index e03408d5a85..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4E43 /* 'CNLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E43 /* 'CNLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4E43 /* 'CNLUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h deleted file mode 100644 index 05210d6801c..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ /dev/null @@ -1,2866 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0058 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x005A - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0066 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0082 - RcompResister settings - Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design - Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide - the appropriate values. -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0088 - RcompTarget settings - RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines, - otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values. -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0092 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0093 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0094 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0095 - MRC Fast Boot - Enables/Disable the MRC fast path thru the MRC - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0096 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x0097 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x0098 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x009C - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00A0 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00A2 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00A3 -**/ - UINT8 UnusedUpdSpace0[2]; - -/** Offset 0x00A5 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x00A6 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00AA - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] - have the same setting - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x00AC - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x00AF - PchPreMemRsvd - Reserved for PCH Pre-Mem Reserved - $EN_DIS -**/ - UINT8 PchPreMemRsvd[9]; - -/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, - 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, - 0xFD:56MB, 0xFE:60MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x00B9 - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x00BA - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x00BB - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x00BC - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, - 2=FixedMid, 3=FixedHigh, and 4=Enabled. - 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x00BD -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x00BE - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, - i.e. divide by 133 or 100 - 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133, - 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00C0 - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00C2 - Mid Frequency - SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvMid; - -/** Offset 0x00C4 - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00C5 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00C6 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00C7 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00C8 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x00C9 -**/ - UINT8 UnusedUpdSpace2[15]; - -/** Offset 0x00D8 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00D9 - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00DA - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00DC - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00DD - QCLK Odd Ratio - Adds 133 or 100 MHz to QCLK frequency, depending on RefClk - $EN_DIS -**/ - UINT8 OddRatioMode; - -/** Offset 0x00DE - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00DF - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00E0 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00E1 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00E2 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00E4 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00E6 - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00E8 - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00EA - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00EB - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00EC - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00ED - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00EE - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00EF - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00F0 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00F1 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00F2 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00F3 - CPU Trace Hub Mode - Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' - trace hub functionality. - 0: Disable, 1:Target Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x00F4 - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x00F5 - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command - Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message - to disable peci reset on C10 exit. The default value is 0: Disable for CNL, - and 1: Enable for all other CPU's - $EN_DIS -**/ - UINT8 PeciC10Reset; - -/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command - Enable or Disable Peci Sx Reset command; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PeciSxReset; - -/** Offset 0x00F8 -**/ - UINT8 UnusedUpdSpace3[4]; - -/** Offset 0x00FC - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x00FD - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x00FE - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x00FF -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x0100 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x0104 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x0108 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x010C - SG dGPU Power Delay - SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 SgDelayAfterPwrEn; - -/** Offset 0x010E - SG dGPU Reset Delay - SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 SgDelayAfterHoldReset; - -/** Offset 0x0110 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x0113 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x0114 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x0115 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x0116 - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x0117 - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x0118 - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x0119 - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x011A - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x011B - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x011C - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x011D - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x011E - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x011F - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0120 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0121 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0122 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0x1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0125 -**/ - UINT8 UnusedUpdSpace5[3]; - -/** Offset 0x0128 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x0130 - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0138 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping - 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction - caused by high package temperatures for processors that implement the Intel Thermal - Velocity Boost (TVB) feature - 0: Disabled, 1: Enabled -**/ - UINT8 TvbRatioClipping; - -/** Offset 0x0145 - Thermal Velocity Boost voltage optimization - 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations - for processors that implement the Intel Thermal Velocity Boost (TVB) feature. - 0: Disabled, 1: Enabled -**/ - UINT8 TvbVoltageOptimization; - -/** Offset 0x0146 -**/ - UINT8 UnusedUpdSpace6[2]; - -/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x0152 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0156 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0176 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0177 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0178 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x017A - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x017E - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0182 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1 - Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2 - Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3 - Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT8 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x01E3 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x01E4 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x01E5 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x01E6 - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x01E7 - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01EB - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01ED - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01F0 - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01F1 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01F2 - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01F3 - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01F4 - GT unslice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtusVoltageMode; - -/** Offset 0x01F5 - voltage offset applied to GT unslice - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOffset; - -/** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusVoltageOverride; - -/** Offset 0x01F9 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtusExtraTurboVoltage; - -/** Offset 0x01FB - Maximum GTus turbo ratio override - 0(Default)=Minimal, 60=Maximum -**/ - UINT8 GtusMaxOcRatio; - -/** Offset 0x01FC - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[4]; - -/** Offset 0x0200 - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x0202 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x0203 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x0204 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x0205 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x0206 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x0207 - Program Cache Attributes - Program Cache Attributes; 0: Program; 1: Disable Program. - $EN_DIS -**/ - UINT8 DisableMtrrProgram; - -/** Offset 0x0208 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-255 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x0209 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x020A - CPU ratio value - CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled. -**/ - UINT8 CpuRatio; - -/** Offset 0x020B - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x020C - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x020D - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x020E - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x020F - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x0210 - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x0211 - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x0212 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x0213 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x0214 - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x0216 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x0218 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x021A - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x021B - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x021C - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x021E - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x0220 - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x0222 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0223 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x0224 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x0225 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x0226 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x0227 - DpSscMarginEnable TYPE:{Combo - Enable/Disable. 0: Disable, Use default DisplayPort SSC modulation range 0.5% down - spread, 1: Enable DisplayPort SSC range reduction. Note this should only be used - on systems that exceeds allowed SSC modulation range as defined in VESA's spec - $EN_DIS -**/ - UINT8 DpSscMarginEnable; - -/** Offset 0x0228 - PrmrrSize - 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 -**/ - UINT32 PrmrrSize; - -/** Offset 0x022C - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x0230 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x0234 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x0238 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x0240 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0244 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0248 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x024C - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0250 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0258 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0260 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x0261 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[3]; - -/** Offset 0x0264 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[3]; - -/** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0451 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x0452 - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x0453 - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x0454 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x0456 - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0458 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x045C - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0460 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0461 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x0462 - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x0463 - ReservedPchPreMem - Reserved for Pch Pre-Mem - $EN_DIS -**/ - UINT8 ReservedPchPreMem[13]; - -/** Offset 0x0470 - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x0471 - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0472 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0473 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0474 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0475 - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0476 - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0477 - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x0478 - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x0479 - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x047A - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x047B - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x047C - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x047D - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x047E - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x047F - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x0480 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x0481 - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x0482 - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x0483 - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x0484 - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x0485 - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x0486 - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x0487 - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x0488 - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x0489 - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x048A - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x048B - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x048C - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x048D - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x048E - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x048F - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x0490 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x0491 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x0492 - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x0493 - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x0494 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x0495 - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x0496 - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x0497 - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x0498 - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x0499 - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x049A - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x049B - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x049C - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x049D - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x049E - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x049F - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x04A0 - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x04A1 - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x04A2 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x04A5 - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x04A6 - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x04A7 - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x04A8 - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x04AA - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x04AB - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x04AC - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x04AD - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x04B0 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6 -**/ - UINT16 ChHashMask; - -/** Offset 0x04B2 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x04B6 - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x04B7 - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x04B8 - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x04BA - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x04BC - CMD Slew Rate Training - Enable/Disable CMD Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x04BD - CMD Drive Strength and Tx Equalization - Enable/Disable CMD Drive Strength and Tx Equalization - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x04BE - CMD Normalization - Enable/Disable CMD Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training - Enable/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x04C0 - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x04C1 - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x04C2 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x04C3 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x04C4 - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x04C5 - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (222= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x04C7 - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (0= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x04C9 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x04CA - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x04CB - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x04CC - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x04CD - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x04CE - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x04CF - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x04D0 - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x04D1 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x04D2 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x04D3 - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x04D4 - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x04D5 - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x04D6 - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x04D7 - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x04D8 - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x04D9 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x04DA - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x04DB - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x04DC - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x04DD - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x04DE - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x04DF - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x04E0 - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x04E1 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x04E2 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x04E3 - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x04E4 - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x04E5 - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x04E6 - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x04E7 - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x04E8 - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x04E9 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x04EA - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x04EB - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x04EC - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x04ED - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Default is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x04EE - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x04EF - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x04F0 - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x04F1 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x04F2 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x04F3 - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x04F4 - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x04F5 - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x04F6 - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x04F7 - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x04F8 - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x04F9 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x04FA - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x04FB - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x04FC - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x04FD - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x04FE - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x04FF - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x0500 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x0501 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x0502 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x0503 - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x0504 - GDXC MOT enable - GDXC MOT enable. - $EN_DIS -**/ - UINT8 GdxcEnable; - -/** Offset 0x0505 - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x0506 - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x0507 - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x0508 - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x0509 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x050A - LpDdrDqDqsReTraining - Enables/Disable LpDdrDqDqsReTraining - $EN_DIS -**/ - UINT8 LpDdrDqDqsReTraining; - -/** Offset 0x050B - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x050D - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x050E - BER Support - Enable/Disable the Rank Margin Tool interpolation/extrapolation. - 0:Disable, 1:Enable -**/ - UINT8 EnBER; - -/** Offset 0x050F - PEG IMR support - This option configures the IMR support for PEG.(def=Disable) - $EN_DIS -**/ - UINT8 PegImrEnable; - -/** Offset 0x0510 - PEG IMR size - The size of IMR to be allocated for PEG EndPoint device.PegImrSize can vary from - 0 to 1024 MB in steps of 2 power N where N = 0 to 10 -**/ - UINT16 PegImrSize; - -/** Offset 0x0512 - PEG Root Port Selection - The Root Port for which the IMR to be allocated -**/ - UINT8 PegImrRpSelection; - -/** Offset 0x0513 - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x0514 - Throttler CKEMin Timer - LPDDR - Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + - BYTE_LENGTH (4). Default is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x0515 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x0516 - MRC Force training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x0517 -**/ - UINT8 ReservedFspmUpd[8]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0520 -**/ - UINT32 Signature; - -/** Offset 0x0524 - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x0525 - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x0527 - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0528 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0529 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x052A - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x0537 - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0539 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x053B - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x053C - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x053D - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x0551 - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x0565 - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x0579 -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x0582 - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x0583 - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:Rank Margin Tool, 1:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x0584 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x0585 - Delta T12 Power Cycle Delay required in ms - Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate - T12 Delay to max 500ms - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelayPreMem; - -/** Offset 0x0587 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[9]; - -/** Offset 0x0590 - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x0592 - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x0594 - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x0595 - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[3]; - -/** Offset 0x0598 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x0599 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x059A - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x059B - ChipsetInit HECI message - DEPRECATED - $EN_DIS -**/ - UINT8 ChipsetInitMessage; - -/** Offset 0x059C - Bypass ChipsetInit sync reset. - DEPRECATED - $EN_DIS -**/ - UINT8 BypassPhySyncReset; - -/** Offset 0x059D - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x059E - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x059F - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x05A0 - Retry mechanism for HECI APIs - Test, 0: disable, 1: enable, Enable/Disable HECI retry. - $EN_DIS -**/ - UINT8 DisableHeciRetry; - -/** Offset 0x05A1 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x05A2 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x05A3 - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x05A4 - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x05A5 - tRd2RdSG - Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdSG; - -/** Offset 0x05A6 - tRd2RdDG - Delay between Read-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDG; - -/** Offset 0x05A7 - tRd2RdDR - Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDR; - -/** Offset 0x05A8 - tRd2RdDD - Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2RdDD; - -/** Offset 0x05A9 - tWr2RdSG - Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. -**/ - UINT8 tWr2RdSG; - -/** Offset 0x05AA - tWr2RdDG - Delay between Write-to-Read commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDG; - -/** Offset 0x05AB - tWr2RdDR - Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDR; - -/** Offset 0x05AC - tWr2RdDD - Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2RdDD; - -/** Offset 0x05AD - tWr2WrSG - Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrSG; - -/** Offset 0x05AE - tWr2WrDG - Delay between Write-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDG; - -/** Offset 0x05AF - tWr2WrDR - Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDR; - -/** Offset 0x05B0 - tWr2WrDD - Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tWr2WrDD; - -/** Offset 0x05B1 - tRd2WrSG - Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrSG; - -/** Offset 0x05B2 - tRd2WrDG - Delay between Read-to-Write commands in different Bank Group for DDR4. All other - DDR technologies should set this equal to SG. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDG; - -/** Offset 0x05B3 - tRd2WrDR - Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDR; - -/** Offset 0x05B4 - tRd2WrDD - Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. -**/ - UINT8 tRd2WrDD; - -/** Offset 0x05B5 - tRRD_L - Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 -**/ - UINT8 tRRD_L; - -/** Offset 0x05B6 - tRRD_S - Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: - AUTO, max: 31 -**/ - UINT8 tRRD_S; - -/** Offset 0x05B7 - tWTR_L - Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: - AUTO, max: 60 -**/ - UINT8 tWTR_L; - -/** Offset 0x05B8 - tWTR_S - Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. - 0: AUTO, max: 28 -**/ - UINT8 tWTR_S; - -/** Offset 0x05B9 -**/ - UINT8 ReservedFspmTestUpd[3]; -} FSP_M_TEST_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x051F -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x0520 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x05BC -**/ - UINT32 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h deleted file mode 100644 index c9024eb3422..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ /dev/null @@ -1,3331 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x0024 - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0028 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x002C - Enable Device 4 - The Device 4 default value is 1: Enable for WHL, and 0: disable for - all other CPU's - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x002D - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x002E -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0031 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0032 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0033 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x0034 - Show SPI controller - Enable/disable to show SPI controller. - $EN_DIS -**/ - UINT8 ShowSpiController; - -/** Offset 0x0035 -**/ - UINT8 UnusedUpdSpace1[3]; - -/** Offset 0x0038 - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x003C - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0040 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0041 - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0042 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x004A - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x0052 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x0062 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x006C - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x006D -**/ - UINT8 UnusedUpdSpace2[2]; - -/** Offset 0x006F - Enable SerialIo Device Mode - 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable - SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device - mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, - and so on. -**/ - UINT8 SerialIoDevMode[12]; - -/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x007F - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x0080 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x0088 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x0089 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x008A - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x008B - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x008C - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x008D - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x0092 - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x0093 - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0094 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2AfePetxiset[16]; - -/** Offset 0x00A4 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2AfeTxiset[16]; - -/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2AfePredeemp[16]; - -/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2AfePehalfbit[16]; - -/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x00FC - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x00FD - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x00FE - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x00FF - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x0100 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0101 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x0102 - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting - 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. - $EN_DIS -**/ - UINT8 PchHdaSndwBufferRcomp; - -/** Offset 0x0108 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x010C - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x0110 - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x0114 - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x0115 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounce; - -/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x011A - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x011B - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x011F - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x0120 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x0124 - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x0128 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x0129 - PchPostMemRsvd - Reserved for PCH Post-Mem - $EN_DIS -**/ - UINT8 PchPostMemRsvd[28]; - -/** Offset 0x0145 - Enable Ufs Controller - Enable/disable Ufs 2.0 Controller. - $EN_DIS -**/ - UINT8 ScsUfsEnabled; - -/** Offset 0x0146 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 PchCnviMode; - -/** Offset 0x0147 - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x0148 - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PchUsb2PhySusPgEnable; - -/** Offset 0x0149 - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x014A -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x014B - CNVi MfUart1 Type - This option configures Uart type which connects to MfUart1 - 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads -**/ - UINT8 PchCnviMfUart1Type; - -/** Offset 0x014C - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x014D - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x014E -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x014F - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x0150 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x0151 - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x0152 - SLP_S0 VM Dynamic Control - SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0VmRuntimeControl; - -/** Offset 0x0153 - SLP_S0 VM 0.70V Support - SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm070VSupport; - -/** Offset 0x0154 - SLP_S0 VM 0.75V Support - SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmSlpS0Vm075VSupport; - -/** Offset 0x0155 - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x0156 - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. - $EN_DIS -**/ - UINT8 WatchDog; - -/** Offset 0x0157 - ASF Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. - $EN_DIS -**/ - UINT8 AsfEnabled; - -/** Offset 0x0158 - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x0159 - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x015A - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x015B - OS Timer - 16 bits Value, Set OS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x015D - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x015F - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0160 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0161 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x0162 -**/ - UINT8 UnusedUpdSpace5[1]; - -/** Offset 0x0163 - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x017B - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x018B - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x019B - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x01B3 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x01CB - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x01FC - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping - CPU and 1 for all other CPUs. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 SlpS0WithGbeSupport; - -/** Offset 0x01FD -**/ - UINT8 UnusedUpdSpace6[3]; - -/** Offset 0x0200 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x0201 - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x0202 - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x0206 - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x020A - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x020E - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x0216 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0217 - CdClock Frequency selection - 0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz - 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0219 -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x021A - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOutDeprecated; - -/** Offset 0x021C - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddressDeprecated[3]; - -/** Offset 0x0228 - Enable or disable eDP device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortEdp; - -/** Offset 0x0229 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x022A - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x022B - Enable or disable HPD of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDHpd; - -/** Offset 0x022C - Enable or disable HPD of DDI port F - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortFHpd; - -/** Offset 0x022D - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x022E - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x022F - Enable or disable DDC of DDI port D - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortDDdc; - -/** Offset 0x0230 - Enable or disable DDC of DDI port F - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 DdiPortFDdc; - -/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock in S3 resume due to GOP absent - $EN_DIS -**/ - UINT8 SkipS3CdClockInit; - -/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms - DEPRECATED - 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay -**/ - UINT16 DeltaT12PowerCycleDelay; - -/** Offset 0x0234 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0238 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x023C - SaPostMemProductionRsvd - Reserved for SA Post-Mem Production - $EN_DIS -**/ - UINT8 SaPostMemProductionRsvd[35]; - -/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for - Alpine ridge -**/ - UINT8 PcieRootPortGen2PllL1CgDisable[24]; - -/** Offset 0x0277 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x0278 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable[5]; - -/** Offset 0x027D - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable[5]; - -/** Offset 0x0282 - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT8 ImonSlope[5]; - -/** Offset 0x0287 - Imon offset correction - DEPRECATED -**/ - UINT8 ImonOffset[5]; - -/** Offset 0x028C - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable[5]; - -/** Offset 0x0291 - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable[5]; - -/** Offset 0x0296 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow[5]; - -/** Offset 0x029B - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock[5]; - -/** Offset 0x02A0 - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x02A1 - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x02A2 - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableIa; - -/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain - Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForIa; - -/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain - Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForGt; - -/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain - Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForSa; - -/** Offset 0x02A7 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit[5]; - -/** Offset 0x02B1 - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline[5]; - -/** Offset 0x02BB -**/ - UINT8 UnusedUpdSpace8[10]; - -/** Offset 0x02C5 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline[5]; - -/** Offset 0x02CF - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold[5]; - -/** Offset 0x02D9 - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold[5]; - -/** Offset 0x02E3 - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold[5]; - -/** Offset 0x02ED - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax[5]; - -/** Offset 0x02F7 - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit[5]; - -/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableGt; - -/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableSa; - -/** Offset 0x0303 - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x0304 - Reserved - Reserved -**/ - UINT8 Reserved2; - -/** Offset 0x0305 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0306 -**/ - UINT8 UnusedUpdSpace9[6]; - -/** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization - @deprecated SkipMpInit has been moved to FspmUpd - $EN_DIS -**/ - UINT8 SkipMpInitDeprecated; - -/** Offset 0x030D - McIVR RFI Frequency Prefix - PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. 0: Plus (+); 1: - Minus (-). -**/ - UINT8 McivrRfiFrequencyPrefix; - -/** Offset 0x030E - McIVR RFI Frequency Adjustment - PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in - increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. 0: Auto. -**/ - UINT8 McivrRfiFrequencyAdjust; - -/** Offset 0x030F - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x0311 - McIVR RFI Spread Spectrum - PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. 0: 0%; 1: +/- 0.5%; 2: +/- - 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. -**/ - UINT8 McivrSpreadSpectrum; - -/** Offset 0x0312 - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x0315 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues. - Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox - command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. -**/ - UINT8 IslVrCmd; - -/** Offset 0x031A - Imon slope1 correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope1[5]; - -/** Offset 0x0324 - CPU VR Power Delivery Design - Used to communicate the power delivery design capability of the board. This value - is an enum of the available power delivery segments that are defined in the Platform - Design Guide. -**/ - UINT32 VrPowerDeliveryDesign; - -/** Offset 0x0328 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0329 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x032A - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x032B - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x032F - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0333 - Enable or Disable processor debug features - Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0334 - Imon offset 1 correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset1[5]; - -/** Offset 0x033E - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS -**/ - UINT8 ReservedCpuPostMemProduction[8]; - -/** Offset 0x0346 - Enable DMI ASPM - Deprecated. - $EN_DIS -**/ - UINT8 PchDmiAspm; - -/** Offset 0x0347 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x034D - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x0352 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x035C - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x0366 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0367 -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x0368 - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x0369 - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x036A - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x036B - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. - 0: 2T, 1: 1T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x036D - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x036E - USB LFPS Filter selection - For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, - 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. -**/ - UINT8 PchUsbHsioFilterSel[10]; - -/** Offset 0x0378 -**/ - UINT8 UnusedUpdSpace11[5]; - -/** Offset 0x037D - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x037E - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x037F -**/ - UINT8 UnusedUpdSpace12; - -/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x038E - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x0390 -**/ - UINT8 UnusedUpdSpace13[3]; - -/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x0394 - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x0395 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x0396 - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x03AE - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03C6 - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x040E - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x0426 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x043E - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x0456 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x046E - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x0486 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x049E - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x04B6 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04CE - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters - Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for - controlling the input offset -**/ - UINT8 PchUsbHsioRxTuningParameters[10]; - -/** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable - Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, - 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable -**/ - UINT8 PchUsbHsioRxTuningEnable[10]; - -/** Offset 0x04FA -**/ - UINT8 UnusedUpdSpace14[4]; - -/** Offset 0x04FE - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x052E - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x0546 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x055E -**/ - UINT8 UnusedUpdSpace15[106]; - -/** Offset 0x05C8 - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x05E0 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05F8 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x0610 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x065D - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x0662 - PCIE Disable RootPort Clock Gating - Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieDisableRootPortClockGating; - -/** Offset 0x0663 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x0664 -**/ - UINT8 UnusedUpdSpace16; - -/** Offset 0x0665 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x0666 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x0667 - Teton Glacier Support - Deprecated - $EN_DIS -**/ - UINT8 TetonGlacierSupport; - -/** Offset 0x0668 - Teton Glacier Cycle Router - Specify to which cycle router Teton Glacier is connected, it is valid only when - Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system -**/ - UINT8 TetonGlacierCR; - -/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x066A - SPI ChipSelect signal polarity - Selects SPI ChipSelect signal polarity. -**/ - UINT8 SerialIoSpiCsPolarity[3]; - -/** Offset 0x066D - PCIE IMR - Enables Isolated Memory Region for PCIe. - $EN_DIS -**/ - UINT8 PcieRpImrEnabled; - -/** Offset 0x066E - PCIE IMR port number - Selects PCIE root port number for IMR feature. -**/ - UINT8 PcieRpImrSelection; - -/** Offset 0x066F - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Static - Configuration 2: Dynamic Configuration. Default is 0: Disabled - 0: Disabled, 1: Static Configuration, 2: Dynamic Configuration -**/ - UINT8 TetonGlacierMode; - -/** Offset 0x0670 - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x0672 - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x0675 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x0676 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x0677 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x0678 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x0679 - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x067A - SLP_S0# Override - Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' - will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion - when debug is enabled. \n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:Disabled, 1:Enabled, 2:Auto -**/ - UINT8 SlpS0Override; - -/** Offset 0x067B - S0ix Override Settings - Select 'Auto', it will be auto-configured according to probe type. 'No Change' will - keep PMC default settings. Or select the desired debug probe type for S0ix Override - settings.\n - Reminder: DCI OOB (aka BSSB) uses CCA probe.\n - Note: This BIOS option should keep 'Auto', other options are intended for advanced - configuration only. - 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x067C - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x067D - PCH Legacy IO Low Latency Enable - Set to enable low latency of legacy IO. 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x067E -**/ - UINT8 UnusedUpdSpace17[2]; - -/** Offset 0x0680 - PCH Pm Lpc Clock Run - This member describes whether or not the LPC ClockRun feature of PCH should be enabled. - Default value is Disabled - $EN_DIS -**/ - UINT8 PchPmLpcClockRun; - -/** Offset 0x0681 - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x0682 - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x0683 - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0685 -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x0686 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0687 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0688 - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x068A - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x068B - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x068C -**/ - UINT8 UnusedUpdSpace19; - -/** Offset 0x068D - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x068E - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x068F - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x0690 - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x0698 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x06A0 - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x06A8 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x06B0 - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x06B8 - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x06C0 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x06C8 - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x06D8 - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x06E0 - PCH Sata Rst Raid Device Id - Enable RAID Alternate ID. - 0:Client, 1:Alternate, 2:Server -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x06E1 - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x06E2 - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x06E3 - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x06E4 - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x06E5 - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x06E9 - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x06EA - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x06EB - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x06F5 - Enable eMMC HS400 Training - Deprecated. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400TuningRequired; - -/** Offset 0x06F6 - Set HS400 Tuning Data Valid - Set if HS400 Tuning Data Valid. - $EN_DIS -**/ - UINT8 PchScsEmmcHs400DllDataValid; - -/** Offset 0x06F7 - Rx Strobe Delay Control - Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). -**/ - UINT8 PchScsEmmcHs400RxStrobeDll1; - -/** Offset 0x06F8 - Tx Data Delay Control - Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). -**/ - UINT8 PchScsEmmcHs400TxDataDll; - -/** Offset 0x06F9 - I/O Driver Strength - Deprecated. - 0:33 Ohm, 1:40 Ohm, 2:50 Ohm -**/ - UINT8 PchScsEmmcHs400DriverStrength; - -/** Offset 0x06FA - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x0700 -**/ - UINT8 UnusedUpdSpace20; - -/** Offset 0x0701 - PcdSerialIoUart0PinMuxing - Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled. - 0:default pins, 1:pins muxed with CNV_BRI/RGI -**/ - UINT8 SerialIoUart0PinMuxing; - -/** Offset 0x0702 -**/ - UINT8 UnusedUpdSpace21[1]; - -/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS linesh. -**/ - UINT8 SerialIoUartHwFlowCtrl[3]; - -/** Offset 0x0706 - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x0707 - Enable Debug UART Controller - Enable debug UART controller after post. - $EN_DIS -**/ - UINT8 SerialIoEnableDebugUartAfterPost; - -/** Offset 0x0708 - Enable Serial IRQ - Determines if enable Serial IRQ. - $EN_DIS -**/ - UINT8 PchSirqEnable; - -/** Offset 0x0709 - Serial IRQ Mode Select - Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. - $EN_DIS -**/ - UINT8 PchSirqMode; - -/** Offset 0x070A - Start Frame Pulse Width - Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. - 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk -**/ - UINT8 PchStartFramePulse; - -/** Offset 0x070B - Reserved - Reserved - $EN_DIS -**/ - UINT8 ReservedForFuture1; - -/** Offset 0x070C - Thermal Device SMI Enable - This locks down SMI Enable on Alert Thermal Sensor Trip. - $EN_DIS -**/ - UINT8 PchTsmicLock; - -/** Offset 0x070D - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x070F - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x0713 - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x0714 - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x0715 - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x0716 - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x0717 - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x071A - Thermal Sensor 0 Target Width - DMT thermal sensor suggested representative values. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x071B - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x071C - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x071D - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x071E - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x071F - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x0720 - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x0721 - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x0722 - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x0723 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x0724 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x0725 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x0726 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x0728 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x072A - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x072B - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x072C - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x072E - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x0730 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x0732 - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x0734 - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x0735 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x0745 - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x074F - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x0750 - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x0753 -**/ - UINT8 UnusedUpdSpace22; - -/** Offset 0x0754 - Pch PCIE device override table pointer - The PCIe device table is being used to override PCIe device ASPM settings. This - is a pointer points to a 32bit address. And it's only used in PostMem phase. Please - refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId - must be 0. -**/ - UINT32 PchPcieDeviceOverrideTablePtr; - -/** Offset 0x0758 - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x0759 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0779 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x077D - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x0785 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x078D - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x078E - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x078F - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x0797 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x079F - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x07A0 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x07A1 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x07A5 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x07A7 - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x07A8 - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x07A9 - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x07AB - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x07AC -**/ - UINT8 ReservedFspsUpd[1]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x07AD -**/ - UINT32 Signature; - -/** Offset 0x07B1 - Enable/Disable Device 7 - Enable: Device 7 enabled, Disable (Default): Device 7 disabled - $EN_DIS -**/ - UINT8 ChapDeviceEnable; - -/** Offset 0x07B2 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x07B3 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x07B4 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x07B5 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x07B6 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x07BA - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x07BB - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x07BC - Enable/Disable CdynmaxClamp - Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x07BD - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisableDeprecated; - -/** Offset 0x07BE - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x07BF - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x07C0 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS -**/ - UINT8 SaPostMemTestRsvd[11]; - -/** Offset 0x07CB - 1-Core Ratio Limit - 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core - Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, - 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, - 8-Core Ratio Limit. Range is 0 to 255 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x07CC - 2-Core Ratio Limit - 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x07CD - 3-Core Ratio Limit - 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x07CE - 4-Core Ratio Limit - 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x07CF - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x07D0 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x07D1 - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. - Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 - , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x07D2 - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x07D3 - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x07D4 - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x07D5 - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x07D6 - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x07D7 - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x07D8 - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For Y SKU, the recommended default for this policy is 15, - For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x07DA - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x07DB - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x07DC - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x07DD - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x07DE - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom1ConfigTdpControl; - -/** Offset 0x07DF - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x07E0 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x07E1 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom2ConfigTdpControl; - -/** Offset 0x07E2 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 - to 128, 0 = AUTO -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x07E3 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x07E4 - Custom Config Tdp Control - Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 -**/ - UINT8 Custom3ConfigTdpControl; - -/** Offset 0x07E5 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x07E6 - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x07E7 - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x07E8 - PL1 timewindow - PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) - 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x07E9 - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x07ED - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features - @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x07EF - Lock or Unlock debug interface features - Lock or Unlock debug interface features; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x07F1 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x07F2 - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x07F3 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x07FB - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x07FF - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0801 - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x0803 - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x0806 - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x0807 - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x0808 - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x0809 - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x080A - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x080B - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x080C - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x080D - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. Policy will be ignored for CNL-U. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. Policy will be ignored for CNL-U. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x080F - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x0810 - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0812 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0813 - TimeUnit for C-State Latency Control0 - TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl0TimeUnit; - -/** Offset 0x0814 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x0815 - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x0816 - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x0817 - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x0818 - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x0819 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: - No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x081A - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x081B - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x081C - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x081D - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x081E - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x0856 - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl0Irtl; - -/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5 - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x0864 - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x0868 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x086C - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x0870 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x0874 - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x0890 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x0894 - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x0898 - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x089A - 5-Core Ratio Limit - 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x089B - 6-Core Ratio Limit - 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x089C - 7-Core Ratio Limit - 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x089D - 8-Core Ratio Limit - 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core - Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver - Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x08A2 - CpuWakeUpTimer - Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased - to 180 seconds. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CpuWakeUpTimer; - -/** Offset 0x08A3 - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x08A4 - Minimum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x08A5 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test - $EN_DIS -**/ - UINT8 ReservedCpuPostMemTest[21]; - -/** Offset 0x08BA - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x08BB - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI - 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x08BC - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x08BD - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08BF - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x08C1 - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x08C2 - PCH Unlock SBI access - Deprecated - $EN_DIS -**/ - UINT8 PchSbiUnlock; - -/** Offset 0x08C3 - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x0954 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x09FC - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x0A5D - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x0A5E - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x0A5F - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0A61 -**/ - UINT8 UnusedUpdSpace23[17]; - -/** Offset 0x0A72 - Skip POSTBOOT SAI - Deprecated - $EN_DIS -**/ - UINT8 SkipPostBootSai; - -/** Offset 0x0A73 - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x0A74 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x07AD -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0A80 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h deleted file mode 100644 index bef3ee5e6b4..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h +++ /dev/null @@ -1,136 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT - Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is - set to UART0. - 0:default pins, 1:pins muxed with CNV_BRI/RGI -**/ - UINT8 PcdSerialIoUart0PinMuxing; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 -**/ - UINT32 PcdSerialIoUartInputClock; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 -**/ - UINT8 ReservedFsptUpd1[44]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0080 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h deleted file mode 100644 index e605e92d0bd..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ /dev/null @@ -1,270 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - - @copyright - Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
- This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License that accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -@par Specification Reference: -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef CPU_CFL//CNL -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#else//CFL -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif -#endif//CPU_CFL-endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. - UINT16 Speed; ///< The maximum capable speed of the device, in MHz. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; -#ifdef CPU_CFL - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; -#endif //CPU_CFL -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h index 98a16d7752a..1ea5b07be13 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h @@ -2,7 +2,7 @@ Header file for Firmware Version Information @copyright - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h index 21b84a3069b..a42410c771b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspEas.h @@ -2,7 +2,7 @@ Intel FSP definition from Intel Firmware Support Package External Architecture Specification v2.0. - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
This file and the accompanying materials are licensed and made available under the terms and conditions of the BSD License. The full text of the license may be found at diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h index 7491aca9a8e..7a4373e9c70 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index b4d4cada49d..8abff098ae4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h index fc0808430fd..02e36ea7b6b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h index b3c96617c0b..e41d07925c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h deleted file mode 100644 index be9d33f860a..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h +++ /dev/null @@ -1,205 +0,0 @@ -/** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - - -#ifndef _GPIO_FSP_H_ -#define _GPIO_FSP_H_ - -// -// Below defines are based on GPIO_CONFIG structure fields -// -#define GPIO_CONF_PAD_MODE_MASK 0xF -#define GPIO_CONF_PAD_MODE_BIT_POS 0 -#define GPIO_CONF_HOST_OWN_MASK 0x3 -#define GPIO_CONF_HOST_OWN_BIT_POS 0 -#define GPIO_CONF_DIR_MASK 0x7 -#define GPIO_CONF_DIR_BIT_POS 0 -#define GPIO_CONF_INV_MASK 0x18 -#define GPIO_CONF_INV_BIT_POS 3 -#define GPIO_CONF_OUTPUT_MASK 0x3 -#define GPIO_CONF_OUTPUT_BIT_POS 0 -#define GPIO_CONF_INT_ROUTE_MASK 0x1F -#define GPIO_CONF_INT_ROUTE_BIT_POS 0 -#define GPIO_CONF_INT_TRIG_MASK 0xE0 -#define GPIO_CONF_INT_TRIG_BIT_POS 5 -#define GPIO_CONF_RESET_MASK 0x7 -#define GPIO_CONF_RESET_BIT_POS 0 -#define GPIO_CONF_TERM_MASK 0x1F -#define GPIO_CONF_TERM_BIT_POS 0 -#define GPIO_CONF_PADTOL_MASK 0x60 -#define GPIO_CONF_PADTOL_BIT_POS 5 -#define GPIO_CONF_LOCK_MASK 0x7 -#define GPIO_CONF_LOCK_BIT_POS 0 -#define GPIO_CONF_RXRAW_MASK 0x3 -#define GPIO_CONF_RXRAW_BIT_POS 0 - -typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; - -/// -/// GPIO Pad Mode -/// -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9 -} GPIO_PAD_MODE; - -/// -/// Host Software Pad Ownership modes -/// -typedef enum { - GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified - GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI - GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO -} GPIO_HOSTSW_OWN; - -/// -/// GPIO Direction -/// -typedef enum { - GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified - GpioDirInOut = - (0x1 | (0x1 << 3)), ///< Set pad for both output and input - GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and - ///input with inversion - GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only - GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion - GpioDirOut = 0x5, ///< Set pad for output only - GpioDirNone = 0x7 ///< Disable both output and input -} GPIO_DIRECTION; - -/// -/// GPIO Output State -/// -typedef enum { - GpioOutDefault = 0x0, ///< Leave output value unmodified - GpioOutLow = 0x1, ///< Set output to low - GpioOutHigh = 0x3 ///< Set output to high -} GPIO_OUTPUT_STATE; - -/// -/// GPIO interrupt configuration -/// This setting is applicable only if GPIO is in input mode. -/// GPIO_INT_CONFIG allows to choose which interrupt is generated -/// (IOxAPIC/SCI/SMI/NMI) -/// and how it is triggered (edge or level). -/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to -/// GpioIntBothEdgecan -/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel -/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. -/// Not all GPIO are capable of generating an SMI or NMI interrupt -/// - -typedef enum { - GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified - GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation - GpioIntNmi = 0x3, ///< Enable NMI interrupt only - GpioIntSmi = 0x5, ///< Enable SMI interrupt only - GpioIntSci = 0x9, ///< Enable SCI interrupt only - GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only - GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered - GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of - ///edge depends on input inversion) - GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger - GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered -} GPIO_INT_CONFIG; - -/// -/// GPIO Power Configuration -/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified -/// Pad Register fields). -/// -typedef enum { - GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified - GpioResetPwrGood = 0x1, ///< Powergood reset - GpioResetDeep = 0x3, ///< Deep GPIO Reset - GpioResetNormal = 0x5, ///< GPIO Reset - GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) -} GPIO_RESET_CONFIG; - -/// -/// GPIO Electrical Configuration -/// Set GPIO termination and Pad Tolerance (applicable only for some pads) -/// Field from GpioTermDefault to GpioTermNative can be OR'ed with -/// GpioTolerance1v8. -/// -typedef enum { - GpioTermDefault = 0x0, ///< Leave termination setting unmodified - GpioTermNone = 0x1, ///< none - GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down - GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down - GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up - GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up - GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up - GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up - GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up - GpioTermNative = 0x1F, ///< Native function controls pads termination - GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance - GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance -} GPIO_ELECTRICAL_CONFIG; - -/// -/// GPIO LockConfiguration -/// Set GPIO configuration lock and output state lock -/// GpioLockPadConfig and GpioLockOutputState can be OR'ed -/// -typedef enum { - GpioLockDefault = 0x0, ///< Leave lock setting unmodified - GpioPadConfigLock = 0x3, ///< Lock Pad Configuration - GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value -} GPIO_LOCK_CONFIG; - -/// -/// Other GPIO Configuration -/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions -/// Supported settings: -/// - RX raw override to '1' - allows to override input value to '1' -/// This setting is applicable only if in input mode (both in GPIO and -/// native usage). -/// The override takes place at the internal pad state directly from buffer -/// and before the RXINV. -/// -typedef enum { - GpioRxRaw1Default = 0x0, ///< Use default input override value - GpioRxRaw1Dis = 0x1, ///< Don't override input - GpioRxRaw1En = 0x3 ///< Override input to '1' -} GPIO_OTHER_CONFIG; - -// -// Possible values of Pad Ownership -// -typedef enum { - GpioPadOwnHost = 0x0, - GpioPadOwnCsme = 0x1, - GpioPadOwnIsh = 0x2, -} GPIO_PAD_OWN; - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 9900a121f25..3c6f9a74085 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 598d78ceb60..52f3307136f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -127,6 +127,7 @@ typedef struct DimmDevice { UINT8 EnergyType; UINT8 reserved10[1]; UINT16 SPDRegVen; // Register Vendor ID in SPD + UINT8 CidBitMap; // SubRankPer CS for DIMM device } MEMMAP_DIMM_DEVICE_INFO_STRUCT; struct ChannelDevice { diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h index 9241692b3ab..93a1f9ac0c4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_prevbooterr.h @@ -1,5 +1,5 @@ /** -Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 276ac79c4c4..e791115c263 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -931,7 +931,17 @@ typedef struct { /** Offset 0x04BA - Reserved **/ - UINT8 Reserved20[7]; + UINT8 Reserved20[2]; + +/** Offset 0x04BC - Disable TC code On USB Connect + Enable(default) or Disable TC cold On Usb Connected + $EN_DIS +**/ + UINT8 DisableTccoldOnUsbConnected; + +/** Offset 0x04BD - Reserved +**/ + UINT8 Reserved21[4]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -965,7 +975,7 @@ typedef struct { /** Offset 0x04C6 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; /** Offset 0x04C7 - VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) @@ -975,7 +985,7 @@ typedef struct { /** Offset 0x04C8 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved23; /** Offset 0x04C9 - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH @@ -985,7 +995,7 @@ typedef struct { /** Offset 0x04CA - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved24; /** Offset 0x04CB - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH @@ -1001,7 +1011,7 @@ typedef struct { /** Offset 0x04CD - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved25; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -1048,9 +1058,11 @@ typedef struct { **/ UINT8 VccSt; -/** Offset 0x04DD - Reserved +/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable + Used by IOM FW to skip powering down the PHY at the end of disconnect flow + $EN_DIS **/ - UINT8 Reserved25; + UINT8 Usb3ComplModeEnable; /** Offset 0x04DE - ITBT DMA LTR TCSS DMA1, DMA2 LTR value diff --git a/tests/include/static.h b/tests/include/static.h new file mode 100644 index 00000000000..4799e2c4535 --- /dev/null +++ b/tests/include/static.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * static.h is generated by util/sconfig during a coreboot build. Since this file might be + * included by other header files that are part of the unit tests, this dummy file is added to + * make the test infrastructure happy. + */ diff --git a/tests/include/tests/lib/fmap/fmap_config.h b/tests/include/tests/lib/fmap/fmap_config.h new file mode 100644 index 00000000000..0a2809b35ac --- /dev/null +++ b/tests/include/tests/lib/fmap/fmap_config.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef FMAPTOOL_GENERATED_HEADER_H_ +#define FMAPTOOL_GENERATED_HEADER_H_ + +/* + * This file was generated using fmaptool from util/cbfstools using + * src/mainboard/google/octopus/chromeos.fmd + */ +#define FMAP_OFFSET 0x204000 +#define FMAP_SIZE 0x620 + +#define FMAP_SECTION_FLASH_START 0 +#define FMAP_SECTION_FLASH_SIZE 0x1000000 +#define FMAP_SECTION_WP_RO_START 0 +#define FMAP_SECTION_WP_RO_SIZE 0x400000 +#define FMAP_SECTION_SI_DESC_START 0 +#define FMAP_SECTION_SI_DESC_SIZE 0x1000 +#define FMAP_SECTION_IFWI_START 0x1000 +#define FMAP_SECTION_IFWI_SIZE 0x1ff000 +#define FMAP_SECTION_RO_VPD_START 0x200000 +#define FMAP_SECTION_RO_VPD_SIZE 0x4000 +#define FMAP_SECTION_RO_SECTION_START 0x204000 +#define FMAP_SECTION_RO_SECTION_SIZE 0x1fc000 +#define FMAP_SECTION_FMAP_START 0x204000 +#define FMAP_SECTION_FMAP_SIZE 0x800 +#define FMAP_SECTION_RO_FRID_START 0x204800 +#define FMAP_SECTION_RO_FRID_SIZE 0x40 +#define FMAP_SECTION_RO_FRID_PAD_START 0x204840 +#define FMAP_SECTION_RO_FRID_PAD_SIZE 0x7c0 +#define FMAP_SECTION_COREBOOT_START 0x205000 +#define FMAP_SECTION_COREBOOT_SIZE 0x1f8000 +#define FMAP_SECTION_GBB_START 0x3fd000 +#define FMAP_SECTION_GBB_SIZE 0x3000 +#define FMAP_SECTION_MISC_RW_START 0x400000 +#define FMAP_SECTION_MISC_RW_SIZE 0x30000 +#define FMAP_SECTION_RW_PRESERVE_START 0x400000 +#define FMAP_SECTION_RW_PRESERVE_SIZE 0x21000 +#define FMAP_SECTION_UNIFIED_MRC_CACHE_START 0x400000 +#define FMAP_SECTION_UNIFIED_MRC_CACHE_SIZE 0x21000 +#define FMAP_SECTION_RECOVERY_MRC_CACHE_START 0x400000 +#define FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE 0x10000 +#define FMAP_SECTION_RW_MRC_CACHE_START 0x410000 +#define FMAP_SECTION_RW_MRC_CACHE_SIZE 0x10000 +#define FMAP_SECTION_RW_VAR_MRC_CACHE_START 0x420000 +#define FMAP_SECTION_RW_VAR_MRC_CACHE_SIZE 0x1000 +#define FMAP_SECTION_RW_ELOG_START 0x421000 +#define FMAP_SECTION_RW_ELOG_SIZE 0x3000 +#define FMAP_SECTION_RW_SHARED_START 0x424000 +#define FMAP_SECTION_RW_SHARED_SIZE 0x4000 +#define FMAP_SECTION_SHARED_DATA_START 0x424000 +#define FMAP_SECTION_SHARED_DATA_SIZE 0x2000 +#define FMAP_SECTION_VBLOCK_DEV_START 0x426000 +#define FMAP_SECTION_VBLOCK_DEV_SIZE 0x2000 +#define FMAP_SECTION_RW_VPD_START 0x428000 +#define FMAP_SECTION_RW_VPD_SIZE 0x2000 +#define FMAP_SECTION_RW_NVRAM_START 0x42a000 +#define FMAP_SECTION_RW_NVRAM_SIZE 0x5000 +#define FMAP_SECTION_FPF_STATUS_START 0x42f000 +#define FMAP_SECTION_FPF_STATUS_SIZE 0x1000 +#define FMAP_SECTION_RW_SECTION_A_START 0x430000 +#define FMAP_SECTION_RW_SECTION_A_SIZE 0x480000 +#define FMAP_SECTION_VBLOCK_A_START 0x430000 +#define FMAP_SECTION_VBLOCK_A_SIZE 0x10000 +#define FMAP_SECTION_FW_MAIN_A_START 0x440000 +#define FMAP_SECTION_FW_MAIN_A_SIZE 0x46ffc0 +#define FMAP_SECTION_RW_FWID_A_START 0x8affc0 +#define FMAP_SECTION_RW_FWID_A_SIZE 0x40 +#define FMAP_SECTION_RW_SECTION_B_START 0x8b0000 +#define FMAP_SECTION_RW_SECTION_B_SIZE 0x480000 +#define FMAP_SECTION_VBLOCK_B_START 0x8b0000 +#define FMAP_SECTION_VBLOCK_B_SIZE 0x10000 +#define FMAP_SECTION_FW_MAIN_B_START 0x8c0000 +#define FMAP_SECTION_FW_MAIN_B_SIZE 0x46ffc0 +#define FMAP_SECTION_RW_FWID_B_START 0xd2ffc0 +#define FMAP_SECTION_RW_FWID_B_SIZE 0x40 +#define FMAP_SECTION_SMMSTORE_START 0xd30000 +#define FMAP_SECTION_SMMSTORE_SIZE 0x40000 +#define FMAP_SECTION_RW_LEGACY_START 0xd70000 +#define FMAP_SECTION_RW_LEGACY_SIZE 0x1c0000 +#define FMAP_SECTION_BIOS_UNUSABLE_START 0xf30000 +#define FMAP_SECTION_BIOS_UNUSABLE_SIZE 0x4f000 +#define FMAP_SECTION_DEVICE_EXTENSION_START 0xf7f000 +#define FMAP_SECTION_DEVICE_EXTENSION_SIZE 0x80000 +#define FMAP_SECTION_UNUSED_HOLE_START 0xfff000 +#define FMAP_SECTION_UNUSED_HOLE_SIZE 0x1000 + +#endif diff --git a/tests/include/tests/lib/fmap/fmap_data.h b/tests/include/tests/lib/fmap/fmap_data.h new file mode 100644 index 00000000000..eaeabd3bf12 --- /dev/null +++ b/tests/include/tests/lib/fmap/fmap_data.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TESTS_FMAP_DATA_H_ +#define TESTS_FMAP_DATA_H_ + +/* + * This file was converted using `xxd -i` from binary output of + * fmaptool from util/cbfstools. Data is based on output generated by + * mentioned tool using src/mainboard/google/octopus/chromeos.fmd file. + */ + +unsigned char tests_fmap_bin[] = { +0x5f, 0x5f, 0x46, 0x4d, 0x41, 0x50, 0x5f, 0x5f, 0x01, 0x01, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x46, 0x4c, +0x41, 0x53, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x40, 0x00, 0x57, 0x50, 0x5f, 0x52, 0x4f, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x53, 0x49, +0x5f, 0x44, 0x45, 0x53, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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b/tests/include/tests/lib/imd_cbmem_data.h @@ -0,0 +1,4119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TESTS_LIB_IMD_CBMEM_DATA_H +#define TESTS_LIB_IMD_CBMEM_DATA_H + +#define CBMEM_SIZE (32 * KiB) + +/* Values used for simple cbmem structure entries */ +#define CBMEM_ENTRY_1_ID 0xA1 +#define CBMEM_ENTRY_1_SIZE (8 * KiB) +#define CBMEM_ENTRY_2_ID 0xA2 +#define CBMEM_ENTRY_2_SIZE (10 * KiB) +#define CBMEM_ENTRY_SM_1_ID 0xB1 +#define CBMEM_ENTRY_SM_1_SIZE 64 +#define CBMEM_ENTRY_SM_2_ID 0xB2 +#define CBMEM_ENTRY_SM_2_SIZE 128 + +/* test_cbmem_data[] is binary image of how CBMEM should look like after calling + prepare_simple_cbmem() */ +uint8_t test_cbmem_data[CBMEM_SIZE] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x81, 0x94, 0x38, 0xc0, 0x08, 0xf0, 0xff, 0xff, +}; + +#endif /* TESTS_LIB_IMD_CBMEM_DATA_H */ diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 5783f189192..32b340e5d94 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -9,6 +9,9 @@ tests-y += edid-test tests-y += cbmem_console-romstage-test tests-y += cbmem_console-ramstage-test tests-y += list-test +tests-y += fmap-test +tests-y += imd_cbmem-romstage-test +tests-y += imd_cbmem-ramstage-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -44,3 +47,23 @@ cbmem_console-ramstage-test-srcs += tests/stubs/console.c list-test-srcs += tests/lib/list-test.c list-test-srcs += src/lib/list.c +fmap-test-srcs += tests/lib/fmap-test.c +fmap-test-srcs += src/lib/fmap.c +fmap-test-srcs += tests/stubs/console.c +fmap-test-srcs += src/lib/boot_device.c +fmap-test-srcs += src/commonlib/region.c +fmap-test-cflags += -I tests/include/tests/lib/fmap +fmap-test-cflags += -I 3rdparty/vboot/firmware/include + +imd_cbmem-ramstage-test-stage := ramstage +imd_cbmem-ramstage-test-srcs += tests/lib/imd_cbmem-test.c +imd_cbmem-ramstage-test-srcs += tests/stubs/console.c +imd_cbmem-ramstage-test-srcs += src/lib/imd.c +imd_cbmem-ramstage-test-mocks += cbmem_top_chipset + +imd_cbmem-romstage-test-stage := romstage +imd_cbmem-romstage-test-srcs += tests/lib/imd_cbmem-test.c +imd_cbmem-romstage-test-srcs += tests/stubs/console.c +imd_cbmem-romstage-test-srcs += src/lib/imd.c +imd_cbmem-romstage-test-mocks += cbmem_top_chipset + diff --git a/tests/lib/fmap-test.c b/tests/lib/fmap-test.c new file mode 100644 index 00000000000..372bb85a865 --- /dev/null +++ b/tests/lib/fmap-test.c @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +#include +#include + +#include +#include + +static struct mem_region_device mem_rdev_rw; +static struct mem_region_device mem_rdev_ro; +static char *flash_buffer = NULL; +static size_t flash_buffer_size = 0; + +static void prepare_flash_buffer(void) +{ + /* Prepare flash buffer with dummy data and FMAP */ + flash_buffer = malloc(FMAP_SECTION_FLASH_SIZE); + flash_buffer_size = FMAP_SECTION_FLASH_SIZE; + + /* Fill first part of buffer with dummy data */ + for (int i = 0; i < FMAP_SECTION_FMAP_START; ++i) + flash_buffer[i] = 'a' + i % ('z' - 'a'); + + /* Copy FMAP section into buffer */ + memcpy(flash_buffer + FMAP_SECTION_FMAP_START, tests_fmap_bin, FMAP_SIZE); + + /* Fill rest of buffer with dummy data */ + for (int i = FMAP_SECTION_FMAP_START + FMAP_SECTION_FMAP_SIZE; + i < FMAP_SECTION_FLASH_SIZE; ++i) + flash_buffer[i] = 'a' + i % ('z' - 'a'); +} + +static int setup_fmap(void **state) +{ + prepare_flash_buffer(); + + mem_rdev_rw = (struct mem_region_device) + MEM_REGION_DEV_RW_INIT(flash_buffer, FMAP_SECTION_FLASH_SIZE); + + mem_rdev_ro = (struct mem_region_device) + MEM_REGION_DEV_RO_INIT(flash_buffer, FMAP_SECTION_FLASH_SIZE); + + return 0; +} + +static int teardown_fmap(void **state) +{ + struct mem_region_device empty = { + .base = NULL, + .rdev = { + .root = NULL, + .ops = NULL, + .region = { + .offset = 0, + .size = 0 + } + } + }; + + mem_rdev_rw = empty; + mem_rdev_ro = empty; + + free(flash_buffer); + flash_buffer = NULL; + flash_buffer_size = 0; + + return 0; +} + +void boot_device_init(void) +{ + /* Setup in unit test setup function */ +} + +const struct region_device *boot_device_ro(void) +{ + return &mem_rdev_rw.rdev; +} + +const struct region_device *boot_device_rw(void) +{ + return &mem_rdev_rw.rdev; +} + +static void test_fmap_locate_area_as_rdev(void **state) +{ + const char buffer[] = "abcdefghijk0123456789"; + struct region_device rdev; + + assert_int_not_equal(-1, fmap_locate_area_as_rdev("RO_VPD", &rdev)); + assert_int_equal(FMAP_SECTION_RO_VPD_START, region_device_offset(&rdev)); + assert_int_equal(FMAP_SECTION_RO_VPD_SIZE, region_device_sz(&rdev)); + + /* Check if locating area second time works */ + assert_int_not_equal(-1, fmap_locate_area_as_rdev("RO_VPD", &rdev)); + assert_int_equal(FMAP_SECTION_RO_VPD_START, region_device_offset(&rdev)); + assert_int_equal(FMAP_SECTION_RO_VPD_SIZE, region_device_sz(&rdev)); + + assert_int_not_equal(-1, fmap_locate_area_as_rdev("RECOVERY_MRC_CACHE", &rdev)); + assert_int_equal(FMAP_SECTION_RECOVERY_MRC_CACHE_START, region_device_offset(&rdev)); + assert_int_equal(FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE, region_device_sz(&rdev)); + + /* Expect error when writing to read-only area */ + assert_int_equal(-1, rdev_writeat(&rdev, buffer, + region_device_offset(&rdev), sizeof(buffer))); + + /* Expect error when looking for incorrect area */ + assert_int_equal(-1, fmap_locate_area_as_rdev("NONEXISTENT_AREA", &rdev)); + assert_int_equal(-1, fmap_locate_area_as_rdev("", &rdev)); + assert_int_equal(-1, fmap_locate_area_as_rdev(NULL, &rdev)); + + /* Function fmap_locate_area_as_rdev is not tested with NULL + as region_device pointer as it is not allowed. */ +} + +static void test_fmap_locate_area_as_rdev_rw(void **state) +{ + struct region_device rdev; + size_t ro_rw_section_size = FMAP_SECTION_MISC_RW_SIZE; + char *buffer1 = malloc(ro_rw_section_size); + char *buffer2 = malloc(ro_rw_section_size); + char *dummy_data = malloc(ro_rw_section_size); + + /* Fill buffer with dummy data */ + for (int i = 0; i < ro_rw_section_size; ++i) + dummy_data[i] = '0' + i % ('9' - '0'); + + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("RW_SECTION_A", &rdev)); + assert_int_equal(FMAP_SECTION_RW_SECTION_A_START, region_device_offset(&rdev)); + assert_int_equal(FMAP_SECTION_RW_SECTION_A_SIZE, region_device_sz(&rdev)); + + /* Check if locating area second time works */ + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("RW_SECTION_A", &rdev)); + assert_int_equal(FMAP_SECTION_RW_SECTION_A_START, region_device_offset(&rdev)); + assert_int_equal(FMAP_SECTION_RW_SECTION_A_SIZE, region_device_sz(&rdev)); + + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("MISC_RW", &rdev)); + assert_int_equal(FMAP_SECTION_MISC_RW_START, region_device_offset(&rdev)); + assert_int_equal(FMAP_SECTION_MISC_RW_SIZE, region_device_sz(&rdev)); + + + /* Expect error when looking for incorrect area */ + assert_int_equal(-1, fmap_locate_area_as_rdev_rw("NONEXISTENT_AREA", &rdev)); + assert_int_equal(-1, fmap_locate_area_as_rdev_rw("", &rdev)); + + /* Expect error when passing invalid references */ + assert_int_equal(-1, fmap_locate_area_as_rdev_rw(NULL, &rdev)); + + /* Function fmap_locate_area_as_rdev_rw is not tested with NULL + as region_device pointer as it is not allowed. */ + + /* Test if returned section region device is writable */ + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("MISC_RW", &rdev)); + assert_int_equal(ro_rw_section_size, + rdev_readat(&rdev, buffer1, 0, ro_rw_section_size)); + assert_int_equal(ro_rw_section_size, + rdev_writeat(&rdev, dummy_data, 0, ro_rw_section_size)); + /* Check if written data is visible and correct after locating area as RO */ + assert_int_not_equal(-1, fmap_locate_area_as_rdev("MISC_RW", &rdev)); + assert_int_equal(ro_rw_section_size, + rdev_readat(&rdev, buffer2, 0, ro_rw_section_size)); + assert_memory_not_equal(buffer1, buffer2, ro_rw_section_size); + assert_memory_equal(dummy_data, buffer2, ro_rw_section_size); + + free(buffer1); + free(buffer2); + free(dummy_data); +} + +static void test_fmap_locate_area(void **state) +{ + struct region ar; + + /* Try to locate named area */ + assert_int_not_equal(-1, fmap_locate_area("COREBOOT", &ar)); + assert_int_equal(FMAP_SECTION_COREBOOT_START, region_offset(&ar)); + assert_int_equal(FMAP_SECTION_COREBOOT_SIZE, region_sz(&ar)); + + /* Check if locating area second time works */ + assert_int_not_equal(-1, fmap_locate_area("COREBOOT", &ar)); + assert_int_equal(FMAP_SECTION_COREBOOT_START, region_offset(&ar)); + assert_int_equal(FMAP_SECTION_COREBOOT_SIZE, region_sz(&ar)); + + /* Look for another area */ + assert_int_not_equal(-1, fmap_locate_area("GBB", &ar)); + assert_int_equal(FMAP_SECTION_GBB_START, region_offset(&ar)); + assert_int_equal(FMAP_SECTION_GBB_SIZE, region_sz(&ar)); + + /* Expect error when looking for incorrect area */ + assert_int_equal(-1, fmap_locate_area("NONEXISTENT_AREA", &ar)); + assert_int_equal(-1, fmap_locate_area("", &ar)); + assert_int_equal(-1, fmap_locate_area(NULL, &ar)); + + /* Expect error when passing invalid region pointer */ + assert_int_equal(-1, fmap_locate_area("SHARED_DATA", NULL)); +} + +static void test_fmap_find_region_name(void **state) +{ + (void)state; + struct region ar; + char found_area_name[FMAP_STRLEN] = ""; + const char *area_name = "RW_PRESERVE"; + + /* Find area by name */ + assert_int_not_equal(-1, fmap_locate_area(area_name, &ar)); + + /* Find name of previously located region */ + assert_int_not_equal(-1, fmap_find_region_name(&ar, found_area_name)); + assert_string_equal(area_name, found_area_name); + + /* Expect error when passing invalid buffer */ + assert_int_equal(-1, fmap_find_region_name(&ar, NULL)); + + /* Expect error when passing invalid region pointer */ + assert_int_equal(-1, fmap_find_region_name(NULL, found_area_name)); + + /* Try to find area outside of flash region */ + ar.offset = FMAP_SECTION_FLASH_START + FMAP_SECTION_FLASH_SIZE + 0x100; + ar.size = 0x1000; + assert_int_equal(-1, fmap_find_region_name(&ar, found_area_name)); + + /* Try to find area with correct offset and incorrect size */ + ar.offset = FMAP_SECTION_COREBOOT_START; + ar.size = FMAP_SECTION_COREBOOT_SIZE / 4; + assert_int_equal(-1, fmap_find_region_name(&ar, found_area_name)); + + /* Try to find area with correct size and incorrect offset */ + ar.offset = FMAP_SECTION_GBB_START - 0x100; + ar.size = FMAP_SECTION_GBB_START; + assert_int_equal(-1, fmap_find_region_name(&ar, found_area_name)); + + /* Try to find area with correct offset overlapping with another area */ + ar.offset = FMAP_SECTION_MISC_RW_START; + ar.size = FMAP_SECTION_MISC_RW_START + 0x1000; + assert_int_equal(-1, fmap_find_region_name(&ar, found_area_name)); +} + +static void test_fmap_read_area(void **state) +{ + const unsigned int section_size = FMAP_SECTION_RW_SECTION_A_SIZE; + const unsigned int section_start = FMAP_SECTION_RW_SECTION_A_START; + char *buffer = malloc(section_size); + + /* Find and read area data. Compare with memory device simulating flash. */ + assert_int_equal(section_size, fmap_read_area("RW_SECTION_A", buffer, section_size)); + assert_memory_equal(flash_buffer + section_start, buffer, section_size); + + /* Expect error when reading incorrect area */ + assert_int_equal(-1, fmap_read_area("NONEXISTENT_SECTION", buffer, section_size)); + assert_int_equal(-1, fmap_read_area("", buffer, section_size)); + assert_int_equal(-1, fmap_read_area(NULL, buffer, section_size)); + + /* Function fmap_read_area is not tested with NULL + as output buffer pointer as it is not allowed. */ + + free(buffer); +} + +static void test_fmap_overwrite_area(void **state) +{ + const char *section_name = "FW_MAIN_A"; + const unsigned int section_size = FMAP_SECTION_FW_MAIN_A_SIZE; + char *buffer1 = malloc(section_size); + char *buffer2 = malloc(section_size); + char *new_data = malloc(section_size / 2); + char *zero_buffer = malloc(section_size / 2); + memset(zero_buffer, 0, section_size / 2); + memset(new_data, 0x42, section_size / 2); + + /* Save buffer for future comparisons */ + assert_int_equal(section_size, fmap_read_area(section_name, buffer1, section_size)); + + /* Overwrite part of section. */ + assert_int_equal(section_size / 2, + fmap_overwrite_area(section_name, new_data, section_size / 2)); + + /* Read and check if memory has changed as expected */ + assert_int_equal(section_size, fmap_read_area(section_name, buffer2, section_size)); + assert_memory_not_equal(buffer1, buffer2, section_size); + /* Check if requested section area was overwritten properly */ + assert_memory_equal(buffer2, new_data, section_size / 2); + /* Check if rest of section was zero-filled */ + assert_memory_equal(buffer2 + (section_size / 2), zero_buffer, section_size / 2); + + /* Expect error when overwriting incorrect section */ + assert_int_equal(-1, fmap_overwrite_area("NONEXISTENT_SECTION", + new_data, section_size / 2)); + assert_int_equal(-1, fmap_overwrite_area(NULL, new_data, section_size / 2)); + + /* Function fmap_overwrite_area is not tested with NULL + as input buffer pointer as it is not allowed. */ + + free(buffer1); + free(buffer2); + free(new_data); + free(zero_buffer); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev, + setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev_rw, + setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_locate_area, + setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_find_region_name, + setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_read_area, + setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_overwrite_area, + setup_fmap, teardown_fmap), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c new file mode 100644 index 00000000000..ef90909a1a1 --- /dev/null +++ b/tests/lib/imd_cbmem-test.c @@ -0,0 +1,630 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include Unit Under Test source code directly instead of linking it. + * This will allow access to internal structures and data without having + * to extract them to another header file. + */ +#include "../lib/imd_cbmem.c" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CBMEM_ENTRY_ID 0xA001 + +static void reset_imd(void) +{ + imd.lg.limit = (uintptr_t)NULL; + imd.lg.r = NULL; + imd.sm.limit = (uintptr_t)NULL; + imd.sm.r = NULL; + + cbmem_initialized = 0; +} + +/* This implementation allows imd_cbmem module tests without linking lib/cbmem_common.c + Function indicates to each hook if cbmem is being recovered or not. */ +void cbmem_run_init_hooks(int is_recovery) +{ + function_called(); +} + +void *__wrap_cbmem_top_chipset(void) +{ + return (void *)_cbmem_top_ptr; +} + +static void *get_cbmem_ptr(void) +{ + void *cbmem_top_ptr = (void *)_cbmem_top_ptr; + if (cbmem_top_ptr) + return cbmem_top_ptr - CBMEM_SIZE; + else + return NULL; +} + +static void clear_cbmem(void) +{ + void *ptr = get_cbmem_ptr(); + if (ptr) + memset(ptr, 0, CBMEM_SIZE); +} + +static void reset_and_clear_cbmem(void) +{ + reset_imd(); + clear_cbmem(); +} + +void prepare_simple_cbmem(void) +{ + reset_and_clear_cbmem(); + + expect_function_call(cbmem_run_init_hooks); + cbmem_initialize_empty(); + + cbmem_entry_add(CBMEM_ENTRY_1_ID, CBMEM_ENTRY_1_SIZE); + cbmem_entry_add(CBMEM_ENTRY_2_ID, CBMEM_ENTRY_2_SIZE); + + cbmem_entry_add(CBMEM_ENTRY_SM_1_ID, CBMEM_ENTRY_SM_1_SIZE); + cbmem_entry_add(CBMEM_ENTRY_SM_2_ID, CBMEM_ENTRY_SM_2_SIZE); +} + +static void test_cbmem_top(void **state) +{ + cbmem_top_init_once(); + + if (ENV_ROMSTAGE) + assert_ptr_equal(cbmem_top_chipset(), cbmem_top()); + + if (ENV_POSTCAR || ENV_RAMSTAGE) + assert_ptr_equal((void *)_cbmem_top_ptr, cbmem_top()); +} + +static void test_cbmem_initialize_empty(void **state) +{ + const struct cbmem_entry *found; + + /* Expect clean call without recovery */ + expect_function_call(cbmem_run_init_hooks); + cbmem_initialize_empty(); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); + /* Check that cbmem has only root, large and small entry. */ + assert_int_equal(2, ((struct imd_root *)imd.lg.r)->num_entries); + assert_int_equal(1, ((struct imd_root *)imd.sm.r)->num_entries); +} + +static void test_cbmem_initialize_empty_id_size(void **state) +{ + const struct cbmem_entry *entry1, *entry2; + + expect_function_call(cbmem_run_init_hooks); + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + entry1 = cbmem_entry_find(SMALL_REGION_ID); + entry2 = cbmem_entry_find(CBMEM_ENTRY_ID); + + assert_non_null(entry1); + assert_non_null(entry2); + assert_ptr_not_equal(entry1, entry2); + /* Check that cbmem has root, large, small entries + and entry with id passed to init function. */ + assert_int_equal(3, ((struct imd_root *)imd.lg.r)->num_entries); + assert_int_equal(1, ((struct imd_root *)imd.sm.r)->num_entries); +} + +static void test_cbmem_initialize(void **state) +{ + int res; + + /* Expect call to fail as there is no previous cbmem to recover */ + res = cbmem_initialize(); + assert_int_equal(1, res); + + /* Create cbmem with few entries and check if initialization will recover */ + prepare_simple_cbmem(); + reset_imd(); + expect_function_call(cbmem_run_init_hooks); + res = cbmem_initialize(); + assert_int_equal(0, res); +} + +void test_cbmem_initialize_id_size_ramstage(void **state) +{ + int res; + const struct cbmem_entry *entry1, *entry2; + + /* Expect call to fail as there is no previous cbmem to recover */ + res = cbmem_initialize_id_size(0, 0); + assert_int_equal(1, res); + + reset_and_clear_cbmem(); + + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(1, res); + + /* Initialize empty cbmem with small region and check if next initialization + correctly recovers and creates its root entry with small region */ + expect_function_call(cbmem_run_init_hooks); + cbmem_initialize_empty_id_size(0, 0); + expect_function_call(cbmem_run_init_hooks); + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(0, res); + + entry1 = cbmem_entry_find(SMALL_REGION_ID); + entry2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(entry1); + assert_non_null(entry2); + assert_ptr_not_equal(entry1, entry2); + /* Check that cbmem has root, large, small entries and entry with id passed + to init function. */ + assert_int_equal(3, ((struct imd_root *)imd.lg.r)->num_entries); + assert_int_equal(1, ((struct imd_root *)imd.sm.r)->num_entries); +} + +void test_cbmem_initialize_id_size_romstage(void **state) +{ + int res; + const struct cbmem_entry *entry1, *entry2; + + /* Expect call to fail as there is no previous cbmem to recover */ + res = cbmem_initialize_id_size(0, 0); + assert_int_equal(1, res); + + /* Initialize empty cbmem with small region and check if next initialization + correctly recovers and creates its root entry with small region */ + expect_function_call(cbmem_run_init_hooks); + cbmem_initialize_empty_id_size(0, 0); + expect_function_call(cbmem_run_init_hooks); + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(0, res); + + entry1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(entry1); + + /* Romstage locks imd cbmem initialization after recovery, + so entry with CBMEM_ENTRY_ID id is not present if it was not recovered. */ + entry2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_null(entry2); + + /* Initialize cbmem with few large and small entries */ + prepare_simple_cbmem(); + + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_1_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_2_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_SM_1_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_SM_2_ID)); + + reset_imd(); + + expect_function_call(cbmem_run_init_hooks); + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(0, res); + + /* Initialization function should be able to recover entries left in cbmem + while having imd structure clean */ + entry1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(entry1); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_1_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_2_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_SM_1_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_SM_2_ID)); +} + +static void test_cbmem_recovery(void **state) +{ + int is_wakeup = 1; + + /* Reset imd, initialize cbmem and add entries for recovery */ + prepare_simple_cbmem(); + expect_function_call(cbmem_run_init_hooks); + assert_int_equal(0, cbmem_recovery(is_wakeup)); + + /* Check that entries have been correctly recovered */ + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_1_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_2_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_SM_1_ID)); + assert_non_null(cbmem_entry_find(CBMEM_ENTRY_SM_2_ID)); + + is_wakeup = 0; + expect_function_call(cbmem_run_init_hooks); + assert_int_equal(0, cbmem_recovery(is_wakeup)); + + /* Check that after recovery with is_wakeup equal to 0 the cbmem is empty + and in initial state. */ + assert_null(cbmem_entry_find(CBMEM_ENTRY_1_ID)); + assert_null(cbmem_entry_find(CBMEM_ENTRY_2_ID)); + assert_null(cbmem_entry_find(CBMEM_ENTRY_SM_1_ID)); + assert_null(cbmem_entry_find(CBMEM_ENTRY_SM_2_ID)); + /* Check that cbmem has root, large and small entry. */ + assert_int_equal(2, ((struct imd_root *)imd.lg.r)->num_entries); + assert_int_equal(1, ((struct imd_root *)imd.sm.r)->num_entries); +} + +static void test_cbmem_entry_add(void **state) +{ + /* IDs used for testing. Don't have to be sequential. + Must not be equal to SMALL_REGION_ID. */ + const int id1 = 0x10; + const int id2 = 0x11; + const int id3 = 0x12; + const struct cbmem_entry *entry1, *entry2; + const struct cbmem_entry *entry_ret2, *entry_ret3; + + /* cbmem_run_init_hooks() will be called by init functions + but this test does not aim to check it */ + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + + /* Expect NULL while looking for nonexistent entries */ + assert_null(cbmem_entry_find(id2)); + assert_null(cbmem_entry_find(id3)); + + entry_ret2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + /* Expect error when trying to add entry with zero size */ + assert_null(cbmem_entry_add(id3, 0)); + + /* Check if entries have been added correctly and are not the same */ + entry1 = cbmem_entry_find(id1); + entry2 = cbmem_entry_find(id2); + assert_non_null(entry1); + assert_non_null(entry2); + assert_ptr_not_equal(entry1, entry2); + assert_ptr_equal(entry_ret2, entry2); + + /* Add entry again and make sure that it has been + found instead of creating again. */ + entry_ret3 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE / 2); + assert_ptr_equal(entry_ret2, entry_ret3); +} + +static void test_cbmem_add(void **state) +{ + const int id0 = 0x55; + const int id1 = 0x66; + const int id2 = 0x77; + const int id3 = 0x88; + const int entry1_size = 0x2000; + const int entry2_size = 0x4d1; + const int entry3_size = 0x30; + void *entry1, *entry2, *entry3, *entry4; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty_id_size(id1, entry1_size); + entry2 = cbmem_add(id2, entry2_size); + entry3 = cbmem_add(id3, entry3_size); + entry1 = cbmem_find(id1); + + /* All pointers should be non-null and distinct. */ + assert_non_null(entry1); + assert_non_null(entry2); + assert_non_null(entry3); + assert_ptr_not_equal(entry1, entry2); + assert_ptr_not_equal(entry1, entry3); + assert_ptr_not_equal(entry2, entry3); + + /* Adding the same ID should yield the same entry pointer. */ + entry4 = cbmem_add(id2, entry2_size); + assert_ptr_equal(entry2, entry4); + + /* Expect error while trying to add range with zero size */ + assert_null(cbmem_add(id0, 0)); +} + +static void test_cbmem_entry_find(void **state) +{ + const int id1 = 0xA0; + const int id2 = 0xDD; + const int id3 = 0xBD; + const size_t entry1_size = CBMEM_ROOT_SIZE; + const size_t entry2_size = CBMEM_ROOT_SIZE / 2; + const size_t entry3_size = 6321; + const struct cbmem_entry *cbm_e1, *cbm_e2, *cbm_e3; + const struct cbmem_entry *entry1, *entry2, *entry3; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, entry1_size); + cbm_e2 = cbmem_entry_add(id2, entry2_size); + cbm_e3 = cbmem_entry_add(id3, entry3_size); + + /* Check pointers correctness and size for each entry */ + entry1 = cbmem_entry_find(id1); + assert_ptr_equal(cbm_e1, entry1); + assert_int_equal(0, (uintptr_t)cbmem_entry_start(cbm_e1) % CBMEM_SM_ALIGN); + assert_int_equal(entry1_size, cbmem_entry_size(entry1)); + + entry2 = cbmem_entry_find(id2); + assert_ptr_equal(cbm_e2, entry2); + assert_int_equal(0, (uintptr_t)cbmem_entry_start(cbm_e2) % CBMEM_SM_ALIGN); + assert_int_equal(entry2_size, cbmem_entry_size(entry2)); + + entry3 = cbmem_entry_find(id3); + assert_ptr_equal(cbm_e3, entry3); + assert_int_equal(0, (uintptr_t)cbmem_entry_start(cbm_e3) % CBMEM_SM_ALIGN); + assert_int_equal(entry3_size, cbmem_entry_size(entry3)); +} + +static void test_cbmem_find(void **state) +{ + const int id1 = 0x30; + const int id2 = 0x22; + const int id3 = 0x101; + void *cbm_e1, *cbm_e2, *entry1, *entry2; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_add(id2, CBMEM_ROOT_SIZE); + + entry1 = cbmem_find(id1); + assert_non_null(entry1); + assert_ptr_equal(cbm_e1, entry1); + + entry2 = cbmem_find(id2); + assert_non_null(entry2); + assert_ptr_equal(cbm_e2, entry2); + + /* Expect error when looking for non-existent id */ + assert_null(cbmem_find(id3)); +} + +static void test_cbmem_entry_remove(void **state) +{ + const int id1 = 0x2D; + const int id2 = 0x3D; + const int id3 = 0x4D; + const struct cbmem_entry *cbm_e1, *cbm_e2; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + /* Entries can be removed only in reverse order they have been added. */ + assert_int_equal(-1, cbmem_entry_remove(cbm_e1)); + assert_int_equal(0, cbmem_entry_remove(cbm_e2)); + assert_int_equal(0, cbmem_entry_remove(cbm_e1)); + + /* Expect error when removing non-existent entry */ + assert_int_equal(-1, cbmem_entry_remove(cbmem_entry_find(id3))); +} + +static void test_cbmem_entry_size(void **state) +{ + const int id1 = 0x4422; + const int id2 = 0x2137; + const int id3 = 0xb111; + const size_t size1 = CBMEM_ROOT_SIZE * 4; + const size_t size2 = 0x43; + const size_t size3 = CBMEM_ROOT_SIZE * 8 + 7; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty_id_size(id1, size1); + assert_non_null(cbmem_entry_add(id2, size2)); + assert_non_null(cbmem_entry_add(id3, size3)); + + /* Entry size needs not to be aligned. + It has to be the same as provided while adding it. */ + assert_int_equal(size1, cbmem_entry_size(cbmem_entry_find(id1))); + assert_int_equal(size2, cbmem_entry_size(cbmem_entry_find(id2))); + assert_int_equal(size3, cbmem_entry_size(cbmem_entry_find(id3))); +} + +static void test_cbmem_entry_start(void **state) +{ + const int id1 = 0x62; + const int id2 = 0x26; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + cbmem_entry_find(CBMEM_ENTRY_ID); + cbmem_entry_add(id1, 0x40); + cbmem_entry_add(id2, CBMEM_ROOT_SIZE * 2); + + /* Check if start address of found entry is the same + as the one returned by cbmem_find() function */ + assert_ptr_equal(cbmem_find(CBMEM_ENTRY_ID), + cbmem_entry_start(cbmem_entry_find(CBMEM_ENTRY_ID))); + assert_ptr_equal(cbmem_find(id1), cbmem_entry_start(cbmem_entry_find(id1))); + assert_ptr_equal(cbmem_find(id2), cbmem_entry_start(cbmem_entry_find(id2))); +} + +/* Reimplementation for testing purposes */ +void bootmem_add_range(uint64_t start, uint64_t size, + const enum bootmem_type tag) +{ + check_expected(start); + check_expected(size); + check_expected(tag); +} + +static void test_cbmem_add_bootmem(void **state) +{ + void *base_ptr = NULL; + size_t size = 0; + const int id1 = 0xCA; + const int id2 = 0xEA; + const int id3 = 0xDA; + const size_t size1 = 1024; + const size_t size2 = 128; + const size_t size3 = 8192; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + cbmem_entry_add(id1, size1); + cbmem_entry_add(id2, size2); + cbmem_entry_add(id3, size3); + + cbmem_get_region(&base_ptr, &size); + assert_int_equal(ALIGN_DOWN(_cbmem_top_ptr, LIMIT_ALIGN), base_ptr + size); + + expect_value(bootmem_add_range, start, base_ptr); + expect_value(bootmem_add_range, size, size); + expect_value(bootmem_add_range, tag, BM_MEM_TABLE); + cbmem_add_bootmem(); + + /* Check that adding bootmem does not change base or size of cbmem */ + cbmem_get_region(&base_ptr, &size); + assert_int_equal(ALIGN_DOWN(_cbmem_top_ptr, LIMIT_ALIGN), base_ptr + size); +} + +static void test_cbmem_get_region(void **state) +{ + int i; + void *base_ptr = NULL; + size_t size = 0; + size_t size_counter = 0; + const size_t entry_size = 0x2000; + const size_t alloc_num = 32; + const size_t small_entry_size = 64; + const size_t small_alloc_num = 3; + + ignore_function_calls(cbmem_run_init_hooks); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + /* Check size and base pointer for empty initialized cbmem */ + cbmem_get_region(&base_ptr, &size); + assert_non_null(base_ptr); + assert_int_not_equal(0, size); + assert_int_equal(CBMEM_ROOT_SIZE + cbmem_overhead_size(), size); + assert_int_equal(ALIGN_DOWN(_cbmem_top_ptr, LIMIT_ALIGN), base_ptr + size); + + /* Check for multiple big allocations */ + for (i = 1; i <= alloc_num; ++i) { + const struct cbmem_entry *e = cbmem_entry_add(i, entry_size); + assert_non_null(e); + size_counter += cbmem_entry_size(e); + + /* Check if size is correct after each big allocation */ + cbmem_get_region(&base_ptr, &size); + assert_int_equal(size_counter + cbmem_overhead_size() + CBMEM_ROOT_SIZE, size); + } + + /* Check for few small allocations. */ + for (; i <= alloc_num + small_alloc_num; ++i) { + const struct cbmem_entry *e = cbmem_entry_add(i, small_entry_size); + assert_non_null(e); + + /* Check if size is correct after each small allocation. It should not change + as small entries have their region allocated and entry size is selected + to fit in it couple of times */ + cbmem_get_region(&base_ptr, &size); + assert_int_equal(size_counter + cbmem_overhead_size() + CBMEM_ROOT_SIZE, size); + } +} + +static void test_general_data_structure(void **state) +{ + /* Initialize cbmem with few big and small entries, then check if binary data structure + is the same as stored in array containing hardcoded dumped cbmem */ + prepare_simple_cbmem(); + assert_memory_equal(get_cbmem_ptr(), test_cbmem_data, CBMEM_SIZE); +} + +static int setup_teardown_test_imd_cbmem(void **state) +{ + reset_and_clear_cbmem(); + return 0; +} + +static int setup_group_imd_cbmem(void **state) +{ + /* Allocate more data to have space for alignment */ + void *top_ptr = malloc(CBMEM_SIZE + DYN_CBMEM_ALIGN_SIZE); + + if (!top_ptr) + return -1; + + *state = top_ptr; + + _cbmem_top_ptr = ALIGN_UP((uintptr_t)top_ptr + CBMEM_SIZE, DYN_CBMEM_ALIGN_SIZE); + return 0; +} + +static int teardown_group_imd_cbmem(void **state) +{ + reset_imd(); + free(*state); + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_cbmem_top, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_initialize_empty, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_initialize_empty_id_size, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_initialize, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), +#if ENV_ROMSTAGE_OR_BEFORE + cmocka_unit_test_setup_teardown(test_cbmem_initialize_id_size_romstage, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), +#else + cmocka_unit_test_setup_teardown(test_cbmem_initialize_id_size_ramstage, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), +#endif + cmocka_unit_test_setup_teardown(test_cbmem_recovery, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_entry_add, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_add, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_entry_find, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_find, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_entry_remove, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_entry_size, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_entry_start, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_add_bootmem, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_cbmem_get_region, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + cmocka_unit_test_setup_teardown(test_general_data_structure, + setup_teardown_test_imd_cbmem, + setup_teardown_test_imd_cbmem), + }; + + return cmocka_run_group_tests(tests, setup_group_imd_cbmem, teardown_group_imd_cbmem); +} diff --git a/util/abuild/abuild b/util/abuild/abuild index 2ba2f72d1fb..408de12e7a0 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -354,7 +354,6 @@ function compile_target eval "$BUILDPREFIX" "$MAKE" "$verboseopt" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" objutil="$TARGET/sharedutils" BUILD_TIMELESS=$TIMELESS \ &> "${build_dir}/make.log" ; \ MAKE_FAILED=$? - cp "${ROOT}/.xcompile" "${build_dir}/xcompile.build" cd "${build_dir}" || return $? etime=$(perl -e 'print time();' 2>/dev/null || date +%s) @@ -466,10 +465,10 @@ function build_config missing_arches="$($MAKE --no-print-directory -f - \ REQUIRED_ARCHES="$required_arches" <<'EOF' -include .xcompile +include $(xcompile) .PHONY: missing_arches missing_arches: - $(if $(XCOMPILE_COMPLETE),,$(error .xcompile is invalid.)) + $(if $(XCOMPILE_COMPLETE),,$(error $(xcompile) is invalid.)) @echo $(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch))) EOF )" @@ -767,7 +766,9 @@ if ! mkdir -p "$TARGET"; then exit 1 fi -$MAKE -C"${ROOT}" UPDATED_SUBMODULES=1 .xcompile || exit 1 +# Generate a single xcompile for all boards +export xcompile="${TARGET}/xcompile" +$MAKE -C"${ROOT}" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1 customizing=$(echo "$customizing" | cut -c3-) if [ "$customizing" = "" ]; then diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 58606e3ed0b..c19c8e638c1 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -16,3 +16,5 @@ $(TARGET): $(OBJ) clean: @rm -f $(TARGET) $(OBJ) + +distclean: clean diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 5ae6d06186d..8b54876db79 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -57,6 +57,7 @@ #include #include #include +#include #include "amdfwtool.h" @@ -239,14 +240,27 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 }, { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 }, + { .type = AMD_HW_IPCFG, .level = PSP_LVL2 }, { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH }, { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH }, + { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH }, { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH }, { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 }, { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 }, + { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 }, { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 }, + { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2}, { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 }, + { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH }, + { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH }, + { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 }, + { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 }, + { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH }, + { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 }, + { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, + { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, + { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, { .type = AMD_ABL0, .level = PSP_BOTH }, { .type = AMD_ABL1, .level = PSP_BOTH }, { .type = AMD_ABL2, .level = PSP_BOTH }, @@ -271,6 +285,7 @@ amd_fw_entry amd_fw_table[] = { }; amd_bios_entry amd_bios_table[] = { + { .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, @@ -366,7 +381,7 @@ typedef struct _psp_directory_header { uint32_t cookie; uint32_t checksum; uint32_t num_entries; - uint32_t reserved; + uint32_t additional_info; } __attribute__((packed, aligned(16))) psp_directory_header; typedef struct _psp_directory_entry { @@ -409,7 +424,7 @@ typedef struct _bios_directory_hdr { uint32_t cookie; uint32_t checksum; uint32_t num_entries; - uint32_t reserved; + uint32_t additional_info; } __attribute__((packed, aligned(16))) bios_directory_hdr; typedef struct _bios_directory_entry { @@ -462,6 +477,7 @@ static void *new_psp_dir(context *ctx, int multi) ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); ptr = BUFF_CURRENT(*ctx); + ((psp_directory_header *)ptr)->additional_info = ctx->current; ctx->current += sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); return ptr; @@ -480,15 +496,20 @@ static void *new_combo_dir(context *ctx) } #endif -static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) +static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx) { psp_combo_directory *cdir = directory; psp_directory_table *dir = directory; bios_directory_table *bdir = directory; + uint32_t table_size = 0; if (!count) return; + /* The table size needs to be 0x1000 aligned. So align the end of table. */ + if (ctx != NULL) + ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); + switch (cookie) { case PSP2_COOKIE: /* caller is responsible for lookup mode */ @@ -505,27 +526,38 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) break; case PSP_COOKIE: case PSPL2_COOKIE: + table_size = ctx->current - dir->header.additional_info; + if ((table_size % TABLE_ALIGNMENT) != 0) { + fprintf(stderr, "The PSP table size should be 4K aligned\n"); + exit(1); + } dir->header.cookie = cookie; dir->header.num_entries = count; - dir->header.reserved = 0; + dir->header.additional_info = (table_size / 0x1000) | (1 << 10); /* checksum everything that comes after the Checksum field */ dir->header.checksum = fletcher32(&dir->header.num_entries, count * sizeof(psp_directory_entry) + sizeof(dir->header.num_entries) - + sizeof(dir->header.reserved)); + + sizeof(dir->header.additional_info)); break; case BDT1_COOKIE: case BDT2_COOKIE: + table_size = ctx->current - bdir->header.additional_info; + if ((table_size % TABLE_ALIGNMENT) != 0) { + fprintf(stderr, "The BIOS table size should be 4K aligned\n"); + exit(1); + } bdir->header.cookie = cookie; bdir->header.num_entries = count; - bdir->header.reserved = 0; + bdir->header.additional_info = (table_size / 0x1000) | (1 << 10); /* checksum everything that comes after the Checksum field */ bdir->header.checksum = fletcher32(&bdir->header.num_entries, count * sizeof(bios_directory_entry) + sizeof(bdir->header.num_entries) - + sizeof(bdir->header.reserved)); + + sizeof(bdir->header.additional_info)); break; } + } static ssize_t copy_blob(void *dest, const char *src_file, size_t room) @@ -678,7 +710,7 @@ static void integrate_psp_firmwares(context *ctx, else level = PSP_BOTH; - ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); + ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { if (!(fw_table[i].level & level)) @@ -767,7 +799,7 @@ static void integrate_psp_firmwares(context *ctx, exit(1); } - fill_dir_header(pspdir, count, cookie); + fill_dir_header(pspdir, count, cookie, ctx); } static void *new_bios_dir(context *ctx, int multi) @@ -784,6 +816,7 @@ static void *new_bios_dir(context *ctx, int multi) else ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); ptr = BUFF_CURRENT(*ctx); + ((bios_directory_hdr *) ptr)->additional_info = ctx->current; ctx->current += sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry); return ptr; @@ -858,7 +891,7 @@ static void integrate_bios_firmwares(context *ctx, else level = BDT_BOTH; - ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); + ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) { if (!(fw_table[i].level & level)) @@ -986,7 +1019,6 @@ static void integrate_bios_firmwares(context *ctx, fw_table[i].type == AMD_BIOS_APCB_BK) ctx->current = ALIGN( ctx->current, ERASE_ALIGNMENT); - bytes = copy_blob(BUFF_CURRENT(*ctx), fw_table[i].filename, BUFF_ROOM(*ctx)); if (bytes <= 0) { @@ -1028,7 +1060,7 @@ static void integrate_bios_firmwares(context *ctx, exit(1); } - fill_dir_header(biosdir, count, cookie); + fill_dir_header(biosdir, count, cookie, ctx); } enum { @@ -1176,6 +1208,7 @@ enum platform { PLATFORM_RAVEN, PLATFORM_PICASSO, PLATFORM_RENOIR, + PLATFORM_CEZANNE, PLATFORM_LUCIENNE, }; @@ -1212,6 +1245,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, break; case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: + case PLATFORM_CEZANNE: amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; @@ -1246,6 +1280,8 @@ static int identify_platform(char *soc_name) return PLATFORM_RAVEN; else if (!strcasecmp(soc_name, "Picasso")) return PLATFORM_PICASSO; + else if (!strcasecmp(soc_name, "Cezanne")) + return PLATFORM_CEZANNE; else if (!strcasecmp(soc_name, "Renoir")) return PLATFORM_RENOIR; else if (!strcasecmp(soc_name, "Lucienne")) @@ -1554,7 +1590,6 @@ int main(int argc, char **argv) return 1; } } - ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { fprintf(stderr, "Error: Failed to allocate memory\n"); @@ -1621,7 +1656,7 @@ int main(int argc, char **argv) combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir); combo_dir->header.lookup = 1; - fill_dir_header(combo_dir, 1, PSP2_COOKIE); + fill_dir_header(combo_dir, 1, PSP2_COOKIE, NULL); #endif if (have_bios_tables(amd_bios_table)) { @@ -1642,7 +1677,19 @@ int main(int argc, char **argv) integrate_bios_firmwares(&ctx, biosdir, 0, amd_bios_table, BDT1_COOKIE); } - amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); + switch (soc_id) { + case PLATFORM_RENOIR: + case PLATFORM_LUCIENNE: + case PLATFORM_CEZANNE: + amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); + break; + case PLATFORM_STONEYRIDGE: + case PLATFORM_RAVEN: + case PLATFORM_PICASSO: + default: + amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); + break; + } } /* Free the filename. */ diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 198642c0771..b12b989b74e 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -3,14 +3,6 @@ #ifndef _AMD_FW_TOOL_H_ #define _AMD_FW_TOOL_H_ -#if defined(__GLIBC__) -typedef unsigned long long int uint64_t; -typedef unsigned int uint32_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -#endif - - typedef enum _amd_fw_type { AMD_FW_PSP_PUBKEY = 0, AMD_FW_PSP_BOOTLOADER = 1, @@ -26,11 +18,13 @@ typedef enum _amd_fw_type { AMD_PSP_FUSE_CHAIN = 11, AMD_FW_PSP_SMUSCS = 95, AMD_DEBUG_UNLOCK = 0x13, + AMD_HW_IPCFG = 0x20, AMD_WRAPPED_IKEK = 0x21, AMD_TOKEN_UNLOCK = 0x22, AMD_SEC_GASKET = 0x24, AMD_MP2_FW = 0x25, AMD_DRIVER_ENTRIES = 0x28, + AMD_FW_KVM_IMAGE = 0x29, AMD_S0I3_DRIVER = 0x2d, AMD_ABL0 = 0x30, AMD_ABL1 = 0x31, @@ -41,9 +35,18 @@ typedef enum _amd_fw_type { AMD_ABL6 = 0x36, AMD_ABL7 = 0x37, AMD_FW_PSP_WHITELIST = 0x3a, + AMD_VBIOS_BTLOADER = 0x3c, AMD_FW_L2_PTR = 0x40, + AMD_FW_USB_PHY = 0x44, + AMD_FW_TOS_SEC_POLICY = 0x45, + AMD_FW_DRTM_TA = 0x47, + AMD_FW_KEYDB_BL = 0x50, + AMD_FW_KEYDB_TOS = 0x51, AMD_FW_PSP_VERSTAGE = 0x52, AMD_FW_VERSTAGE_SIG = 0x53, + AMD_RPMC_NVRAM = 0x54, + AMD_FW_DMCU_ERAM = 0x58, + AMD_FW_DMCU_ISR = 0x59, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, @@ -52,6 +55,7 @@ typedef enum _amd_fw_type { } amd_fw_type; typedef enum _amd_bios_type { + AMD_BIOS_RTM_PUBKEY = 5, AMD_BIOS_APCB = 0x60, AMD_BIOS_APOB = 0x61, AMD_BIOS_BIN = 0x62, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 21e7317e22d..b6e14a8f9a3 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -2,6 +2,7 @@ #include #include #include +#include #include "amdfwtool.h" @@ -90,6 +91,9 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, } else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE; subprog = 0; + } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE") == 0) { + fw_type = AMD_HW_IPCFG; + subprog = 0; } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE; subprog = 1; @@ -167,12 +171,22 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { fw_type = AMD_WRAPPED_IKEK; subprog = 0; + } else if (strcmp(fw_name, "PSP_SECG0_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + subprog = 0; } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { fw_type = AMD_SEC_GASKET; subprog = 1; } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { fw_type = AMD_SEC_GASKET; subprog = 2; + } else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_MP2_FW; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { if (cb_config->load_mp2_fw == 1) { fw_type = AMD_MP2_FW; @@ -197,10 +211,44 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, } else { fw_type = AMD_FW_SKIP; } + } else if (strcmp(fw_name, "AMD_DRIVER_ENTRIES") == 0) { + fw_type = AMD_DRIVER_ENTRIES; + subprog = 0; + } else if (strcmp(fw_name, "VBIOS_BTLOADER_FILE") == 0) { + fw_type = AMD_VBIOS_BTLOADER; + subprog = 0; + } else if (strcmp(fw_name, "SECURE_POLICY_L1_FILE") == 0) { + fw_type = AMD_FW_TOS_SEC_POLICY; + subprog = 0; + } else if (strcmp(fw_name, "UNIFIEDUSB_FILE") == 0) { + fw_type = AMD_FW_USB_PHY; + subprog = 0; + } else if (strcmp(fw_name, "DRTMTA_FILE") == 0) { + fw_type = AMD_FW_DRTM_TA; + subprog = 0; + } else if (strcmp(fw_name, "KEYDBBL_FILE") == 0) { + fw_type = AMD_FW_KEYDB_BL; + subprog = 0; + } else if (strcmp(fw_name, "KEYDB_TOS_FILE") == 0) { + fw_type = AMD_FW_KEYDB_TOS; + subprog = 0; + } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { + fw_type = AMD_FW_DMCU_ERAM; + subprog = 0; + } else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) { + fw_type = AMD_FW_DMCU_ISR; + subprog = 0; + } else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) { + fw_type = AMD_FW_KVM_IMAGE; + subprog = 0; + } else if (strcmp(fw_name, "RPMC_FILE") == 0) { + fw_type = AMD_RPMC_NVRAM; + subprog = 0; } else { fw_type = AMD_FW_INVALID; /* TODO: Add more */ } + /* Search and fill the filename */ psp_tableptr = &amd_psp_fw_table[0]; if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) { @@ -261,6 +309,10 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, fw_type = AMD_BIOS_PMUD; subprog = 1; instance = 4; + } else if (strcmp(fw_name, "RTM_PUBKEY_FILE") == 0) { + fw_type = AMD_BIOS_RTM_PUBKEY; + subprog = 0; + instance = 0; } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { if (cb_config->load_mp2_fw == 1) { fw_type = AMD_BIOS_MP2_CFG; diff --git a/util/apcb/description.md b/util/apcb/description.md new file mode 100644 index 00000000000..674243ac2d1 --- /dev/null +++ b/util/apcb/description.md @@ -0,0 +1,4 @@ +AMD PSP Control Block tools + +* _apcb_edit.py_ - This tool allows patching an existing APCB binary with + specific SPDs and GPIO selection pins. `Python3` diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 5d943e43fed..e2a84e4c510 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -359,10 +359,11 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) defer gnvs.Close() Add_gpl(gnvs) - gnvs.WriteString(`#include + gnvs.WriteString(`#include +#include /* FIXME: check this function. */ -void acpi_create_gnvs(struct global_nvs *gnvs) +void mainboard_fill_gnvs(struct global_nvs *gnvs) { /* The lid is open by default. */ gnvs->lids = 1; diff --git a/util/autoport/readme.md b/util/autoport/readme.md index bfaaef6f4e4..f2b2697da6c 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -335,7 +335,7 @@ this value is correct. This can also be determined from the board's schematics. ## GNVS -`acpi_create_gnvs` sets values in GNVS, which then ACPI makes use of for +`mainboard_fill_gnvs` sets values in GNVS, which then ACPI makes use of for various power-related functions. Normally, there is no need to modify it on laptops (desktops have no "lid"!) but it makes sense to proofread it. diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 68cbe681343..950286c6b60 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -44,12 +44,9 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { Comment: "FIXME: check all registers", Registers: map[string]string{ /* FIXME:XX hardcoded. */ - "c1_acpower": "1", - "c2_acpower": "3", - "c3_acpower": "5", - "c1_battery": "1", - "c2_battery": "3", - "c3_battery": "5", + "acpi_c1": "1", + "acpi_c2": "3", + "acpi_c3": "5", }, Children: []DevTreeNode{ { diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 31c3e7c483d..1024ff67b2c 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # @@ -26,6 +26,20 @@ CBMEM_PATH="" # Used if nvramtool is not in default $PATH, e.g. not installed or when using `sudo` NVRAMTOOL_PATH="" +case $(uname) in + FreeBSD) + if [ ! -x /usr/local/bin/gmake ]; then + echo "Please install gmake, or build and install devel/gmake from ports." + exit $EXIT_FAILURE + else + MAKE=gmake + fi + ;; + *) + MAKE=make + ;; +esac + # test a command # # $1: 0 ($LOCAL) to run command locally, @@ -198,7 +212,21 @@ Long options: " } -getopt -T +case $(uname) in + FreeBSD) + if [ ! -x /usr/local/bin/getopt ]; then + echo "Please install getopt, or build and install misc/getopt from ports." + exit $EXIT_FAILURE + else + GETOPT=/usr/local/bin/getopt + fi + ;; + *) + GETOPT=/usr/bin/getopt + ;; +esac + +$GETOPT -T if [ $? -ne 4 ]; then echo "GNU-compatible getopt(1) required." exit $EXIT_FAILURE @@ -208,7 +236,7 @@ LONGOPTS="cbmem:,clobber,help,image:,remote-host:,upload-results" LONGOPTS="${LONGOPTS},serial-device:,serial-speed:" LONGOPTS="${LONGOPTS},ssh-port:" -ARGS=$(getopt -o c:n:Chi:r:s:S:u -l "$LONGOPTS" -n "$0" -- "$@"); +ARGS=$($GETOPT -o c:n:Chi:r:s:S:u -l "$LONGOPTS" -n "$0" -- "$@"); if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi eval set -- "$ARGS" while true ; do @@ -287,7 +315,14 @@ fi # Results will be placed in a temporary location until we're ready to upload. # If the user does not wish to upload, results will remain in /tmp. -tmpdir=$(mktemp -d --tmpdir coreboot_board_status.XXXXXXXX) +case $(uname) in + FreeBSD) + tmpdir=$(mktemp -d -t coreboot_board_status) + ;; + *) + tmpdir=$(mktemp -d --tmpdir coreboot_board_status.XXXXXXXX) + ;; +esac # Obtain coreboot config by running cbfstool on the ROM image. cbfstool may # already exist in build/ or util/cbfstool/, but if not then we'll build it @@ -302,7 +337,7 @@ if [ ! -x $cbfstool_cmd ]; then exit $EXIT_FAILURE fi else - make -C util/cbfstool/ + $MAKE -C util/cbfstool/ do_clean_cbfstool=1 fi fi @@ -313,7 +348,7 @@ echo "Extracting config.txt from $COREBOOT_IMAGE" $cbfstool_cmd "$COREBOOT_IMAGE" extract -n config -f "${tmpdir}/config.txt" >/dev/null 2>&1 mv "${tmpdir}/config.txt" "${tmpdir}/config.short.txt" cp "${tmpdir}/config.short.txt" "${tmpcfg}" -yes "" | make "DOTCONFIG=${tmpcfg}" oldconfig 2>/dev/null >/dev/null +yes "" | $MAKE "DOTCONFIG=${tmpcfg}" oldconfig 2>/dev/null >/dev/null mv "${tmpcfg}" "${tmpdir}/config.txt" rm -f "${tmpcfg}.old" $cbfstool_cmd "$COREBOOT_IMAGE" print > "${tmpdir}/cbfs.txt" @@ -326,10 +361,17 @@ if [ -n "$(echo $rom_contents | grep payload_version)" ]; then echo "Extracting payload_version from $COREBOOT_IMAGE" $cbfstool_cmd "$COREBOOT_IMAGE" extract -n payload_version -f "${tmpdir}/payload_version.txt" >/dev/null 2>&1 fi -md5sum -b "$COREBOOT_IMAGE" > "${tmpdir}/rom_checksum.txt" +case $(uname) in + FreeBSD) + md5 "$COREBOOT_IMAGE" > "${tmpdir}/rom_checksum.txt" + ;; + *) + md5sum -b "$COREBOOT_IMAGE" > "${tmpdir}/rom_checksum.txt" + ;; +esac if test $do_clean_cbfstool -eq 1; then - make -C util/cbfstool clean + $MAKE -C util/cbfstool clean fi # Obtain board and revision info to form the directory structure: diff --git a/util/board_status/getrevision.sh b/util/board_status/getrevision.sh index 20871f6beec..ddbfde0e767 100755 --- a/util/board_status/getrevision.sh +++ b/util/board_status/getrevision.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # From the flashrom project but heavily modified since then. diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 25c5096ae17..41be7820465 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -13,6 +13,7 @@ FLASH@##ROM_BASE## ##ROM_SIZE## { ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## ##SPD_CACHE_ENTRY## + ##VPD_ENTRY## FMAP@##FMAP_BASE## ##FMAP_SIZE## COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## } diff --git a/util/cbfstool/partitioned_file.c b/util/cbfstool/partitioned_file.c index b6d4f1b8080..4835f6bdc2a 100644 --- a/util/cbfstool/partitioned_file.c +++ b/util/cbfstool/partitioned_file.c @@ -1,6 +1,8 @@ /* read and write binary file "partitions" described by FMAP */ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __BSD_VISIBLE 1 + #include "partitioned_file.h" #include "cbfs_sections.h" @@ -8,6 +10,7 @@ #include #include #include +#include struct partitioned_file { struct fmap *fmap; @@ -57,7 +60,7 @@ static partitioned_file_t *reopen_flat_file(const char *filename, access_mode = write_access ? "rb+" : "rb"; file->stream = fopen(filename, access_mode); - if (!file->stream) { + if (!file->stream || flock(fileno(file->stream), LOCK_EX)) { perror(filename); partitioned_file_close(file); return NULL; @@ -78,7 +81,7 @@ partitioned_file_t *partitioned_file_create_flat(const char *filename, } file->stream = fopen(filename, "wb"); - if (!file->stream) { + if (!file->stream || flock(fileno(file->stream), LOCK_EX)) { perror(filename); free(file); return NULL; @@ -268,6 +271,7 @@ void partitioned_file_close(partitioned_file_t *file) file->fmap = NULL; buffer_delete(&file->buffer); if (file->stream) { + flock(fileno(file->stream), LOCK_UN); fclose(file->stream); file->stream = NULL; } diff --git a/util/chromeos/gen_test_hwid.sh b/util/chromeos/gen_test_hwid.sh index f77564a971a..163a12aa0cd 100755 --- a/util/chromeos/gen_test_hwid.sh +++ b/util/chromeos/gen_test_hwid.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/crossgcc/.gitignore b/util/crossgcc/.gitignore index 0dfddd3b66b..e6ff06c9c7f 100644 --- a/util/crossgcc/.gitignore +++ b/util/crossgcc/.gitignore @@ -1,6 +1,7 @@ acpica-unix-*/ binutils-*/ build-*BINUTILS/ +build-*CMAKE/ build-*EXPAT/ build-*GCC/ build-*GDB/ @@ -11,6 +12,7 @@ build-*MPFR/ build-*PYTHON/ build-*LVM/ build-*IASL/ +cmake-*/ expat-*/ gcc-*/ gdb-*/ diff --git a/util/crossgcc/Dockerfile b/util/crossgcc/Dockerfile deleted file mode 100644 index 9f1a58c7601..00000000000 --- a/util/crossgcc/Dockerfile +++ /dev/null @@ -1,37 +0,0 @@ -FROM debian:sid -MAINTAINER Martin Roth - -RUN \ - useradd -p locked -m coreboot && \ - apt-get -qq update && \ - apt-get -qq upgrade && \ - apt-get -qqy install gcc g++ gnat-6 make patch python diffutils bison \ - flex git doxygen ccache subversion p7zip-full unrar-free \ - m4 wget curl bzip2 vim-common cmake xz-utils pkg-config \ - dh-autoreconf unifont \ - libssl-dev libgmp-dev zlib1g-dev libpci-dev liblzma-dev \ - libyaml-dev libncurses5-dev uuid-dev libusb-dev libftdi-dev \ - libusb-1.0-0-dev libreadline-dev libglib2.0-dev libgmp-dev \ - libelf-dev libxml2-dev libfreetype6-dev && \ - apt-get clean - -COPY buildgcc Makefile* root/coreboot/util/crossgcc/ -COPY patches/ /root/coreboot/util/crossgcc/patches/ -COPY sum/ /root/coreboot/util/crossgcc/sum/ -COPY tarballs/ /root/coreboot/util/crossgcc/tarballs/ - -RUN \ - cd /root/coreboot/util/crossgcc && \ - make all_without_gdb \ - BUILD_LANGUAGES=c,ada CPUS=$(nproc) DEST=/opt/xgcc && \ - cd /root && \ - rm -rf coreboot - -RUN mkdir /home/coreboot/.ccache && \ - chown coreboot:coreboot /home/coreboot/.ccache && \ - mkdir /home/coreboot/cb_build && \ - chown coreboot:coreboot /home/coreboot/cb_build -VOLUME /home/coreboot/.ccache - -ENV PATH $PATH:/opt/xgcc/bin -USER coreboot diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 582e600c042..74de5bd91eb 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -65,7 +65,5 @@ jenkins-build-toolchain: $(MAKE) crossgcc clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' #TODO: Re-enable gdb build after the builders can build it again. #$(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)' - rm -f .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does - -cat .xcompile PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) test-toolchain diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5af3d5aadfd..96256cdfb10 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # shellcheck disable=SC2030,SC2031,SC2059 # The above line must be directly after the shebang line. # Disables these warnings: diff --git a/util/docker/Makefile b/util/docker/Makefile index cf14c0d5b48..87e21be8b13 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -43,9 +43,9 @@ test-docker-login: test-docker coreboot-sdk: test-docker @echo "Building coreboot SDK $(crossgcc_version) from commit $(DOCKER_COMMIT)" cat coreboot-sdk/Dockerfile | \ - sed "s/{{DOCKER_COMMIT}}/$(DOCKER_COMMIT)/" | \ - sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/" | \ - sed "s/{{CROSSGCC_PARAM}}/$(COREBOOT_CROSSGCC_PARAM)/" | \ + sed "s/{{DOCKER_COMMIT}}/$(DOCKER_COMMIT)/g" | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/g" | \ + sed "s/{{CROSSGCC_PARAM}}/$(COREBOOT_CROSSGCC_PARAM)/g" | \ $(DOCKER) build -t coreboot/coreboot-sdk:$(COREBOOT_IMAGE_TAG) - upload-coreboot-sdk: test-docker-login @@ -53,7 +53,7 @@ upload-coreboot-sdk: test-docker-login coreboot-jenkins-node: test-docker cat coreboot-jenkins-node/Dockerfile | \ - sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/" | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/g" | \ sed "s|{{SSH_KEY}}|$$(cat coreboot-jenkins-node/authorized_keys)|" | \ $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) - @@ -110,11 +110,11 @@ docker-run-local: test-docker $(DOCKER_CCACHE) docker-build-coreboot: docker-run-local docker-build-coreboot: override DOCKER_RUN_LOCAL := \ - make clean && make $(BUILD_CMD); rm -f .xcompile + make clean && make $(BUILD_CMD) docker-abuild: docker-run-local docker-abuild: override DOCKER_RUN_LOCAL := \ - make clean && util/abuild/abuild $(ABUILD_ARGS); rm -f .xcompile + make clean && util/abuild/abuild $(ABUILD_ARGS) docker-what-jenkins-does: docker-run-local docker-what-jenkins-does: override DOCKER_RUN_LOCAL := \ diff --git a/util/docker/coreboot.org-status/board-status.html/bucketize.sh b/util/docker/coreboot.org-status/board-status.html/bucketize.sh index cb643e73bcc..fd3a94b3722 100755 --- a/util/docker/coreboot.org-status/board-status.html/bucketize.sh +++ b/util/docker/coreboot.org-status/board-status.html/bucketize.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # usage: $0 [weekly|monthly|quarterly] < filenames # sorts files of the form VENDOR/BOARD/COMMIT/DATE/revision.txt # into buckets of the given granularity diff --git a/util/docker/coreboot.org-status/board-status.html/status-to-html.sh b/util/docker/coreboot.org-status/board-status.html/status-to-html.sh index 6630b30c1f4..2fb958c2d4a 100755 --- a/util/docker/coreboot.org-status/board-status.html/status-to-html.sh +++ b/util/docker/coreboot.org-status/board-status.html/status-to-html.sh @@ -1,2 +1,2 @@ -#!/bin/sh +#!/usr/bin/env sh ls -d */*/*/*/ | `dirname $0`/bucketize.sh weekly | `dirname $0`/tohtml.sh diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 98bbc9481e6..0244b8e2720 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh export COREBOOT_DIR="../coreboot.git" export GIT_DIR="$COREBOOT_DIR/.git" CODE_GITWEB="https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=" diff --git a/util/docker/coreboot.org-status/run.sh b/util/docker/coreboot.org-status/run.sh index ba5ec919293..84de3caa20a 100755 --- a/util/docker/coreboot.org-status/run.sh +++ b/util/docker/coreboot.org-status/run.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/docker/doc.coreboot.org/ditaa.sh b/util/docker/doc.coreboot.org/ditaa.sh index 5f27f534973..637379f3e7e 100755 --- a/util/docker/doc.coreboot.org/ditaa.sh +++ b/util/docker/doc.coreboot.org/ditaa.sh @@ -1,2 +1,2 @@ -#!/bin/sh +#!/usr/bin/env sh exec java -jar /usr/lib/ditaa0_9.jar $* diff --git a/util/docker/doc.coreboot.org/makeSphinx.sh b/util/docker/doc.coreboot.org/makeSphinx.sh index 3b0c4e336fe..96a593c7eda 100755 --- a/util/docker/doc.coreboot.org/makeSphinx.sh +++ b/util/docker/doc.coreboot.org/makeSphinx.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash if [ "$1" == "livehtml" ]; then echo "Starting live documentation build" diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh index ec81dd34dc8..53b9a7f8f2c 100755 --- a/util/find_usbdebug/find_usbdebug.sh +++ b/util/find_usbdebug/find_usbdebug.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index 3df3730ef2b..b82a74b5132 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index f0c0b659e29..99c8941be47 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # Part of Gerrit Code Review (http://code.google.com/p/gerrit/) # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/util/gitconfig/pre-commit b/util/gitconfig/pre-commit index 7b7ab4846cf..8b571a72df7 100755 --- a/util/gitconfig/pre-commit +++ b/util/gitconfig/pre-commit @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh ## ## SPDX-License-Identifier: GPL-2.0-only diff --git a/util/gitconfig/test/commit-message-hook.sh b/util/gitconfig/test/commit-message-hook.sh index a99570f1984..f231f1425ef 100755 --- a/util/gitconfig/test/commit-message-hook.sh +++ b/util/gitconfig/test/commit-message-hook.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/util/gitconfig/test/helpers.sh b/util/gitconfig/test/helpers.sh index 2e8b4070f92..fbb844264b7 100644 --- a/util/gitconfig/test/helpers.sh +++ b/util/gitconfig/test/helpers.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/util/gitconfig/test/timeout.sh b/util/gitconfig/test/timeout.sh index 989afcc2b49..2d600f4a779 100755 --- a/util/gitconfig/test/timeout.sh +++ b/util/gitconfig/test/timeout.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/util/ifdtool/Makefile.inc b/util/ifdtool/Makefile.inc new file mode 100644 index 00000000000..b2d8f878041 --- /dev/null +++ b/util/ifdtool/Makefile.inc @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o + +IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror +IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include +IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap +IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h + +$(objutil)/ifdtool/%.o: $(top)/util/ifdtool/%.c + $(HOSTCC) $(IFDTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +$(objutil)/ifdtool/%.o: $(top)/util/cbfstool/flashmap/%.c + $(HOSTCC) $(IFDTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +$(objutil)/ifdtool/ifdtool: $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) + printf " IFDTOOL\n" + $(HOSTCC) $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) -o $@ diff --git a/util/kconfig/check.sh b/util/kconfig/check.sh index 55b79ba1ba2..2e0060fd458 100755 --- a/util/kconfig/check.sh +++ b/util/kconfig/check.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # Needed for systems without gettext $* -x c -o /dev/null - > /dev/null 2>&1 << EOF #include diff --git a/util/kconfig/lxdialog/check-lxdialog.sh b/util/kconfig/lxdialog/check-lxdialog.sh index 78939da0b2e..6833febc2ca 100755 --- a/util/kconfig/lxdialog/check-lxdialog.sh +++ b/util/kconfig/lxdialog/check-lxdialog.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # Check ncurses compatibility # What library to link diff --git a/util/lint/lint b/util/lint/lint index a8c08d53704..6bf982d1afa 100755 --- a/util/lint/lint +++ b/util/lint/lint @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index c43151acfc5..2f65321a6fe 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-001-no-global-config-in-romstage b/util/lint/lint-001-no-global-config-in-romstage index 1ed55e0ca7a..e81bea7d341 100755 --- a/util/lint/lint-001-no-global-config-in-romstage +++ b/util/lint/lint-001-no-global-config-in-romstage @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch index bc34e6bb4f7..113d0ae9d12 100755 --- a/util/lint/lint-007-checkpatch +++ b/util/lint/lint-007-checkpatch @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-008-kconfig b/util/lint/lint-008-kconfig index 31aba55e921..c24ff14069c 100755 --- a/util/lint/lint-008-kconfig +++ b/util/lint/lint-008-kconfig @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-014-qualified-types b/util/lint/lint-014-qualified-types index 8da23b6d1fb..48810cf3cd4 100755 --- a/util/lint/lint-014-qualified-types +++ b/util/lint/lint-014-qualified-types @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-extended-007-checkpatch b/util/lint/lint-extended-007-checkpatch index e2b39de3e6a..8ec11885b1d 100755 --- a/util/lint/lint-extended-007-checkpatch +++ b/util/lint/lint-extended-007-checkpatch @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines index 74f1f03ecc4..3ab0fbfbc90 100755 --- a/util/lint/lint-extended-015-final-newlines +++ b/util/lint/lint-extended-015-final-newlines @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-extended-020-signed-off-by b/util/lint/lint-extended-020-signed-off-by index cc1b7acf811..6d569aa80a7 100755 --- a/util/lint/lint-extended-020-signed-off-by +++ b/util/lint/lint-extended-020-signed-off-by @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # DESCR: Check for a signed-off-by line on the latest git commit diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 518b232f327..ccecba6ce49 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-only # # DESCR: Check that files have license headers diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 430404383a6..fd4d0e4d12e 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-004-style-labels b/util/lint/lint-stable-004-style-labels index 36d2581974e..393774fdaef 100755 --- a/util/lint/lint-stable-004-style-labels +++ b/util/lint/lint-stable-004-style-labels @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index d87f8a41e94..617440bd146 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # DESCR: Check that every board has a meaningful board_info.txt diff --git a/util/lint/lint-stable-006-board-name b/util/lint/lint-stable-006-board-name index 77d4e567085..6f4e4b67512 100755 --- a/util/lint/lint-stable-006-board-name +++ b/util/lint/lint-stable-006-board-name @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # DESCR: Check that every vendor and board has a Kconfig.name diff --git a/util/lint/lint-stable-008-kconfig b/util/lint/lint-stable-008-kconfig index 3b204fbd577..3323971fac2 100755 --- a/util/lint/lint-stable-008-kconfig +++ b/util/lint/lint-stable-008-kconfig @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-009-old-licenses b/util/lint/lint-stable-009-old-licenses index d2aff3a83ae..8226fdd6423 100755 --- a/util/lint/lint-stable-009-old-licenses +++ b/util/lint/lint-stable-009-old-licenses @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-010-asm-syntax b/util/lint/lint-stable-010-asm-syntax index 344068fcb35..474a05d4236 100755 --- a/util/lint/lint-stable-010-asm-syntax +++ b/util/lint/lint-stable-010-asm-syntax @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-012-executable-bit b/util/lint/lint-stable-012-executable-bit index 5651a67d543..640bb08870e 100755 --- a/util/lint/lint-stable-012-executable-bit +++ b/util/lint/lint-stable-012-executable-bit @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # DESCR: Check that source files are not executable diff --git a/util/lint/lint-stable-013-site-local b/util/lint/lint-stable-013-site-local index 4579cf94c52..53693f21d35 100755 --- a/util/lint/lint-stable-013-site-local +++ b/util/lint/lint-stable-013-site-local @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # DESCR: Verify that site-local is not in the coreboot repository diff --git a/util/lint/lint-stable-016-non-ascii b/util/lint/lint-stable-016-non-ascii index 4c97c37ba02..52b6679aa19 100755 --- a/util/lint/lint-stable-016-non-ascii +++ b/util/lint/lint-stable-016-non-ascii @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs index 4f298508cea..311ef38cd0c 100755 --- a/util/lint/lint-stable-017-configs +++ b/util/lint/lint-stable-017-configs @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-018-symlinks b/util/lint/lint-stable-018-symlinks index 8739a8b0190..cd5c8440c1e 100755 --- a/util/lint/lint-stable-018-symlinks +++ b/util/lint/lint-stable-018-symlinks @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-019-header-files b/util/lint/lint-stable-019-header-files index 11cb6b750c9..fc440d1b695 100755 --- a/util/lint/lint-stable-019-header-files +++ b/util/lint/lint-stable-019-header-files @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-021-coreboot-lowercase b/util/lint/lint-stable-021-coreboot-lowercase index 45bc8199fdc..b13cb4487ed 100755 --- a/util/lint/lint-stable-021-coreboot-lowercase +++ b/util/lint/lint-stable-021-coreboot-lowercase @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-022-clang-format b/util/lint/lint-stable-022-clang-format index 031fdb1f394..9c94fbc0601 100755 --- a/util/lint/lint-stable-022-clang-format +++ b/util/lint/lint-stable-022-clang-format @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-023-filenames b/util/lint/lint-stable-023-filenames index a70f9889578..8b519a80dd3 100755 --- a/util/lint/lint-stable-023-filenames +++ b/util/lint/lint-stable-023-filenames @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/lint/lint-stable-024-kconfig-no-subsystem b/util/lint/lint-stable-024-kconfig-no-subsystem index 46dbc971f08..9a532e8c5ef 100755 --- a/util/lint/lint-stable-024-kconfig-no-subsystem +++ b/util/lint/lint-stable-024-kconfig-no-subsystem @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: GPL-2.0-or-later # # DESCR: Check that no board's Kconfig sets SUBSYSTEM_(VENDOR|DEVICE)_ID diff --git a/util/lint/remccoms3.sed b/util/lint/remccoms3.sed index 429d3bd4229..fd700df80fb 100644 --- a/util/lint/remccoms3.sed +++ b/util/lint/remccoms3.sed @@ -1,4 +1,4 @@ -#! /bin/sed -nf +#!/usr/bin/env sed -nf # Remove C and C++ comments, by Brian Hiles (brian_hiles@rocketmail.com) diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 87380779bce..96a689e380b 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -15,6 +15,9 @@ # Reason: AFE means `Analog Front-End`, and appears on register names. #afe||safe # +# Reason: It is sometimes used as an abbreviation for `presence`. +#pres||press +# # Reason: On RISC-V, `SEPC` is the name of a register. #sepc||spec # @@ -6766,7 +6769,6 @@ pressentation||presentation pressented||presented pressent||present pressre||pressure -pres||press preverve||preserve prevews||previews prevew||preview diff --git a/util/mainboard/description.md b/util/mainboard/description.md new file mode 100644 index 00000000000..4050a804067 --- /dev/null +++ b/util/mainboard/description.md @@ -0,0 +1,3 @@ +mainboard specific scripts + +* _google_ - Directory for google mainboard specific scripts diff --git a/util/msrtool/configure b/util/msrtool/configure index cf78ad14102..59d5c63639e 100755 --- a/util/msrtool/configure +++ b/util/msrtool/configure @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # # This program is free software; you can redistribute it and/or modify diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index f5e6738c5c3..e4a44f45c1f 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -18,14 +18,14 @@ #define HEXCHARS "0123456789abcdefABCDEF" -enum { +typedef enum { MSRTYPE_RDONLY, MSRTYPE_RDWR, MSRTYPE_WRONLY, MSRTYPE_EOT } MsrTypes; -enum { +typedef enum { PRESENT_RSVD, PRESENT_DEC, PRESENT_BIN, diff --git a/util/post/Makefile b/util/post/Makefile index d0a3eb99e40..0941cde0a10 100644 --- a/util/post/Makefile +++ b/util/post/Makefile @@ -2,3 +2,5 @@ all: $(CC) post.c -o post clean: rm -f post + +distclean: clean diff --git a/util/qemu/description.md b/util/qemu/description.md new file mode 100644 index 00000000000..6e3a16c398d --- /dev/null +++ b/util/qemu/description.md @@ -0,0 +1,3 @@ +__qemu__ + +- Makefile & comprehensive default config for QEMU Q35 emulation diff --git a/util/release/gerrit_stats.pl b/util/release/gerrit_stats.pl index 65004263072..94681579e19 100755 --- a/util/release/gerrit_stats.pl +++ b/util/release/gerrit_stats.pl @@ -1,4 +1,4 @@ -#!/usr/bin/perl +#!/usr/bin/env perl # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/riscv/make-spike-elf.sh b/util/riscv/make-spike-elf.sh index 834e8d2cb67..135b62ad977 100755 --- a/util/riscv/make-spike-elf.sh +++ b/util/riscv/make-spike-elf.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # # This script is based on: # https://docs.google.com/document/d/1Pvf9Yxorcd3sbgs8WcomcTl3J4bmX6e1UE0ROCefR88 diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 18b34b5e87e..c3d985945a7 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -349,8 +349,8 @@ static void yynoreturn yy_fatal_error ( const char* msg ); (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 49 -#define YY_END_OF_BUFFER 50 +#define YY_NUM_RULES 50 +#define YY_END_OF_BUFFER 51 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -358,31 +358,31 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[203] = +static const flex_int16_t yy_accept[206] = { 0, - 0, 0, 50, 48, 1, 3, 48, 48, 48, 43, - 43, 41, 44, 48, 44, 44, 44, 44, 44, 48, - 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, - 1, 3, 48, 0, 48, 48, 0, 2, 43, 44, - 48, 48, 48, 9, 48, 48, 44, 48, 48, 48, - 48, 48, 48, 48, 48, 48, 48, 35, 48, 48, - 48, 48, 48, 48, 15, 48, 48, 48, 48, 48, - 48, 48, 48, 48, 47, 47, 48, 0, 42, 48, - 48, 48, 25, 48, 48, 34, 39, 48, 48, 48, - 48, 48, 22, 48, 48, 33, 48, 31, 48, 48, - - 16, 48, 19, 21, 48, 8, 48, 48, 29, 48, - 30, 7, 48, 0, 45, 48, 4, 48, 48, 48, - 32, 48, 48, 48, 48, 48, 48, 48, 48, 28, - 48, 48, 48, 48, 48, 46, 46, 6, 48, 48, - 48, 12, 48, 48, 48, 48, 48, 23, 48, 48, - 14, 48, 48, 48, 48, 5, 26, 48, 48, 17, - 48, 20, 48, 13, 48, 48, 48, 48, 48, 27, - 37, 48, 48, 48, 48, 48, 48, 48, 48, 48, - 10, 48, 48, 48, 11, 48, 18, 48, 48, 48, - 36, 48, 48, 24, 48, 38, 48, 48, 48, 48, - - 40, 0 + 0, 0, 51, 49, 1, 3, 49, 49, 49, 44, + 44, 42, 45, 49, 45, 45, 45, 45, 45, 49, + 49, 49, 49, 49, 49, 49, 49, 49, 49, 49, + 1, 3, 49, 0, 49, 49, 0, 2, 44, 45, + 49, 49, 49, 9, 49, 49, 45, 49, 49, 49, + 49, 49, 49, 49, 49, 49, 49, 49, 36, 49, + 49, 49, 49, 49, 49, 15, 49, 49, 49, 49, + 49, 49, 49, 49, 49, 48, 48, 49, 0, 43, + 49, 49, 49, 25, 49, 49, 35, 40, 49, 49, + 49, 49, 49, 49, 22, 49, 49, 34, 49, 31, + + 49, 49, 16, 49, 19, 21, 49, 8, 49, 49, + 29, 49, 30, 7, 49, 0, 46, 49, 4, 49, + 49, 49, 32, 49, 49, 49, 33, 49, 49, 49, + 49, 49, 28, 49, 49, 49, 49, 49, 47, 47, + 6, 49, 49, 49, 12, 49, 49, 49, 49, 49, + 23, 49, 49, 14, 49, 49, 49, 49, 5, 26, + 49, 49, 17, 49, 20, 49, 13, 49, 49, 49, + 49, 49, 27, 38, 49, 49, 49, 49, 49, 49, + 49, 49, 49, 10, 49, 49, 49, 11, 49, 18, + 49, 49, 49, 37, 49, 49, 24, 49, 39, 49, + + 49, 49, 49, 41, 0 } ; static const YY_CHAR yy_ec[256] = @@ -425,136 +425,138 @@ static const YY_CHAR yy_meta[40] = 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[210] = +static const flex_int16_t yy_base[213] = { 0, - 0, 0, 275, 0, 272, 276, 270, 38, 42, 39, - 234, 0, 45, 257, 55, 59, 83, 65, 62, 249, - 244, 68, 25, 48, 54, 75, 247, 75, 234, 0, - 264, 276, 106, 260, 111, 76, 261, 276, 0, 110, - 113, 248, 237, 0, 236, 225, 119, 232, 227, 237, - 226, 234, 238, 225, 232, 232, 226, 232, 217, 217, - 227, 217, 219, 221, 0, 208, 216, 210, 210, 63, - 220, 212, 218, 118, 0, 276, 135, 230, 0, 223, - 216, 202, 215, 205, 212, 0, 0, 203, 201, 207, - 204, 204, 0, 202, 192, 0, 196, 0, 200, 190, - - 0, 193, 0, 0, 199, 0, 191, 190, 0, 181, - 0, 0, 208, 207, 0, 178, 0, 191, 190, 183, - 0, 187, 177, 173, 183, 171, 177, 182, 183, 0, - 170, 177, 164, 167, 156, 0, 276, 0, 168, 172, - 164, 0, 163, 165, 161, 163, 168, 0, 152, 157, - 0, 150, 150, 149, 146, 0, 0, 158, 160, 0, - 144, 161, 147, 0, 154, 158, 139, 139, 146, 0, - 0, 145, 137, 136, 121, 132, 118, 128, 118, 110, - 0, 122, 120, 125, 0, 114, 0, 115, 118, 110, - 0, 107, 109, 0, 107, 0, 86, 80, 62, 61, - - 0, 276, 48, 155, 157, 159, 161, 163, 165 + 0, 0, 278, 0, 275, 279, 273, 38, 42, 39, + 237, 0, 45, 260, 55, 59, 83, 65, 62, 54, + 248, 68, 25, 59, 73, 86, 251, 81, 238, 0, + 268, 279, 77, 264, 104, 117, 265, 279, 0, 114, + 117, 252, 241, 0, 240, 229, 123, 236, 231, 241, + 230, 238, 242, 229, 231, 235, 235, 229, 235, 220, + 220, 230, 220, 222, 224, 0, 211, 219, 213, 213, + 118, 223, 215, 221, 92, 0, 279, 140, 233, 0, + 226, 219, 205, 218, 208, 215, 0, 0, 206, 204, + 210, 207, 198, 206, 0, 204, 194, 0, 198, 0, + + 202, 192, 0, 195, 0, 0, 201, 0, 193, 192, + 0, 183, 0, 0, 210, 209, 0, 180, 0, 193, + 192, 185, 0, 189, 179, 175, 0, 185, 173, 179, + 184, 185, 0, 172, 179, 166, 169, 158, 0, 279, + 0, 170, 174, 166, 0, 165, 167, 163, 165, 170, + 0, 154, 159, 0, 152, 152, 151, 148, 0, 0, + 160, 162, 0, 146, 163, 149, 0, 156, 160, 141, + 141, 148, 0, 0, 147, 126, 125, 123, 134, 120, + 130, 120, 112, 0, 124, 122, 127, 0, 116, 0, + 117, 119, 101, 0, 93, 97, 0, 86, 0, 74, + + 64, 45, 46, 0, 279, 48, 159, 161, 163, 165, + 167, 169 } ; -static const flex_int16_t yy_def[210] = +static const flex_int16_t yy_def[213] = { 0, - 202, 1, 202, 203, 202, 202, 203, 204, 205, 203, - 10, 203, 10, 203, 10, 10, 10, 10, 10, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 202, 202, 204, 206, 207, 205, 208, 202, 10, 10, - 10, 203, 203, 203, 203, 203, 10, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 202, 207, 209, 41, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 202, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 202, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - - 203, 0, 202, 202, 202, 202, 202, 202, 202 + 205, 1, 205, 206, 205, 205, 206, 207, 208, 206, + 10, 206, 10, 206, 10, 10, 10, 10, 10, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 205, 205, 207, 209, 210, 208, 211, 205, 10, 10, + 10, 206, 206, 206, 206, 206, 10, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 205, 210, 212, 41, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 205, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 205, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, + + 206, 206, 206, 206, 0, 205, 205, 205, 205, 205, + 205, 205 } ; -static const flex_int16_t yy_nxt[316] = +static const flex_int16_t yy_nxt[319] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 15, 13, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4, 25, 26, 4, 27, 28, 4, 29, 4, 4, 4, 4, 34, - 34, 60, 35, 37, 38, 39, 39, 39, 30, 40, - 40, 40, 40, 40, 61, 40, 40, 40, 40, 40, + 34, 61, 35, 37, 38, 39, 39, 39, 30, 40, 40, 40, 40, 40, 62, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 63, 64, 56, 37, 38, 201, - 43, 65, 45, 66, 106, 107, 52, 44, 46, 40, - 40, 40, 50, 67, 200, 57, 58, 51, 53, 59, - - 199, 71, 68, 47, 72, 198, 69, 34, 34, 73, - 75, 48, 78, 78, 49, 30, 40, 40, 40, 79, - 79, 79, 197, 79, 79, 40, 40, 40, 196, 79, - 79, 79, 79, 79, 79, 111, 78, 78, 112, 113, - 195, 194, 193, 192, 191, 190, 189, 188, 187, 186, - 185, 184, 183, 182, 84, 33, 33, 36, 36, 34, - 34, 77, 77, 37, 37, 78, 78, 181, 180, 179, - 178, 177, 176, 175, 174, 173, 172, 171, 170, 169, - 168, 167, 166, 165, 164, 163, 162, 161, 160, 159, - 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, - - 148, 147, 146, 145, 144, 143, 142, 141, 140, 139, - 138, 137, 136, 135, 134, 133, 132, 131, 130, 129, - 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, - 118, 117, 116, 115, 114, 110, 109, 108, 105, 104, - 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, - 93, 92, 91, 90, 89, 88, 87, 86, 85, 83, - 82, 81, 80, 38, 76, 31, 74, 70, 55, 54, - 42, 41, 32, 31, 202, 3, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202 + 40, 40, 40, 40, 204, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 54, 63, 57, 203, 34, 34, + 43, 76, 45, 55, 202, 64, 52, 44, 46, 40, + 40, 40, 50, 201, 65, 58, 59, 51, 53, 60, + + 66, 200, 67, 47, 68, 79, 79, 72, 30, 113, + 73, 48, 114, 69, 49, 74, 199, 70, 37, 38, + 40, 40, 40, 80, 80, 80, 198, 80, 80, 40, + 40, 40, 197, 80, 80, 80, 80, 80, 80, 108, + 109, 79, 79, 196, 115, 195, 194, 193, 192, 191, + 190, 189, 188, 187, 186, 185, 184, 183, 85, 33, + 33, 36, 36, 34, 34, 78, 78, 37, 37, 79, + 79, 182, 181, 180, 179, 178, 177, 176, 175, 174, + 173, 172, 171, 170, 169, 168, 167, 166, 165, 164, + 163, 162, 161, 160, 159, 158, 157, 156, 155, 154, + + 153, 152, 151, 150, 149, 148, 147, 146, 145, 144, + 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, + 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, + 123, 122, 121, 120, 119, 118, 117, 116, 112, 111, + 110, 107, 106, 105, 104, 103, 102, 101, 100, 99, + 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, + 88, 87, 86, 84, 83, 82, 81, 38, 77, 31, + 75, 71, 56, 42, 41, 32, 31, 205, 3, 205, + 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, + 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, + + 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, + 205, 205, 205, 205, 205, 205, 205, 205 } ; -static const flex_int16_t yy_chk[316] = +static const flex_int16_t yy_chk[319] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, - 8, 23, 8, 9, 9, 10, 10, 10, 203, 10, + 8, 23, 8, 9, 9, 10, 10, 10, 206, 10, 10, 13, 13, 13, 23, 10, 10, 10, 10, 10, - 10, 15, 15, 15, 24, 16, 16, 16, 19, 19, - 19, 18, 18, 18, 24, 25, 22, 36, 36, 200, - 15, 25, 16, 25, 70, 70, 19, 15, 16, 17, - 17, 17, 18, 26, 199, 22, 22, 18, 19, 22, - - 198, 28, 26, 17, 28, 197, 26, 33, 33, 28, - 33, 17, 35, 35, 17, 35, 40, 40, 40, 41, - 41, 41, 195, 41, 41, 47, 47, 47, 193, 41, - 41, 41, 41, 41, 41, 74, 77, 77, 74, 77, - 192, 190, 189, 188, 186, 184, 183, 182, 180, 179, - 178, 177, 176, 175, 47, 204, 204, 205, 205, 206, - 206, 207, 207, 208, 208, 209, 209, 174, 173, 172, - 169, 168, 167, 166, 165, 163, 162, 161, 159, 158, - 155, 154, 153, 152, 150, 149, 147, 146, 145, 144, - 143, 141, 140, 139, 135, 134, 133, 132, 131, 129, - - 128, 127, 126, 125, 124, 123, 122, 120, 119, 118, - 116, 114, 113, 110, 108, 107, 105, 102, 100, 99, - 97, 95, 94, 92, 91, 90, 89, 88, 85, 84, - 83, 82, 81, 80, 78, 73, 72, 71, 69, 68, - 67, 66, 64, 63, 62, 61, 60, 59, 58, 57, - 56, 55, 54, 53, 52, 51, 50, 49, 48, 46, - 45, 43, 42, 37, 34, 31, 29, 27, 21, 20, - 14, 11, 7, 5, 3, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202 + 10, 15, 15, 15, 203, 16, 16, 16, 19, 19, + 19, 18, 18, 18, 20, 24, 22, 202, 33, 33, + 15, 33, 16, 20, 201, 24, 19, 15, 16, 17, + 17, 17, 18, 200, 25, 22, 22, 18, 19, 22, + + 25, 198, 25, 17, 26, 35, 35, 28, 35, 75, + 28, 17, 75, 26, 17, 28, 196, 26, 36, 36, + 40, 40, 40, 41, 41, 41, 195, 41, 41, 47, + 47, 47, 193, 41, 41, 41, 41, 41, 41, 71, + 71, 78, 78, 192, 78, 191, 189, 187, 186, 185, + 183, 182, 181, 180, 179, 178, 177, 176, 47, 207, + 207, 208, 208, 209, 209, 210, 210, 211, 211, 212, + 212, 175, 172, 171, 170, 169, 168, 166, 165, 164, + 162, 161, 158, 157, 156, 155, 153, 152, 150, 149, + 148, 147, 146, 144, 143, 142, 138, 137, 136, 135, + + 134, 132, 131, 130, 129, 128, 126, 125, 124, 122, + 121, 120, 118, 116, 115, 112, 110, 109, 107, 104, + 102, 101, 99, 97, 96, 94, 93, 92, 91, 90, + 89, 86, 85, 84, 83, 82, 81, 79, 74, 73, + 72, 70, 69, 68, 67, 65, 64, 63, 62, 61, + 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 46, 45, 43, 42, 37, 34, 31, + 29, 27, 21, 14, 11, 7, 5, 3, 205, 205, + 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, + 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, + + 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, + 205, 205, 205, 205, 205, 205, 205, 205 } ; static yy_state_type yy_last_accepting_state; @@ -819,13 +821,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 203 ) + if ( yy_current_state >= 206 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 276 ); + while ( yy_base[yy_current_state] != 279 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -981,43 +983,43 @@ YY_RULE_SETUP YY_BREAK case 33: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=GPIO; return(BUS);} YY_BREAK case 34: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 35: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 36: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 37: YY_RULE_SETUP -{return(INHERIT);} +{return(IOAPIC_IRQ);} YY_BREAK case 38: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(INHERIT);} YY_BREAK case 39: YY_RULE_SETUP -{return(END);} +{return(SUBSYSTEMID);} YY_BREAK case 40: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(END);} YY_BREAK case 41: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 42: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 43: YY_RULE_SETUP @@ -1029,12 +1031,11 @@ YY_RULE_SETUP YY_BREAK case 45: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 46: -/* rule 46 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 47: /* rule 47 can match eol */ @@ -1042,11 +1043,16 @@ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 48: +/* rule 48 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 49: YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} + YY_BREAK +case 50: +YY_RULE_SETUP ECHO; YY_BREAK case YY_STATE_EOF(INITIAL): @@ -1345,7 +1351,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 203 ) + if ( yy_current_state >= 206 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1373,11 +1379,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 203 ) + if ( yy_current_state >= 206 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 202); + yy_is_jam = (yy_current_state == 205); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 815bfc7e555..ca5389e50ab 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -793,6 +793,10 @@ static struct device *new_device_with_path(struct bus *parent, case LPC: new_d->path = ".type=DEVICE_PATH_LPC,{.lpc={ .addr = 0x%x }}"; break; + + case GPIO: + new_d->path = ".type=DEVICE_PATH_GPIO,{.gpio={ .id = 0x%x }}"; + break; } return new_d; @@ -1081,12 +1085,9 @@ static void emit_dev_links(FILE *fil, struct device *ptr) fprintf(fil, "\t};\n"); } -static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) +static struct chip_instance *get_chip_instance(const struct device *dev) { - int pin; - struct chip_instance *chip_ins = ptr->chip_instance; - int has_children = dev_has_children(ptr); - + struct chip_instance *chip_ins = dev->chip_instance; /* * If the chip instance of device has base_chip_instance pointer set, then follow that * to update the chip instance for current device. @@ -1094,6 +1095,15 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next if (chip_ins->base_chip_instance) chip_ins = chip_ins->base_chip_instance; + return chip_ins; +} + +static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) +{ + int pin; + struct chip_instance *chip_ins = get_chip_instance(ptr); + int has_children = dev_has_children(ptr); + /* Emit probe structures. */ if (ptr->probe && (emit_fw_config_probe(fil, ptr) < 0)) { if (head) @@ -1205,18 +1215,27 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next) { + struct chip_instance *chip_ins = get_chip_instance(ptr); + /* Only devices on root bus here. */ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { - fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", + fprintf(head, "extern DEVTREE_CONST struct device *const __pci_0_%02x_%d;\n", ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", + fprintf(fil, "DEVTREE_CONST struct device *const __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + + if (chip_ins->chip->chiph_exists) { + fprintf(head, "extern DEVTREE_CONST void *const __pci_0_%02x_%d_config;\n", + ptr->path_a, ptr->path_b); + fprintf(fil, "DEVTREE_CONST void *const __pci_0_%02x_%d_config = &%s_info_%d;\n", + ptr->path_a, ptr->path_b, chip_ins->chip->name_underscore, chip_ins->id); + } } if (ptr->bustype == PNP) { - fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n", + fprintf(head, "extern DEVTREE_CONST struct device *const __pnp_%04x_%02x;\n", ptr->path_a, ptr->path_b); - fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", + fprintf(fil, "DEVTREE_CONST struct device *const __pnp_%04x_%02x = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); } } @@ -1529,6 +1548,12 @@ static void override_devicetree(struct bus *base_parent, * | | | * +-----------------------------------------------------------------+ * | | | + * | smbios_slot info | Copy SMBIOS slot information from override.| + * | | This allows variants to override PCI(e) | + * | | slot information in SMBIOS tables. | + * | | | + * +-----------------------------------------------------------------+ + * | | | * | chip_instance | Each register of chip_instance is copied | * | | over from override device to base device: | * | | 1. If register with same key is present in | @@ -1639,6 +1664,12 @@ static void update_device(struct device *base_dev, struct device *override_dev) */ base_dev->probe = override_dev->probe; + /* Copy SMBIOS slot information from base device */ + base_dev->smbios_slot_type = override_dev->smbios_slot_type; + base_dev->smbios_slot_length = override_dev->smbios_slot_length; + base_dev->smbios_slot_data_width = override_dev->smbios_slot_data_width; + base_dev->smbios_slot_designation = override_dev->smbios_slot_designation; + /* * Update base_chip_instance member in chip instance of override tree to forward it to * the chip instance in base tree. diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index a772b96b364..5bdc52b6920 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -40,6 +40,7 @@ spi {yylval.number=SPI; return(BUS);} usb {yylval.number=USB; return(BUS);} lpc {yylval.number=LPC; return(BUS);} espi {yylval.number=ESPI; return(BUS);} +gpio {yylval.number=GPIO; return(BUS);} irq {yylval.number=IRQ; return(RESOURCE);} drq {yylval.number=DRQ; return(RESOURCE);} io {yylval.number=IO; return(RESOURCE);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 43fd14f0901..a8d1e1db1f3 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.6.3. */ +/* A Bison parser, made by GNU Bison 3.7.2. */ /* Bison implementation for Yacc-like parsers in C @@ -49,7 +49,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.6.3" +#define YYBISON_VERSION "3.7.2" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -71,6 +71,7 @@ /* sconfig, coreboot device tree compiler */ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include "sconfig.h" int yylex(); @@ -103,96 +104,7 @@ static struct fw_config_field *cur_field; # endif # endif -/* Use api.header.include to #include this header - instead of duplicating it here. */ -#ifndef YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -/* Debug traces. */ -#ifndef YYDEBUG -# define YYDEBUG 0 -#endif -#if YYDEBUG -extern int yydebug; -#endif - -/* Token kinds. */ -#ifndef YYTOKENTYPE -# define YYTOKENTYPE - enum yytokentype - { - YYEMPTY = -2, - YYEOF = 0, /* "end of file" */ - YYerror = 256, /* error */ - YYUNDEF = 257, /* "invalid token" */ - CHIP = 258, /* CHIP */ - DEVICE = 259, /* DEVICE */ - REGISTER = 260, /* REGISTER */ - ALIAS = 261, /* ALIAS */ - REFERENCE = 262, /* REFERENCE */ - ASSOCIATION = 263, /* ASSOCIATION */ - BOOL = 264, /* BOOL */ - STATUS = 265, /* STATUS */ - MANDATORY = 266, /* MANDATORY */ - BUS = 267, /* BUS */ - RESOURCE = 268, /* RESOURCE */ - END = 269, /* END */ - EQUALS = 270, /* EQUALS */ - HEX = 271, /* HEX */ - STRING = 272, /* STRING */ - PCI = 273, /* PCI */ - PNP = 274, /* PNP */ - I2C = 275, /* I2C */ - APIC = 276, /* APIC */ - CPU_CLUSTER = 277, /* CPU_CLUSTER */ - CPU = 278, /* CPU */ - DOMAIN = 279, /* DOMAIN */ - IRQ = 280, /* IRQ */ - DRQ = 281, /* DRQ */ - SLOT_DESC = 282, /* SLOT_DESC */ - IO = 283, /* IO */ - NUMBER = 284, /* NUMBER */ - SUBSYSTEMID = 285, /* SUBSYSTEMID */ - INHERIT = 286, /* INHERIT */ - IOAPIC_IRQ = 287, /* IOAPIC_IRQ */ - IOAPIC = 288, /* IOAPIC */ - PCIINT = 289, /* PCIINT */ - GENERIC = 290, /* GENERIC */ - SPI = 291, /* SPI */ - USB = 292, /* USB */ - MMIO = 293, /* MMIO */ - LPC = 294, /* LPC */ - ESPI = 295, /* ESPI */ - FW_CONFIG_TABLE = 296, /* FW_CONFIG_TABLE */ - FW_CONFIG_FIELD = 297, /* FW_CONFIG_FIELD */ - FW_CONFIG_OPTION = 298, /* FW_CONFIG_OPTION */ - FW_CONFIG_PROBE = 299 /* FW_CONFIG_PROBE */ - }; - typedef enum yytokentype yytoken_kind_t; -#endif - -/* Value type. */ -#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED -union YYSTYPE -{ - - struct device *dev; - struct chip_instance *chip_instance; - char *string; - int number; - - -}; -typedef union YYSTYPE YYSTYPE; -# define YYSTYPE_IS_TRIVIAL 1 -# define YYSTYPE_IS_DECLARED 1 -#endif - - -extern YYSTYPE yylval; - -int yyparse (void); - -#endif /* !YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#include "sconfig.tab.h_shipped" /* Symbol kind. */ enum yysymbol_kind_t { @@ -238,36 +150,37 @@ enum yysymbol_kind_t YYSYMBOL_MMIO = 38, /* MMIO */ YYSYMBOL_LPC = 39, /* LPC */ YYSYMBOL_ESPI = 40, /* ESPI */ - YYSYMBOL_FW_CONFIG_TABLE = 41, /* FW_CONFIG_TABLE */ - YYSYMBOL_FW_CONFIG_FIELD = 42, /* FW_CONFIG_FIELD */ - YYSYMBOL_FW_CONFIG_OPTION = 43, /* FW_CONFIG_OPTION */ - YYSYMBOL_FW_CONFIG_PROBE = 44, /* FW_CONFIG_PROBE */ - YYSYMBOL_YYACCEPT = 45, /* $accept */ - YYSYMBOL_devtree = 46, /* devtree */ - YYSYMBOL_chipchildren = 47, /* chipchildren */ - YYSYMBOL_devicechildren = 48, /* devicechildren */ - YYSYMBOL_chip = 49, /* chip */ - YYSYMBOL_50_1 = 50, /* @1 */ - YYSYMBOL_device = 51, /* device */ - YYSYMBOL_52_2 = 52, /* @2 */ - YYSYMBOL_53_3 = 53, /* @3 */ - YYSYMBOL_alias = 54, /* alias */ - YYSYMBOL_status = 55, /* status */ - YYSYMBOL_resource = 56, /* resource */ - YYSYMBOL_reference = 57, /* reference */ - YYSYMBOL_registers = 58, /* registers */ - YYSYMBOL_subsystemid = 59, /* subsystemid */ - YYSYMBOL_ioapic_irq = 60, /* ioapic_irq */ - YYSYMBOL_smbios_slot_desc = 61, /* smbios_slot_desc */ - YYSYMBOL_fw_config_table = 62, /* fw_config_table */ - YYSYMBOL_fw_config_table_children = 63, /* fw_config_table_children */ - YYSYMBOL_fw_config_field_children = 64, /* fw_config_field_children */ - YYSYMBOL_fw_config_field = 65, /* fw_config_field */ - YYSYMBOL_66_4 = 66, /* $@4 */ - YYSYMBOL_67_5 = 67, /* $@5 */ - YYSYMBOL_68_6 = 68, /* $@6 */ - YYSYMBOL_fw_config_option = 69, /* fw_config_option */ - YYSYMBOL_fw_config_probe = 70 /* fw_config_probe */ + YYSYMBOL_GPIO = 41, /* GPIO */ + YYSYMBOL_FW_CONFIG_TABLE = 42, /* FW_CONFIG_TABLE */ + YYSYMBOL_FW_CONFIG_FIELD = 43, /* FW_CONFIG_FIELD */ + YYSYMBOL_FW_CONFIG_OPTION = 44, /* FW_CONFIG_OPTION */ + YYSYMBOL_FW_CONFIG_PROBE = 45, /* FW_CONFIG_PROBE */ + YYSYMBOL_YYACCEPT = 46, /* $accept */ + YYSYMBOL_devtree = 47, /* devtree */ + YYSYMBOL_chipchildren = 48, /* chipchildren */ + YYSYMBOL_devicechildren = 49, /* devicechildren */ + YYSYMBOL_chip = 50, /* chip */ + YYSYMBOL_51_1 = 51, /* @1 */ + YYSYMBOL_device = 52, /* device */ + YYSYMBOL_53_2 = 53, /* @2 */ + YYSYMBOL_54_3 = 54, /* @3 */ + YYSYMBOL_alias = 55, /* alias */ + YYSYMBOL_status = 56, /* status */ + YYSYMBOL_resource = 57, /* resource */ + YYSYMBOL_reference = 58, /* reference */ + YYSYMBOL_registers = 59, /* registers */ + YYSYMBOL_subsystemid = 60, /* subsystemid */ + YYSYMBOL_ioapic_irq = 61, /* ioapic_irq */ + YYSYMBOL_smbios_slot_desc = 62, /* smbios_slot_desc */ + YYSYMBOL_fw_config_table = 63, /* fw_config_table */ + YYSYMBOL_fw_config_table_children = 64, /* fw_config_table_children */ + YYSYMBOL_fw_config_field_children = 65, /* fw_config_field_children */ + YYSYMBOL_fw_config_field = 66, /* fw_config_field */ + YYSYMBOL_67_4 = 67, /* $@4 */ + YYSYMBOL_68_5 = 68, /* $@5 */ + YYSYMBOL_69_6 = 69, /* $@6 */ + YYSYMBOL_fw_config_option = 70, /* fw_config_option */ + YYSYMBOL_fw_config_probe = 71 /* fw_config_probe */ }; typedef enum yysymbol_kind_t yysymbol_kind_t; @@ -577,10 +490,10 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 2 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 97 +#define YYLAST 79 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 45 +#define YYNTOKENS 46 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 26 /* YYNRULES -- Number of rules. */ @@ -588,7 +501,8 @@ union yyalloc /* YYNSTATES -- Number of states. */ #define YYNSTATES 89 -#define YYMAXUTOK 299 +/* YYMAXUTOK -- Last valid token kind. */ +#define YYMAXUTOK 300 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM @@ -631,19 +545,20 @@ static const yytype_int8 yytranslate[] = 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, - 35, 36, 37, 38, 39, 40, 41, 42, 43, 44 + 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, + 45 }; #if YYDEBUG /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_int8 yyrline[] = { - 0, 24, 24, 24, 24, 26, 26, 26, 26, 26, - 28, 28, 28, 28, 28, 28, 28, 28, 28, 30, - 30, 39, 39, 47, 47, 55, 57, 61, 61, 63, - 66, 69, 72, 75, 78, 81, 84, 87, 91, 94, - 94, 97, 97, 100, 100, 106, 106, 112, 112, 118, - 122 + 0, 25, 25, 25, 25, 27, 27, 27, 27, 27, + 29, 29, 29, 29, 29, 29, 29, 29, 29, 31, + 31, 40, 40, 48, 48, 56, 58, 62, 62, 64, + 67, 70, 73, 76, 79, 82, 85, 88, 92, 95, + 95, 98, 98, 101, 101, 107, 107, 113, 113, 119, + 123 }; #endif @@ -665,7 +580,7 @@ static const char *const yytname[] = "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "LPC", "ESPI", - "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", + "GPIO", "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", "FW_CONFIG_PROBE", "$accept", "devtree", "chipchildren", "devicechildren", "chip", "@1", "device", "@2", "@3", "alias", "status", "resource", "reference", "registers", "subsystemid", "ioapic_irq", @@ -690,11 +605,11 @@ static const yytype_int16 yytoknum[] = 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, - 295, 296, 297, 298, 299 + 295, 296, 297, 298, 299, 300 }; #endif -#define YYPACT_NINF (-12) +#define YYPACT_NINF (-15) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) @@ -708,15 +623,15 @@ static const yytype_int16 yytoknum[] = STATE-NUM. */ static const yytype_int8 yypact[] = { - -12, 9, -12, 18, -12, -12, -12, -12, 2, -12, - -12, 25, -12, 16, 14, 10, 30, 31, -12, -12, - -12, -12, -12, 17, -12, 32, 22, 3, 44, -12, - -12, -11, 29, 20, 36, 37, -12, -7, -12, 38, - -12, -12, -12, -12, 39, 29, -12, -12, -6, -12, - 28, -12, -12, -12, -12, -12, -3, -12, 33, -12, - 41, 34, 35, 42, -12, -12, -12, -12, -12, -12, - -12, -12, 1, 45, 48, 40, 27, 49, -12, 43, - 50, 46, 47, -12, -12, 51, -12, -12, -12 + -15, 9, -15, 0, -15, -15, -15, -15, -11, -15, + -15, 2, -15, 45, -8, 13, 6, 19, -15, -15, + -15, -15, -15, 10, -15, 23, 12, 11, 36, -15, + -15, -7, 25, 39, 30, 37, -15, -6, -15, 38, + -15, -15, -15, -15, 40, 25, -15, -15, -1, -15, + 24, -15, -15, -15, -15, -15, -3, -15, 27, -15, + 41, 31, 32, 46, -15, -15, -15, -15, -15, -15, + -15, -15, 1, 47, 48, 35, 33, 49, -15, 42, + 51, 43, 44, -15, -15, 52, -15, -15, -15 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -738,9 +653,9 @@ static const yytype_int8 yydefact[] = /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -12, -12, -12, 13, 12, -12, 58, -12, -12, -12, - 52, -12, -12, 60, -12, -12, -12, -12, -12, 4, - -12, -12, -12, -12, -12, -12 + -15, -15, -15, 15, 17, -15, 57, -15, -15, -15, + 34, -15, -15, 62, -15, -15, -15, -15, -15, -14, + -15, -15, -15, -15, -15, -15 }; /* YYDEFGOTO[NTERM-NUM]. */ @@ -756,56 +671,52 @@ static const yytype_int8 yydefgoto[] = number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int8 yytable[] = { - 3, 15, 16, 38, 3, 15, 16, 49, 54, 2, - 58, 59, 3, 5, 58, 78, 10, 25, 34, 3, - 15, 16, 26, 17, 60, 19, 44, 61, 60, 62, - 18, 61, 39, 62, 37, 7, 39, 39, 41, 42, - 48, 63, 14, 23, 11, 63, 29, 27, 28, 32, - 4, 33, 35, 46, 47, 50, 52, 55, 74, 77, - 79, 82, 73, 75, 76, 80, 83, 85, 88, 81, - 72, 20, 84, 22, 0, 0, 87, 86, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 53 + 3, 15, 16, 10, 3, 15, 16, 38, 49, 2, + 58, 59, 3, 54, 58, 78, 37, 7, 5, 14, + 25, 23, 48, 27, 60, 26, 34, 61, 60, 62, + 19, 61, 11, 62, 41, 42, 28, 39, 39, 29, + 32, 33, 63, 39, 35, 44, 63, 46, 3, 15, + 16, 4, 17, 55, 47, 50, 73, 52, 74, 18, + 75, 76, 79, 77, 81, 80, 83, 82, 85, 88, + 20, 84, 72, 87, 86, 22, 0, 0, 0, 53 }; static const yytype_int8 yycheck[] = { 3, 4, 5, 14, 3, 4, 5, 14, 14, 0, - 13, 14, 3, 1, 13, 14, 14, 7, 15, 3, - 4, 5, 12, 7, 27, 13, 6, 30, 27, 32, - 14, 30, 43, 32, 30, 17, 43, 43, 9, 10, - 36, 44, 17, 29, 42, 44, 29, 17, 17, 17, - 41, 29, 8, 17, 17, 17, 17, 29, 17, 17, - 15, 34, 29, 29, 29, 17, 17, 17, 17, 29, - 57, 13, 29, 13, -1, -1, 29, 31, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 45 + 13, 14, 3, 14, 13, 14, 30, 17, 1, 17, + 7, 29, 36, 17, 27, 12, 15, 30, 27, 32, + 13, 30, 43, 32, 9, 10, 17, 44, 44, 29, + 17, 29, 45, 44, 8, 6, 45, 17, 3, 4, + 5, 42, 7, 29, 17, 17, 29, 17, 17, 14, + 29, 29, 15, 17, 29, 17, 17, 34, 17, 17, + 13, 29, 57, 29, 31, 13, -1, -1, -1, 45 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 46, 0, 3, 41, 49, 62, 17, 63, 50, - 14, 42, 65, 47, 17, 4, 5, 7, 14, 49, - 51, 57, 58, 29, 68, 7, 12, 17, 17, 29, - 67, 64, 17, 29, 15, 8, 66, 64, 14, 43, - 69, 9, 10, 55, 6, 54, 17, 17, 64, 14, - 17, 53, 17, 55, 14, 29, 48, 52, 13, 14, - 27, 30, 32, 44, 49, 51, 56, 58, 59, 60, - 61, 70, 48, 29, 17, 29, 29, 17, 14, 15, + 0, 47, 0, 3, 42, 50, 63, 17, 64, 51, + 14, 43, 66, 48, 17, 4, 5, 7, 14, 50, + 52, 58, 59, 29, 69, 7, 12, 17, 17, 29, + 68, 65, 17, 29, 15, 8, 67, 65, 14, 44, + 70, 9, 10, 56, 6, 55, 17, 17, 65, 14, + 17, 54, 17, 56, 14, 29, 49, 53, 13, 14, + 27, 30, 32, 45, 50, 52, 57, 59, 60, 61, + 62, 71, 49, 29, 17, 29, 29, 17, 14, 15, 17, 29, 34, 17, 29, 17, 31, 29, 17 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_int8 yyr1[] = { - 0, 45, 46, 46, 46, 47, 47, 47, 47, 47, - 48, 48, 48, 48, 48, 48, 48, 48, 48, 50, - 49, 52, 51, 53, 51, 54, 54, 55, 55, 56, - 57, 58, 59, 59, 60, 61, 61, 61, 62, 63, - 63, 64, 64, 66, 65, 67, 65, 68, 65, 69, - 70 + 0, 46, 47, 47, 47, 48, 48, 48, 48, 48, + 49, 49, 49, 49, 49, 49, 49, 49, 49, 51, + 50, 53, 52, 54, 52, 55, 55, 56, 56, 57, + 58, 59, 60, 60, 61, 62, 62, 62, 63, 64, + 64, 65, 65, 67, 66, 68, 66, 69, 66, 70, + 71 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ @@ -1028,7 +939,7 @@ yydestruct (const char *yymsg, } -/* The lookahead symbol. */ +/* Lookahead token kind. */ int yychar; /* The semantic value of the lookahead symbol. */ @@ -1046,34 +957,30 @@ int yynerrs; int yyparse (void) { - yy_state_fast_t yystate; + yy_state_fast_t yystate = 0; /* Number of tokens to shift before error messages enabled. */ - int yyerrstatus; + int yyerrstatus = 0; - /* The stacks and their tools: - 'yyss': related to states. - 'yyvs': related to semantic values. - - Refer to the stacks through separate pointers, to allow yyoverflow + /* Refer to the stacks through separate pointers, to allow yyoverflow to reallocate them elsewhere. */ /* Their size. */ - YYPTRDIFF_T yystacksize; + YYPTRDIFF_T yystacksize = YYINITDEPTH; - /* The state stack. */ + /* The state stack: array, bottom, top. */ yy_state_t yyssa[YYINITDEPTH]; - yy_state_t *yyss; - yy_state_t *yyssp; + yy_state_t *yyss = yyssa; + yy_state_t *yyssp = yyss; - /* The semantic value stack. */ + /* The semantic value stack: array, bottom, top. */ YYSTYPE yyvsa[YYINITDEPTH]; - YYSTYPE *yyvs; - YYSTYPE *yyvsp; + YYSTYPE *yyvs = yyvsa; + YYSTYPE *yyvsp = yyvs; int yyn; /* The return value of yyparse. */ int yyresult; - /* Lookahead token as an internal (translated) token number. */ + /* Lookahead symbol kind. */ yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; /* The variables used to return semantic value and location from the action routines. */ @@ -1087,15 +994,6 @@ yyparse (void) Keep to zero when no symbol should be popped. */ int yylen = 0; - yynerrs = 0; - yystate = 0; - yyerrstatus = 0; - - yystacksize = YYINITDEPTH; - yyssp = yyss = yyssa; - yyvsp = yyvs = yyvsa; - - YYDPRINTF ((stderr, "Starting parse\n")); yychar = YYEMPTY; /* Cause a token to be read. */ @@ -1296,11 +1194,11 @@ yyreduce: YY_REDUCE_PRINT (yyn); switch (yyn) { - case 2: + case 2: /* devtree: %empty */ { cur_parent = root_parent; } break; - case 19: + case 19: /* @1: %empty */ { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); chip_enqueue_tail(cur_chip_instance); @@ -1308,125 +1206,125 @@ yyreduce: } break; - case 20: + case 20: /* chip: CHIP STRING @1 chipchildren END */ { cur_chip_instance = chip_dequeue_tail(); } break; - case 21: + case 21: /* @2: %empty */ { (yyval.dev) = new_device_raw(cur_parent, cur_chip_instance, (yyvsp[-3].number), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 22: + case 22: /* device: DEVICE BUS NUMBER alias status @2 devicechildren END */ { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 23: + case 23: /* @3: %empty */ { (yyval.dev) = new_device_reference(cur_parent, cur_chip_instance, (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 24: + case 24: /* device: DEVICE REFERENCE STRING status @3 devicechildren END */ { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 25: + case 25: /* alias: %empty */ { (yyval.string) = NULL; } break; - case 26: + case 26: /* alias: ALIAS STRING */ { (yyval.string) = (yyvsp[0].string); } break; - case 29: + case 29: /* resource: RESOURCE NUMBER EQUALS NUMBER */ { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 30: + case 30: /* reference: REFERENCE STRING ASSOCIATION STRING */ { add_reference(cur_chip_instance, (yyvsp[0].string), (yyvsp[-2].string)); } break; - case 31: + case 31: /* registers: REGISTER STRING EQUALS STRING */ { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 32: + case 32: /* subsystemid: SUBSYSTEMID NUMBER NUMBER */ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 33: + case 33: /* subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT */ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 34: + case 34: /* ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER */ { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; - case 35: + case 35: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } break; - case 36: + case 36: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } break; - case 37: + case 37: /* smbios_slot_desc: SLOT_DESC STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; - case 38: + case 38: /* fw_config_table: FW_CONFIG_TABLE fw_config_table_children END */ { } break; - case 43: + case 43: /* $@4: %empty */ { cur_field = new_fw_config_field((yyvsp[-2].string), strtoul((yyvsp[-1].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); } break; - case 44: + case 44: /* fw_config_field: FW_CONFIG_FIELD STRING NUMBER NUMBER $@4 fw_config_field_children END */ { } break; - case 45: + case 45: /* $@5: %empty */ { cur_field = new_fw_config_field((yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); } break; - case 46: + case 46: /* fw_config_field: FW_CONFIG_FIELD STRING NUMBER $@5 fw_config_field_children END */ { } break; - case 47: + case 47: /* $@6: %empty */ { cur_field = get_fw_config_field((yyvsp[0].string)); } break; - case 48: + case 48: /* fw_config_field: FW_CONFIG_FIELD STRING $@6 fw_config_field_children END */ { } break; - case 49: - { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0)); } + case 49: /* fw_config_option: FW_CONFIG_OPTION STRING NUMBER */ + { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoull((yyvsp[0].string), NULL, 0)); } break; - case 50: + case 50: /* fw_config_probe: FW_CONFIG_PROBE STRING STRING */ { add_fw_config_probe(cur_parent, (yyvsp[-1].string), (yyvsp[0].string)); } break; @@ -1590,13 +1488,13 @@ yyabortlab: yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; - /* Fall through. */ + goto yyreturn; #endif -/*-----------------------------------------------------. -| yyreturn -- parsing is finished, return the result. | -`-----------------------------------------------------*/ +/*-------------------------------------------------------. +| yyreturn -- parsing is finished, clean up and return. | +`-------------------------------------------------------*/ yyreturn: if (yychar != YYEMPTY) { diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index b05831fc33e..6983c3bb76c 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.6.3. */ +/* A Bison parser, made by GNU Bison 3.7.2. */ /* Bison interface for Yacc-like parsers in C @@ -35,8 +35,8 @@ especially those whose name start with YY_ or yy_. They are private implementation details that can be changed or removed. */ -#ifndef YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_C0D3_SRC_COREBOOT_GIT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_C0D3_SRC_COREBOOT_GIT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -92,10 +92,11 @@ extern int yydebug; MMIO = 293, /* MMIO */ LPC = 294, /* LPC */ ESPI = 295, /* ESPI */ - FW_CONFIG_TABLE = 296, /* FW_CONFIG_TABLE */ - FW_CONFIG_FIELD = 297, /* FW_CONFIG_FIELD */ - FW_CONFIG_OPTION = 298, /* FW_CONFIG_OPTION */ - FW_CONFIG_PROBE = 299 /* FW_CONFIG_PROBE */ + GPIO = 296, /* GPIO */ + FW_CONFIG_TABLE = 297, /* FW_CONFIG_TABLE */ + FW_CONFIG_FIELD = 298, /* FW_CONFIG_FIELD */ + FW_CONFIG_OPTION = 299, /* FW_CONFIG_OPTION */ + FW_CONFIG_PROBE = 300 /* FW_CONFIG_PROBE */ }; typedef enum yytokentype yytoken_kind_t; #endif @@ -108,7 +109,7 @@ union YYSTYPE struct device *dev; struct chip_instance *chip_instance; char *string; - int number; + uint64_t number; }; @@ -122,4 +123,4 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_C0D3_SRC_COREBOOT_GIT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 84dfe248fd1..8e0379183c3 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -20,7 +20,7 @@ static struct fw_config_field *cur_field; uint64_t number; } -%token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE +%token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI GPIO FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE %% devtree: { cur_parent = root_parent; } | devtree chip | devtree fw_config_table; diff --git a/util/scripts/cross-repo-cherrypick b/util/scripts/cross-repo-cherrypick index 35e4b335025..c640e33f654 100755 --- a/util/scripts/cross-repo-cherrypick +++ b/util/scripts/cross-repo-cherrypick @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # cross-repo-cherrypick - rebase helper script # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/scripts/decode_spd.sh b/util/scripts/decode_spd.sh index e515154ee7c..252a4b7d324 100755 --- a/util/scripts/decode_spd.sh +++ b/util/scripts/decode_spd.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # # # SPDX-License-Identifier: GPL-2.0-only diff --git a/util/scripts/find-unused-kconfig-symbols.sh b/util/scripts/find-unused-kconfig-symbols.sh index 3b84d25f57e..48a89b96dfe 100755 --- a/util/scripts/find-unused-kconfig-symbols.sh +++ b/util/scripts/find-unused-kconfig-symbols.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # Permission to use, copy, modify, and/or distribute this software for # any purpose with or without fee is hereby granted, provided that the # above copyright notice and this permission notice appear in all copies. diff --git a/util/scripts/no-fsf-addresses.sh b/util/scripts/no-fsf-addresses.sh index ef54fc1be84..aceeeb831fa 100755 --- a/util/scripts/no-fsf-addresses.sh +++ b/util/scripts/no-fsf-addresses.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/usr/bin/env sh # SPDX-License-Identifier: ISC filelist=$(git ls-files $* | \ diff --git a/util/spd_tools/description.md b/util/spd_tools/description.md new file mode 100644 index 00000000000..aa127816c53 --- /dev/null +++ b/util/spd_tools/description.md @@ -0,0 +1,11 @@ +Tools for generating SPD files for DDR4 memory used in platforms with +memory down configuration. + + + +* _gen_spd.go_ - Generates de-duplicated SPD files using a + global memory part list provided by the + mainboard in JSON format. `Go` + +* _gen_part_id.go_ - Allocates DRAM strap IDs for different + DDR4 memory parts used by the board. `Go` diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index f8c425d1046..6e604a072ec 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -8,6 +8,60 @@ #define ISA_PNP_ADDR 0x279 static const struct superio_registers reg_table[] = { + {0x5570, "IT5570E", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2d,EOT}, + {0x55,0x70,NANA,0x01,RSVD,0x00,0x00,RSVD,RSVD,RSVD,RSVD,RSVD,0x00,EOT}}, + {0x01, "Serial Port 1 (UART1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xf8,0x00,0x00,0x03,0x02,0x00,EOT}}, + {0x02, "Serial Port 2 (UART2)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xf8,0x00,0x00,0x03,0x02,0x00,EOT}}, + {0x04, "System Wake-Up Control (SWUC)", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "KBC Mouse", + {0x30,0x70,0x71,EOT}, + {0x00,0x0c,0x01,EOT}}, + {0x06, "KBC Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0x0a, "Consumer IR", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x03,0x10,0x00,0x02,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x70,0x71,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, + 0xf9,0xfa,0xfb,0xfc,EOT}, + {0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01,EOT}}, + {0x10, "RTC-like Timer (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x70,0x71,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, + {0x00,0x00,0x70,0x02,0x72,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x01,0x00, + 0x49,0x4a,0x00,0x00,0x00,EOT}}, + {0x11, "Power Management Interface Channel 1 (PMC1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Management Interface Channel 2 (PMC2)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x13, "Serial Peripheral Interface (SSPI)", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x03,0x00,0x00,0x02,EOT}}, + {0x14, "Platform Environment Control Interface (PECI)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x17, "Power Management Interface Channel 3 (PMC3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, + {0x18, "Power Management Interface Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x74,0x00,0x78,0x01,0x01,EOT}}, + {0x19, "Power Management Interface Channel 5 (PMC5)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x7a,0x00,0x7c,0x01,0x01,EOT}}, + {EOT}}}, {0x8228, "IT8228E", { {EOT}}}, {0x8500, "IT8500B/E", { @@ -1244,6 +1298,35 @@ static const struct superio_registers ec_table[] = { 0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,EOT}}, {EOT}}}, + {0x8720, "IT8720F", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x40,0x41, + 0x42,0x43,0x44,0x45,0x50,0x51,0x52,0x53,0x54,0x55, + 0x56,0x57,0x58,0x59,0x5b,0x5c,0x5d,0x5e,0x5f,0x60, + 0x61,0x62,0x63,0x64,0x65,0x68,0x69,0x6a,0x6b,0x6c, + 0x6d,0x70,0x71,0x72,0x73,0x74,0x75,0x80,0x81,0x82, + 0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,0x90,0x91, + 0x92,0x94,0x95,0x96,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80, + 0x58,0x09,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x07, + 0x50,MISC,MISC,MISC,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,0x00,0x00,0x7f,0x7f,0x7f,0x50, + 0x00,0x00,0x90,0x00,0x12,0x60,0x00,0x00,0x00,0x7f, + 0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x00,0x00, + 0x7f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA, + 0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0xff,0x00, + 0x00,0xff,0x00,0x00,EOT}}, + {EOT}}}, {0x8728, "IT8728F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index d2b72f26344..ffd12be1654 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -538,13 +538,13 @@ static const struct superio_registers reg_table[] = { {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, {0x07, "GPIO 6, GPIO 7, GPIO 8", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, - {0x00,0x7f,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x7f,NANA,0x00,NANA,0xff,NANA,0x00,NANA,0x00,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x08, "WDT1, WDT_MEM, GPIO 0, GPIO 1", {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT}, - {0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0x00,0x00,0xff,NANA,0x00,NANA,0x00,0xff,NANA,0x00,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xfe,EOT}, - {0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}}, + {0x00,0xff,NANA,0x00,NANA,0x7f,NANA,0x00,NANA,NANA,0x00,0x00,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,NANA,0x00,EOT}}, {0x0a, "ACPI", {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfc,0xfe,EOT}, {0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x00,0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, diff --git a/util/supermicro/description.md b/util/supermicro/description.md new file mode 100644 index 00000000000..858401688c6 --- /dev/null +++ b/util/supermicro/description.md @@ -0,0 +1,3 @@ +Tools for supermicro platforms + +* _smcbiosinfo_ - Generates SMC biosinfo for BMC BIOS updates `C` diff --git a/util/supermicro/smcbiosinfo/description.md b/util/supermicro/smcbiosinfo/description.md deleted file mode 100644 index 21170eb6f07..00000000000 --- a/util/supermicro/smcbiosinfo/description.md +++ /dev/null @@ -1 +0,0 @@ -Generates SMC biosinfo for BMC BIOS updates `C` diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index d09419682ac..c530fa81205 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -51,12 +51,15 @@ junit.xml: echo TOOLLIST= \ +amdfwtool \ cbmem \ ectool \ futility \ +intelmetool \ inteltool \ intelvbttool \ nvramtool \ +post \ superiotool TEST_PAYLOADLIST_INTERNAL= \ @@ -89,8 +92,10 @@ endif unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/nvramcui BLD=nvramcui MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml unset COREBOOT_BUILD_DIR;$(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=payloads/coreinfo BLD=coreinfo MFLAGS= MAKEFLAGS= MAKETARGET=defaultbuild junit.xml (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) - $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra124/lp0 BLD=tegra124_lp0 MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml - $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra210/lp0 BLD=tegra120_lp0 MFLAGS= MAKEFLAGS= MAKETARGET=all junit.xml +# These targets don't use the standard build system, so we need to provide an xcompile to them. + $(MAKE) xcompile=$(COREBOOT_BUILD_DIR)/xcompile $(COREBOOT_BUILD_DIR)/xcompile + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra124/lp0 BLD=tegra124_lp0 MFLAGS= MAKEFLAGS=xcompile=$(COREBOOT_BUILD_DIR)/xcompile MAKETARGET=all junit.xml + $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra210/lp0 BLD=tegra120_lp0 MFLAGS= MAKEFLAGS=xcompile=$(COREBOOT_BUILD_DIR)/xcompile MAKETARGET=all junit.xml $(MAKE) unit-tests JUNIT_OUTPUT=y test-basic: test-lint test-tools test-abuild test-payloads test-cleanup diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index c2374230d60..9fdda034066 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -51,7 +51,7 @@ program_exists() { if [ "$("${XGCCPATH}/iasl" 2>/dev/null | grep -c ACPI)" -gt 0 ]; then - IASL=${XGCCPATH}iasl + IASL=${XGCCPATH}/iasl elif [ "$(iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then IASL=iasl fi