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  1. +1 −0 .gitignore
  2. +39 −1 CHANGELOG.md
  3. +18 −21 Makefile
  4. +200 −15 README.md
  5. +0 −79 libpayloadbin/.config
  6. +0 −43 libpayloadbin/build/libpayload-config.h
  7. +158 −29 sortbootorder.c
  8. 0 spansion.c
  9. +3 −1 spi.h
  10. +2 −0 spi_flash.c
  11. +18 −0 spi_flash.h
  12. +1 −1 version.h
  13. +113 −2 winbond.c
1 change: 1 addition & 0 deletions .gitignore
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@@ -1,5 +1,6 @@
*.o
*.elf
build

cscope.*
tags
40 changes: 39 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -8,6 +8,13 @@ Releases 4.5.x are based on mainline support submitted in

## [Unreleased]

## [v4.5.6] - 2017-06-29
### Added
- Add option to enable/disable BIOS WP jumper operation

### Changed
- Use the same version for legacy and mainline builds

## [v4.5.5] - 2017-05-30
### Added
- Add option in setup for setting `mPCIe1 SATA` priority (ASM106X cards)
Expand All @@ -20,6 +27,32 @@ Releases 4.5.x are based on mainline support submitted in
### Fixed
- Change `ehci enable` letter from `e` to `h` (conflict with `ipxe` priority)

## [v4.0.6] - 2017-05-30
### Added
- Add option in setup for setting `mPCIe1 SATA` priority (ASM106X cards)

### Changed
- Letters reserved for device sorting: from `a-m` to `a-j`

### Fixed
- Change `ehci enable` letter from `e` to `h` (conflict with `ipxe` priority)

## [v4.0.5.1] - 2017-03-31
### Changed
- changed the name to `PC Engines apu setup` in welcome string
- changed `Serial console redirection` to `Legacy console redirection`

## [v4.0.5] - 2017-03-30
### Added
- EHCI0 controller disable/enable option

## [v4.0.4] - 2017-02-28
### Added
- serial console redirection option (`SgaBIOS` enable) - by default enabled

### Fixed
- fixed writing bootorder files with sizes bigger than 255 bytes

## [v4.5.4] - 2017-02-23
### Changed
- adds new option tag when there isn't one in bootorder file
Expand Down Expand Up @@ -69,10 +102,15 @@ initial commit based on [coreboot_140908](http://pcengines.ch/tmp/coreboot_14090
### Fixed
- used proper way to access extended SPI registers

[Unreleased]: https://github.com/pcengines/sortbootorder/compare/v4.0.5...coreboot-4.0.x
[Unreleased]: https://github.com/pcengines/sortbootorder/compare/v4.5.6...master
[v4.5.6]: https://github.com/pcengines/sortbootorder/compare/v4.5.5...v4.5.6
[v4.5.5]: https://github.com/pcengines/sortbootorder/compare/v4.5.4...v4.5.5
[v4.5.4]: https://github.com/pcengines/sortbootorder/compare/v4.5.3...v4.5.4
[v4.5.3]: https://github.com/pcengines/sortbootorder/compare/v4.5.2...v4.5.3
[v4.0.6]: https://github.com/pcengines/sortbootorder/compare/v4.0.5.1...v4.0.6
[v4.0.5.1]: https://github.com/pcengines/sortbootorder/compare/v4.0.5...v4.0.5.1
[v4.0.5]: https://github.com/pcengines/sortbootorder/compare/v4.0.4...v4.0.5
[v4.0.4]: https://github.com/pcengines/sortbootorder/compare/v4.0.3...v4.0.4
[v4.0.3]: https://github.com/pcengines/sortbootorder/compare/v4.0.2...v4.0.3
[v4.0.2]: https://github.com/pcengines/sortbootorder/compare/v4.0.1...v4.0.2
[v4.5.2]: https://github.com/pcengines/sortbootorder/compare/v4.0.1...v4.5.2
Expand Down
39 changes: 18 additions & 21 deletions Makefile
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Expand Up @@ -26,30 +26,31 @@
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
COREBOOT_REL ?= mainline
COREBOOT_ROOT ?= ../../../..

$(if $(wildcard .xcompile),,$(eval $(shell ../../../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile)))
.xcompile: ../../../../util/xcompile/xcompile

CONFIG_COMPILER_GCC := y
ARCH-y := x86_32

include .xcompile
include $(COREBOOT_ROOT)/.xcompile

src := $(CURDIR)
srctree := $(src)
sortbootorder_obj := $(src)/build
build_dir := $(src)/build

LIBCONFIG_PATH := $(realpath ../../../libpayload)
LIBPAYLOAD_DIR := $(sortbootorder_obj)/libpayload
LIBCONFIG_PATH := $(realpath $(COREBOOT_ROOT)/payloads/libpayload)
LIBPAYLOAD_DIR := $(build_dir)/libpayload
HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/lib/libpayload.a)
LIB_CONFIG ?= configs/defconfig-tinycurses

# CFLAGS := -Wall -Werror -Os
CFLAGS := -Wall -g -Os -fno-builtin
CFLAGS := -Wall -Werror -Os -fno-builtin
ifeq ($(COREBOOT_REL),legacy)
CFLAGS += -DCOREBOOT_LEGACY
endif

TARGET := sortbootorder
OBJS := $(patsubst %.c,%.o,$(wildcard *.c))

ARCH-y := x86_32
ARCH-$(CONFIG_LP_ARCH_ARMV) := arm
ARCH-$(CONFIG_LP_ARCH_POWERPC) := powerpc
ARCH-$(CONFIG_LP_ARCH_X86) := x86_32

CC := $(CC_$(ARCH-y))
AS := $(AS_$(ARCH-y))
Expand All @@ -60,17 +61,14 @@ LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas

# Make is silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)
Q := @
Q := @
endif

all: Makefile $(TARGET).elf

$(TARGET).elf: $(OBJS) libpayload
$(Q)printf " LPCC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LPCC) -o $@ $(OBJS)
$(Q)$(OBJCOPY) --only-keep-debug $@ sortbootorder.debug
$(Q)$(OBJCOPY) --strip-debug $@
$(Q)$(OBJCOPY) --add-gnu-debuglink=sortbootorder.debug $@
$(Q)$(LPCC) $(CFLAGS) -o $@ $(OBJS)

%.o: %.c libpayload
$(Q)printf " LPCC $(subst $(shell pwd)/,,$(@))\n"
Expand All @@ -88,15 +86,14 @@ libpayload:
$(Q)printf "Building libpayload @ $(LIBCONFIG_PATH).\n"
$(Q)make -C $(LIBCONFIG_PATH) distclean
$(Q)make -C $(LIBCONFIG_PATH) defconfig KBUILD_DEFCONFIG=$(LIB_CONFIG)
$(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(sortbootorder_obj) install
$(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(build_dir) install
endif

clean:
$(Q)rm -f $(TARGET).elf $(TARGET).debug *.o
$(Q)rm .xcompile

distclean: clean
$(Q)rm -rf $(sortbootorder_obj)
$(Q)rm -rf $(build_dir)


.PHONY: all clean distclean do-it-all depend with-depends without-depends debian postinst
215 changes: 200 additions & 15 deletions README.md
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@@ -1,25 +1,210 @@
Sortbootorder
-------------

This repository contain source code of `sortbootorder` payload that sorts and
save boot order in flash.
This repository contains source code of `sortbootorder` payload that sorts and
saves boot order in flash.

Below instructions assume you use APU2 image builder according to instructions
provided [here](https://github.com/pcengines/apu2-documentation).
## Contents

<!-- TOC -->

- [Contents](#contents)
- [Theory of operation](#theory-of-operation)
- [Example menu view](#example-menu-view)
- [Settings description](#settings-description)
- [bootorder file](#bootorder-file)
- [bootorder_map file](#bootorder_map-file)
- [Default settings](#default-settings)
- [BIOS WP option](#bios-wp-option)
- [Building](#building)
- [Manual build](#manual-build)
- [Adding sortbootorder to coreboot.rom file](#adding-sortbootorder-to-corebootrom-file)
- [Recent automated building process](#recent-automated-building-process)

<!-- /TOC -->

## Theory of operation

### Example menu view

> Exact list may be different, depending on BIOS release version.

For coreboot mainline (4.5.x) version:

```
a USB 1 / USB 2 SS and HS
b SDCARD
c mSATA
d SATA
e mPCIe1 SATA1 and SATA2
f iPXE (disabled)
r Restore boot order defaults
n Network/PXE boot - Currently Disabled
u USB boot - Currently Enabled
l Legacy console redirection - Currently Disabled
w Enable BIOS write protect - Currently Disabled
x Exit setup without save
s Save configuration and exit
```

For coreboot legacy (4.0.x) version:

```
a USB 1 / USB 2 SS and HS
b SDCARD
c mSATA
d SATA
e mPCIe1 SATA1 and SATA2
f iPXE (disabled)
r Restore boot order defaults
n Network/PXE boot - Currently Disabled
u USB boot - Currently Enabled
l Legacy console redirection - Currently Enabled
t Serial console - Currently Enabled
o UART C - Currently Enabled
p UART D - Currently Enabled
h EHCI0 controller - Currently Disabled
w Enable BIOS write protect - Currently Disabled
x Exit setup without save
s Save configuration and exit
```

First part of the list is used to set boot device priorities. Second part of
the list is used to enable/disable specific settings. Those information are
stored in `bootorder` file, which is written back to flash after hitting `s`
key.

### Settings description

* `r Restore boot order defaults` - restores boot order to default settings
* `n Network/PXE boot` - enables/disables the network boot (iPXE)
* `u USB boot` - enables/disables boot from USB drives
* `l Legacy console redirection` - enables/disables serial redirection to the
sgabios (serial text console emulation).
* `t Serial console` - enables/disables output to the serial console
Useful for legacy software, which is not using native serial port output, but
uses standard PC text console instead (eg. FreeDOS).
* `o UART C` - enables/disables UART C on GPIO header. Disabled UART means
enabled GPIO.
* `p UART D` - enables/disables UART D on GPIO header. Disabled UART means
enabled GPIO.
* `h EHCI0 controller` - enables/disables EHCI0 controller (used in apu3)
* `w Enable BIOS write protect` - enables/disables BIOS WP functionality. For
details, see descritption in [BIOS WP option](#bios-wp-option).
* `x Exit setup without save` - exits setup menu without saving the settings
* `s Save configuration and exit` - exits setup menu saving the settings

### bootorder file

Sortbootorder manages `bootorder` file which is initially shipped from
[coreboot repository](https://github.com/pcengines/coreboot/blob/coreboot-4.5.x/src/mainboard/pcengines/apu2/bootorder)
This is binary file that has to be 4096 bytes long in order to entirely fill
one FLASH sector.

Relevant content of this file may look like this:

```
/pci@i0cf8/usb@10/usb-*@1
/pci@i0cf8/usb@10/usb-*@2
/pci@i0cf8/usb@10/usb-*@3
/pci@i0cf8/usb@10/usb-*@4
/pci@i0cf8/*@14,7
/pci@i0cf8/*@11/drive@0/disk@0
/pci@i0cf8/*@11/drive@1/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0
/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0
/rom@genroms/pxe.rom
pxen0
scon1
usben1
```

Rest of this file is filled with characters to meet that 4096 bytes
requirement.

When device is attached and detected by `SeaBIOS`, then `SeaBIOS` begins to check
if such device node is written into `bootorder` file. If it is, it gains priority
according to it's place on the list.
You can refer to
[SeaBIOS](https://github.com/pcengines/seabios/blob/coreboot-4.0.x/docs/Runtime_config.md#configuring-boot-order)
documentation for more insight.

### bootorder_map file

[bootorder_map](https://github.com/pcengines/coreboot/blob/coreboot-4.5.x/src/mainboard/pcengines/apu2/bootorder_map)
file is used to match device letter and description with corresponding node from
`bootorder` file.

### Default settings

* Bootorder list default settings:

```
a USB 1 / USB 2 SS and HS
b SDCARD
c mSATA
d SATA
e mPCIe1 SATA1 and SATA2
f iPXE
```

* Rest of default settings:

```
Network/PXE boot - Disabled
Serial console redirection - Disabled
USB boot - Enabled
```

Default bootorder list settings are taken from
[bootorder_def file](https://github.com/pcengines/coreboot/blob/coreboot-4.5.x/src/mainboard/pcengines/apu2/bootorder_def).
They can be restored by hitting `r` key. It only restores to default boot
list order, not other specific settings such as `USB enable` or `serial console
enable`.

### BIOS WP option

`Enable BIOS write protect` option (`w`) enables or disables flash write
protection feature. When enabled, then BIOS WP jumper (1-2 pins of J2) controls
the possibility of writing to flash. When BIOS WP is shorted and option is
enabled no writes to flash is possible, including disabling the write protect
option itself and updating the BIOS is also not possible (using e.g. `flashrom`
tool).

## Building

### Manual build

> coreboot is in `./coreboot-${BR_NAME}` directory

```sh
git clone https://github.com/pcengines/sortbootorder.git sortbootorder
cd sortbootorder
# for mainline coreboot (4.5.x)
COREBOOT_ROOT=../coreboot-${BR_NAME} make distclean
COREBOOT_ROOT=../coreboot-${BR_NAME} make
# for legacy coreboot (4.0.x)
COREBOOT_ROOT=../coreboot-${BR_NAME} make distclean
COREBOOT_ROOT=../coreboot-${BR_NAME} COREBOOT_REL=legacy make
```
cd coreboot-apu2b-20160304/
git clone https://github.com/pcengines/sortbootorder.git payloads/pcengines/sortbootorder
cd payloads/libpayload
make defconfig
cp /xgcc/.xcompile-libpayload .xcompile
make
make install
cd ../pcengines/sortbootorder
make

### Adding sortbootorder to coreboot.rom file

```sh
cd && cd coreboot-${BR_NAME}
./build/cbfstool ./build/coreboot.rom remove -n img/setup
./build/cbfstool ./build/coreboot.rom add-payload -f payloads/pcengines/sortbootorder/sortbootorder.elf -n img/setup -t payload
```

For adding `sortbootorder` to `coreboot.rom` image please follow
[README.md](https://github.com/pcengines/apu2-documentation)
Above commands first remove already existing `img/setup` from CBFS and then add
`sortbootorder.elf` as payload under the name `img/setup` to `coreboot.rom`.

### Recent automated building process

Please follow
[release process](https://github.com/pcengines/apu2-documentation/blob/master/docs/release_process.md)
document to build complete `coreboot` binary, already including `SeaBIOS` and
other payloads (such us `sortbootorder`).