Showing with 45 additions and 19 deletions.
  1. +4 −0 CHANGELOG.md
  2. +14 −3 README.md
  3. +27 −16 sortbootorder.c
4 changes: 4 additions & 0 deletions CHANGELOG.md
View file
Expand Up @@ -7,6 +7,10 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
[this gerrit ref](https://review.coreboot.org/#/c/14138/).

## [Unreleased]
## [v4.6.13] - 2019-02-26
### Added
- CPU boost runtime configuration

## [v4.6.12] - 2018-12-03
### Fixed
- BIOS WP feature for different SPI parts
Expand Down
17 changes: 14 additions & 3 deletions README.md
View file
Expand Up @@ -8,6 +8,7 @@ saves boot order in flash.

<!-- TOC -->

- [Sortbootorder](#sortbootorder)
- [Contents](#contents)
- [Theory of operation](#theory-of-operation)
- [Example menu view](#example-menu-view)
Expand Down Expand Up @@ -49,6 +50,7 @@ saves boot order in flash.
p UART D - Currently Enabled
m Force mPCIe2 slot CLK (GPP3 PCIe) - Currently Disabled
h EHCI0 controller - Currently Disabled
l Core Performance Boost - Currently Enabled
w Enable BIOS write protect - Currently Disabled
x Exit setup without save
s Save configuration and exit
Expand Down Expand Up @@ -81,6 +83,7 @@ key.
It is advised to set to `Disable` if no extension card is attached to mPCIe2
slot.
* `h EHCI0 controller` - enables/disables EHCI0 controller (used in apu3)
* `l Core Performance Boost` - enables/disables CPU boost.
* `w Enable BIOS write protect` - enables/disables BIOS WP functionality. For
details, see descritption in [BIOS WP option](#bios-wp-option).
* `x Exit setup without save` - exits setup menu without saving the settings
Expand Down Expand Up @@ -109,6 +112,7 @@ Relevant content of this file may look like this:
pxen0
scon1
usben1
...
```

Rest of this file is filled with characters to meet that 4096 bytes
Expand Down Expand Up @@ -144,12 +148,19 @@ file is used to match device letter and description with corresponding node from

```
Network/PXE boot - Disabled
Serial console redirection - Disabled
Serial console - Enabled
USB boot - Enabled
Force mPCIe2 slot CLK (GPP3 PCIe) - Disabled
UART C - Enabled
UART D - Enabled
EHCI0 controller - Disabled
Core Performance Boost - Enabled
Redirect console output to COM2 - Disabled
BIOS write protect - Disabled
```

Default bootorder list settings are taken from
[bootorder_def file](https://github.com/pcengines/coreboot/blob/coreboot-4.5.x/src/mainboard/pcengines/apu2/bootorder_def).
[bootorder_def file](https://github.com/pcengines/coreboot/blob/develop/src/mainboard/pcengines/apu2/bootorder_def).
They can be restored by hitting `r` key. It only restores to default boot
list order, not other specific settings such as `USB enable` or `serial console
enable`.
Expand All @@ -159,7 +170,7 @@ enable`.
`Enable BIOS write protect` option (`w`) enables or disables flash write
protection feature. When enabled, then BIOS WP jumper (1-2 pins of J2) controls
the possibility of writing to flash. When BIOS WP is shorted and option is
enabled no writes to flash is possible, including disabling the write protect
enabled no writes to flash are possible, including disabling the write protect
option itself and updating the BIOS is also not possible (using e.g. `flashrom`
tool).

Expand Down
43 changes: 27 additions & 16 deletions sortbootorder.c
View file
Expand Up @@ -69,14 +69,13 @@ static u8 com2_available;

#ifndef TARGET_APU1
static u8 ehci0_toggle;
static u8 mpcie2_clk_toggle;
static u8 boost_toggle;
#endif

static u8 uartc_toggle;
static u8 uartd_toggle;

#ifndef TARGET_APU1
static u8 mpcie2_clk_toggle;
#endif

static char bootlist_def[MAX_DEVICES][MAX_LENGTH];
static char bootlist_map[MAX_DEVICES][MAX_LENGTH];
Expand Down Expand Up @@ -179,6 +178,14 @@ int main(void) {
token = strstr(bootorder_data, "ehcien");
token += strlen("ehcien");
ehci0_toggle = token ? strtoul(token, NULL, 10) : 1;

token = strstr(bootorder_data, "mpcie2_clk");
token += strlen("mpcie2_clk");
mpcie2_clk_toggle = token ? strtoul(token, NULL, 10) : 0;

token = strstr(bootorder_data, "boosten");
token += strlen("boosten");
boost_toggle = token ? strtoul(token, NULL, 10) : 0;
#endif

token = strstr(bootorder_data, "uartc");
Expand All @@ -189,12 +196,6 @@ int main(void) {
token += strlen("uartd");
uartd_toggle = token ? strtoul(token, NULL, 10) : 0;

#ifndef TARGET_APU1
token = strstr(bootorder_data, "mpcie2_clk");
token += strlen("mpcie2_clk");
mpcie2_clk_toggle = token ? strtoul(token, NULL, 10) : 0;
#endif

spi_wp_toggle = is_flash_locked();

show_boot_device_list( bootlist, max_lines, bootlist_def_ln );
Expand Down Expand Up @@ -250,6 +251,10 @@ int main(void) {
case 'H':
ehci0_toggle ^= 0x1;
break;
case 'l':
case 'L':
boost_toggle ^= 0x1;
break;
case 'Z':
handle_reg_sec_menu();
break;
Expand All @@ -266,6 +271,7 @@ int main(void) {
#ifndef TARGET_APU1
update_tag_value(bootlist, &max_lines, "mpcie2_clk", mpcie2_clk_toggle + '0');
update_tag_value(bootlist, &max_lines, "ehcien", ehci0_toggle + '0');
update_tag_value(bootlist, &max_lines, "boosten", boost_toggle + '0');
#endif
save_flash(flash_address, bootlist, max_lines, spi_wp_toggle);
// fall through to exit ...
Expand Down Expand Up @@ -367,6 +373,7 @@ static void show_boot_device_list( char buffer[MAX_DEVICES][MAX_LENGTH], u8 line
#ifndef TARGET_APU1
printf(" m Force mPCIe2 slot CLK (GPP3 PCIe) - Currently %s\n", (mpcie2_clk_toggle) ? "Enabled" : "Disabled");
printf(" h EHCI0 controller - Currently %s\n", (ehci0_toggle) ? "Enabled" : "Disabled");
printf(" l Core Performance Boost - Currently %s\n", (boost_toggle) ? "Enabled" : "Disabled");
#endif
printf(" w Enable BIOS write protect - Currently %s\n", (spi_wp_toggle) ? "Enabled" : "Disabled");
printf(" x Exit setup without save\n");
Expand Down Expand Up @@ -511,13 +518,6 @@ static void refresh_tag_values(u8 max_lines)
token += strlen("com2en");
com2_toggle = strtoul(token, NULL, 10);
}
#ifndef TARGET_APU1
token = strstr(&(bootlist_def[i][0]), "ehcien");
if(token) {
token += strlen("ehcien");
ehci0_toggle = strtoul(token, NULL, 10);
}
#endif

token = strstr(&(bootlist_def[i][0]), "uartc");
if(token) {
Expand All @@ -530,12 +530,23 @@ static void refresh_tag_values(u8 max_lines)
token += strlen("uartd");
uartd_toggle = strtoul(token, NULL, 10);
}

#ifndef TARGET_APU1
token = strstr(&(bootlist_def[i][0]), "ehcien");
if(token) {
token += strlen("ehcien");
ehci0_toggle = strtoul(token, NULL, 10);
}
token = strstr(&(bootlist_def[i][0]), "mpcie2_clk");
if(token) {
token += strlen("mpcie2_clk");
mpcie2_clk_toggle = strtoul(token, NULL, 10);
}
token = strstr(&(bootlist_def[i][0]), "boosten");
if(token) {
token += strlen("boosten");
boost_toggle = strtoul(token, NULL, 10);
}
#endif
}
}