CHANGELOG.md

@@ -7,6 +7,14 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## [Unreleased]
+## [v4.6.19] - 2020-07-29
+### Added
+- new option in menu to allow reverse PCI addressing order
+
+### Fixed
+- SPI unlock when updating runtime configuration by adding prints to
+ delay SPI status register bits change
+
 ## [v4.6.18] - 2020-04-26
 ### Added
 - PCI Express power management features runtime configuration
@@ -188,7 +196,8 @@ initial commit based on [coreboot_140908](http://pcengines.ch/tmp/coreboot_14090
 ### Fixed
 - used proper way to access extended SPI registers
 
-[Unreleased]: https://github.com/pcengines/sortbootorder/compare/v4.6.18...master
+[Unreleased]: https://github.com/pcengines/sortbootorder/compare/v4.6.19...master
+[v4.6.19]: https://github.com/pcengines/sortbootorder/compare/v4.6.18...v4.6.19
 [v4.6.18]: https://github.com/pcengines/sortbootorder/compare/v4.6.17...v4.6.18
 [v4.6.17]: https://github.com/pcengines/sortbootorder/compare/v4.6.16...v4.6.17
 [v4.6.16]: https://github.com/pcengines/sortbootorder/compare/v4.6.15...v4.6.16

sortbootorder.c

@@ -93,6 +93,7 @@ static u8 ehci0_toggle;
 static u8 mpcie2_clk_toggle;
 static u8 boost_toggle;
 static u8 sd3_toggle;
+static u8 pciereverse_toggle;
 #ifndef COREBOOT_LEGACY
 static u8 iommu_toggle;
 static u8 pciepm_toggle;
@@ -218,6 +219,11 @@ int main(void) {
 	token = strstr(bootorder_data, "sd3mode");
 	token += strlen("sd3mode");
 	sd3_toggle = token ? strtoul(token, NULL, 10) : 0;
+
+	token = strstr(bootorder_data, "pciereverse");
+	token += strlen("pciereverse");
+	pciereverse_toggle = token ? strtoul(token, NULL, 10) : 0;
+
 #ifndef COREBOOT_LEGACY
 	token = strstr(bootorder_data, "iommu");
 	token += strlen("iommu");
@@ -311,6 +317,10 @@ int main(void) {
 			case 'J':
 				sd3_toggle ^= 0x1;
 				break;
+			case 'g':
+			case 'G':
+				pciereverse_toggle ^= 0x1;
+				break;
 #ifndef COREBOOT_LEGACY
 			case 'v':
 			case 'V':
@@ -457,6 +467,9 @@ static void show_boot_device_list(char buffer[MAX_DEVICES][MAX_LENGTH],
 		(wdg_timeout) ? "Enabled" : "Disabled");
 	printf("  j SD 3.0 mode - Currently %s\n",
 		(sd3_toggle) ? "Enabled" : "Disabled");
+	printf("  g Reverse order of PCI addresses - Currently %s\n",
+		(pciereverse_toggle) ? "Enabled" : "Disabled");
+
 #ifndef COREBOOT_LEGACY
 	printf("  v IOMMU - Currently %s\n",
 		(iommu_toggle) ? "Enabled" : "Disabled");
@@ -635,6 +648,7 @@ static void update_tags(char bootlist[MAX_DEVICES][MAX_LENGTH], u8 *max_lines)
 	update_tag_value(bootlist, max_lines, "ehcien", ehci0_toggle + '0');
 	update_tag_value(bootlist, max_lines, "boosten", boost_toggle + '0');
 	update_tag_value(bootlist, max_lines, "sd3mode", sd3_toggle + '0');
+	update_tag_value(bootlist, max_lines, "pciereverse", pciereverse_toggle + '0');
 #ifndef COREBOOT_LEGACY
 	update_tag_value(bootlist, max_lines, "iommu", iommu_toggle + '0');
 	update_tag_value(bootlist, max_lines, "pciepm", pciepm_toggle + '0');
@@ -705,6 +719,10 @@ static void refresh_tag_values(u8 max_lines)
 			token += strlen("sd3mode");
 			sd3_toggle = strtoul(token, NULL, 10);
 		}
+		if(token) {
+			token += strlen("pciereverse");
+			pciereverse_toggle = strtoul(token, NULL, 10);
+		}
 #ifndef COREBOOT_LEGACY
 		token = strstr(&(bootlist_def[i][0]), "iommu");
 		if(token) {

utils/flash_access.c

@@ -113,10 +113,13 @@ void save_flash(int flash_address, char buffer[MAX_DEVICES][MAX_LENGTH],
 
 	// try to unlock the flash if it is locked
 	if (spi_flash_is_locked(flash_device)) {
+		printf("Flash is locked, trying to unlock...\n");
 		spi_flash_unlock(flash_device);
 		if (spi_flash_is_locked(flash_device)) {
 			printf("Flash is write protected. Exiting...\n");
 			return;
+		} else {
+			printf("Flash unlocked successfully.\n");
 		}
 	}