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Some basic components that may be useful in the future, a few scripts/notes about tools...

Three folders:

  • simulations => Screenshots of timing diagrams if available.
  • src => VHDL sources.
  • testbenches => Related testbenches.


  • alu: a simple ALU.
  • dff: a basic D flip-flop.
  • bcd_counter: a modulo-10 counter with asynchronous reset and enable signal.
  • gates: a simple component to illustrate the difference between combinatorial logic and clocked process.
  • mux_2to1: a 2-to-1 multiplexer (4 solutions).
  • mux_4to1: a 4-to-1 multiplexer (4 solutions).
  • myfsm: a FSM with 3 states decomposed in 3 processes.
  • seg_decoder: a 7-segment decoder.