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add floating-point for x86-64

git-archimport-id: bonzini@gnu.org--2004b/lightning--stable--1.2--patch-49
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1 parent 3a04a40 commit 58c4dcea4396193ec4ac18b54ff84dba0c12719c @bonzini bonzini committed Nov 23, 2006
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@@ -1,3 +1,17 @@
+2006-11-23 Paolo Bonzini <bonzini@gnu.org>
+
+ * lightning/core-common.h: Add casts in "*i_p" variants.
+ * lightning/i386/asm-32.h: Add _r1.
+ * lightning/i386/asm-64.h: Likewise, and add SSE instructions.
+ * lightning/i386/asm-i386.h: Merge SSE instructions from Gwenole.
+ Use short form for 16-bit AX instructions. Remove _r1
+ * lightning/i386/core-64.h: Add FP ABI support in its infancy.
+ * lightning/i386/core-i386.h: Move jit_arg_f and jit_arg_d...
+ * lightning/i386/core-32.h: ... and jit_prepare_f and jit_prepare_d...
+ * lightning/i386/fp-32.h: ... here.
+ * lightning/i386/fp-64.h: Write the code.
+ * lightning/sparc/fp.h: Fix jit_extr_{f_d,d_f} register order.
+
2006-11-22 Paolo Bonzini <bonzini@gnu.org>
* lightning/i386/asm-i386.h: Move x86-64 instructions...
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5 NEWS
@@ -2,6 +2,11 @@ NEWS FROM VERSION 1.2 TO 1.3
o Initial support for x86-64 back-end (mostly untested).
+o lightning is more strict on casts from integer to pointer.
+ Be sure to use the _p variants when your immediates are
+ of pointer type. This was done to ease 64-bit cleanliness
+ tests.
+
o Many bug fixes.
o JIT_FPRET is used as JIT_RET to move return values.
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@@ -396,30 +396,30 @@ typedef union jit_code {
#define jit_bmsi_ul(label, rs, is) jit_bmsi_l((label), (rs), (is))
#define jit_ltr_p(d, s1, s2) jit_ltr_ul((d), (s1), (s2))
-#define jit_lti_p(d, rs, is) jit_lti_ul((d), (rs), (is))
+#define jit_lti_p(d, rs, is) jit_lti_ul((d), (rs), (long)(is))
#define jit_ler_p(d, s1, s2) jit_ler_ul((d), (s1), (s2))
-#define jit_lei_p(d, rs, is) jit_lei_ul((d), (rs), (is))
+#define jit_lei_p(d, rs, is) jit_lei_ul((d), (rs), (long)(is))
#define jit_gtr_p(d, s1, s2) jit_gtr_ul((d), (s1), (s2))
-#define jit_gti_p(d, rs, is) jit_gti_ul((d), (rs), (is))
+#define jit_gti_p(d, rs, is) jit_gti_ul((d), (rs), (long)(is))
#define jit_ger_p(d, s1, s2) jit_ger_ul((d), (s1), (s2))
-#define jit_gei_p(d, rs, is) jit_gei_ul((d), (rs), (is))
+#define jit_gei_p(d, rs, is) jit_gei_ul((d), (rs), (long)(is))
#define jit_eqr_p(d, s1, s2) jit_eqr_ul((d), (s1), (s2))
-#define jit_eqi_p(d, rs, is) jit_eqi_ul((d), (rs), (is))
+#define jit_eqi_p(d, rs, is) jit_eqi_ul((d), (rs), (long)(is))
#define jit_ner_p(d, s1, s2) jit_ner_ul((d), (s1), (s2))
-#define jit_nei_p(d, rs, is) jit_nei_ul((d), (rs), (is))
+#define jit_nei_p(d, rs, is) jit_nei_ul((d), (rs), (long)(is))
#define jit_bltr_p(label, s1, s2) jit_bltr_ul((label), (s1), (s2))
-#define jit_blti_p(label, rs, is) jit_blti_ul((label), (rs), (is))
+#define jit_blti_p(label, rs, is) jit_blti_ul((label), (rs), (long)(is))
#define jit_bler_p(label, s1, s2) jit_bler_ul((label), (s1), (s2))
-#define jit_blei_p(label, rs, is) jit_blei_ul((label), (rs), (is))
+#define jit_blei_p(label, rs, is) jit_blei_ul((label), (rs), (long)(is))
#define jit_bgtr_p(label, s1, s2) jit_bgtr_ul((label), (s1), (s2))
-#define jit_bgti_p(label, rs, is) jit_bgti_ul((label), (rs), (is))
+#define jit_bgti_p(label, rs, is) jit_bgti_ul((label), (rs), (long)(is))
#define jit_bger_p(label, s1, s2) jit_bger_ul((label), (s1), (s2))
-#define jit_bgei_p(label, rs, is) jit_bgei_ul((label), (rs), (is))
+#define jit_bgei_p(label, rs, is) jit_bgei_ul((label), (rs), (long)(is))
#define jit_beqr_p(label, s1, s2) jit_beqr_ul((label), (s1), (s2))
-#define jit_beqi_p(label, rs, is) jit_beqi_ul((label), (rs), (is))
+#define jit_beqi_p(label, rs, is) jit_beqi_ul((label), (rs), (long)(is))
#define jit_bner_p(label, s1, s2) jit_bner_ul((label), (s1), (s2))
-#define jit_bnei_p(label, rs, is) jit_bnei_ul((label), (rs), (is))
+#define jit_bnei_p(label, rs, is) jit_bnei_ul((label), (rs), (long)(is))
#define jit_retval_ui(rd) jit_retval_i((rd))
#define jit_retval_uc(rd) jit_retval_i((rd))
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@@ -45,6 +45,7 @@
#include "asm-i386.h"
+#define _r1(R) ( ((R) & ~3) == _AL || ((R) & ~3) == _AH ? _rN(R) : JITFAIL( "8-bit register required"))
#define _rA(R) _r4(R)
/* Use RIP-addressing in 64-bit mode, if possible */
@@ -58,14 +59,14 @@
#define _m64only(X) JITFAIL("invalid instruction in 32-bit mode")
#define _m64(X) ((void)0)
-#define CALLsr(R) CALLLsr(R)
-#define JMPsr(R) JMPLsr(R)
-
#define _AH 0x24
#define _CH 0x25
#define _DH 0x26
#define _BH 0x27
+#define CALLsr(R) CALLLsr(R)
+#define JMPsr(R) JMPLsr(R)
+
#define DECWr(RD) (_d16(), _Or (0x48,_r2(RD) ))
#define DECLr(RD) _Or (0x48,_r4(RD) )
#define INCWr(RD) (_d16(), _Or (0x40,_r2(RD) ))
View
@@ -127,6 +127,8 @@
#define _R15 0x4F
#define _RIP -2
+#define _r1(R) ( ((unsigned) _rC((R) - 16)) < (0x30 - 16) ? _rN(R) : JITFAIL( "8-bit register required"))
+
#if 0
#define _r8(R) ( (_rC(R) == 0x50) ? _rN(R) : JITFAIL("64-bit register required"))
#else
@@ -335,6 +337,40 @@
#define BSWAPQr(R) (_REXQrr(0, R), _OOr (0x0fc8,_r8(R) ))
+
+
+#define __SSEQrr(OP,RS,RSA,RD,RDA) (_REXQrr(RD, RS), _OO_Mrm (0x0f00|(OP) ,_b11,RDA(RD),RSA(RS) ))
+#define __SSEQmr(OP,MD,MB,MI,MS,RD,RDA) (_REXQmr(MB, MI, RD), _OO_r_X (0x0f00|(OP) ,RDA(RD) ,MD,MB,MI,MS ))
+#define __SSEQrm(OP,RS,RSA,MD,MB,MI,MS) (_REXQrm(RS, MB, MI), _OO_r_X (0x0f00|(OP) ,RSA(RS) ,MD,MB,MI,MS ))
+#define __SSEQ1rm(OP,RS,RSA,MD,MB,MI,MS) (_REXQrm(RS, MB, MI), _OO_r_X (0x0f01|(OP) ,RSA(RS) ,MD,MB,MI,MS ))
+
+#define _SSEQrr(PX,OP,RS,RSA,RD,RDA) (_jit_B(PX), __SSEQrr(OP, RS, RSA, RD, RDA))
+#define _SSEQmr(PX,OP,MD,MB,MI,MS,RD,RDA) (_jit_B(PX), __SSEQmr(OP, MD, MB, MI, MS, RD, RDA))
+#define _SSEQrm(PX,OP,RS,RSA,MD,MB,MI,MS) (_jit_B(PX), __SSEQrm(OP, RS, RSA, MD, MB, MI, MS))
+#define _SSEQ1rm(PX,OP,RS,RSA,MD,MB,MI,MS) (_jit_B(PX), __SSEQ1rm(OP, RS, RSA, MD, MB, MI, MS))
+
+#define CVTSS2SIQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTSI, RS,_rX, RD,_r8)
+#define CVTSS2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_r8)
+#define CVTSD2SIQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTSI, RS,_rX, RD,_r8)
+#define CVTSD2SIQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTSI, MD, MB, MI, MS, RD,_r8)
+
+#define CVTSI2SSQrr(RS, RD) _SSEQrr(0xf3, X86_SSE_CVTIS, RS,_r8, RD,_rX)
+#define CVTSI2SSQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf3, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
+#define CVTSI2SDQrr(RS, RD) _SSEQrr(0xf2, X86_SSE_CVTIS, RS,_r8, RD,_rX)
+#define CVTSI2SDQmr(MD, MB, MI, MS, RD) _SSEQmr(0xf2, X86_SSE_CVTIS, MD, MB, MI, MS, RD,_rX)
+
+#define MOVDQXrr(RS, RD) _SSEQrr(0x66, 0x6e, RS,_r8, RD,_rX)
+#define MOVDQXmr(MD, MB, MI, MS, RD) _SSEQmr(0x66, 0x6e, MD, MB, MI, MS, RD,_rX)
+
+#define MOVDXQrr(RS, RD) _SSEQrr(0x66, 0x7e, RS,_rX, RD,_r8)
+#define MOVDXQrm(RS, MD, MB, MI, MS) _SSEQrm(0x66, 0x7e, RS,_rX, MD, MB, MI, MS)
+#define MOVDQMrr(RS, RD) __SSEQrr( 0x6e, RS,_r8, RD,_rM)
+#define MOVDQMmr(MD, MB, MI, MS, RD) __SSEQmr( 0x6e, MD, MB, MI, MS, RD,_rM)
+#define MOVDMQrr(RS, RD) __SSEQrr( 0x7e, RS,_rM, RD,_r8)
+#define MOVDMQrm(RS, MD, MB, MI, MS) __SSEQrm( 0x7e, RS,_rM, MD, MB, MI, MS)
+
+
+
#define CALLsr(R) CALLQsr(R)
#define JMPsr(R) JMPQsr(R)
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