Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP
Newer
Older
100644 461 lines (411 sloc) 18.207 kB
dc99065 added flags computation optimization
bellard authored
1 /* Interface between the opcode library and its callers.
2 Written by Cygnus Support, 1993.
3
4 The opcode library (libopcodes.a) provides instruction decoders for
5 a large variety of instruction sets, callable with an identical
6 interface, for making instruction-processing programs more independent
7 of the instruction set being processed. */
8
9 #ifndef DIS_ASM_H
10 #define DIS_ASM_H
11
c27004e 64 bit target support
bellard authored
12 #include <stdlib.h>
dc99065 added flags computation optimization
bellard authored
13 #include <stdio.h>
04369ff ppc port
bellard authored
14 #include <string.h>
43d4145 bfd.h dependancy removed
bellard authored
15 #include <inttypes.h>
16
17 #define PARAMS(x) x
18 typedef void *PTR;
19 typedef uint64_t bfd_vma;
bc51c5c initial x86-64 host support (Gwenole Beauchesne)
bellard authored
20 typedef int64_t bfd_signed_vma;
43d4145 bfd.h dependancy removed
bellard authored
21 typedef uint8_t bfd_byte;
bc51c5c initial x86-64 host support (Gwenole Beauchesne)
bellard authored
22 #define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
43d4145 bfd.h dependancy removed
bellard authored
23
c27004e 64 bit target support
bellard authored
24 #define BFD64
25
43d4145 bfd.h dependancy removed
bellard authored
26 enum bfd_flavour {
27 bfd_target_unknown_flavour,
28 bfd_target_aout_flavour,
29 bfd_target_coff_flavour,
30 bfd_target_ecoff_flavour,
31 bfd_target_elf_flavour,
32 bfd_target_ieee_flavour,
33 bfd_target_nlm_flavour,
34 bfd_target_oasys_flavour,
35 bfd_target_tekhex_flavour,
36 bfd_target_srec_flavour,
37 bfd_target_ihex_flavour,
38 bfd_target_som_flavour,
39 bfd_target_os9k_flavour,
40 bfd_target_versados_flavour,
41 bfd_target_msdos_flavour,
42 bfd_target_evax_flavour
43 };
44
45 enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
46
5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files
ths authored
47 enum bfd_architecture
43d4145 bfd.h dependancy removed
bellard authored
48 {
49 bfd_arch_unknown, /* File arch not known */
50 bfd_arch_obscure, /* Arch known, not one of these */
51 bfd_arch_m68k, /* Motorola 68xxx */
52 #define bfd_mach_m68000 1
53 #define bfd_mach_m68008 2
54 #define bfd_mach_m68010 3
55 #define bfd_mach_m68020 4
56 #define bfd_mach_m68030 5
57 #define bfd_mach_m68040 6
58 #define bfd_mach_m68060 7
48024e4 m68k disassembler (Paul Brook)
bellard authored
59 #define bfd_mach_cpu32 8
60 #define bfd_mach_mcf5200 9
61 #define bfd_mach_mcf5206e 10
62 #define bfd_mach_mcf5307 11
63 #define bfd_mach_mcf5407 12
64 #define bfd_mach_mcf528x 13
65 #define bfd_mach_mcfv4e 14
66 #define bfd_mach_mcf521x 15
67 #define bfd_mach_mcf5249 16
68 #define bfd_mach_mcf547x 17
69 #define bfd_mach_mcf548x 18
3b46e62 find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the sta…
ths authored
70 bfd_arch_vax, /* DEC Vax */
43d4145 bfd.h dependancy removed
bellard authored
71 bfd_arch_i960, /* Intel 960 */
72 /* The order of the following is important.
5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files
ths authored
73 lower number indicates a machine type that
43d4145 bfd.h dependancy removed
bellard authored
74 only accepts a subset of the instructions
75 available to machines with higher numbers.
76 The exception is the "ca", which is
5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files
ths authored
77 incompatible with all other machines except
43d4145 bfd.h dependancy removed
bellard authored
78 "core". */
79
80 #define bfd_mach_i960_core 1
81 #define bfd_mach_i960_ka_sa 2
82 #define bfd_mach_i960_kb_sb 3
83 #define bfd_mach_i960_mc 4
84 #define bfd_mach_i960_xa 5
85 #define bfd_mach_i960_ca 6
86 #define bfd_mach_i960_jx 7
87 #define bfd_mach_i960_hx 8
88
89 bfd_arch_a29k, /* AMD 29000 */
90 bfd_arch_sparc, /* SPARC */
91 #define bfd_mach_sparc 1
aa0aa4f added ARM and Sparc disassemblers
bellard authored
92 /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
43d4145 bfd.h dependancy removed
bellard authored
93 #define bfd_mach_sparc_sparclet 2
94 #define bfd_mach_sparc_sparclite 3
95 #define bfd_mach_sparc_v8plus 4
aa0aa4f added ARM and Sparc disassemblers
bellard authored
96 #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
97 #define bfd_mach_sparc_sparclite_le 6
98 #define bfd_mach_sparc_v9 7
99 #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
100 #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
101 #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
102 /* Nonzero if MACH has the v9 instruction set. */
43d4145 bfd.h dependancy removed
bellard authored
103 #define bfd_mach_sparc_v9_p(mach) \
aa0aa4f added ARM and Sparc disassemblers
bellard authored
104 ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
105 && (mach) != bfd_mach_sparc_sparclite_le)
43d4145 bfd.h dependancy removed
bellard authored
106 bfd_arch_mips, /* MIPS Rxxxx */
107 #define bfd_mach_mips3000 3000
108 #define bfd_mach_mips3900 3900
109 #define bfd_mach_mips4000 4000
110 #define bfd_mach_mips4010 4010
111 #define bfd_mach_mips4100 4100
112 #define bfd_mach_mips4300 4300
113 #define bfd_mach_mips4400 4400
114 #define bfd_mach_mips4600 4600
115 #define bfd_mach_mips4650 4650
116 #define bfd_mach_mips5000 5000
117 #define bfd_mach_mips6000 6000
118 #define bfd_mach_mips8000 8000
119 #define bfd_mach_mips10000 10000
120 #define bfd_mach_mips16 16
121 bfd_arch_i386, /* Intel 386 */
122 #define bfd_mach_i386_i386 0
123 #define bfd_mach_i386_i8086 1
bc51c5c initial x86-64 host support (Gwenole Beauchesne)
bellard authored
124 #define bfd_mach_i386_i386_intel_syntax 2
125 #define bfd_mach_x86_64 3
126 #define bfd_mach_x86_64_intel_syntax 4
43d4145 bfd.h dependancy removed
bellard authored
127 bfd_arch_we32k, /* AT&T WE32xxx */
128 bfd_arch_tahoe, /* CCI/Harris Tahoe */
129 bfd_arch_i860, /* Intel 860 */
130 bfd_arch_romp, /* IBM ROMP PC/RT */
131 bfd_arch_alliant, /* Alliant */
132 bfd_arch_convex, /* Convex */
133 bfd_arch_m88k, /* Motorola 88xxx */
134 bfd_arch_pyramid, /* Pyramid Technology */
135 bfd_arch_h8300, /* Hitachi H8/300 */
136 #define bfd_mach_h8300 1
137 #define bfd_mach_h8300h 2
138 #define bfd_mach_h8300s 3
139 bfd_arch_powerpc, /* PowerPC */
a245862 ppc64 target
bellard authored
140 #define bfd_mach_ppc 0
141 #define bfd_mach_ppc64 1
142 #define bfd_mach_ppc_403 403
143 #define bfd_mach_ppc_403gc 4030
144 #define bfd_mach_ppc_505 505
145 #define bfd_mach_ppc_601 601
146 #define bfd_mach_ppc_602 602
147 #define bfd_mach_ppc_603 603
148 #define bfd_mach_ppc_ec603e 6031
149 #define bfd_mach_ppc_604 604
150 #define bfd_mach_ppc_620 620
151 #define bfd_mach_ppc_630 630
152 #define bfd_mach_ppc_750 750
153 #define bfd_mach_ppc_860 860
154 #define bfd_mach_ppc_a35 35
155 #define bfd_mach_ppc_rs64ii 642
156 #define bfd_mach_ppc_rs64iii 643
157 #define bfd_mach_ppc_7400 7400
43d4145 bfd.h dependancy removed
bellard authored
158 bfd_arch_rs6000, /* IBM RS/6000 */
159 bfd_arch_hppa, /* HP PA RISC */
160 bfd_arch_d10v, /* Mitsubishi D10V */
161 bfd_arch_z8k, /* Zilog Z8000 */
162 #define bfd_mach_z8001 1
163 #define bfd_mach_z8002 2
164 bfd_arch_h8500, /* Hitachi H8/500 */
165 bfd_arch_sh, /* Hitachi SH */
fdf9b3e sh4 target (Samuel Tardieu)
bellard authored
166 #define bfd_mach_sh 1
167 #define bfd_mach_sh2 0x20
168 #define bfd_mach_sh_dsp 0x2d
169 #define bfd_mach_sh2a 0x2a
170 #define bfd_mach_sh2a_nofpu 0x2b
171 #define bfd_mach_sh2e 0x2e
43d4145 bfd.h dependancy removed
bellard authored
172 #define bfd_mach_sh3 0x30
fdf9b3e sh4 target (Samuel Tardieu)
bellard authored
173 #define bfd_mach_sh3_nommu 0x31
174 #define bfd_mach_sh3_dsp 0x3d
43d4145 bfd.h dependancy removed
bellard authored
175 #define bfd_mach_sh3e 0x3e
176 #define bfd_mach_sh4 0x40
fdf9b3e sh4 target (Samuel Tardieu)
bellard authored
177 #define bfd_mach_sh4_nofpu 0x41
178 #define bfd_mach_sh4_nommu_nofpu 0x42
179 #define bfd_mach_sh4a 0x4a
180 #define bfd_mach_sh4a_nofpu 0x4b
181 #define bfd_mach_sh4al_dsp 0x4d
182 #define bfd_mach_sh5 0x50
43d4145 bfd.h dependancy removed
bellard authored
183 bfd_arch_alpha, /* Dec Alpha */
eddf68a Integrate Alpha target in Qemu core.
j_mayer authored
184 #define bfd_mach_alpha 1
43d4145 bfd.h dependancy removed
bellard authored
185 bfd_arch_arm, /* Advanced Risc Machines ARM */
186 #define bfd_mach_arm_2 1
187 #define bfd_mach_arm_2a 2
188 #define bfd_mach_arm_3 3
189 #define bfd_mach_arm_3M 4
190 #define bfd_mach_arm_4 5
191 #define bfd_mach_arm_4T 6
192 bfd_arch_ns32k, /* National Semiconductors ns32000 */
193 bfd_arch_w65, /* WDC 65816 */
194 bfd_arch_tic30, /* Texas Instruments TMS320C30 */
195 bfd_arch_v850, /* NEC V850 */
196 #define bfd_mach_v850 0
197 bfd_arch_arc, /* Argonaut RISC Core */
198 #define bfd_mach_arc_base 0
199 bfd_arch_m32r, /* Mitsubishi M32R/D */
200 #define bfd_mach_m32r 0 /* backwards compatibility */
201 bfd_arch_mn10200, /* Matsushita MN10200 */
202 bfd_arch_mn10300, /* Matsushita MN10300 */
203 bfd_arch_last
204 };
8f860bb s390 disassembler support, by Ulrich Hecht.
ths authored
205 #define bfd_mach_s390_31 31
206 #define bfd_mach_s390_64 64
43d4145 bfd.h dependancy removed
bellard authored
207
208 typedef struct symbol_cache_entry
209 {
210 const char *name;
211 union
212 {
213 PTR p;
214 bfd_vma i;
215 } udata;
216 } asymbol;
dc99065 added flags computation optimization
bellard authored
217
218 typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...));
219
220 enum dis_insn_type {
221 dis_noninsn, /* Not a valid instruction */
222 dis_nonbranch, /* Not a branch instruction */
223 dis_branch, /* Unconditional branch */
224 dis_condbranch, /* Conditional branch */
225 dis_jsr, /* Jump to subroutine */
226 dis_condjsr, /* Conditional jump to subroutine */
227 dis_dref, /* Data reference instruction */
228 dis_dref2 /* Two data references in instruction */
229 };
230
5fafdf2 find -type f | xargs sed -i 's/[\t ]$//g' # on most files
ths authored
231 /* This struct is passed into the instruction decoding routine,
dc99065 added flags computation optimization
bellard authored
232 and is passed back out into each callback. The various fields are used
233 for conveying information from your main routine into your callbacks,
234 for passing information into the instruction decoders (such as the
235 addresses of the callback functions), or for passing information
236 back from the instruction decoders to their callers.
237
238 It must be initialized before it is first passed; this can be done
239 by hand, or using one of the initialization macros below. */
240
241 typedef struct disassemble_info {
242 fprintf_ftype fprintf_func;
243 FILE *stream;
244 PTR application_data;
245
246 /* Target description. We could replace this with a pointer to the bfd,
247 but that would require one. There currently isn't any such requirement
248 so to avoid introducing one we record these explicitly. */
249 /* The bfd_flavour. This can be bfd_target_unknown_flavour. */
250 enum bfd_flavour flavour;
251 /* The bfd_arch value. */
252 enum bfd_architecture arch;
253 /* The bfd_mach value. */
254 unsigned long mach;
255 /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
256 enum bfd_endian endian;
257
258 /* An array of pointers to symbols either at the location being disassembled
259 or at the start of the function being disassembled. The array is sorted
260 so that the first symbol is intended to be the one used. The others are
261 present for any misc. purposes. This is not set reliably, but if it is
262 not NULL, it is correct. */
263 asymbol **symbols;
264 /* Number of symbols in array. */
265 int num_symbols;
266
267 /* For use by the disassembler.
268 The top 16 bits are reserved for public use (and are documented here).
269 The bottom 16 bits are for the internal use of the disassembler. */
270 unsigned long flags;
271 #define INSN_HAS_RELOC 0x80000000
272 PTR private_data;
273
274 /* Function used to get bytes to disassemble. MEMADDR is the
275 address of the stuff to be disassembled, MYADDR is the address to
276 put the bytes in, and LENGTH is the number of bytes to read.
277 INFO is a pointer to this struct.
278 Returns an errno value or 0 for success. */
279 int (*read_memory_func)
280 PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
281 struct disassemble_info *info));
282
283 /* Function which should be called if we get an error that we can't
284 recover from. STATUS is the errno value from read_memory_func and
285 MEMADDR is the address that we were trying to read. INFO is a
286 pointer to this struct. */
287 void (*memory_error_func)
288 PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info));
289
290 /* Function called to print ADDR. */
291 void (*print_address_func)
292 PARAMS ((bfd_vma addr, struct disassemble_info *info));
293
294 /* Function called to determine if there is a symbol at the given ADDR.
295 If there is, the function returns 1, otherwise it returns 0.
296 This is used by ports which support an overlay manager where
297 the overlay number is held in the top part of an address. In
298 some circumstances we want to include the overlay number in the
299 address, (normally because there is a symbol associated with
300 that address), but sometimes we want to mask out the overlay bits. */
301 int (* symbol_at_address_func)
302 PARAMS ((bfd_vma addr, struct disassemble_info * info));
303
304 /* These are for buffer_read_memory. */
305 bfd_byte *buffer;
306 bfd_vma buffer_vma;
307 int buffer_length;
308
309 /* This variable may be set by the instruction decoder. It suggests
310 the number of bytes objdump should display on a single line. If
311 the instruction decoder sets this, it should always set it to
312 the same value in order to get reasonable looking output. */
313 int bytes_per_line;
314
315 /* the next two variables control the way objdump displays the raw data */
316 /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
317 /* output will look like this:
318 00: 00000000 00000000
319 with the chunks displayed according to "display_endian". */
320 int bytes_per_chunk;
321 enum bfd_endian display_endian;
322
323 /* Results from instruction decoders. Not all decoders yet support
324 this information. This info is set each time an instruction is
325 decoded, and is only valid for the last such instruction.
326
327 To determine whether this decoder supports this information, set
328 insn_info_valid to 0, decode an instruction, then check it. */
329
330 char insn_info_valid; /* Branch info has been set. */
331 char branch_delay_insns; /* How many sequential insn's will run before
332 a branch takes effect. (0 = normal) */
333 char data_size; /* Size of data reference in insn, in bytes */
334 enum dis_insn_type insn_type; /* Type of instruction */
335 bfd_vma target; /* Target address of branch or dref, if known;
336 zero if unknown. */
337 bfd_vma target2; /* Second target address for dref2 */
338
aa0aa4f added ARM and Sparc disassemblers
bellard authored
339 /* Command line options specific to the target disassembler. */
340 char * disassembler_options;
341
dc99065 added flags computation optimization
bellard authored
342 } disassemble_info;
343
344
345 /* Standard disassemblers. Disassemble one instruction at the given
346 target address. Return number of bytes processed. */
347 typedef int (*disassembler_ftype)
348 PARAMS((bfd_vma, disassemble_info *));
349
350 extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*));
351 extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
352 extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*));
353 extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
354 extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
355 extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));
356 extern int print_insn_h8300 PARAMS ((bfd_vma, disassemble_info*));
357 extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*));
358 extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*));
359 extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*));
360 extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
361 extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
aa0aa4f added ARM and Sparc disassemblers
bellard authored
362 extern int print_insn_arm PARAMS ((bfd_vma, disassemble_info*));
dc99065 added flags computation optimization
bellard authored
363 extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*));
364 extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*));
365 extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*));
366 extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*));
367 extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*));
368 extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*));
369 extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*));
370 extern int print_insn_m32r PARAMS ((bfd_vma, disassemble_info*));
371 extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*));
372 extern int print_insn_mn10200 PARAMS ((bfd_vma, disassemble_info*));
373 extern int print_insn_mn10300 PARAMS ((bfd_vma, disassemble_info*));
374 extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*));
375 extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*));
376 extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*));
377 extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*));
378 extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*));
379 extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*));
380 extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*));
381 extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*));
b9adb4a PowerPC disas code
bellard authored
382 extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*));
eddf68a Integrate Alpha target in Qemu core.
j_mayer authored
383 extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
8f860bb s390 disassembler support, by Ulrich Hecht.
ths authored
384 extern int print_insn_s390 PARAMS ((bfd_vma, disassemble_info*));
dc99065 added flags computation optimization
bellard authored
385
43d4145 bfd.h dependancy removed
bellard authored
386 #if 0
dc99065 added flags computation optimization
bellard authored
387 /* Fetch the disassembler for a given BFD, if that support is available. */
388 extern disassembler_ftype disassembler PARAMS ((bfd *));
43d4145 bfd.h dependancy removed
bellard authored
389 #endif
dc99065 added flags computation optimization
bellard authored
390
391
392 /* This block of definitions is for particular callers who read instructions
393 into a buffer before calling the instruction decoder. */
394
395 /* Here is a function which callers may wish to use for read_memory_func.
396 It gets bytes from a buffer. */
397 extern int buffer_read_memory
398 PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *));
399
400 /* This function goes with buffer_read_memory.
401 It prints a message using info->fprintf_func and info->stream. */
402 extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *));
403
404
405 /* Just print the address in hex. This is included for completeness even
406 though both GDB and objdump provide their own (to print symbolic
407 addresses). */
408 extern void generic_print_address
409 PARAMS ((bfd_vma, struct disassemble_info *));
410
411 /* Always true. */
412 extern int generic_symbol_at_address
413 PARAMS ((bfd_vma, struct disassemble_info *));
414
415 /* Macro to initialize a disassemble_info struct. This should be called
416 by all applications creating such a struct. */
417 #define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
418 (INFO).flavour = bfd_target_unknown_flavour, \
419 (INFO).arch = bfd_arch_unknown, \
420 (INFO).mach = 0, \
421 (INFO).endian = BFD_ENDIAN_UNKNOWN, \
422 INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)
423
424 /* Call this macro to initialize only the internal variables for the
425 disassembler. Architecture dependent things such as byte order, or machine
426 variant are not touched by this macro. This makes things much easier for
aa1f17c Spelling fixes, by Stefan Weil.
ths authored
427 GDB which must initialize these things separately. */
dc99065 added flags computation optimization
bellard authored
428
429 #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
430 (INFO).fprintf_func = (FPRINTF_FUNC), \
431 (INFO).stream = (STREAM), \
432 (INFO).symbols = NULL, \
433 (INFO).num_symbols = 0, \
434 (INFO).buffer = NULL, \
435 (INFO).buffer_vma = 0, \
436 (INFO).buffer_length = 0, \
437 (INFO).read_memory_func = buffer_read_memory, \
438 (INFO).memory_error_func = perror_memory, \
439 (INFO).print_address_func = generic_print_address, \
440 (INFO).symbol_at_address_func = generic_symbol_at_address, \
441 (INFO).flags = 0, \
442 (INFO).bytes_per_line = 0, \
443 (INFO).bytes_per_chunk = 0, \
444 (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
aa0aa4f added ARM and Sparc disassemblers
bellard authored
445 (INFO).disassembler_options = NULL, \
dc99065 added flags computation optimization
bellard authored
446 (INFO).insn_info_valid = 0
447
aa0aa4f added ARM and Sparc disassemblers
bellard authored
448 #define _(x) x
48024e4 m68k disassembler (Paul Brook)
bellard authored
449 #define ATTRIBUTE_UNUSED __attribute__((unused))
aa0aa4f added ARM and Sparc disassemblers
bellard authored
450
451 /* from libbfd */
452
453 bfd_vma bfd_getl32 (const bfd_byte *addr);
454 bfd_vma bfd_getb32 (const bfd_byte *addr);
6af0bf9 MIPS target (Jocelyn Mayer)
bellard authored
455 bfd_vma bfd_getl16 (const bfd_byte *addr);
456 bfd_vma bfd_getb16 (const bfd_byte *addr);
aa0aa4f added ARM and Sparc disassemblers
bellard authored
457 typedef enum bfd_boolean {false, true} boolean;
48024e4 m68k disassembler (Paul Brook)
bellard authored
458 typedef boolean bfd_boolean;
aa0aa4f added ARM and Sparc disassemblers
bellard authored
459
dc99065 added flags computation optimization
bellard authored
460 #endif /* ! defined (DIS_ASM_H) */
Something went wrong with that request. Please try again.