Skip to content
Newer
Older
100644 407 lines (358 sloc) 16 KB
dc99065 added flags computation optimization
bellard authored
1 /* Interface between the opcode library and its callers.
2 Written by Cygnus Support, 1993.
3
4 The opcode library (libopcodes.a) provides instruction decoders for
5 a large variety of instruction sets, callable with an identical
6 interface, for making instruction-processing programs more independent
7 of the instruction set being processed. */
8
9 #ifndef DIS_ASM_H
10 #define DIS_ASM_H
11
12 #include <stdio.h>
04369ff ppc port
bellard authored
13 #include <string.h>
43d4145 bfd.h dependancy removed
bellard authored
14 #include <inttypes.h>
15
16 #define PARAMS(x) x
17 typedef void *PTR;
18 typedef uint64_t bfd_vma;
bc51c5c initial x86-64 host support (Gwenole Beauchesne)
bellard authored
19 typedef int64_t bfd_signed_vma;
43d4145 bfd.h dependancy removed
bellard authored
20 typedef uint8_t bfd_byte;
bc51c5c initial x86-64 host support (Gwenole Beauchesne)
bellard authored
21 #define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
43d4145 bfd.h dependancy removed
bellard authored
22
23 enum bfd_flavour {
24 bfd_target_unknown_flavour,
25 bfd_target_aout_flavour,
26 bfd_target_coff_flavour,
27 bfd_target_ecoff_flavour,
28 bfd_target_elf_flavour,
29 bfd_target_ieee_flavour,
30 bfd_target_nlm_flavour,
31 bfd_target_oasys_flavour,
32 bfd_target_tekhex_flavour,
33 bfd_target_srec_flavour,
34 bfd_target_ihex_flavour,
35 bfd_target_som_flavour,
36 bfd_target_os9k_flavour,
37 bfd_target_versados_flavour,
38 bfd_target_msdos_flavour,
39 bfd_target_evax_flavour
40 };
41
42 enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
43
44 enum bfd_architecture
45 {
46 bfd_arch_unknown, /* File arch not known */
47 bfd_arch_obscure, /* Arch known, not one of these */
48 bfd_arch_m68k, /* Motorola 68xxx */
49 #define bfd_mach_m68000 1
50 #define bfd_mach_m68008 2
51 #define bfd_mach_m68010 3
52 #define bfd_mach_m68020 4
53 #define bfd_mach_m68030 5
54 #define bfd_mach_m68040 6
55 #define bfd_mach_m68060 7
56 bfd_arch_vax, /* DEC Vax */
57 bfd_arch_i960, /* Intel 960 */
58 /* The order of the following is important.
59 lower number indicates a machine type that
60 only accepts a subset of the instructions
61 available to machines with higher numbers.
62 The exception is the "ca", which is
63 incompatible with all other machines except
64 "core". */
65
66 #define bfd_mach_i960_core 1
67 #define bfd_mach_i960_ka_sa 2
68 #define bfd_mach_i960_kb_sb 3
69 #define bfd_mach_i960_mc 4
70 #define bfd_mach_i960_xa 5
71 #define bfd_mach_i960_ca 6
72 #define bfd_mach_i960_jx 7
73 #define bfd_mach_i960_hx 8
74
75 bfd_arch_a29k, /* AMD 29000 */
76 bfd_arch_sparc, /* SPARC */
77 #define bfd_mach_sparc 1
aa0aa4f added ARM and Sparc disassemblers
bellard authored
78 /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
43d4145 bfd.h dependancy removed
bellard authored
79 #define bfd_mach_sparc_sparclet 2
80 #define bfd_mach_sparc_sparclite 3
81 #define bfd_mach_sparc_v8plus 4
aa0aa4f added ARM and Sparc disassemblers
bellard authored
82 #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
83 #define bfd_mach_sparc_sparclite_le 6
84 #define bfd_mach_sparc_v9 7
85 #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
86 #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
87 #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
88 /* Nonzero if MACH has the v9 instruction set. */
43d4145 bfd.h dependancy removed
bellard authored
89 #define bfd_mach_sparc_v9_p(mach) \
aa0aa4f added ARM and Sparc disassemblers
bellard authored
90 ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
91 && (mach) != bfd_mach_sparc_sparclite_le)
43d4145 bfd.h dependancy removed
bellard authored
92 bfd_arch_mips, /* MIPS Rxxxx */
93 #define bfd_mach_mips3000 3000
94 #define bfd_mach_mips3900 3900
95 #define bfd_mach_mips4000 4000
96 #define bfd_mach_mips4010 4010
97 #define bfd_mach_mips4100 4100
98 #define bfd_mach_mips4300 4300
99 #define bfd_mach_mips4400 4400
100 #define bfd_mach_mips4600 4600
101 #define bfd_mach_mips4650 4650
102 #define bfd_mach_mips5000 5000
103 #define bfd_mach_mips6000 6000
104 #define bfd_mach_mips8000 8000
105 #define bfd_mach_mips10000 10000
106 #define bfd_mach_mips16 16
107 bfd_arch_i386, /* Intel 386 */
108 #define bfd_mach_i386_i386 0
109 #define bfd_mach_i386_i8086 1
bc51c5c initial x86-64 host support (Gwenole Beauchesne)
bellard authored
110 #define bfd_mach_i386_i386_intel_syntax 2
111 #define bfd_mach_x86_64 3
112 #define bfd_mach_x86_64_intel_syntax 4
43d4145 bfd.h dependancy removed
bellard authored
113 bfd_arch_we32k, /* AT&T WE32xxx */
114 bfd_arch_tahoe, /* CCI/Harris Tahoe */
115 bfd_arch_i860, /* Intel 860 */
116 bfd_arch_romp, /* IBM ROMP PC/RT */
117 bfd_arch_alliant, /* Alliant */
118 bfd_arch_convex, /* Convex */
119 bfd_arch_m88k, /* Motorola 88xxx */
120 bfd_arch_pyramid, /* Pyramid Technology */
121 bfd_arch_h8300, /* Hitachi H8/300 */
122 #define bfd_mach_h8300 1
123 #define bfd_mach_h8300h 2
124 #define bfd_mach_h8300s 3
125 bfd_arch_powerpc, /* PowerPC */
126 bfd_arch_rs6000, /* IBM RS/6000 */
127 bfd_arch_hppa, /* HP PA RISC */
128 bfd_arch_d10v, /* Mitsubishi D10V */
129 bfd_arch_z8k, /* Zilog Z8000 */
130 #define bfd_mach_z8001 1
131 #define bfd_mach_z8002 2
132 bfd_arch_h8500, /* Hitachi H8/500 */
133 bfd_arch_sh, /* Hitachi SH */
134 #define bfd_mach_sh 0
135 #define bfd_mach_sh3 0x30
136 #define bfd_mach_sh3e 0x3e
137 #define bfd_mach_sh4 0x40
138 bfd_arch_alpha, /* Dec Alpha */
139 bfd_arch_arm, /* Advanced Risc Machines ARM */
140 #define bfd_mach_arm_2 1
141 #define bfd_mach_arm_2a 2
142 #define bfd_mach_arm_3 3
143 #define bfd_mach_arm_3M 4
144 #define bfd_mach_arm_4 5
145 #define bfd_mach_arm_4T 6
146 bfd_arch_ns32k, /* National Semiconductors ns32000 */
147 bfd_arch_w65, /* WDC 65816 */
148 bfd_arch_tic30, /* Texas Instruments TMS320C30 */
149 bfd_arch_v850, /* NEC V850 */
150 #define bfd_mach_v850 0
151 bfd_arch_arc, /* Argonaut RISC Core */
152 #define bfd_mach_arc_base 0
153 bfd_arch_m32r, /* Mitsubishi M32R/D */
154 #define bfd_mach_m32r 0 /* backwards compatibility */
155 bfd_arch_mn10200, /* Matsushita MN10200 */
156 bfd_arch_mn10300, /* Matsushita MN10300 */
157 bfd_arch_last
158 };
159
160 typedef struct symbol_cache_entry
161 {
162 const char *name;
163 union
164 {
165 PTR p;
166 bfd_vma i;
167 } udata;
168 } asymbol;
dc99065 added flags computation optimization
bellard authored
169
170 typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...));
171
172 enum dis_insn_type {
173 dis_noninsn, /* Not a valid instruction */
174 dis_nonbranch, /* Not a branch instruction */
175 dis_branch, /* Unconditional branch */
176 dis_condbranch, /* Conditional branch */
177 dis_jsr, /* Jump to subroutine */
178 dis_condjsr, /* Conditional jump to subroutine */
179 dis_dref, /* Data reference instruction */
180 dis_dref2 /* Two data references in instruction */
181 };
182
183 /* This struct is passed into the instruction decoding routine,
184 and is passed back out into each callback. The various fields are used
185 for conveying information from your main routine into your callbacks,
186 for passing information into the instruction decoders (such as the
187 addresses of the callback functions), or for passing information
188 back from the instruction decoders to their callers.
189
190 It must be initialized before it is first passed; this can be done
191 by hand, or using one of the initialization macros below. */
192
193 typedef struct disassemble_info {
194 fprintf_ftype fprintf_func;
195 FILE *stream;
196 PTR application_data;
197
198 /* Target description. We could replace this with a pointer to the bfd,
199 but that would require one. There currently isn't any such requirement
200 so to avoid introducing one we record these explicitly. */
201 /* The bfd_flavour. This can be bfd_target_unknown_flavour. */
202 enum bfd_flavour flavour;
203 /* The bfd_arch value. */
204 enum bfd_architecture arch;
205 /* The bfd_mach value. */
206 unsigned long mach;
207 /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
208 enum bfd_endian endian;
209
210 /* An array of pointers to symbols either at the location being disassembled
211 or at the start of the function being disassembled. The array is sorted
212 so that the first symbol is intended to be the one used. The others are
213 present for any misc. purposes. This is not set reliably, but if it is
214 not NULL, it is correct. */
215 asymbol **symbols;
216 /* Number of symbols in array. */
217 int num_symbols;
218
219 /* For use by the disassembler.
220 The top 16 bits are reserved for public use (and are documented here).
221 The bottom 16 bits are for the internal use of the disassembler. */
222 unsigned long flags;
223 #define INSN_HAS_RELOC 0x80000000
224 PTR private_data;
225
226 /* Function used to get bytes to disassemble. MEMADDR is the
227 address of the stuff to be disassembled, MYADDR is the address to
228 put the bytes in, and LENGTH is the number of bytes to read.
229 INFO is a pointer to this struct.
230 Returns an errno value or 0 for success. */
231 int (*read_memory_func)
232 PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length,
233 struct disassemble_info *info));
234
235 /* Function which should be called if we get an error that we can't
236 recover from. STATUS is the errno value from read_memory_func and
237 MEMADDR is the address that we were trying to read. INFO is a
238 pointer to this struct. */
239 void (*memory_error_func)
240 PARAMS ((int status, bfd_vma memaddr, struct disassemble_info *info));
241
242 /* Function called to print ADDR. */
243 void (*print_address_func)
244 PARAMS ((bfd_vma addr, struct disassemble_info *info));
245
246 /* Function called to determine if there is a symbol at the given ADDR.
247 If there is, the function returns 1, otherwise it returns 0.
248 This is used by ports which support an overlay manager where
249 the overlay number is held in the top part of an address. In
250 some circumstances we want to include the overlay number in the
251 address, (normally because there is a symbol associated with
252 that address), but sometimes we want to mask out the overlay bits. */
253 int (* symbol_at_address_func)
254 PARAMS ((bfd_vma addr, struct disassemble_info * info));
255
256 /* These are for buffer_read_memory. */
257 bfd_byte *buffer;
258 bfd_vma buffer_vma;
259 int buffer_length;
260
261 /* This variable may be set by the instruction decoder. It suggests
262 the number of bytes objdump should display on a single line. If
263 the instruction decoder sets this, it should always set it to
264 the same value in order to get reasonable looking output. */
265 int bytes_per_line;
266
267 /* the next two variables control the way objdump displays the raw data */
268 /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
269 /* output will look like this:
270 00: 00000000 00000000
271 with the chunks displayed according to "display_endian". */
272 int bytes_per_chunk;
273 enum bfd_endian display_endian;
274
275 /* Results from instruction decoders. Not all decoders yet support
276 this information. This info is set each time an instruction is
277 decoded, and is only valid for the last such instruction.
278
279 To determine whether this decoder supports this information, set
280 insn_info_valid to 0, decode an instruction, then check it. */
281
282 char insn_info_valid; /* Branch info has been set. */
283 char branch_delay_insns; /* How many sequential insn's will run before
284 a branch takes effect. (0 = normal) */
285 char data_size; /* Size of data reference in insn, in bytes */
286 enum dis_insn_type insn_type; /* Type of instruction */
287 bfd_vma target; /* Target address of branch or dref, if known;
288 zero if unknown. */
289 bfd_vma target2; /* Second target address for dref2 */
290
aa0aa4f added ARM and Sparc disassemblers
bellard authored
291 /* Command line options specific to the target disassembler. */
292 char * disassembler_options;
293
dc99065 added flags computation optimization
bellard authored
294 } disassemble_info;
295
296
297 /* Standard disassemblers. Disassemble one instruction at the given
298 target address. Return number of bytes processed. */
299 typedef int (*disassembler_ftype)
300 PARAMS((bfd_vma, disassemble_info *));
301
302 extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*));
303 extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
304 extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*));
305 extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
306 extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
307 extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));
308 extern int print_insn_h8300 PARAMS ((bfd_vma, disassemble_info*));
309 extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*));
310 extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*));
311 extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*));
312 extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*));
313 extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
aa0aa4f added ARM and Sparc disassemblers
bellard authored
314 extern int print_insn_arm PARAMS ((bfd_vma, disassemble_info*));
dc99065 added flags computation optimization
bellard authored
315 extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*));
316 extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*));
317 extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*));
318 extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*));
319 extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*));
320 extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*));
321 extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*));
322 extern int print_insn_m32r PARAMS ((bfd_vma, disassemble_info*));
323 extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*));
324 extern int print_insn_mn10200 PARAMS ((bfd_vma, disassemble_info*));
325 extern int print_insn_mn10300 PARAMS ((bfd_vma, disassemble_info*));
326 extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*));
327 extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*));
328 extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*));
329 extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*));
330 extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*));
331 extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*));
332 extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*));
333 extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*));
b9adb4a PowerPC disas code
bellard authored
334 extern int print_insn_ppc PARAMS ((bfd_vma, disassemble_info*));
dc99065 added flags computation optimization
bellard authored
335
43d4145 bfd.h dependancy removed
bellard authored
336 #if 0
dc99065 added flags computation optimization
bellard authored
337 /* Fetch the disassembler for a given BFD, if that support is available. */
338 extern disassembler_ftype disassembler PARAMS ((bfd *));
43d4145 bfd.h dependancy removed
bellard authored
339 #endif
dc99065 added flags computation optimization
bellard authored
340
341
342 /* This block of definitions is for particular callers who read instructions
343 into a buffer before calling the instruction decoder. */
344
345 /* Here is a function which callers may wish to use for read_memory_func.
346 It gets bytes from a buffer. */
347 extern int buffer_read_memory
348 PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *));
349
350 /* This function goes with buffer_read_memory.
351 It prints a message using info->fprintf_func and info->stream. */
352 extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *));
353
354
355 /* Just print the address in hex. This is included for completeness even
356 though both GDB and objdump provide their own (to print symbolic
357 addresses). */
358 extern void generic_print_address
359 PARAMS ((bfd_vma, struct disassemble_info *));
360
361 /* Always true. */
362 extern int generic_symbol_at_address
363 PARAMS ((bfd_vma, struct disassemble_info *));
364
365 /* Macro to initialize a disassemble_info struct. This should be called
366 by all applications creating such a struct. */
367 #define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
368 (INFO).flavour = bfd_target_unknown_flavour, \
369 (INFO).arch = bfd_arch_unknown, \
370 (INFO).mach = 0, \
371 (INFO).endian = BFD_ENDIAN_UNKNOWN, \
372 INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)
373
374 /* Call this macro to initialize only the internal variables for the
375 disassembler. Architecture dependent things such as byte order, or machine
376 variant are not touched by this macro. This makes things much easier for
377 GDB which must initialize these things seperatly. */
378
379 #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
380 (INFO).fprintf_func = (FPRINTF_FUNC), \
381 (INFO).stream = (STREAM), \
382 (INFO).symbols = NULL, \
383 (INFO).num_symbols = 0, \
384 (INFO).buffer = NULL, \
385 (INFO).buffer_vma = 0, \
386 (INFO).buffer_length = 0, \
387 (INFO).read_memory_func = buffer_read_memory, \
388 (INFO).memory_error_func = perror_memory, \
389 (INFO).print_address_func = generic_print_address, \
390 (INFO).symbol_at_address_func = generic_symbol_at_address, \
391 (INFO).flags = 0, \
392 (INFO).bytes_per_line = 0, \
393 (INFO).bytes_per_chunk = 0, \
394 (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
aa0aa4f added ARM and Sparc disassemblers
bellard authored
395 (INFO).disassembler_options = NULL, \
dc99065 added flags computation optimization
bellard authored
396 (INFO).insn_info_valid = 0
397
aa0aa4f added ARM and Sparc disassemblers
bellard authored
398 #define _(x) x
399
400 /* from libbfd */
401
402 bfd_vma bfd_getl32 (const bfd_byte *addr);
403 bfd_vma bfd_getb32 (const bfd_byte *addr);
404 typedef enum bfd_boolean {false, true} boolean;
405
dc99065 added flags computation optimization
bellard authored
406 #endif /* ! defined (DIS_ASM_H) */
Something went wrong with that request. Please try again.