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multi-cycle reads on fpga

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pepijndevos committed Aug 8, 2019
1 parent 7e6a22e commit d8db23b97c50d87e3f81d7199f97b7b97f0d51d7
Showing with 68 additions and 32 deletions.
  1. +2 −6 alu.vhd
  2. +19 −0 bram.v
  3. +7 −7 cpu.vhd
  4. +6 −6 cpu_tb.v
  5. +2 −0 littlebee/cpu/cpu.gprj
  6. +25 −13 littlebee/cpu/src/top.vhd
  7. +7 −0 rom.mem
@@ -18,13 +18,10 @@ architecture rtl of alu is
signal ci, cip : std_logic; -- carry in
signal co : std_logic; -- carry out
signal cr : std_logic; -- reset value
signal first : std_logic; -- ignore co on first clock
begin

c <= ci;

ci <= cr when first = '1' else cip;

process(opcode, a, b, ci)
begin
case opcode is
@@ -71,10 +68,9 @@ begin
begin
if(rising_edge(clk)) then
if(rst_n = '0') then
first <= '1';
ci <= cr;
else
first <= '0';
cip <= co;
ci <= co;
end if;
end if;
end process;
19 bram.v
@@ -0,0 +1,19 @@
module bram(input clk, wren_n, oen_n,
input [15:0] address, data_in,
output reg [15:0] data_out);

parameter bits = 10;

reg [15:0] memory [0:(1<<bits)-1];
// fuck Gowin FPGA Designer software
initial $readmemb("/home/pepijn/code/74xx-liberty/cpu/rom.mem", memory);

always @(posedge clk)
if (wren_n == 1'b0)
memory[address] <= data_in;

always @(posedge clk)
if (oen_n == 1'b0)
data_out <= memory[address];

endmodule
14 cpu.vhd
@@ -41,9 +41,9 @@ begin
y => pcinc
);

-- "00" & lit ld lit, b
-- "010" ld a, [b]
-- "011" ld [a], a
-- "00" & lit ld lit, B
-- "010" ld A, [B]
-- "011" ld [B], B
-- "1000" & op op A, B, A
-- "1001" & op op A, B, B
-- "1010" & op op A, B, PC
@@ -90,15 +90,15 @@ begin
alu_rst_n <= '1';
state <= ALU_OP;
else -- indirect load
address <= a;
data_out <= b;
if op(13) = '0' then -- ld b, [a]
address <= b;
data_out <= a;
if op(13) = '0' then -- ld a, [b]
wren_n <= '0';
oen_n <= '1';
counter <= x"f";
alu_rst_n <= '1';
state <= ALU_OP;
else -- ld [a], a
else -- ld [b], b
wren_n <= '1';
oen_n <= '0';
counter <= x"3";
@@ -75,23 +75,23 @@ module testbench (input clk, rst, [15:0]data_in,
assert property ( // EXECUTE ld lit, B
@(posedge clk) DUT.state == 1 && DUT.op[15:14] == 2'b00 |=>
DUT.state == 3 && // ALU
DUT.b == DUT.op[13:0] && // read address
DUT.B == DUT.op[13:0] && // read address
wren_n == 1
);
assert property ( // EXECUTE ld A, [B]
@(posedge clk) DUT.state == 1 && DUT.op[15:13] == 3'b010 |=>
DUT.state == 3 && // ALU
address == DUT.a && // write address
data_out == DUT.b &&
address == DUT.b && // write address
data_out == DUT.a &&
wren_n == 0 &&
oen_n == 1
);
assert property ( // EXECUTE ld [A], A
assert property ( // EXECUTE ld [B], B
@(posedge clk) DUT.state == 1 && DUT.op[15:13] == 3'b011 |=>
DUT.state == 2 && // LOAD
address == DUT.a && // read address
address == DUT.b && // read address
wren_n == 1 &&
oen_n == 0
);
@@ -114,7 +114,7 @@ module testbench (input clk, rst, [15:0]data_in,
assert property ( // LOAD
@(posedge clk) DUT.state == 2 && DUT.counter == 0 |=>
DUT.state == 3 && // ALU
DUT.a == $past(data_in) &&
DUT.b == $past(data_in) &&
wren_n == 1 &&
oen_n == 0
);
@@ -11,5 +11,7 @@
<File path="src/cpu.cst" type="file.cst" enable="1"/>
<File path="src/cpu.sdc" type="file.sdc" enable="1"/>
<File path="src/top.vhd" type="file.source" enable="1"/>
<File path="/home/pepijn/code/74xx-liberty/cpu/bram.v" type="file.source" enable="1"/>
<File path="/home/pepijn/code/74xx-liberty/cpu/rom.mem" type="file.other" enable="1"/>
</FileList>
</Project>
@@ -15,6 +15,20 @@ architecture behavior of top is
signal data_in : std_logic_vector(15 downto 0);
signal data_out : std_logic_vector(15 downto 0);
signal wren_n : std_logic;
signal oen_n : std_logic;


component bram
port (
clk : in std_logic;
wren_n : in std_logic;
oen_n : in std_logic;
address : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0)
);
end component;

begin

led <= data_out(15 downto 8);
@@ -25,20 +39,18 @@ begin
address => address,
data_in => data_in,
data_out => data_out,
wren_n => wren_n
wren_n => wren_n,
oen_n => oen_n
);

mem: bram port map (
clk => clk,
wren_n => wren_n,
oen_n => oen_n,
address => address,
data_in => data_out,
data_out => data_in
);

process(address)
begin
case address is
when x"0000" => data_in <= "1100101000000000"; -- B A 0 A ;
when x"0001" => data_in <= "1100000000000001"; -- add A 1 A;
when x"0002" => data_in <= "0000000000000010"; -- ld B 0010;
when x"0003" => data_in <= "0100000000000000"; -- ld A [B] ;
when x"0004" => data_in <= "0000000000000001"; -- ld B 0001;
when x"0005" => data_in <= "1010101000000000"; -- jp B ;
when others => data_in <= "0000000000000000";
end case;
end process;

end;
@@ -0,0 +1,7 @@
1100101000000000 // B A 0 A
1100000000000001 // add A 1 A
0000000011111111 // ld B 00ff
0100000000000000 // ld A [B]
0000000000000001 // ld B 0001
1010101000000000 // jp B
0000000000000000

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