Browse files

Added SNEV and JPV instructions

  • Loading branch information...
1 parent 67231dc commit 765af6b19dc078593f44ee8e491cef4c9cd322c0 @perfp committed Jan 2, 2012
Showing with 22 additions and 3 deletions.
  1. +12 −2 Chip8Emulator/CPU.cs
  2. +10 −1 Chip8EmulatorTests/CPUTests.cs
View
14 Chip8Emulator/CPU.cs
@@ -27,8 +27,9 @@ public CPU(Memory memory)
InstructionSet[0x6] = LD;
InstructionSet[0x7] = ADD;
InstructionSet[0x8] = REG;
- InstructionSet[0x9] = SNER;
+ InstructionSet[0x9] = SNEV;
InstructionSet[0xA] = LDI;
+ InstructionSet[0xB] = JPV;
RegisterCommands[0x0] = (x, y) => Register[x] = Register[y];
@@ -183,7 +184,7 @@ private bool REG(ushort instruction)
return false;
}
- private bool SNER(ushort instruction)
+ private bool SNEV(ushort instruction)
{
var regX = GetX(instruction);
var regY = GetY(instruction);
@@ -198,6 +199,15 @@ private bool SNER(ushort instruction)
}
+ private bool JPV(ushort instruction)
+ {
+ var offset = Register[0];
+ var address = GetAddress(instruction);
+
+ var a = (ushort)offset + address;
+
+ }
+
private byte GetY(ushort instruction)
{
return (byte) (instruction >> 4 & 0x0f);
View
11 Chip8EmulatorTests/CPUTests.cs
@@ -265,7 +265,16 @@ public void CanHandleSNExy()
Assert.AreEqual(0x202, cpu.InstructionPointer);
}
-
+
+ [TestMethod]
+ public void CanHandleJPOffset()
+ {
+ var cpu = SetupMachine();
+ cpu.Register[0] = 0x30;
+ cpu.ProcessInstruction(0xb300);
+
+ Assert.AreEqual(0x330, cpu.InstructionPointer);
+ }
private CPU SetupMachine()
{

0 comments on commit 765af6b

Please sign in to comment.