From 9435b3ae1fc6421f2c1d7ea6e4afcbc3711e9f06 Mon Sep 17 00:00:00 2001 From: peter Date: Thu, 28 Apr 2022 00:01:29 +0100 Subject: [PATCH] Start of 68000 assembly book --- content/asm/68000/_index.html | 20 +++ content/asm/68000/opcodes/_index.html | 10 ++ .../asm/68000/opcodes/conventions/_index.html | 141 ++++++++++++++++++ content/asm/68000/opcodes/math/_index.html | 7 + .../asm/68000/opcodes/math/abcd/_index.html | 53 +++++++ .../asm/68000/opcodes/math/addx/_index.html | 64 ++++++++ themes/area51/assets/scss/custom/table.scss | 8 + .../area51/layouts/shortcodes/m68k/block.html | 4 + .../area51/layouts/shortcodes/m68k/flags.html | 31 ++++ .../layouts/shortcodes/m68k/instruction.html | 110 ++++++++++++++ .../area51/layouts/shortcodes/m68k/size.html | 9 ++ 11 files changed, 457 insertions(+) create mode 100644 content/asm/68000/_index.html create mode 100644 content/asm/68000/opcodes/_index.html create mode 100644 content/asm/68000/opcodes/conventions/_index.html create mode 100644 content/asm/68000/opcodes/math/_index.html create mode 100644 content/asm/68000/opcodes/math/abcd/_index.html create mode 100644 content/asm/68000/opcodes/math/addx/_index.html create mode 100644 themes/area51/layouts/shortcodes/m68k/block.html create mode 100644 themes/area51/layouts/shortcodes/m68k/flags.html create mode 100644 themes/area51/layouts/shortcodes/m68k/instruction.html create mode 100644 themes/area51/layouts/shortcodes/m68k/size.html diff --git a/content/asm/68000/_index.html b/content/asm/68000/_index.html new file mode 100644 index 00000000..7444f328 --- /dev/null +++ b/content/asm/68000/_index.html @@ -0,0 +1,20 @@ +--- +type: "bookTitle" +title: "68000 Assembly Language" +linkTitle: "68000 Assembly" +weight: 20 +categories: + - microprocessor + - book +book: + title: "68000 Microprocessor Family" + subTitle: "Notes about assembly language" + author: "Peter Mount, Area51.dev & Contributors" + copyright: "CC BY-SA" +--- +
+

+ This section covers assembly language for the 68000 Microprocessor family. +

+
+ diff --git a/content/asm/68000/opcodes/_index.html b/content/asm/68000/opcodes/_index.html new file mode 100644 index 00000000..1cdc65b7 --- /dev/null +++ b/content/asm/68000/opcodes/_index.html @@ -0,0 +1,10 @@ +--- +type: "manual" +title: "Opcodes" +linkTitle: "Instruction Set" +weight: 20 +description: "Instruction Set" +--- +

+ In this section we cover every available instruction for the 68000 family of processors. +

diff --git a/content/asm/68000/opcodes/conventions/_index.html b/content/asm/68000/opcodes/conventions/_index.html new file mode 100644 index 00000000..8c5f439d --- /dev/null +++ b/content/asm/68000/opcodes/conventions/_index.html @@ -0,0 +1,141 @@ +--- +type: "manual" +title: "Conventions" +linkTitle: "Conventions" +weight: 1 +description: "The conventions used in the documentation" +--- + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operands
AnAny Address Register n (example: A3 is address register 3)
DnAny Data Register n (example: D5 is data register 5)
RnAny data or address registerData register D7–D0, used during compare.
PCProgram counter
SRStatus register
CCRCondition codes register (low order byte of SR)
SSPSupervisor stack pointer
USPUser stack pointer
SPActive stack pointer (same as A7)
XExtend flag of the CCR
NNegative flag of the CCR
ZZero flag of the CCR
VOverflow flag of the CCR
CCarry flag of the CCR
Immediate dataImmediate data for the instruction
dAddress displacement
SourceDestination Source
contentsDestination contents
VectorLocation of exception vector
eaAny valid effective address
Notation
+Arithmetic addition or postincrement indicator +
–Arithmetic subtraction or predecrement indicator +
×Arithmetic multiplication +
÷Arithmetic division or conjunction symbol +
~Invert; operand is logically complemented. +
ΛLogical AND +
VLogical OR +
⊕Logical exclusive OR +
→Source operand is moved to destination operand. +
←→Two operands are exchanged. +
+
\ No newline at end of file diff --git a/content/asm/68000/opcodes/math/_index.html b/content/asm/68000/opcodes/math/_index.html new file mode 100644 index 00000000..62bce5c9 --- /dev/null +++ b/content/asm/68000/opcodes/math/_index.html @@ -0,0 +1,7 @@ +--- +type: "manual" +title: "Arithmetic" +linkTitle: "Arithmetic" +weight: 3 +description: Arithmetic operations +--- diff --git a/content/asm/68000/opcodes/math/abcd/_index.html b/content/asm/68000/opcodes/math/abcd/_index.html new file mode 100644 index 00000000..c556b54a --- /dev/null +++ b/content/asm/68000/opcodes/math/abcd/_index.html @@ -0,0 +1,53 @@ +--- +type: "manual" +title: "ABCD Add Decimal with Extend" +linkTitle: "ABCD" +#weight: 3 +description: "ABCD Add Decimal with Extend" +tags: + - 68000 instruction +--- + + {{< m68k/block title="Operation" >}} + \(Source_{10} + Destination_{10} + X \longrightarrow Destination\) + {{< /m68k/block >}} + + {{< m68k/block title="Syntax" >}} + ABCD Dy, Dx
+ ABCD -(Ay), -(Ax) + {{< /m68k/block >}} + + {{< m68k/size byte="1" >}} + + {{< m68k/block title="Description" >}} +

+ Adds the source operand to the destination operand along with the extend bit, + and stores the result in the destination location. The addition is performed using binary-coded decimal arithmetic. + The operands, which are packed binary-coded decimal + numbers, can be addressed in two different ways: +

+
+
Data Register to Data Register
+
The operands are contained in the data registers specified in the instruction
+
Memory to Memory
+
+ The operands are addressed with the predecrement addressing mode using the address registers specified in the + instruction. +
+
+

This operation is a byte operation only.

+ {{< /m68k/block >}} + + {{< m68k/flags + X="Set the same as the carry bit" + Z="Cleared if the result is nonzero; unchanged otherwise" + C="Set if a decimal carry was generated; cleared otherwise" + >}} +
+ Normally, the Z condition code bit is set via programming before the start of an operation. + This allows successful tests for zero results upon completion of multiple-precision operations. +
+ {{< /m68k/flags >}} + + {{< m68k/instruction def="1100R10000Mr">}} +
diff --git a/content/asm/68000/opcodes/math/addx/_index.html b/content/asm/68000/opcodes/math/addx/_index.html new file mode 100644 index 00000000..1bd8a2ec --- /dev/null +++ b/content/asm/68000/opcodes/math/addx/_index.html @@ -0,0 +1,64 @@ +--- +type: "manual" +title: "ADDX" +linkTitle: "ADDX" +#weight: 3 +description: "ADD Extended" +tags: + - 68000 instruction +m68k: + operation: "Source + Destination + X \\longrightarrow Destination" + asm: + - "ADDX Dy, Dx" + - "ADDX -(Ay), -(Ax)" + size: + - Byte + - Word + - Long + flags: + "x": "Set the same as the carry bit" +--- + + {{< m68k/block title="Operation" >}} + \(Source + Destination + X \longrightarrow Destination\) + {{< /m68k/block >}} + + {{< m68k/block title="Syntax" >}} + ADDX Dy, Dx
+ ADDX -(Ay), -(Ax)
+ {{< /m68k/block >}} + + {{< m68k/size byte="1" word="1" long="1" >}} + + {{< m68k/block title="Description" >}} +

+ Adds the source operand and the extend bit to the destination operand and + stores the result in the destination location. The operands can be addressed in two + different ways: +

+
+
Data register to data register
+
The data registers specified in the instruction contain the operands.
+
Memory to memory
+
The address registers specified in the instruction address the operands using the predecrement addressing mode.
+
+

+ The size of the operation can be specified as byte, word, or long. +

+ {{< /m68k/block >}} + + {{< m68k/flags + X="Set the same as the carry bit" + N="Set if the result is negative; cleared otherwise" + Z="Cleared if the result is nonzero; unchanged otherwise" + V="Set if an overflow occurs; cleared otherwise" + C="Set if a carry is generated; cleared otherwise" + >}} +
+ Normally, the Z condition code bit is set via programming before the start of an operation. + This allows successful tests for zero results upon completion of multiple-precision operations. +
+ {{< /m68k/flags >}} + + {{< m68k/instruction def="1101R1S00Mr">}} +
diff --git a/themes/area51/assets/scss/custom/table.scss b/themes/area51/assets/scss/custom/table.scss index f75b592a..c01c0664 100644 --- a/themes/area51/assets/scss/custom/table.scss +++ b/themes/area51/assets/scss/custom/table.scss @@ -397,6 +397,14 @@ table.diskMap { } } + td.font-normal { + font-size: 100% !important; + } + + td.align-top { + vertical-align: top; + } + td:first-child, td.blrtb, td.blrt, diff --git a/themes/area51/layouts/shortcodes/m68k/block.html b/themes/area51/layouts/shortcodes/m68k/block.html new file mode 100644 index 00000000..57143d78 --- /dev/null +++ b/themes/area51/layouts/shortcodes/m68k/block.html @@ -0,0 +1,4 @@ + + {{$.Get "title"}}: + {{$.Inner}} + diff --git a/themes/area51/layouts/shortcodes/m68k/flags.html b/themes/area51/layouts/shortcodes/m68k/flags.html new file mode 100644 index 00000000..18c243fc --- /dev/null +++ b/themes/area51/layouts/shortcodes/m68k/flags.html @@ -0,0 +1,31 @@ + + Flags: + + + + + + + + + + + + + + + + + + + + +
XNZVC
{{- with $.Get "X"}}*{{else}}U{{end -}}{{- with $.Get "N"}}*{{else}}U{{end -}}{{- with $.Get "Z"}}*{{else}}U{{end -}}{{- with $.Get "V"}}*{{else}}U{{end -}}{{- with $.Get "C"}}*{{else}}U{{end -}}
+
X {{with $.Get "X"}}{{.}}{{else}}Undefined{{end -}}
+
N {{with $.Get "N"}}{{.}}{{else}}Undefined{{end -}}
+
Z {{with $.Get "Z"}}{{.}}{{else}}Undefined{{end -}}
+
V {{with $.Get "V"}}{{.}}{{else}}Undefined{{end -}}
+
C {{with $.Get "C"}}{{.}}{{else}}Undefined{{end -}}
+ {{.Inner}} + + diff --git a/themes/area51/layouts/shortcodes/m68k/instruction.html b/themes/area51/layouts/shortcodes/m68k/instruction.html new file mode 100644 index 00000000..6bc35d0e --- /dev/null +++ b/themes/area51/layouts/shortcodes/m68k/instruction.html @@ -0,0 +1,110 @@ +{{- define "m68klookuptable" -}} + + + + + + + + {{- range $k, $v := $ -}} + {{- if ne $k "field" -}} + + {{- end -}} + {{- end -}} + +
{{$.field}}Operation
{{$k}}{{$v}}
+{{- end -}} + +{{- with $.Get "def" -}} +{{- $scratch := newScratch -}} +Format: + + + + + + + + + + + {{- range split . "" -}} + {{- if eq . "0" -}} + {{- else if eq . "1" -}} + {{- else if eq . "d" -}} + {{- else if eq . "E" -}} + + + {{- else if eq . "M" -}} + {{- else if eq . "m" -}} + {{- else if eq . "R" -}} + {{- else if eq . "r" -}} + {{- else if eq . "S" -}} + {{- else -}} + {{- end -}} + {{- $scratch.Set . 1 -}} + {{- end -}} + + +
1514131211109876543210
01RegisterE/A ModeE/A RegisterR/MO/MRxRySize{{.}}
+ + +{{- with $scratch.Get "R" -}} + + + + Rx the source register. + + +{{- end -}} + +{{- with $scratch.Get "r" -}} + + + + Ry the destination register. + + +{{- end -}} + +{{- with $scratch.Get "M" -}} + + + + R/M Specifies the operand addressing mode: + {{- template "m68klookuptable" (dict "field" "R/M" "0" "Uses data registers" "1" "Uses address registers or memory") -}} + + +{{- end -}} + +{{- with $scratch.Get "m" -}} + + + + O/M the operation Mode: + {{- template "m68klookuptable" (dict "field" "O/M" "0" "Result into register" "1" "Result into address") -}} + + +{{- end -}} + +{{- with $scratch.Get "S" -}} + + + + Size the size of the operation: + {{- template "m68klookuptable" (dict "field" "Size" "00" "Byte" "01" "Word" "10" "Long") -}} + + +{{- end -}} + +{{- with $scratch.Get "E" -}} + + + + O/M the operation Mode: + {{- template "m68klookuptable" (dict "field" "O/M" "0" "Result into register" "1" "Result into address") -}} + + +{{- end -}} + +{{- end -}} diff --git a/themes/area51/layouts/shortcodes/m68k/size.html b/themes/area51/layouts/shortcodes/m68k/size.html new file mode 100644 index 00000000..12a32da0 --- /dev/null +++ b/themes/area51/layouts/shortcodes/m68k/size.html @@ -0,0 +1,9 @@ +{{- $s := slice -}} +{{- with $.Get "byte"}}{{$s = $s | append "Byte"}}{{end -}} +{{- with $.Get "word"}}{{$s = $s | append "Word"}}{{end -}} +{{- with $.Get "long"}}{{$s = $s | append "Long"}}{{end -}} + + + Data Size + {{delimit $s ", "}} +