diff --git a/magma/fromverilog.py b/magma/fromverilog.py
index f1e7d4073c..6a54cec7cd 100755
--- a/magma/fromverilog.py
+++ b/magma/fromverilog.py
@@ -107,7 +107,7 @@ def ParseVerilogModule(node, type_map):
 
     return node.name, args
 
-def FromVerilog(source, func, type_map, module=None):
+def FromVerilog(source, func, type_map, target_modules=None):
     parser = VerilogParser()
 
     ast = parser.parse(source)
@@ -117,11 +117,14 @@ def FromVerilog(source, func, type_map, module=None):
     v.visit(ast)
 
     if func == DefineCircuit:
-        # only allow a single verilog module
-        assert len(v.nodes) == 1
+        # only allow a single verilog module unless we're only defining one
+        # circuit (only one module in target_modules), otherwise, they would
+        # all use the same source, so if they are compiled together, there will
+        # be multiple definitions of the same verilog module
+        assert len(v.nodes) == 1 or len(target_modules) == 1
     modules = []
     for node in v.nodes:
-        if module is not None and node.name != module:
+        if target_modules is not None and node.name not in target_modules:
             continue
         try:
             name, args = ParseVerilogModule(node, type_map)
@@ -130,23 +133,21 @@ def FromVerilog(source, func, type_map, module=None):
                 # inline source
                 circuit.verilogFile = source
                 EndDefine()
-            if module is not None:
-                assert node.name == module
-                return circuit
             modules.append(circuit)
         except Exception as e:
             logger.warning(f"Could not parse module {node.name} ({e}), "
                            f"skipping")
-    if module is not None:
-        raise Exception(f"Could not find module {module}")
-
+    if not modules:
+        logger.warning(f"Did not import any modules from verilog, either could "
+                       f"not parse or could not find any of the target_modules "
+                       f"({target_modules})")
     return modules
 
-def FromVerilogFile(file, func, type_map, module=None):
+def FromVerilogFile(file, func, type_map, target_modules=None):
     if file is None:
         return None
     verilog = open(file).read()
-    return FromVerilog(verilog, func, type_map, module)
+    return FromVerilog(verilog, func, type_map, target_modules)
 
 def FromTemplatedVerilog(templatedverilog, func, type_map, **kwargs):
     verilog = Template(templatedverilog).render(**kwargs)
@@ -162,8 +163,8 @@ def FromTemplatedVerilogFile(file, func, type_map, **kwargs):
 def DeclareFromVerilog(source, type_map={}):
     return FromVerilog(source, DeclareCircuit, type_map)
 
-def DeclareFromVerilogFile(file, module=None, type_map={}):
-    return FromVerilogFile(file, DeclareCircuit, type_map, module)
+def DeclareFromVerilogFile(file, target_modules=None, type_map={}):
+    return FromVerilogFile(file, DeclareCircuit, type_map, target_modules)
 
 def DeclareFromTemplatedVerilog(source, type_map={}, **kwargs):
     return FromTemplatedVerilog(source, DeclareCircuit, type_map, **kwargs)
@@ -172,11 +173,11 @@ def DeclareFromTemplatedVerilogFile(file, type_map={}, **kwargs):
     return FromTemplatedVerilogFile(file, DeclareCircuit, type_map, **kwargs)
 
 
-def DefineFromVerilog(source, type_map={}):
-    return FromVerilog(source, DefineCircuit, type_map)
+def DefineFromVerilog(source, type_map={}, target_modules=None):
+    return FromVerilog(source, DefineCircuit, type_map, target_modules)
 
-def DefineFromVerilogFile(file, module=None, type_map={}):
-    return FromVerilogFile(file, DefineCircuit, type_map, module)
+def DefineFromVerilogFile(file, target_modules=None, type_map={}):
+    return FromVerilogFile(file, DefineCircuit, type_map, target_modules)
 
 def DefineFromTemplatedVerilog(source, type_map={}, **kwargs):
     return FromTemplatedVerilog(source, DefineCircuit, type_map, **kwargs)
diff --git a/tests/test_verilog/test_from_file.py b/tests/test_verilog/test_from_file.py
index 171b408167..f27ce773f0 100644
--- a/tests/test_verilog/test_from_file.py
+++ b/tests/test_verilog/test_from_file.py
@@ -13,10 +13,7 @@ def check_port(definition, port, type, direction):
     else:
         raise NotImplementedError(direction)
 
-def test():
-    file_path = os.path.dirname(__file__)
-    RXMOD = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"))[0]
-
+def check_rxmod(RXMOD):
     check_port(RXMOD, "RX", m.BitType, "input")
     check_port(RXMOD, "CLK", m.BitType, "input")
     check_port(RXMOD, "data", m.ArrayType, "output")
@@ -24,17 +21,19 @@ def test():
 
     m.compile("build/test_rxmod", RXMOD)
     assert m.testing.check_files_equal(__file__, "build/test_rxmod.v",
-            "gold/test_rxmod.v")
+            "gold/test_rxmod.v")    
 
-def test_module_arg():
+def test_basic():
     file_path = os.path.dirname(__file__)
-    RXMOD = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"), "RXMOD")
+    RXMOD = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"))[0]
 
-    check_port(RXMOD, "RX", m.BitType, "input")
-    check_port(RXMOD, "CLK", m.BitType, "input")
-    check_port(RXMOD, "data", m.ArrayType, "output")
-    check_port(RXMOD, "valid", m.BitType, "output")
+    check_rxmod(RXMOD)
+
+
+def test_target_modules_arg():
+    file_path = os.path.dirname(__file__)
+    circuits = m.DefineFromVerilogFile(os.path.join(file_path, "rxmod.v"), ["RXMOD"])
+    assert len(circuits) == 1
+    assert circuits[0].name == "RXMOD"
 
-    m.compile("build/test_rxmod_module_arg", RXMOD)
-    assert m.testing.check_files_equal(__file__, "build/test_rxmod_module_arg.v",
-            "gold/test_rxmod.v")
+    check_rxmod(circuits[0])