diff --git a/magma/backend/verilog.py b/magma/backend/verilog.py
index 6985b1632d..67e12f9f8e 100644
--- a/magma/backend/verilog.py
+++ b/magma/backend/verilog.py
@@ -112,7 +112,7 @@ def arg(k,v):
             # find the output connected to v
             w = v.value()
             if not w:
-                logging.warning(f'{str(self.defn.name)}.{str(type(self).name)}_{self.name}.{str(v)} not connected')
+                logging.warning(f'{v.debug_name} not connected')
                 continue
             v = w
         if isinstance(k, IntegerTypes):
diff --git a/magma/circuit.py b/magma/circuit.py
index d598d8d6cd..6830f80fb9 100644
--- a/magma/circuit.py
+++ b/magma/circuit.py
@@ -6,7 +6,7 @@
     from functools import reduce
 from . import cache_definition
 import operator
-from collections import namedtuple
+from collections import namedtuple, Counter
 from .interface import *
 from .wire import *
 from .t import Flip
@@ -240,7 +240,7 @@ def debug_name(self):
         defn_str = ""
         if hasattr(self, 'defn') and self.defn is not None:
             defn_str = str(self.defn.name)
-        return f"{defn_str}_{self.name}"
+        return f"{defn_str}.{self.name}"
 
     def __call__(input, *outputs, **kw):
         debug_info = get_callee_frame_info()
@@ -264,7 +264,7 @@ def __call__(input, *outputs, **kw):
                 i = getattr(input, key)
                 wire( value, getattr(input, key), debug_info)
             else:
-                report_wiring_warning('Circuit {} does not have input {}'.format(input.debug_name, key), debug_info)
+                report_wiring_warning('Instance {} does not have input {}'.format(input.debug_name, key), debug_info)
 
         o = input.interface.outputs()
         return o[0] if len(o) == 1 else tuple(o)
@@ -436,6 +436,7 @@ def __new__(metacls, name, bases, dct):
         self.firrtl = None
 
         self._instances = []
+        self.instanced_circuits_counter = Counter()
         self._is_definition = dct.get('is_definition', False)
         self.is_instance = False
 
@@ -466,11 +467,8 @@ def instances(self):
     #
     def place(cls, inst):
         if not inst.name:
-            inst.name = 'inst' + str(len(cls.instances))
-            # osnr's suggested name
-            #inst.name = 'inst' + str(len(cls.instances)) + '_' + inst.__class__.name
-            #print('naming circuit instance', inst.name)
-        #print('placing', inst, 'in', cls)
+            inst.name = f"{type(inst).name}_inst{str(cls.instanced_circuits_counter[type(inst).name])}"
+            cls.instanced_circuits_counter[type(inst).name] += 1
         inst.defn = cls
         inst.stack = inspect.stack()
         cls.instances.append(inst)
diff --git a/magma/t.py b/magma/t.py
index 49fe4fdb02..af4dcfe12b 100644
--- a/magma/t.py
+++ b/magma/t.py
@@ -63,7 +63,7 @@ def debug_name(self):
         if isinstance(self.name, DefnRef):
             defn_str = str(self.name.defn.name) + "."
         elif isinstance(self.name, InstRef):
-            inst_str = str(type(self.name.inst).name) + "_" + str(self.name.inst.name) + "."
+            inst_str = str(self.name.inst.name) + "."
             defn_str = str(self.name.inst.defn.name) + "."
         return f"{defn_str}{inst_str}{str(self)}"
 
diff --git a/tests/gold/basic_function_call.json b/tests/gold/basic_function_call.json
index a923036806..4f19fc7780 100644
--- a/tests/gold/basic_function_call.json
+++ b/tests/gold/basic_function_call.json
@@ -17,15 +17,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["self.O","Mux2_inst0.O"],
+          ["self.S","Mux2_inst0.S"]
         ]
       },
       "basic_function_call":{
@@ -35,14 +35,14 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "basic_func_inst0":{
             "modref":"global.basic_func"
           }
         },
         "connections":[
-          ["self.I","inst0.I"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I","basic_func_inst0.I"],
+          ["self.O","basic_func_inst0.O"],
+          ["self.S","basic_func_inst0.S"]
         ]
       }
     }
diff --git a/tests/gold/basic_function_call.v b/tests/gold/basic_function_call.v
index 9bbc086790..89ef46c5a8 100644
--- a/tests/gold/basic_function_call.v
+++ b/tests/gold/basic_function_call.v
@@ -1,12 +1,12 @@
 module basic_func (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  Mux2_inst0_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(Mux2_inst0_O));
+assign O = Mux2_inst0_O;
 endmodule
 
 module basic_function_call (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-basic_func inst0 (.I(I), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  basic_func_inst0_O;
+basic_func basic_func_inst0 (.I(I), .S(S), .O(basic_func_inst0_O));
+assign O = basic_func_inst0_O;
 endmodule
 
diff --git a/tests/gold/if_statement_basic.json b/tests/gold/if_statement_basic.json
index f6123f4106..ad4e6c231a 100644
--- a/tests/gold/if_statement_basic.json
+++ b/tests/gold/if_statement_basic.json
@@ -17,15 +17,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["self.O","Mux2_inst0.O"],
+          ["self.S","Mux2_inst0.S"]
         ]
       }
     }
diff --git a/tests/gold/if_statement_basic.v b/tests/gold/if_statement_basic.v
index 8ae0f243cd..1612fd548b 100644
--- a/tests/gold/if_statement_basic.v
+++ b/tests/gold/if_statement_basic.v
@@ -1,6 +1,6 @@
 module basic_if (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  Mux2_inst0_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(Mux2_inst0_O));
+assign O = Mux2_inst0_O;
 endmodule
 
diff --git a/tests/gold/if_statement_nested.json b/tests/gold/if_statement_nested.json
index d8639d87a6..890d0fccb5 100644
--- a/tests/gold/if_statement_nested.json
+++ b/tests/gold/if_statement_nested.json
@@ -17,27 +17,27 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           },
-          "inst1":{
+          "Mux2_inst1":{
             "modref":"global.Mux2"
           },
-          "inst2":{
+          "Mux2_inst2":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.3","inst0.I0"],
-          ["self.I.2","inst0.I1"],
-          ["inst2.I0","inst0.O"],
-          ["self.S.1","inst0.S"],
-          ["self.I.1","inst1.I0"],
-          ["self.I.0","inst1.I1"],
-          ["inst2.I1","inst1.O"],
-          ["self.S.1","inst1.S"],
-          ["self.O","inst2.O"],
-          ["self.S.0","inst2.S"]
+          ["self.I.3","Mux2_inst0.I0"],
+          ["self.I.2","Mux2_inst0.I1"],
+          ["Mux2_inst2.I0","Mux2_inst0.O"],
+          ["self.S.1","Mux2_inst0.S"],
+          ["self.I.1","Mux2_inst1.I0"],
+          ["self.I.0","Mux2_inst1.I1"],
+          ["Mux2_inst2.I1","Mux2_inst1.O"],
+          ["self.S.1","Mux2_inst1.S"],
+          ["self.O","Mux2_inst2.O"],
+          ["self.S.0","Mux2_inst2.S"]
         ]
       }
     }
diff --git a/tests/gold/if_statement_nested.v b/tests/gold/if_statement_nested.v
index 2c06f27381..17920505c0 100644
--- a/tests/gold/if_statement_nested.v
+++ b/tests/gold/if_statement_nested.v
@@ -1,10 +1,10 @@
 module if_statement_nested (input [3:0] I, input [1:0] S, output  O);
-wire  inst0_O;
-wire  inst1_O;
-wire  inst2_O;
-Mux2 inst0 (.I0(I[3]), .I1(I[2]), .S(S[1]), .O(inst0_O));
-Mux2 inst1 (.I0(I[1]), .I1(I[0]), .S(S[1]), .O(inst1_O));
-Mux2 inst2 (.I0(inst0_O), .I1(inst1_O), .S(S[0]), .O(inst2_O));
-assign O = inst2_O;
+wire  Mux2_inst0_O;
+wire  Mux2_inst1_O;
+wire  Mux2_inst2_O;
+Mux2 Mux2_inst0 (.I0(I[3]), .I1(I[2]), .S(S[1]), .O(Mux2_inst0_O));
+Mux2 Mux2_inst1 (.I0(I[1]), .I1(I[0]), .S(S[1]), .O(Mux2_inst1_O));
+Mux2 Mux2_inst2 (.I0(Mux2_inst0_O), .I1(Mux2_inst1_O), .S(S[0]), .O(Mux2_inst2_O));
+assign O = Mux2_inst2_O;
 endmodule
 
diff --git a/tests/gold/return_tuple.json b/tests/gold/return_tuple.json
index 3e6767dfef..da9d111ee0 100644
--- a/tests/gold/return_tuple.json
+++ b/tests/gold/return_tuple.json
@@ -15,4 +15,4 @@
     }
   }
 }
-}
+}
\ No newline at end of file
diff --git a/tests/gold/simple_circuit_1.json b/tests/gold/simple_circuit_1.json
index 340dafb231..7dc49706e1 100644
--- a/tests/gold/simple_circuit_1.json
+++ b/tests/gold/simple_circuit_1.json
@@ -8,13 +8,13 @@
           ["c","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "logic_inst0":{
             "modref":"global.logic"
           }
         },
         "connections":[
-          ["self.c","inst0.O0"],
-          ["self.a","inst0.a"]
+          ["self.c","logic_inst0.O0"],
+          ["self.a","logic_inst0.a"]
         ]
       },
       "Mux2":{
@@ -47,6 +47,9 @@
           ["O0","Bit"]
         ]],
         "instances":{
+          "Mux2_inst0":{
+            "modref":"global.Mux2"
+          },
           "bit_const_0_None":{
             "modref":"corebit.const",
             "modargs":{"value":["Bool",false]}
@@ -55,20 +58,17 @@
             "modref":"corebit.const",
             "modargs":{"value":["Bool",true]}
           },
-          "inst0":{
+          "eq_inst0":{
             "modref":"global.eq"
-          },
-          "inst1":{
-            "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["inst0.I1","bit_const_0_None.out"],
-          ["inst1.I0","bit_const_0_None.out"],
-          ["inst1.I1","bit_const_1_None.out"],
-          ["self.a","inst0.I0"],
-          ["inst1.S","inst0.O"],
-          ["self.O0","inst1.O"]
+          ["bit_const_0_None.out","Mux2_inst0.I0"],
+          ["bit_const_1_None.out","Mux2_inst0.I1"],
+          ["self.O0","Mux2_inst0.O"],
+          ["eq_inst0.O","Mux2_inst0.S"],
+          ["eq_inst0.I1","bit_const_0_None.out"],
+          ["self.a","eq_inst0.I0"]
         ]
       }
     }
diff --git a/tests/gold/ternary.json b/tests/gold/ternary.json
index 209da6ef7d..c74e27e13b 100644
--- a/tests/gold/ternary.json
+++ b/tests/gold/ternary.json
@@ -17,15 +17,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["self.O","inst0.O"],
-          ["self.S","inst0.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["self.O","Mux2_inst0.O"],
+          ["self.S","Mux2_inst0.S"]
         ]
       }
     }
diff --git a/tests/gold/ternary.v b/tests/gold/ternary.v
index 716db0cde1..d084e8aed0 100644
--- a/tests/gold/ternary.v
+++ b/tests/gold/ternary.v
@@ -1,6 +1,6 @@
 module ternary (input [1:0] I, input  S, output  O);
-wire  inst0_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(inst0_O));
-assign O = inst0_O;
+wire  Mux2_inst0_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S), .O(Mux2_inst0_O));
+assign O = Mux2_inst0_O;
 endmodule
 
diff --git a/tests/gold/ternary_nested.json b/tests/gold/ternary_nested.json
index 28dbfa9c96..54e5191f26 100644
--- a/tests/gold/ternary_nested.json
+++ b/tests/gold/ternary_nested.json
@@ -17,21 +17,21 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           },
-          "inst1":{
+          "Mux2_inst1":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.2","inst0.I0"],
-          ["self.I.1","inst0.I1"],
-          ["inst1.I0","inst0.O"],
-          ["self.S.1","inst0.S"],
-          ["self.I.0","inst1.I1"],
-          ["self.O","inst1.O"],
-          ["self.S.0","inst1.S"]
+          ["self.I.2","Mux2_inst0.I0"],
+          ["self.I.1","Mux2_inst0.I1"],
+          ["Mux2_inst1.I0","Mux2_inst0.O"],
+          ["self.S.1","Mux2_inst0.S"],
+          ["self.I.0","Mux2_inst1.I1"],
+          ["self.O","Mux2_inst1.O"],
+          ["self.S.0","Mux2_inst1.S"]
         ]
       }
     }
diff --git a/tests/gold/ternary_nested.v b/tests/gold/ternary_nested.v
index c505a33db7..533c090da5 100644
--- a/tests/gold/ternary_nested.v
+++ b/tests/gold/ternary_nested.v
@@ -1,8 +1,8 @@
 module ternary_nested (input [3:0] I, input [1:0] S, output  O);
-wire  inst0_O;
-wire  inst1_O;
-Mux2 inst0 (.I0(I[2]), .I1(I[1]), .S(S[1]), .O(inst0_O));
-Mux2 inst1 (.I0(inst0_O), .I1(I[0]), .S(S[0]), .O(inst1_O));
-assign O = inst1_O;
+wire  Mux2_inst0_O;
+wire  Mux2_inst1_O;
+Mux2 Mux2_inst0 (.I0(I[2]), .I1(I[1]), .S(S[1]), .O(Mux2_inst0_O));
+Mux2 Mux2_inst1 (.I0(Mux2_inst0_O), .I1(I[0]), .S(S[0]), .O(Mux2_inst1_O));
+assign O = Mux2_inst1_O;
 endmodule
 
diff --git a/tests/gold/ternary_nested2.json b/tests/gold/ternary_nested2.json
index 6f6705e4fe..cf087834f1 100644
--- a/tests/gold/ternary_nested2.json
+++ b/tests/gold/ternary_nested2.json
@@ -17,21 +17,21 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "Mux2_inst0":{
             "modref":"global.Mux2"
           },
-          "inst1":{
+          "Mux2_inst1":{
             "modref":"global.Mux2"
           }
         },
         "connections":[
-          ["self.I.1","inst0.I0"],
-          ["self.I.0","inst0.I1"],
-          ["inst1.I1","inst0.O"],
-          ["self.S.0","inst0.S"],
-          ["self.I.2","inst1.I0"],
-          ["self.O","inst1.O"],
-          ["self.S.1","inst1.S"]
+          ["self.I.1","Mux2_inst0.I0"],
+          ["self.I.0","Mux2_inst0.I1"],
+          ["Mux2_inst1.I1","Mux2_inst0.O"],
+          ["self.S.0","Mux2_inst0.S"],
+          ["self.I.2","Mux2_inst1.I0"],
+          ["self.O","Mux2_inst1.O"],
+          ["self.S.1","Mux2_inst1.S"]
         ]
       }
     }
diff --git a/tests/gold/ternary_nested2.v b/tests/gold/ternary_nested2.v
index b19d439ce2..8e0cf2618a 100644
--- a/tests/gold/ternary_nested2.v
+++ b/tests/gold/ternary_nested2.v
@@ -1,8 +1,8 @@
 module ternary_nested2 (input [3:0] I, input [1:0] S, output  O);
-wire  inst0_O;
-wire  inst1_O;
-Mux2 inst0 (.I0(I[1]), .I1(I[0]), .S(S[0]), .O(inst0_O));
-Mux2 inst1 (.I0(I[2]), .I1(inst0_O), .S(S[1]), .O(inst1_O));
-assign O = inst1_O;
+wire  Mux2_inst0_O;
+wire  Mux2_inst1_O;
+Mux2 Mux2_inst0 (.I0(I[1]), .I1(I[0]), .S(S[0]), .O(Mux2_inst0_O));
+Mux2 Mux2_inst1 (.I0(I[2]), .I1(Mux2_inst0_O), .S(S[1]), .O(Mux2_inst1_O));
+assign O = Mux2_inst1_O;
 endmodule
 
diff --git a/tests/gold/test_assign_operator2_3_coreir.json b/tests/gold/test_assign_operator2_3_coreir.json
index 39f2074a13..486b0f5a61 100644
--- a/tests/gold/test_assign_operator2_3_coreir.json
+++ b/tests/gold/test_assign_operator2_3_coreir.json
@@ -16,13 +16,13 @@
           ["c",["Array",3,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "And3_inst0":{
             "modref":"global.And3"
           }
         },
         "connections":[
-          ["inst0.O","inst0.I0"],
-          ["self.a","inst0.I1"],
+          ["And3_inst0.O","And3_inst0.I0"],
+          ["self.a","And3_inst0.I1"],
           ["self.c","self.b"]
         ]
       }
diff --git a/tests/gold/test_assign_operator2_3_verilog.v b/tests/gold/test_assign_operator2_3_verilog.v
index 5d4e3c26ca..235247117e 100644
--- a/tests/gold/test_assign_operator2_3_verilog.v
+++ b/tests/gold/test_assign_operator2_3_verilog.v
@@ -1,6 +1,6 @@
 module test_assign_operator2_3_verilog (input [2:0] a, input [2:0] b, output [2:0] c);
-wire [2:0] inst0_O;
-And3 inst0 (.I0(inst0_O), .I1(a), .O(inst0_O));
+wire [2:0] And3_inst0_O;
+And3 And3_inst0 (.I0(And3_inst0_O), .I1(a), .O(And3_inst0_O));
 assign c = b;
 endmodule
 
diff --git a/tests/gold/test_assign_operator2_None_coreir.json b/tests/gold/test_assign_operator2_None_coreir.json
index d57bd07487..6f2c2e82da 100644
--- a/tests/gold/test_assign_operator2_None_coreir.json
+++ b/tests/gold/test_assign_operator2_None_coreir.json
@@ -16,13 +16,13 @@
           ["c","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "AndNone_inst0":{
             "modref":"global.AndNone"
           }
         },
         "connections":[
-          ["inst0.O","inst0.I0"],
-          ["self.a","inst0.I1"],
+          ["AndNone_inst0.O","AndNone_inst0.I0"],
+          ["self.a","AndNone_inst0.I1"],
           ["self.c","self.b"]
         ]
       }
diff --git a/tests/gold/test_assign_operator2_None_verilog.v b/tests/gold/test_assign_operator2_None_verilog.v
index 1e1e0067ba..2429c453a1 100644
--- a/tests/gold/test_assign_operator2_None_verilog.v
+++ b/tests/gold/test_assign_operator2_None_verilog.v
@@ -1,6 +1,6 @@
 module test_assign_operator2_None_verilog (input  a, input  b, output  c);
-wire  inst0_O;
-AndNone inst0 (.I0(inst0_O), .I1(a), .O(inst0_O));
+wire  AndNone_inst0_O;
+AndNone AndNone_inst0 (.I0(AndNone_inst0_O), .I1(a), .O(AndNone_inst0_O));
 assign c = b;
 endmodule
 
diff --git a/tests/gold/test_assign_operator_3_coreir.json b/tests/gold/test_assign_operator_3_coreir.json
index b5fa32f9ee..47a75dfedc 100644
--- a/tests/gold/test_assign_operator_3_coreir.json
+++ b/tests/gold/test_assign_operator_3_coreir.json
@@ -16,14 +16,14 @@
           ["c",["Array",3,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "And3_inst0":{
             "modref":"global.And3"
           }
         },
         "connections":[
-          ["self.a","inst0.I0"],
-          ["self.b","inst0.I1"],
-          ["self.c","inst0.O"]
+          ["self.a","And3_inst0.I0"],
+          ["self.b","And3_inst0.I1"],
+          ["self.c","And3_inst0.O"]
         ]
       }
     }
diff --git a/tests/gold/test_assign_operator_3_verilog.v b/tests/gold/test_assign_operator_3_verilog.v
index 35a1794797..b0aaf0f156 100644
--- a/tests/gold/test_assign_operator_3_verilog.v
+++ b/tests/gold/test_assign_operator_3_verilog.v
@@ -1,6 +1,6 @@
 module test_assign_operator_3_verilog (input [2:0] a, input [2:0] b, output [2:0] c);
-wire [2:0] inst0_O;
-And3 inst0 (.I0(a), .I1(b), .O(inst0_O));
-assign c = inst0_O;
+wire [2:0] And3_inst0_O;
+And3 And3_inst0 (.I0(a), .I1(b), .O(And3_inst0_O));
+assign c = And3_inst0_O;
 endmodule
 
diff --git a/tests/gold/test_assign_operator_None_coreir.json b/tests/gold/test_assign_operator_None_coreir.json
index f913151931..63b6c2aa64 100644
--- a/tests/gold/test_assign_operator_None_coreir.json
+++ b/tests/gold/test_assign_operator_None_coreir.json
@@ -16,14 +16,14 @@
           ["c","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "AndNone_inst0":{
             "modref":"global.AndNone"
           }
         },
         "connections":[
-          ["self.a","inst0.I0"],
-          ["self.b","inst0.I1"],
-          ["self.c","inst0.O"]
+          ["self.a","AndNone_inst0.I0"],
+          ["self.b","AndNone_inst0.I1"],
+          ["self.c","AndNone_inst0.O"]
         ]
       }
     }
diff --git a/tests/gold/test_assign_operator_None_verilog.v b/tests/gold/test_assign_operator_None_verilog.v
index 25e1e332f6..f3015eab4d 100644
--- a/tests/gold/test_assign_operator_None_verilog.v
+++ b/tests/gold/test_assign_operator_None_verilog.v
@@ -1,6 +1,6 @@
 module test_assign_operator_None_verilog (input  a, input  b, output  c);
-wire  inst0_O;
-AndNone inst0 (.I0(a), .I1(b), .O(inst0_O));
-assign c = inst0_O;
+wire  AndNone_inst0_O;
+AndNone AndNone_inst0 (.I0(a), .I1(b), .O(AndNone_inst0_O));
+assign c = AndNone_inst0_O;
 endmodule
 
diff --git a/tests/gold/test_map_circuit.json b/tests/gold/test_map_circuit.json
index 89a5f48b19..1ae1101ef2 100644
--- a/tests/gold/test_map_circuit.json
+++ b/tests/gold/test_map_circuit.json
@@ -8,13 +8,13 @@
           ["c",["Array",10,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "logic_inst0":{
             "modref":"global.logic"
           }
         },
         "connections":[
-          ["self.c","inst0.O"],
-          ["self.a","inst0.a"]
+          ["self.c","logic_inst0.O"],
+          ["self.a","logic_inst0.a"]
         ]
       },
       "Not":{
@@ -38,58 +38,58 @@
           ["O",["Array",10,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "Not_inst0":{
             "modref":"global.Not"
           },
-          "inst1":{
+          "Not_inst1":{
             "modref":"global.Not"
           },
-          "inst2":{
+          "Not_inst2":{
             "modref":"global.Not"
           },
-          "inst3":{
+          "Not_inst3":{
             "modref":"global.Not"
           },
-          "inst4":{
+          "Not_inst4":{
             "modref":"global.Not"
           },
-          "inst5":{
+          "Not_inst5":{
             "modref":"global.Not"
           },
-          "inst6":{
+          "Not_inst6":{
             "modref":"global.Not"
           },
-          "inst7":{
+          "Not_inst7":{
             "modref":"global.Not"
           },
-          "inst8":{
+          "Not_inst8":{
             "modref":"global.Not"
           },
-          "inst9":{
+          "Not_inst9":{
             "modref":"global.Not"
           }
         },
         "connections":[
-          ["self.a.0","inst0.I"],
-          ["self.O.0","inst0.O"],
-          ["self.a.1","inst1.I"],
-          ["self.O.1","inst1.O"],
-          ["self.a.2","inst2.I"],
-          ["self.O.2","inst2.O"],
-          ["self.a.3","inst3.I"],
-          ["self.O.3","inst3.O"],
-          ["self.a.4","inst4.I"],
-          ["self.O.4","inst4.O"],
-          ["self.a.5","inst5.I"],
-          ["self.O.5","inst5.O"],
-          ["self.a.6","inst6.I"],
-          ["self.O.6","inst6.O"],
-          ["self.a.7","inst7.I"],
-          ["self.O.7","inst7.O"],
-          ["self.a.8","inst8.I"],
-          ["self.O.8","inst8.O"],
-          ["self.a.9","inst9.I"],
-          ["self.O.9","inst9.O"]
+          ["self.a.0","Not_inst0.I"],
+          ["self.O.0","Not_inst0.O"],
+          ["self.a.1","Not_inst1.I"],
+          ["self.O.1","Not_inst1.O"],
+          ["self.a.2","Not_inst2.I"],
+          ["self.O.2","Not_inst2.O"],
+          ["self.a.3","Not_inst3.I"],
+          ["self.O.3","Not_inst3.O"],
+          ["self.a.4","Not_inst4.I"],
+          ["self.O.4","Not_inst4.O"],
+          ["self.a.5","Not_inst5.I"],
+          ["self.O.5","Not_inst5.O"],
+          ["self.a.6","Not_inst6.I"],
+          ["self.O.6","Not_inst6.O"],
+          ["self.a.7","Not_inst7.I"],
+          ["self.O.7","Not_inst7.O"],
+          ["self.a.8","Not_inst8.I"],
+          ["self.O.8","Not_inst8.O"],
+          ["self.a.9","Not_inst9.I"],
+          ["self.O.9","Not_inst9.O"]
         ]
       }
     }
diff --git a/tests/gold/test_map_circuit.v b/tests/gold/test_map_circuit.v
index 5edc2e062b..a133f260b6 100644
--- a/tests/gold/test_map_circuit.v
+++ b/tests/gold/test_map_circuit.v
@@ -3,32 +3,32 @@ assign O = 1'b0;
 endmodule
 
 module logic (input [9:0] a, output [9:0] O);
-wire  inst0_O;
-wire  inst1_O;
-wire  inst2_O;
-wire  inst3_O;
-wire  inst4_O;
-wire  inst5_O;
-wire  inst6_O;
-wire  inst7_O;
-wire  inst8_O;
-wire  inst9_O;
-Not inst0 (.I(a[0]), .O(inst0_O));
-Not inst1 (.I(a[1]), .O(inst1_O));
-Not inst2 (.I(a[2]), .O(inst2_O));
-Not inst3 (.I(a[3]), .O(inst3_O));
-Not inst4 (.I(a[4]), .O(inst4_O));
-Not inst5 (.I(a[5]), .O(inst5_O));
-Not inst6 (.I(a[6]), .O(inst6_O));
-Not inst7 (.I(a[7]), .O(inst7_O));
-Not inst8 (.I(a[8]), .O(inst8_O));
-Not inst9 (.I(a[9]), .O(inst9_O));
-assign O = {inst9_O,inst8_O,inst7_O,inst6_O,inst5_O,inst4_O,inst3_O,inst2_O,inst1_O,inst0_O};
+wire  Not_inst0_O;
+wire  Not_inst1_O;
+wire  Not_inst2_O;
+wire  Not_inst3_O;
+wire  Not_inst4_O;
+wire  Not_inst5_O;
+wire  Not_inst6_O;
+wire  Not_inst7_O;
+wire  Not_inst8_O;
+wire  Not_inst9_O;
+Not Not_inst0 (.I(a[0]), .O(Not_inst0_O));
+Not Not_inst1 (.I(a[1]), .O(Not_inst1_O));
+Not Not_inst2 (.I(a[2]), .O(Not_inst2_O));
+Not Not_inst3 (.I(a[3]), .O(Not_inst3_O));
+Not Not_inst4 (.I(a[4]), .O(Not_inst4_O));
+Not Not_inst5 (.I(a[5]), .O(Not_inst5_O));
+Not Not_inst6 (.I(a[6]), .O(Not_inst6_O));
+Not Not_inst7 (.I(a[7]), .O(Not_inst7_O));
+Not Not_inst8 (.I(a[8]), .O(Not_inst8_O));
+Not Not_inst9 (.I(a[9]), .O(Not_inst9_O));
+assign O = {Not_inst9_O,Not_inst8_O,Not_inst7_O,Not_inst6_O,Not_inst5_O,Not_inst4_O,Not_inst3_O,Not_inst2_O,Not_inst1_O,Not_inst0_O};
 endmodule
 
 module Foo (input [9:0] a, output [9:0] c);
-wire [9:0] inst0_O;
-logic inst0 (.a(a), .O(inst0_O));
-assign c = inst0_O;
+wire [9:0] logic_inst0_O;
+logic logic_inst0 (.a(a), .O(logic_inst0_O));
+assign c = logic_inst0_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_add8cin.json b/tests/test_circuit/gold/test_add8cin.json
index e6f90da810..f8626cd7b6 100644
--- a/tests/test_circuit/gold/test_add8cin.json
+++ b/tests/test_circuit/gold/test_add8cin.json
@@ -14,28 +14,28 @@
             "modref":"corebit.const",
             "modargs":{"value":["Bool",false]}
           },
-          "inst0":{
+          "coreir_Add8_cin_inst0":{
             "genref":"coreir.add",
             "genargs":{"width":["Int",8]}
           },
-          "inst1":{
+          "coreir_Add8_cin_inst1":{
             "genref":"coreir.add",
             "genargs":{"width":["Int",8]}
           }
         },
         "connections":[
-          ["inst1.in0.0","bit_const_0_None.out"],
-          ["inst1.in0.1","bit_const_0_None.out"],
-          ["inst1.in0.2","bit_const_0_None.out"],
-          ["inst1.in0.3","bit_const_0_None.out"],
-          ["inst1.in0.4","bit_const_0_None.out"],
-          ["inst1.in0.5","bit_const_0_None.out"],
-          ["inst1.in0.6","bit_const_0_None.out"],
-          ["inst1.out","inst0.in0"],
-          ["self.I1","inst0.in1"],
-          ["self.O","inst0.out"],
-          ["self.CIN","inst1.in0.7"],
-          ["self.I0","inst1.in1"]
+          ["coreir_Add8_cin_inst1.in0.0","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.in0.1","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.in0.2","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.in0.3","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.in0.4","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.in0.5","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.in0.6","bit_const_0_None.out"],
+          ["coreir_Add8_cin_inst1.out","coreir_Add8_cin_inst0.in0"],
+          ["self.I1","coreir_Add8_cin_inst0.in1"],
+          ["self.O","coreir_Add8_cin_inst0.out"],
+          ["self.CIN","coreir_Add8_cin_inst1.in0.7"],
+          ["self.I0","coreir_Add8_cin_inst1.in1"]
         ]
       },
       "test":{
@@ -46,15 +46,15 @@
           ["O",["Array",8,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "Add8_cin_inst0":{
             "modref":"global.Add8_cin"
           }
         },
         "connections":[
-          ["self.CIN","inst0.CIN"],
-          ["self.I0","inst0.I0"],
-          ["self.I1","inst0.I1"],
-          ["self.O","inst0.O"]
+          ["self.CIN","Add8_cin_inst0.CIN"],
+          ["self.I0","Add8_cin_inst0.I0"],
+          ["self.I1","Add8_cin_inst0.I1"],
+          ["self.O","Add8_cin_inst0.O"]
         ]
       }
     }
diff --git a/tests/test_circuit/gold/test_anon_value_Array(2,Bit).json b/tests/test_circuit/gold/test_anon_value_Array(2,Bit).json
index 430357bdda..48b1342859 100644
--- a/tests/test_circuit/gold/test_anon_value_Array(2,Bit).json
+++ b/tests/test_circuit/gold/test_anon_value_Array(2,Bit).json
@@ -16,14 +16,14 @@
           ["O",["Array",2,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2"
           }
         },
         "connections":[
-          ["self.I0","inst0.I0"],
-          ["self.I1","inst0.I1"],
-          ["self.O","inst0.O"]
+          ["self.I0","And2_inst0.I0"],
+          ["self.I1","And2_inst0.I1"],
+          ["self.O","And2_inst0.O"]
         ]
       }
     }
diff --git a/tests/test_circuit/gold/test_anon_value_Array(2,Bit).v b/tests/test_circuit/gold/test_anon_value_Array(2,Bit).v
index 42af4fd886..058f17080a 100644
--- a/tests/test_circuit/gold/test_anon_value_Array(2,Bit).v
+++ b/tests/test_circuit/gold/test_anon_value_Array(2,Bit).v
@@ -1,6 +1,6 @@
 module main (input [1:0] I0, input [1:0] I1, output [1:0] O);
-wire [1:0] inst0_O;
-And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O));
-assign O = inst0_O;
+wire [1:0] And2_inst0_O;
+And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_anon_value_Bit.json b/tests/test_circuit/gold/test_anon_value_Bit.json
index d08f37d5be..1afbaed4d0 100644
--- a/tests/test_circuit/gold/test_anon_value_Bit.json
+++ b/tests/test_circuit/gold/test_anon_value_Bit.json
@@ -16,14 +16,14 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2"
           }
         },
         "connections":[
-          ["self.I0","inst0.I0"],
-          ["self.I1","inst0.I1"],
-          ["self.O","inst0.O"]
+          ["self.I0","And2_inst0.I0"],
+          ["self.I1","And2_inst0.I1"],
+          ["self.O","And2_inst0.O"]
         ]
       }
     }
diff --git a/tests/test_circuit/gold/test_anon_value_Bit.v b/tests/test_circuit/gold/test_anon_value_Bit.v
index 2534dfb8a1..f0fc76a4fb 100644
--- a/tests/test_circuit/gold/test_anon_value_Bit.v
+++ b/tests/test_circuit/gold/test_anon_value_Bit.v
@@ -1,6 +1,6 @@
 module main (input  I0, input  I1, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_anon_value_Bits(2).json b/tests/test_circuit/gold/test_anon_value_Bits(2).json
index 430357bdda..48b1342859 100644
--- a/tests/test_circuit/gold/test_anon_value_Bits(2).json
+++ b/tests/test_circuit/gold/test_anon_value_Bits(2).json
@@ -16,14 +16,14 @@
           ["O",["Array",2,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2"
           }
         },
         "connections":[
-          ["self.I0","inst0.I0"],
-          ["self.I1","inst0.I1"],
-          ["self.O","inst0.O"]
+          ["self.I0","And2_inst0.I0"],
+          ["self.I1","And2_inst0.I1"],
+          ["self.O","And2_inst0.O"]
         ]
       }
     }
diff --git a/tests/test_circuit/gold/test_anon_value_Bits(2).v b/tests/test_circuit/gold/test_anon_value_Bits(2).v
index 42af4fd886..058f17080a 100644
--- a/tests/test_circuit/gold/test_anon_value_Bits(2).v
+++ b/tests/test_circuit/gold/test_anon_value_Bits(2).v
@@ -1,6 +1,6 @@
 module main (input [1:0] I0, input [1:0] I1, output [1:0] O);
-wire [1:0] inst0_O;
-And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O));
-assign O = inst0_O;
+wire [1:0] And2_inst0_O;
+And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json
index a98bdada87..fe742125fa 100644
--- a/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json
+++ b/tests/test_circuit/gold/test_anon_value_Tuple(x=Bit,y=Bit).json
@@ -16,14 +16,14 @@
           ["O",["Record",[["x","Bit"],["y","Bit"]]]]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2"
           }
         },
         "connections":[
-          ["self.I0","inst0.I0"],
-          ["self.I1","inst0.I1"],
-          ["self.O","inst0.O"]
+          ["self.I0","And2_inst0.I0"],
+          ["self.I1","And2_inst0.I1"],
+          ["self.O","And2_inst0.O"]
         ]
       }
     }
diff --git a/tests/test_circuit/gold/test_for_loop_def.json b/tests/test_circuit/gold/test_for_loop_def.json
index 92e3e3822d..abcc3eb6ea 100644
--- a/tests/test_circuit/gold/test_for_loop_def.json
+++ b/tests/test_circuit/gold/test_for_loop_def.json
@@ -16,33 +16,33 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"}
           },
-          "inst1":{
+          "And2_inst1":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"}
           },
-          "inst2":{
+          "And2_inst2":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"}
           },
-          "inst3":{
+          "And2_inst3":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"56"}
           }
         },
         "connections":[
-          ["self.I.0","inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"58"}],
-          ["self.I.1","inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"59"}],
-          ["inst1.I0","inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
-          ["self.I.1","inst1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
-          ["inst2.I0","inst1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
-          ["self.I.1","inst2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
-          ["inst3.I0","inst2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
-          ["self.I.1","inst3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
-          ["self.O","inst3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}]
+          ["self.I.0","And2_inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"58"}],
+          ["self.I.1","And2_inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"59"}],
+          ["And2_inst1.I0","And2_inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
+          ["self.I.1","And2_inst1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
+          ["And2_inst2.I0","And2_inst1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
+          ["self.I.1","And2_inst2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
+          ["And2_inst3.I0","And2_inst2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"61"}],
+          ["self.I.1","And2_inst3.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"62"}],
+          ["self.O","And2_inst3.O",{"filename":"tests/test_circuit/test_define.py","lineno":"65"}]
         ],
         "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"52"}
       }
diff --git a/tests/test_circuit/gold/test_for_loop_def.v b/tests/test_circuit/gold/test_for_loop_def.v
index 096c57ae9a..9434662f43 100644
--- a/tests/test_circuit/gold/test_for_loop_def.v
+++ b/tests/test_circuit/gold/test_for_loop_def.v
@@ -1,30 +1,30 @@
 // Defined at tests/test_circuit/test_define.py:52
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-wire  inst1_O;
-wire  inst2_O;
-wire  inst3_O;
+wire  And2_inst0_O;
+wire  And2_inst1_O;
+wire  And2_inst2_O;
+wire  And2_inst3_O;
 // Instanced at tests/test_circuit/test_define.py:56
 // Argument I0(I[0]) wired at tests/test_circuit/test_define.py:58
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:59
-// Argument O(inst0_O) wired at tests/test_circuit/test_define.py:61
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
+// Argument O(And2_inst0_O) wired at tests/test_circuit/test_define.py:61
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
 // Instanced at tests/test_circuit/test_define.py:56
-// Argument I0(inst0_O) wired at tests/test_circuit/test_define.py:61
+// Argument I0(And2_inst0_O) wired at tests/test_circuit/test_define.py:61
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:62
-// Argument O(inst1_O) wired at tests/test_circuit/test_define.py:61
-And2 inst1 (.I0(inst0_O), .I1(I[1]), .O(inst1_O));
+// Argument O(And2_inst1_O) wired at tests/test_circuit/test_define.py:61
+And2 And2_inst1 (.I0(And2_inst0_O), .I1(I[1]), .O(And2_inst1_O));
 // Instanced at tests/test_circuit/test_define.py:56
-// Argument I0(inst1_O) wired at tests/test_circuit/test_define.py:61
+// Argument I0(And2_inst1_O) wired at tests/test_circuit/test_define.py:61
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:62
-// Argument O(inst2_O) wired at tests/test_circuit/test_define.py:61
-And2 inst2 (.I0(inst1_O), .I1(I[1]), .O(inst2_O));
+// Argument O(And2_inst2_O) wired at tests/test_circuit/test_define.py:61
+And2 And2_inst2 (.I0(And2_inst1_O), .I1(I[1]), .O(And2_inst2_O));
 // Instanced at tests/test_circuit/test_define.py:56
-// Argument I0(inst2_O) wired at tests/test_circuit/test_define.py:61
+// Argument I0(And2_inst2_O) wired at tests/test_circuit/test_define.py:61
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:62
-// Argument O(inst3_O) wired at tests/test_circuit/test_define.py:65
-And2 inst3 (.I0(inst2_O), .I1(I[1]), .O(inst3_O));
+// Argument O(And2_inst3_O) wired at tests/test_circuit/test_define.py:65
+And2 And2_inst3 (.I0(And2_inst2_O), .I1(I[1]), .O(And2_inst3_O));
 // Wired at tests/test_circuit/test_define.py:65
-assign O = inst3_O;
+assign O = And2_inst3_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_interleaved_instance_wiring.json b/tests/test_circuit/gold/test_interleaved_instance_wiring.json
index 002ce928b8..bc5f1dc8ba 100644
--- a/tests/test_circuit/gold/test_interleaved_instance_wiring.json
+++ b/tests/test_circuit/gold/test_interleaved_instance_wiring.json
@@ -16,27 +16,27 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"84"}
           },
-          "inst1":{
+          "And2_inst1":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"85"}
           },
-          "inst2":{
+          "And2_inst2":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"91"}
           }
         },
         "connections":[
-          ["self.I.0","inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"87"}],
-          ["self.I.1","inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"88"}],
-          ["inst1.I0","inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"89"}],
-          ["self.I.1","inst1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"90"}],
-          ["inst2.I0","inst1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"92"}],
-          ["self.I.0","inst2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"93"}],
-          ["self.O","inst2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"95"}]
+          ["self.I.0","And2_inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"87"}],
+          ["self.I.1","And2_inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"88"}],
+          ["And2_inst1.I0","And2_inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"89"}],
+          ["self.I.1","And2_inst1.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"90"}],
+          ["And2_inst2.I0","And2_inst1.O",{"filename":"tests/test_circuit/test_define.py","lineno":"92"}],
+          ["self.I.0","And2_inst2.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"93"}],
+          ["self.O","And2_inst2.O",{"filename":"tests/test_circuit/test_define.py","lineno":"95"}]
         ],
         "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"82"}
       }
diff --git a/tests/test_circuit/gold/test_interleaved_instance_wiring.v b/tests/test_circuit/gold/test_interleaved_instance_wiring.v
index c21bec8775..d065ac6410 100644
--- a/tests/test_circuit/gold/test_interleaved_instance_wiring.v
+++ b/tests/test_circuit/gold/test_interleaved_instance_wiring.v
@@ -1,24 +1,24 @@
 // Defined at tests/test_circuit/test_define.py:82
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-wire  inst1_O;
-wire  inst2_O;
+wire  And2_inst0_O;
+wire  And2_inst1_O;
+wire  And2_inst2_O;
 // Instanced at tests/test_circuit/test_define.py:84
 // Argument I0(I[0]) wired at tests/test_circuit/test_define.py:87
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:88
-// Argument O(inst0_O) wired at tests/test_circuit/test_define.py:89
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
+// Argument O(And2_inst0_O) wired at tests/test_circuit/test_define.py:89
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
 // Instanced at tests/test_circuit/test_define.py:85
-// Argument I0(inst0_O) wired at tests/test_circuit/test_define.py:89
+// Argument I0(And2_inst0_O) wired at tests/test_circuit/test_define.py:89
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:90
-// Argument O(inst1_O) wired at tests/test_circuit/test_define.py:92
-And2 inst1 (.I0(inst0_O), .I1(I[1]), .O(inst1_O));
+// Argument O(And2_inst1_O) wired at tests/test_circuit/test_define.py:92
+And2 And2_inst1 (.I0(And2_inst0_O), .I1(I[1]), .O(And2_inst1_O));
 // Instanced at tests/test_circuit/test_define.py:91
-// Argument I0(inst1_O) wired at tests/test_circuit/test_define.py:92
+// Argument I0(And2_inst1_O) wired at tests/test_circuit/test_define.py:92
 // Argument I1(I[0]) wired at tests/test_circuit/test_define.py:93
-// Argument O(inst2_O) wired at tests/test_circuit/test_define.py:95
-And2 inst2 (.I0(inst1_O), .I1(I[0]), .O(inst2_O));
+// Argument O(And2_inst2_O) wired at tests/test_circuit/test_define.py:95
+And2 And2_inst2 (.I0(And2_inst1_O), .I1(I[0]), .O(And2_inst2_O));
 // Wired at tests/test_circuit/test_define.py:95
-assign O = inst2_O;
+assign O = And2_inst2_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_simple_def.json b/tests/test_circuit/gold/test_simple_def.json
index 154617ad89..1beb98176d 100644
--- a/tests/test_circuit/gold/test_simple_def.json
+++ b/tests/test_circuit/gold/test_simple_def.json
@@ -16,15 +16,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"16"}
           }
         },
         "connections":[
-          ["self.I.0","inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"18"}],
-          ["self.I.1","inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"19"}],
-          ["self.O","inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"20"}]
+          ["self.I.0","And2_inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"18"}],
+          ["self.I.1","And2_inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"19"}],
+          ["self.O","And2_inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"20"}]
         ],
         "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"14"}
       }
diff --git a/tests/test_circuit/gold/test_simple_def.v b/tests/test_circuit/gold/test_simple_def.v
index 0aad313fa9..5deaa8053b 100644
--- a/tests/test_circuit/gold/test_simple_def.v
+++ b/tests/test_circuit/gold/test_simple_def.v
@@ -1,12 +1,12 @@
 // Defined at tests/test_circuit/test_define.py:14
 module main (input [1:0] I, output  O);
-wire  inst0_O;
+wire  And2_inst0_O;
 // Instanced at tests/test_circuit/test_define.py:16
 // Argument I0(I[0]) wired at tests/test_circuit/test_define.py:18
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:19
-// Argument O(inst0_O) wired at tests/test_circuit/test_define.py:20
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
+// Argument O(And2_inst0_O) wired at tests/test_circuit/test_define.py:20
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
 // Wired at tests/test_circuit/test_define.py:20
-assign O = inst0_O;
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_simple_def_class.json b/tests/test_circuit/gold/test_simple_def_class.json
index 143885afef..ee45f8e90e 100644
--- a/tests/test_circuit/gold/test_simple_def_class.json
+++ b/tests/test_circuit/gold/test_simple_def_class.json
@@ -16,15 +16,15 @@
           ["O","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "And2_inst0":{
             "modref":"global.And2",
             "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"16"}
           }
         },
         "connections":[
-          ["self.I.0","inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"18"}],
-          ["self.I.1","inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"19"}],
-          ["self.O","inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"20"}]
+          ["self.I.0","And2_inst0.I0",{"filename":"tests/test_circuit/test_define.py","lineno":"18"}],
+          ["self.I.1","And2_inst0.I1",{"filename":"tests/test_circuit/test_define.py","lineno":"19"}],
+          ["self.O","And2_inst0.O",{"filename":"tests/test_circuit/test_define.py","lineno":"20"}]
         ],
         "metadata":{"filename":"tests/test_circuit/test_define.py","lineno":"14"}
       }
diff --git a/tests/test_circuit/gold/test_simple_def_class.v b/tests/test_circuit/gold/test_simple_def_class.v
index d5ebac6c39..ba7deffbf0 100644
--- a/tests/test_circuit/gold/test_simple_def_class.v
+++ b/tests/test_circuit/gold/test_simple_def_class.v
@@ -1,12 +1,12 @@
 // Defined at tests/test_circuit/test_define.py:29
 module Main (input [1:0] I, output  O);
-wire  inst0_O;
+wire  And2_inst0_O;
 // Instanced at tests/test_circuit/test_define.py:34
 // Argument I0(I[0]) wired at tests/test_circuit/test_define.py:35
 // Argument I1(I[1]) wired at tests/test_circuit/test_define.py:36
-// Argument O(inst0_O) wired at tests/test_circuit/test_define.py:37
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
+// Argument O(And2_inst0_O) wired at tests/test_circuit/test_define.py:37
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
 // Wired at tests/test_circuit/test_define.py:37
-assign O = inst0_O;
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_circuit/gold/test_unwired_output.v b/tests/test_circuit/gold/test_unwired_output.v
index 4440ae2726..510420101c 100644
--- a/tests/test_circuit/gold/test_unwired_output.v
+++ b/tests/test_circuit/gold/test_unwired_output.v
@@ -1,5 +1,5 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-And2 inst0 (.I1(I[1]), .O(inst0_O));
+wire  And2_inst0_O;
+And2 And2_inst0 (.I1(I[1]), .O(And2_inst0_O));
 endmodule
 
diff --git a/tests/test_circuit/test_inspect.py b/tests/test_circuit/test_inspect.py
index c82e14719d..de6207170f 100644
--- a/tests/test_circuit/test_inspect.py
+++ b/tests/test_circuit/test_inspect.py
@@ -11,21 +11,22 @@ def test_str_repr():
     m.EndCircuit()
 
     assert str(Logic2) == "Logic2(I0: In(Bit), I1: In(Bit), O: Out(Bit))"
+    print(repr(Logic2))
     assert repr(Logic2) == """\
 Logic2 = DefineCircuit("Logic2", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
-inst0 = XOr2()
-inst1 = And2()
-wire(inst1.O, inst0.I0)
-wire(1, inst0.I1)
-wire(Logic2.I0, inst1.I0)
-wire(Logic2.I1, inst1.I1)
-wire(inst0.O, Logic2.O)
+XOr2_inst0 = XOr2()
+And2_inst0 = And2()
+wire(And2_inst0.O, XOr2_inst0.I0)
+wire(1, XOr2_inst0.I1)
+wire(Logic2.I0, And2_inst0.I0)
+wire(Logic2.I1, And2_inst0.I1)
+wire(XOr2_inst0.O, Logic2.O)
 EndCircuit()\
 """
 
     expected = [
-        "inst0<XOr2(I0: In(Bit), I1: In(Bit), O: Out(Bit))>",
-        "inst1<And2(I0: In(Bit), I1: In(Bit), O: Out(Bit))>"
+        "XOr2_inst0<XOr2(I0: In(Bit), I1: In(Bit), O: Out(Bit))>",
+        "And2_inst0<And2(I0: In(Bit), I1: In(Bit), O: Out(Bit))>"
     ]
     for inst, expected in zip(Logic2.instances, expected):
         assert str(inst) == expected
@@ -44,4 +45,4 @@ def test_str_repr_anon():
     string = str(anon)
     assert string[:len("AnonymousCircuitInst")] == "AnonymousCircuitInst"
     assert string[-len("<I0: Array(3,In(Bit)), I1: Array(3,In(Bit)), O: Array(3,Out(Bit))>"):] == "<I0: Array(3,In(Bit)), I1: Array(3,In(Bit)), O: Array(3,Out(Bit))>"
-    assert repr(anon) == 'AnonymousCircuitType("I0", array([inst0.I0, inst1.I0, inst2.I0]), "I1", array([inst0.I1, inst1.I1, inst2.I1]), "O", array([inst0.O, inst1.O, inst2.O]))'
+    assert repr(anon) == 'AnonymousCircuitType("I0", array([And2_inst0.I0, And2_inst1.I0, And2_inst2.I0]), "I1", array([And2_inst0.I1, And2_inst1.I1, And2_inst2.I1]), "O", array([And2_inst0.O, And2_inst1.O, And2_inst2.O]))'
diff --git a/tests/test_coreir/gold/linker_test0.json b/tests/test_coreir/gold/linker_test0.json
index 6adaf5cf1d..9b6cbc7c02 100644
--- a/tests/test_coreir/gold/linker_test0.json
+++ b/tests/test_coreir/gold/linker_test0.json
@@ -9,15 +9,15 @@
           ["O",["Array",16,"Bit"]]
         ]],
         "instances":{
-          "inst0":{
+          "commonlib_smax_width_16_inst0":{
             "genref":"commonlib.smax",
             "genargs":{"width":["Int",16]}
           }
         },
         "connections":[
-          ["self.I0","inst0.in0"],
-          ["self.I1","inst0.in1"],
-          ["self.O","inst0.out"]
+          ["self.I0","commonlib_smax_width_16_inst0.in0"],
+          ["self.I1","commonlib_smax_width_16_inst0.in1"],
+          ["self.O","commonlib_smax_width_16_inst0.out"]
         ]
       }
     }
diff --git a/tests/test_coreir/gold/test_compile_coreir_verilog.v b/tests/test_coreir/gold/test_compile_coreir_verilog.v
index 75a6a1e457..31b4f29494 100644
--- a/tests/test_coreir/gold/test_compile_coreir_verilog.v
+++ b/tests/test_coreir/gold/test_compile_coreir_verilog.v
@@ -14,20 +14,20 @@ module main (
 );
 
 
-  wire  inst0__I0;
-  wire  inst0__I1;
-  wire  inst0__O;
-  And2 inst0(
-    .I0(inst0__I0),
-    .I1(inst0__I1),
-    .O(inst0__O)
+  wire  And2_inst0__I0;
+  wire  And2_inst0__I1;
+  wire  And2_inst0__O;
+  And2 And2_inst0(
+    .I0(And2_inst0__I0),
+    .I1(And2_inst0__I1),
+    .O(And2_inst0__O)
   );
 
-  assign inst0__I0 = I[0];
+  assign And2_inst0__I0 = I[0];
 
-  assign inst0__I1 = I[1];
+  assign And2_inst0__I1 = I[1];
 
-  assign O = inst0__O;
+  assign O = And2_inst0__O;
 
 
 endmodule  // main
diff --git a/tests/test_coreir/gold/test_multi_direction_tuple_instance.json b/tests/test_coreir/gold/test_multi_direction_tuple_instance.json
index 7fdd054e02..d010985064 100644
--- a/tests/test_coreir/gold/test_multi_direction_tuple_instance.json
+++ b/tests/test_coreir/gold/test_multi_direction_tuple_instance.json
@@ -15,13 +15,13 @@
           ["ifc",["Record",[["I","BitIn"],["O","Bit"]]]]
         ]],
         "instances":{
-          "inst0":{
+          "Foo_inst0":{
             "modref":"global.Foo"
           }
         },
         "connections":[
-          ["self.ifc.I","inst0.ifc.I"],
-          ["self.ifc.O","inst0.ifc.O"]
+          ["self.ifc.I","Foo_inst0.ifc.I"],
+          ["self.ifc.O","Foo_inst0.ifc.O"]
         ]
       }
     }
diff --git a/tests/test_coreir/gold/test_nesting.json b/tests/test_coreir/gold/test_nesting.json
index b6a21bb381..135697c486 100644
--- a/tests/test_coreir/gold/test_nesting.json
+++ b/tests/test_coreir/gold/test_nesting.json
@@ -15,23 +15,23 @@
           ["I",["Record",[["x",["Record",[["a","BitIn"],["b","BitIn"]]]],["y",["Record",[["a","Bit"],["b","Bit"]]]],["z",["Record",[["a","BitIn"],["b","Bit"]]]]]]]
         ]],
         "instances":{
-          "inst0":{
+          "Foo_inst0":{
             "modref":"global.Foo"
           },
-          "inst1":{
+          "Foo_inst1":{
             "modref":"global.Foo"
           },
-          "inst2":{
+          "Foo_inst2":{
             "modref":"global.Foo"
           }
         },
         "connections":[
-          ["self.I.x.a","inst0.ifc.I"],
-          ["self.I.y.a","inst0.ifc.O"],
-          ["self.I.x.b","inst1.ifc.I"],
-          ["self.I.y.b","inst1.ifc.O"],
-          ["self.I.z.a","inst2.ifc.I"],
-          ["self.I.z.b","inst2.ifc.O"]
+          ["self.I.x.a","Foo_inst0.ifc.I"],
+          ["self.I.y.a","Foo_inst0.ifc.O"],
+          ["self.I.x.b","Foo_inst1.ifc.I"],
+          ["self.I.y.b","Foo_inst1.ifc.O"],
+          ["self.I.z.a","Foo_inst2.ifc.I"],
+          ["self.I.z.b","Foo_inst2.ifc.O"]
         ]
       }
     }
diff --git a/tests/test_ir/gold/declaretest.v b/tests/test_ir/gold/declaretest.v
index 2534dfb8a1..f0fc76a4fb 100644
--- a/tests/test_ir/gold/declaretest.v
+++ b/tests/test_ir/gold/declaretest.v
@@ -1,6 +1,6 @@
 module main (input  I0, input  I1, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_ir/test_ir.py b/tests/test_ir/test_ir.py
index 64795fde0e..90fc07bcd8 100644
--- a/tests/test_ir/test_ir.py
+++ b/tests/test_ir/test_ir.py
@@ -23,16 +23,16 @@ def test_print_ir():
     #print(result)
     assert result == """\
 And2 = DefineCircuit("And2", "I", Array(2,In(Bit)), "O", Out(Bit))
-inst0 = And2()
-wire(And2.I[0], inst0.I0)
-wire(And2.I[1], inst0.I1)
-wire(inst0.O, And2.O)
+And2_inst0 = And2()
+wire(And2.I[0], And2_inst0.I0)
+wire(And2.I[1], And2_inst0.I1)
+wire(And2_inst0.O, And2.O)
 EndCircuit()
 main = DefineCircuit("main", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
-inst0 = And2()
-wire(main.I0, inst0.I[0])
-wire(main.I1, inst0.I[1])
-wire(inst0.O, main.O)
+And2_inst0 = And2()
+wire(main.I0, And2_inst0.I[0])
+wire(main.I1, And2_inst0.I[1])
+wire(And2_inst0.O, main.O)
 EndCircuit()
 """
 #    assert result == """\
diff --git a/tests/test_meta/gold/class.v b/tests/test_meta/gold/class.v
index 2534dfb8a1..f0fc76a4fb 100644
--- a/tests/test_meta/gold/class.v
+++ b/tests/test_meta/gold/class.v
@@ -1,6 +1,6 @@
 module main (input  I0, input  I1, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_meta/gold/creg.v b/tests/test_meta/gold/creg.v
index 33d5a7a57c..2b0c803e1f 100644
--- a/tests/test_meta/gold/creg.v
+++ b/tests/test_meta/gold/creg.v
@@ -1,14 +1,14 @@
 module Register2 (input [1:0] I, output [1:0] O, input  CLK);
-wire  inst0_O;
-wire  inst1_O;
-DFF inst0 (.I(I[0]), .O(inst0_O), .CLK(CLK));
-DFF inst1 (.I(I[1]), .O(inst1_O), .CLK(CLK));
-assign O = {inst1_O,inst0_O};
+wire  DFF_inst0_O;
+wire  DFF_inst1_O;
+DFF DFF_inst0 (.I(I[0]), .O(DFF_inst0_O), .CLK(CLK));
+DFF DFF_inst1 (.I(I[1]), .O(DFF_inst1_O), .CLK(CLK));
+assign O = {DFF_inst1_O,DFF_inst0_O};
 endmodule
 
 module main (input  CLK, input [1:0] I, output [1:0] O);
-wire [1:0] inst0_O;
-Register2 inst0 (.I(I), .O(inst0_O), .CLK(CLK));
-assign O = inst0_O;
+wire [1:0] Register2_inst0_O;
+Register2 Register2_inst0 (.I(I), .O(Register2_inst0_O), .CLK(CLK));
+assign O = Register2_inst0_O;
 endmodule
 
diff --git a/tests/test_type/test_const_wire_golden.json b/tests/test_type/test_const_wire_golden.json
index 87833a54e1..22f4874df8 100644
--- a/tests/test_type/test_const_wire_golden.json
+++ b/tests/test_type/test_const_wire_golden.json
@@ -16,12 +16,12 @@
             "modref":"corebit.const",
             "modargs":{"value":["Bool",false]}
           },
-          "inst0":{
+          "foo_inst0":{
             "modref":"global.foo"
           }
         },
         "connections":[
-          ["inst0.I","bit_const_0_None.out"],
+          ["foo_inst0.I","bit_const_0_None.out"],
           ["self.O","bit_const_0_None.out"]
         ]
       }
diff --git a/tests/test_type/test_coreir_wrap_golden_AsyncReset.json b/tests/test_type/test_coreir_wrap_golden_AsyncReset.json
index 9725656fc0..5fb23d0df5 100644
--- a/tests/test_type/test_coreir_wrap_golden_AsyncReset.json
+++ b/tests/test_type/test_coreir_wrap_golden_AsyncReset.json
@@ -16,18 +16,18 @@
             "modref":"corebit.const",
             "modargs":{"value":["Bool",false]}
           },
-          "inst0":{
-            "modref":"global.foo"
-          },
-          "inst1":{
+          "coreir_wrapBit_inst0":{
             "genref":"coreir.wrap",
             "genargs":{"type":["CoreIRType",["Named","coreir.arst"]]}
+          },
+          "foo_inst0":{
+            "modref":"global.foo"
           }
         },
         "connections":[
-          ["inst1.in","bit_const_0_None.out"],
+          ["coreir_wrapBit_inst0.in","bit_const_0_None.out"],
           ["self.O","bit_const_0_None.out"],
-          ["inst1.out","inst0.r"]
+          ["foo_inst0.r","coreir_wrapBit_inst0.out"]
         ]
       }
     }
diff --git a/tests/test_type/test_coreir_wrap_golden_Clock.json b/tests/test_type/test_coreir_wrap_golden_Clock.json
index d90d799d63..f5d370b114 100644
--- a/tests/test_type/test_coreir_wrap_golden_Clock.json
+++ b/tests/test_type/test_coreir_wrap_golden_Clock.json
@@ -16,18 +16,18 @@
             "modref":"corebit.const",
             "modargs":{"value":["Bool",false]}
           },
-          "inst0":{
-            "modref":"global.foo"
-          },
-          "inst1":{
+          "coreir_wrapBit_inst0":{
             "genref":"coreir.wrap",
             "genargs":{"type":["CoreIRType",["Named","coreir.clk"]]}
+          },
+          "foo_inst0":{
+            "modref":"global.foo"
           }
         },
         "connections":[
-          ["inst1.in","bit_const_0_None.out"],
+          ["coreir_wrapBit_inst0.in","bit_const_0_None.out"],
           ["self.O","bit_const_0_None.out"],
-          ["inst1.out","inst0.r"]
+          ["foo_inst0.r","coreir_wrapBit_inst0.out"]
         ]
       }
     }
diff --git a/tests/test_verilog/gold/test_rxmod_top.json b/tests/test_verilog/gold/test_rxmod_top.json
index a5c151de99..887696f0d6 100644
--- a/tests/test_verilog/gold/test_rxmod_top.json
+++ b/tests/test_verilog/gold/test_rxmod_top.json
@@ -19,15 +19,15 @@
           ["valid","Bit"]
         ]],
         "instances":{
-          "inst0":{
+          "RXMOD_inst0":{
             "modref":"global.RXMOD"
           }
         },
         "connections":[
-          ["self.CLK","inst0.CLK"],
-          ["self.RX","inst0.RX"],
-          ["self.data","inst0.data"],
-          ["self.valid","inst0.valid"]
+          ["self.CLK","RXMOD_inst0.CLK"],
+          ["self.RX","RXMOD_inst0.RX"],
+          ["self.data","RXMOD_inst0.data"],
+          ["self.valid","RXMOD_inst0.valid"]
         ]
       }
     }
diff --git a/tests/test_wire/gold/arg1.v b/tests/test_wire/gold/arg1.v
index db3c22b3ac..6e284cc404 100644
--- a/tests/test_wire/gold/arg1.v
+++ b/tests/test_wire/gold/arg1.v
@@ -1,6 +1,6 @@
 module main (input  I, output  O);
-wire  inst0_O;
-Buf inst0 (.I(I), .O(inst0_O));
-assign O = inst0_O;
+wire  Buf_inst0_O;
+Buf Buf_inst0 (.I(I), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/arg2.v b/tests/test_wire/gold/arg2.v
index 11b4faa2bc..313319687d 100644
--- a/tests/test_wire/gold/arg2.v
+++ b/tests/test_wire/gold/arg2.v
@@ -1,6 +1,6 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/array1.v b/tests/test_wire/gold/array1.v
index 31c332c7db..25029d19b2 100644
--- a/tests/test_wire/gold/array1.v
+++ b/tests/test_wire/gold/array1.v
@@ -1,6 +1,6 @@
 module main (output  O);
-wire  inst0_O;
-AndN2 inst0 (.I({1'b1,1'b0}), .O(inst0_O));
-assign O = inst0_O;
+wire  AndN2_inst0_O;
+AndN2 AndN2_inst0 (.I({1'b1,1'b0}), .O(AndN2_inst0_O));
+assign O = AndN2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/array2.v b/tests/test_wire/gold/array2.v
index 3d3935a7ca..c5c2c43e3f 100644
--- a/tests/test_wire/gold/array2.v
+++ b/tests/test_wire/gold/array2.v
@@ -1,6 +1,6 @@
 module main (input  I, output  O);
-wire  inst0_O;
-AndN2 inst0 (.I({1'b1,I}), .O(inst0_O));
-assign O = inst0_O;
+wire  AndN2_inst0_O;
+AndN2 AndN2_inst0 (.I({1'b1,I}), .O(AndN2_inst0_O));
+assign O = AndN2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/array3.v b/tests/test_wire/gold/array3.v
index e5ad4826a8..39561f7c1b 100644
--- a/tests/test_wire/gold/array3.v
+++ b/tests/test_wire/gold/array3.v
@@ -1,6 +1,6 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-AndN2 inst0 (.I(I), .O(inst0_O));
-assign O = inst0_O;
+wire  AndN2_inst0_O;
+AndN2 AndN2_inst0 (.I(I), .O(AndN2_inst0_O));
+assign O = AndN2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/call1.v b/tests/test_wire/gold/call1.v
index 2534dfb8a1..f0fc76a4fb 100644
--- a/tests/test_wire/gold/call1.v
+++ b/tests/test_wire/gold/call1.v
@@ -1,6 +1,6 @@
 module main (input  I0, input  I1, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I0), .I1(I1), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I0), .I1(I1), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/call2.v b/tests/test_wire/gold/call2.v
index e5ad4826a8..39561f7c1b 100644
--- a/tests/test_wire/gold/call2.v
+++ b/tests/test_wire/gold/call2.v
@@ -1,6 +1,6 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-AndN2 inst0 (.I(I), .O(inst0_O));
-assign O = inst0_O;
+wire  AndN2_inst0_O;
+AndN2 AndN2_inst0 (.I(I), .O(AndN2_inst0_O));
+assign O = AndN2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/compose.v b/tests/test_wire/gold/compose.v
index 4796b76c02..f7ea820c87 100644
--- a/tests/test_wire/gold/compose.v
+++ b/tests/test_wire/gold/compose.v
@@ -1,8 +1,8 @@
 module main (input  I, output  O);
-wire  inst0_O;
-wire  inst1_O;
-Buf inst0 (.I(I), .O(inst0_O));
-Buf inst1 (.I(inst0_O), .O(inst1_O));
-assign O = inst1_O;
+wire  Buf_inst0_O;
+wire  Buf_inst1_O;
+Buf Buf_inst0 (.I(I), .O(Buf_inst0_O));
+Buf Buf_inst1 (.I(Buf_inst0_O), .O(Buf_inst1_O));
+assign O = Buf_inst1_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const0.v b/tests/test_wire/gold/const0.v
index 8594983146..a899c17bb0 100644
--- a/tests/test_wire/gold/const0.v
+++ b/tests/test_wire/gold/const0.v
@@ -1,6 +1,6 @@
 module main (output  O);
-wire  inst0_O;
-Buf inst0 (.I(1'b0), .O(inst0_O));
-assign O = inst0_O;
+wire  Buf_inst0_O;
+Buf Buf_inst0 (.I(1'b0), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const1.v b/tests/test_wire/gold/const1.v
index 127a8904db..d6d13c39b6 100644
--- a/tests/test_wire/gold/const1.v
+++ b/tests/test_wire/gold/const1.v
@@ -1,6 +1,6 @@
 module main (output  O);
-wire  inst0_O;
-Buf inst0 (.I(1'b1), .O(inst0_O));
-assign O = inst0_O;
+wire  Buf_inst0_O;
+Buf Buf_inst0 (.I(1'b1), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_Bits_1.v b/tests/test_wire/gold/const_bits_Bits_1.v
index c3880d061d..41d770e3b8 100644
--- a/tests/test_wire/gold/const_bits_Bits_1.v
+++ b/tests/test_wire/gold/const_bits_Bits_1.v
@@ -1,6 +1,6 @@
 module main (output [0:0] O);
-wire [0:0] inst0_O;
-Buf inst0 (.I({1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire [0:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_Bits_2.v b/tests/test_wire/gold/const_bits_Bits_2.v
index 810ccc3ac3..fccad692ff 100644
--- a/tests/test_wire/gold/const_bits_Bits_2.v
+++ b/tests/test_wire/gold/const_bits_Bits_2.v
@@ -1,6 +1,6 @@
 module main (output [1:0] O);
-wire [1:0] inst0_O;
-Buf inst0 (.I({1'b0,1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire [1:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b0,1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_Bits_3.v b/tests/test_wire/gold/const_bits_Bits_3.v
index 9466fb975c..9bd34d4fb7 100644
--- a/tests/test_wire/gold/const_bits_Bits_3.v
+++ b/tests/test_wire/gold/const_bits_Bits_3.v
@@ -1,6 +1,6 @@
 module main (output [2:0] O);
-wire [2:0] inst0_O;
-Buf inst0 (.I({1'b0,1'b0,1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire [2:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b0,1'b0,1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_SInt_1.v b/tests/test_wire/gold/const_bits_SInt_1.v
index 37ac294f4b..ce39b06def 100644
--- a/tests/test_wire/gold/const_bits_SInt_1.v
+++ b/tests/test_wire/gold/const_bits_SInt_1.v
@@ -1,6 +1,6 @@
 module main (output signed [0:0] O);
-wire signed [0:0] inst0_O;
-Buf inst0 (.I({1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire signed [0:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_SInt_2.v b/tests/test_wire/gold/const_bits_SInt_2.v
index 7bda4cbae6..d8b4336377 100644
--- a/tests/test_wire/gold/const_bits_SInt_2.v
+++ b/tests/test_wire/gold/const_bits_SInt_2.v
@@ -1,6 +1,6 @@
 module main (output signed [1:0] O);
-wire signed [1:0] inst0_O;
-Buf inst0 (.I({1'b0,1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire signed [1:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b0,1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_SInt_3.v b/tests/test_wire/gold/const_bits_SInt_3.v
index 0992e6cb63..6922436114 100644
--- a/tests/test_wire/gold/const_bits_SInt_3.v
+++ b/tests/test_wire/gold/const_bits_SInt_3.v
@@ -1,6 +1,6 @@
 module main (output signed [2:0] O);
-wire signed [2:0] inst0_O;
-Buf inst0 (.I({1'b0,1'b0,1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire signed [2:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b0,1'b0,1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_UInt_1.v b/tests/test_wire/gold/const_bits_UInt_1.v
index c3880d061d..41d770e3b8 100644
--- a/tests/test_wire/gold/const_bits_UInt_1.v
+++ b/tests/test_wire/gold/const_bits_UInt_1.v
@@ -1,6 +1,6 @@
 module main (output [0:0] O);
-wire [0:0] inst0_O;
-Buf inst0 (.I({1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire [0:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_UInt_2.v b/tests/test_wire/gold/const_bits_UInt_2.v
index 810ccc3ac3..fccad692ff 100644
--- a/tests/test_wire/gold/const_bits_UInt_2.v
+++ b/tests/test_wire/gold/const_bits_UInt_2.v
@@ -1,6 +1,6 @@
 module main (output [1:0] O);
-wire [1:0] inst0_O;
-Buf inst0 (.I({1'b0,1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire [1:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b0,1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/const_bits_UInt_3.v b/tests/test_wire/gold/const_bits_UInt_3.v
index 9466fb975c..9bd34d4fb7 100644
--- a/tests/test_wire/gold/const_bits_UInt_3.v
+++ b/tests/test_wire/gold/const_bits_UInt_3.v
@@ -1,6 +1,6 @@
 module main (output [2:0] O);
-wire [2:0] inst0_O;
-Buf inst0 (.I({1'b0,1'b0,1'b1}), .O(inst0_O));
-assign O = inst0_O;
+wire [2:0] Buf_inst0_O;
+Buf Buf_inst0 (.I({1'b0,1'b0,1'b1}), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/flip.v b/tests/test_wire/gold/flip.v
index 127a8904db..d6d13c39b6 100644
--- a/tests/test_wire/gold/flip.v
+++ b/tests/test_wire/gold/flip.v
@@ -1,6 +1,6 @@
 module main (output  O);
-wire  inst0_O;
-Buf inst0 (.I(1'b1), .O(inst0_O));
-assign O = inst0_O;
+wire  Buf_inst0_O;
+Buf Buf_inst0 (.I(1'b1), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/named1.v b/tests/test_wire/gold/named1.v
index db3c22b3ac..6e284cc404 100644
--- a/tests/test_wire/gold/named1.v
+++ b/tests/test_wire/gold/named1.v
@@ -1,6 +1,6 @@
 module main (input  I, output  O);
-wire  inst0_O;
-Buf inst0 (.I(I), .O(inst0_O));
-assign O = inst0_O;
+wire  Buf_inst0_O;
+Buf Buf_inst0 (.I(I), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/named2a.v b/tests/test_wire/gold/named2a.v
index 11b4faa2bc..313319687d 100644
--- a/tests/test_wire/gold/named2a.v
+++ b/tests/test_wire/gold/named2a.v
@@ -1,6 +1,6 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/named2b.v b/tests/test_wire/gold/named2b.v
index 11b4faa2bc..313319687d 100644
--- a/tests/test_wire/gold/named2b.v
+++ b/tests/test_wire/gold/named2b.v
@@ -1,6 +1,6 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/named2c.v b/tests/test_wire/gold/named2c.v
index 11b4faa2bc..313319687d 100644
--- a/tests/test_wire/gold/named2c.v
+++ b/tests/test_wire/gold/named2c.v
@@ -1,6 +1,6 @@
 module main (input [1:0] I, output  O);
-wire  inst0_O;
-And2 inst0 (.I0(I[0]), .I1(I[1]), .O(inst0_O));
-assign O = inst0_O;
+wire  And2_inst0_O;
+And2 And2_inst0 (.I0(I[0]), .I1(I[1]), .O(And2_inst0_O));
+assign O = And2_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/gold/pos.v b/tests/test_wire/gold/pos.v
index db3c22b3ac..6e284cc404 100644
--- a/tests/test_wire/gold/pos.v
+++ b/tests/test_wire/gold/pos.v
@@ -1,6 +1,6 @@
 module main (input  I, output  O);
-wire  inst0_O;
-Buf inst0 (.I(I), .O(inst0_O));
-assign O = inst0_O;
+wire  Buf_inst0_O;
+Buf Buf_inst0 (.I(I), .O(Buf_inst0_O));
+assign O = Buf_inst0_O;
 endmodule
 
diff --git a/tests/test_wire/test_errors.py b/tests/test_wire/test_errors.py
index 1db686167e..24bfb55743 100644
--- a/tests/test_wire/test_errors.py
+++ b/tests/test_wire/test_errors.py
@@ -49,7 +49,7 @@ def test_muliple_outputs_circuit(caplog):
     a = A()
     wire(a, main.I)
     assert "\n".join(x.msg for x in caplog.records) == """\
-\033[1mtests/test_wire/test_errors.py:50: Can only wire circuits with one output. Argument 0 to wire `main_inst0` has outputs [inst0.O, inst0.U]
+\033[1mtests/test_wire/test_errors.py:50: Can only wire circuits with one output. Argument 0 to wire `main.A_inst0` has outputs [inst0.O, inst0.U]
     wire(a, main.I)
 """
 
@@ -101,7 +101,7 @@ def test_no_key(caplog):
     a = A()
     a(K=main.I)
     assert "\n".join(x.msg for x in caplog.records) == """\
-\033[1mtests/test_wire/test_errors.py:102: Circuit main_inst0 does not have input K
+\033[1mtests/test_wire/test_errors.py:102: Instance main.A_inst0 does not have input K
     a(K=main.I)
 """