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Update IR
IR commit: dfd22749acb2a8cb7c728600e1d89f84cab4f99c Fixes oss-fuzz #63548
1 parent 4ae483a commit 1068a5f

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3 files changed

+78
-55
lines changed

3 files changed

+78
-55
lines changed

‎ext/opcache/jit/ir/ir_aarch64.dasc

+60-6
Original file line numberDiff line numberDiff line change
@@ -463,6 +463,22 @@ int ir_get_target_constraints(const ir_ctx *ctx, ir_ref ref, ir_target_constrain
463463
}
464464
flags = IR_USE_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG | IR_OP3_SHOULD_BE_IN_REG;
465465
break;
466+
case IR_COND:
467+
insn = &ctx->ir_base[ref];
468+
n = 0;
469+
if (IR_IS_CONST_REF(insn->op1)) {
470+
constraints->tmp_regs[n] = IR_TMP_REG(1, ctx->ir_base[insn->op1].type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
471+
n++;
472+
}
473+
if (IR_IS_CONST_REF(insn->op2)) {
474+
constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
475+
n++;
476+
}
477+
if (IR_IS_CONST_REF(insn->op3)) {
478+
constraints->tmp_regs[n] = IR_TMP_REG(3, insn->type, IR_LOAD_SUB_REF, IR_DEF_SUB_REF);
479+
n++;
480+
}
481+
break;
466482
case IR_COPY_INT:
467483
case IR_COPY_FP:
468484
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG;
@@ -2138,6 +2154,18 @@ static void ir_emit_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
21382154
case IR_GT:
21392155
| cset Rw(def_reg), gt
21402156
break;
2157+
case IR_ULT:
2158+
| cset Rw(def_reg), lt
2159+
break;
2160+
case IR_UGE:
2161+
| cset Rw(def_reg), hs
2162+
break;
2163+
case IR_ULE:
2164+
| cset Rw(def_reg), le
2165+
break;
2166+
case IR_UGT:
2167+
| cset Rw(def_reg), hi
2168+
break;
21412169
}
21422170
if (IR_REG_SPILLED(ctx->regs[def][0])) {
21432171
ir_emit_store(ctx, insn->type, def, def_reg);
@@ -2212,7 +2240,11 @@ static void ir_emit_jcc(ir_ctx *ctx, uint8_t op, uint32_t b, ir_ref def, ir_insn
22122240
ir_get_true_false_blocks(ctx, b, &true_block, &false_block, &next_block);
22132241
if (true_block == next_block) {
22142242
/* swap to avoid unconditional JMP */
2215-
op ^= 1; // reverse
2243+
if (int_cmp || op == IR_EQ || op == IR_NE) {
2244+
op ^= 1; // reverse
2245+
} else {
2246+
op ^= 5; // reverse
2247+
}
22162248
true_block = false_block;
22172249
false_block = 0;
22182250
} else if (false_block == next_block) {
@@ -2276,6 +2308,18 @@ static void ir_emit_jcc(ir_ctx *ctx, uint8_t op, uint32_t b, ir_ref def, ir_insn
22762308
case IR_GT:
22772309
| bgt =>true_block
22782310
break;
2311+
case IR_ULT:
2312+
| blt =>true_block
2313+
break;
2314+
case IR_UGE:
2315+
| bhs =>true_block
2316+
break;
2317+
case IR_ULE:
2318+
| ble =>true_block
2319+
break;
2320+
case IR_UGT:
2321+
| bhi =>true_block
2322+
break;
22792323
// case IR_ULT: fprintf(stderr, "\tjb .LL%d\n", true_block); break;
22802324
// case IR_UGE: fprintf(stderr, "\tjae .LL%d\n", true_block); break;
22812325
// case IR_ULE: fprintf(stderr, "\tjbe .LL%d\n", true_block); break;
@@ -2421,15 +2465,15 @@ static void ir_emit_cond(ir_ctx *ctx, ir_ref def, ir_insn *insn)
24212465

24222466
if (IR_IS_TYPE_INT(type)) {
24232467
if (ir_type_size[type] == 8) {
2424-
| csel Rx(def_reg), Rx(op2_reg), Rx(op3_reg), eq
2468+
| csel Rx(def_reg), Rx(op2_reg), Rx(op3_reg), ne
24252469
} else {
2426-
| csel Rw(def_reg), Rw(op2_reg), Rw(op3_reg), eq
2470+
| csel Rw(def_reg), Rw(op2_reg), Rw(op3_reg), ne
24272471
}
24282472
} else{
24292473
if (type == IR_DOUBLE) {
2430-
| fcsel Rd(def_reg-IR_REG_FP_FIRST), Rd(op2_reg-IR_REG_FP_FIRST), Rd(op3_reg-IR_REG_FP_FIRST), eq
2474+
| fcsel Rd(def_reg-IR_REG_FP_FIRST), Rd(op2_reg-IR_REG_FP_FIRST), Rd(op3_reg-IR_REG_FP_FIRST), ne
24312475
} else {
2432-
| fcsel Rs(def_reg-IR_REG_FP_FIRST), Rs(op2_reg-IR_REG_FP_FIRST), Rs(op3_reg-IR_REG_FP_FIRST), eq
2476+
| fcsel Rs(def_reg-IR_REG_FP_FIRST), Rs(op2_reg-IR_REG_FP_FIRST), Rs(op3_reg-IR_REG_FP_FIRST), ne
24332477
}
24342478
}
24352479

@@ -3851,6 +3895,12 @@ static int32_t ir_emit_arguments(ir_ctx *ctx, ir_ref def, ir_insn *insn, ir_reg
38513895
val_insn->const_flags |= IR_CONST_EMIT;
38523896
| adr Rx(dst_reg), =>label
38533897
continue;
3898+
} else if (val_insn->op == IR_SYM || val_insn->op == IR_FUNC) {
3899+
void *addr = (ctx->loader && ctx->loader->resolve_sym_name) ?
3900+
ctx->loader->resolve_sym_name(ctx->loader, ir_get_str(ctx, val_insn->val.i32)) :
3901+
ir_resolve_sym_name(ir_get_str(ctx, val_insn->val.i32));
3902+
ir_emit_load_imm_int(ctx, IR_ADDR, dst_reg, (intptr_t)addr);
3903+
continue;
38543904
}
38553905
IR_ASSERT(val_insn->op == IR_ADDR || val_insn->op == IR_FUNC_ADDR);
38563906
} else if (ir_type_size[type] == 1) {
@@ -3875,7 +3925,11 @@ static int32_t ir_emit_arguments(ir_ctx *ctx, ir_ref def, ir_insn *insn, ir_reg
38753925
| adr Rx(tmp_reg), =>label
38763926
| str Rx(tmp_reg), [sp, #stack_offset]
38773927
} else if (val_insn->op == IR_FUNC || val_insn->op == IR_SYM) {
3878-
IR_ASSERT(0 && "sym");
3928+
void *addr = (ctx->loader && ctx->loader->resolve_sym_name) ?
3929+
ctx->loader->resolve_sym_name(ctx->loader, ir_get_str(ctx, val_insn->val.i32)) :
3930+
ir_resolve_sym_name(ir_get_str(ctx, val_insn->val.i32));
3931+
ir_emit_load_imm_int(ctx, IR_ADDR, tmp_reg, (intptr_t)addr);
3932+
| str Rx(tmp_reg), [sp, #stack_offset]
38793933
} else {
38803934
IR_ASSERT(tmp_reg != IR_REG_NONE);
38813935
ir_emit_load_imm_int(ctx, type, tmp_reg, val_insn->val.i64);

‎ext/opcache/jit/ir/ir_fold.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1282,7 +1282,7 @@ IR_FOLD(SUB(_,NEG))
12821282
{
12831283
/* a + (-b) => a - b */
12841284
opt ^= 1; /* ADD <-> SUB */
1285-
op2 = op2_insn->op2;
1285+
op2 = op2_insn->op1;
12861286
IR_FOLD_RESTART;
12871287
}
12881288

‎ext/opcache/jit/ir/ir_x86.dasc

+17-48
Original file line numberDiff line numberDiff line change
@@ -4088,17 +4088,17 @@ static void ir_emit_cmp_fp(ir_ctx *ctx, ir_ref def, ir_insn *insn)
40884088
| setb Rb(def_reg)
40894089
break;
40904090
case IR_UGE:
4091-
| setnp Rb(def_reg)
4092-
| mov Rd(tmp_reg), 0
4093-
| cmovb Rd(def_reg), Rd(tmp_reg)
4091+
| setp Rb(def_reg)
4092+
| mov Rd(tmp_reg), 1
4093+
| cmovae Rd(def_reg), Rd(tmp_reg)
40944094
break;
40954095
case IR_ULE:
40964096
| setbe Rb(def_reg)
40974097
break;
40984098
case IR_UGT:
4099-
| setnp Rb(def_reg)
4100-
| mov Rd(tmp_reg), 0
4101-
| cmovbe Rd(def_reg), Rd(tmp_reg)
4099+
| setp Rb(def_reg)
4100+
| mov Rd(tmp_reg), 1
4101+
| cmova Rd(def_reg), Rd(tmp_reg)
41024102
break;
41034103
}
41044104
if (IR_REG_SPILLED(ctx->regs[def][0])) {
@@ -4135,15 +4135,17 @@ static void ir_emit_jcc(ir_ctx *ctx, uint8_t op, uint32_t b, ir_ref def, ir_insn
41354135
uint32_t true_block, false_block, next_block;
41364136
ir_backend_data *data = ctx->data;
41374137
dasm_State **Dst = &data->dasm_state;
4138-
bool swap = 0;
41394138

41404139
ir_get_true_false_blocks(ctx, b, &true_block, &false_block, &next_block);
41414140
if (true_block == next_block) {
41424141
/* swap to avoid unconditional JMP */
4143-
op ^= 1; // reverse
4142+
if (int_cmp || op == IR_EQ || op == IR_NE) {
4143+
op ^= 1; // reverse
4144+
} else {
4145+
op ^= 5; // reverse
4146+
}
41444147
true_block = false_block;
41454148
false_block = 0;
4146-
swap = 1;
41474149
} else if (false_block == next_block) {
41484150
false_block = 0;
41494151
}
@@ -4202,9 +4204,7 @@ static void ir_emit_jcc(ir_ctx *ctx, uint8_t op, uint32_t b, ir_ref def, ir_insn
42024204
| jp =>true_block
42034205
break;
42044206
case IR_LT:
4205-
if (swap) {
4206-
| jb =>true_block
4207-
} else if (!false_block) {
4207+
if (!false_block) {
42084208
| jp >1
42094209
| jb =>true_block
42104210
|1:
@@ -4214,15 +4214,10 @@ static void ir_emit_jcc(ir_ctx *ctx, uint8_t op, uint32_t b, ir_ref def, ir_insn
42144214
}
42154215
break;
42164216
case IR_GE:
4217-
if (swap) {
4218-
| jp =>true_block
4219-
}
42204217
| jae =>true_block
42214218
break;
42224219
case IR_LE:
4223-
if (swap) {
4224-
| jbe =>true_block
4225-
} else if (!false_block) {
4220+
if (!false_block) {
42264221
| jp >1
42274222
| jbe =>true_block
42284223
|1:
@@ -4232,47 +4227,21 @@ static void ir_emit_jcc(ir_ctx *ctx, uint8_t op, uint32_t b, ir_ref def, ir_insn
42324227
}
42334228
break;
42344229
case IR_GT:
4235-
if (swap) {
4236-
| jp =>true_block
4237-
}
42384230
| ja =>true_block
42394231
break;
4240-
//
42414232
case IR_ULT:
4242-
if (swap) {
4243-
| jp =>true_block
4244-
}
42454233
| jb =>true_block
42464234
break;
42474235
case IR_UGE:
4248-
if (swap) {
4249-
| jae =>true_block
4250-
} else if (!false_block) {
4251-
| jp >1
4252-
| jae =>true_block
4253-
|1:
4254-
} else {
4255-
| jp =>false_block
4256-
| jae =>true_block
4257-
}
4236+
| jp =>true_block
4237+
| jae =>true_block
42584238
break;
42594239
case IR_ULE:
4260-
if (swap) {
4261-
| jp =>true_block
4262-
}
42634240
| jbe =>true_block
42644241
break;
42654242
case IR_UGT:
4266-
if (swap) {
4267-
| ja =>true_block
4268-
} else if (!false_block) {
4269-
| jp >1
4270-
| ja =>true_block
4271-
|1:
4272-
} else {
4273-
| jp =>false_block
4274-
| ja =>true_block
4275-
}
4243+
| jp =>true_block
4244+
| ja =>true_block
42764245
break;
42774246
}
42784247
}

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