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Rearranged MCU #ifdefs to support ATmega 4/8/16/328 and ATmega 16/32/…

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commit 0de9edc4668ec995a0221bb6aa45048203a58aef 1 parent a0ee435
Peter Kvitek kvitekp authored

Showing 5 changed files with 72 additions and 47 deletions. Show diff stats Hide diff stats

  1. +4 2 boot.h
  2. +47 34 gpio.h
  3. +7 3 serial.cc
  4. +8 2 serial.h
  5. +6 6 timer.h
6 boot.h
@@ -40,11 +40,13 @@ inline void Boot(bool init_timers) {
40 40 }
41 41
42 42 // Neuter the UARTs.
  43 +#ifdef HAS_USART0
43 44 UCSR0B = 0;
  45 +#endif
44 46
45   -#ifndef ATMEGA328P
  47 +#ifdef HAS_USART1
46 48 UCSR1B = 0;
47   -#endif // ATMEGA328P
  49 +#endif
48 50 }
49 51
50 52 } // avr
81 gpio.h
@@ -187,9 +187,46 @@ struct NumberedGpioInternal { };
187 187 template<bool safe> struct NumberedGpioInternal<n, safe> { \
188 188 typedef GpioImpl<port, timer, bit, safe> Impl; };
189 189
190   -#ifndef ATMEGA328P
  190 +// Pin definitions for ATmega lineup
  191 +
  192 +#if defined(ATMEGA48P) || defined(ATMEGA88P) || defined(ATMEGA168P) || defined(ATMEGA328P)
  193 +
  194 +SetupGpio(0, PortD, NoPwmChannel, 0);
  195 +SetupGpio(1, PortD, NoPwmChannel, 1);
  196 +SetupGpio(2, PortD, NoPwmChannel, 2);
  197 +SetupGpio(3, PortD, PwmChannel2B, 3);
  198 +SetupGpio(4, PortD, NoPwmChannel, 4);
  199 +SetupGpio(5, PortD, PwmChannel0B, 5);
  200 +SetupGpio(6, PortD, PwmChannel0A, 6);
  201 +SetupGpio(7, PortD, NoPwmChannel, 7);
  202 +SetupGpio(8, PortB, NoPwmChannel, 0);
  203 +SetupGpio(9, PortB, PwmChannel1A, 1);
  204 +SetupGpio(10, PortB, PwmChannel1B, 2);
  205 +SetupGpio(11, PortB, PwmChannel2A, 3);
  206 +SetupGpio(12, PortB, NoPwmChannel, 4);
  207 +SetupGpio(13, PortB, NoPwmChannel, 5);
  208 +SetupGpio(14, PortC, NoPwmChannel, 0);
  209 +SetupGpio(15, PortC, NoPwmChannel, 1);
  210 +SetupGpio(16, PortC, NoPwmChannel, 2);
  211 +SetupGpio(17, PortC, NoPwmChannel, 3);
  212 +SetupGpio(18, PortC, NoPwmChannel, 4);
  213 +SetupGpio(19, PortC, NoPwmChannel, 5);
  214 +
  215 +SetupGpio(255, PortB, NoPwmChannel, 0);
  216 +
  217 +typedef Gpio<PortB, 5> SpiSCK;
  218 +typedef Gpio<PortB, 4> SpiMISO;
  219 +typedef Gpio<PortB, 3> SpiMOSI;
  220 +typedef Gpio<PortB, 2> SpiSS;
  221 +
  222 +typedef Gpio<PortD, 4> UartSpiXCK;
  223 +typedef Gpio<PortD, 1> UartSpiTX;
  224 +typedef Gpio<PortD, 0> UartSpiRX;
  225 +
  226 +#define HAS_USART0
  227 +
  228 +#elif defined(ATMEGA164P) || defined(ATMEGA324P) || defined(ATMEGA644P) || defined(ATMEGA1284P)
191 229
192   -// Pin definitions for ATmega644p and ATmega1284p
193 230 SetupGpio(0, PortB, NoPwmChannel, 0);
194 231 SetupGpio(1, PortB, NoPwmChannel, 1);
195 232 SetupGpio(2, PortB, NoPwmChannel, 2);
@@ -228,42 +265,18 @@ typedef Gpio<PortB, 0> UartSpiXCK;
228 265 typedef Gpio<PortD, 1> UartSpiTX;
229 266 typedef Gpio<PortD, 0> UartSpiRX;
230 267
231   -#else
  268 +#define HAS_USART0
  269 +#define HAS_USART1
232 270
233   -// Pin definitions for ATmega168p and ATmega328p
234   -SetupGpio(0, PortD, NoPwmChannel, 0);
235   -SetupGpio(1, PortD, NoPwmChannel, 1);
236   -SetupGpio(2, PortD, NoPwmChannel, 2);
237   -SetupGpio(3, PortD, PwmChannel2B, 3);
238   -SetupGpio(4, PortD, NoPwmChannel, 4);
239   -SetupGpio(5, PortD, PwmChannel0B, 5);
240   -SetupGpio(6, PortD, PwmChannel0A, 6);
241   -SetupGpio(7, PortD, NoPwmChannel, 7);
242   -SetupGpio(8, PortB, NoPwmChannel, 0);
243   -SetupGpio(9, PortB, PwmChannel1A, 1);
244   -SetupGpio(10, PortB, PwmChannel1B, 2);
245   -SetupGpio(11, PortB, PwmChannel2A, 3);
246   -SetupGpio(12, PortB, NoPwmChannel, 4);
247   -SetupGpio(13, PortB, NoPwmChannel, 5);
248   -SetupGpio(14, PortC, NoPwmChannel, 0);
249   -SetupGpio(15, PortC, NoPwmChannel, 1);
250   -SetupGpio(16, PortC, NoPwmChannel, 2);
251   -SetupGpio(17, PortC, NoPwmChannel, 3);
252   -SetupGpio(18, PortC, NoPwmChannel, 4);
253   -SetupGpio(19, PortC, NoPwmChannel, 5);
254   -
255   -SetupGpio(255, PortB, NoPwmChannel, 0);
  271 +#ifdef ATMEGA1284P
  272 +#define HAS_TIMER3
  273 +#endif
256 274
257   -typedef Gpio<PortB, 5> SpiSCK;
258   -typedef Gpio<PortB, 4> SpiMISO;
259   -typedef Gpio<PortB, 3> SpiMOSI;
260   -typedef Gpio<PortB, 2> SpiSS;
  275 +#else
261 276
262   -typedef Gpio<PortD, 4> UartSpiXCK;
263   -typedef Gpio<PortD, 1> UartSpiTX;
264   -typedef Gpio<PortD, 0> UartSpiRX;
  277 +#error Unsupported MCU type
265 278
266   -#endif // ATMEGA328P
  279 +#endif
267 280
268 281 // Two specializations of the numbered pin template, one which clears the timer
269 282 // for each access to the PWM pins, as does the original Arduino wire lib,
10 serial.cc
@@ -27,28 +27,32 @@ using namespace avrlib;
27 27
28 28 #ifdef SERIAL_RX_0
29 29
30   -#ifndef ATMEGA328P
  30 +#if defined(HAS_USART0) && defined(HAS_USART1)
31 31
32 32 ISR(USART0_RX_vect) {
33 33 SerialInput<SerialPort0>::Received();
34 34 }
35 35
36   -#else
  36 +#elif defined(HAS_USART0)
37 37
38 38 ISR(USART_RX_vect) {
39 39 SerialInput<SerialPort0>::Received();
40 40 }
41 41
42   -#endif // ATMEGA328P
  42 +#endif // #ifdef HAS_USART
43 43
44 44 #endif // SERIAL_RX_0
45 45
46 46
47 47 #ifdef SERIAL_RX_1
48 48
  49 +#ifdef HAS_USART1
  50 +
49 51 ISR(USART1_RX_vect) {
50 52 SerialInput<SerialPort1>::Received();
51 53 }
52 54
  55 +#endif // #ifdef HAS_USART1
  56 +
53 57 #endif // SERIAL_RX_1
54 58
10 serial.h
@@ -241,6 +241,9 @@ struct Serial {
241 241 static inline Value ImmediateRead() { return Impl::IO::ImmediateRead(); }
242 242 };
243 243
  244 +
  245 +#ifdef HAS_USART0
  246 +
244 247 IORegister(UBRR0H);
245 248 IORegister(UBRR0L);
246 249 IORegister(UCSR0A);
@@ -260,7 +263,10 @@ typedef SerialPort<
260 263 kSerialOutputBufferSize,
261 264 kSerialInputBufferSize> SerialPort0;
262 265
263   -#ifndef ATMEGA328P
  266 +#endif // #ifdef HAS_USART0
  267 +
  268 +
  269 +#ifdef HAS_USART1
264 270
265 271 IORegister(UBRR1H);
266 272 IORegister(UBRR1L);
@@ -281,7 +287,7 @@ typedef SerialPort<
281 287 kSerialOutputBufferSize,
282 288 kSerialInputBufferSize> SerialPort1;
283 289
284   -#endif // ATMEGA328P
  290 +#endif // #ifdef HAS_USART1
285 291
286 292 } // namespace avrlib
287 293
12 timer.h
@@ -49,14 +49,14 @@ SpecialFunctionRegister(OCR1B);
49 49 SpecialFunctionRegister(OCR2A);
50 50 SpecialFunctionRegister(OCR2B);
51 51
52   -#ifdef ATMEGA1284P
  52 +#ifdef HAS_TIMER3
53 53 SpecialFunctionRegister(TCCR3A);
54 54 SpecialFunctionRegister(TCCR3B);
55 55 SpecialFunctionRegister(TIMSK3);
56 56 SpecialFunctionRegister(TCNT3);
57 57 SpecialFunctionRegister(OCR3A);
58 58 SpecialFunctionRegister(OCR3B);
59   -#endif // ATMEGA1284P
  59 +#endif // HAS_TIMER3
60 60
61 61 enum TimerMode {
62 62 TIMER_NORMAL = 0,
@@ -130,7 +130,7 @@ template<> struct NumberedTimer<2> {
130 130 TCNT2Register> Impl;
131 131 };
132 132
133   -#ifdef ATMEGA1284P
  133 +#ifdef HAS_TIMER3
134 134 template<> struct NumberedTimer<3> {
135 135 typedef TimerImpl<
136 136 TCCR3ARegister,
@@ -138,7 +138,7 @@ template<> struct NumberedTimer<3> {
138 138 TIMSK3Register,
139 139 TCNT3Register> Impl;
140 140 };
141   -#endif // ATMEGA1284P
  141 +#endif // HAS_TIMER3
142 142
143 143 template<int n>
144 144 struct Timer {
@@ -190,9 +190,9 @@ typedef PwmChannel<Timer<2>, COM2B1, OCR2BRegister> PwmChannel2B;
190 190 #define TIMER_1_TICK ISR(TIMER1_OVF_vect)
191 191 #define TIMER_2_TICK ISR(TIMER2_OVF_vect)
192 192
193   -#ifdef ATMEGA1284P
  193 +#ifdef HAS_TIMER3
194 194 #define TIMER_3_TICK ISR(TIMER3_OVF_vect)
195   -#endif // ATMEGA1284P
  195 +#endif // HAS_TIMER3
196 196
197 197 } // namespace avrlib
198 198

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