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BL602 SDK (Pine64 version)

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This repository contains the Pine64 fork of Bouffalo Lab's SDK for their BL602 Wi-Fi/BLE Combo RISC-V SoC. Documentation, including upstream documentation, translations, mirrored technical documentation, and original reverse engineered documentation is at bl602-docs, which is cloned as a submodule of this repository at docs. Use git submodule update --init to initialize the submodule.

This repository is the central focus of Pine64's Nutcracker Challenge. The main task is to reverse engineer the following files:

This is being done at bl602-re.


You can find a lot of documentation on PINE64 Documentation Website and PINE64 Documentation Repository, where you can find Datasheets, Reference Manuals and various other documentation materials.

Quick Start

In order to build sample apps, you need to set a few environment variables:

export BL60X_SDK_PATH=/path/to/this/repo

In order to build all sample apps simply call make, for example:


To only build the sample app of interest, go to the directory of the app, then call make, for example:

cd customer_app/bl602_boot2


make CONFIG_TOOLPREFIX=riscv64-linux-gnu-

if you wish to bypass the bundled cross-compiler and using your distribution's own cross-compiler.

There is a linker script (written in python) at image_conf/ To run this, you need to specify the application and the target, for example:

python3 bl602_boot2 bl602

Note: If you decide to copy any project outside of the customer_app folder, you will need to define a few variables in order to compile it:

export BL60X_SDK_PATH=/path/to/this/repo
export CONFIG_CHIP_NAME=bl602


To set up a development environment in Docker, and do a full build of all the example projects, using the bundled toolchain:

docker build -t bl602sdk -f Dockerfile.bundled
docker run -t -i --rm bl602sdk
# make


BL602 is a 32-bit RISC-V based combo chipset supporting Wi-Fi and BLE (Bluetooth Low Energy). The chip is made by Nanjing-based Bouffalo Lab for ultra-low-power applications. In terms of price range and feature set, the chip is competing against Espressif ESP8266. The RISC-V core is based on SiFive E24.

At the moment there are mainly three development boards:

Comparison with ESP8266

  Bouffalo Lab BL602 Espressif ESP8266

32-bit RISC-V (SiFive E24)

@192MHz (dynamic @1-192MHz)

L1 cache


32-bit Xtensa

@80MHz (and 160MHz)




1 Kb eFuse

optional embdedded flash

XIP QSPI flash support

32 KiB instruction RAM

32 KiB instruction cache RAM

80 KiB user-data RAM

16 KiB ETS system-data RAM

No programmable ROM

QSPI flash support (up to 16 MB)


802.11 b/g/n @2.4GHz


802.11 b/g/n @2.4GHz


Bluetooth LE 5.0 NONE
GPIO x16 x16
SDIO x1 2.0 slave x1 v2.0 slave
SPI x1 x2
UART x2 x1.5 (One Tx only)
I2C x1 x1 (software implemented)
I2S NONE x1 (with DMA)
PWM channels x5 x4
ADC 12-bit 10-bit (SAR)
DAC 10-bit NONE
Analog Comparator x2 NONE
DMA x4 with I2S

RTC (up to 1 year)

x2 32-bit general-purpose

x1 hardware

x1 software

(no interrupt gen. on sw. timer)

IR Remote Control x1 x1
Debug JTAG support ?


  • C++ 52.4%
  • C 30.1%
  • Roff 11.3%
  • HTML 4.7%
  • Python 0.8%
  • Makefile 0.2%
  • Other 0.5%